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From: Christoffer Dall <christoffer.dall@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com
Subject: Re: [PATCH v4 2/5] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 16 Mar 2015 12:15:59 +0100	[thread overview]
Message-ID: <20150316111559.GA26480@cbox> (raw)
In-Reply-To: <1426503716-13931-3-git-send-email-alex.bennee@linaro.org>

On Mon, Mar 16, 2015 at 11:01:53AM +0000, Alex Bennée wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
> 
> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
> index 1ad3eb0..2f21ae7 100644
> --- a/hw/intc/arm_gic_kvm.c
> +++ b/hw/intc/arm_gic_kvm.c
> @@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
>       * the appropriate CPU interfaces in the kernel) */
>      kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
>  
> +    /* irq_state[n].trigger -> GICD_ICFGRn
> +     * (restore targets before pending IRQs so we treat level/edge

targets? trigger? configurations?

> +     * correctly */
> +    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
> +
>      /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
>      kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
> @@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
>      kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
>  
> -    /* irq_state[n].trigger -> GICD_ICFRn */
> -    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
>  
>      /* s->priorityX[irq] -> ICD_IPRIORITYRn */
>      kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
> -- 
> 2.3.2
> 

WARNING: multiple messages have this Message-ID (diff)
From: Christoffer Dall <christoffer.dall@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com,
	qemu-devel@nongnu.org, kvm@vger.kernel.org,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [Qemu-devel] [PATCH v4 2/5] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 16 Mar 2015 12:15:59 +0100	[thread overview]
Message-ID: <20150316111559.GA26480@cbox> (raw)
In-Reply-To: <1426503716-13931-3-git-send-email-alex.bennee@linaro.org>

On Mon, Mar 16, 2015 at 11:01:53AM +0000, Alex Bennée wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
> 
> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
> index 1ad3eb0..2f21ae7 100644
> --- a/hw/intc/arm_gic_kvm.c
> +++ b/hw/intc/arm_gic_kvm.c
> @@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
>       * the appropriate CPU interfaces in the kernel) */
>      kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
>  
> +    /* irq_state[n].trigger -> GICD_ICFGRn
> +     * (restore targets before pending IRQs so we treat level/edge

targets? trigger? configurations?

> +     * correctly */
> +    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
> +
>      /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
>      kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
> @@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
>      kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
>  
> -    /* irq_state[n].trigger -> GICD_ICFRn */
> -    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
>  
>      /* s->priorityX[irq] -> ICD_IPRIORITYRn */
>      kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
> -- 
> 2.3.2
> 

WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/5] hw/intc: arm_gic_kvm.c restore config first
Date: Mon, 16 Mar 2015 12:15:59 +0100	[thread overview]
Message-ID: <20150316111559.GA26480@cbox> (raw)
In-Reply-To: <1426503716-13931-3-git-send-email-alex.bennee@linaro.org>

On Mon, Mar 16, 2015 at 11:01:53AM +0000, Alex Benn?e wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
> 
> Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
> 
> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
> index 1ad3eb0..2f21ae7 100644
> --- a/hw/intc/arm_gic_kvm.c
> +++ b/hw/intc/arm_gic_kvm.c
> @@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
>       * the appropriate CPU interfaces in the kernel) */
>      kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
>  
> +    /* irq_state[n].trigger -> GICD_ICFGRn
> +     * (restore targets before pending IRQs so we treat level/edge

targets? trigger? configurations?

> +     * correctly */
> +    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
> +
>      /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
>      kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
> @@ -378,8 +383,6 @@ static void kvm_arm_gic_put(GICState *s)
>      kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
>      kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
>  
> -    /* irq_state[n].trigger -> GICD_ICFRn */
> -    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
>  
>      /* s->priorityX[irq] -> ICD_IPRIORITYRn */
>      kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
> -- 
> 2.3.2
> 

  reply	other threads:[~2015-03-16 11:15 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-16 11:01 [PATCH v4 0/5] QEMU ARM64 Migration Fixes Alex Bennée
2015-03-16 11:01 ` Alex Bennée
2015-03-16 11:01 ` [Qemu-devel] " Alex Bennée
2015-03-16 11:01 ` [PATCH v4 1/5] target-arm: kvm: save/restore mp state Alex Bennée
2015-03-16 11:01   ` Alex Bennée
2015-03-16 11:01   ` [Qemu-devel] " Alex Bennée
2015-03-17 15:17   ` Peter Maydell
2015-03-17 15:17     ` Peter Maydell
2015-03-17 15:17     ` [Qemu-devel] " Peter Maydell
2015-03-16 11:01 ` [PATCH v4 2/5] hw/intc: arm_gic_kvm.c restore config first Alex Bennée
2015-03-16 11:01   ` Alex Bennée
2015-03-16 11:01   ` [Qemu-devel] " Alex Bennée
2015-03-16 11:15   ` Christoffer Dall [this message]
2015-03-16 11:15     ` Christoffer Dall
2015-03-16 11:15     ` [Qemu-devel] " Christoffer Dall
2015-03-16 11:01 ` [PATCH v4 3/5] target-arm: kvm64 sync FP register state Alex Bennée
2015-03-16 11:01   ` Alex Bennée
2015-03-16 11:01   ` [Qemu-devel] " Alex Bennée
2015-03-17 15:29   ` Peter Maydell
2015-03-17 15:29     ` Peter Maydell
2015-03-17 15:29     ` [Qemu-devel] " Peter Maydell
2015-03-16 11:01 ` [PATCH v4 4/5] target-arm: kvm64 fix save/restore of SPSR regs Alex Bennée
2015-03-16 11:01   ` Alex Bennée
2015-03-16 11:01   ` [Qemu-devel] " Alex Bennée
2015-03-16 12:52   ` Christoffer Dall
2015-03-16 12:52     ` Christoffer Dall
2015-03-16 12:52     ` [Qemu-devel] " Christoffer Dall
2015-03-17 16:18   ` Peter Maydell
2015-03-17 16:18     ` Peter Maydell
2015-03-17 16:18     ` [Qemu-devel] " Peter Maydell
2015-03-17 19:04     ` Christoffer Dall
2015-03-17 19:04       ` Christoffer Dall
2015-03-17 19:04       ` [Qemu-devel] " Christoffer Dall
2015-03-17 19:08       ` Peter Maydell
2015-03-17 19:08         ` Peter Maydell
2015-03-17 19:08         ` [Qemu-devel] " Peter Maydell
2015-03-16 11:01 ` [PATCH v4 5/5] target-arm: cpu.h document why env->spsr exists Alex Bennée
2015-03-16 11:01   ` Alex Bennée
2015-03-16 11:01   ` [Qemu-devel] " Alex Bennée
2015-03-17 15:50   ` Peter Maydell
2015-03-17 15:50     ` Peter Maydell
2015-03-17 15:50     ` [Qemu-devel] " Peter Maydell

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