* [U-Boot] [PATCH 1/7] powerpc: mpc5xxx: remove BC3450 board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 2/7] powerpc: ppc4xx: remove JSE " Masahiro Yamada
` (6 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 4 -
board/bc3450/Kconfig | 9 -
board/bc3450/MAINTAINERS | 6 -
board/bc3450/Makefile | 8 -
board/bc3450/bc3450.c | 586 ----------------------------
board/bc3450/cmd_bc3450.c | 805 ---------------------------------------
board/bc3450/mt48lc16m16a2-75.h | 18 -
configs/BC3450_defconfig | 3 -
doc/README.scrapyard | 15 +-
include/configs/BC3450.h | 541 --------------------------
10 files changed, 8 insertions(+), 1987 deletions(-)
delete mode 100644 board/bc3450/Kconfig
delete mode 100644 board/bc3450/MAINTAINERS
delete mode 100644 board/bc3450/Makefile
delete mode 100644 board/bc3450/bc3450.c
delete mode 100644 board/bc3450/cmd_bc3450.c
delete mode 100644 board/bc3450/mt48lc16m16a2-75.h
delete mode 100644 configs/BC3450_defconfig
delete mode 100644 include/configs/BC3450.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 9da00da..1b81fb5 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -14,9 +14,6 @@ config TARGET_A3M071
config TARGET_A4M072
bool "Support a4m072"
-config TARGET_BC3450
- bool "Support BC3450"
-
config TARGET_CANMB
bool "Support canmb"
@@ -84,7 +81,6 @@ endchoice
source "board/a3m071/Kconfig"
source "board/a4m072/Kconfig"
-source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
source "board/galaxy5200/Kconfig"
diff --git a/board/bc3450/Kconfig b/board/bc3450/Kconfig
deleted file mode 100644
index a0fc19f..0000000
--- a/board/bc3450/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BC3450
-
-config SYS_BOARD
- default "bc3450"
-
-config SYS_CONFIG_NAME
- default "BC3450"
-
-endif
diff --git a/board/bc3450/MAINTAINERS b/board/bc3450/MAINTAINERS
deleted file mode 100644
index 81a7076..0000000
--- a/board/bc3450/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BC3450 BOARD
-#M: -
-S: Maintained
-F: board/bc3450/
-F: include/configs/BC3450.h
-F: configs/BC3450_defconfig
diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile
deleted file mode 100644
index b8d22ba..0000000
--- a/board/bc3450/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bc3450.o cmd_bc3450.o
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
deleted file mode 100644
index a5c6d75..0000000
--- a/board/bc3450/bc3450.c
+++ /dev/null
@@ -1,586 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * (C) Copyright 2006
- * Stefan Strobl, GERSYS GmbH, stefan.strobl at gersys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-#endif
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-#ifdef CONFIG_RTC_MPC5200
-#include <rtc.h>
-#endif
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
- hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
-
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-int checkboard (void)
-{
-#if defined (CONFIG_TQM5200)
- puts ("Board: TQM5200 (TQ-Components GmbH)\n");
-#endif
-
-#if defined (CONFIG_BC3450)
- puts ("Dev: GERSYS BC3450\n");
-#endif
-
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#ifdef CONFIG_POST
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
- struct mpc5xxx_gpio *gpio;
-
- gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
-
- /*
- * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
- * CODEC or UART mode. Consumer IrDA should still be possible.
- */
- gpio->port_config &= ~(0x07000000);
- gpio->port_config |= 0x03000000;
-
- /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
- gpio->simple_gpioe |= 0x20000000;
-
- /* Configure GPIO_IRDA_1 as input */
- gpio->simple_ddr &= ~(0x20000000);
-
- return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-#ifdef CONFIG_RTC_MPC5200
- struct rtc_time t;
-
- /* set to Wed Dec 31 19:00:00 1969 */
- t.tm_sec = t.tm_min = 0;
- t.tm_hour = 19;
- t.tm_mday = 31;
- t.tm_mon = 12;
- t.tm_year = 1969;
- t.tm_wday = 3;
-
- rtc_set(&t);
-#endif /* CONFIG_RTC_MPC5200 */
-
-#ifdef CONFIG_PS2MULT
- ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
- return (0);
-}
-#endif /* CONFIG_BOARD_EARLY_INIT_R */
-
-
-int last_stage_init (void)
-{
- /*
- * auto scan for really existing devices and re-set chip select
- * configuration.
- */
- u16 save, tmp;
- int restore;
-
- /*
- * Check for SRAM and SRAM size
- */
-
- /* save original SRAM content */
- save = *(volatile u16 *)CONFIG_SYS_CS2_START;
- restore = 1;
-
- /* write test pattern to SRAM */
- *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in SRAM detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
- /* no SRAM at all, disable cs */
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
- *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
- *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
- restore = 0;
- __asm__ volatile ("sync");
- } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
- /* make sure that we access a mirrored address */
- *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
- __asm__ volatile ("sync");
- if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
- /* SRAM size = 512 kByte */
- *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
- 0x80000);
- __asm__ volatile ("sync");
- puts ("SRAM: 512 kB\n");
- }
- else
- puts ("!! possible error in SRAM detection\n");
- } else {
- puts ("SRAM: 1 MB\n");
- }
- /* restore origianl SRAM content */
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS2_START = save;
- __asm__ volatile ("sync");
- }
-
- /*
- * Check for Grafic Controller
- */
-
- /* save origianl FB content */
- save = *(volatile u16 *)CONFIG_SYS_CS1_START;
- restore = 1;
-
- /* write test pattern to FB memory */
- *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in grafic controller detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
- /* no grafic controller at all, disable cs */
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
- *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
- *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
- restore = 0;
- __asm__ volatile ("sync");
- } else {
- puts ("VGA: SMI501 (Voyager) with 8 MB\n");
- }
- /* restore origianl FB content */
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS1_START = save;
- __asm__ volatile ("sync");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_VIDEO_SM501
-
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#error CONFIG_VIDEO_SM501_16BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-
-#ifdef CONFIG_VIDEO_SM501_32BPP
-static const SMI_REGS init_regs [] =
-{
-#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
- /* FP only */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x091a0a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x091a0a01},
- {0x00054, 0x0},
- {0x80000, 0x01013106},
- {0x80004, 0xc428bb17},
- {0x80000, 0x03013106},
- {0x8000C, 0x00000000},
- {0x80010, 0x0a000a00},
- {0x80014, 0x02800000},
- {0x80018, 0x01e00000},
- {0x8001C, 0x00000000},
- {0x80020, 0x01e00280},
- {0x80024, 0x02fa027f},
- {0x80028, 0x004a028b},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e9},
- {0x80200, 0x00010200},
- {0x80000, 0x0f013106},
-#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
- /* CRT only */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x10090a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x10090a01},
- {0x00054, 0x0},
- {0x80200, 0x00010000},
- {0x80204, 0x0},
- {0x80208, 0x0A000A00},
- {0x8020C, 0x02fa027f},
- {0x80210, 0x004a028b},
- {0x80214, 0x020c01df},
- {0x80218, 0x000201e9},
- {0x80200, 0x00013306},
-#else /* panel + CRT */
- {0x00004, 0x0},
- {0x00048, 0x00021807},
- {0x0004C, 0x091a0a01},
- {0x00054, 0x1},
- {0x00040, 0x00021807},
- {0x00044, 0x091a0a01},
- {0x00054, 0x0},
- {0x80000, 0x0f013106},
- {0x80004, 0xc428bb17},
- {0x8000C, 0x00000000},
- {0x80010, 0x0a000a00},
- {0x80014, 0x02800000},
- {0x80018, 0x01e00000},
- {0x8001C, 0x00000000},
- {0x80020, 0x01e00280},
- {0x80024, 0x02fa027f},
- {0x80028, 0x004a028b},
- {0x8002C, 0x020c01df},
- {0x80030, 0x000201e9},
- {0x80200, 0x00010000},
-#endif
- {0, 0}
-};
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
- if (line_number == 1) {
-#if defined (CONFIG_TQM5200)
- strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#else
-#error No supported board selected
-#endif /* CONFIG_TQM5200 */
-
-#if defined (CONFIG_BC3450)
- } else if (line_number == 2) {
- strcpy (info, " Dev: GERSYS BC3450");
-#endif /* CONFIG_BC3450 */
- }
- else {
- info [0] = '\0';
- }
-}
-#endif
-
-/*
- * Returns SM501 register base address. First thing called in the
- * driver. Checks if SM501 is physically present.
- */
-unsigned int board_video_init (void)
-{
- u16 save, tmp;
- int restore, ret;
-
- /*
- * Check for Grafic Controller
- */
-
- /* save origianl FB content */
- save = *(volatile u16 *)CONFIG_SYS_CS1_START;
- restore = 1;
-
- /* write test pattern to FB memory */
- *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
- __asm__ volatile ("sync");
- /*
- * Put a different pattern on the data lines: otherwise they may float
- * long enough to read back what we wrote.
- */
- tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
- if (tmp == 0xA5A5)
- puts ("!! possible error in grafic controller detection\n");
-
- if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
- /* no grafic controller found */
- restore = 0;
- ret = 0;
- } else {
- ret = SM501_MMIO_BASE;
- }
-
- if (restore) {
- *(volatile u16 *)CONFIG_SYS_CS1_START = save;
- __asm__ volatile ("sync");
- }
- return ret;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
- return SM501_FB_BASE;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
- return init_regs;
-}
-
-int board_get_width (void)
-{
- return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
- return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
deleted file mode 100644
index 3c6e798..0000000
--- a/board/bc3450/cmd_bc3450.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Strobl, GERSYS GmbH, stefan.strobl at gersys.de
- *
- * (C) Copyright 2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-/*
- * BC3450 specific commands
- */
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Definitions for DS1620 chip
- */
-#define THERM_START_CONVERT 0xee
-#define THERM_RESET 0xaf
-#define THERM_READ_CONFIG 0xac
-#define THERM_READ_TEMP 0xaa
-#define THERM_READ_TL 0xa2
-#define THERM_READ_TH 0xa1
-#define THERM_WRITE_CONFIG 0x0c
-#define THERM_WRITE_TL 0x02
-#define THERM_WRITE_TH 0x01
-
-#define CONFIG_SYS_1SHOT 1
-#define CONFIG_SYS_STANDALONE 0
-
-struct therm {
- int hi;
- int lo;
-};
-
-/*
- * SM501 Register
- */
-#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */
-#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */
-#define SM501_POWER_MODE0_GATE 0x00000040UL
-#define SM501_POWER_MODE1_GATE 0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
-#define SM501_GPIO_DATA_LOW 0x00010000UL
-#define SM501_GPIO_DATA_HIGH 0x00010004UL
-#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
-#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
-#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
-#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL
-
-/* SM501 CRT Display Control Bits */
-#define SM501_CDC_SEL (1 << 9)
-#define SM501_CDC_TE (1 << 8)
-#define SM501_CDC_E (1 << 2)
-
-/* SM501 Panel Display Control Bits */
-#define SM501_PDC_FPEN (1 << 27)
-#define SM501_PDC_BIAS (1 << 26)
-#define SM501_PDC_DATA (1 << 25)
-#define SM501_PDC_VDDEN (1 << 24)
-
-/* SM501 GPIO Data LOW Bits */
-#define SM501_GPIO24 0x01000000
-#define SM501_GPIO25 0x02000000
-#define SM501_GPIO26 0x04000000
-#define SM501_GPIO27 0x08000000
-#define SM501_GPIO28 0x10000000
-#define SM501_GPIO29 0x20000000
-#define SM501_GPIO30 0x40000000
-#define SM501_GPIO31 0x80000000
-
-/* SM501 GPIO Data HIGH Bits */
-#define SM501_GPIO46 0x00004000
-#define SM501_GPIO47 0x00008000
-#define SM501_GPIO48 0x00010000
-#define SM501_GPIO49 0x00020000
-#define SM501_GPIO50 0x00040000
-#define SM501_GPIO51 0x00080000
-
-/* BC3450 GPIOs @ SM501 Data LOW */
-#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
-#define DS1620_DQ SM501_GPIO29 /* I/O */
-#define DS1620_CLK SM501_GPIO30 /* High active O/P */
-#define DS1620_RES SM501_GPIO31 /* Low active O/P */
-/* BC3450 GPIOs @ SM501 Data HIGH */
-#define BUZZER SM501_GPIO47 /* Low active O/P */
-#define DS1620_TLOW SM501_GPIO48 /* High active I/P */
-#define PWR_OFF SM501_GPIO49 /* Low active O/P */
-#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */
-
-
-/*
- * Initialise GPIO on SM501
- *
- * This function may be called from several other functions.
- * Yet, the initialisation sequence is executed only the first
- * time the function is called.
- */
-int sm501_gpio_init (void)
-{
- static int init_done = 0;
-
- if (init_done) {
- debug("sm501_gpio_init: nothing to be done.\n");
- return 1;
- }
-
- /* enable SM501 GPIO control (in both power modes) */
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
- POWER_MODE_GATE_GPIO_PWM_I2C;
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
- POWER_MODE_GATE_GPIO_PWM_I2C;
-
- /* set up default O/Ps */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~(DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~(FP_DATA_TRI);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
- (BUZZER | PWR_OFF);
-
- /* configure directions for SM501 GPIO pins */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
- ~(0x3F << 14);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
- ~(DIP | DS1620_DQ);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
- (DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
- ~DS1620_TLOW;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
- (PWR_OFF | BUZZER | FP_DATA_TRI);
-
- init_done = 1;
- debug("sm501_gpio_init: done.\n");
-
- return 0;
-}
-
-
-/*
- * dip - read Config Inputs
- *
- * read and prints the dip switch
- * and/or external config inputs (4bits) 0...0x0F
- */
-int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- vu_long rc = 0;
-
- sm501_gpio_init ();
-
- /* read dip switch */
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc = ~rc;
- rc &= DIP;
- rc = (int) (rc >> 24);
-
- /* plausibility check */
- if (rc > 0x0F)
- return -1;
-
- printf ("0x%lx\n", rc);
- return 0;
-}
-
-U_BOOT_CMD (dip, 1, 1, cmd_dip,
- "read dip switch and config inputs",
- "\n"
- " - prints the state of the dip switch and/or\n"
- " external configuration inputs as hex value.\n"
- " - \"Config 1\" is the LSB");
-
-
-/*
- * buz - turns Buzzer on/off
- */
-#ifdef CONFIG_BC3450_BUZZER
-static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 2) {
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
- }
-
- sm501_gpio_init ();
-
- if (strncmp (argv[1], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~(BUZZER);
- return 0;
- } else if (strncmp (argv[1], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
- BUZZER;
- return 0;
- }
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
-}
-
-U_BOOT_CMD (buz, 2, 1, cmd_buz,
- "turns buzzer on/off",
- "\n" "buz <on/off>\n" " - turns the buzzer on or off");
-#endif /* CONFIG_BC3450_BUZZER */
-
-
-/*
- * fp - front panel commands
- */
-static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- sm501_gpio_init ();
-
- if (strncmp (argv[1], "on", 2) == 0) {
- /* turn on VDD first */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
- udelay (1000);
- /* then put data on */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
- /* wait some time and enable backlight */
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
- return 0;
- } else if (strncmp (argv[1], "off", 3) == 0) {
- /* turn off the backlight first */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
- udelay (200000);
- /* wait some time, then remove data */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
- udelay (1000);
- /* and remove VDD last */
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_VDDEN;
- return 0;
- } else if (strncmp (argv[1], "bl", 2) == 0) {
- /* turn on/off backlight only */
- if (strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |=
- SM501_PDC_BIAS;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) |=
- SM501_PDC_FPEN;
- return 0;
- } else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_FPEN;
- udelay (1000);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_PANEL_DISPLAY_CONTROL) &=
- ~SM501_PDC_BIAS;
- return 0;
- }
- }
-#ifdef CONFIG_BC3450_CRT
- else if (strncmp (argv[1], "crt", 3) == 0) {
- /* enables/disables the crt output (debug only) */
- if (strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) |=
- (SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) &=
- ~SM501_CDC_SEL;
- return 0;
- } else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) &=
- ~(SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *) (SM501_MMIO_BASE +
- SM501_CRT_DISPLAY_CONTROL) |=
- SM501_CDC_SEL;
- return 0;
- }
- }
-#endif /* CONFIG_BC3450_CRT */
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (fp, 3, 1, cmd_fp,
- "front panes access functions",
- "\n"
- "fp bl <on/off>\n"
- " - turns the CCFL backlight of the display on/off\n"
- "fp <on/off>\n" " - turns the whole display on/off"
-#ifdef CONFIG_BC3450_CRT
- "\n"
- "fp crt <on/off>\n"
- " - enables/disables the crt output (debug only)"
-#endif /* CONFIG_BC3450_CRT */
- );
-
-/*
- * temp - DS1620 thermometer
- */
-/* GERSYS BC3450 specific functions */
-static inline void bc_ds1620_set_clk (int clk)
-{
- if (clk)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
- DS1620_CLK;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~DS1620_CLK;
-}
-
-static inline void bc_ds1620_set_data (int dat)
-{
- if (dat)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
- DS1620_DQ;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
- ~DS1620_DQ;
-}
-
-static inline int bc_ds1620_get_data (void)
-{
- vu_long rc;
-
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc &= DS1620_DQ;
- if (rc != 0)
- rc = 1;
- return (int) rc;
-}
-
-static inline void bc_ds1620_set_data_dir (int dir)
-{
- if (dir) /* in */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
- else /* out */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
-}
-
-static inline void bc_ds1620_set_reset (int res)
-{
- if (res)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
-}
-
-/* hardware independent functions */
-static void ds1620_send_bits (int nr, int value)
-{
- int i;
-
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_data (value & 1);
- bc_ds1620_set_clk (0);
- udelay (1);
- bc_ds1620_set_clk (1);
- udelay (1);
-
- value >>= 1;
- }
-}
-
-static unsigned int ds1620_recv_bits (int nr)
-{
- unsigned int value = 0, mask = 1;
- int i;
-
- bc_ds1620_set_data (0);
-
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_clk (0);
- udelay (1);
-
- if (bc_ds1620_get_data ())
- value |= mask;
-
- mask <<= 1;
-
- bc_ds1620_set_clk (1);
- udelay (1);
- }
-
- return value;
-}
-
-static void ds1620_out (int cmd, int bits, int value)
-{
- bc_ds1620_set_clk (1);
- bc_ds1620_set_data_dir (0);
-
- bc_ds1620_set_reset (0);
- udelay (1);
- bc_ds1620_set_reset (1);
-
- udelay (1);
-
- ds1620_send_bits (8, cmd);
- if (bits)
- ds1620_send_bits (bits, value);
-
- udelay (1);
-
- /* go stand alone */
- bc_ds1620_set_data_dir (1);
- bc_ds1620_set_reset (0);
- bc_ds1620_set_clk (0);
-
- udelay (10000);
-}
-
-static unsigned int ds1620_in (int cmd, int bits)
-{
- unsigned int value;
-
- bc_ds1620_set_clk (1);
- bc_ds1620_set_data_dir (0);
-
- bc_ds1620_set_reset (0);
- udelay (1);
- bc_ds1620_set_reset (1);
-
- udelay (1);
-
- ds1620_send_bits (8, cmd);
-
- bc_ds1620_set_data_dir (1);
- value = ds1620_recv_bits (bits);
-
- /* go stand alone */
- bc_ds1620_set_data_dir (1);
- bc_ds1620_set_reset (0);
- bc_ds1620_set_clk (0);
-
- return value;
-}
-
-static int cvt_9_to_int (unsigned int val)
-{
- if (val & 0x100)
- val |= 0xfffffe00;
-
- return val;
-}
-
-/* set thermostate thresholds */
-static void ds1620_write_state (struct therm *therm)
-{
- ds1620_out (THERM_WRITE_TL, 9, therm->lo);
- ds1620_out (THERM_WRITE_TH, 9, therm->hi);
- ds1620_out (THERM_START_CONVERT, 0, 0);
-}
-
-static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- struct therm therm;
-
- sm501_gpio_init ();
-
- /* print temperature */
- if (argc == 1) {
- i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
- printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
- return 0;
- }
-
- /* set to default operation */
- if (strncmp (argv[1], "set", 3) == 0) {
- if (strncmp (argv[2], "default", 3) == 0) {
- therm.hi = +88;
- therm.lo = -20;
- therm.hi <<= 1;
- therm.lo <<= 1;
- ds1620_write_state (&therm);
- ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
- return 0;
- }
- }
-
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (temp, 3, 1, cmd_temp,
- "print current temperature",
- "\n" "temp\n" " - print current temperature");
-
-#ifdef CONFIG_BC3450_CAN
-/*
- * Initialise CAN interface
- *
- * return 1 on CAN initialization failure
- * return 0 if no failure
- */
-int can_init (void)
-{
- static int init_done = 0;
- int i;
- struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
- struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
-
- /* GPIO configuration of the CAN pins is done in BC3450.h */
-
- if (!init_done) {
- /* init CAN 1 */
- can1->canctl1 |= 0x80; /* CAN enable */
- udelay (100);
-
- i = 0;
- can1->canctl0 |= 0x02; /* sleep mode */
- /* wait until sleep mode reached */
- while (!(can1->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not enter sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- i = 0;
- can1->canctl0 = 0x01; /* enter init mode */
- /* wait until init mode reached */
- while (!(can1->canctl1 & 0x01)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not enter init mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- can1->canctl1 = 0x80;
- can1->canctl1 |= 0x40;
- can1->canbtr0 = 0x0F;
- can1->canbtr1 = 0x7F;
- can1->canidac &= ~(0x30);
- can1->canidar1 = 0x00;
- can1->canidar3 = 0x00;
- can1->canidar5 = 0x00;
- can1->canidar7 = 0x00;
- can1->canidmr0 = 0xFF;
- can1->canidmr1 = 0xFF;
- can1->canidmr2 = 0xFF;
- can1->canidmr3 = 0xFF;
- can1->canidmr4 = 0xFF;
- can1->canidmr5 = 0xFF;
- can1->canidmr6 = 0xFF;
- can1->canidmr7 = 0xFF;
-
- i = 0;
- can1->canctl0 &= ~(0x01); /* leave init mode */
- can1->canctl0 &= ~(0x02);
- /* wait until init and sleep mode left */
- while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not leave init/sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
-
- /* init CAN 2 */
- can2->canctl1 |= 0x80; /* CAN enable */
- udelay (100);
-
- i = 0;
- can2->canctl0 |= 0x02; /* sleep mode */
- /* wait until sleep mode reached */
- while (!(can2->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not enter sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- i = 0;
- can2->canctl0 = 0x01; /* enter init mode */
- /* wait until init mode reached */
- while (!(can2->canctl1 & 0x01)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not enter init mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- can2->canctl1 = 0x80;
- can2->canctl1 |= 0x40;
- can2->canbtr0 = 0x0F;
- can2->canbtr1 = 0x7F;
- can2->canidac &= ~(0x30);
- can2->canidar1 = 0x00;
- can2->canidar3 = 0x00;
- can2->canidar5 = 0x00;
- can2->canidar7 = 0x00;
- can2->canidmr0 = 0xFF;
- can2->canidmr1 = 0xFF;
- can2->canidmr2 = 0xFF;
- can2->canidmr3 = 0xFF;
- can2->canidmr4 = 0xFF;
- can2->canidmr5 = 0xFF;
- can2->canidmr6 = 0xFF;
- can2->canidmr7 = 0xFF;
- can2->canctl0 &= ~(0x01); /* leave init mode */
- can2->canctl0 &= ~(0x02);
-
- i = 0;
- /* wait until init mode left */
- while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
- udelay (10);
- i++;
- if (i == 10) {
- printf ("%s: CAN2 initialize error, "
- "can not leave init/sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
- }
- init_done = 1;
- }
- return 0;
-}
-
-/*
- * Do CAN test
- * by sending message between CAN1 and CAN2
- *
- * return 1 on CAN failure
- * return 0 if no failure
- */
-int do_can (char * const argv[])
-{
- int i;
- struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
- struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
-
- /* send a message on CAN1 */
- can1->cantbsel = 0x01;
- can1->cantxfg.idr[0] = 0x55;
- can1->cantxfg.idr[1] = 0x00;
- can1->cantxfg.idr[1] &= ~0x8;
- can1->cantxfg.idr[1] &= ~0x10;
- can1->cantxfg.dsr[0] = 0xCC;
- can1->cantxfg.dlr = 1;
- can1->cantxfg.tbpr = 0;
- can1->cantflg = 0x01;
-
- i = 0;
- while ((can1->cantflg & 0x01) == 0) {
- i++;
- if (i == 10) {
- printf ("%s: CAN1 send timeout, "
- "can not send message!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
- udelay (1000);
-
- i = 0;
- while (!(can2->canrflg & 0x01)) {
- i++;
- if (i == 10) {
- printf ("%s: CAN2 receive timeout, "
- "no message received!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
-
- if (can2->canrxfg.dsr[0] != 0xCC) {
- printf ("%s: CAN2 receive error, "
- "data mismatch!\n", __FUNCTION__);
- return 1;
- }
-
- /* send a message on CAN2 */
- can2->cantbsel = 0x01;
- can2->cantxfg.idr[0] = 0x55;
- can2->cantxfg.idr[1] = 0x00;
- can2->cantxfg.idr[1] &= ~0x8;
- can2->cantxfg.idr[1] &= ~0x10;
- can2->cantxfg.dsr[0] = 0xCC;
- can2->cantxfg.dlr = 1;
- can2->cantxfg.tbpr = 0;
- can2->cantflg = 0x01;
-
- i = 0;
- while ((can2->cantflg & 0x01) == 0) {
- i++;
- if (i == 10) {
- printf ("%s: CAN2 send error, "
- "can not send message!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
- udelay (1000);
-
- i = 0;
- while (!(can1->canrflg & 0x01)) {
- i++;
- if (i == 10) {
- printf ("%s: CAN1 receive timeout, "
- "no message received!\n", __FUNCTION__);
- return 1;
- }
- udelay (1000);
- }
-
- if (can1->canrxfg.dsr[0] != 0xCC) {
- printf ("%s: CAN1 receive error 0x%02x\n",
- __FUNCTION__, (can1->canrxfg.dsr[0]));
- return 1;
- }
-
- return 0;
-}
-#endif /* CONFIG_BC3450_CAN */
-
-/*
- * test - BC3450 HW test routines
- */
-int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-#ifdef CONFIG_BC3450_CAN
- int rcode;
-
- can_init ();
-#endif /* CONFIG_BC3450_CAN */
-
- sm501_gpio_init ();
-
- if (argc != 2) {
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
- }
-
- if (strncmp (argv[1], "unit-off", 8) == 0) {
- printf ("waiting 2 seconds...\n");
- udelay (2000000);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
- ~PWR_OFF;
- return 0;
- }
-#ifdef CONFIG_BC3450_CAN
- else if (strncmp (argv[1], "can", 2) == 0) {
- rcode = do_can (argv);
- if (simple_strtoul (argv[2], NULL, 10) == 2) {
- if (rcode == 0)
- printf ("OK\n");
- else
- printf ("Error\n");
- }
- return rcode;
- }
-#endif /* CONFIG_BC3450_CAN */
-
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
-}
-
-U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
-#ifdef CONFIG_BC3450_CAN
- "test can\n"
- " - connect CAN1 (X8) with CAN2 (X9) for this test\n"
-#endif /* CONFIG_BC3450_CAN */
- "test unit-off\n"
- " - turns off the BC3450 unit\n"
- " WARNING: Unsaved environment variables will be lost!"
-);
-#endif
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
deleted file mode 100644
index 3d99796..0000000
--- a/board/bc3450/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
-#define SDRAM_CONFIG2 0x8AD70000
-/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/configs/BC3450_defconfig b/configs/BC3450_defconfig
deleted file mode 100644
index ecb46e9..0000000
--- a/configs/BC3450_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_BC3450=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index cd8f4ae..481f4d8 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,13 +12,14 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-hawkboard arm arm926ejs - - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
-a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
-cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
-cm41xx arm arm920t - -
-dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
-jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
+BC3450 powerpc mpc5xxx - -
+hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
+a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang <ratbert@faraday-tech.com>
+cm4008 arm arm920t a2f39e83 2015-02-24 Greg Ungerer <greg.ungerer@opengear.com>
+cm41xx arm arm920t a2f39e83 2015-02-24
+dkb arm arm926ejs 346cfba4 2015-02-24 Lei Wen <leiwen@marvell.com>
+jadecpu arm arm926ejs 41fbbbbc 2015-02-24 Matthias Weisser <weisserm@arcor.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
deleted file mode 100644
index 802e9cc..0000000
--- a/include/configs/BC3450.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/*
- * -- Version 1.1 --
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * (C) Copyright 2005
- * Stefan Strobl, GERSYS GmbH, stefan.strobl at gersys.de.
- *
- * History:
- * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
-
-#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
-#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
-#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
-#define CONFIG_BC3450_USB 1 /* + USB support */
-# define CONFIG_FAT 1 /* + FAT support */
-# define CONFIG_EXT2 1 /* + EXT2 support */
-#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
-#undef CONFIG_BC3450_CAN /* + CAN transceiver */
-#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
-#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
-#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
-#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
-#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * AT-PS/2 Multiplexer
- */
-#ifdef CONFIG_BC3450_PS2
-# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
-# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-# define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_BC3450_PS2 */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-# define CONFIG_PCI 1
-# define CONFIG_PCI_PNP 1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/*
- * Video console
- */
-# define CONFIG_VIDEO
-# define CONFIG_VIDEO_SM501
-# define CONFIG_VIDEO_SM501_32BPP
-# define CONFIG_CFB_CONSOLE
-# define CONFIG_VIDEO_LOGO
-# define CONFIG_VGA_AS_SINGLE_DEVICE
-# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
-# define CONFIG_VIDEO_SW_CURSOR
-# define CONFIG_SPLASH_SCREEN
-# define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Partitions
- */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * USB
- */
-#ifdef CONFIG_BC3450_USB
-# define CONFIG_USB_OHCI
-# define CONFIG_USB_STORAGE
-#endif /* CONFIG_BC3450_USB */
-
-/*
- * POST support
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif /* CONFIG_POST */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_BSP
-
-#ifdef CONFIG_VIDEO
- #define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_BC3450_IDE
- #define CONFIG_CMD_IDE
-#endif
-
-#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
- #ifdef CONFIG_FAT
- #define CONFIG_CMD_FAT
- #endif
-
- #ifdef CONFIG_EXT2
- #define CONFIG_CMD_EXT2
- #endif
-#endif
-
-#ifdef CONFIG_BC3450_USB
- #define CONFIG_CMD_USB
-#endif
-
-#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
-#endif
-
-#ifdef CONFIG_POST
- #define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo;"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ipaddr=192.168.1.10\0" \
- "serverip=192.168.1.3\0" \
- "netmask=255.255.255.0\0" \
- "hostname=bc3450\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "kernel_addr=fc0a0000\0" \
- "ramdisk_addr=fc1c0000\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addcons=setenv bootargs $(bootargs) " \
- "console=ttyS0,$(baudrate) console=tty0\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile); " \
- "run nfsargs addip addcons; bootm\0" \
- "ide_nfs=run nfsargs addip addcons; " \
- "disk 200000 0:1; bootm\0" \
- "ide_ide=run ideargs addip addcons; " \
- "disk 200000 0:1; bootm\0" \
- "usb_self=run usbload; run ramargs addip addcons; " \
- "bootm 200000 400000\0" \
- "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
- "usbboot 400000 0:2\0" \
- "bootfile=uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 $(filesize);" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for I?C EEPROM M24C32
- * M24C64 should work also. For other EEPROMs config should be verified.
- *
- * The TQM5200 module may hold an EEPROM at address 0x50.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * RTC configuration
- */
-#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
-# define CONFIG_RTC_M41T11 1
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#else
-# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
-# define CONFIG_BOARD_EARLY_INIT_R
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif /*CONFIG_POST*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- *
- * Define CONFIG_MPC5xxx_MII10 to force FEC@10MBIT
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#undef CONFIG_MPC5xxx_MII10
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration on BC3450
- *
- * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
- * PSC2: UART2 [0x xxxxxx4x]
- * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
- * PSC3: USB2 [0x xxxxx1xx]
- * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
- * (this has to match
- * CONFIG_USB_CONFIG which is
- * used by usb_ohci.c to set
- * the USB ports)
- * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
- * (this is reset to '5'
- * in FEC driver: fec.c)
- * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
- * ATA/CS: ??? [0x x1xxxxxx]
- * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
- * CS1: Use Pin gpio_wkup_6 as second
- * SDRAM chip select (mem_cs1)
- * Timer: CAN2 / SPI
- * I2C: CAN1 / I?C2 [0x bxxxxxxx]
- */
-#ifdef CONFIG_BC3450_AC97
-# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
-#else /* PSC2=UART2 */
-# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
- /* more extensive mem test */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-/* automatic configuration of chip selects */
-#ifdef CONFIG_TQM5200
-# define CONFIG_LAST_STAGE_INIT
-#endif /* CONFIG_TQM5200 */
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#ifdef CONFIG_TQM5200
-# define CONFIG_SYS_CS2_START 0xE5000000
-# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
-# define CONFIG_SYS_CS2_CFG 0x0004D930
-#endif /* CONFIG_TQM5200 */
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#ifdef CONFIG_TQM5200
-# define SM501_FB_BASE 0xE0000000
-# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-# define CONFIG_SYS_CS1_CFG 0x8F48FF70
-# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-#endif /* CONFIG_TQM5200 */
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
- /* flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*
- * USB stuff
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
-
-/*
- * IDE/ATA stuff Supports IDE harddisk
- */
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 2/7] powerpc: ppc4xx: remove JSE board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
2015-03-17 3:28 ` [U-Boot] [PATCH 1/7] powerpc: mpc5xxx: remove BC3450 board support Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 3/7] powerpc: mpc5xxx: remove aev, TB5200 " Masahiro Yamada
` (5 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Williams <steve@icarus.com>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/jse/Kconfig | 9 -
board/jse/MAINTAINERS | 6 -
board/jse/Makefile | 12 -
board/jse/README.txt | 48 ----
board/jse/flash.c | 491 ----------------------------------------
board/jse/host_bridge.c | 77 -------
board/jse/init.S | 75 ------
board/jse/jse.c | 147 ------------
board/jse/jse_priv.h | 12 -
board/jse/sdram.c | 169 --------------
configs/JSE_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/JSE.h | 276 ----------------------
14 files changed, 1 insertion(+), 1329 deletions(-)
delete mode 100644 board/jse/Kconfig
delete mode 100644 board/jse/MAINTAINERS
delete mode 100644 board/jse/Makefile
delete mode 100644 board/jse/README.txt
delete mode 100644 board/jse/flash.c
delete mode 100644 board/jse/host_bridge.c
delete mode 100644 board/jse/init.S
delete mode 100644 board/jse/jse.c
delete mode 100644 board/jse/jse_priv.h
delete mode 100644 board/jse/sdram.c
delete mode 100644 configs/JSE_defconfig
delete mode 100644 include/configs/JSE.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 5db5e34..e151200 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_CSB272
config TARGET_CSB472
bool "Support csb472"
-config TARGET_JSE
- bool "Support JSE"
-
config TARGET_KORAT
bool "Support korat"
@@ -204,7 +201,6 @@ source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/jse/Kconfig"
source "board/korat/Kconfig"
source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
diff --git a/board/jse/Kconfig b/board/jse/Kconfig
deleted file mode 100644
index 48905fa..0000000
--- a/board/jse/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_JSE
-
-config SYS_BOARD
- default "jse"
-
-config SYS_CONFIG_NAME
- default "JSE"
-
-endif
diff --git a/board/jse/MAINTAINERS b/board/jse/MAINTAINERS
deleted file mode 100644
index 818a5a0..0000000
--- a/board/jse/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JSE BOARD
-M: Stephen Williams <steve@icarus.com>
-S: Maintained
-F: board/jse/
-F: include/configs/JSE.h
-F: configs/JSE_defconfig
diff --git a/board/jse/Makefile b/board/jse/Makefile
deleted file mode 100644
index feac3a8..0000000
--- a/board/jse/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright 2004 Picture Elements, Inc.
-# Stephen Williams <steve@icarus.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = jse.o sdram.o flash.o host_bridge.o
-obj-y += init.o
diff --git a/board/jse/README.txt b/board/jse/README.txt
deleted file mode 100644
index 84497db..0000000
--- a/board/jse/README.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-JSE Configuration Details
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xf4000000 - 0xf4000fff
-
-The 405GPr includes a 4K on-chip memory that can be placed however
-software chooses. I choose to place the memory at this address, to
-keep it out of the cachable areas.
-
-
-Memory Bank 1 -- SystemACE Controller
--------------------------------------
-
-0xf0000000 - 0xf00fffff
-
-The SystemACE chip is along on peripheral bank CS#1. We don't need
-much space, but 1Meg is the smallest we can configure the chip to
-allocate. We need it far away from the flash region, because this
-region is set to be non-cached.
-
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC405GPr
-chip.
-
-SDRAM
------
-
-0x00000000 - 0x07ffffff (128 MBytes)
diff --git a/board/jse/flash.c b/board/jse/flash.c
deleted file mode 100644
index a550f7d..0000000
--- a/board/jse/flash.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh at net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#if CONFIG_SYS_MAX_FLASH_BANKS != 1
-#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
-#endif
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
-
- /* Init: no FLASHes known */
- flash_info[0].flash_id = FLASH_UNKNOWN;
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM + monitor_flash_len - 1,
- &flash_info[0]);
- flash_info[0].size = size_b0;
-
- return size_b0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-/*
- * This implementation assumes that the flash chips are uniform sector
- * devices. This is true for all likely JSE devices.
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- unsigned idx;
- unsigned long sector_size = info->size / info->sector_count;
-
- for (idx = 0; idx < info->sector_count; idx += 1) {
- info->start[idx] = base + (idx * sector_size);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf ("SST ");
- break;
- case FLASH_MAN_STM:
- printf ("ST Micro ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- /* (Reduced table of only parts expected in JSE boards.) */
- switch (info->flash_id) {
- case FLASH_MAN_AMD | FLASH_AM040:
- printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_MAN_STM | FLASH_AM040:
- printf ("MM29W040W (512 Kbit, uniform sector size)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
-
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- printf("Unknown flash manufacturer code: 0x%x\n", value);
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* Calculate the sector offsets (Use JSE Optimized code). */
- flash_get_offsets(base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr =
- (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf ("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) ==
- FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay (1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7 (info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait@least 80us - let's wait 1 ms */
- udelay (1000);
-
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 =
- (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c
deleted file mode 100644
index 76c07b0..0000000
--- a/board/jse/host_bridge.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve at icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ident "$Id:$"
-
-# include <common.h>
-# include <pci.h>
-# include "jse_priv.h"
-
-/*
- * The JSE board has an Intel 21555 non-transparent bridge for
- * communication with the host. We need to render it harmless on the
- * JSE side, but leave it alone on the host (primary) side. Normally,
- * this will all be done before the host BIOS can gain access to the
- * board, due to the Primary Access Lockout bit.
- *
- * The host_bridge_init function is called as a late initialization
- * function, after most of the board is set up, including a PCI scan.
- */
-
-void host_bridge_init (void)
-{
- /* The bridge chip is at a fixed location. */
- pci_dev_t dev = PCI_BDF (0, 10, 0);
-
- /* Set PCI Class code --
- The primary side sees this class code at 0x08 in the
- primary config space. This must be something other then a
- bridge, or MS Windows starts doing weird stuff to me. */
- pci_write_config_dword (dev, 0x48, 0x04800000);
-
- /* Set subsystem ID --
- The primary side sees this value at 0x2c. We set it here so
- that the host can tell what sort of device this is:
- We are a Picture Elements [0x12c5] JSE [0x008a]. */
- pci_write_config_dword (dev, 0x6c, 0x008a12c5);
-
- /* Downstream (Primary-to-Secondary) BARs are set up mostly
- off. We need only the Memory-0 Bar so that the host can get
- at the CSR region to set up tables and the lot. */
-
- /* Downstream Memory 0 setup (4K for CSR) */
- pci_write_config_dword (dev, 0xac, 0xfffff000);
- /* Downstream Memory 1 setup (off) */
- pci_write_config_dword (dev, 0xb0, 0x00000000);
- /* Downstream Memory 2 setup (off) */
- pci_write_config_dword (dev, 0xb4, 0x00000000);
- /* Downstream Memory 3 setup (off) */
- pci_write_config_dword (dev, 0xb8, 0x00000000);
-
- /* Upstream (Secondary-to-Primary) BARs are used to get at
- host memory from the JSE card. Create two regions: a small
- one to manage individual word reads/writes, and a larger
- one for doing bulk frame moves. */
-
- /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
- pci_write_config_dword (dev, 0xc4, 0xfffff000);
- /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
- pci_write_config_dword (dev, 0xc8, 0xfffff000);
-
- /* Upstream Memory 2 (BAR4) uses page translation, and is set
- up in CCR1. Configure for 4K pages. */
-
- /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
- bit as well, so we are done configuring after this
- point. Therefore, this must be the last step.
-
- CC1[15:12]= 0 (disable I2O message unit)
- CC1[11:8] = 0x5 (4K page size)
- CC0[11] = 1 (Secondary Clock Disable: disable clock)
- CC0[10] = 0 (Primary Access Lockout: allow primary access)
- */
- pci_write_config_dword (dev, 0xcc, 0x05000800);
-}
diff --git a/board/jse/init.S b/board/jse/init.S
deleted file mode 100644
index 4e449fe..0000000
--- a/board/jse/init.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* */
-/* */
-/* The layout for the PEI JSE board: */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - SystemACE */
-/* Bank 2 - not used */
-/* Bank 3 - not used */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - not used */
-/*------------------------------------------------------------------------- */
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*----------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*----------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------- */
- /* Memory Bank 0 (Flash) initialization */
- /*----------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr EBC0_CFGDATA,r4
-
- blr
diff --git a/board/jse/jse.c b/board/jse/jse.c
deleted file mode 100644
index a0913c3..0000000
--- a/board/jse/jse.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve at icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-# include <common.h>
-# include <asm/ppc4xx.h>
-# include <asm/processor.h>
-# include <asm/io.h>
-# include "jse_priv.h"
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-int board_early_init_f (void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the JSE board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED/UNUSED
- | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
- | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
- | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
- | IRQ 31 (EXT IRQ 6) (unused)
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /* Configure the interface to the SystemACE MCU port.
- The SystemACE is fast, but there is no reason to have
- excessivly tight timings. So the settings are slightly
- generous. */
-
- /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
- WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, 0x01011000);
-
- /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
-
- /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
- /* CPC0_CR1 |= PCIPW */
- mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init (void)
-{
- return board_early_init_f ();
-}
-
-#endif
-
-/*
- * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
- * also in the init_sequence array) but later. Many more things are
- * configured, but we are still running from flash.
- */
-int checkboard (void)
-{
- unsigned vers, status;
-
- /* check that the SystemACE chip is alive. */
- printf ("ACE: ");
- vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
- printf ("SystemACE %u.%u (build %u)",
- (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
-
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
-#ifdef DEBUG
- printf (" STATUS=0x%08x", status);
-#endif
- /* If the flash card is present and there is an initial error,
- then force a restart of the program. */
- if (status & 0x00000010) {
- printf (" CFDETECT");
-
- if (status & 0x04) {
- /* CONTROLREG = CFGPROG */
- writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- udelay (500);
- /* CONTROLREG = CFGRESET */
- writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- udelay (500);
- writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
- /* CONTROLREG = CFGSTART */
- writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
-
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
- }
- }
-
- /* Wait for the SystemACE to program its chain of devices. */
- while ((status & 0x84) == 0x00) {
- udelay (500);
- status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
- }
-
- if (status & 0x04)
- printf (" CFG-ERROR");
- if (status & 0x80)
- printf (" CFGDONE");
-
- printf ("\n");
-
- /* Force /RTS to active. The board it not wired quite
- correctly to use cts/rtc flow control, so just force the
- /RST active and forget about it. */
- writeb (readb (0xef600404) | 0x03, 0xef600404);
-
- printf ("JSE: ready\n");
-
- return 0;
-}
-
-/* **** No more functions called by board_init_f. **** */
-
-/*
- * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
- * point, basic setup is done, U-Boot has been moved into SDRAM and
- * PCI has been set up. From here we done late setup.
- */
-int misc_init_r (void)
-{
- host_bridge_init ();
- return 0;
-}
diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h
deleted file mode 100644
index f61204b..0000000
--- a/board/jse/jse_priv.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __jse_priv_H
-#define __jse_prov_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve at icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern void host_bridge_init(void);
-
-#endif
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
deleted file mode 100644
index 5639bed..0000000
--- a/board/jse/sdram.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve at icarus.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-# define SDRAM_LEN 0x08000000
-
-/*
- * this is even after checkboard. It returns the size of the SDRAM
- * that we have installed. This function is called by board_init_f
- * in arch/powerpc/lib/board.c to initialize the memory and return what I
- * found.
- */
-phys_size_t initdram (int board_type)
-{
- /* Configure the SDRAMS */
-
- /* disable memory controller */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- udelay (500);
-
- /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Clear SDRAM0_ECCCFG (disable ECC) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
- mtdcr (SDRAM0_CFGDATA, 0xffffffff);
-
- /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, 0x010a4016);
-
- /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, 0x00084001);
-
- /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- mtdcr (SDRAM0_CFGDATA, 0x04084001);
-
- /* Memory Bank 2 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* Memory Bank 3 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- mtdcr (SDRAM0_CFGDATA, 0x00000000);
-
- /* refresh timer = 0x400 */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, 0x04000000);
-
- /* Power management idle timer set to the default. */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
- mtdcr (SDRAM0_CFGDATA, 0x07c00000);
-
- udelay (500);
-
- /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, 0x80e00000);
-
- return SDRAM_LEN;
-}
-
-/*
- * The U-Boot core, as part of the initialization to prepare for
- * loading the monitor into SDRAM, requests of this function that the
- * memory be tested. Return 0 if the memory tests OK.
- */
-int testdram (void)
-{
- unsigned long idx;
- unsigned val;
- unsigned errors;
- volatile unsigned long *sdram;
-
-#ifdef DEBUG
- printf ("SDRAM Controller Registers --\n");
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_CFG : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, 0x24);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_STATUS: 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_B0CR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_B1CR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_TR : 0x%08x\n", val);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- val = mfdcr (SDRAM0_CFGDATA);
- printf (" SDRAM0_RTR : 0x%08x\n", val);
-#endif
-
- /* Wait for memory to be ready by testing MRSCMPbit
- bit. Really, there should already have been plenty of time,
- given it was started long ago. But, best to check. */
- for (idx = 0; idx < 1000000; idx += 1) {
- mtdcr (SDRAM0_CFGADDR, 0x24);
- val = mfdcr (SDRAM0_CFGDATA);
- if (val & 0x80000000)
- break;
- }
-
- if (!(val & 0x80000000)) {
- printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
- return 1;
- }
-
- /* Start memory test. */
- printf ("test: %u MB - ", SDRAM_LEN / 1048576);
-
- sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
-
- printf ("write - ");
- for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
- sdram[idx + 0] = idx;
- sdram[idx + 1] = ~idx;
- }
-
- printf ("read - ");
- errors = 0;
- for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
- if (sdram[idx + 0] != idx)
- errors += 1;
- if (sdram[idx + 1] != ~idx)
- errors += 1;
- if (errors > 0)
- break;
- }
-
- if (errors > 0) {
- printf ("NOT OK\n");
- printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
- sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
- return 1;
- }
-
- printf ("ok\n");
- return 0;
-}
diff --git a/configs/JSE_defconfig b/configs/JSE_defconfig
deleted file mode 100644
index 14c9c2f..0000000
--- a/configs/JSE_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_JSE=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 481f4d8..668431c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
BC3450 powerpc mpc5xxx - -
hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
deleted file mode 100644
index 5cc2557..0000000
--- a/include/configs/JSE.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * (C) Copyright 2003 Picture Elements, Inc.
- * Stephen Williams <steve@icarus.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options for the JSE board
- * (Theoretically easy to change, but the board is fixed.)
- */
-
-#define CONFIG_JSE 1
- /* JSE has a PPC405GPr */
-#define CONFIG_405GP 1
- /* ... with a 33MHz OSC. connected to the SysCLK input */
-#define CONFIG_SYS_CLK_FREQ 33333333
- /* ... with on-chip memory here (4KBytes) */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
- /* Do not set up locked dcache as init ram. */
-#undef CONFIG_SYS_INIT_DCACHE_CS
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
- /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
-#define CONFIG_SYSTEMACE 1
-#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
-#define CONFIG_SYS_SYSTEMACE_WIDTH 8
-#define CONFIG_DOS_PARTITION 1
-
- /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
- /* ... place INIT RAM in the OCM address */
-# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
- /* ... give it the whole init ram */
-# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
- /* ... Shave a bit off the end for global data */
-# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
- /* ... and place the stack pointer at the top of what's left. */
-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
- /* Enable board_pre_init function */
-#define CONFIG_BOARD_PRE_INIT 1
-#define CONFIG_BOARD_EARLY_INIT_F 1
- /* Disable post-clk setup init function */
-#undef CONFIG_BOARD_POSTCLK_INIT
- /* Disable call to post_init_f: late init function. */
-#undef CONFIG_POST
- /* Enable DRAM test. */
-#define CONFIG_SYS_DRAM_TEST 1
- /* Enable misc_init_r function. */
-#define CONFIG_MISC_INIT_R 1
-
- /* JSE has EEPROM chips that are good for environment. */
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#undef CONFIG_ENV_IS_NOWHERE
-
- /* This is the 7bit address of the device, not including P. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
- /* After the device address, need one more address byte. */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
- /* The EEPROM is 512 bytes. */
-#define CONFIG_SYS_EEPROM_SIZE 512
- /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
- /* Put the environment in the second half. */
-#define CONFIG_ENV_OFFSET 0x00
-#define CONFIG_ENV_SIZE 512
-
- /* The JSE connects UART1 to the console tap connector. */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
- /* Set console baudrate to 9600 */
-#define CONFIG_BAUDRATE 9600
-
-/*
- * Configuration related to auto-boot.
- *
- * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
- * before resorting to autoboot. This value can be overridden by the
- * bootdelay environment variable.
- *
- * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
- * user that an autoboot will happen.
- *
- * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
- * execute to boot the JSE. This loads the uimage and initrd.img files
- * from CompactFlash into memory, then boots them from memory.
- *
- * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
- * it going on the JSE.
- */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
-#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-
- /* watchdog disabled */
-#undef CONFIG_WATCHDOG
- /* SPD EEPROM (sdram speed config) disabled */
-#undef CONFIG_SPD_EEPROM
-#undef SPD_EEPROM_ADDRESS
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 3/7] powerpc: mpc5xxx: remove aev, TB5200 board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
2015-03-17 3:28 ` [U-Boot] [PATCH 1/7] powerpc: mpc5xxx: remove BC3450 board support Masahiro Yamada
2015-03-17 3:28 ` [U-Boot] [PATCH 2/7] powerpc: ppc4xx: remove JSE " Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 4/7] powerpc: ppc4xx: remove W7OLMC/W7OLMG " Masahiro Yamada
` (4 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 6 -
board/tqc/tqm5200/Kconfig | 26 --
board/tqc/tqm5200/MAINTAINERS | 3 -
board/tqc/tqm5200/Makefile | 2 +-
board/tqc/tqm5200/cmd_tb5200.c | 88 -------
board/tqc/tqm5200/tqm5200.c | 12 +-
configs/TB5200_B_defconfig | 4 -
configs/TB5200_defconfig | 3 -
configs/aev_defconfig | 3 -
doc/README.scrapyard | 2 +
include/configs/TB5200.h | 496 ---------------------------------------
include/configs/aev.h | 390 ------------------------------
12 files changed, 4 insertions(+), 1031 deletions(-)
delete mode 100644 board/tqc/tqm5200/cmd_tb5200.c
delete mode 100644 configs/TB5200_B_defconfig
delete mode 100644 configs/TB5200_defconfig
delete mode 100644 configs/aev_defconfig
delete mode 100644 include/configs/TB5200.h
delete mode 100644 include/configs/aev.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index 1b81fb5..e2d48f3 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -65,15 +65,9 @@ config TARGET_DIGSY_MTC
config TARGET_PCM030
bool "Support pcm030"
-config TARGET_AEV
- bool "Support aev"
-
config TARGET_CHARON
bool "Support charon"
-config TARGET_TB5200
- bool "Support TB5200"
-
config TARGET_TQM5200
bool "Support TQM5200"
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
index 0e4cd69..738dc80 100644
--- a/board/tqc/tqm5200/Kconfig
+++ b/board/tqc/tqm5200/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_AEV
-
-config SYS_BOARD
- default "tqm5200"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "aev"
-
-endif
-
if TARGET_CHARON
config SYS_BOARD
@@ -24,19 +11,6 @@ config SYS_CONFIG_NAME
endif
-if TARGET_TB5200
-
-config SYS_BOARD
- default "tqm5200"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TB5200"
-
-endif
-
if TARGET_TQM5200
config SYS_BOARD
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
index d3eb543..12d143d 100644
--- a/board/tqc/tqm5200/MAINTAINERS
+++ b/board/tqc/tqm5200/MAINTAINERS
@@ -9,9 +9,6 @@ F: configs/cam5200_defconfig
F: configs/cam5200_niosflash_defconfig
F: configs/fo300_defconfig
F: configs/MiniFAP_defconfig
-F: include/configs/TB5200.h
-F: configs/TB5200_defconfig
-F: configs/TB5200_B_defconfig
F: configs/TQM5200_defconfig
F: configs/TQM5200_B_defconfig
F: configs/TQM5200_B_HIGHBOOT_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index 80c1eba..f7c97b7 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
+obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c
deleted file mode 100644
index 876258d..0000000
--- a/board/tqc/tqm5200/cmd_tb5200.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2005 - 2006
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * TB5200 specific functions
- */
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_CMD_BSP)
-#if defined (CONFIG_TB5200)
-
-#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
-
-static void led_init(void)
-{
- struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
- /* configure timer 4 for simple GPIO output */
- gpt->gpt4.emsr |= 0x00000024;
-}
-
-int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
- led_init();
-
- if (strcmp (argv[1], "on") == 0) {
- debug ("switch status LED on\n");
- gpt->gpt4.emsr |= (1 << 4);
- } else if (strcmp (argv[1], "off") == 0) {
- debug ("switch status LED off\n");
- gpt->gpt4.emsr &= ~(1 << 4);
- } else {
- printf ("Usage:\nled on/off\n");
- return 1;
- }
-
- return 0;
-}
-
-static void sm501_backlight (unsigned int state)
-{
- if (state == 1) {
- *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
- (1 << 26) | (1 << 27);
- } else if (state == 0)
- *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
- ~((1 << 26) | (1 << 27));
-}
-
-int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (strcmp (argv[1], "on") == 0) {
- debug ("switch backlight on\n");
- sm501_backlight (1);
- } else if (strcmp (argv[1], "off") == 0) {
- debug ("switch backlight off\n");
- sm501_backlight (0);
- } else {
- printf ("Usage:\nbacklight on/off\n");
- return 1;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- led , 2, 1, cmd_led,
- "switch status LED on or off",
- "on/off"
-);
-
-U_BOOT_CMD(
- backlight , 2, 1, cmd_backlight,
- "switch backlight on or off",
- "on/off"
- );
-
-#endif /* CONFIG_STK52XX */
-#endif
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index e9363ea..4d4f29d 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -258,11 +258,6 @@ phys_size_t initdram (int board_type)
int checkboard (void)
{
-#if defined(CONFIG_AEVFIFO)
- puts ("Board: AEVFIFO\n");
- return 0;
-#endif
-
#if defined(CONFIG_TQM5200S)
# define MODULE_NAME "TQM5200S"
#else
@@ -271,8 +266,6 @@ int checkboard (void)
#if defined(CONFIG_STK52XX)
# define CARRIER_NAME "STK52xx"
-#elif defined(CONFIG_TB5200)
-# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
# define CARRIER_NAME "CAM5200"
#elif defined(CONFIG_FO300)
@@ -762,7 +755,7 @@ void video_get_info_str (int line_number, char *info)
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
- defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
+ defined(CONFIG_STK52XX)
} else if (line_number == 2) {
#if defined (CONFIG_CHARON)
strcpy (info, " on a CHARON carrier board");
@@ -770,9 +763,6 @@ void video_get_info_str (int line_number, char *info)
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#endif
-#if defined (CONFIG_TB5200)
- strcpy (info, " on a TB5200 carrier board");
-#endif
#if defined (CONFIG_FO300)
strcpy (info, " on a FO300 carrier board");
#endif
diff --git a/configs/TB5200_B_defconfig b/configs/TB5200_B_defconfig
deleted file mode 100644
index 00d06c9..0000000
--- a/configs/TB5200_B_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TB5200=y
diff --git a/configs/TB5200_defconfig b/configs/TB5200_defconfig
deleted file mode 100644
index 13d8e2d..0000000
--- a/configs/TB5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TB5200=y
diff --git a/configs/aev_defconfig b/configs/aev_defconfig
deleted file mode 100644
index b2a9589..0000000
--- a/configs/aev_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_AEV=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 668431c..e3c4e2c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+aev powerpc mpc5xxx - -
+TB5200 powerpc mpc5xxx - -
JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
BC3450 powerpc mpc5xxx - -
hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
deleted file mode 100644
index b4daedc..0000000
--- a/include/configs/TB5200.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0xFFF00000 boot high (for a backup copy of U-Boot)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
-#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Video console
- */
-#if 1
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_USB
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC07FFFF;" \
- "erase FC000000 FC07FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC07FFFF\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-#endif /* CONFIG_TQM5200_B */
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* List of I2C addresses to be verified by POST */
-#undef CONFIG_SYS_POST_I2C_ADDRS
-#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_SLAVE}
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_TQM5200_B */
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#if defined(CONFIG_TQM5200_B)
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
- "1280k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-#else
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
- "1408k(kernel)," \
- "2m(initrd)," \
- "4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
-#endif /* CONFIG_TQM5200_B */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_TQM5200_B */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#if defined(CONFIG_TQM5200_B)
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#endif /* CONFIG_TQM5200_B */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC@10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC3: Bits 20:23 (mask: 0x00000300):
- * 0001 -> USB2
- * 0000 -> GPIO
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
- year */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START 0xE5000000
-#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
-#define CONFIG_SYS_CS2_CFG 0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE 0xE0000000
-#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-#define CONFIG_SYS_CS1_CFG 0x8F48FF70
-#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
deleted file mode 100644
index 2dffcfb..0000000
--- a/include/configs/aev.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause at tqs.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
-#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
-#define CONFIG_AEVFIFO 1
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration with room for
- * max 64 MByte Flash ROM)
- * 0xFFF00000 boot high (for a backup copy of U-Boot)
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#ifdef CONFIG_AEVFIFO
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-/* #define CONFIG_PCI_SCAN_SHOW 1 */
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif /* CONFIG_AEVFIFO */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define CONFIG_TIMESTAMP /* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} " \
- "console=ttyS0,${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#ifdef CONFIG_TQM5200_REV100
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
-#else
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
-#endif
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif /* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC@10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START 0xE5000000
-#define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */
-#define CONFIG_SYS_CS2_CFG 0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE 0xE0000000
-#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
-#define CONFIG_SYS_CS1_CFG 0x8F48FF70
-#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 4/7] powerpc: ppc4xx: remove W7OLMC/W7OLMG board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
` (2 preceding siblings ...)
2015-03-17 3:28 ` [U-Boot] [PATCH 3/7] powerpc: mpc5xxx: remove aev, TB5200 " Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 5/7] powerpc: mpc5xxx: remove galaxy5200 " Masahiro Yamada
` (3 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Erik Theisen <etheisen@mindspring.com>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 7 -
board/w7o/Kconfig | 19 -
board/w7o/MAINTAINERS | 8 -
board/w7o/Makefile | 13 -
board/w7o/cmd_vpd.c | 48 ---
board/w7o/errors.h | 81 ----
board/w7o/flash.c | 927 ----------------------------------------
board/w7o/fpga.c | 371 ----------------
board/w7o/fsboot.c | 73 ----
board/w7o/init.S | 244 -----------
board/w7o/post1.S | 724 -------------------------------
board/w7o/post2.c | 98 -----
board/w7o/u-boot.lds.debug | 121 ------
board/w7o/vpd.c | 412 ------------------
board/w7o/vpd.h | 118 -----
board/w7o/w7o.c | 257 -----------
board/w7o/w7o.h | 73 ----
board/w7o/watchdog.c | 31 --
configs/W7OLMC_defconfig | 3 -
configs/W7OLMG_defconfig | 3 -
doc/README.scrapyard | 2 +
include/configs/W7OLMC.h | 314 --------------
include/configs/W7OLMG.h | 317 --------------
23 files changed, 2 insertions(+), 4262 deletions(-)
delete mode 100644 board/w7o/Kconfig
delete mode 100644 board/w7o/MAINTAINERS
delete mode 100644 board/w7o/Makefile
delete mode 100644 board/w7o/cmd_vpd.c
delete mode 100644 board/w7o/errors.h
delete mode 100644 board/w7o/flash.c
delete mode 100644 board/w7o/fpga.c
delete mode 100644 board/w7o/fsboot.c
delete mode 100644 board/w7o/init.S
delete mode 100644 board/w7o/post1.S
delete mode 100644 board/w7o/post2.c
delete mode 100644 board/w7o/u-boot.lds.debug
delete mode 100644 board/w7o/vpd.c
delete mode 100644 board/w7o/vpd.h
delete mode 100644 board/w7o/w7o.c
delete mode 100644 board/w7o/w7o.h
delete mode 100644 board/w7o/watchdog.c
delete mode 100644 configs/W7OLMC_defconfig
delete mode 100644 configs/W7OLMG_defconfig
delete mode 100644 include/configs/W7OLMC.h
delete mode 100644 include/configs/W7OLMG.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index e151200..75e4507 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -32,12 +32,6 @@ config TARGET_SC3
config TARGET_T3CORP
bool "Support t3corp"
-config TARGET_W7OLMC
- bool "Support W7OLMC"
-
-config TARGET_W7OLMG
- bool "Support W7OLMG"
-
config TARGET_ZEUS
bool "Support zeus"
@@ -212,7 +206,6 @@ source "board/prodrive/p3p440/Kconfig"
source "board/sbc405/Kconfig"
source "board/sc3/Kconfig"
source "board/t3corp/Kconfig"
-source "board/w7o/Kconfig"
source "board/xes/xpedite1000/Kconfig"
source "board/xilinx/ml507/Kconfig"
source "board/xilinx/ppc405-generic/Kconfig"
diff --git a/board/w7o/Kconfig b/board/w7o/Kconfig
deleted file mode 100644
index fd1b422..0000000
--- a/board/w7o/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_W7OLMC
-
-config SYS_BOARD
- default "w7o"
-
-config SYS_CONFIG_NAME
- default "W7OLMC"
-
-endif
-
-if TARGET_W7OLMG
-
-config SYS_BOARD
- default "w7o"
-
-config SYS_CONFIG_NAME
- default "W7OLMG"
-
-endif
diff --git a/board/w7o/MAINTAINERS b/board/w7o/MAINTAINERS
deleted file mode 100644
index bfedee5..0000000
--- a/board/w7o/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-W7O BOARD
-M: Erik Theisen <etheisen@mindspring.com>
-S: Maintained
-F: board/w7o/
-F: include/configs/W7OLMC.h
-F: configs/W7OLMC_defconfig
-F: include/configs/W7OLMG.h
-F: configs/W7OLMG_defconfig
diff --git a/board/w7o/Makefile b/board/w7o/Makefile
deleted file mode 100644
index 955de50..0000000
--- a/board/w7o/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2001
-# Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
- watchdog.o
-obj-y += init.o post1.o
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
deleted file mode 100644
index 879cb61..0000000
--- a/board/w7o/cmd_vpd.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_CMD_BSP)
-
-#include "vpd.h"
-
-/* ======================================================================
- * Interpreter command to retrieve board specific Vital Product Data, "VPD"
- * ======================================================================
- */
-int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- VPD vpd; /* Board specific data struct */
- uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
-
- /* Validate usage */
- if (argc > 2)
- return cmd_usage(cmdtp);
-
- /* Passed in EEPROM address */
- if (argc == 2)
- dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
-
- /* Read VPD and output it */
- if (!vpd_get_data (dev_addr, &vpd)) {
- vpd_print (&vpd);
- return 0;
- }
-
- return 1;
-}
-
-U_BOOT_CMD(
- vpd, 2, 1, do_vpd,
- "Read Vital Product Data",
- "[dev_addr]\n"
- " - Read VPD Data from default address, or device address 'dev_addr'."
-);
-
-#endif
diff --git a/board/w7o/errors.h b/board/w7o/errors.h
deleted file mode 100644
index 05540fb..0000000
--- a/board/w7o/errors.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, william.hunter at mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ERRORS_H_
-#define _ERRORS_H_
-
-#define ERR_FF -1 /* led test value(2) */
-#define ERR_00 0x0000 /* led test value(2) */
-#define ERR_LED 0x01 /* led test failed (1)(3)(4) */
-#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */
-#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */
-#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */
-#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */
-#define ERR_ADDG 0x08 /* start Address ghosting test (13) */
-#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */
-#define ERR_POST1 0x0a /* post1 tests complete */
-#define ERR_TMP1 0x0b /* */
-#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */
-#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */
-#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */
-#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */
-#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */
-#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */
-#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */
-#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */
-#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */
-#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */
-#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */
-#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */
-#define ERR_RTCG 0x18 /* start RTC test */
-#define ERR_RTCBAT 0x19 /* RTC battery failure */
-#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */
-#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */
-#define ERR_FPGAG 0x20 /* fault during FPGA programming */
-#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */
-#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */
-#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */
-#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */
-#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */
-#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */
-#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */
-#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */
-#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */
-#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */
-#define ERR_TempG 0x2b /* start temp sensor tests */
-#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */
-#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */
-#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */
-#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */
-#define ERR_lm75r 0x30 /* temp sensor read failure */
-#define ERR_lm75w 0x31 /* temp sensor write failure */
-
-
-#define ERR_POSTOK 0x55 /* PANIC: psych... OK */
-
-#if !defined(__ASSEMBLY__)
-extern void log_stat(int errcode);
-extern void log_warn(int errcode);
-extern void log_err(int errcode);
-#endif
-
-/*
-Debugging suggestions:
-(1) periferal data bus shorted or crossed
-(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
-(3) check p_we, p_r/w, p_oe, p_rdy lines.
-(4) check LED buffers
-(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
-(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
-(7) check SDRAM control lines and clocks
-(8) check decoupling caps, replace LSW SDRAM
-(9) check decoupling caps, replace MSW SDRAM
-(10)
-(11)
-(12)
-(13) SDRAM address shorted or unconnected, check sdram caps
-*/
-#endif /* _ERRORS_H_ */
diff --git a/board/w7o/flash.c b/board/w7o/flash.c
deleted file mode 100644
index 26bddc4..0000000
--- a/board/w7o/flash.c
+++ /dev/null
@@ -1,927 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- * Based on code by:
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#include <watchdog.h>
-
-/* info for FLASH chips */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word8(flash_info_t *info, ulong dest, ulong data);
-static int write_word32(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-unsigned long flash_init(void)
-{
- int i;
- unsigned long size_b0, base_b0;
- unsigned long size_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* Get Size of Boot and Main Flashes */
- size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
- &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- return 0;
- }
- size_b1 =
- flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
- &flash_info[1]);
- if (flash_info[1].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size_b1, size_b1 << 20);
- return 0;
- }
-
- /* Calculate base addresses */
- base_b0 = -size_b0;
-
- /* Setup offsets for Boot Flash */
- flash_get_offsets(base_b0, &flash_info[0]);
-
- /* Protect board level data */
- (void) flash_protect(FLAG_PROTECT_SET,
- base_b0,
- flash_info[0].start[1] - 1, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect(FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- /* Protect the FPGA image */
- (void) flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN -
- 1, &flash_info[1]);
-
- /* Protect the default boot image */
- (void) flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN,
- FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN +
- 0x600000 - 1, &flash_info[1]);
-
- /* Setup offsets for Main Flash */
- flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
-
- return size_b0 + size_b1;
-}
-
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table - FOR BOOT ROM ONLY!!! */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- }
-} /* end flash_get_offsets() */
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("1 x AMD ");
- break;
- case FLASH_MAN_STM:
- printf("1 x STM ");
- break;
- case FLASH_MAN_INTEL:
- printf("2 x Intel ");
- break;
- default:
- printf("Unknown Vendor ");
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- printf("AM29LV040 (4096 Kbit, uniform sector size)\n");
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
- printf("M29W040B (4096 Kbit, uniform block size)\n");
- else
- printf("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
- break;
- case FLASH_28F320J3A:
- printf("28F320J3A (32 Mbit = 128K x 32)\n");
- break;
- case FLASH_28F640J3A:
- printf("28F640J3A (64 Mbit = 128K x 64)\n");
- break;
- case FLASH_28F128J3A:
- printf("28F128J3A (128 Mbit = 128K x 128)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
- printf(" Size: %ld KB in %d Blocks\n",
- info->size >> 10, info->sector_count);
- } else {
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- }
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
- }
- printf("\n");
-} /* end flash_print_info() */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong base = (ulong) addr;
-
- /* Setup default type */
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
-
- /* Test for Boot Flash */
- if (base == FLASH_BASE0_PRELIM) {
- unsigned char value;
- volatile unsigned char *addr2 = (unsigned char *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- *(addr2 + 0x555) = 0xaa;
- *(addr2 + 0x2aa) = 0x55;
- *(addr2 + 0x555) = 0x90;
-
- /* Manufacture ID */
- value = *addr2;
- switch (value) {
- case (unsigned char) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (unsigned char) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- *addr2 = 0xf0; /* no or unknown flash */
- return 0;
- }
-
- /* Device ID */
- value = *(addr2 + 1);
- switch (value) {
- case (unsigned char) AMD_ID_LV040B:
- case (unsigned char) STM_ID_29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512Kb */
- default:
- *addr2 = 0xf0; /* => no or unknown flash */
- return 0;
- }
- } else { /* MAIN Flash */
- unsigned long value;
- volatile unsigned long *addr2 = (unsigned long *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- *addr2 = 0x90909090;
-
- /* Manufacture ID */
- value = *addr2;
- switch (value) {
- case (unsigned long) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- *addr2 = 0xff; /* no or unknown flash */
- return 0;
- }
-
- /* Device ID - This shit is interleaved... */
- value = *(addr2 + 1);
- switch (value) {
- case (unsigned long) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000 * 2;
- break; /* => 2 X 4 MB */
- case (unsigned long) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000 * 2;
- break; /* => 2 X 8 MB */
- case (unsigned long) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000 * 2;
- break; /* => 2 X 16 MB */
- default:
- *addr2 = 0xff; /* => no or unknown flash */
- }
- }
-
- /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- /* set up sector start address table */
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- break;
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base +
- (i * 0x00020000 * 2); /* 2 Banks */
- break;
- }
-
- /* Test for Boot Flash */
- if (base == FLASH_BASE0_PRELIM) {
- volatile unsigned char *addr2;
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address,
- * (AX .. A0) = 0x02
- * D0 = 1 if protected
- */
- addr2 = (volatile unsigned char *) (info->start[i]);
- info->protect[i] = *(addr2 + 2) & 1;
- }
-
- /* Restore read mode */
- *(unsigned char *) base = 0xF0; /* Reset NORMAL Flash */
- } else { /* Main Flash */
- volatile unsigned long *addr2;
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address,
- * (AX .. A0) = 0x02
- * D0 = 1 if protected
- */
- addr2 = (volatile unsigned long *) (info->start[i]);
- info->protect[i] = *(addr2 + 2) & 0x1;
- }
-
- /* Restore read mode */
- *(unsigned long *) base = 0xFFFFFFFF; /* Reset Flash */
- }
-
- return info->size;
-} /* end flash_get_size() */
-
-static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
-{
- int i;
-
- volatile uchar *vaddr = (uchar *) addr;
-
- /* Loop X times */
- for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */
- udelay(10);
- /* Pause 10 us */
-
- /* Check for completion */
- if ((vaddr[0] & 0x80) == (cmp_val & 0x80))
- return 0;
-
- /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
- if (!(i % 110000))
- putc('.');
-
- /* Kick the dog if needed */
- WATCHDOG_RESET();
- }
-
- return 1;
-} /* wait_for_DQ7() */
-
-static int flash_erase8(flash_info_t *info, int s_first, int s_last)
-{
- int tcode, rcode = 0;
- volatile uchar *addr = (uchar *) (info->start[0]);
- volatile uchar *sector_addr;
- int flag, prot, sect;
-
- /* Validate arguments */
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- /* Check for KNOWN flash type */
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- /* Check for protected sectors */
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- sector_addr = (uchar *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) ==
- FLASH_MAN_STM)
- printf("Erasing block %p\n", sector_addr);
- else
- printf("Erasing sector %p\n", sector_addr);
-
- /* Disable interrupts which might cause timeout */
- flag = disable_interrupts();
-
- *(addr + 0x555) = (uchar) 0xAA;
- *(addr + 0x2aa) = (uchar) 0x55;
- *(addr + 0x555) = (uchar) 0x80;
- *(addr + 0x555) = (uchar) 0xAA;
- *(addr + 0x2aa) = (uchar) 0x55;
- *sector_addr = (uchar) 0x30; /* sector erase */
-
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- * Takes up to 6 seconds.
- */
- tcode = wait_for_DQ7((ulong) sector_addr, 0x80, 6000);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Make sure we didn't timeout */
- if (tcode) {
- printf("Timeout\n");
- rcode = 1;
- }
- }
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (uchar *) info->start[0];
- *addr = (uchar) 0xF0; /* reset bank */
-
- printf(" done\n");
- return rcode;
-} /* end flash_erase8() */
-
-static int flash_erase32(flash_info_t *info, int s_first, int s_last)
-{
- int flag, sect;
- ulong start, now, last;
- int prot = 0;
-
- /* Validate arguments */
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
- return 1;
- }
-
- /* Check for KNOWN flash type */
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- /* Check for protected sectors */
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- start = get_timer(0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- WATCHDOG_RESET();
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *) (info->start[sect]);
- unsigned long status;
-
- /* Disable interrupts which might cause a timeout */
- flag = disable_interrupts();
-
- *addr = 0x00500050; /* clear status register */
- *addr = 0x00200020; /* erase setup */
- *addr = 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- now = get_timer(start);
- if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- /* suspend erase */
- *addr = 0x00B000B0;
- /* reset to read mode */
- *addr = 0x00FF00FF;
- return 1;
- }
-
- /*
- * show that we're waiting
- * every second (?)
- */
- if ((now - last) > 990) {
- putc('.');
- last = now;
- }
- }
- *addr = 0x00FF00FF; /* reset to read mode */
- }
- }
- printf(" done\n");
- return 0;
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
- return flash_erase8(info, s_first, s_last);
- else
- return flash_erase32(info, s_first, s_last);
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_buff8(flash_info_t *info, uchar *src, ulong addr,
- ulong cnt)
-{
- ulong cp, wp, data;
- ulong start;
- int i, l, rc;
-
- start = get_timer(0);
-
- wp = (addr & ~3); /* get lower word
- aligned address */
-
- /*
- * handle unaligned start bytes
- */
- l = addr - wp;
- if (l != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- rc = write_word8(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word8(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += 4;
- cnt -= 4;
- if (get_timer(start) > 1000) { /* every second */
- WATCHDOG_RESET();
- putc('.');
- start = get_timer(0);
- }
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
-
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return write_word8(info, wp, data);
-}
-
-#define FLASH_WIDTH 4 /* flash bus width in bytes */
-static int write_buff32(flash_info_t *info, uchar *src, ulong addr,
- ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
- ulong start;
-
- start = get_timer(0);
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- /* get lower FLASH_WIDTH aligned address */
- wp = (addr & ~(FLASH_WIDTH - 1));
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < FLASH_WIDTH && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- rc = write_word32(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i = 0; i < FLASH_WIDTH; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word32(info, wp, data);
- if (rc != 0)
- return rc;
-
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- if (get_timer(start) > 990) { /* every second */
- putc('.');
- start = get_timer(0);
- }
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
-
- for (; i < FLASH_WIDTH; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return write_word32(info, wp, data);
-}
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- int retval;
-
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
- retval = write_buff8(info, src, addr, cnt);
- else
- retval = write_buff32(info, src, addr, cnt);
-
- return retval;
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-static int write_word8(flash_info_t *info, ulong dest, ulong data)
-{
- volatile uchar *addr2 = (uchar *) (info->start[0]);
- volatile uchar *dest2 = (uchar *) dest;
- volatile uchar *data2 = (uchar *) &data;
- int flag;
- int i, tcode, rcode = 0;
-
- /* Check if Flash is (sufficently) erased */
- if ((*((volatile uchar *)dest) & (uchar)data) != (uchar)data)
- return 2;
-
- for (i = 0; i < (4 / sizeof(uchar)); i++) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *(addr2 + 0x555) = (uchar) 0xAA;
- *(addr2 + 0x2aa) = (uchar) 0x55;
- *(addr2 + 0x555) = (uchar) 0xA0;
-
- dest2[i] = data2[i];
-
- /* Wait for write to complete, up to 1ms */
- tcode = wait_for_DQ7((ulong) &dest2[i], data2[i], 1);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* Make sure we didn't timeout */
- if (tcode)
- rcode = 1;
- }
-
- return rcode;
-}
-
-static int write_word32(flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- while (((status = *addr) & 0x00800080) != 0x00800080) {
- WATCHDOG_RESET();
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x00FF00FF; /* restore read mode */
- return 1;
- }
- }
-
- *addr = 0x00FF00FF; /* restore read mode */
-
- return 0;
-}
-
-static int _flash_protect(flash_info_t *info, long sector)
-{
- int i;
- int flag;
- ulong status;
- int rcode = 0;
- volatile long *addr = (long *)sector;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- /* Disable interrupts which might cause Flash to timeout */
- flag = disable_interrupts();
-
- /* Issue command */
- *addr = 0x00500050L; /* Clear the status register */
- *addr = 0x00600060L; /* Set lock bit setup */
- *addr = 0x00010001L; /* Set lock bit confirm */
-
- /* Wait for command completion */
- for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */
- udelay(10);
- if ((*addr & 0x00800080L) == 0x00800080L)
- break;
- }
-
- /* Not successful? */
- status = *addr;
- if (status != 0x00800080L) {
- printf("Protect %x sector failed: %x\n",
- (uint) sector, (uint) status);
- rcode = 1;
- }
-
- /* Restore read mode */
- *addr = 0x00ff00ffL;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- break;
- case FLASH_AM040: /* No soft sector protection */
- break;
- }
-
- /* Turn protection on for this sector */
- for (i = 0; i < info->sector_count; i++) {
- if (info->start[i] == sector) {
- info->protect[i] = 1;
- break;
- }
- }
-
- return rcode;
-}
-
-static int _flash_unprotect(flash_info_t *info, long sector)
-{
- int i;
- int flag;
- ulong status;
- int rcode = 0;
- volatile long *addr = (long *) sector;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- case FLASH_28F640J3A:
- case FLASH_28F128J3A:
- /* Disable interrupts which might cause Flash to timeout */
- flag = disable_interrupts();
-
- *addr = 0x00500050L; /* Clear the status register */
- *addr = 0x00600060L; /* Clear lock bit setup */
- *addr = 0x00D000D0L; /* Clear lock bit confirm */
-
- /* Wait for command completion */
- for (i = 0; i < 80; i++) { /* 700ms timeout, wait 800 */
- udelay(10000); /* Delay 10ms */
- if ((*addr & 0x00800080L) == 0x00800080L)
- break;
- }
-
- /* Not successful? */
- status = *addr;
- if (status != 0x00800080L) {
- printf("Un-protect %x sector failed: %x\n",
- (uint) sector, (uint) status);
- *addr = 0x00ff00ffL;
- rcode = 1;
- }
-
- /* restore read mode */
- *addr = 0x00ff00ffL;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- break;
- case FLASH_AM040: /* No soft sector protection */
- break;
- }
-
- /*
- * Fix Intel's little red wagon. Reprotect
- * sectors that were protected before we undid
- * protection on a specific sector.
- */
- for (i = 0; i < info->sector_count; i++) {
- if (info->start[i] != sector) {
- if (info->protect[i]) {
- if (_flash_protect(info, info->start[i]))
- rcode = 1;
- }
- } else /* Turn protection off for this sector */
- info->protect[i] = 0;
- }
-
- return rcode;
-}
-
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int rcode;
-
- if (prot)
- rcode = _flash_protect(info, info->start[sector]);
- else
- rcode = _flash_unprotect(info, info->start[sector]);
-
- return rcode;
-}
diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c
deleted file mode 100644
index a27e8ab..0000000
--- a/board/w7o/fpga.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com
- * and
- * Bill Hunter, Wave 7 Optics, william.hunter at mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include "w7o.h"
-#include <asm/processor.h>
-#include <linux/compiler.h>
-#include "errors.h"
-
-static void
-fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
-{
- unsigned long i;
- volatile unsigned long val;
- volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
-
- for (i = 0; i < len; i++, src++) {
- val = *src;
- *dest = (unsigned short) ((val & 0xff000000L) >> 16);
- *dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
- *dest = (unsigned short) (val & 0x0000ff00L);
- *dest = (unsigned short) ((val & 0x000000ffL) << 8);
- }
-
- /* Terminate programming with 4 C clocks */
- dest = daddr;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
- val = *(unsigned short *) dest;
-
-}
-
-
-int
-fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
-{
- int i; /* index, intr disable flag */
- int start; /* timer */
- unsigned long greg, grego; /* GPIO & output register */
- unsigned long length; /* image size in words */
- unsigned long *source; /* image source addr */
- unsigned short *dest; /* destination FPGA addr */
- volatile unsigned short *ndest; /* temp dest FPGA addr */
- unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
- unsigned long eirq = GPIO_XCV_IRQ;
- int retval = -1; /* Function return value */
- __maybe_unused volatile unsigned short val; /* temp val */
-
- /* Setup some basic values */
- length = (size / 4) + 1; /* size in words, rounding UP
- is OK */
- source = (unsigned long *) saddr;
- dest = (unsigned short *) daddr;
-
- /* Get DCR output register */
- grego = in32(PPC405GP_GPIO0_OR);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Setup timeout timer */
- start = get_timer(0);
-
- /* Wait for FPGA init line to go low */
- while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
- /* Check for timeout - 100us max, so use 3ms */
- if (get_timer(start) > 3) {
- printf(" failed to start init.\n");
- log_warn(ERR_XINIT0); /* Don't halt */
-
- /* Reset line stays low */
- goto done; /* I like gotos... */
- }
- }
-
- /* Unreset FPGA */
- grego |= GPIO_XCV_PROG; /* PROG line high */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Wait for FPGA end of init period = init line go hi */
- while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
-
- /* Check for timeout */
- if (get_timer(start) > 3) {
- printf(" failed to exit init.\n");
- log_warn(ERR_XINIT1);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- goto done;
- }
- }
-
- /* Now program FPGA ... */
- ndest = dest;
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
- /* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg |= eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
-
- /* turn on open drain for CNFG */
- greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
- greg |= cnfg; /* CNFG open drain */
- out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
-
- /* Turn output enable on for CNFG */
- greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
- greg |= cnfg; /* CNFG tristate inactive */
- out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
-
- /* Setup FPGA for programming */
- grego &= ~cnfg; /* CONFIG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /*
- * Program the FPGA
- */
- printf("\n destination: 0x%lx ", (unsigned long) ndest);
-
- fpga_img_write(source, length, (unsigned short *) ndest);
-
- /* Done programming */
- grego |= cnfg; /* CONFIG line high */
- out32(PPC405GP_GPIO0_OR, grego);
-
- /* Turn output enable OFF for CNFG */
- greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
- greg &= ~cnfg; /* CNFG tristate inactive */
- out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
-
- /* Toggle IRQ/GPIO */
- greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
- greg &= ~eirq; /* toggle irq/gpio */
- mtdcr(CPC0_CR0, greg); /* ... just do it */
-
- /* XXX - Next FPGA addr */
- ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
- cnfg >>= 1; /* XXX - Next */
- eirq >>= 1;
- }
-
- /* Terminate programming with 4 C clocks */
- ndest = dest;
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
- val = *ndest;
- val = *ndest;
- val = *ndest;
- val = *ndest;
- ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
- }
-
- /* Setup timer */
- start = get_timer(0);
-
- /* Wait for FPGA end of programming period = Test DONE low */
- while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
-
- /* Check for timeout */
- if (get_timer(start) > 3) {
- printf(" done failed to come high.\n");
- log_warn(ERR_XDONE1);
-
- /* Reset FPGA */
- grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(PPC405GP_GPIO0_OR, grego);
-
- goto done;
- }
- }
-
- printf("\n FPGA load succeeded\n");
- retval = 0; /* Program OK */
-
-done:
- return retval;
-}
-
-/* FPGA image is stored in flash */
-extern flash_info_t flash_info[];
-
-int init_fpga(void)
-{
- unsigned int i, j, ptr; /* General purpose */
- unsigned char bufchar; /* General purpose character */
- unsigned char *buf; /* Start of image pointer */
- unsigned long len; /* Length of image */
- unsigned char *fn_buf; /* Start of filename string */
- unsigned int fn_len; /* Length of filename string */
- unsigned char *xcv_buf; /* Pointer to start of image */
- unsigned long xcv_len; /* Length of image */
- unsigned long crc; /* 30bit crc in image */
- unsigned long calc_crc; /* Calc'd 30bit crc */
- int retval = -1;
-
- /* Tell the world what we are doing */
- printf("FPGA: ");
-
- /*
- * Get address of first sector where the FPGA
- * image is stored.
- */
- buf = (unsigned char *) flash_info[1].start[0];
-
- /*
- * Get the stored image's CRC & length.
- */
- crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
- len = *(unsigned long *) (buf + 8); /* Image len is next long */
-
- /* Pedantic */
- if ((len < 0x133A4) || (len > 0x80000))
- goto bad_image;
-
- /*
- * Get the file name pointer and length.
- * filename length is next short
- */
- fn_len = (*(unsigned short *) (buf + 12) & 0xff);
- fn_buf = buf + 14;
-
- /*
- * Get the FPGA image pointer and length length.
- */
- xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
- xcv_len = len - 14 - fn_len; /* fpga image length */
-
- /* Check for uninitialized FLASH */
- if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
- || (len == 0))
- goto bad_image;
-
- /*
- * Calculate and Check the image's CRC.
- */
- calc_crc = crc32(0, xcv_buf, xcv_len);
- if (crc != calc_crc) {
- printf("\nfailed - bad CRC\n");
- goto done;
- }
-
- /* Output the file name */
- printf("file name : ");
- for (i = 0; i < fn_len; i++) {
- bufchar = fn_buf[+i];
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * find rest of display data
- */
- ptr = 15; /* Offset to ncd filename
- length in fpga image */
- j = xcv_buf[ptr]; /* Get len of ncd filename */
- if (j > 32)
- goto bad_image;
- ptr = ptr + j + 3; /* skip ncd filename string +
- 3 bytes more bytes */
-
- /*
- * output target device string
- */
- j = xcv_buf[ptr++] - 1; /* len of targ str less term */
- if (j > 32)
- goto bad_image;
- printf("\n target : ");
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * output compilation date string and time string
- */
- ptr += 3; /* skip 2 bytes */
- printf("\n synth time : ");
- j = (xcv_buf[ptr++] - 1); /* len of date str less term */
- if (j > 32)
- goto bad_image;
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- ptr += 3; /* Skip 2 bytes */
- printf(" - ");
- j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
- if (j > 32)
- goto bad_image;
- for (i = 0; i < j; i++) {
- bufchar = (xcv_buf[ptr++]);
- if (bufchar < ' ' || bufchar > '~')
- bufchar = '.';
- putc(bufchar);
- }
-
- /*
- * output crc and length strings
- */
- printf("\n len & crc : 0x%lx 0x%lx", len, crc);
-
- /*
- * Program the FPGA.
- */
- retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
- (unsigned short *) 0xfd000000L);
- return retval;
-
-bad_image:
- printf("\n BAD FPGA image format @ %lx\n",
- flash_info[1].start[0]);
- log_warn(ERR_XIMAGE);
-done:
- return retval;
-}
-
-void test_fpga(unsigned short *daddr)
-{
- int i;
- volatile unsigned short *ndest = daddr;
-
- for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
-#if defined(CONFIG_W7OLMG)
- ndest[0x7e] = 0x55aa;
- if (ndest[0x7e] != 0x55aa)
- log_warn(ERR_XRW1 + i);
- ndest[0x7e] = 0xaa55;
- if (ndest[0x7e] != 0xaa55)
- log_warn(ERR_XRW1 + i);
- ndest[0x7e] = 0xc318;
- if (ndest[0x7e] != 0xc318)
- log_warn(ERR_XRW1 + i);
-
-#elif defined(CONFIG_W7OLMC)
- ndest[0x800] = 0x55aa;
- ndest[0x801] = 0xaa55;
- ndest[0x802] = 0xc318;
- ndest[0x4800] = 0x55aa;
- ndest[0x4801] = 0xaa55;
- ndest[0x4802] = 0xc318;
- if ((ndest[0x800] != 0x55aa) ||
- (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
- log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
- if ((ndest[0x4800] != 0x55aa) ||
- (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
- log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
-
-#else
-#error "Unknown W7O board configuration"
-#endif
- }
-
- printf(" FPGA ready\n");
- return;
-}
diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c
deleted file mode 100644
index 8f4fe31..0000000
--- a/board/w7o/fsboot.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wave 7 Optics, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <elf.h>
-
-/*
- * FIXME: Add code to test image and it's header.
- */
-static int
-image_check(ulong addr)
-{
- return valid_elf_image(addr);
-}
-
-void
-init_fsboot(void)
-{
- char *envp;
- ulong loadaddr;
- ulong testaddr;
- ulong alt_loadaddr;
- char buf[9];
-
- /*
- * Get test image address
- */
- if ((envp = getenv("testaddr")) != NULL)
- testaddr = simple_strtoul(envp, NULL, 16);
- else
- testaddr = -1;
-
- /*
- * Are we going to test boot and image?
- */
- if ((testaddr != -1) && image_check(testaddr)) {
-
- /* Set alt_loadaddr */
- alt_loadaddr = testaddr;
- sprintf(buf, "%lX", alt_loadaddr);
- setenv("alt_loadaddr", buf);
-
- /* Clear test_addr */
- setenv("testaddr", NULL);
-
- /*
- * Save current environment with alt_loadaddr,
- * and cleared testaddr.
- */
- saveenv();
-
- /*
- * Setup temporary loadaddr to alt_loadaddr
- * XXX - DO NOT SAVE ENVIRONMENT!
- */
- loadaddr = alt_loadaddr;
- sprintf(buf, "%lX", loadaddr);
- setenv("loadaddr", buf);
-
- } else { /* Normal boot */
- setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */
- setenv("testaddr", NULL); /* Clear testaddr */
- saveenv();
- }
-
- return;
-}
diff --git a/board/w7o/init.S b/board/w7o/init.S
deleted file mode 100644
index dfde149..0000000
--- a/board/w7o/init.S
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/******************************************************************************
- * Function: ext_bus_cntlr_init
- *
- * Description: Configures EBC Controller and a few basic chip selects.
- *
- * CS0 is setup to get the Boot Flash out of the addresss range
- * so that we may setup a stack. CS7 is setup so that we can
- * access and reset the hardware watchdog.
- *
- * IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- *
- * Notes: Does NOT use the stack.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl ext_bus_cntlr_init
- .type ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
- mflr r0
- /********************************************************************
- * Prefetch entire ext_bus_cntrl_init function into the icache.
- * This is necessary because we are going to change the same CS we
- * are executing from. Otherwise a CPU lockup may occur.
- *******************************************************************/
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
-
- /* Calculate number of cache lines for this function */
- addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
- mtctr r4
-..ebcloop:
- icbt r0, r3 /* prefetch cache line for addr in r3*/
- addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
- bdnz ..ebcloop /* continue for $CTR cache lines */
-
- /********************************************************************
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings. 200usec should be enough.
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
- *******************************************************************/
- addis r3, 0, 0x0
- ori r3, r3, 0xA000 /* wait 200us from reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /********************************************************************
- * Setup External Bus Controller (EBC).
- *******************************************************************/
- addi r3, 0, EBC0_CFG
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
- ori r4, r4, 0x0 /* Drive CS with external master */
- mtdcr EBC0_CFGDATA, r4
-
- /********************************************************************
- * Change PCIINT signal to PerWE
- *******************************************************************/
- mfdcr r4, CPC0_CR1
- ori r4, r4, 0x4000
- mtdcr CPC0_CR1, r4
-
- /********************************************************************
- * Memory Bank 0 (Flash Bank 0) initialization
- *******************************************************************/
- addi r3, 0, PB1AP
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP at h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP at l
- mtdcr EBC0_CFGDATA, r4
-
- addi r3, 0, PB0CR
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR at h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR at l
- mtdcr EBC0_CFGDATA, r4
-
- /********************************************************************
- * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
- *******************************************************************/
- addi r3, 0, PB7AP
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP at h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP at l
- mtdcr EBC0_CFGDATA, r4
-
- addi r3, 0, PB7CR
- mtdcr EBC0_CFGADDR, r3
- addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR at h
- ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR at l
- mtdcr EBC0_CFGDATA, r4
-
- /* We are all done */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function: sdram_init
- *
- * Description: Configures SDRAM memory banks.
- *
- * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
- * via the IIC bus and then configures the SDRAM memory
- * banks appropriately. If Auto Memory Configuration is
- * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
- * SDRAM is soldered down.
- *
- * Notes: Expects that the stack is already setup.
- *****************************************************************************/
- .section ".text"
- .align 2
- .globl sdram_init
- .type sdram_init, @function
-sdram_init:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save link register */
-
- /*
- * First call spd_sdram to try to init SDRAM according to the
- * contents of the SPD EEPROM. If the SPD EEPROM is blank or
- * erronious, spd_sdram returns 0 in R3.
- */
- li r3,0
- bl spd_sdram
- addic. r3, r3, 0 /* Check for error, save dram size */
- bne ..sdri_done /* If it worked, we're done... */
-
- /********************************************************************
- * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
- * is the SMALLEST SDRAM size the 405 supports. We can do this
- * because W7O boards have soldered on RAM, and there will always
- * be some amount present. If we were using DIMMs, we should hang
- * the board instead, since it doesn't have any RAM to continue
- * running with.
- *******************************************************************/
-
- /*
- * Disable memory controller to allow
- * values to be changed.
- */
- addi r3, 0, SDRAM0_CFG
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0
- ori r4, r4, 0x0
- mtdcr SDRAM0_CFGDATA, r4
-
- /*
- * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
- * All other banks are disabled.
- */
- addi r3, 0, SDRAM0_B0CR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
- ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
- mtdcr SDRAM0_CFGDATA, r4
-
- /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
- addi r4, 0, 0 /* Zero the data reg */
-
- addi r3, r3, 4 /* Point to MB1CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- addi r3, r3, 4 /* Point to MB2CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- addi r3, r3, 4 /* Point to MB3CF reg */
- mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
- mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
-
- /********************************************************************
- * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- * To set the appropriate timings, we assume sdram is
- * 100MHz (pc100 compliant).
- *******************************************************************/
-
- /*
- * Set up SDTR1
- */
- addi r3, 0, SDRAM0_TR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
- ori r4, r4, 0x400D
- mtdcr SDRAM0_CFGDATA, r4
-
- /*
- * Set RTR
- */
- addi r3, 0, SDRAM0_RTR
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms at 100Mhz */
- mtdcr SDRAM0_CFGDATA, r4
-
- /********************************************************************
- * Delay to ensure 200usec have elapsed since reset. Assume worst
- * case that the core is running 200Mhz:
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- *******************************************************************/
- addis r3, 0, 0x0000
- ori r3, r3, 0xA000 /* Wait 200us from reset */
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 /* spin loop */
-
- /********************************************************************
- * Set memory controller options reg, MCOPT1.
- *******************************************************************/
- addi r3, 0, SDRAM0_CFG
- mtdcr SDRAM0_CFGADDR, r3
- addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
- ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
- mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
-
-..sdri_done:
- /* restore and return */
- lwz r0, +12(r1) /* Get saved link register */
- addi r1, r1, +8 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-.Lfe1: .size sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */
diff --git a/board/w7o/post1.S b/board/w7o/post1.S
deleted file mode 100644
index aae5387..0000000
--- a/board/w7o/post1.S
+++ /dev/null
@@ -1,724 +0,0 @@
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, william.hunter at mediaone.net
- * and
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * Description:
- * Routine to exercise memory for the bringing up of our boards.
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include <watchdog.h>
-
-#include "errors.h"
-
-#define _ASMLANGUAGE
-
- .globl test_sdram
- .globl test_led
- .globl log_stat
- .globl log_warn
- .globl log_err
- .globl temp_uart_init
- .globl post_puts
- .globl disp_hex
-
-/*****************************************************
-******* Text Strings for low level printing ******
-******* In section got2 *******
-*****************************************************/
-
-/*
- * Define the text strings for errors and warnings.
- * Switch to .data section.
- */
- .section ".data"
-err_str: .asciz "*** POST ERROR = "
-warn_str: .asciz "*** POST WARNING = "
-end_str: .asciz "\r\n"
-
-/*
- * Enter the labels in Global Entry Table (GOT).
- * Switch to .got2 section.
- */
- START_GOT
- GOT_ENTRY(err_str)
- GOT_ENTRY(warn_str)
- GOT_ENTRY(end_str)
- END_GOT
-
-/*
- * Switch back to .text section.
- */
- .text
-
-/****************************************
- ****************************************
- ******** LED register test ********
- ****************************************
- ***************************************/
-test_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- addi r3, 0, ERR_FF /* first test value is ffff */
- addi r4, r3, 0 /* save copy of pattern */
- bl set_led /* store first test value */
- bl get_led /* read it back */
- xor. r4, r4, r3 /* compare to original */
-#if defined(CONFIG_W7OLMC)
- andi. r4, r4, 0x00ff /* lmc has 8 bits */
-#else
- andi. r4, r4, 0xffff /* lmg has 16 bits */
-#endif
- beq LED2 /* next test */
- addi r3, 0, ERR_LED /* error code = 1 */
- bl log_err /* display error and halt */
-LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */
- addi r4, r3, 0 /* save copy of pattern */
- bl set_led /* store first test value */
- bl get_led /* read it back */
- xor. r4, r4, r3 /* compare to original */
-#if defined(CONFIG_W7OLMC)
- andi. r4, r4, 0x00ff /* lmc has 8 bits */
-#else
- andi. r4, r4, 0xffff /* lmg has 16 bits */
-#endif
- beq LED3 /* next test */
- addi r3, 0, ERR_LED /* error code = 1 */
- bl log_err /* display error and halt */
-
-LED3: /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/****************************************
- ****************************************
- ******** SDRAM TESTS ********
- ****************************************
- ***************************************/
-test_sdram:
- /* called with mem size in r3 */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stmw r30, +8(r1) /* save R30,R31 */
- /* r30 is log2(mem size) */
- /* r31 is mem size */
-
- /* take log2 of total mem size */
- addi r31, r3, 0 /* save total mem size */
- addi r30, 0, 0 /* clear r30 */
-l2_loop:
- srwi. r31, r31, 1 /* shift right 1 */
- addi r30, r30, 1 /* count shifts */
- bne l2_loop /* loop till done */
- addi r30, r30, -1 /* correct for over count */
- addi r31, r3, 0 /* save original size */
-
- /* now kick the dog and test the mem */
- WATCHDOG_RESET /* Reset the watchdog */
- bl Data_Buster /* test crossed/shorted data lines */
- addi r3, r30, 0 /* get log2(memsize) */
- addi r4, r31, 0 /* get memsize */
- bl Ghost_Buster /* test crossed/shorted addr lines */
- addi r3, r31, 0 /* get mem size */
- bl Bit_Buster /* check for bad internal bits */
-
- /* restore stack and return */
- lmw r30, +8(r1) /* Restore r30, r31 */
- lwz r0, +20(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +16 /* Remove frame from stack */
- blr /* Return to calling function */
-
-
-/****************************************
- ******** sdram data bus test ********
- ***************************************/
-Data_Buster:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -24(r1) /* Save back chain and move SP */
- stw r0, +28(r1) /* Save link register */
- stmw r28, 8(r1) /* save r28 - r31 on stack */
- /* r31 i/o register */
- /* r30 sdram base address */
- /* r29 5555 syndrom */
- /* r28 aaaa syndrom */
-
- /* set up led register for this test */
- addi r3, 0, ERR_RAMG /* set led code to 1 */
- bl log_stat /* store test value */
- /* now test the dram data bus */
- xor r30, r30, r30 /* load r30 with base addr of sdram */
- addis r31, 0, 0x5555 /* load r31 with test value */
- ori r31, r31, 0x5555
- stw r31,0(r30) /* sto the value */
- lwz r29,0(r30) /* read it back */
- xor r29,r31,r29 /* compare it to original */
- addis r31, 0, 0xaaaa /* load r31 with test value */
- ori r31, r31, 0xaaaa
- stw r31,0(r30) /* sto the value */
- lwz r28,0(r30) /* read it back */
- xor r28,r31,r28 /* compare it to original */
- or r3,r28,r29 /* or together both error terms */
- /*
- * Now that we have the error bits,
- * we have to decide which part they are in.
- */
- bl get_idx /* r5 is now index to error */
- addi r3, r3, ERR_RAMG
- cmpwi r3, ERR_RAMG /* check for errors */
- beq db_done /* skip if no errors */
- bl log_err /* log the error */
-
-db_done:
- lmw r28, 8(r1) /* restore r28 - r31 from stack */
- lwz r0, +28(r1) /* Get saved link register */
- addi r1, r1, +24 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******** test for address ghosting in dram ********
- ***************************************************/
-
-Ghost_Buster:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -36(r1) /* Save back chain and move SP */
- stw r0, +40(r1) /* Save link register */
- stmw r25, 8(r1) /* save r25 - r31 on stack */
- /* r31 = scratch register */
- /* r30 is main referance loop counter,
- 0 to 23 */
- /* r29 is ghost loop count, 0 to 22 */
- /* r28 is referance address */
- /* r27 is ghost address */
- /* r26 is log2 (mem size) =
- number of byte addr bits */
- /* r25 is mem size */
-
- /* save the log2(mem size) and mem size */
- addi r26, r3, 0 /* r26 is number of byte addr bits */
- addi r25, r4, 0 /* r25 is mem size in bytes */
-
- /* set the leds for address ghost test */
- addi r3, 0, ERR_ADDG
- bl set_led
-
- /* first fill memory with zeros */
- srwi r31, r25, 2 /* convert bytes to longs */
- mtctr r31 /* setup byte counter */
- addi r28, 0, 0 /* start at address at 0 */
- addi r31, 0, 0 /* data value = 0 */
-clr_loop:
- stw r31, 0(r28) /* Store zero value */
- addi r28, r28, 4 /* Increment to next word */
- andi. r27, r28, 0xffff /* check for 2^16 loops */
- bne clr_skip /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-clr_skip:
- bdnz clr_loop /* Round and round... */
-
- /* now do main test */
- addi r30, 0, 0 /* start referance counter at 0 */
-outside:
- /*
- * Calculate the referance address
- * the referance address is calculated by setting the (r30-1)
- * bit of the base address
- * when r30=0, the referance address is the base address.
- * thus the sequence 0,1,2,4,8,..,2^(n-1)
- * setting the bit is done with the following shift functions.
- */
- WATCHDOG_RESET /* Reset the watchdog */
-
- addi r31, 0, 1 /* r31 = 1 */
- slw r28, r31, r30 /* set bit coresponding to loop cnt */
- srwi r28, r28, 1 /* then shift it right one so */
- /* we start at location 0 */
- /* fill referance address with Fs */
- addi r31, 0, 0x00ff /* r31 = one byte of set bits */
- stb r31,0(r28) /* save ff in referance address */
-
- /* ghost (inner) loop, now check all posible ghosted addresses */
- addi r29, 0, 0 /* start ghosted loop counter at 0 */
-inside:
- /*
- * Calculate the ghost address by flipping one
- * bit of referance address. This gives the
- * sequence 1,2,4,8,...,2^(n-1)
- */
- addi r31, 0, 1 /* r31 = 1 */
- slw r27, r31, r29 /* set bit coresponding to loop cnt */
- xor r27, r28, r27 /* ghost address = ref addr with
- bit flipped*/
-
- /* now check for ghosting */
- lbz r31,0(r27) /* get content of ghost addr */
- cmpwi r31, 0 /* compare read value to 0 */
- bne Casper /* we found a ghost! */
-
- /* now close ghost ( inner ) loop */
- addi r29, r29, 1 /* increment inner loop counter */
- cmpw r29, r26 /* check for last inner loop */
- blt inside /* do more inner loops */
-
- /* now close referance ( outer ) loop */
- addi r31, 0, 0 /* r31 = zero */
- stb r31, 0(28) /* zero out the altered address loc. */
- /*
- * Increment and check for end, count is zero based.
- * With the ble, this gives us one more loops than
- * address bits for sequence 0,1,2,4,8,...2^(n-1)
- */
- addi r30, r30, 1 /* increment outer loop counter */
- cmpw r30, r26 /* check for last inner loop */
- ble outside /* do more outer loops */
-
- /* were done, lets go home */
- b gb_done
-Casper: /* we found a ghost !! */
- addi r3, 0, ERR_ADDF /* get indexed error message */
- bl log_err /* log error led error code */
-gb_done: /* pack your bags, and go home */
- lmw r25, 8(r1) /* restore r25 - r31 from stack */
- lwz r0, +40(r1) /* Get saved link register */
- addi r1, r1, +36 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-/****************************************************
- ******** SDRAM data fill tests **********
- ***************************************************/
-Bit_Buster:
- /* called with mem size in r3 */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
- stw r5, +12(r1) /* save r5 */
-
- addis r5, r3, 0 /* save mem size */
-
- /* Test 55555555 */
- addi r3, 0, ERR_R55G /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0x5555
- ori r4, r4, 0x5555
- bl fill_test
-
- /* Test aaaaaaaa */
- addi r3, 0, ERR_RAAG /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0xAAAA
- ori r4, r4, 0xAAAA
- bl fill_test
-
- /* Test 00000000 */
- addi r3, 0, ERR_R00G /* set up error code in case we fail */
- bl log_stat /* store test value */
- addis r4, 0, 0
- ori r4, r4, 0
- bl fill_test
-
- /* restore stack and return */
- lwz r5, +12(r1) /* restore r4 */
- lwz r4, +8(r1) /* restore r4 */
- lwz r0, +20(r1) /* Get saved link register */
- addi r1, r1, +16 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******** fill test ********
- ***************************************************/
-/* tests memory by filling with value, and reading back */
-/* r5 = Size of memory in bytes */
-/* r4 = Value to write */
-/* r3 = Error code */
-fill_test:
- mflr r0 /* Get link register */
- stwu r1, -32(r1) /* Save back chain and move SP */
- stw r0, +36(r1) /* Save link register */
- stmw r27, 8(r1) /* save r27 - r31 on stack */
- /* r31 - scratch register */
- /* r30 - memory address */
- mr r27, r3
- mr r28, r4
- mr r29, r5
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- /* first fill memory with Value */
- srawi r31, r29, 2 /* convert bytes to longs */
- mtctr r31 /* setup counter */
- addi r30, 0, 0 /* Make r30 = addr 0 */
-ft_0: stw r28, 0(r30) /* Store value */
- addi r30, r30, 4 /* Increment to next word */
- andi. r31, r30, 0xffff /* check for 2^16 loops */
- bne ft_0a /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-ft_0a: bdnz ft_0 /* Round and round... */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- /* Now confirm Value is in memory */
- srawi r31, r29, 2 /* convert bytes to longs */
- mtctr r31 /* setup counter */
- addi r30, 0, 0 /* Make r30 = addr 0 */
-ft_1: lwz r31, 0(r30) /* get value from memory */
- xor. r31, r31, r28 /* Writen = Read ? */
- bne ft_err /* If bad, than halt */
- addi r30, r30, 4 /* Increment to next word */
- andi. r31, r30, 0xffff /* check for 2^16 loops*/
- bne ft_1a /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
-ft_1a: bdnz ft_1 /* Round and round... */
-
- WATCHDOG_RESET /* Reset the watchdog */
-
- b fill_done /* restore and return */
-
-ft_err: addi r29, r27, 0 /* save current led code */
- addi r27, r31, 0 /* get pattern in r27 */
- bl get_idx /* get index from r27 */
- add r27, r27, r29 /* add index to old led code */
- bl log_err /* output led err code, halt CPU */
-
-fill_done:
- lmw r27, 8(r1) /* restore r27 - r31 from stack */
- lwz r0, +36(r1) /* Get saved link register */
- addi r1, r1, +32 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************
- ******* get error index from r3 pattern ********
- ***************************************************/
-get_idx: /* r3 = (MSW(r3) !=0)*2 +
- (LSW(r3) !=0) */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- andi. r4, r3, 0xffff /* check for lower bits */
- beq gi2 /* skip if no bits set */
- andis. r4, r3, 0xffff /* check for upper bits */
- beq gi3 /* skip if no bits set */
- addi r3, 0, 3 /* both upper and lower bits set */
- b gi_done
-gi2: andis. r4, r3, 0xffff /* check for upper bits*/
- beq gi4 /* skip if no bits set */
- addi r3, 0, 2 /* only upper bits set */
- b gi_done
-gi3: addi r3, 0, 1 /* only lower bits set */
- b gi_done
-gi4: addi r3, 0, 0 /* no bits set */
-gi_done:
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/****************************************************
- ******** set LED to R5 and hang ********
- ***************************************************/
-log_stat: /* output a led code and continue */
-set_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
-#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */
- xori r3,r3, 0xffff /* complement led code, active low */
- sth r3, 0(r4) /* store first test value */
- xori r3,r3, 0xffff /* complement led code, active low */
-#else /* if not gateway, then don't invert */
- sth r3, 0(r4) /* store first test value */
-#endif
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-get_led:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r4, +8(r1) /* save R4 */
-
- addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
- lhz r3, 0(r4) /* store first test value */
-#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */
- xori r3,r3, 0xffff /* complement led code, active low */
-#endif
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- lwz r4, +8(r1) /* restore r4 */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-log_err: /* output the error and hang the board ( for now ) */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r3, +8(r1) /* save a copy of error code */
- bl set_led /* set the led pattern */
- GET_GOT /* get GOT address in r14 */
- lwz r3,GOT(err_str) /* get address of string */
- bl post_puts /* output the warning string */
- lwz r3, +8(r1) /* get error code */
- addi r4, 0, 2 /* set disp length to 2 nibbles */
- bl disp_hex /* output the error code */
- lwz r3,GOT(end_str) /* get address of string */
- bl post_puts /* output the warning string */
-halt:
- b halt /* hang */
-
- /* restore stack and return */
- lwz r0, +16(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +12 /* Remove frame from stack */
- blr /* Return to calling function */
-
-log_warn: /* output a warning, then continue with operations */
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stw r3, +8(r1) /* save a copy of error code */
- stw r14, +12(r1) /* save a copy of r14 (used by GOT) */
-
- bl set_led /* set the led pattern */
- GET_GOT /* get GOT address in r14 */
- lwz r3,GOT(warn_str) /* get address of string */
- bl post_puts /* output the warning string */
- lwz r3, +8(r1) /* get error code */
- addi r4, 0, 2 /* set disp length to 2 nibbles */
- bl disp_hex /* output the error code */
- lwz r3,GOT(end_str) /* get address of string */
- bl post_puts /* output the warning string */
-
- addis r3, 0, 64 /* has a long delay */
- mtctr r3
-log_2:
- WATCHDOG_RESET /* this keeps dog from barking, */
- /* and takes time */
- bdnz log_2 /* loop till time expires */
-
- /* restore stack and return */
- lwz r0, +20(r1) /* Get saved link register */
- lwz r14, +12(r1) /* restore r14 */
- mtlr r0 /* Restore link register */
- addi r1, r1, +16 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/*******************************************************************
- * temp_uart_init
- * Temporary UART initialization routine
- * Sets up UART0 to run at 9600N81 off of the internal clock.
- * R3-R4 are used.
- ******************************************************************/
-temp_uart_init:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save link register */
-
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
- stb r4, 0(r3)
-
- /* set baud rate to use internal clock,
- baud = (200e6/16)/31/42 = 9600 */
-
- addis r3, 0, 0xef60 /* Address of baud divisor reg */
- ori r3, r3, 0x0300 /* UART0_DLM */
- addi r4, 0, +42 /* uart baud divisor LSB = 93 */
- stb r4, 0(r3) /* baud = (200 /16)/14/93 */
-
- addi r3, r3, 0x0001 /* uart baud divisor addr */
- addi r4, 0, 0
- stb r4, 0(r3) /* Divisor Latch MSB = 0 */
-
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
- stb r4, 0(r3)
-
- /* output a few line feeds */
- addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
- addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
-
- /* restore stack and return */
- lwz r0, +12(r1) /* Get saved link register */
- mtlr r0 /* Restore link register */
- addi r1, r1, +8 /* Remove frame from stack */
- blr /* Return to calling function */
-
-/**********************************************************************
- ** post_putc
- ** outputs charactor in R3
- ** r3 returns the error code ( -1 if there is an error )
- *********************************************************************/
-
-post_putc:
-
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -20(r1) /* Save back chain and move SP */
- stw r0, +24(r1) /* Save link register */
- stmw r29, 8(r1) /* save r29 - r31 on stack
- r31 - uart base address
- r30 - delay counter
- r29 - scratch reg */
-
- addis r31, 0, 0xef60 /* Point to uart base */
- ori r31, r31, 0x0300
- addis r30, 0, 152 /* Load about 10,000,000 ticks. */
-pputc_lp:
- lbz r29, 5(r31) /* Read Line Status Register */
- andi. r29, r29, 0x20 /* Check THRE status */
- bne thre_set /* Branch if FIFO empty */
- addic. r30, r30, -1 /* Decrement and check if empty. */
- bne pputc_lp /* Try, try again */
- addi r3, 0, -1 /* Load error code for timeout */
- b pputc_done /* Bail out with error code set */
-thre_set:
- stb r3, 0(r31) /* Store character to UART */
- addi r3, 0, 0 /* clear error code */
-pputc_done:
- lmw r29, 8(r1) /*restore r29 - r31 from stack */
- lwz r0, +24(r1) /* Get saved link register */
- addi r1, r1, +20 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/****************************************************************
- post_puts
- Accepts a null-terminated string pointed to by R3
- Outputs to the serial port until 0x00 is found.
- r3 returns the error code ( -1 if there is an error )
-*****************************************************************/
-post_puts:
-
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -12(r1) /* Save back chain and move SP */
- stw r0, +16(r1) /* Save link register */
- stw r31, 8(r1) /* save r31 - char pointer */
-
- addi r31, r3, 0 /* move pointer to R31 */
-pputs_nxt:
- lbz r3, 0(r31) /* Get next character */
- addic. r3, r3, 0 /* Check for zero */
- beq pputs_term /* bail out if zero */
- bl post_putc /* output the char */
- addic. r3, r3, 0 /* check for error */
- bne pputs_err
- addi r31, r31, 1 /* point to next char */
- b pputs_nxt /* loop till term */
-pputs_err:
- addi r3, 0, -1 /* set error code */
- b pputs_end /* were outa here */
-pputs_term:
- addi r3, 0, 1 /* set success code */
- /* restore stack and return */
-pputs_end:
- lwz r31, 8(r1) /* restore r27 - r31 from stack */
- lwz r0, +16(r1) /* Get saved link register */
- addi r1, r1, +12 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
-
-
-/********************************************************************
- ***** disp_hex
- ***** Routine to display a hex value from a register.
- ***** R3 is value to display
- ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word
- ***** Returns -1 in R3 if there is an error ( ie serial port hangs )
- ***** Returns 0 in R3 if no error
- *******************************************************************/
-disp_hex:
- /* save the return info on stack */
- mflr r0 /* Get link register */
- stwu r1, -16(r1) /* Save back chain and move SP */
- stw r0, +20(r1) /* Save link register */
- stmw r30, 8(r1) /* save r30 - r31 on stack */
- /* r31 output char */
- /* r30 uart base address */
- addi r30, 0, 8 /* Go through 8 nibbles. */
- addi r31, r3, 0
-pputh_nxt:
- rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */
- andi. r3, r31, 0x0f /* Get nibble. */
- addi r3, r3, 0x30 /* Add zero's ASCII code. */
- cmpwi r3, 0x03a
- blt pputh_out
- addi r3, r3, 0x07 /* 0x27 for lower case. */
-pputh_out:
- cmpw r30, r4
- bgt pputh_skip
- bl post_putc
- addic. r3, r3, 0 /* check for error */
- bne pputh_err
-pputh_skip:
- addic. r30, r30, -1
- bne pputh_nxt
- xor r3, r3, r3 /* Clear error code */
- b pputh_done
-pputh_err:
- addi r3, 0, -1 /* set error code */
-pputh_done:
- /* restore stack and return */
- lmw r30, 8(r1) /* restore r30 - r31 from stack */
- lwz r0, +20(r1) /* Get saved link register */
- addi r1, r1, +16 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
diff --git a/board/w7o/post2.c b/board/w7o/post2.c
deleted file mode 100644
index 76b6597..0000000
--- a/board/w7o/post2.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter at mediaone.net
- * and
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <rtc.h>
-#include "errors.h"
-#include "dtt.h"
-
-/* for LM75 DTT POST test */
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_SET 0x3
-
-#if defined(CONFIG_RTC_M48T35A)
-void rtctest(void)
-{
- volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9);
- struct rtc_time tmp;
-
- /* set up led code for RTC tests */
- log_stat(ERR_RTCG);
-
- /*
- * Do RTC battery test. The first write after power up
- * fails if battery is low.
- */
- *tchar = 0xaa;
- if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
- *tchar = 0x55; /* Reset test address */
-
- /*
- * Now lets check the validity of the values in the RTC.
- */
- rtc_get(&tmp);
- if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) |
- (tmp.tm_min < 0) | (tmp.tm_min > 59) |
- (tmp.tm_hour < 0) | (tmp.tm_hour > 23) |
- (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) |
- (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) |
- (tmp.tm_year < 2000) | (tmp.tm_year > 2500) |
- (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) {
- log_warn(ERR_RTCTIM);
- rtc_reset();
- }
-
- /*
- * Now lets do a check to see if the NV RAM is there.
- */
- *tchar = 0xaa;
- if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
- *tchar = 0x55; /* Reset test address */
-
-} /* rtctest() */
-#endif /* CONFIG_RTC_M48T35A */
-
-
-#ifdef CONFIG_DTT_LM75
-int dtt_test(int sensor)
-{
- short temp, trip, hyst;
-
- /* get values */
- temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
- trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
- hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
-
- /* check values */
- if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) ||
- (trip != CONFIG_SYS_DTT_MAX_TEMP) ||
- (temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP))
- return 1;
-
- return 0;
-} /* dtt_test() */
-#endif /* CONFIG_DTT_LM75 */
-
-/*****************************************/
-
-void post2(void)
-{
-#if defined(CONFIG_RTC_M48T35A)
- rtctest();
-#endif /* CONFIG_RTC_M48T35A */
-
-#ifdef CONFIG_DTT_LM75
- log_stat(ERR_TempG);
- if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
- if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
-#endif /* CONFIG_DTT_LM75 */
-} /* post2() */
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
deleted file mode 100644
index 5740efb..0000000
--- a/board/w7o/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c
deleted file mode 100644
index fbcc394..0000000
--- a/board/w7o/vpd.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#if defined(VXWORKS)
-#include <stdio.h>
-#include <string.h>
-#define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0
-extern char iicReadByte(char, char);
-extern ulong_t crc32(unsigned char *, unsigned long);
-#else
-#include <common.h>
-#endif
-
-#include "vpd.h"
-
-/*
- * vpd_reader() - reads VPD data from I2C EEPROMS.
- * returns pointer to buffer or NULL.
- */
-static unsigned char *vpd_reader(unsigned char *buf, unsigned dev_addr,
- unsigned off, unsigned count)
-{
- unsigned offset = off; /* Calculated offset */
-
- /*
- * The main board EEPROM contains
- * SDRAM SPD in the first 128 bytes,
- * so skew the offset.
- */
- if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
- offset += SDRAM_SPD_DATA_SIZE;
-
- /* Try to read the I2C EEPROM */
-#if defined(VXWORKS)
- {
- int i;
-
- for (i = 0; i < count; ++i)
- buf[i] = iicReadByte(dev_addr, offset + i);
- }
-#else
- if (eeprom_read(dev_addr, offset, buf, count)) {
- printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n",
- count, dev_addr, offset);
- return NULL;
- }
-#endif
-
- return buf;
-}
-
-
-/*
- * vpd_get_packet() - returns next VPD packet or NULL.
- */
-static vpd_packet_t *vpd_get_packet(vpd_packet_t * vpd_packet)
-{
- vpd_packet_t *packet = vpd_packet;
-
- if (packet != NULL) {
- if (packet->identifier == VPD_PID_TERM)
- return NULL;
- else
- packet = (vpd_packet_t *) ((char *) packet +
- packet->size + 2);
- }
-
- return packet;
-}
-
-
-/*
- * vpd_find_packet() - Locates and returns the specified
- * VPD packet or NULL on error.
- */
-static vpd_packet_t *vpd_find_packet(vpd_t * vpd, unsigned char ident)
-{
- vpd_packet_t *packet = (vpd_packet_t *) &vpd->packets;
-
- /* Guaranteed illegal */
- if (ident == VPD_PID_GI)
- return NULL;
-
- /* Scan tuples looking for a match */
- while ((packet->identifier != ident) &&
- (packet->identifier != VPD_PID_TERM))
- packet = vpd_get_packet(packet);
-
- /* Did we find it? */
- if ((packet->identifier) && (packet->identifier != ident))
- return NULL;
- return packet;
-}
-
-
-/*
- * vpd_is_valid() - Validates contents of VPD data
- * in I2C EEPROM. Returns 1 for
- * success or 0 for failure.
- */
-static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
-{
- unsigned num_bytes;
- vpd_packet_t *packet;
- vpd_t *vpd = (vpd_t *) buf;
- unsigned short stored_crc16, calc_crc16 = 0xffff;
-
- /* Check Eyecatcher */
- if (strncmp
- ((char *) (vpd->header.eyecatcher), VPD_EYECATCHER,
- VPD_EYE_SIZE) != 0) {
- unsigned offset = 0;
-
- if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
- offset += SDRAM_SPD_DATA_SIZE;
- printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr,
- offset);
-
- return 0;
- }
-
- /* Check Length */
- if (vpd->header.size > VPD_MAX_EEPROM_SIZE) {
- printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n",
- dev_addr, vpd->header.size);
- return 0;
- }
-
- /* Now find the termination packet */
- packet = vpd_find_packet(vpd, VPD_PID_TERM);
- if (packet == NULL) {
- printf("Error: VPD EEPROM 0x%x missing termination packet\n",
- dev_addr);
- return 0;
- }
-
- /* Calculate data size */
- num_bytes = (unsigned long) ((unsigned char *) packet -
- (unsigned char *) vpd +
- sizeof(vpd_packet_t));
-
- /* Find stored CRC and clear it */
- packet = vpd_find_packet(vpd, VPD_PID_CRC);
- if (packet == NULL) {
- printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr);
- return 0;
- }
- memcpy(&stored_crc16, packet->data, sizeof(ushort));
- memset(packet->data, 0, sizeof(ushort));
-
- /* OK, lets calculate the CRC and check it */
-#if defined(VXWORKS)
- calc_crc16 = (0xffff & crc32(buf, num_bytes));
-#else
- calc_crc16 = (0xffff & crc32(0, buf, num_bytes));
-#endif
- /* Now restore the CRC */
- memcpy(packet->data, &stored_crc16, sizeof(ushort));
- if (stored_crc16 != calc_crc16) {
- printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n",
- dev_addr, stored_crc16);
- return 0;
- }
-
- return 1;
-}
-
-
-/*
- * size_ok() - Check to see if packet size matches
- * size of data we want. Returns 1 for
- * good match or 0 for failure.
- */
-static int size_ok(vpd_packet_t *packet, unsigned long size)
-{
- if (packet->size != size) {
- printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
- return 0;
- }
- return 1;
-}
-
-
-/*
- * strlen_ok() - Check to see if packet size matches
- * strlen of the string we want to populate.
- * Returns 1 for valid length or 0 for failure.
- */
-static int strlen_ok(vpd_packet_t *packet, unsigned long length)
-{
- if (packet->size >= length) {
- printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
- return 0;
- }
- return 1;
-}
-
-
-/*
- * get_vpd_data() - populates the passed VPD structure 'vpdInfo'
- * with data obtained from the specified
- * I2C EEPROM 'dev_addr'. Returns 0 for
- * success or 1 for failure.
- */
-int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
-{
- unsigned char buf[VPD_EEPROM_SIZE];
- vpd_t *vpd = (vpd_t *) buf;
- vpd_packet_t *packet;
-
- if (vpdInfo == NULL)
- return 1;
-
- /*
- * Fill vpdInfo with 0s to blank out
- * unused fields, fill vpdInfo->ethAddrs
- * with all 0xffs so that other's code can
- * determine how many real Ethernet addresses
- * there are. OUIs starting with 0xff are
- * broadcast addresses, and would never be
- * permantely stored.
- */
- memset((void *) vpdInfo, 0, sizeof(VPD));
- memset((void *) &vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs));
- vpdInfo->_devAddr = dev_addr;
-
- /* Read the minimum size first */
- if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL)
- return 1;
-
- /* Check validity of VPD data */
- if (!vpd_is_valid(dev_addr, buf)) {
- printf("VPD Data is INVALID!\n");
- return 1;
- }
-
- /*
- * Walk all the packets and populate
- * the VPD info structure.
- */
- packet = (vpd_packet_t *) &vpd->packets;
- do {
- switch (packet->identifier) {
- case VPD_PID_GI:
- printf("Error: Illegal VPD value\n");
- break;
- case VPD_PID_PID:
- if (strlen_ok(packet, MAX_PROD_ID)) {
- strncpy(vpdInfo->productId,
- (char *) (packet->data),
- packet->size);
- }
- break;
- case VPD_PID_REV:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->revisionId = *packet->data;
- break;
- case VPD_PID_SN:
- if (size_ok(packet, sizeof(unsigned long))) {
- memcpy(&vpdInfo->serialNum,
- packet->data,
- sizeof(unsigned long));
- }
- break;
- case VPD_PID_MANID:
- if (size_ok(packet, sizeof(unsigned char)))
- vpdInfo->manuID = *packet->data;
- break;
- case VPD_PID_PCO:
- if (size_ok(packet, sizeof(unsigned long))) {
- memcpy(&vpdInfo->configOpt,
- packet->data,
- sizeof(unsigned long));
- }
- break;
- case VPD_PID_SYSCLK:
- if (size_ok(packet, sizeof(unsigned long)))
- memcpy(&vpdInfo->sysClk,
- packet->data,
- sizeof(unsigned long));
- break;
- case VPD_PID_SERCLK:
- if (size_ok(packet, sizeof(unsigned long)))
- memcpy(&vpdInfo->serClk,
- packet->data,
- sizeof(unsigned long));
- break;
- case VPD_PID_FLASH:
- if (size_ok(packet, 9)) { /* XXX - hardcoded,
- padding in struct */
- memcpy(&vpdInfo->flashCfg, packet->data, 9);
- }
- break;
- case VPD_PID_ETHADDR:
- memcpy(vpdInfo->ethAddrs, packet->data, packet->size);
- break;
- case VPD_PID_POTS:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->numPOTS = (unsigned) *packet->data;
- break;
- case VPD_PID_DS1:
- if (size_ok(packet, sizeof(char)))
- vpdInfo->numDS1 = (unsigned) *packet->data;
- case VPD_PID_GAL:
- case VPD_PID_CRC:
- case VPD_PID_TERM:
- break;
- default:
- printf("Warning: Found unknown VPD packet ID 0x%x\n",
- packet->identifier);
- break;
- }
- } while ((packet = vpd_get_packet(packet)));
-
- return 0;
-}
-
-
-/*
- * vpd_init() - Initialize default VPD environment
- */
-int vpd_init(unsigned char dev_addr)
-{
- return 0;
-}
-
-
-/*
- * vpd_print() - Pretty print the VPD data.
- */
-void vpd_print(VPD *vpdInfo)
-{
- const char *const sp = "";
- const char *const sfmt = "%4s%-20s: \"%s\"\n";
- const char *const cfmt = "%4s%-20s: '%c'\n";
- const char *const dfmt = "%4s%-20s: %ld\n";
- const char *const hfmt = "%4s%-20s: %08lX\n";
- const char *const dsfmt = "%4s%-20s: %d\n";
- const char *const hsfmt = "%4s%-20s: %04X\n";
- const char *const dhfmt = "%4s%-20s: %ld (%lX)\n";
-
- printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr);
-
- if (vpdInfo->productId[0])
- printf(sfmt, sp, "Product ID", vpdInfo->productId);
- else
- printf(sfmt, sp, "Product ID", "UNKNOWN");
-
- if (vpdInfo->revisionId)
- printf(cfmt, sp, "Revision ID", vpdInfo->revisionId);
-
- if (vpdInfo->serialNum)
- printf(dfmt, sp, "Serial Number", vpdInfo->serialNum);
-
- if (vpdInfo->manuID)
- printf(dfmt, sp, "Manufacture ID", (long) vpdInfo->manuID);
-
- if (vpdInfo->configOpt)
- printf(hfmt, sp, "Configuration", vpdInfo->configOpt);
-
- if (vpdInfo->sysClk)
- printf(dhfmt, sp, "System Clock", vpdInfo->sysClk,
- vpdInfo->sysClk);
-
- if (vpdInfo->serClk)
- printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk,
- vpdInfo->serClk);
-
- if (vpdInfo->numPOTS)
- printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS);
-
- if (vpdInfo->numDS1)
- printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1);
-
- /* Print Ethernet Addresses */
- if (vpdInfo->ethAddrs[0][0] != 0xff) {
- int i, j;
-
- printf("%4sEtherNet Address(es): ", sp);
- for (i = 0; i < MAX_ETH_ADDRS; i++) {
- if (vpdInfo->ethAddrs[i][0] != 0xff) {
- for (j = 0; j < 6; j++) {
- printf("%02X",
- vpdInfo->ethAddrs[i][j]);
- if (((j + 1) % 6) != 0)
- printf(":");
- else
- printf(" ");
- }
- if (((i + 1) % 3) == 0)
- printf("\n%24s: ", sp);
- }
- }
- printf("\n");
- }
-
- if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) {
- printf("Main Flash Configuration:\n");
- printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg);
- printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev);
- printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth);
- printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs);
- printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols);
- printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth);
- printf(dsfmt, sp, "WE Data Width",
- vpdInfo->flashCfg.weDataWidth);
- }
-}
diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h
deleted file mode 100644
index 2395b18..0000000
--- a/board/w7o/vpd.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _VPD_H_
-#define _VPD_H_
-
-/*
- * Main Flash Configuration.
- */
-typedef struct flashCfg_s {
- unsigned short mfg; /* Manufacture ID */
- unsigned short dev; /* Device ID */
- unsigned char devWidth; /* Device Width */
- unsigned char numDevs; /* Number of devices */
- unsigned char numCols; /* Number of columns */
- unsigned char colWidth; /* Width of a column */
- unsigned char weDataWidth; /* Write/Erase Data Width */
-} flashCfg_t;
-
-/*
- * Vital Product Data - VPD
- */
-#define MAX_PROD_ID 15
-#define MAX_ETH_ADDRS 10
-typedef unsigned char EthAddr[6];
-typedef struct vpd {
- unsigned char _devAddr; /* Device address during read */
- char productId[MAX_PROD_ID]; /* Product ID */
- char revisionId; /* Revision ID as a char */
- unsigned long serialNum; /* Serial number */
- unsigned char manuID; /* Manufact ID - byte int */
- unsigned long configOpt; /* Config Option - bit field */
- unsigned long sysClk; /* System clock in Hertz */
- unsigned long serClk; /* Ext. clock in Hertz */
- flashCfg_t flashCfg; /* Flash configuration */
- unsigned long numPOTS; /* Number of POTS lines */
- unsigned long numDS1; /* Number of DS1 circuits */
- EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */
-} VPD;
-
-
-#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */
-#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */
-
-/*
- * PIDs - Packet Identifiers
- */
-#define VPD_PID_GI 0x0 /* Guaranted Illegal */
-#define VPD_PID_PID 0x1 /* Product Identifier */
-#define VPD_PID_REV 0x2 /* Product Revision */
-#define VPD_PID_SN 0x3 /* Serial Number */
-#define VPD_PID_MANID 0x4 /* Manufacture ID */
-#define VPD_PID_PCO 0x5 /* Product configuration */
-#define VPD_PID_SYSCLK 0x6 /* System Clock */
-#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */
-#define VPD_PID_CRC 0x8 /* VPD CRC */
-#define VPD_PID_FLASH 0x9 /* Flash Configuration */
-#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */
-#define VPD_PID_GAL 0xB /* Galileo Switch Config */
-#define VPD_PID_POTS 0xC /* Number of POTS Lines */
-#define VPD_PID_DS1 0xD /* Number of DS1s */
-#define VPD_PID_TERM 0xFF /* Termination packet */
-
-/*
- * VPD - Eyecatcher/Magic
- */
-#define VPD_EYECATCHER "W7O"
-#define VPD_EYE_SIZE 3
-typedef struct vpd_header {
- unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */
- unsigned short size __attribute__((packed)); /* size of EEPROM */
-} vpd_header_t;
-
-
-#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \
- sizeof(vpd_header_t))
-typedef struct vpd_s {
- vpd_header_t header;
- unsigned char packets[VPD_DATA_SIZE];
-} vpd_t;
-
-typedef struct vpd_packet {
- unsigned char identifier;
- unsigned char size;
- unsigned char data[1];
-} vpd_packet_t;
-
-/*
- * VPD configOpt bit mask
- */
-#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */
-#define VPD_HAS_RTC 0x2 /* Battery backed RTC */
-#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */
-#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */
-#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */
-#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */
-#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */
-#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */
-#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */
-#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */
-#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */
-#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */
-#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */
-#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */
-#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */
-#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */
-#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */
-
-#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */
-
-extern int vpd_get_data(unsigned char dev_addr, VPD *vpd);
-extern void vpd_print(VPD *vpdInfo);
-
-#endif /* _VPD_H_ */
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
deleted file mode 100644
index afbbaf5..0000000
--- a/board/w7o/w7o.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include "w7o.h"
-#include <asm/processor.h>
-
-#include "vpd.h"
-#include "errors.h"
-#include <watchdog.h>
-
-unsigned long get_dram_size (void);
-void sdram_init(void);
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
-#if defined(CONFIG_W7OLMG)
- /*
- * Setup GPIO pins - reset devices.
- */
- out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
-
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
- INT0 highest priority */
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
-#elif defined(CONFIG_W7OLMC)
- /*
- * Setup GPIO pins
- */
- out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
- out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
-
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
- INT0 highest priority */
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
-#else /* Unknown */
-# error "Unknown W7O board configuration"
-#endif
-
- WATCHDOG_RESET (); /* Reset the watchdog */
- temp_uart_init (); /* init the uart for debug */
- WATCHDOG_RESET (); /* Reset the watchdog */
- test_led (); /* test the LEDs */
- test_sdram (get_dram_size ()); /* test the dram */
- log_stat (ERR_POST1); /* log status,post1 complete */
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- VPD vpd;
-
- puts ("Board: ");
-
- /* VPD data present in I2C EEPROM */
- if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
- /*
- * Known board type.
- */
- if (vpd.productId[0] &&
- ((strncmp (vpd.productId, "GMM", 3) == 0) ||
- (strncmp (vpd.productId, "CMM", 3) == 0))) {
-
- /* Output board information on startup */
- printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
- return (0);
- }
- }
-
- puts ("### Unknown HW ID - assuming NOTHING\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- /*
- * ToDo: Move the asm init routine sdram_init() to this C file,
- * or even better use some common ppc4xx code available
- * in arch/powerpc/cpu/ppc4xx
- */
- sdram_init();
-
- return get_dram_size ();
-}
-
-unsigned long get_dram_size (void)
-{
- int tmp, i, regs[4];
- int size = 0;
-
- /* Get bank Size registers */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
- regs[0] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
- regs[1] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
- regs[2] = mfdcr (SDRAM0_CFGDATA);
-
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
- regs[3] = mfdcr (SDRAM0_CFGDATA);
-
- /* compute the size, add each bank if enabled */
- for (i = 0; i < 4; i++) {
- if (regs[i] & 0x0001) { /* if enabled, */
- tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
- tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
- size += tmp;
- }
- }
-
- return size;
-}
-
-int misc_init_f (void)
-{
- return 0;
-}
-
-static void w7o_env_init (VPD * vpd)
-{
- /*
- * Read VPD
- */
- if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
- return;
-
- /*
- * Known board type.
- */
- if (vpd->productId[0] &&
- ((strncmp (vpd->productId, "GMM", 3) == 0) ||
- (strncmp (vpd->productId, "CMM", 3) == 0))) {
- char buf[30];
- char *eth;
- char *serial = getenv ("serial#");
- char *ethaddr = getenv ("ethaddr");
-
- /* Set 'serial#' envvar if serial# isn't set */
- if (!serial) {
- sprintf (buf, "%s-%ld", vpd->productId,
- vpd->serialNum);
- setenv ("serial#", buf);
- }
-
- /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = (char *)(vpd->ethAddrs[0]);
- if (ethaddr
- && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
- /* Now setup ethaddr */
- sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
- eth[0], eth[1], eth[2], eth[3], eth[4],
- eth[5]);
- setenv ("ethaddr", buf);
- }
- }
-} /* w7o_env_init() */
-
-
-int misc_init_r (void)
-{
- VPD vpd; /* VPD information */
-
-#if defined(CONFIG_W7OLMG)
- unsigned long greg; /* GPIO Register */
-
- greg = in32 (PPC405GP_GPIO0_OR);
-
- /*
- * XXX - Unreset devices - this should be moved into VxWorks driver code
- */
- greg |= 0x41800000L; /* SAM, PHY, Galileo */
-
- out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
-#endif /* CONFIG_W7OLMG */
-
- /*
- * Initialize W7O environment variables
- */
- w7o_env_init (&vpd);
-
- /*
- * Initialize the FPGA(s).
- */
- if (init_fpga () == 0)
- test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
-
- /* More POST testing. */
- post2 ();
-
- /* Done with hardware initialization and POST. */
- log_stat (ERR_POSTOK);
-
- /* Call silly, fail safe boot init routine */
- init_fsboot ();
-
- return (0);
-}
diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h
deleted file mode 100644
index 9ef682c..0000000
--- a/board/w7o/w7o.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _W7O_H_
-#define _W7O_H_
-#include <config.h>
-
-/* AMCC 405GP PowerPC GPIO registers */
-#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
-#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
-#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
-#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
-
-/* LMG FPGA <=> CPU GPIO signals */
-#define LMG_XCV_INIT 0x10000000L
-#define LMG_XCV_PROG 0x04000000L
-#define LMG_XCV_DONE 0x00400000L
-#define LMG_XCV_CNFG_0 0x08000000L
-#define LMG_XCV_IRQ_0 0x0L
-
-/* LMC FPGA <=> CPU GPIO signals */
-#define LMC_XCV_INIT 0x00800000L
-#define LMC_XCV_PROG 0x40000000L
-#define LMC_XCV_DONE 0x01000000L
-#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
-#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
-#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
-#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
-#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
-#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
-
-
-/*
- * Setup FPGA <=> GPIO mappings
- */
-#if defined(CONFIG_W7OLMG)
-# define GPIO_XCV_INIT LMG_XCV_INIT
-# define GPIO_XCV_PROG LMG_XCV_PROG
-# define GPIO_XCV_DONE LMG_XCV_DONE
-# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
-# define GPIO_GPIO_1 0x40000000L
-# define GPIO_GPIO_6 0x02000000L
-# define GPIO_GPIO_7 0x01000000L
-# define GPIO_GPIO_8 0x00800000L
-#elif defined(CONFIG_W7OLMC)
-# define GPIO_XCV_INIT LMC_XCV_INIT
-# define GPIO_XCV_PROG LMC_XCV_PROG
-# define GPIO_XCV_DONE LMC_XCV_DONE
-# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
-# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
-#else
-# error "Unknown W7O board configuration"
-#endif
-
-/* Power On Self Tests */
-extern void post2(void);
-extern int test_led(void);
-extern int test_sdram(unsigned long size);
-extern void test_fpga(unsigned short *daddr);
-
-/* FGPA */
-extern int init_fpga(void);
-
-/* Misc */
-extern int temp_uart_init(void);
-extern void init_fsboot(void);
-
-#endif /* _W7O_H_ */
diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c
deleted file mode 100644
index ff1b212..0000000
--- a/board/w7o/watchdog.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * W7O board level hardware watchdog.
- */
-#include <common.h>
-#include <config.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-
-void hw_watchdog_reset(void)
-{
- volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000);
-
- /*
- * Read the LMG's hwd register and toggle the
- * watchdog bit to reset it. On the LMC, just
- * reading it is enough, but toggling the bit
- * doen't hurt either.
- */
- *hwd = *hwd ^ 0x8000;
-
-} /* hw_watchdog_reset() */
-
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/configs/W7OLMC_defconfig b/configs/W7OLMC_defconfig
deleted file mode 100644
index 573427b..0000000
--- a/configs/W7OLMC_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_W7OLMC=y
diff --git a/configs/W7OLMG_defconfig b/configs/W7OLMG_defconfig
deleted file mode 100644
index 7410124..0000000
--- a/configs/W7OLMG_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_W7OLMG=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index e3c4e2c..c416f3a 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
+W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
aev powerpc mpc5xxx - -
TB5200 powerpc mpc5xxx - -
JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
deleted file mode 100644
index 895ad46..0000000
--- a/include/configs/W7OLMC.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
-#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR F0080000
-
-#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.2
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_REGINFO
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
-
-#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
-#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 384000
-
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE {9600}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-/* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
-#undef CONFIG_USE_PERWE
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB1AP 0x05850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB2AP 0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB2CR 0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB3AP 0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
-
-/* bank 4 is FPGA 1 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB4AP 0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB4CR 0xFD11A000
-
-/* bank 5 is FPGA 2 */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB5AP 0x02000400
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB5CR 0xFD21A000
-
-/* bank 6 is unused */
-/* PB6AP = 0 */
-#define CONFIG_SYS_EBC_PB6AP 0x00000000
-/* PB6CR = 0 */
-#define CONFIG_SYS_EBC_PB6CR 0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-/*define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
-#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
-#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
-#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
-#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
deleted file mode 100644
index 2a38116..0000000
--- a/include/configs/W7OLMG.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen at mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
-#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADADDR F0080000
-
-#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden@boot */
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.2
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DTT
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
-
-#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
-#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
-#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#endif
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD 384000
-
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE {9600}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-/* resource configuration */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Set up values for external bus controller
- * used by cpu_init.c
- *-----------------------------------------------------------------------
- */
- /* use PerWE instead of PCI_INT ( these functions share a pin ) */
-#define CONFIG_USE_PERWE 1
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* bank 0 is boot flash */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
-/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
-
-/* bank 1 is main flash */
-/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB1AP 0x04850240
-/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
-#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
-
-/* bank 2 is RTC/NVRAM */
-/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_EBC_PB2AP 0x03000440
-/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB2CR 0xFC018000
-
-/* bank 3 is FPGA 0 */
-/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB3AP 0x02000400
-/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
-
-/* bank 4 is SAM 8 bit range */
-/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
-#define CONFIG_SYS_EBC_PB4AP 0x02840380
-/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
-#define CONFIG_SYS_EBC_PB4CR 0xFE878000
-
-/* bank 5 is SAM 16 bit range */
-/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
-#define CONFIG_SYS_EBC_PB5AP 0x05040d80
-/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
-#define CONFIG_SYS_EBC_PB5CR 0xFD87A000
-
-/* bank 6 is unused */
-/* PB6AP = 0 */
-#define CONFIG_SYS_EBC_PB6AP 0x00000000
-/* PB6CR = 0 */
-#define CONFIG_SYS_EBC_PB6CR 0x00000000
-
-/* bank 7 is LED register */
-/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
-/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
-#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-/*define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-
-#else /* Use Boot Flash for environment variables */
-/*-----------------------------------------------------------------------
- * Flash EEPROM for environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (ATMEL 24C04N)
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-
-/*
- * Init Memory Controller:
- */
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * FPGA(s) configuration
- */
-#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
-#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
-#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
-#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
-#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 5/7] powerpc: mpc5xxx: remove galaxy5200 board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
` (3 preceding siblings ...)
2015-03-17 3:28 ` [U-Boot] [PATCH 4/7] powerpc: ppc4xx: remove W7OLMC/W7OLMG " Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 6/7] powerpc: ppc4xx: remove korat " Masahiro Yamada
` (2 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
arch/powerpc/cpu/mpc5xxx/Kconfig | 4 -
board/galaxy5200/Kconfig | 9 -
board/galaxy5200/MAINTAINERS | 7 -
board/galaxy5200/Makefile | 8 -
board/galaxy5200/galaxy5200.c | 185 ---------------
configs/galaxy5200_LOWBOOT_defconfig | 4 -
configs/galaxy5200_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/galaxy5200.h | 431 -----------------------------------
9 files changed, 1 insertion(+), 652 deletions(-)
delete mode 100644 board/galaxy5200/Kconfig
delete mode 100644 board/galaxy5200/MAINTAINERS
delete mode 100644 board/galaxy5200/Makefile
delete mode 100644 board/galaxy5200/galaxy5200.c
delete mode 100644 configs/galaxy5200_LOWBOOT_defconfig
delete mode 100644 configs/galaxy5200_defconfig
delete mode 100644 include/configs/galaxy5200.h
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index e2d48f3..eec9d7d 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -20,9 +20,6 @@ config TARGET_CANMB
config TARGET_CM5200
bool "Support cm5200"
-config TARGET_GALAXY5200
- bool "Support galaxy5200"
-
config TARGET_INKA4X0
bool "Support inka4x0"
@@ -77,7 +74,6 @@ source "board/a3m071/Kconfig"
source "board/a4m072/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/galaxy5200/Kconfig"
source "board/ifm/o2dnt2/Kconfig"
source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
diff --git a/board/galaxy5200/Kconfig b/board/galaxy5200/Kconfig
deleted file mode 100644
index 3103581..0000000
--- a/board/galaxy5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GALAXY5200
-
-config SYS_BOARD
- default "galaxy5200"
-
-config SYS_CONFIG_NAME
- default "galaxy5200"
-
-endif
diff --git a/board/galaxy5200/MAINTAINERS b/board/galaxy5200/MAINTAINERS
deleted file mode 100644
index 614625d..0000000
--- a/board/galaxy5200/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-GALAXY5200 BOARD
-#M: Eric Millbrandt <emillbrandt@dekaresearch.com>
-S: Orphan (since 2014-06)
-F: board/galaxy5200/
-F: include/configs/galaxy5200.h
-F: configs/galaxy5200_defconfig
-F: configs/galaxy5200_LOWBOOT_defconfig
diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile
deleted file mode 100644
index e0fcd39..0000000
--- a/board/galaxy5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := galaxy5200.o
diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c
deleted file mode 100644
index 5d957b7..0000000
--- a/board/galaxy5200/galaxy5200.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
- volatile struct mpc5xxx_cdm *cdm =
- (struct mpc5xxx_cdm *)MPC5XXX_CDM;
- volatile struct mpc5xxx_sdram *sdram =
- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
- /* precharge all banks */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
- /* set mode register: extended mode */
- out_be32 (&sdram->mode, (SDRAM_EMODE));
-
- /* set mode register: reset DLL */
- out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
-#endif
-
- /* precharge all banks */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
- /* auto refresh */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
- /* set mode register */
- out_be32 (&sdram->mode, (SDRAM_MODE));
-
- /* normal operation */
- out_be32 (&sdram->ctrl,
- (SDRAM_CONTROL | hi_addr_bit));
-
- /* set CDM clock enable register, set MPC5200B SDRAM bus */
- /* to reduced driver strength */
- out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make
- * real use of CONFIG_SYS_SDRAM_BASE. The code does not
- * work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- volatile struct mpc5xxx_mmap_ctl *mm =
- (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
- volatile struct mpc5xxx_sdram *sdram =
- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- /* 256MB at 0x0 */
- out_be32 (&mm->sdram0, 0x0000001b);
- /* disabled */
- out_be32 (&mm->sdram1, 0x10000000);
-
- /* setup config registers */
- out_be32 (&sdram->config1, SDRAM_CONFIG1);
- out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else
- dramsize = test2;
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- out_be32 (&mm->sdram0,
- (0x13 + __builtin_ffs(dramsize >> 20) - 1));
- } else {
- /* disabled */
- out_be32 (&mm->sdram0, 0);
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = in_be32(&mm->sdram0) & 0xFF;
- if (dramsize >= 0x13)
- dramsize = (1 << (dramsize - 0x13)) << 20;
- else
- dramsize = 0;
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = in_be32(&mm->sdram1) & 0xFF;
- if (dramsize2 >= 0x13)
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- else
- dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
-
-int checkboard(void)
-{
- puts("Board: galaxy5200\n");
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
- debug ("init_ide_reset\n");
-
- /* Configure TIMER_5 as GPIO output for ATA reset */
- /* Deassert reset */
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
-}
-
-void ide_set_reset (int idereset)
-{
- volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
- debug ("ide_reset(%d)\n", idereset);
-
- /* Configure TIMER_5 as GPIO output for ATA reset */
- if (idereset) {
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
-
- /* Make a delay. MPC5200 spec says 25 usec min */
- udelay(50);
- } else {
- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
- udelay(50);
- }
-}
-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/configs/galaxy5200_LOWBOOT_defconfig b/configs/galaxy5200_LOWBOOT_defconfig
deleted file mode 100644
index 4f193f5..0000000
--- a/configs/galaxy5200_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200_LOWBOOT"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
diff --git a/configs/galaxy5200_defconfig b/configs/galaxy5200_defconfig
deleted file mode 100644
index 0fdf643..0000000
--- a/configs/galaxy5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index c416f3a..1f2320b 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
aev powerpc mpc5xxx - -
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
deleted file mode 100644
index b555d82..0000000
--- a/include/configs/galaxy5200.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messatechnik GmbH
- *
- * (C) Copyright 2009
- * Jon Smirl <jonsmirl@gmail.com>
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_BOARDINFO "galaxy5200"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFE000000 boot low
- * 0x00100000 boot from RAM (for testing only) does not work
- */
-#ifdef CONFIG_galaxy5200_LOWBOOT
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
- /* define gps port conf. */
- /* register later on to */
- /* enable UART function! */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
-
-#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-/* RAMBOOT will be defined automatically in memory section */
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
- "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
- /* even with bootdelay=0 */
-#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to U-Boot;"\
- "echo"
-
-#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
- "bootm ff040000 ff900000 fffc0000"
-#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
-#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#define CONFIG_SYS_XLB_PIPELINING 1
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
-
-/*
- * EEPROM CAT24WC32 configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
-#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_SIZE 4096
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xfe000000
-/*
- * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
- * variable defined
- */
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
- /* (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Use hardware protection. This seems required, as the BDI uses hardware
- * protection. Without this, U-Boot can't work with this sectors as its
- * protection is software only by default.
- */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-/*
- * Environment settings
- */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
- /* beginning of the EEPROM */
-#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
-
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * SDRAM configuration
- */
-#define SDRAM_DDR 1
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x71500F00
-#define SDRAM_CONFIG1 0x73711930
-#define SDRAM_CONFIG2 0x47770000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
- /* bootloader or debugger config */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-
-/* End of used area in SPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Chip Select configuration for NAND flash */
-#define CONFIG_SYS_CS1_START 0x20000000
-#define CONFIG_SYS_CS1_SIZE 0x90000
-#define CONFIG_SYS_CS1_CFG 0x00025b00
-
-/* Chip Select configuration for Epson S1D13513 */
-#define CONFIG_SYS_CS3_START 0x10000000
-#define CONFIG_SYS_CS3_SIZE 0x400000
-#define CONFIG_SYS_CS3_CFG 0xffff3d10
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR 0x01
-#define CONFIG_NO_AUTOLOAD 1
-
-/*
- * GPIO configuration
- *
- * GPS port configuration
- *
- * [29:31] = 01x
- * AC97 on PSC1
- * PSC1_0 -> AC97 SDATA out
- * PSC1_1 -> AC97 SDTA in
- * PSC1_2 -> AC97 SYNC out
- * PSC1_3 -> AC97 bitclock out
- * PSC1_4 -> AC97 reset out
- *
- * [28] = Reserved
- *
- * [25:27] = 110
- * SPI on PSC2
- * PSC2_0 -> MOSI
- * PSC2_1 -> MISO
- * PSC2_2 -> n/a
- * PSC2_3 -> CLK
- * PSC2_4 -> SS
- *
- * [24] = Reserved
- *
- * [20:23] = 0001
- * USB on PSC3
- * PSC3_0 -> USB_OE OE out
- * PSC3_1 -> USB_TXN Tx- out
- * PSC3_2 -> USB_TXP Tx+ out
- * PSC3_3 -> USB_TXD
- * PSC3_4 -> USB_RXP Rx+ in
- * PSC3_5 -> USB_RXN Rx- in
- * PSC3_6 -> USB_PWR PortPower out
- * PSC3_7 -> USB_SPEED speed out
- * PSC3_8 -> USB_SUSPEND suspend
- * PSC3_9 -> USB_OVRCURNT overcurrent in
- *
- * [18:19] = 10
- * Two UARTs
- *
- * [17] = 0
- * USB differential mode
- *
- * [16] = 1
- * PCI disabled
- *
- * [12:15] = 0101
- * Ethernet 100Mbit with MD
- * ETH_0 -> ETH Txen
- * ETH_1 -> ETH TxD0
- * ETH_2 -> ETH TxD1
- * ETH_3 -> ETH TxD2
- * ETH_4 -> ETH TxD3
- * ETH_5 -> ETH Txerr
- * ETH_6 -> ETH MDC
- * ETH_7 -> ETH MDIO
- * ETH_8 -> ETH RxDv
- * ETH_9 -> ETH RxCLK
- * ETH_10 -> ETH Collision
- * ETH_11 -> ETH TxD
- * ETH_12 -> ETH RxD0
- * ETH_13 -> ETH RxD1
- * ETH_14 -> ETH RxD2
- * ETH_15 -> ETH RxD3
- * ETH_16 -> ETH Rxerr
- * ETH_17 -> ETH CRS
- *
- * [9:11] = 111
- * SPI on PSC6
- * PSC6_0 -> MISO
- * PSC6_1 -> SS#
- * PSC6_2 -> MOSI
- * PSC6_3 -> CLK
- *
- * [8] = 0
- * IrDA/USB 48MHz clock generated internally
- *
- * [6:7] = 01
- * ATA chip selects on csb_4/5
- * CSB_4 -> ATA_CS0 out
- * CSB_5 -> ATA_CS1 out
- *
- * [5] = 1
- * PSC3_4 is used as CS6
- *
- * [4] = 1
- * PSC3_5 is used as CS7
- *
- * [2:3] = 00
- * No Alternatives
- *
- * [1] = 0
- * gpio_wkup_7 is GPIO
- *
- * [0] = 0
- * gpio_wkup_6 is GPIO
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_CRC32_VERIFY 1
-
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-#define CONFIG_VERSION_VARIABLE 1
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-/* no burst access on the LPB */
-#define CONFIG_SYS_CS_BURST 0x00000000
-/* one deadcycle for the 33MHz statemachine */
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
-
-#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*
- * USB settings
- */
-#define CONFIG_USB_CLOCK 0x0001bbbb
-/* USB is on PSC3 */
-#define CONFIG_PSC3_USB
-#define CONFIG_USB_CONFIG 0x00000100
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*
- * IDE/ATA stuff Supports IDE harddisk
- */
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-#define CONFIG_ATAPI 1
-
-/* we enable IDE and FAT support, so we also need partition support */
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * Open Firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,5200 at 0"
-#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
-#define OF_SOC "soc5200 at f0000000"
-#define OF_STDOUT_PATH "/soc5200 at f0000000/serial at 2600"
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 6/7] powerpc: ppc4xx: remove korat board support
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
` (4 preceding siblings ...)
2015-03-17 3:28 ` [U-Boot] [PATCH 5/7] powerpc: mpc5xxx: remove galaxy5200 " Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 20:40 ` Tom Rini
2015-03-17 3:28 ` [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards Masahiro Yamada
2015-03-17 6:10 ` [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Sinan Akman
7 siblings, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/korat/Kconfig | 9 -
board/korat/MAINTAINERS | 7 -
board/korat/Makefile | 9 -
board/korat/README | 64 ----
board/korat/config.mk | 27 --
board/korat/init.S | 80 -----
board/korat/korat.c | 633 ----------------------------------------
board/korat/u-boot-F7FC.lds | 124 --------
configs/korat_defconfig | 3 -
configs/korat_perm_defconfig | 4 -
doc/README.scrapyard | 1 +
include/configs/korat.h | 550 ----------------------------------
13 files changed, 1 insertion(+), 1514 deletions(-)
delete mode 100644 board/korat/Kconfig
delete mode 100644 board/korat/MAINTAINERS
delete mode 100644 board/korat/Makefile
delete mode 100644 board/korat/README
delete mode 100644 board/korat/config.mk
delete mode 100644 board/korat/init.S
delete mode 100644 board/korat/korat.c
delete mode 100644 board/korat/u-boot-F7FC.lds
delete mode 100644 configs/korat_defconfig
delete mode 100644 configs/korat_perm_defconfig
delete mode 100644 include/configs/korat.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 75e4507..9e52d3f 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_CSB272
config TARGET_CSB472
bool "Support csb472"
-config TARGET_KORAT
- bool "Support korat"
-
config TARGET_LWMON5
bool "Support lwmon5"
select SUPPORT_SPL
@@ -195,7 +192,6 @@ source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/korat/Kconfig"
source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
diff --git a/board/korat/Kconfig b/board/korat/Kconfig
deleted file mode 100644
index f434dea..0000000
--- a/board/korat/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_KORAT
-
-config SYS_BOARD
- default "korat"
-
-config SYS_CONFIG_NAME
- default "korat"
-
-endif
diff --git a/board/korat/MAINTAINERS b/board/korat/MAINTAINERS
deleted file mode 100644
index 8b96846..0000000
--- a/board/korat/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-KORAT BOARD
-M: Larry Johnson <lrj@acm.org>
-S: Maintained
-F: board/korat/
-F: include/configs/korat.h
-F: configs/korat_defconfig
-F: configs/korat_perm_defconfig
diff --git a/board/korat/Makefile b/board/korat/Makefile
deleted file mode 100644
index 63914bc..0000000
--- a/board/korat/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = korat.o
-extra-y += init.o
diff --git a/board/korat/README b/board/korat/README
deleted file mode 100644
index e059f78..0000000
--- a/board/korat/README
+++ /dev/null
@@ -1,64 +0,0 @@
-The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
-chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
-addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
-from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
-Bank #1 (with the starting address depending on the flash size detected at
-runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
-cannot be modified in the field. This also prevents FLASH0 from executing
-commands to return chip information, so its configuration is hard-coded in
-U-Boot.
-
-There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
-permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
-0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
-located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
-for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
-used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
-0xF7FDFFFF are used for the redundant copy of the parameters. These locations
-are used by both versions of U-Boot.
-
-On booting, the permanent U-Boot in FLASH0 begins executing. After performing
-minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
-the switch is sensed as open before a timeout period, then U-Boot branches to
-address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
-beginning. If the switch remains closed thoughout the timeout period, the
-permanent U-Boot activates the on-board buzzer until the switch is sensed as
-opened. It then continues to execute without branching to FLASH1. The effect
-of this is that normally the Korat board boots its upgradable U-Boot, but, if
-this has been corrupted, the user can boot the permanent U-Boot, which can then
-be used to erase and reload FLASH1 as needed.
-
-Note that it is not necessary for the permanent U-Boot to have all the latest
-features, but only that it have sufficient functionality (working "tftp",
-"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
-assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
-sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
-
-The build sequence:
-
- make korat_perm_config
- make all
-
-builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
-preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
-
- make korat_config
- make all
-
-creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
-leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
-
-2008-02-22, Larry Johnson <lrj@acm.org>
-
-
-The CompactFlash(R) controller on the Korat board provides a hi-speed USB
-interface. This may be connected to either a dedicated port on the on-board
-USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
-environment variable "korat_usbcf" can be used to specify which of these two
-USB host ports is used for CompactFlash. The valid setting for the variable are
-the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
-PowerPC USB port is used. In all other cases the on-board USB controller is
-used, but if "korat_usbcf" is defined but is set to a string other than the two
-valid options, a warning is also issued.
-
-2009-01-28, Larry Johnson <lrj@acm.org>
diff --git a/board/korat/config.mk b/board/korat/config.mk
deleted file mode 100644
index 42e0060..0000000
--- a/board/korat/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# Korat (PPC440EPx) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(emul),1)
-PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
-endif
-
-ifndef CONFIG_KORAT_PERMANENT
-LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
-endif
diff --git a/board/korat/init.S b/board/korat/init.S
deleted file mode 100644
index 20c5bdd..0000000
--- a/board/korat/init.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
-
- /*
- * TLB entries for SDRAM are not needed on this platform. They are
- * generated dynamically in the SPD DDR2 detection routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
- AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- /* I wonder why this must be executable -- lrj at acm.org 2007-10-08 */
- tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
-
- /* TLB-entry PCI IO Space - from sr at denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
-
- tlbtab_end
-
-#if defined(CONFIG_KORAT_PERMANENT)
- .globl korat_branch_absolute
-korat_branch_absolute:
- mtlr r3
- blr
-#endif
diff --git a/board/korat/korat.c b/board/korat/korat.c
deleted file mode 100644
index d9ab2fd..0000000
--- a/board/korat/korat.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * (C) Copyright 2007-2010
- * Larry Johnson, lrj at acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <asm/ppc440.h>
-#include <asm/bitops.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-uic.h>
-#include <asm/processor.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-ulong flash_get_size(ulong base, int banknum);
-
-#if defined(CONFIG_KORAT_PERMANENT)
-void korat_buzzer(int const on)
-{
- if (on) {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
- } else {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
- }
-}
-#endif
-
-int board_early_init_f(void)
-{
- uint32_t sdr0_pfc1, sdr0_pfc2;
- uint32_t reg;
- int eth;
-
-#if defined(CONFIG_KORAT_PERMANENT)
- unsigned mscount;
-
- extern void korat_branch_absolute(uint32_t addr);
-
- for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
- udelay(1000);
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
- /* This call does not return. */
- korat_branch_absolute(
- CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
- }
- }
- korat_buzzer(1);
- while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
- udelay(1000);
-
- korat_buzzer(0);
-#endif
-
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /*
- * Take sim card reader and CF controller out of reset. Also enable PHY
- * auto-detect until board-specific PHY resets are available.
- */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
-
- /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
- * if the SFP module is present, and for copper if it is not present.
- */
- for (eth = 0; eth < 2; ++eth) {
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
- /* SFP module not present: configure PHY for copper. */
- /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
- 0x06 << (4 * eth));
- } else {
- /* SFP module present: configure PHY for fiber and
- enable output */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
- }
- }
- /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
-
- /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
- udelay(1000);
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
-
- /* select Ethernet (and optionally IIC1) pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
-#ifdef CONFIG_I2C_MULTI_BUS
- sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
-#endif
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* PCI arbiter enabled */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
- return 0;
-}
-
-/*
- * The boot flash on CS0 normally has its write-enable pin disabled, and so will
- * not respond to CFI commands. This routine therefore fills in the flash
- * information for the boot flash. (The flash@CS1 operates normally.)
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- uint32_t addr;
- int i;
-
- if (1 != banknum)
- return 0;
-
- info->size = CONFIG_SYS_FLASH0_SIZE;
- info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
- info->flash_id = 0x01000000;
- info->portwidth = 2;
- info->chipwidth = 2;
- info->buffer_size = 32;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 2;
- info->cmd_reset = 0x00F0;
- info->interface = 2;
- info->legacy_unlock = 0;
- info->manufacturer_id = 1;
- info->device_id = 0x007E;
-
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
- info->device_id2 = 0x2101;
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
- info->device_id2 = 0x2301;
-#else
-#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
- info->ext_addr = 0x0040;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0055;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
- for (i = 0, addr = -info->size;
- i < info->sector_count;
- ++i, addr += 0x20000) {
- info->start[i] = addr;
- info->protect[i] = 0x00;
- }
- return 1;
-}
-
-static int man_data_read(unsigned int addr)
-{
- /*
- * Read an octet of data from address "addr" in the manufacturer's
- * information serial EEPROM, or -1 on error.
- */
- u8 data[2];
-
- if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
- 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
- debug("man_data_read(0x%02X) failed\n", addr);
- return -1;
- }
- debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
- return data[0];
-}
-
-static unsigned int man_data_field_addr(unsigned int const field)
-{
- /*
- * The manufacturer's information serial EEPROM contains a sequence of
- * zero-delimited fields. Return the starting address of field "field",
- * or 0 on error.
- */
- unsigned addr, i;
-
- if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
- /* Only format "A" is currently supported */
- return 0;
-
- for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
- if ('\0' == man_data_read(addr))
- ++i;
- }
- return (addr < 256) ? addr : 0;
-}
-
-static char *man_data_read_field(char s[], unsigned const field,
- unsigned const length)
-{
- /*
- * Place the null-terminated contents of field "field" of length
- * "length" from the manufacturer's information serial EEPROM into
- * string "s[length + 1]" and return a pointer to s, or return 0 on
- * error. In either case the original contents of s[] is not preserved.
- */
- unsigned addr, i;
-
- addr = man_data_field_addr(field);
- if (0 == addr || addr + length >= 255)
- return 0;
-
- for (i = 0; i < length; ++i) {
- int const c = man_data_read(addr++);
-
- if (c <= 0)
- return 0;
-
- s[i] = (char)c;
- }
- if (0 != man_data_read(addr))
- return 0;
-
- s[i] = '\0';
- return s;
-}
-
-static void set_serial_number(void)
-{
- /*
- * If the environmental variable "serial#" is not set, try to set it
- * from the manufacturer's information serial EEPROM.
- */
- char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
-
- if (getenv("serial#"))
- return;
-
- if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
- return;
-
- s[MAN_INFO_LENGTH] = '-';
- if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
- MAN_MAC_ADDR_LENGTH))
- return;
-
- setenv("serial#", s);
-}
-
-static void set_mac_addresses(void)
-{
- /*
- * If the environmental variables "ethaddr" and/or "eth1addr" are not
- * set, try to set them from the manufacturer's information serial
- * EEPROM.
- */
-
-#if MAN_MAC_ADDR_LENGTH % 2 != 0
-#error MAN_MAC_ADDR_LENGTH must be an even number
-#endif
-
- char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
- char *src;
- char *dst;
-
- if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
- return;
-
- if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
- MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
- return;
-
- for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
- *dst++ = *src++;
- *dst++ = *src++;
- *dst++ = ':';
- }
- if (0 == getenv("ethaddr"))
- setenv("ethaddr", s);
-
- if (0 == getenv("eth1addr")) {
- ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
- setenv("eth1addr", s);
- }
-}
-
-int misc_init_r(void)
-{
- uint32_t pbcr;
- int size_val;
- uint32_t reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- char const *const act = getenv("usbact");
- char const *const usbcf = getenv("korat_usbcf");
-
- /*
- * Re-do FLASH1 sizing and adjust flash start and offset.
- */
- gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(flash1_size) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /*
- * Re-do FLASH1 sizing and adjust flash offset to reserve space for
- * environment
- */
- gd->bd->bi_flashoffset =
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
-#if defined(CONFIG_KORAT_PERMANENT)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info + 1);
-#else
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info);
-#endif
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
-
- /*
- * USB suff...
- */
- /*
- * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
- * ("pci") for the CompactFlash.
- */
- if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
- /*
- * If environment variable "usbcf" is defined and set to "ppc",
- * then connect the CompactFlash controller to the PowerPC USB
- * port.
- */
- printf("Attaching CompactFlash controller to PPC USB\n");
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
- } else {
- if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
- printf("Warning: \"korat_usbcf\" is not set to a legal "
- "value (\"ppc\" or \"pci\")\n");
-
- printf("Attaching CompactFlash controller to PCI USB\n");
- }
- if (act == NULL || strcmp(act, "hostdev") == 0) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- /*
- * To enable the USB 2.0 Device function
- * through the UTMI interface
- */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- } else if (strcmp(act, "dev") == 0) {
- /*-------------------PATCH-------------------------------*/
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60306000);
- /*-------------------PATCH-------------------------------*/
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device(int phy)\n");
- }
-
- mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
- reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
- mtsdr(SDR0_SRST1, reg);
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- set_serial_number();
- set_mac_addresses();
- gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char const *const s = getenv("serial#");
- u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
-
- printf("Board: Korat, Rev. %X", rev);
- if (s)
- printf(", serial# %s", s);
-
- printf(".\n Ethernet PHY 0: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(", PHY 1: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(".\n");
-#if defined(CONFIG_KORAT_PERMANENT)
- printf(" Executing permanent copy of U-Boot.\n");
-#endif
- return 0;
-}
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /* First do 440EP(x) common setup */
- __pci_target_init(hose);
-
- /*
- * Set up Configuration registers for on-board NEC uPD720101 USB
- * controller.
- */
- pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u32 val[4];
- int rc;
-
- ft_cpu_setup(blob, bd);
-
- /* Fixup NOR mapping */
- val[0] = 1; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
- val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc)
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds
deleted file mode 100644
index bee4d9a..0000000
--- a/board/korat/u-boot-F7FC.lds
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xF7FBFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xF7FBF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/configs/korat_defconfig b/configs/korat_defconfig
deleted file mode 100644
index d363aab..0000000
--- a/configs/korat_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
diff --git a/configs/korat_perm_defconfig b/configs/korat_perm_defconfig
deleted file mode 100644
index 8c6b4c4..0000000
--- a/configs/korat_perm_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 1f2320b..59d2142 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
diff --git a/include/configs/korat.h b/include/configs/korat.h
deleted file mode 100644
index 5494a60..0000000
--- a/include/configs/korat.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * (C) Copyright 2007-2009
- * Larry Johnson, lrj at acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol at fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel at fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * korat.h - configuration for Korat board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_SYS_CLK_FREQ 33333333
-
-#ifdef CONFIG_KORAT_PERMANENT
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xF7F60000
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*
- * Manufacturer's information serial EEPROM parameters
- */
-#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
-#define MAN_INFO_FIELD 2
-#define MAN_INFO_LENGTH 9
-#define MAN_MAC_ADDR_FIELD 3
-#define MAN_MAC_ADDR_LENGTH 12
-
-/*
- * Base addresses -- Note these are effective addresses where the actual
- * resources get mapped (not physical addresses).
- */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH0_SIZE 0x01000000
-#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
-#define CONFIG_SYS_FLASH1_TOP 0xF8000000
-#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
-#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#define CONFIG_SYS_CPLD_BASE 0xc0000000
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
-#undef CONFIG_SYS_INIT_RAM_DCACHE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#define CONFIG_DDR_ECC /* Use ECC when available */
-#define SPD_EEPROM_ADDRESS {0x50}
-#define CONFIG_PROG_SDRAM_TLB
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
- /* per 440EPx Errata CHIP_11 */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T60 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* I2C SYSMON (LM73) */
-#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
-#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_MIN_TEMP -30
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME korat
-
-/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "u_boot=korat/u-boot.bin\0" \
- "load=tftp 200000 ${u_boot}\0" \
- "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
- "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
- "F7F60000 F7FBFFFF\0" \
- "upd=run load update\0" \
- "bootfile=korat/uImage\0" \
- "dtb=korat/korat.dtb\0" \
- "kernel_addr=F4000000\0" \
- "ramdisk_addr=F4400000\0" \
- "dtb_addr=F41E0000\0" \
- "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
- "cp.b ${fileaddr} F4000000 ${filesize}\0" \
- "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
- "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
- "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
- "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
- "${dtb}\0" \
- "rd_size=73728\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "ramdisk_size=${rd_size}\0" \
- "usbdev=sda1\0" \
- "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
- "rootpath=/opt/eldk/ppc_4xxFP\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "pciclk=33\0" \
- "addide=setenv bootargs ${bootargs} ide=reverse " \
- "idebus=${pciclk}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_cf=run usbargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_nfs=run nfsargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_self=run ramargs addip addtty; " \
- "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_cf"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
- /* buffers & descriptors */
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 3
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
- * Korat-specific options
- */
-#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
- /* CONFIG_SYS_PCI_MEMBASE */
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data have to be in the
- * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
- * during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
-/* Memory Bank 1 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
-#define CONFIG_SYS_EBC_PB1AP 0x04017300
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
-#endif
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x04017300
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
-
-/*
- * GPIO Setup
- *
- * Korat GPIO usage:
- *
- * Init.
- * Pin Source I/O value Function
- * ------ ------ --- ----- ---------------------------------
- * GPIO00 Alt1 I/O x PerAddr07
- * GPIO01 Alt1 I/O x PerAddr06
- * GPIO02 Alt1 I/O x PerAddr05
- * GPIO03 GPIO x x GPIO03 to expansion bus connector
- * GPIO04 GPIO x x GPIO04 to expansion bus connector
- * GPIO05 GPIO x x GPIO05 to expansion bus connector
- * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
- * GPIO07 Alt1 O x PerCS2 (CPLD)
- * GPIO08 Alt1 O x PerCS3 to expansion bus connector
- * GPIO09 Alt1 O x PerCS4 to expansion bus connector
- * GPIO10 Alt1 O x PerCS5 to expansion bus connector
- * GPIO11 Alt1 I x PerErr
- * GPIO12 GPIO O 0 ATMega !Reset
- * GPIO13 GPIO x x Test Point 2 (TP2)
- * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
- * GPIO15 GPIO O 0 CPU Run LED !On
- * GPIO16 Alt1 O x GMC1TxD0
- * GPIO17 Alt1 O x GMC1TxD1
- * GPIO18 Alt1 O x GMC1TxD2
- * GPIO19 Alt1 O x GMC1TxD3
- * GPIO20 Alt1 I x RejectPkt0
- * GPIO21 Alt1 I x RejectPkt1
- * GPIO22 GPIO I x PGOOD_DDR
- * GPIO23 Alt1 O x SCPD0
- * GPIO24 Alt1 O x GMC0TxD2
- * GPIO25 Alt1 O x GMC0TxD3
- * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
- * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
- * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
- * GPIO29 GPIO I x Test jumper !Present
- * GPIO30 GPIO I x SFP module #0 !Present
- * GPIO31 GPIO I x SFP module #1 !Present
- *
- * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
- * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
- * GPIO34 Alt2 I x !UART1_CTS
- * GPIO35 Alt2 O x !UART1_RTS
- * GPIO36 Alt1 I x !UART0_CTS
- * GPIO37 Alt1 O x !UART0_RTS
- * GPIO38 Alt2 O x UART1_Tx
- * GPIO39 Alt2 I x UART1_Rx
- * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
- * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
- * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
- * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
- * GPIO44 xxxx x x (grounded through pulldown)
- * GPIO45 GPIO O 0 PHY #0 Enable
- * GPIO46 GPIO O 0 PHY #1 Enable
- * GPIO47 GPIO I x Reset switch !Pressed
- * GPIO48 GPIO I x Shutdown switch !Pressed
- * GPIO49 xxxx x x (reserved for trace port)
- * . . . . .
- * . . . . .
- * . . . . .
- * GPIO63 xxxx x x (reserved for trace port)
- */
-
-#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
-#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
-#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
-#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
-#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
-#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
-#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
-#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
-#define CONFIG_SYS_GPIO_PHY0_EN 45
-#define CONFIG_SYS_GPIO_PHY1_EN 46
-#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
` (5 preceding siblings ...)
2015-03-17 3:28 ` [U-Boot] [PATCH 6/7] powerpc: ppc4xx: remove korat " Masahiro Yamada
@ 2015-03-17 3:28 ` Masahiro Yamada
2015-03-17 6:07 ` Sinan Akman
2015-03-17 17:00 ` [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD (was: [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards) Kim Phillips
2015-03-17 6:10 ` [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Sinan Akman
7 siblings, 2 replies; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 3:28 UTC (permalink / raw)
To: u-boot
Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
They have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Michael Barkowski <michael.barkowski@freescale.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 33 --
board/freescale/common/pq-mds-pib.c | 26 -
board/freescale/mpc8308rdb/Kconfig | 12 -
board/freescale/mpc8308rdb/MAINTAINERS | 6 -
board/freescale/mpc8308rdb/Makefile | 10 -
board/freescale/mpc8308rdb/mpc8308rdb.c | 192 -------
board/freescale/mpc8308rdb/sdram.c | 81 ---
board/freescale/mpc8313erdb/Kconfig | 12 -
board/freescale/mpc8313erdb/MAINTAINERS | 9 -
board/freescale/mpc8313erdb/Makefile | 8 -
board/freescale/mpc8313erdb/README | 111 ----
board/freescale/mpc8313erdb/mpc8313erdb.c | 157 ------
board/freescale/mpc8313erdb/sdram.c | 124 -----
board/freescale/mpc8315erdb/Kconfig | 12 -
board/freescale/mpc8315erdb/MAINTAINERS | 6 -
board/freescale/mpc8315erdb/Makefile | 8 -
board/freescale/mpc8315erdb/README | 105 ----
board/freescale/mpc8315erdb/mpc8315erdb.c | 246 ---------
board/freescale/mpc8315erdb/sdram.c | 111 ----
board/freescale/mpc8323erdb/Kconfig | 12 -
board/freescale/mpc8323erdb/MAINTAINERS | 6 -
board/freescale/mpc8323erdb/Makefile | 8 -
board/freescale/mpc8323erdb/README | 71 ---
board/freescale/mpc8323erdb/mpc8323erdb.c | 222 --------
board/freescale/mpc832xemds/Kconfig | 12 -
board/freescale/mpc832xemds/MAINTAINERS | 10 -
board/freescale/mpc832xemds/Makefile | 9 -
board/freescale/mpc832xemds/README | 128 -----
board/freescale/mpc832xemds/mpc832xemds.c | 166 ------
board/freescale/mpc832xemds/pci.c | 146 ------
board/freescale/mpc8349emds/Kconfig | 12 -
board/freescale/mpc8349emds/MAINTAINERS | 6 -
board/freescale/mpc8349emds/Makefile | 10 -
board/freescale/mpc8349emds/ddr.c | 101 ----
board/freescale/mpc8349emds/mpc8349emds.c | 285 -----------
board/freescale/mpc8349emds/pci.c | 192 -------
board/freescale/mpc8349itx/Kconfig | 12 -
board/freescale/mpc8349itx/MAINTAINERS | 8 -
board/freescale/mpc8349itx/Makefile | 8 -
board/freescale/mpc8349itx/README | 187 -------
board/freescale/mpc8349itx/mpc8349itx.c | 390 --------------
board/freescale/mpc8349itx/pci.c | 105 ----
board/freescale/mpc837xemds/Kconfig | 12 -
board/freescale/mpc837xemds/MAINTAINERS | 7 -
board/freescale/mpc837xemds/Makefile | 9 -
board/freescale/mpc837xemds/README | 104 ----
board/freescale/mpc837xemds/mpc837xemds.c | 346 -------------
board/freescale/mpc837xemds/pci.c | 147 ------
board/freescale/mpc837xemds/pci.h | 6 -
configs/MPC8308RDB_defconfig | 3 -
configs/MPC8313ERDB_33_defconfig | 4 -
configs/MPC8313ERDB_66_defconfig | 4 -
configs/MPC8313ERDB_NAND_33_defconfig | 5 -
configs/MPC8313ERDB_NAND_66_defconfig | 5 -
configs/MPC8315ERDB_defconfig | 3 -
configs/MPC8323ERDB_defconfig | 3 -
configs/MPC832XEMDS_ATM_defconfig | 4 -
configs/MPC832XEMDS_HOST_33_defconfig | 4 -
configs/MPC832XEMDS_HOST_66_defconfig | 4 -
configs/MPC832XEMDS_SLAVE_defconfig | 4 -
configs/MPC832XEMDS_defconfig | 3 -
configs/MPC8349EMDS_defconfig | 3 -
configs/MPC8349ITXGP_defconfig | 4 -
configs/MPC8349ITX_LOWBOOT_defconfig | 4 -
configs/MPC8349ITX_defconfig | 4 -
configs/MPC837XEMDS_HOST_defconfig | 4 -
configs/MPC837XEMDS_defconfig | 3 -
doc/README.scrapyard | 8 +
include/configs/MPC8308RDB.h | 582 ---------------------
include/configs/MPC8313ERDB.h | 719 --------------------------
include/configs/MPC8315ERDB.h | 659 ------------------------
include/configs/MPC8323ERDB.h | 555 --------------------
include/configs/MPC832XEMDS.h | 624 -----------------------
include/configs/MPC8349EMDS.h | 810 ------------------------------
include/configs/MPC8349ITX.h | 806 -----------------------------
include/configs/MPC837XEMDS.h | 719 --------------------------
76 files changed, 8 insertions(+), 9548 deletions(-)
delete mode 100644 board/freescale/mpc8308rdb/Kconfig
delete mode 100644 board/freescale/mpc8308rdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8308rdb/Makefile
delete mode 100644 board/freescale/mpc8308rdb/mpc8308rdb.c
delete mode 100644 board/freescale/mpc8308rdb/sdram.c
delete mode 100644 board/freescale/mpc8313erdb/Kconfig
delete mode 100644 board/freescale/mpc8313erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8313erdb/Makefile
delete mode 100644 board/freescale/mpc8313erdb/README
delete mode 100644 board/freescale/mpc8313erdb/mpc8313erdb.c
delete mode 100644 board/freescale/mpc8313erdb/sdram.c
delete mode 100644 board/freescale/mpc8315erdb/Kconfig
delete mode 100644 board/freescale/mpc8315erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8315erdb/Makefile
delete mode 100644 board/freescale/mpc8315erdb/README
delete mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c
delete mode 100644 board/freescale/mpc8315erdb/sdram.c
delete mode 100644 board/freescale/mpc8323erdb/Kconfig
delete mode 100644 board/freescale/mpc8323erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8323erdb/Makefile
delete mode 100644 board/freescale/mpc8323erdb/README
delete mode 100644 board/freescale/mpc8323erdb/mpc8323erdb.c
delete mode 100644 board/freescale/mpc832xemds/Kconfig
delete mode 100644 board/freescale/mpc832xemds/MAINTAINERS
delete mode 100644 board/freescale/mpc832xemds/Makefile
delete mode 100644 board/freescale/mpc832xemds/README
delete mode 100644 board/freescale/mpc832xemds/mpc832xemds.c
delete mode 100644 board/freescale/mpc832xemds/pci.c
delete mode 100644 board/freescale/mpc8349emds/Kconfig
delete mode 100644 board/freescale/mpc8349emds/MAINTAINERS
delete mode 100644 board/freescale/mpc8349emds/Makefile
delete mode 100644 board/freescale/mpc8349emds/ddr.c
delete mode 100644 board/freescale/mpc8349emds/mpc8349emds.c
delete mode 100644 board/freescale/mpc8349emds/pci.c
delete mode 100644 board/freescale/mpc8349itx/Kconfig
delete mode 100644 board/freescale/mpc8349itx/MAINTAINERS
delete mode 100644 board/freescale/mpc8349itx/Makefile
delete mode 100644 board/freescale/mpc8349itx/README
delete mode 100644 board/freescale/mpc8349itx/mpc8349itx.c
delete mode 100644 board/freescale/mpc8349itx/pci.c
delete mode 100644 board/freescale/mpc837xemds/Kconfig
delete mode 100644 board/freescale/mpc837xemds/MAINTAINERS
delete mode 100644 board/freescale/mpc837xemds/Makefile
delete mode 100644 board/freescale/mpc837xemds/README
delete mode 100644 board/freescale/mpc837xemds/mpc837xemds.c
delete mode 100644 board/freescale/mpc837xemds/pci.c
delete mode 100644 board/freescale/mpc837xemds/pci.h
delete mode 100644 configs/MPC8308RDB_defconfig
delete mode 100644 configs/MPC8313ERDB_33_defconfig
delete mode 100644 configs/MPC8313ERDB_66_defconfig
delete mode 100644 configs/MPC8313ERDB_NAND_33_defconfig
delete mode 100644 configs/MPC8313ERDB_NAND_66_defconfig
delete mode 100644 configs/MPC8315ERDB_defconfig
delete mode 100644 configs/MPC8323ERDB_defconfig
delete mode 100644 configs/MPC832XEMDS_ATM_defconfig
delete mode 100644 configs/MPC832XEMDS_HOST_33_defconfig
delete mode 100644 configs/MPC832XEMDS_HOST_66_defconfig
delete mode 100644 configs/MPC832XEMDS_SLAVE_defconfig
delete mode 100644 configs/MPC832XEMDS_defconfig
delete mode 100644 configs/MPC8349EMDS_defconfig
delete mode 100644 configs/MPC8349ITXGP_defconfig
delete mode 100644 configs/MPC8349ITX_LOWBOOT_defconfig
delete mode 100644 configs/MPC8349ITX_defconfig
delete mode 100644 configs/MPC837XEMDS_HOST_defconfig
delete mode 100644 configs/MPC837XEMDS_defconfig
delete mode 100644 include/configs/MPC8308RDB.h
delete mode 100644 include/configs/MPC8313ERDB.h
delete mode 100644 include/configs/MPC8315ERDB.h
delete mode 100644 include/configs/MPC8323ERDB.h
delete mode 100644 include/configs/MPC832XEMDS.h
delete mode 100644 include/configs/MPC8349EMDS.h
delete mode 100644 include/configs/MPC8349ITX.h
delete mode 100644 include/configs/MPC837XEMDS.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 4d6cb09..a7ff0d4 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -19,31 +19,6 @@ config TARGET_VE8313
config TARGET_VME8349
bool "Support vme8349"
-config TARGET_MPC8308RDB
- bool "Support MPC8308RDB"
-
-config TARGET_MPC8313ERDB
- bool "Support MPC8313ERDB"
- select SUPPORT_SPL
-
-config TARGET_MPC8315ERDB
- bool "Support MPC8315ERDB"
-
-config TARGET_MPC8323ERDB
- bool "Support MPC8323ERDB"
-
-config TARGET_MPC832XEMDS
- bool "Support MPC832XEMDS"
-
-config TARGET_MPC8349EMDS
- bool "Support MPC8349EMDS"
-
-config TARGET_MPC8349ITX
- bool "Support MPC8349ITX"
-
-config TARGET_MPC837XEMDS
- bool "Support MPC837XEMDS"
-
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
@@ -68,14 +43,6 @@ config TARGET_HRCON
endchoice
source "board/esd/vme8349/Kconfig"
-source "board/freescale/mpc8308rdb/Kconfig"
-source "board/freescale/mpc8313erdb/Kconfig"
-source "board/freescale/mpc8315erdb/Kconfig"
-source "board/freescale/mpc8323erdb/Kconfig"
-source "board/freescale/mpc832xemds/Kconfig"
-source "board/freescale/mpc8349emds/Kconfig"
-source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/km83xx/Kconfig"
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 1eb3786..4313ac3 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -36,11 +36,7 @@ int pib_init(void)
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_MPC832XEMDS)
- val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
-#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
@@ -55,12 +51,8 @@ int pib_init(void)
eieio();
-#if defined(CONFIG_MPC832XEMDS)
- printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
-#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_MPC8569MDS)
@@ -76,24 +68,6 @@ int pib_init(void)
eieio();
printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_MPC832XEMDS)
- val8 = 0;
- i2c_write(0x26, 0x7, 1, &val8, 1);
- val8 = 0xf7;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x21, 0x6, 1, &val8, 1);
- i2c_write(0x21, 0x7, 1, &val8, 1);
-
- val8 = 0xdf;
- i2c_write(0x21, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x21, 0x3, 1, &val8, 1);
-
- eieio();
-
- printf("QOC3 ATM card on PMC1\n");
#endif
#endif
/* Reset to original I2C bus */
diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig
deleted file mode 100644
index 48d25e5..0000000
--- a/board/freescale/mpc8308rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8308RDB
-
-config SYS_BOARD
- default "mpc8308rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8308RDB"
-
-endif
diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS
deleted file mode 100644
index 07ff2abd..0000000
--- a/board/freescale/mpc8308rdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8308RDB BOARD
-M: Ilya Yanok <yanok@emcraft.com>
-S: Maintained
-F: board/freescale/mpc8308rdb/
-F: include/configs/MPC8308RDB.h
-F: configs/MPC8308RDB_defconfig
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
deleted file mode 100644
index ec2b85d..0000000
--- a/board/freescale/mpc8308rdb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010
-# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8308rdb.o sdram.o
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
deleted file mode 100644
index 93e1c50..0000000
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK 0x00400000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- /* active low */
- clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- /* inactive high */
- setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-}
-#endif /* CONFIG_MPC8XXX_SPI */
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
- return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-static u8 read_board_info(void)
-{
- u8 val8;
- i2c_set_bus_num(0);
-
- if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
- return val8;
- else
- return 0;
-}
-
-int checkboard(void)
-{
- static const char * const rev_str[] = {
- "1.0",
- "<reserved>",
- "<reserved>",
- "<reserved>",
- "<unknown>",
- };
- u8 info;
- int i;
-
- info = read_board_info();
- i = (!info) ? 4 : info & 0x03;
-
- printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
-
- return 0;
-}
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- sysconf83xx_t *sysconf = &immr->sysconf;
- law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(1, pcie_reg);
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
-#ifdef CONFIG_MPC8XXX_SPI
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- sysconf83xx_t *sysconf = &immr->sysconf;
-
- /*
- * Set proper bits in SICRH to allow SPI on header J8
- *
- * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
- * switch. The pinmux configuration does not have a fine enough
- * granularity to support both simultaneously.
- */
- clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
- puts("WARNING: SPI enabled, TSEC2 support is broken\n");
-
- /* Set header J8 SPI chip select output, disabled */
- setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
- setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
- CONFIG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- return 1;
- }
-#endif
-
- return 0;
-}
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
- fdt_fixup_esdhc(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rv, num_if = 0;
-
- /* Initialize TSECs first */
- rv = cpu_eth_init(bis);
- if (rv >= 0)
- num_if += rv;
- else
- printf("ERROR: failed to initialize TSECs.\n");
-
- rv = pci_eth_init(bis);
- if (rv >= 0)
- num_if += rv;
- else
- printf("ERROR: failed to initialize PCI Ethernet.\n");
-
- return num_if;
-}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
deleted file mode 100644
index 89b665e..0000000
--- a/board/freescale/mpc8308rdb/sdram.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- * Authors: Nick.Spence at freescale.com
- * Wilson.Lo at freescale.com
- * scottwood at freescale.com
- *
- * This files is mostly identical to the original from
- * board\freescale\mpc8315erdb\sdram.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
- out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
- out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
- /* Currently we use only one CS, so disable the other bank. */
- out_be32(&im->ddr.cs_config[1], 0);
-
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
- sync();
-
- /* enable DDR controller */
- setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
- sync();
-
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
-}
-
-phys_size_t initdram(int board_type)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize;
-
- if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM */
- msize = fixed_sdram();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
-}
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
deleted file mode 100644
index 145608f..0000000
--- a/board/freescale/mpc8313erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8313ERDB
-
-config SYS_BOARD
- default "mpc8313erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8313ERDB"
-
-endif
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
deleted file mode 100644
index 807fb0b..0000000
--- a/board/freescale/mpc8313erdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8313ERDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/mpc8313erdb/
-F: include/configs/MPC8313ERDB.h
-F: configs/MPC8313ERDB_33_defconfig
-F: configs/MPC8313ERDB_66_defconfig
-F: configs/MPC8313ERDB_NAND_33_defconfig
-F: configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
deleted file mode 100644
index 77fad75..0000000
--- a/board/freescale/mpc8313erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
deleted file mode 100644
index be7ef32..0000000
--- a/board/freescale/mpc8313erdb/README
+++ /dev/null
@@ -1,111 +0,0 @@
-Freescale MPC8313ERDB Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
- To boot the image at 0xFE000000 in NOR flash, use these DIP
- switch settings for S3 S4:
-
- +------+ +------+
- | | | **** |
- | **** | | |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- To boot the image at the beginning of NAND flash, use these
- DIP switch settings for S3 S4:
-
- +------+ +------+
- | * | | *** |
- | *** | | * |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x07ff_ffff DDR 128M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe200_0000 0xe20f_ffff PCI IO 16M
- 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
- 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
- 0xfa00_0000 0xfa00_7fff Board Status/ 32K
- LED Control (CS3)
- 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
-
- When booting from NAND, NAND flash is CS0 and NOR flash
- is CS1.
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8313ERDB.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC831x MPC831x specific
- CONFIG_MPC8313ERDB MPC8313ERDB board specific
-
-4. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8313ERDB_XXX_config
- (where XXX is:
- 33 - 33 MHz oscillator, boot from NOR flash
- 66 - 66 MHz oscillator, boot from NOR flash
- NAND_33 - 33 MHz oscillator, boot from NAND flash
- NAND_66 - 66 MHz oscillator, boot from NAND flash)
- make
-
-5. Downloading and Flashing Images
-
-5.1 Reflash U-boot Image using U-boot
-
- NOR flash:
-
- =>run tftpflash
-
- You may want to try
- =>tftpboot $loadaddr $uboot
- first, to make sure that the TFTP load will succeed before it
- goes ahead and wipes out your current firmware. And of course,
- have an alternate means of programming the flash available
- if the new u-boot doesn't boot.
-
- NAND flash:
-
- =>tftpboot $loadaddr <filename>
- =>nand erase 0 0x80000
- =>nand write $loadaddr 0 0x80000
-
- ...where 0x80000 is the filesize rounded up to
- the next 0x20000 increment.
-
-5.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- =>run nfsboot
- or
- =>run ramboot
-
-6 Notes
-
- The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
deleted file mode 100644
index eac193e..0000000
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <ns16550.h>
-#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-#include <asm/gpio.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- gd->flags |= GD_FLG_SILENT;
-#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
- mpc83xx_gpio_init_f();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
- mpc83xx_gpio_init_r();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8313ERDB\n");
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
- .size = CONFIG_SYS_PCI1_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
- .size = CONFIG_SYS_PCI1_MMIO_SIZE,
- .flags = PCI_REGION_MEM
- },
- {
- .bus_start = CONFIG_SYS_PCI1_IO_BASE,
- .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
- .size = CONFIG_SYS_PCI1_IO_SIZE,
- .flags = PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
- int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
- CONFIG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- rc = 1;
- }
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-#else /* CONFIG_SPL_BUILD */
-void board_init_f(ulong bootflag)
-{
- board_early_init_f();
- NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- init_timebase();
- initdram(0);
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
deleted file mode 100644
index 6282c3d..0000000
--- a/board/freescale/mpc8313erdb/sdram.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Authors: Nick.Spence at freescale.com
- * Wilson.Lo at freescale.com
- * scottwood at freescale.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-static void resume_from_sleep(void)
-{
- u32 magic = *(u32 *)0;
-
- typedef void (*func_t)(void);
- func_t resume = *(func_t *)4;
-
- if (magic == 0xf5153ae5)
- resume();
-
- gd->flags &= ~GD_FLG_SILENT;
- puts("\nResume from sleep failed: bad magic word\n");
-}
-#endif
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- __udelay(50000);
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
- CSBNDS_EA);
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
- /* Currently we use only one CS, so disable the other bank. */
- im->ddr.cs_config[1] = 0;
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
- else
-#endif
- im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
-
- im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-#endif
-
- return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- msize = fixed_sdram();
-
- /* Local Bus setup lbcr and mrtpr */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- sync();
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- resume_from_sleep();
-#endif
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
-}
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
deleted file mode 100644
index f76b0d1..0000000
--- a/board/freescale/mpc8315erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
- default "mpc8315erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8315ERDB"
-
-endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
deleted file mode 100644
index 938c152..0000000
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8315ERDB BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc8315erdb/
-F: include/configs/MPC8315ERDB.h
-F: configs/MPC8315ERDB_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
deleted file mode 100644
index fbb68c5..0000000
--- a/board/freescale/mpc8315erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
deleted file mode 100644
index b32132d..0000000
--- a/board/freescale/mpc8315erdb/README
+++ /dev/null
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
- To boot the image at 0xFE000000 in NOR flash, use these DIP
- switch settings for S3 S4:
-
- +------+ +------+
- | | | **** |
- | **** | | |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- To boot the image at the beginning of NAND flash, use these
- DIP switch settings for S3 S4:
-
- +------+ +------+
- | * | | *** |
- | *** | | * |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x07ff_ffff DDR 128M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
- 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
-
- When booting from NAND, NAND flash is CS0 and NOR flash
- is CS1.
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8315ERDB.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC831x MPC831x specific
- CONFIG_MPC8315 MPC8315 specific
- CONFIG_MPC8315ERDB MPC8315ERDB board specific
-
-4. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
- make all
-
-5. Downloading and Flashing Images
-
-5.1 Reflash U-boot Image using U-boot
-
- NOR flash:
-
- tftp 40000 u-boot.bin
- protect off all
- erase fe000000 fe1fffff
-
- cp.b 40000 fe000000 xxxx
- protect on all
-
- You have to supply the correct byte count with 'xxxx'
- from the TFTP result log.
-
- NAND flash:
-
- =>tftpboot $loadaddr <filename>
- =>nand erase 0 0x80000
- =>nand write $loadaddr 0 0x80000
-
- ...where 0x80000 is the filesize rounded up to
- the next 0x20000 increment.
-
-5.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- =>run nfsboot
- or
- =>run ramboot
-
-6 Notes
-
- The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
deleted file mode 100644
index ed611c5..0000000
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <scottwood@freescale.com>
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- gd->flags |= GD_FLG_SILENT;
-
- return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
- u8 val8;
- i2c_set_bus_num(0);
-
- if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
- return val8;
- else
- return 0;
-}
-
-int checkboard(void)
-{
- static const char * const rev_str[] = {
- "0.0",
- "0.1",
- "1.0",
- "1.1",
- "<unknown>",
- };
- u8 info;
- int i;
-
- info = read_board_info();
- i = (!info) ? 4: info & 0x03;
-
- printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI_MEM_BASE,
- phys_start: CONFIG_SYS_PCI_MEM_PHYS,
- size: CONFIG_SYS_PCI_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
- size: CONFIG_SYS_PCI_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI_IO_BASE,
- phys_start: CONFIG_SYS_PCI_IO_PHYS,
- size: CONFIG_SYS_PCI_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-
- /* Configure the clock for PCIE controller */
- clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
- SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, bd_t *bd)
-{
- const char disabled[] = "disabled";
- const char *path;
- int ret;
-
- if (hwconfig_arg_cmp("board_type", "tsec1")) {
- return;
- } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
- printf("NOTICE: No or unknown board_type hwconfig specified.\n"
- " Assuming board with TSEC1.\n");
- return;
- }
-
- ret = fdt_path_offset(fdt, "/aliases");
- if (ret < 0) {
- printf("WARNING: can't find /aliases node\n");
- return;
- }
-
- path = fdt_getprop(fdt, ret, "ethernet0", NULL);
- if (!path) {
- printf("WARNING: can't find ethernet0 alias\n");
- return;
- }
-
- do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- fdt_fixup_dr_usb(blob, bd);
- fdt_tsec1_fixup(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Initialize TSECs first */
- return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8315ERDB\n");
- return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
- board_early_init_f();
- NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- init_timebase();
- initdram(0);
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
deleted file mode 100644
index 6c94312..0000000
--- a/board/freescale/mpc8315erdb/sdram.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence at freescale.com
- * Wilson.Lo at freescale.com
- * scottwood at freescale.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
- u32 magic = *(u32 *)0;
-
- typedef void (*func_t)(void);
- func_t resume = *(func_t *)4;
-
- if (magic == 0xf5153ae5)
- resume();
-
- gd->flags &= ~GD_FLG_SILENT;
- puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- __udelay(50000);
-
- im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
- /* Currently we use only one CS, so disable the other bank. */
- im->ddr.cs_config[1] = 0;
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
- else
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- sync();
-
- return msize;
-}
-#else
-static long fixed_sdram(void)
-{
- return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM */
- msize = fixed_sdram();
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- resume_from_sleep();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
-}
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
deleted file mode 100644
index acf8122..0000000
--- a/board/freescale/mpc8323erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8323ERDB
-
-config SYS_BOARD
- default "mpc8323erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8323ERDB"
-
-endif
diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
deleted file mode 100644
index 05057c0..0000000
--- a/board/freescale/mpc8323erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8323ERDB BOARD
-M: Michael Barkowski <michael.barkowski@freescale.com>
-S: Maintained
-F: board/freescale/mpc8323erdb/
-F: include/configs/MPC8323ERDB.h
-F: configs/MPC8323ERDB_defconfig
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
deleted file mode 100644
index f2e7497..0000000
--- a/board/freescale/mpc8323erdb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8323erdb.o
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
deleted file mode 100644
index 6f89829..0000000
--- a/board/freescale/mpc8323erdb/README
+++ /dev/null
@@ -1,71 +0,0 @@
-Freescale MPC8323ERDB Board
------------------------------------------
-
-1. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x03ff_ffff DDR 64M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xd000_0000 0xd3ff_ffff PCI IO 64M
- 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
-
-2. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8323ERDB_config
- make
-
-3. Downloading and Flashing Images
-
-3.1 Reflash U-boot Image using U-boot
-
- N.b, have an alternate means of programming
- the flash available if the new u-boot doesn't boot.
-
- First try a:
-
- tftpboot $loadaddr $uboot
-
- to make sure that the TFTP load will succeed before
- an erase goes ahead and wipes out your current firmware.
- Then do a:
-
- run tftpflash
-
- which is a shorter version of the manual sequence:
-
- tftp $loadaddr u-boot.bin
- protect off fe000000 +$filesize
- erase fe000000 +$filesize
- cp.b $loadaddr fe000000 $filesize
-
- To keep your old u-boot's environment variables, do a:
-
- saveenv
-
- prior to resetting the board.
-
-3.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- run nfsboot
-
- or
-
- run ramboot
-
-4 Notes
-
- The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
deleted file mode 100644
index 0a0152a..0000000
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Michael Barkowski <michael.barkowski@freescale.com>
- * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#include <libfdt.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* UCC3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
-
- /* UCC2 */
- {0, 18, 1, 0, 1}, /* TxD0 */
- {0, 19, 1, 0, 1}, /* TxD1 */
- {0, 20, 1, 0, 1}, /* TxD2 */
- {0, 21, 1, 0, 1}, /* TxD3 */
- {0, 27, 1, 0, 1}, /* TxER */
- {0, 30, 1, 0, 1}, /* TxEN */
- {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
- {0, 22, 2, 0, 1}, /* RxD0 */
- {0, 23, 2, 0, 1}, /* RxD1 */
- {0, 24, 2, 0, 1}, /* RxD2 */
- {0, 25, 2, 0, 1}, /* RxD3 */
- {0, 26, 1, 0, 1}, /* RxER */
- {0, 28, 2, 0, 1}, /* Rx_DV */
- {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
- {0, 29, 2, 0, 1}, /* COL */
- {0, 31, 2, 0, 1}, /* CRS */
-
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
- msize = fixed_sdram();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__ ("sync");
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- __asm__ __volatile__ ("sync");
- return msize;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8323ERDB\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
-int mac_read_from_eeprom(void)
-{
- uchar buf[28];
- char str[18];
- int i = 0;
- unsigned int crc = 0;
- unsigned char enetvar[32];
-
- /* Read MAC addresses from EEPROM */
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
- printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
- } else {
- uint32_t crc_buf;
-
- memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
-
- if (crc32(crc, buf, 24) == crc_buf) {
- printf("Reading MAC from EEPROM\n");
- for (i = 0; i < 4; i++) {
- if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
- sprintf(str,
- "%02X:%02X:%02X:%02X:%02X:%02X",
- buf[i * 6], buf[i * 6 + 1],
- buf[i * 6 + 2], buf[i * 6 + 3],
- buf[i * 6 + 4], buf[i * 6 + 5]);
- sprintf((char *)enetvar,
- i ? "eth%daddr" : "ethaddr", i);
- setenv((char *)enetvar, str);
- }
- }
- }
- }
- return 0;
-}
-#endif /* CONFIG_I2C_MAC_OFFSET */
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
deleted file mode 100644
index e4cfa15..0000000
--- a/board/freescale/mpc832xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
- default "mpc832xemds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC832XEMDS"
-
-endif
diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
deleted file mode 100644
index 56d7073..0000000
--- a/board/freescale/mpc832xemds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-MPC832XEMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc832xemds/
-F: include/configs/MPC832XEMDS.h
-F: configs/MPC832XEMDS_defconfig
-F: configs/MPC832XEMDS_ATM_defconfig
-F: configs/MPC832XEMDS_HOST_33_defconfig
-F: configs/MPC832XEMDS_HOST_66_defconfig
-F: configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
deleted file mode 100644
index 6676351..0000000
--- a/board/freescale/mpc832xemds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
deleted file mode 100644
index 4142aa9..0000000
--- a/board/freescale/mpc832xemds/README
+++ /dev/null
@@ -1,128 +0,0 @@
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW3 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
- SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
- SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
- First, make sure the board default setting is consistent with the document
- shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_1000 (core PLL setting, core enable)
- SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
- SW5[1-8]= 0010_0110 (Boot from high end)
- SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
- SW7[1-8]= 1000_0011 (QE PLL setting)
-
- ENET3/4 MII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 2-3 (MII mode)
- J3 2-3 (MII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 mounted (ETH4/2 MII)
- JP3 mounted (ETH3 MII)
- JP4 mounted (HRCW from BCSR)
-
- ENET3/4 RMII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 1-2 (RMII mode)
- J3 1-2 (RMII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 removed (ETH4/2 RMII)
- JP3 removed (ETH3 RMII)
- JP4 removed (HRCW from FLASH)
-
- on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS2 32K
- 0xf801_0000 0xf801_7fff PIB CS3 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC832XEPB.h
-
- CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
- CONFIG_MPC832x MPC832x specific
- CONFIG_MPC832XEMDS MPC832XEMDS board specific
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC832XEMDS_config
- make
-
- MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
-
- 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
- 2)To Make U-Boot image support PCI 33MHz, use
- Make MPC832XEMDS_HOST_33_config
-
- 3)To Make U-Boot image support PCI 66MHz, use
- Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
- tftp 20000 u-boot.bin
- protect off fe000000 fe0fffff
- erase fe000000 fe0fffff
- cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
deleted file mode 100644
index adf4254..0000000
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* ETH3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
-
- /* ETH4 */
- {1, 18, 1, 0, 1}, /* TxD0 */
- {1, 19, 1, 0, 1}, /* TxD1 */
- {1, 20, 1, 0, 1}, /* TxD2 */
- {1, 21, 1, 0, 1}, /* TxD3 */
- {1, 27, 1, 0, 1}, /* TxER */
- {1, 30, 1, 0, 1}, /* TxEN */
- {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
-
- {1, 22, 2, 0, 1}, /* RxD0 */
- {1, 23, 2, 0, 1}, /* RxD1 */
- {1, 24, 2, 0, 1}, /* RxD2 */
- {1, 25, 2, 0, 1}, /* RxD3 */
- {1, 26, 1, 0, 1}, /* RxER */
- {1, 28, 2, 0, 1}, /* Rx_DV */
- {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
- {1, 29, 2, 0, 1}, /* COL */
- {1, 31, 2, 0, 1}, /* CRS */
-
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
- volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[9] &= ~0x08;
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- return 0;
-}
-
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-
- msize = fixed_sdram();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__ ("sync");
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- __asm__ __volatile__ ("sync");
- return msize;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC832XEMDS\n");
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
deleted file mode 100644
index e8b2b11..0000000
--- a/board/freescale/mpc832xemds/pci.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
deleted file mode 100644
index 51f0b34..0000000
--- a/board/freescale/mpc8349emds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8349EMDS
-
-config SYS_BOARD
- default "mpc8349emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8349EMDS"
-
-endif
diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
deleted file mode 100644
index 141e77a..0000000
--- a/board/freescale/mpc8349emds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8349EMDS BOARD
-M: Kim Phillips <kim.phillips@freescale.com>
-S: Maintained
-F: board/freescale/mpc8349emds/
-F: include/configs/MPC8349EMDS.h
-F: configs/MPC8349EMDS_defconfig
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
deleted file mode 100644
index 5c315f9..0000000
--- a/board/freescale/mpc8349emds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8349emds.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
deleted file mode 100644
index aae003d..0000000
--- a/board/freescale/mpc8349emds/ddr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 300, 4, 4, 2, 0},
- {2, 365, 4, 6, 2, 0},
- {2, 450, 4, 7, 2, 0},
- {2, 850, 4, 31, 2, 0},
- {1, 300, 4, 4, 2, 0},
- {1, 365, 4, 6, 2, 0},
- {1, 450, 4, 7, 2, 0},
- {1, 850, 4, 31, 2, 0},
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned int i;
- ulong ddr_freq;
-
- if (ctrl_num != 0) /* we have only one controller */
- return;
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (pdimm[i].n_ranks)
- break;
- }
- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
- return;
-
- pbsp = udimm0;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[i].n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- popts->dqs_config = 0; /* only true DQS signal is used on board */
-}
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
deleted file mode 100644
index 02b5040..0000000
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <miiphy.h>
-#ifdef CONFIG_SYS_FSL_DDR2
-#include <fsl_ddr_sdram.h>
-#else
-#include <spd_sdram.h>
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-int board_early_init_f (void)
-{
- volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[1] &= ~0x01;
-
-#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
- /* Use USB PHY on SYS board */
- bcsr[5] |= 0x02;
-#endif
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- phys_size_t msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_SYS_FSL_DDR2
- msize = spd_sdram() * 1024 * 1024;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- ddr_enable_ecc(msize);
-#endif
-#else
- msize = fsl_ddr_sdram();
-#endif
-#else
- msize = fixed_sdram() * 1024 * 1024;
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- sdram_init();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return msize;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20; /* DDR size in bytes */
- u32 ddr_size_log2 = __ilog2(ddr_size);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
- im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
- /* currently we use only one CS, so disable the other banks */
- im->ddr.cs_config[0] = 0;
- im->ddr.cs_config[1] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- im->ddr.sdram_cfg =
- SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
- | SDRAM_CFG_2T_EN
-#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
- /* for 32-bit mode burst length is 8 */
- im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
- udelay(200);
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
- /*
- * Warning: do not read the BCSR registers here
- *
- * There is a timing bug in the 8349E and 8349EA BCSR code
- * version 1.2 (read from BCSR 11) that will cause the CFI
- * flash initialization code to overwrite BCSR 0, disabling
- * the serial ports and gigabit ethernet
- */
-
- puts("Board: Freescale MPC8349EMDS\n");
- return 0;
-}
-
-/*
- * if MPC8349EMDS is soldered with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM) \
- && defined(CONFIG_SYS_OR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
- /*
- * Setup SDRAM Base and Option Registers, already done in cpu_init.c
- */
-
- /* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
-
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
- asm("sync");
- /*1 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*2 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*3 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*4 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*5 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*6 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*7 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*8 times*/
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-}
-#else
-void sdram_init(void)
-{
-}
-#endif
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-
-#define SPI_CS_MASK 0x80000000
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat &= ~SPI_CS_MASK;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
- iopd->dat |= SPI_CS_MASK;
-}
-#endif /* CONFIG_HARD_SPI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
deleted file mode 100644
index 9f7324f..0000000
--- a/board/freescale/mpc8349emds/pci.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-#ifndef CONFIG_PCISLAVE
-void pib_init(void)
-{
- u8 val8, orig_i2c_bus;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
- /* Switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
- val8 = 0xf4; /* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
- val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
- val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
-#else
- val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
-#endif
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
- val8 = 0;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
- asm("eieio");
-
-#if defined(PCI_64BIT)
- printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
- printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
- printf("PCI1: 32-bit on PMC1\n");
- printf("PCI2: 32-bit on PMC2, PMC3\n");
-#else
- printf("PCI1: 32-bit on PMC1, PMC2\n");
- printf("PCI2: 32-bit on PMC3\n");
-#endif
- /* Reset to original I2C bus */
- i2c_set_bus_num(orig_i2c_bus);
-}
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
- /* Enable all 8 PCI_CLK_OUTPUTS */
- clk->occr = 0xff000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- mpc83xx_pci_init(1, reg);
-
- /* Configure PCI Inbound Translation Windows (3 1MB windows) */
- pci_ctrl->pitar0 = 0x0;
- pci_ctrl->pibar0 = 0x0;
- pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- pci_ctrl->pitar1 = 0x0;
- pci_ctrl->pibar1 = 0x0;
- pci_ctrl->piebar1 = 0x0;
- pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- pci_ctrl->pitar2 = 0x0;
- pci_ctrl->pibar2 = 0x0;
- pci_ctrl->piebar2 = 0x0;
- pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
deleted file mode 100644
index ce3fffd..0000000
--- a/board/freescale/mpc8349itx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8349ITX
-
-config SYS_BOARD
- default "mpc8349itx"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8349ITX"
-
-endif
diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
deleted file mode 100644
index d0388ad..0000000
--- a/board/freescale/mpc8349itx/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-MPC8349ITX BOARD
-#M: -
-S: Maintained
-F: board/freescale/mpc8349itx/
-F: include/configs/MPC8349ITX.h
-F: configs/MPC8349ITX_defconfig
-F: configs/MPC8349ITX_LOWBOOT_defconfig
-F: configs/MPC8349ITXGP_defconfig
diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
deleted file mode 100644
index e9092ad..0000000
--- a/board/freescale/mpc8349itx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8349itx.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
deleted file mode 100644
index 48bbd50..0000000
--- a/board/freescale/mpc8349itx/README
+++ /dev/null
@@ -1,187 +0,0 @@
-Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
----------------------------------------------------
-
-1. Board Description
-
- The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
- the Freescale MPC8349E processor in a Mini-ITX form factor.
-
- The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
-
- A) One 8MB on-board flash EEPROM chip, instead of two.
- B) No SATA controller
- C) No Compact Flash slot
- D) No Mini-PCI slot
- E) No Vitesse 7385 5-port Ethernet switch
- F) No 4-port USB Type-A interface
-
-2. Board Switches and Jumpers
-
-2.0 Descriptions for all of the board jumpers can be found in the User
- Guide. Of particular interest to U-Boot developers is jumper J22:
-
- Pos. Name Default Description
- -----------------------------------------------------------------------
- A LGPL0 ON (0) HRCW source, bit 0
- B LGPL1 ON (0) HRCW source, bit 1
- C LGPL3 ON (0) HRCW source, bit 2
- D LGPL5 OFF (1) PCI_SYNC_OUT frequency
- E BOOT1 ON (0) Flash EEPROM boot device
- F PCI_M66EN ON (0) PCI 66MHz enable
- G I2C-WP ON (0) I2C EEPROM write protection
- H F_WP OFF (1) Flash EEPROM write protection
-
- Jumper J22.E is only for the ITX, and it decides the configuration
- of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
- U4 is located at address FE000000 and flash chip U7 is at FE800000.
- If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
-
- For U-Boot development, J22.E can be used to switch back-and-forth
- between two U-Boot images.
-
-3. Memory Map
-
-3.1. The memory map should look pretty much like this:
-
- 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
- 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
- 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
- 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
- 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
- 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
- 0xF001_0000 - 0xF001_FFFF Local bus expansion slot
- 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
- 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
- 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
-
-3.2 Flash EEPROM layout.
-
- On the ITX, jumper J22.E is used to determine which flash chips are
- at which address. When J22.E is switched, addresses from FE000000
- to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
-
- On the ITX, at the normal boot address (aka HIGHBOOT):
-
- FE00_0000 HRCW
- FE70_0000 Alternative U-Boot image
- FE80_0000 Alternative HRCW
- FEF0_0000 U-Boot image
- FEFF_FFFF End of flash
-
- On the ITX, at the low boot address (LOWBOOT)
-
- FE00_0000 HRCW and U-Boot image
- FE04_0000 U-Boot environment variables
- FE80_0000 Alternative HRCW and U-Boot image
- FEFF_FFFF End of flash
-
- On the ITX-GP, the only option is LOWBOOT and there is only one chip
-
- FE00_0000 HRCW and U-Boot image
- FE04_0000 U-Boot environment variables
- F7FF_FFFF End of flash
-
-4. Definitions
-
-4.1 Explanation of NEW definitions in:
-
- include/configs/MPC8349ITX.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC8349 MPC8349 specific
- CONFIG_MPC8349ITX MPC8349E-mITX
- CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
-
-5. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
-
- make MPC8349ITX_config
- or:
- make MPC8349ITXGP_config
- or:
- make MPC8349ITX_LOWBOOT_config
-
- make
-
-6. Downloading and Flashing Images
-
-6.1 Download via tftp:
-
- tftp $loadaddr <uboot>
-
- where "<uboot>" is the path and filename, on the TFTP server, of
- the U-Boot image.
-
-6.1 Reflash U-Boot Image using U-Boot
-
- setenv uboot <uboot>
- run tftpflash
-
- where "<uboot>" is the path and filename, on the TFTP server, of
- the U-Boot image.
-
-6.2 Using the HRCW to switch between two different U-Boot images on the ITX
-
- Because the ITX has 16MB of flash, it is possible to keep two U-Boot
- images in flash, and use the HRCW to specify which one is to be used
- when the board boots. This trick is especially effective with a
- hardware debugger that can override the HRCW, such as the BDI-2000.
-
- When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
- at address FE000000. When the BMS bit is 1, the ITX will boot the
- image at address FEF00000.
-
- Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
- change the BMS bit whenever you want to boot the other image.
-
- Step-by-step instructions:
-
- 1) Build an ITX image to be loaded at FEF00000
-
- make distclean
- make MPC8349ITX_config
- make
-
- 2) Take the u-boot.bin image and flash it at FEF00000.
-
- tftp $loadaddr u-boot.bin
- protect off all
- erase FEF00000 +$filesize
- cp.b $loadaddr FEF00000 $filesize
-
- 3) Build an ITX image to be loaded at FE000000
-
- make distclean
- make MPC8349ITX_LOWBOOT_config
- make
-
- 4) Take the u-boot.bin image and flash it at FE000000.
-
- tftp $loadaddr u-boot.bin
- protect off FE000000 +$filesize
- erase FE000000 +$filesize
- cp.b $loadaddr FE000000 $filesize
-
- The HRCW in flash is currently set to boot the image at FE000000.
-
- If you have a hardware debugger, configure it to set the HRCW to
- B460A000 04040000 if you want to boot the image at FEF00000, or set
- it to B060A000 04040000 if you want to boot the image at FE000000.
-
- To change the HRCW in flash to boot the image at FEF00000, use these
- U-Boot commands:
-
- cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
- mw.b 1020 b4 8 ; modify BMS bit
- protect off FE000000 +10000
- erase FE000000 +10000
- cp.b 1000 FE000000 10000
-
-7. Notes
- 1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
deleted file mode 100644
index 22a1d99..0000000
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <vsc7385.h>
-#ifdef CONFIG_PCI
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#ifndef CONFIG_SPD_EEPROM
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- /* The size of RAM, in bytes */
- u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
- u32 ddr_size_log2 = __ilog2(ddr_size);
-
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
- /* Only one CS for DDR */
- im->ddr.cs_config[1] = 0;
- im->ddr.cs_config[2] = 0;
- im->ddr.cs_config[3] = 0;
-
- debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
- debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
-
- debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
- debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
- im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
- im->ddr.sdram_mode =
- (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
- im->ddr.sdram_interval =
- (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
- SDRAM_INTERVAL_BSTOPRE_SHIFT);
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
- debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
- debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
- debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
- debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
-
- return CONFIG_SYS_DDR_SIZE;
-}
-#endif
-
-#ifdef CONFIG_PCI
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
- {
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0x0f,
- PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {
- PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
-}
-#endif
-
-volatile static struct pci_controller hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxmitx_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxmitx_config_table,
-#endif
- }
-};
-#endif /* CONFIG_PCI */
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-#ifdef CONFIG_DDR_ECC
- volatile ddr83xx_t *ddr = &im->ddr;
-#endif
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#ifdef CONFIG_SPD_EEPROM
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#ifdef CONFIG_DDR_ECC
- if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
- /* Unlike every other board, on the 83xx spd_sdram() returns
- megabytes instead of just bytes. That's why we need to
- multiple by 1MB when calling ddr_enable_ecc(). */
- ddr_enable_ecc(msize * 1048576);
-#endif
-
- /* return total bus RAM size(bytes) */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_MPC8349ITX
- puts("Board: Freescale MPC8349E-mITX\n");
-#else
- puts("Board: Freescale MPC8349E-mITX-GP\n");
-#endif
-
- return 0;
-}
-
-/*
- * Implement a work-around for a hardware problem with compact
- * flash.
- *
- * Program the UPM if compact flash is enabled.
- */
-int misc_init_f(void)
-{
-#ifdef CONFIG_VSC7385_ENET
- volatile u32 *vsc7385_cpuctrl;
-
- /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
- default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
- means it is 0 when the IRQ is not active. This makes the wire-AND
- logic always assert IRQ7 to CPU even if there is no request from the
- switch. Since the compact flash and the switch share the same IRQ,
- the Linux kernel will think that the compact flash is requesting irq
- and get stuck when it tries to clear the IRQ. Thus we need to set
- the L2_IRQ0 and L2_IRQ1 to active low.
-
- The following code sets the L1_IRQ and L2_IRQ polarity to active low.
- Without this code, compact flash will not work in Linux because
- unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
- don't enable compact flash for U-Boot.
- */
-
- vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
- *vsc7385_cpuctrl |= 0x0c;
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
- /* UPM Table Configuration Code */
- static uint UPMATable[] = {
- 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
- 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
- 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
- };
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-
- /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
- GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
- */
- immap->im_lbc.mamr = 0x08404440;
-
- upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
- puts("UPMA: Configured for compact flash\n");
-#endif
-
- return 0;
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * Make sure the EEPROM has the HRCW correctly programmed.
- * Make sure the RTC is correctly programmed.
- *
- * The MPC8349E-mITX can be configured to load the HRCW from
- * EEPROM instead of flash. This is controlled via jumpers
- * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
- * jumpered), but if they're set to 001 or 010, then the HRCW is
- * read from the "I2C EEPROM".
- *
- * This function makes sure that the I2C EEPROM is programmed
- * correctly.
- *
- * If a VSC7385 microcode image is present, then upload it.
- */
-int misc_init_r(void)
-{
- int rc = 0;
-
-#if defined(CONFIG_SYS_I2C)
- unsigned int orig_bus = i2c_get_bus_num();
- u8 i2c_data;
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
- u8 ds1339_data[17];
-#endif
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- static u8 eeprom_data[] = /* HRCW data */
- {
- 0xAA, 0x55, 0xAA, /* Preamble */
- 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
- 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
- (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
- (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
- (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
- CONFIG_SYS_HRCW_LOW & 0xFF,
- 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
- 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
- (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
- (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
- (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
- CONFIG_SYS_HRCW_HIGH & 0xFF
- };
-
- u8 data[sizeof(eeprom_data)];
-#endif
-
- printf("Board revision: ");
- i2c_set_bus_num(1);
- if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
- printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
- else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
- printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
- else {
- printf("Unknown\n");
- rc = 1;
- }
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- i2c_set_bus_num(0);
-
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
- if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
- if (i2c_write
- (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
- sizeof(eeprom_data)) != 0) {
- puts("Failure writing the HRCW to EEPROM via I2C.\n");
- rc = 1;
- }
- }
- } else {
- puts("Failure reading the HRCW from EEPROM via I2C.\n");
- rc = 1;
- }
-#endif
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
- i2c_set_bus_num(1);
-
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
- == 0) {
-
- /* Work-around for MPC8349E-mITX bug #13601.
- If the RTC does not contain valid register values, the DS1339
- Linux driver will not work.
- */
-
- /* Make sure status register bits 6-2 are zero */
- ds1339_data[0x0f] &= ~0x7c;
-
- /* Check for a valid day register value */
- ds1339_data[0x03] &= ~0xf8;
- if (ds1339_data[0x03] == 0) {
- ds1339_data[0x03] = 1;
- }
-
- /* Check for a valid date register value */
- ds1339_data[0x04] &= ~0xc0;
- if ((ds1339_data[0x04] == 0) ||
- ((ds1339_data[0x04] & 0x0f) > 9) ||
- (ds1339_data[0x04] >= 0x32)) {
- ds1339_data[0x04] = 1;
- }
-
- /* Check for a valid month register value */
- ds1339_data[0x05] &= ~0x60;
-
- if ((ds1339_data[0x05] == 0) ||
- ((ds1339_data[0x05] & 0x0f) > 9) ||
- ((ds1339_data[0x05] >= 0x13)
- && (ds1339_data[0x05] <= 0x19))) {
- ds1339_data[0x05] = 1;
- }
-
- /* Enable Oscillator and rate select */
- ds1339_data[0x0e] = 0x1c;
-
- /* Work-around for MPC8349E-mITX bug #13330.
- Ensure that the RTC control register contains the value 0x1c.
- This affects SATA performance.
- */
-
- if (i2c_write
- (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
- sizeof(ds1339_data))) {
- puts("Failure writing to the RTC via I2C.\n");
- rc = 1;
- }
- } else {
- puts("Failure reading from the RTC via I2C.\n");
- rc = 1;
- }
-#endif
-
- i2c_set_bus_num(orig_bus);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
- CONFIG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- rc = 1;
- }
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
deleted file mode 100644
index afc9df0..0000000
--- a/board/freescale/mpc8349itx/pci.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
- u8 reg8;
-
-#if defined(CONFIG_SYS_I2C)
- i2c_set_bus_num(1);
- /* Read the PCI_M66EN jumper setting */
- if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
- (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
- if (reg8 & I2C_8574_PCI66)
- clk->occr = 0xff000000; /* 66 MHz PCI */
- else
- clk->occr = 0xff600001; /* 33 MHz PCI */
- } else {
- clk->occr = 0xff600001; /* 33 MHz PCI */
- }
-#else
- clk->occr = 0xff000000; /* 66 MHz PCI */
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig
deleted file mode 100644
index 20d29db..0000000
--- a/board/freescale/mpc837xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC837XEMDS
-
-config SYS_BOARD
- default "mpc837xemds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC837XEMDS"
-
-endif
diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
deleted file mode 100644
index 6ff1346..0000000
--- a/board/freescale/mpc837xemds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC837XEMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc837xemds/
-F: include/configs/MPC837XEMDS.h
-F: configs/MPC837XEMDS_defconfig
-F: configs/MPC837XEMDS_HOST_defconfig
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
deleted file mode 100644
index 70b2147..0000000
--- a/board/freescale/mpc837xemds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc837xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README
deleted file mode 100644
index faf21c9..0000000
--- a/board/freescale/mpc837xemds/README
+++ /dev/null
@@ -1,104 +0,0 @@
-Freescale MPC837xEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW4[8] is the bit labeled 8 on Switch 4.
- SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
- SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 For the MPC837xEMDS Processor Board
-
- First, make sure the board default setting is consistent with the
- document shipped with your board. Then apply the following setting:
- SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
- SW4[1-8]= 0000_0110 (core PLL setting)
- SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
- SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
- SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
- J3 2-3, TSEC1 LVDD1 with 2.5V
- J6 2-3, TSEC2 LVDD2 with 2.5V
- J9 2-3, CLKIN from osc on board
- J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
- J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
- mounted, HRCW load from BCSR.
-
- on board Oscillator: 66M
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
- 0xe010_0000 0xe02f_ffff Empty 2M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xe05f_ffff Empty 2M
- 0xe060_0000 0xe060_7fff NAND Flash 32K
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC837XEMDS.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
- CONFIG_MPC837x MPC837x specific
- CONFIG_MPC837XEMDS MPC837XEMDS board specific
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC837XEMDS_config
- make
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp 40000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
- tftp 40000 u-boot.bin
- protect off fe000000 fe1fffff
- erase fe000000 fe1fffff
-
- cp.b 40000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-
-6. Notes
- 1) The console baudrate for MPC837XEMDS is 115200bps.
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
deleted file mode 100644
index 572913c..0000000
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <spd_sdram.h>
-#include <tsec.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <fsl_mdio.h>
-#include <phy.h>
-#include "pci.h"
-#include "../common/pq-mds-pib.h"
-
-int board_early_init_f(void)
-{
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[0x9] &= ~0x04;
- /* Clear all of the interrupt of BCSR */
- bcsr[0xe] = 0xff;
-
-#ifdef CONFIG_FSL_SERDES
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u32 spridr = in_be32(&immr->sysconf.spridr);
-
- /* we check only part num, and don't look for CPU revisions */
- switch (PARTID_NO_E(spridr)) {
- case SPR_8377:
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- case SPR_8378:
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
- FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
- break;
- case SPR_8379:
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- default:
- printf("serdes not configured: unknown CPU part number: "
- "%04x\n", spridr >> 16);
- break;
- }
-#endif /* CONFIG_FSL_SERDES */
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bd)
-{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
- if (!hwconfig("esdhc"))
- return 0;
-
- /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
- bcsr[0xc] |= 0x4c;
-
- /* Set proper bits in SICR to allow SD signals through */
- clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
- clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
- SICRH_GPIO2_E_SD | SICRH_SPI_SD);
-
- return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
-int board_eth_init(bd_t *bd)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- u32 rcwh = in_be32(&im->reset.rcwh);
- u32 tsec_mode;
- int num = 0;
-
- /* New line after Net: */
- printf("\n");
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
-
- printf(CONFIG_TSEC1_NAME ": ");
-
- tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
- if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
- printf("RGMII\n");
- /* this is default, no need to fixup */
- } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
- printf("SGMII\n");
- tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
- tsec_info[num].flags = TSEC_GIGABIT;
- } else {
- printf("unsupported PHY type\n");
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
-
- printf(CONFIG_TSEC2_NAME ": ");
-
- tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
- if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
- printf("RGMII\n");
- /* this is default, no need to fixup */
- } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
- printf("SGMII\n");
- tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
- tsec_info[num].flags = TSEC_GIGABIT;
- } else {
- printf("unsupported PHY type\n");
- }
- num++;
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bd, &mdio_info);
-
- return tsec_eth_init(bd, tsec_info, num);
-}
-
-static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
- int phy_addr)
-{
- const u32 *ph;
- int off;
- int err;
-
- off = fdt_path_offset(blob, alias);
- if (off < 0) {
- printf("WARNING: could not find %s alias: %s.\n", alias,
- fdt_strerror(off));
- return;
- }
-
- err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
-
- if (err) {
- printf("WARNING: could not set phy-connection-type for %s: "
- "%s.\n", alias, fdt_strerror(err));
- return;
- }
-
- ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
- if (!ph) {
- printf("WARNING: could not get phy-handle for %s.\n",
- alias);
- return;
- }
-
- off = fdt_node_offset_by_phandle(blob, *ph);
- if (off < 0) {
- printf("WARNING: could not get phy node for %s: %s\n", alias,
- fdt_strerror(off));
- return;
- }
-
- phy_addr = cpu_to_fdt32(phy_addr);
- err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
- if (err < 0) {
- printf("WARNING: could not set phy node's reg for %s: "
- "%s.\n", alias, fdt_strerror(err));
- return;
- }
-}
-
-static void ft_tsec_fixup(void *blob, bd_t *bd)
-{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- u32 rcwh = in_be32(&im->reset.rcwh);
- u32 tsec_mode;
-
-#ifdef CONFIG_TSEC1
- tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
- if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
- __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
-#endif
-
-#ifdef CONFIG_TSEC2
- tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
- if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
- __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
-#endif
-}
-#else
-static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
-#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- return 0;
-}
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize DDR ECC byte */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* return total bus DDR size(bytes) */
- return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
-#if (CONFIG_SYS_DDR_SIZE != 512)
-#warning Currenly any ddr size other than 512 is not supported
-#endif
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
- udelay(50000);
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- udelay(1000);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- udelay(1000);
-
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__("sync");
- udelay(1000);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- udelay(2000);
- return CONFIG_SYS_DDR_SIZE;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC837xEMDS\n");
- return 0;
-}
-
-#ifdef CONFIG_PCI
-int board_pci_host_broken(void)
-{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
-
- /* It's always OK in case of external arbiter. */
- if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
- return 0;
-
- if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
- return 1;
-
- return 0;
-}
-
-static void ft_pci_fixup(void *blob, bd_t *bd)
-{
- const char *status = "broken (no arbiter)";
- int off;
- int err;
-
- off = fdt_path_offset(blob, "pci0");
- if (off < 0) {
- printf("WARNING: could not find pci0 alias: %s.\n",
- fdt_strerror(off));
- return;
- }
-
- err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
- if (err) {
- printf("WARNING: could not set status for pci0: %s.\n",
- fdt_strerror(err));
- return;
- }
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- ft_tsec_fixup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
- fdt_fixup_esdhc(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
- if (board_pci_host_broken())
- ft_pci_fixup(blob, bd);
- ft_pcie_fixup(blob, bd);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
deleted file mode 100644
index 39c40e5..0000000
--- a/board/freescale/mpc837xemds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/fsl_i2c.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI_MEM_BASE,
- phys_start: CONFIG_SYS_PCI_MEM_PHYS,
- size: CONFIG_SYS_PCI_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
- size: CONFIG_SYS_PCI_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI_IO_BASE,
- phys_start: CONFIG_SYS_PCI_IO_PHYS,
- size: CONFIG_SYS_PCI_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static int is_pex_x2(void)
-{
- const char *pex_x2 = getenv("pex_x2");
-
- if (pex_x2 && !strcmp(pex_x2, "yes"))
- return 1;
- return 0;
-}
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
- u32 spridr = in_be32(&immr->sysconf.spridr);
- int pex2 = is_pex_x2();
-
- if (board_pci_host_broken())
- goto skip_pci;
-
- /* Enable all 5 PCI_CLK_OUTPUTS */
- clk->occr |= 0xf8000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- udelay(2000);
-
- mpc83xx_pci_init(1, reg);
-skip_pci:
- /* There is no PEX in MPC8379 parts. */
- if (PARTID_NO_E(spridr) == SPR_8379)
- return;
-
- if (pex2)
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- else
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
- /* Configure the clock for PCIE controller */
- clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
- SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- if (!pex2)
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
-}
-
-void ft_pcie_fixup(void *blob, bd_t *bd)
-{
- const char *status = "disabled (PCIE1 is x2)";
-
- if (!is_pex_x2())
- return;
-
- do_fixup_by_path(blob, "pci2", "status", status,
- strlen(status) + 1, 1);
-}
diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h
deleted file mode 100644
index fd7a916..0000000
--- a/board/freescale/mpc837xemds/pci.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BOARD_MPC837XEMDS_PCI_H
-#define __BOARD_MPC837XEMDS_PCI_H
-
-extern void ft_pcie_fixup(void *blob, bd_t *bd);
-
-#endif /* __BOARD_MPC837XEMDS_PCI_H */
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
deleted file mode 100644
index 64717ec..0000000
--- a/configs/MPC8308RDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8308RDB=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
deleted file mode 100644
index ca6c304..0000000
--- a/configs/MPC8313ERDB_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
deleted file mode 100644
index 974bdf9..0000000
--- a/configs/MPC8313ERDB_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
deleted file mode 100644
index ba81885..0000000
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
deleted file mode 100644
index afe8740..0000000
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
deleted file mode 100644
index ebebbed..0000000
--- a/configs/MPC8315ERDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8315ERDB=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
deleted file mode 100644
index 7c03842..0000000
--- a/configs/MPC8323ERDB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8323ERDB=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
deleted file mode 100644
index e1ba08d..0000000
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
deleted file mode 100644
index 55df0f6..0000000
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
deleted file mode 100644
index 1ceee68..0000000
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
deleted file mode 100644
index ef67be5..0000000
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
deleted file mode 100644
index 0398472..0000000
--- a/configs/MPC832XEMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC832XEMDS=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
deleted file mode 100644
index f6af218..0000000
--- a/configs/MPC8349EMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349EMDS=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
deleted file mode 100644
index f853309..0000000
--- a/configs/MPC8349ITXGP_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
deleted file mode 100644
index 5321801..0000000
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
deleted file mode 100644
index 83f25ae..0000000
--- a/configs/MPC8349ITX_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8349ITX=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
deleted file mode 100644
index d3be43a..0000000
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PCI"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XEMDS=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
deleted file mode 100644
index d3b7c1d..0000000
--- a/configs/MPC837XEMDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XEMDS=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 59d2142..b8c9f9c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,14 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+MPC8308RDB powerpc mpc83xx - - Ilya Yanok <yanok@emcraft.com>
+MPC8313ERDB powerpc mpc83xx - -
+MPC8315ERDB powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
+MPC8323ERDB powerpc mpc83xx - - Michael Barkowski <michael.barkowski@freescale.com>
+MPC832XEMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
+MPC8349EMDS powerpc mpc83xx - - Kim Phillips <kim.phillips@freescale.com>
+MPC8349ITX powerpc mpc83xx - -
+MPC837XEMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
deleted file mode 100644
index bf974fd..0000000
--- a/include/configs/MPC8308RDB.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_MISC_INIT_R
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ESDHC_USE_PIO
-
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * On-board devices
- *
- * TSEC1 is SoC TSEC
- * TSEC2 is VSC switch
- */
-#define CONFIG_TSEC1
-#define CONFIG_VSC7385_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_TSEC2 |\
- SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_CRS |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * SERDES
- */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1 0xe3000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_LOZ \
- | DDRCDR_NZ_LOZ \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (6 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (4 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-/* 127 64KB sectors and 8 8KB top sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit Port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
- /* VSC7385 Base address on CS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8-bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
- /* 0xFFFE09FF */
-/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-/* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-#endif
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * SPI on header J8
- *
- * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
- * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
- */
-#ifdef CONFIG_MPC8XXX_SPI
-#define CONFIG_CMD_SPI
-#define CONFIG_USE_SPIFLASH
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#endif
-
-/*
- * Board info - revision and where boot from
- */
-#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-/* enable PCIE clock */
-#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC0"
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${consoledev},${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "kernel_addr=FE080000\0" \
- "fdt_addr=FE280000\0" \
- "ramdisk_addr=FE290000\0" \
- "u-boot=mpc8308rdb/u-boot.bin\0" \
- "kernel_addr_r=1000000\0" \
- "fdt_addr_r=C00000\0" \
- "hostname=mpc8308rdb\0" \
- "bootfile=mpc8308rdb/uImage\0" \
- "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
- "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${fdt_addr_r} ${fdtfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "bootcmd=run flash_self\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
- " +${filesize};cp.b ${fileaddr} " \
- __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
deleted file mode 100644
index dd81229..0000000
--- a/include/configs/MPC8313ERDB.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
-#define CONFIG_MPC8313ERDB 1
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0x4000
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif
-
-#endif /* CONFIG_NAND */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00001000
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (10 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32 \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0632 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
- /* 0xFF006FF7 TODO SLOW 16 MB flash size */
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
- /* 16 MB window size */
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
-
-/* drivers/mtd/nand/nand.c */
-#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=e2800000.flash"
-#define MTDPARTS_DEFAULT \
- "mtdparts=e2800000.flash:512k(uboot),128k(env),3m at 1m(kernel),-(fs)"
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR 0xFA000000
-#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
- /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFF8FF7 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
- /* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFE09FF */
-
- /* Access window base@VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-#define CONFIG_MPC83XX_GPIO 1
-#define CONFIG_CMD_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_5X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
- /* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME mpc8313erdb
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
deleted file mode 100644
index 98e9072..0000000
--- a/include/configs/MPC8315ERDB.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC831x 1 /* MPC831x CPU family */
-#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
-#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_HWCONFIG
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_LOZ \
- | DDRCDR_NZ_LOZ \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (6 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (4 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00140000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-#define CONFIG_FSL_ELBC 1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-/* 127 64KB sectors and 8 8KB top sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE0600000
-#endif
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=e0600000.flash"
-#define MTDPARTS_DEFAULT \
- "mtdparts=e0600000.flash:512k(uboot),128k(env),3m at 1m(kernel),-(fs)"
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
- !defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Board info - revision and where boot from
- */
-#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#define CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_SYS_SCCR_USBDRCM 3
-
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_PHY_TYPE "utmi"
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * Environment
- */
-#if !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_128M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#define CONFIG_SYS_IBAT6L 0
-#define CONFIG_SYS_IBAT6U 0
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc8315erdb.dtb\0" \
- "usb_phy_type=utmi\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
deleted file mode 100644
index 65a63e2..0000000
--- a/include/configs/MPC8323ERDB.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_PCI 1
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2_5X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT 1
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 64 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_9)
- /* 0x80010101 */
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (3 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x26253222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (31 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x1f9048c7 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x03f00000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
- /* Window base@flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE006FF7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board EEPROM
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 4
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-#define CONFIG_UEC_ETH2 /* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ASKENV
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if (CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#else
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#endif
-
-/* Nothing in BAT7 */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#if (CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
-#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
-
-/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
- * (see CONFIG_SYS_I2C_EEPROM) */
- /* MAC address offset in I2C EEPROM */
-#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME mpc8323erdb
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
-#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftp $loadaddr $uboot;" \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off "\
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
deleted file mode 100644
index 1735b3c..0000000
--- a/include/configs/MPC832XEMDS.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
-#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL 0x00000000
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_AP \
- | CSCONFIG_ODT_WR_CFG \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80840102 */
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3935D322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (31 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x0F9048CA */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe006ff7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
-
-/*
- * Windows to access PIB via local bus
- */
- /* PIB window base 0xF8008000 */
-#define CONFIG_SYS_PIB_BASE 0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
-
-/*
- * CS2 on Local Bus, to PIB
- */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * CS3 on Local Bus, to PIB
- */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 3
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-#define CONFIG_UEC_ETH2 /* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */ #define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc832x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
deleted file mode 100644
index 6b7d648..0000000
--- a/include/configs/MPC8349EMDS.h
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mpc8349emds board configuration file
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_PCI
-#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-
-/*
- * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
- * undefine it to use old spd_sdram.c
- */
-#define CONFIG_SYS_FSL_DDR2
-#ifdef CONFIG_SYS_FSL_DDR2
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x52
-#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#endif
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef CONFIG_DDR_2T_TIMING
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
-
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x47d00432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#else
-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_1 0x36332321
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
-
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
- /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000023
-#else
-/* the default burst length is 4 - for 64-bit data path */
- /* DLL,normal,seq,4/2.5, 4 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#endif
-#endif
-#endif
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
- */
-#define CONFIG_SYS_BCSR 0xE2400000
- /* Access window base@BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
- /* 0xFFFFE8F0 */
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
- */
-#undef CONFIG_SYS_LB_SDRAM
-
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 /* 32-bit port */ \
- | BR_MS_SDRAM /* MSEL = SDRAM */ \
- | BR_V) /* Valid */
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* SPI */
-#define CONFIG_MPC8XXX_SPI
-#undef CONFIG_SOFT_SPI /* SPI bit-banged */
-
-/* GPIOs. Used as SPI chip selects */
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
-#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/* USB */
-#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif /* PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL (\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST) */
-
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_HOSTNAME mpc8349emds
-#define CONFIG_ROOTPATH "/nfsroot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=mpc8349emds\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
- "update=protect off fe000000 fe03ffff; " \
- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc834x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
deleted file mode 100644
index 398918a..0000000
--- a/include/configs/MPC8349ITX.h
+++ /dev/null
@@ -1,806 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
-
- Memory map:
-
- 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
- 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
- 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
- 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
- 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
- 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
- 0xF001_0000-0xF001_FFFF Local bus expansion slot
- 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
- 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
- 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
-
- I2C address list:
- Align. Board
- Bus Addr Part No. Description Length Location
- ----------------------------------------------------------------
- I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
-
- I2C1 0x20 PCF8574 I2C Expander 0 U8
- I2C1 0x21 PCF8574 I2C Expander 0 U10
- I2C1 0x38 PCF8574A I2C Expander 0 U8
- I2C1 0x39 PCF8574A I2C Expander 0 U10
- I2C1 0x51 (DDR) DDR EEPROM 1 U1
- I2C1 0x68 DS1339 RTC 1 U68
-
- Note that a given board has *either* a pair of 8574s or a pair of 8574As.
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349 /* MPC8349 specific */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFEF00000
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
-
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-
-#ifdef CONFIG_MPC8349ITX
-/* The CF card interface on the back of the board */
-#define CONFIG_COMPACT_FLASH
-#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
-#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
-#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C
-#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
-
-/*
- * Device configurations
- */
-
-/* I2C */
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
-
-#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
-
-/* Don't probe these addresses: */
-#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
- {1, CONFIG_SYS_I2C_8574_ADDR2}, \
- {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
- {1, CONFIG_SYS_I2C_8574A_ADDR2} }
-/* Bit definitions for the 8574[A] I2C expander */
- /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
-#define I2C_8574_REVISION 0x03
-#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
-#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
-#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
-#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
-
-#endif
-
-/* Compact Flash */
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
-#define CONFIG_SYS_ATA_STRIDE 2
-
-/* If a CF card is not inserted, time out quickly */
-#define ATA_RESET_TIME 1
-
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_SATA_SIL3114
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 4
-#define CONFIG_LIBATA
-#define CONFIG_LBA48
-
-#endif
-
-#ifdef CONFIG_SYS_USB_HOST
-/*
- * Support USB
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-
-/* Current USB implementation supports the only USB controller,
- * so we have to choose between the MPH or the DR ones */
-#if 1
-#define CONFIG_HAS_FSL_MPH_USB
-#else
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x2000
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
-
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-#endif
-
-/* No SPD? Then manually set up DDR parameters */
-#ifndef CONFIG_SPD_EEPROM
- #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
- #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-
- #define CONFIG_SYS_DDR_TIMING_1 0x26242321
- #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
-#endif
-
-/*
- *Flash on the Local Bus
- */
-
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* 127 64KB sectors + 8 8KB sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-/* The ITX has two flash chips, but the ITX-GP has only one. To support both
-boards, we say we have two, but don't display a message if we find only one. */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC2
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFEFFE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * BRx, ORx, LBLAWBARx, and LBLAWARx
- */
-
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
-
-/* Vitesse 7385 */
-
-#define CONFIG_SYS_VSC7385_BASE 0xF8000000
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-/* LED */
-
-#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-/* Compact Flash */
-
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_CF_BASE 0xF0000000
-
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
-
-#endif
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE ttyS0
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_MPC83XX_PCI2
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE \
- (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE \
- (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE \
- (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS \
- (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
-#endif
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR 0x00000000
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
- #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
-
-/* TSEC */
-
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
-
-#define CONFIG_TSEC1
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
-#define TSEC1_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_PHYIDX 0
-#define TSEC2_FLAGS TSEC_GIGABIT
-#endif
-
-#define CONFIG_ETHPRIME "Freescale TSEC"
-
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_OVERWRITE
-
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
- #undef CONFIG_FLASH_CFI_DRIVER
- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
- || defined(CONFIG_USB_STORAGE)
- #define CONFIG_DOS_PARTITION
- #define CONFIG_CMD_FAT
- #define CONFIG_SUPPORT_VFAT
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
- #define CONFIG_CMD_IDE
-#endif
-
-#ifdef CONFIG_SATA_SIL3114
- #define CONFIG_CMD_SATA
-#endif
-
-#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
- #define CONFIG_CMD_EXT2
-#endif
-
-#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
-#endif
-
-#ifdef CONFIG_SYS_I2C
- #define CONFIG_CMD_I2C
-#endif
-
-/* Watchdog */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
-#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
-
-/*
- * System IO Config
- */
-/* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRH SICRH_TSOBI1
- /* USB DR as device + USB MPH as host */
-#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
-
-#define CONFIG_SYS_HID0_INIT 0x00000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_IBAT4L 0
-#define CONFIG_SYS_IBAT4U 0
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth0"
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_HOSTNAME "mpc8349emitx"
-#else
-#define CONFIG_HOSTNAME "mpc8349emitxgp"
-#endif
-
-/* Default path and filenames */
-#define CONFIG_ROOTPATH "/nfsroot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_FDTFILE "mpc8349emitx.dtb"
-#else
-#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
-#endif
-
-#define CONFIG_BOOTDELAY 6
-
-#define CONFIG_BOOTARGS \
- "root=/dev/nfs rw" \
- " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
- " ip=" __stringify(CONFIG_IPADDR) ":" \
- __stringify(CONFIG_SERVERIP) ":" \
- __stringify(CONFIG_GATEWAYIP) ":" \
- __stringify(CONFIG_NETMASK) ":" \
- CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
- " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" __stringify(CONFIG_CONSOLE) "\0" \
- "netdev=" CONFIG_NETDEV "\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
- " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
- " console=$console,$baudrate $othbootargs; " \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw" \
- " console=$console,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
deleted file mode 100644
index 832c10f..0000000
--- a/include/configs/MPC837XEMDS.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_6X1 |\
- HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#endif
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
-
-/*
- * IP blocks clock configuration
- */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR 0x31100000
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_HWCONFIG
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */ /* ODT 150ohm on SoC */
-
-#undef CONFIG_DDR_ECC /* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
-
-#if defined(CONFIG_SPD_EEPROM)
-#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
-#else
-/*
- * Manually set up DDR parameters
- * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
- * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
- */
-#define CONFIG_SYS_DDR_SIZE 512 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
- | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
- | CSCONFIG_ROW_BIT_14 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010202 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00620802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3935d322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (6 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x131088c8 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03E00100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x1432 << SDRAM_MODE_SD_SHIFT))
- /* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00140000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_FSL_ELBC 1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE000FF7 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_CMD_NAND 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-
-#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
- | OR_FCM_BCTLD \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_RST \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF919E */
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#ifndef __ASSEMBLY__
-extern int board_pci_host_broken(void);
-#endif
-#define CONFIG_PCIE
-#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
-
-#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 3
-#define TSEC1_PHY_ADDR_SGMII 8
-#define TSEC2_PHY_ADDR_SGMII 4
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_FSL_SERDES2 0xe3100
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc8379_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards
2015-03-17 3:28 ` [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards Masahiro Yamada
@ 2015-03-17 6:07 ` Sinan Akman
2015-03-17 12:28 ` Masahiro Yamada
2015-03-17 13:15 ` Tom Rini
2015-03-17 17:00 ` [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD (was: [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards) Kim Phillips
1 sibling, 2 replies; 22+ messages in thread
From: Sinan Akman @ 2015-03-17 6:07 UTC (permalink / raw)
To: u-boot
Hi Masahiro
On 03/16/2015 11:28 PM, Masahiro Yamada wrote:
> Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
> MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
I had sent an e-mail on that few weeks ago :
http://lists.denx.de/pipermail/u-boot/2015-February/203613.html
I am receiving the boards from FSL and I would like to
take over the maintainership of MPC8323ERDB and MPC8308RDB
boards. I should have them in about a week.
Could you please delay the removal of those two boards
to give me a bit time to test generic board changes on the
actual board. I really like to keep those boards supported.
Thanks much
Sinan Akman
>
> They have not been converted to Generic Board, so should be removed.
> (See doc/README.generic-board for details.)
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Ilya Yanok <yanok@emcraft.com>
> Cc: Dave Liu <daveliu@freescale.com>
> Cc: Michael Barkowski <michael.barkowski@freescale.com>
> Cc: Kim Phillips <kim.phillips@freescale.com>
> ---
>
> arch/powerpc/cpu/mpc83xx/Kconfig | 33 --
> board/freescale/common/pq-mds-pib.c | 26 -
> board/freescale/mpc8308rdb/Kconfig | 12 -
> board/freescale/mpc8308rdb/MAINTAINERS | 6 -
> board/freescale/mpc8308rdb/Makefile | 10 -
> board/freescale/mpc8308rdb/mpc8308rdb.c | 192 -------
> board/freescale/mpc8308rdb/sdram.c | 81 ---
> board/freescale/mpc8313erdb/Kconfig | 12 -
> board/freescale/mpc8313erdb/MAINTAINERS | 9 -
> board/freescale/mpc8313erdb/Makefile | 8 -
> board/freescale/mpc8313erdb/README | 111 ----
> board/freescale/mpc8313erdb/mpc8313erdb.c | 157 ------
> board/freescale/mpc8313erdb/sdram.c | 124 -----
> board/freescale/mpc8315erdb/Kconfig | 12 -
> board/freescale/mpc8315erdb/MAINTAINERS | 6 -
> board/freescale/mpc8315erdb/Makefile | 8 -
> board/freescale/mpc8315erdb/README | 105 ----
> board/freescale/mpc8315erdb/mpc8315erdb.c | 246 ---------
> board/freescale/mpc8315erdb/sdram.c | 111 ----
> board/freescale/mpc8323erdb/Kconfig | 12 -
> board/freescale/mpc8323erdb/MAINTAINERS | 6 -
> board/freescale/mpc8323erdb/Makefile | 8 -
> board/freescale/mpc8323erdb/README | 71 ---
> board/freescale/mpc8323erdb/mpc8323erdb.c | 222 --------
> board/freescale/mpc832xemds/Kconfig | 12 -
> board/freescale/mpc832xemds/MAINTAINERS | 10 -
> board/freescale/mpc832xemds/Makefile | 9 -
> board/freescale/mpc832xemds/README | 128 -----
> board/freescale/mpc832xemds/mpc832xemds.c | 166 ------
> board/freescale/mpc832xemds/pci.c | 146 ------
> board/freescale/mpc8349emds/Kconfig | 12 -
> board/freescale/mpc8349emds/MAINTAINERS | 6 -
> board/freescale/mpc8349emds/Makefile | 10 -
> board/freescale/mpc8349emds/ddr.c | 101 ----
> board/freescale/mpc8349emds/mpc8349emds.c | 285 -----------
> board/freescale/mpc8349emds/pci.c | 192 -------
> board/freescale/mpc8349itx/Kconfig | 12 -
> board/freescale/mpc8349itx/MAINTAINERS | 8 -
> board/freescale/mpc8349itx/Makefile | 8 -
> board/freescale/mpc8349itx/README | 187 -------
> board/freescale/mpc8349itx/mpc8349itx.c | 390 --------------
> board/freescale/mpc8349itx/pci.c | 105 ----
> board/freescale/mpc837xemds/Kconfig | 12 -
> board/freescale/mpc837xemds/MAINTAINERS | 7 -
> board/freescale/mpc837xemds/Makefile | 9 -
> board/freescale/mpc837xemds/README | 104 ----
> board/freescale/mpc837xemds/mpc837xemds.c | 346 -------------
> board/freescale/mpc837xemds/pci.c | 147 ------
> board/freescale/mpc837xemds/pci.h | 6 -
> configs/MPC8308RDB_defconfig | 3 -
> configs/MPC8313ERDB_33_defconfig | 4 -
> configs/MPC8313ERDB_66_defconfig | 4 -
> configs/MPC8313ERDB_NAND_33_defconfig | 5 -
> configs/MPC8313ERDB_NAND_66_defconfig | 5 -
> configs/MPC8315ERDB_defconfig | 3 -
> configs/MPC8323ERDB_defconfig | 3 -
> configs/MPC832XEMDS_ATM_defconfig | 4 -
> configs/MPC832XEMDS_HOST_33_defconfig | 4 -
> configs/MPC832XEMDS_HOST_66_defconfig | 4 -
> configs/MPC832XEMDS_SLAVE_defconfig | 4 -
> configs/MPC832XEMDS_defconfig | 3 -
> configs/MPC8349EMDS_defconfig | 3 -
> configs/MPC8349ITXGP_defconfig | 4 -
> configs/MPC8349ITX_LOWBOOT_defconfig | 4 -
> configs/MPC8349ITX_defconfig | 4 -
> configs/MPC837XEMDS_HOST_defconfig | 4 -
> configs/MPC837XEMDS_defconfig | 3 -
> doc/README.scrapyard | 8 +
> include/configs/MPC8308RDB.h | 582 ---------------------
> include/configs/MPC8313ERDB.h | 719 --------------------------
> include/configs/MPC8315ERDB.h | 659 ------------------------
> include/configs/MPC8323ERDB.h | 555 --------------------
> include/configs/MPC832XEMDS.h | 624 -----------------------
> include/configs/MPC8349EMDS.h | 810 ------------------------------
> include/configs/MPC8349ITX.h | 806 -----------------------------
> include/configs/MPC837XEMDS.h | 719 --------------------------
> 76 files changed, 8 insertions(+), 9548 deletions(-)
> delete mode 100644 board/freescale/mpc8308rdb/Kconfig
> delete mode 100644 board/freescale/mpc8308rdb/MAINTAINERS
> delete mode 100644 board/freescale/mpc8308rdb/Makefile
> delete mode 100644 board/freescale/mpc8308rdb/mpc8308rdb.c
> delete mode 100644 board/freescale/mpc8308rdb/sdram.c
> delete mode 100644 board/freescale/mpc8313erdb/Kconfig
> delete mode 100644 board/freescale/mpc8313erdb/MAINTAINERS
> delete mode 100644 board/freescale/mpc8313erdb/Makefile
> delete mode 100644 board/freescale/mpc8313erdb/README
> delete mode 100644 board/freescale/mpc8313erdb/mpc8313erdb.c
> delete mode 100644 board/freescale/mpc8313erdb/sdram.c
> delete mode 100644 board/freescale/mpc8315erdb/Kconfig
> delete mode 100644 board/freescale/mpc8315erdb/MAINTAINERS
> delete mode 100644 board/freescale/mpc8315erdb/Makefile
> delete mode 100644 board/freescale/mpc8315erdb/README
> delete mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c
> delete mode 100644 board/freescale/mpc8315erdb/sdram.c
> delete mode 100644 board/freescale/mpc8323erdb/Kconfig
> delete mode 100644 board/freescale/mpc8323erdb/MAINTAINERS
> delete mode 100644 board/freescale/mpc8323erdb/Makefile
> delete mode 100644 board/freescale/mpc8323erdb/README
> delete mode 100644 board/freescale/mpc8323erdb/mpc8323erdb.c
> delete mode 100644 board/freescale/mpc832xemds/Kconfig
> delete mode 100644 board/freescale/mpc832xemds/MAINTAINERS
> delete mode 100644 board/freescale/mpc832xemds/Makefile
> delete mode 100644 board/freescale/mpc832xemds/README
> delete mode 100644 board/freescale/mpc832xemds/mpc832xemds.c
> delete mode 100644 board/freescale/mpc832xemds/pci.c
> delete mode 100644 board/freescale/mpc8349emds/Kconfig
> delete mode 100644 board/freescale/mpc8349emds/MAINTAINERS
> delete mode 100644 board/freescale/mpc8349emds/Makefile
> delete mode 100644 board/freescale/mpc8349emds/ddr.c
> delete mode 100644 board/freescale/mpc8349emds/mpc8349emds.c
> delete mode 100644 board/freescale/mpc8349emds/pci.c
> delete mode 100644 board/freescale/mpc8349itx/Kconfig
> delete mode 100644 board/freescale/mpc8349itx/MAINTAINERS
> delete mode 100644 board/freescale/mpc8349itx/Makefile
> delete mode 100644 board/freescale/mpc8349itx/README
> delete mode 100644 board/freescale/mpc8349itx/mpc8349itx.c
> delete mode 100644 board/freescale/mpc8349itx/pci.c
> delete mode 100644 board/freescale/mpc837xemds/Kconfig
> delete mode 100644 board/freescale/mpc837xemds/MAINTAINERS
> delete mode 100644 board/freescale/mpc837xemds/Makefile
> delete mode 100644 board/freescale/mpc837xemds/README
> delete mode 100644 board/freescale/mpc837xemds/mpc837xemds.c
> delete mode 100644 board/freescale/mpc837xemds/pci.c
> delete mode 100644 board/freescale/mpc837xemds/pci.h
> delete mode 100644 configs/MPC8308RDB_defconfig
> delete mode 100644 configs/MPC8313ERDB_33_defconfig
> delete mode 100644 configs/MPC8313ERDB_66_defconfig
> delete mode 100644 configs/MPC8313ERDB_NAND_33_defconfig
> delete mode 100644 configs/MPC8313ERDB_NAND_66_defconfig
> delete mode 100644 configs/MPC8315ERDB_defconfig
> delete mode 100644 configs/MPC8323ERDB_defconfig
> delete mode 100644 configs/MPC832XEMDS_ATM_defconfig
> delete mode 100644 configs/MPC832XEMDS_HOST_33_defconfig
> delete mode 100644 configs/MPC832XEMDS_HOST_66_defconfig
> delete mode 100644 configs/MPC832XEMDS_SLAVE_defconfig
> delete mode 100644 configs/MPC832XEMDS_defconfig
> delete mode 100644 configs/MPC8349EMDS_defconfig
> delete mode 100644 configs/MPC8349ITXGP_defconfig
> delete mode 100644 configs/MPC8349ITX_LOWBOOT_defconfig
> delete mode 100644 configs/MPC8349ITX_defconfig
> delete mode 100644 configs/MPC837XEMDS_HOST_defconfig
> delete mode 100644 configs/MPC837XEMDS_defconfig
> delete mode 100644 include/configs/MPC8308RDB.h
> delete mode 100644 include/configs/MPC8313ERDB.h
> delete mode 100644 include/configs/MPC8315ERDB.h
> delete mode 100644 include/configs/MPC8323ERDB.h
> delete mode 100644 include/configs/MPC832XEMDS.h
> delete mode 100644 include/configs/MPC8349EMDS.h
> delete mode 100644 include/configs/MPC8349ITX.h
> delete mode 100644 include/configs/MPC837XEMDS.h
>
> diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
> index 4d6cb09..a7ff0d4 100644
> --- a/arch/powerpc/cpu/mpc83xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc83xx/Kconfig
> @@ -19,31 +19,6 @@ config TARGET_VE8313
> config TARGET_VME8349
> bool "Support vme8349"
>
> -config TARGET_MPC8308RDB
> - bool "Support MPC8308RDB"
> -
> -config TARGET_MPC8313ERDB
> - bool "Support MPC8313ERDB"
> - select SUPPORT_SPL
> -
> -config TARGET_MPC8315ERDB
> - bool "Support MPC8315ERDB"
> -
> -config TARGET_MPC8323ERDB
> - bool "Support MPC8323ERDB"
> -
> -config TARGET_MPC832XEMDS
> - bool "Support MPC832XEMDS"
> -
> -config TARGET_MPC8349EMDS
> - bool "Support MPC8349EMDS"
> -
> -config TARGET_MPC8349ITX
> - bool "Support MPC8349ITX"
> -
> -config TARGET_MPC837XEMDS
> - bool "Support MPC837XEMDS"
> -
> config TARGET_MPC837XERDB
> bool "Support MPC837XERDB"
>
> @@ -68,14 +43,6 @@ config TARGET_HRCON
> endchoice
>
> source "board/esd/vme8349/Kconfig"
> -source "board/freescale/mpc8308rdb/Kconfig"
> -source "board/freescale/mpc8313erdb/Kconfig"
> -source "board/freescale/mpc8315erdb/Kconfig"
> -source "board/freescale/mpc8323erdb/Kconfig"
> -source "board/freescale/mpc832xemds/Kconfig"
> -source "board/freescale/mpc8349emds/Kconfig"
> -source "board/freescale/mpc8349itx/Kconfig"
> -source "board/freescale/mpc837xemds/Kconfig"
> source "board/freescale/mpc837xerdb/Kconfig"
> source "board/ids/ids8313/Kconfig"
> source "board/keymile/km83xx/Kconfig"
> diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
> index 1eb3786..4313ac3 100644
> --- a/board/freescale/common/pq-mds-pib.c
> +++ b/board/freescale/common/pq-mds-pib.c
> @@ -36,11 +36,7 @@ int pib_init(void)
> i2c_write(0x26, 0x6, 1, &val8, 1);
> val8 = 0x34;
> i2c_write(0x26, 0x7, 1, &val8, 1);
> -#if defined(CONFIG_MPC832XEMDS)
> - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
> -#else
> val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
> -#endif
> i2c_write(0x26, 0x2, 1, &val8, 1);
> val8 = 0xff;
> i2c_write(0x26, 0x3, 1, &val8, 1);
> @@ -55,12 +51,8 @@ int pib_init(void)
>
> eieio();
>
> -#if defined(CONFIG_MPC832XEMDS)
> - printf("PCI 32bit bus on PMC2 &PMC3\n");
> -#else
> printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
> #endif
> -#endif
>
> #if defined(CONFIG_PQ_MDS_PIB_ATM)
> #if defined(CONFIG_MPC8569MDS)
> @@ -76,24 +68,6 @@ int pib_init(void)
> eieio();
>
> printf("QOC3 ATM card on PMC0\n");
> -#elif defined(CONFIG_MPC832XEMDS)
> - val8 = 0;
> - i2c_write(0x26, 0x7, 1, &val8, 1);
> - val8 = 0xf7;
> - i2c_write(0x26, 0x3, 1, &val8, 1);
> -
> - val8 = 0;
> - i2c_write(0x21, 0x6, 1, &val8, 1);
> - i2c_write(0x21, 0x7, 1, &val8, 1);
> -
> - val8 = 0xdf;
> - i2c_write(0x21, 0x2, 1, &val8, 1);
> - val8 = 0xef;
> - i2c_write(0x21, 0x3, 1, &val8, 1);
> -
> - eieio();
> -
> - printf("QOC3 ATM card on PMC1\n");
> #endif
> #endif
> /* Reset to original I2C bus */
> diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig
> deleted file mode 100644
> index 48d25e5..0000000
> --- a/board/freescale/mpc8308rdb/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8308RDB
> -
> -config SYS_BOARD
> - default "mpc8308rdb"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8308RDB"
> -
> -endif
> diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS
> deleted file mode 100644
> index 07ff2abd..0000000
> --- a/board/freescale/mpc8308rdb/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MPC8308RDB BOARD
> -M: Ilya Yanok <yanok@emcraft.com>
> -S: Maintained
> -F: board/freescale/mpc8308rdb/
> -F: include/configs/MPC8308RDB.h
> -F: configs/MPC8308RDB_defconfig
> diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
> deleted file mode 100644
> index ec2b85d..0000000
> --- a/board/freescale/mpc8308rdb/Makefile
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -# (C) Copyright 2010
> -# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := mpc8308rdb.o sdram.o
> diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
> deleted file mode 100644
> index 93e1c50..0000000
> --- a/board/freescale/mpc8308rdb/mpc8308rdb.c
> +++ /dev/null
> @@ -1,192 +0,0 @@
> -/*
> - * Copyright (C) 2010 Freescale Semiconductor, Inc.
> - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <hwconfig.h>
> -#include <i2c.h>
> -#include <spi.h>
> -#include <libfdt.h>
> -#include <fdt_support.h>
> -#include <pci.h>
> -#include <mpc83xx.h>
> -#include <vsc7385.h>
> -#include <netdev.h>
> -#include <fsl_esdhc.h>
> -#include <asm/io.h>
> -#include <asm/fsl_serdes.h>
> -#include <asm/fsl_mpc83xx_serdes.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * The following are used to control the SPI chip selects for the SPI command.
> - */
> -#ifdef CONFIG_MPC8XXX_SPI
> -
> -#define SPI_CS_MASK 0x00400000
> -
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> - return bus == 0 && cs == 0;
> -}
> -
> -void spi_cs_activate(struct spi_slave *slave)
> -{
> - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> -
> - /* active low */
> - clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
> -}
> -
> -void spi_cs_deactivate(struct spi_slave *slave)
> -{
> - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> -
> - /* inactive high */
> - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
> -}
> -#endif /* CONFIG_MPC8XXX_SPI */
> -
> -#ifdef CONFIG_FSL_ESDHC
> -int board_mmc_init(bd_t *bd)
> -{
> - return fsl_esdhc_mmc_init(bd);
> -}
> -#endif
> -
> -static u8 read_board_info(void)
> -{
> - u8 val8;
> - i2c_set_bus_num(0);
> -
> - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
> - return val8;
> - else
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - static const char * const rev_str[] = {
> - "1.0",
> - "<reserved>",
> - "<reserved>",
> - "<reserved>",
> - "<unknown>",
> - };
> - u8 info;
> - int i;
> -
> - info = read_board_info();
> - i = (!info) ? 4 : info & 0x03;
> -
> - printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
> -
> - return 0;
> -}
> -
> -static struct pci_region pcie_regions_0[] = {
> - {
> - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
> - .size = CONFIG_SYS_PCIE1_MEM_SIZE,
> - .flags = PCI_REGION_MEM,
> - },
> - {
> - .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
> - .size = CONFIG_SYS_PCIE1_IO_SIZE,
> - .flags = PCI_REGION_IO,
> - },
> -};
> -
> -void pci_init_board(void)
> -{
> - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> - sysconf83xx_t *sysconf = &immr->sysconf;
> - law83xx_t *pcie_law = sysconf->pcielaw;
> - struct pci_region *pcie_reg[] = { pcie_regions_0 };
> -
> - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> -
> - /* Deassert the resets in the control register */
> - out_be32(&sysconf->pecr1, 0xE0008000);
> - udelay(2000);
> -
> - /* Configure PCI Express Local Access Windows */
> - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
> - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
> -
> - mpc83xx_pcie_init(1, pcie_reg);
> -}
> -/*
> - * Miscellaneous late-boot configurations
> - *
> - * If a VSC7385 microcode image is present, then upload it.
> -*/
> -int misc_init_r(void)
> -{
> -#ifdef CONFIG_MPC8XXX_SPI
> - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> - sysconf83xx_t *sysconf = &immr->sysconf;
> -
> - /*
> - * Set proper bits in SICRH to allow SPI on header J8
> - *
> - * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
> - * switch. The pinmux configuration does not have a fine enough
> - * granularity to support both simultaneously.
> - */
> - clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
> - puts("WARNING: SPI enabled, TSEC2 support is broken\n");
> -
> - /* Set header J8 SPI chip select output, disabled */
> - setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
> - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
> -#endif
> -
> -#ifdef CONFIG_VSC7385_IMAGE
> - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> - CONFIG_VSC7385_IMAGE_SIZE)) {
> - puts("Failure uploading VSC7385 microcode.\n");
> - return 1;
> - }
> -#endif
> -
> - return 0;
> -}
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> - fdt_fixup_dr_usb(blob, bd);
> - fdt_fixup_esdhc(blob, bd);
> -
> - return 0;
> -}
> -#endif
> -
> -int board_eth_init(bd_t *bis)
> -{
> - int rv, num_if = 0;
> -
> - /* Initialize TSECs first */
> - rv = cpu_eth_init(bis);
> - if (rv >= 0)
> - num_if += rv;
> - else
> - printf("ERROR: failed to initialize TSECs.\n");
> -
> - rv = pci_eth_init(bis);
> - if (rv >= 0)
> - num_if += rv;
> - else
> - printf("ERROR: failed to initialize PCI Ethernet.\n");
> -
> - return num_if;
> -}
> diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
> deleted file mode 100644
> index 89b665e..0000000
> --- a/board/freescale/mpc8308rdb/sdram.c
> +++ /dev/null
> @@ -1,81 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> - *
> - * Authors: Nick.Spence at freescale.com
> - * Wilson.Lo at freescale.com
> - * scottwood at freescale.com
> - *
> - * This files is mostly identical to the original from
> - * board\freescale\mpc8315erdb\sdram.c
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <mpc83xx.h>
> -
> -#include <asm/bitops.h>
> -#include <asm/io.h>
> -
> -#include <asm/processor.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* Fixed sdram init -- doesn't use serial presence detect.
> - *
> - * This is useful for faster booting in configs where the RAM is unlikely
> - * to be changed, or for things like NAND booting where space is tight.
> - */
> -static long fixed_sdram(void)
> -{
> - immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> - u32 msize_log2 = __ilog2(msize);
> -
> - out_be32(&im->sysconf.ddrlaw[0].bar,
> - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
> - out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
> - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
> -
> - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
> - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
> -
> - /* Currently we use only one CS, so disable the other bank. */
> - out_be32(&im->ddr.cs_config[1], 0);
> -
> - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
> - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
> - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
> - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
> - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
> -
> - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
> - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
> - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
> - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
> -
> - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
> - sync();
> -
> - /* enable DDR controller */
> - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
> - sync();
> -
> - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
> -}
> -
> -phys_size_t initdram(int board_type)
> -{
> - immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize;
> -
> - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM */
> - msize = fixed_sdram();
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return msize;
> -}
> diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
> deleted file mode 100644
> index 145608f..0000000
> --- a/board/freescale/mpc8313erdb/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8313ERDB
> -
> -config SYS_BOARD
> - default "mpc8313erdb"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8313ERDB"
> -
> -endif
> diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
> deleted file mode 100644
> index 807fb0b..0000000
> --- a/board/freescale/mpc8313erdb/MAINTAINERS
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -MPC8313ERDB BOARD
> -#M: -
> -S: Maintained
> -F: board/freescale/mpc8313erdb/
> -F: include/configs/MPC8313ERDB.h
> -F: configs/MPC8313ERDB_33_defconfig
> -F: configs/MPC8313ERDB_66_defconfig
> -F: configs/MPC8313ERDB_NAND_33_defconfig
> -F: configs/MPC8313ERDB_NAND_66_defconfig
> diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
> deleted file mode 100644
> index 77fad75..0000000
> --- a/board/freescale/mpc8313erdb/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := mpc8313erdb.o sdram.o
> diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
> deleted file mode 100644
> index be7ef32..0000000
> --- a/board/freescale/mpc8313erdb/README
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -Freescale MPC8313ERDB Board
> ------------------------------------------
> -
> -1. Board Switches and Jumpers
> -
> - S3 is used to set CONFIG_SYS_RESET_SOURCE.
> -
> - To boot the image at 0xFE000000 in NOR flash, use these DIP
> - switch settings for S3 S4:
> -
> - +------+ +------+
> - | | | **** |
> - | **** | | |
> - +------+ ON +------+ ON
> - 4321 4321
> - (where the '*' indicates the position of the tab of the switch.)
> -
> - To boot the image at the beginning of NAND flash, use these
> - DIP switch settings for S3 S4:
> -
> - +------+ +------+
> - | * | | *** |
> - | *** | | * |
> - +------+ ON +------+ ON
> - 4321 4321
> - (where the '*' indicates the position of the tab of the switch.)
> -
> - When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
> -
> -2. Memory Map
> - The memory map looks like this:
> -
> - 0x0000_0000 0x07ff_ffff DDR 128M
> - 0x8000_0000 0x8fff_ffff PCI MEM 256M
> - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
> - 0xe000_0000 0xe00f_ffff IMMR 1M
> - 0xe200_0000 0xe20f_ffff PCI IO 16M
> - 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
> - 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
> - 0xfa00_0000 0xfa00_7fff Board Status/ 32K
> - LED Control (CS3)
> - 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
> -
> - When booting from NAND, NAND flash is CS0 and NOR flash
> - is CS1.
> -
> -3. Definitions
> -
> -3.1 Explanation of NEW definitions in:
> -
> - include/configs/MPC8313ERDB.h
> -
> - CONFIG_MPC83xx MPC83xx family
> - CONFIG_MPC831x MPC831x specific
> - CONFIG_MPC8313ERDB MPC8313ERDB board specific
> -
> -4. Compilation
> -
> - Assuming you're using BASH (or similar) as your shell:
> -
> - export CROSS_COMPILE=your-cross-compiler-prefix-
> - make distclean
> - make MPC8313ERDB_XXX_config
> - (where XXX is:
> - 33 - 33 MHz oscillator, boot from NOR flash
> - 66 - 66 MHz oscillator, boot from NOR flash
> - NAND_33 - 33 MHz oscillator, boot from NAND flash
> - NAND_66 - 66 MHz oscillator, boot from NAND flash)
> - make
> -
> -5. Downloading and Flashing Images
> -
> -5.1 Reflash U-boot Image using U-boot
> -
> - NOR flash:
> -
> - =>run tftpflash
> -
> - You may want to try
> - =>tftpboot $loadaddr $uboot
> - first, to make sure that the TFTP load will succeed before it
> - goes ahead and wipes out your current firmware. And of course,
> - have an alternate means of programming the flash available
> - if the new u-boot doesn't boot.
> -
> - NAND flash:
> -
> - =>tftpboot $loadaddr <filename>
> - =>nand erase 0 0x80000
> - =>nand write $loadaddr 0 0x80000
> -
> - ...where 0x80000 is the filesize rounded up to
> - the next 0x20000 increment.
> -
> -5.2 Downloading and Booting Linux Kernel
> -
> - Ensure that all networking-related environment variables are set
> - properly (including ipaddr, serverip, gatewayip (if needed),
> - netmask, ethaddr, eth1addr, rootpath (if using NFS root),
> - fdtfile, and bootfile).
> -
> - Then, do one of the following, depending on whether you
> - want an NFS root or a ramdisk root:
> -
> - =>run nfsboot
> - or
> - =>run ramboot
> -
> -6 Notes
> -
> - The console baudrate for MPC8313ERDB is 115200bps.
> diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
> deleted file mode 100644
> index eac193e..0000000
> --- a/board/freescale/mpc8313erdb/mpc8313erdb.c
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -/*
> - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
> - *
> - * Author: Scott Wood <scottwood@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <libfdt.h>
> -#endif
> -#include <pci.h>
> -#include <mpc83xx.h>
> -#include <vsc7385.h>
> -#include <ns16550.h>
> -#include <nand.h>
> -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
> -#include <asm/gpio.h>
> -#endif
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> -
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - gd->flags |= GD_FLG_SILENT;
> -#endif
> -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
> - mpc83xx_gpio_init_f();
> -#endif
> -
> - return 0;
> -}
> -
> -int board_early_init_r(void)
> -{
> -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
> - mpc83xx_gpio_init_r();
> -#endif
> -
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Board: Freescale MPC8313ERDB\n");
> - return 0;
> -}
> -
> -#ifndef CONFIG_SPL_BUILD
> -static struct pci_region pci_regions[] = {
> - {
> - .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
> - .size = CONFIG_SYS_PCI1_MEM_SIZE,
> - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
> - .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
> - .size = CONFIG_SYS_PCI1_MMIO_SIZE,
> - .flags = PCI_REGION_MEM
> - },
> - {
> - .bus_start = CONFIG_SYS_PCI1_IO_BASE,
> - .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
> - .size = CONFIG_SYS_PCI1_IO_SIZE,
> - .flags = PCI_REGION_IO
> - }
> -};
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - struct pci_region *reg[] = { pci_regions };
> -
> - /* Enable all 3 PCI_CLK_OUTPUTs. */
> - clk->occr |= 0xe0000000;
> -
> - /*
> - * Configure PCI Local Access Windows
> - */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
> -
> - mpc83xx_pci_init(1, reg);
> -}
> -
> -/*
> - * Miscellaneous late-boot configurations
> - *
> - * If a VSC7385 microcode image is present, then upload it.
> -*/
> -int misc_init_r(void)
> -{
> - int rc = 0;
> -
> -#ifdef CONFIG_VSC7385_IMAGE
> - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> - CONFIG_VSC7385_IMAGE_SIZE)) {
> - puts("Failure uploading VSC7385 microcode.\n");
> - rc = 1;
> - }
> -#endif
> -
> - return rc;
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> -#else /* CONFIG_SPL_BUILD */
> -void board_init_f(ulong bootflag)
> -{
> - board_early_init_f();
> - NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
> - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
> - puts("NAND boot... ");
> - init_timebase();
> - initdram(0);
> - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
> - CONFIG_SYS_NAND_U_BOOT_RELOC);
> -}
> -
> -void board_init_r(gd_t *gd, ulong dest_addr)
> -{
> - nand_boot();
> -}
> -
> -void putc(char c)
> -{
> - if (gd->flags & GD_FLG_SILENT)
> - return;
> -
> - if (c == '\n')
> - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
> -
> - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
> -}
> -#endif
> diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
> deleted file mode 100644
> index 6282c3d..0000000
> --- a/board/freescale/mpc8313erdb/sdram.c
> +++ /dev/null
> @@ -1,124 +0,0 @@
> -/*
> - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
> - *
> - * Authors: Nick.Spence at freescale.com
> - * Wilson.Lo at freescale.com
> - * scottwood at freescale.com
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <spd_sdram.h>
> -
> -#include <asm/bitops.h>
> -#include <asm/io.h>
> -
> -#include <asm/processor.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
> -static void resume_from_sleep(void)
> -{
> - u32 magic = *(u32 *)0;
> -
> - typedef void (*func_t)(void);
> - func_t resume = *(func_t *)4;
> -
> - if (magic == 0xf5153ae5)
> - resume();
> -
> - gd->flags &= ~GD_FLG_SILENT;
> - puts("\nResume from sleep failed: bad magic word\n");
> -}
> -#endif
> -
> -/* Fixed sdram init -- doesn't use serial presence detect.
> - *
> - * This is useful for faster booting in configs where the RAM is unlikely
> - * to be changed, or for things like NAND booting where space is tight.
> - */
> -static long fixed_sdram(void)
> -{
> - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> -
> -#ifndef CONFIG_SYS_RAMBOOT
> - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
> - u32 msize_log2 = __ilog2(msize);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
> - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
> -
> - /*
> - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
> - * or the DDR2 controller may fail to initialize correctly.
> - */
> - __udelay(50000);
> -
> -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
> -#warning Chip select bounds is only configurable in 16MB increments
> -#endif
> - im->ddr.csbnds[0].csbnds =
> - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
> - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
> - CSBNDS_EA);
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> -
> - /* Currently we use only one CS, so disable the other bank. */
> - im->ddr.cs_config[1] = 0;
> -
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> -
> -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
> - else
> -#endif
> - im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
> -
> - im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
> -
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - sync();
> -
> - /* enable DDR controller */
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> -#endif
> -
> - return msize;
> -}
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile fsl_lbc_t *lbc = &im->im_lbc;
> - u32 msize;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - msize = fixed_sdram();
> -
> - /* Local Bus setup lbcr and mrtpr */
> - lbc->lbcr = CONFIG_SYS_LBC_LBCR;
> - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
> - sync();
> -
> -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - resume_from_sleep();
> -#endif
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return msize;
> -}
> diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
> deleted file mode 100644
> index f76b0d1..0000000
> --- a/board/freescale/mpc8315erdb/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8315ERDB
> -
> -config SYS_BOARD
> - default "mpc8315erdb"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8315ERDB"
> -
> -endif
> diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
> deleted file mode 100644
> index 938c152..0000000
> --- a/board/freescale/mpc8315erdb/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MPC8315ERDB BOARD
> -M: Dave Liu <daveliu@freescale.com>
> -S: Maintained
> -F: board/freescale/mpc8315erdb/
> -F: include/configs/MPC8315ERDB.h
> -F: configs/MPC8315ERDB_defconfig
> diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
> deleted file mode 100644
> index fbb68c5..0000000
> --- a/board/freescale/mpc8315erdb/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := mpc8315erdb.o sdram.o
> diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
> deleted file mode 100644
> index b32132d..0000000
> --- a/board/freescale/mpc8315erdb/README
> +++ /dev/null
> @@ -1,105 +0,0 @@
> -Freescale MPC8315ERDB Board
> ------------------------------------------
> -
> -1. Board Switches and Jumpers
> -
> - S3 is used to set CONFIG_SYS_RESET_SOURCE.
> -
> - To boot the image at 0xFE000000 in NOR flash, use these DIP
> - switch settings for S3 S4:
> -
> - +------+ +------+
> - | | | **** |
> - | **** | | |
> - +------+ ON +------+ ON
> - 4321 4321
> - (where the '*' indicates the position of the tab of the switch.)
> -
> - To boot the image at the beginning of NAND flash, use these
> - DIP switch settings for S3 S4:
> -
> - +------+ +------+
> - | * | | *** |
> - | *** | | * |
> - +------+ ON +------+ ON
> - 4321 4321
> - (where the '*' indicates the position of the tab of the switch.)
> -
> - When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
> -
> -2. Memory Map
> - The memory map looks like this:
> -
> - 0x0000_0000 0x07ff_ffff DDR 128M
> - 0x8000_0000 0x8fff_ffff PCI MEM 256M
> - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
> - 0xe000_0000 0xe00f_ffff IMMR 1M
> - 0xe030_0000 0xe03f_ffff PCI IO 1M
> - 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
> - 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
> -
> - When booting from NAND, NAND flash is CS0 and NOR flash
> - is CS1.
> -
> -3. Definitions
> -
> -3.1 Explanation of NEW definitions in:
> -
> - include/configs/MPC8315ERDB.h
> -
> - CONFIG_MPC83xx MPC83xx family
> - CONFIG_MPC831x MPC831x specific
> - CONFIG_MPC8315 MPC8315 specific
> - CONFIG_MPC8315ERDB MPC8315ERDB board specific
> -
> -4. Compilation
> -
> - Assuming you're using BASH (or similar) as your shell:
> -
> - export CROSS_COMPILE=your-cross-compiler-prefix-
> - make distclean
> - make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
> - make all
> -
> -5. Downloading and Flashing Images
> -
> -5.1 Reflash U-boot Image using U-boot
> -
> - NOR flash:
> -
> - tftp 40000 u-boot.bin
> - protect off all
> - erase fe000000 fe1fffff
> -
> - cp.b 40000 fe000000 xxxx
> - protect on all
> -
> - You have to supply the correct byte count with 'xxxx'
> - from the TFTP result log.
> -
> - NAND flash:
> -
> - =>tftpboot $loadaddr <filename>
> - =>nand erase 0 0x80000
> - =>nand write $loadaddr 0 0x80000
> -
> - ...where 0x80000 is the filesize rounded up to
> - the next 0x20000 increment.
> -
> -5.2 Downloading and Booting Linux Kernel
> -
> - Ensure that all networking-related environment variables are set
> - properly (including ipaddr, serverip, gatewayip (if needed),
> - netmask, ethaddr, eth1addr, rootpath (if using NFS root),
> - fdtfile, and bootfile).
> -
> - Then, do one of the following, depending on whether you
> - want an NFS root or a ramdisk root:
> -
> - =>run nfsboot
> - or
> - =>run ramboot
> -
> -6 Notes
> -
> - The console baudrate for MPC8315ERDB is 115200bps.
> diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
> deleted file mode 100644
> index ed611c5..0000000
> --- a/board/freescale/mpc8315erdb/mpc8315erdb.c
> +++ /dev/null
> @@ -1,246 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - *
> - * Author: Scott Wood <scottwood@freescale.com>
> - * Dave Liu <daveliu@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <hwconfig.h>
> -#include <i2c.h>
> -#include <libfdt.h>
> -#include <fdt_support.h>
> -#include <pci.h>
> -#include <mpc83xx.h>
> -#include <netdev.h>
> -#include <asm/io.h>
> -#include <ns16550.h>
> -#include <nand.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> -
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - gd->flags |= GD_FLG_SILENT;
> -
> - return 0;
> -}
> -
> -#ifndef CONFIG_NAND_SPL
> -
> -static u8 read_board_info(void)
> -{
> - u8 val8;
> - i2c_set_bus_num(0);
> -
> - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
> - return val8;
> - else
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - static const char * const rev_str[] = {
> - "0.0",
> - "0.1",
> - "1.0",
> - "1.1",
> - "<unknown>",
> - };
> - u8 info;
> - int i;
> -
> - info = read_board_info();
> - i = (!info) ? 4: info & 0x03;
> -
> - printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
> -
> - return 0;
> -}
> -
> -static struct pci_region pci_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI_MEM_PHYS,
> - size: CONFIG_SYS_PCI_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
> - size: CONFIG_SYS_PCI_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> - {
> - bus_start: CONFIG_SYS_PCI_IO_BASE,
> - phys_start: CONFIG_SYS_PCI_IO_PHYS,
> - size: CONFIG_SYS_PCI_IO_SIZE,
> - flags: PCI_REGION_IO
> - }
> -};
> -
> -static struct pci_region pcie_regions_0[] = {
> - {
> - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
> - .size = CONFIG_SYS_PCIE1_MEM_SIZE,
> - .flags = PCI_REGION_MEM,
> - },
> - {
> - .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
> - .size = CONFIG_SYS_PCIE1_IO_SIZE,
> - .flags = PCI_REGION_IO,
> - },
> -};
> -
> -static struct pci_region pcie_regions_1[] = {
> - {
> - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
> - .size = CONFIG_SYS_PCIE2_MEM_SIZE,
> - .flags = PCI_REGION_MEM,
> - },
> - {
> - .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
> - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
> - .size = CONFIG_SYS_PCIE2_IO_SIZE,
> - .flags = PCI_REGION_IO,
> - },
> -};
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile sysconf83xx_t *sysconf = &immr->sysconf;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - volatile law83xx_t *pcie_law = sysconf->pcielaw;
> - struct pci_region *reg[] = { pci_regions };
> - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
> -
> - /* Enable all 3 PCI_CLK_OUTPUTs. */
> - clk->occr |= 0xe0000000;
> -
> - /*
> - * Configure PCI Local Access Windows
> - */
> - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
> -
> - mpc83xx_pci_init(1, reg);
> -
> - /* Configure the clock for PCIE controller */
> - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
> - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
> -
> - /* Deassert the resets in the control register */
> - out_be32(&sysconf->pecr1, 0xE0008000);
> - out_be32(&sysconf->pecr2, 0xE0008000);
> - udelay(2000);
> -
> - /* Configure PCI Express Local Access Windows */
> - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
> - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
> -
> - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
> - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
> -
> - mpc83xx_pcie_init(2, pcie_reg);
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -void fdt_tsec1_fixup(void *fdt, bd_t *bd)
> -{
> - const char disabled[] = "disabled";
> - const char *path;
> - int ret;
> -
> - if (hwconfig_arg_cmp("board_type", "tsec1")) {
> - return;
> - } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
> - printf("NOTICE: No or unknown board_type hwconfig specified.\n"
> - " Assuming board with TSEC1.\n");
> - return;
> - }
> -
> - ret = fdt_path_offset(fdt, "/aliases");
> - if (ret < 0) {
> - printf("WARNING: can't find /aliases node\n");
> - return;
> - }
> -
> - path = fdt_getprop(fdt, ret, "ethernet0", NULL);
> - if (!path) {
> - printf("WARNING: can't find ethernet0 alias\n");
> - return;
> - }
> -
> - do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
> -}
> -
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> - fdt_fixup_dr_usb(blob, bd);
> - fdt_tsec1_fixup(blob, bd);
> -
> - return 0;
> -}
> -#endif
> -
> -int board_eth_init(bd_t *bis)
> -{
> - cpu_eth_init(bis); /* Initialize TSECs first */
> - return pci_eth_init(bis);
> -}
> -
> -#else /* CONFIG_NAND_SPL */
> -
> -int checkboard(void)
> -{
> - puts("Board: Freescale MPC8315ERDB\n");
> - return 0;
> -}
> -
> -void board_init_f(ulong bootflag)
> -{
> - board_early_init_f();
> - NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
> - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
> - puts("NAND boot... ");
> - init_timebase();
> - initdram(0);
> - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
> - CONFIG_SYS_NAND_U_BOOT_RELOC);
> -}
> -
> -void board_init_r(gd_t *gd, ulong dest_addr)
> -{
> - nand_boot();
> -}
> -
> -void putc(char c)
> -{
> - if (gd->flags & GD_FLG_SILENT)
> - return;
> -
> - if (c == '\n')
> - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
> -
> - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
> -}
> -
> -#endif /* CONFIG_NAND_SPL */
> diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
> deleted file mode 100644
> index 6c94312..0000000
> --- a/board/freescale/mpc8315erdb/sdram.c
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - *
> - * Authors: Nick.Spence at freescale.com
> - * Wilson.Lo at freescale.com
> - * scottwood at freescale.com
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <spd_sdram.h>
> -
> -#include <asm/bitops.h>
> -#include <asm/io.h>
> -
> -#include <asm/processor.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static void resume_from_sleep(void)
> -{
> - u32 magic = *(u32 *)0;
> -
> - typedef void (*func_t)(void);
> - func_t resume = *(func_t *)4;
> -
> - if (magic == 0xf5153ae5)
> - resume();
> -
> - gd->flags &= ~GD_FLG_SILENT;
> - puts("\nResume from sleep failed: bad magic word\n");
> -}
> -
> -/* Fixed sdram init -- doesn't use serial presence detect.
> - *
> - * This is useful for faster booting in configs where the RAM is unlikely
> - * to be changed, or for things like NAND booting where space is tight.
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> -static long fixed_sdram(void)
> -{
> - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> - u32 msize_log2 = __ilog2(msize);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
> - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
> -
> - /*
> - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
> - * or the DDR2 controller may fail to initialize correctly.
> - */
> - __udelay(50000);
> -
> - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> -
> - /* Currently we use only one CS, so disable the other bank. */
> - im->ddr.cs_config[1] = 0;
> -
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> -
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
> - else
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
> -
> - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
> -
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - sync();
> -
> - /* enable DDR controller */
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - sync();
> -
> - return msize;
> -}
> -#else
> -static long fixed_sdram(void)
> -{
> - return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> -}
> -#endif /* CONFIG_SYS_RAMBOOT */
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
> - u32 msize;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM */
> - msize = fixed_sdram();
> -
> - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
> - resume_from_sleep();
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return msize;
> -}
> diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
> deleted file mode 100644
> index acf8122..0000000
> --- a/board/freescale/mpc8323erdb/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8323ERDB
> -
> -config SYS_BOARD
> - default "mpc8323erdb"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8323ERDB"
> -
> -endif
> diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
> deleted file mode 100644
> index 05057c0..0000000
> --- a/board/freescale/mpc8323erdb/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MPC8323ERDB BOARD
> -M: Michael Barkowski <michael.barkowski@freescale.com>
> -S: Maintained
> -F: board/freescale/mpc8323erdb/
> -F: include/configs/MPC8323ERDB.h
> -F: configs/MPC8323ERDB_defconfig
> diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
> deleted file mode 100644
> index f2e7497..0000000
> --- a/board/freescale/mpc8323erdb/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := mpc8323erdb.o
> diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
> deleted file mode 100644
> index 6f89829..0000000
> --- a/board/freescale/mpc8323erdb/README
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -Freescale MPC8323ERDB Board
> ------------------------------------------
> -
> -1. Memory Map
> - The memory map looks like this:
> -
> - 0x0000_0000 0x03ff_ffff DDR 64M
> - 0x8000_0000 0x8fff_ffff PCI MEM 256M
> - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
> - 0xe000_0000 0xe00f_ffff IMMR 1M
> - 0xd000_0000 0xd3ff_ffff PCI IO 64M
> - 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
> -
> -2. Compilation
> -
> - Assuming you're using BASH (or similar) as your shell:
> -
> - export CROSS_COMPILE=your-cross-compiler-prefix-
> - make distclean
> - make MPC8323ERDB_config
> - make
> -
> -3. Downloading and Flashing Images
> -
> -3.1 Reflash U-boot Image using U-boot
> -
> - N.b, have an alternate means of programming
> - the flash available if the new u-boot doesn't boot.
> -
> - First try a:
> -
> - tftpboot $loadaddr $uboot
> -
> - to make sure that the TFTP load will succeed before
> - an erase goes ahead and wipes out your current firmware.
> - Then do a:
> -
> - run tftpflash
> -
> - which is a shorter version of the manual sequence:
> -
> - tftp $loadaddr u-boot.bin
> - protect off fe000000 +$filesize
> - erase fe000000 +$filesize
> - cp.b $loadaddr fe000000 $filesize
> -
> - To keep your old u-boot's environment variables, do a:
> -
> - saveenv
> -
> - prior to resetting the board.
> -
> -3.2 Downloading and Booting Linux Kernel
> -
> - Ensure that all networking-related environment variables are set
> - properly (including ipaddr, serverip, gatewayip (if needed),
> - netmask, ethaddr, eth1addr, rootpath (if using NFS root),
> - fdtfile, and bootfile).
> -
> - Then, do one of the following, depending on whether you
> - want an NFS root or a ramdisk root:
> -
> - run nfsboot
> -
> - or
> -
> - run ramboot
> -
> -4 Notes
> -
> - The console baudrate for MPC8323ERDB is 115200bps.
> diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
> deleted file mode 100644
> index 0a0152a..0000000
> --- a/board/freescale/mpc8323erdb/mpc8323erdb.c
> +++ /dev/null
> @@ -1,222 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - *
> - * Michael Barkowski <michael.barkowski@freescale.com>
> - * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License version 2 as published
> - * by the Free Software Foundation.
> - */
> -
> -#include <common.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <i2c.h>
> -#include <miiphy.h>
> -#include <command.h>
> -#include <libfdt.h>
> -#if defined(CONFIG_PCI)
> -#include <pci.h>
> -#endif
> -#include <asm/mmu.h>
> -
> -const qe_iop_conf_t qe_iop_conf_tab[] = {
> - /* UCC3 */
> - {1, 0, 1, 0, 1}, /* TxD0 */
> - {1, 1, 1, 0, 1}, /* TxD1 */
> - {1, 2, 1, 0, 1}, /* TxD2 */
> - {1, 3, 1, 0, 1}, /* TxD3 */
> - {1, 9, 1, 0, 1}, /* TxER */
> - {1, 12, 1, 0, 1}, /* TxEN */
> - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
> -
> - {1, 4, 2, 0, 1}, /* RxD0 */
> - {1, 5, 2, 0, 1}, /* RxD1 */
> - {1, 6, 2, 0, 1}, /* RxD2 */
> - {1, 7, 2, 0, 1}, /* RxD3 */
> - {1, 8, 2, 0, 1}, /* RxER */
> - {1, 10, 2, 0, 1}, /* RxDV */
> - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
> - {1, 11, 2, 0, 1}, /* COL */
> - {1, 13, 2, 0, 1}, /* CRS */
> -
> - /* UCC2 */
> - {0, 18, 1, 0, 1}, /* TxD0 */
> - {0, 19, 1, 0, 1}, /* TxD1 */
> - {0, 20, 1, 0, 1}, /* TxD2 */
> - {0, 21, 1, 0, 1}, /* TxD3 */
> - {0, 27, 1, 0, 1}, /* TxER */
> - {0, 30, 1, 0, 1}, /* TxEN */
> - {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
> -
> - {0, 22, 2, 0, 1}, /* RxD0 */
> - {0, 23, 2, 0, 1}, /* RxD1 */
> - {0, 24, 2, 0, 1}, /* RxD2 */
> - {0, 25, 2, 0, 1}, /* RxD3 */
> - {0, 26, 1, 0, 1}, /* RxER */
> - {0, 28, 2, 0, 1}, /* Rx_DV */
> - {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
> - {0, 29, 2, 0, 1}, /* COL */
> - {0, 31, 2, 0, 1}, /* CRS */
> -
> - {3, 4, 3, 0, 2}, /* MDIO */
> - {3, 5, 1, 0, 2}, /* MDC */
> -
> - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
> -};
> -
> -int fixed_sdram(void);
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
> -
> - msize = fixed_sdram();
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return (msize * 1024 * 1024);
> -}
> -
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> - u32 ddr_size;
> - u32 ddr_size_log2;
> -
> - msize = CONFIG_SYS_DDR_SIZE;
> - for (ddr_size = msize << 20, ddr_size_log2 = 0;
> - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
> - if (ddr_size & 1) {
> - return -1;
> - }
> - }
> - im->sysconf.ddrlaw[0].ar =
> - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
> - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
> - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - __asm__ __volatile__ ("sync");
> - udelay(200);
> -
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - __asm__ __volatile__ ("sync");
> - return msize;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Board: Freescale MPC8323ERDB\n");
> - return 0;
> -}
> -
> -static struct pci_region pci_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - }
> -};
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - struct pci_region *reg[] = { pci_regions };
> -
> - /* Enable all 3 PCI_CLK_OUTPUTs. */
> - clk->occr |= 0xe0000000;
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
> -
> - mpc83xx_pci_init(1, reg);
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
> -int mac_read_from_eeprom(void)
> -{
> - uchar buf[28];
> - char str[18];
> - int i = 0;
> - unsigned int crc = 0;
> - unsigned char enetvar[32];
> -
> - /* Read MAC addresses from EEPROM */
> - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
> - printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
> - CONFIG_SYS_I2C_EEPROM_ADDR);
> - } else {
> - uint32_t crc_buf;
> -
> - memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
> -
> - if (crc32(crc, buf, 24) == crc_buf) {
> - printf("Reading MAC from EEPROM\n");
> - for (i = 0; i < 4; i++) {
> - if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
> - sprintf(str,
> - "%02X:%02X:%02X:%02X:%02X:%02X",
> - buf[i * 6], buf[i * 6 + 1],
> - buf[i * 6 + 2], buf[i * 6 + 3],
> - buf[i * 6 + 4], buf[i * 6 + 5]);
> - sprintf((char *)enetvar,
> - i ? "eth%daddr" : "ethaddr", i);
> - setenv((char *)enetvar, str);
> - }
> - }
> - }
> - }
> - return 0;
> -}
> -#endif /* CONFIG_I2C_MAC_OFFSET */
> diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
> deleted file mode 100644
> index e4cfa15..0000000
> --- a/board/freescale/mpc832xemds/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC832XEMDS
> -
> -config SYS_BOARD
> - default "mpc832xemds"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC832XEMDS"
> -
> -endif
> diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
> deleted file mode 100644
> index 56d7073..0000000
> --- a/board/freescale/mpc832xemds/MAINTAINERS
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -MPC832XEMDS BOARD
> -M: Dave Liu <daveliu@freescale.com>
> -S: Maintained
> -F: board/freescale/mpc832xemds/
> -F: include/configs/MPC832XEMDS.h
> -F: configs/MPC832XEMDS_defconfig
> -F: configs/MPC832XEMDS_ATM_defconfig
> -F: configs/MPC832XEMDS_HOST_33_defconfig
> -F: configs/MPC832XEMDS_HOST_66_defconfig
> -F: configs/MPC832XEMDS_SLAVE_defconfig
> diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
> deleted file mode 100644
> index 6676351..0000000
> --- a/board/freescale/mpc832xemds/Makefile
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y += mpc832xemds.o
> -obj-$(CONFIG_PCI) += pci.o
> diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
> deleted file mode 100644
> index 4142aa9..0000000
> --- a/board/freescale/mpc832xemds/README
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -Freescale MPC832XEMDS Board
> ------------------------------------------
> -1. Board Switches and Jumpers
> -1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
> - For some reason, the HW designers describe the switch settings
> - in terms of 0 and 1, and then map that to physical switches where
> - the label "On" refers to logic 0 and "Off" is logic 1.
> -
> - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
> - bits may contribute to signals that are numbered based at 0,
> - and some of those signals may be high-bit-number-0 too. Heed
> - well the names and labels and do not get confused.
> -
> - "Off" == 1
> - "On" == 0
> -
> - SW3 is switch 18 as silk-screened onto the board.
> - SW4[8] is the bit labeled 8 on Switch 4.
> - SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
> - SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
> - SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
> - and bits labeled 8 is set as "Off".
> -
> -1.1 For the MPC832XEMDS PROTO Board
> -
> - First, make sure the board default setting is consistent with the document
> - shipped with your board. Then apply the following setting:
> - SW3[1-8]= 0000_1000 (core PLL setting, core enable)
> - SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
> - SW5[1-8]= 0010_0110 (Boot from high end)
> - SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
> - SW7[1-8]= 1000_0011 (QE PLL setting)
> -
> - ENET3/4 MII mode settings:
> - J1 1-2 (ETH3_TXER)
> - J2 2-3 (MII mode)
> - J3 2-3 (MII mode)
> - J4 2-3 (ADSL clockOscillator)
> - J5 1-2 (ETH4_TXER)
> - J6 2-3 (ClockOscillator)
> - JP1 removed (don't force PORESET)
> - JP2 mounted (ETH4/2 MII)
> - JP3 mounted (ETH3 MII)
> - JP4 mounted (HRCW from BCSR)
> -
> - ENET3/4 RMII mode settings:
> - J1 1-2 (ETH3_TXER)
> - J2 1-2 (RMII mode)
> - J3 1-2 (RMII mode)
> - J4 2-3 (ADSL clockOscillator)
> - J5 1-2 (ETH4_TXER)
> - J6 2-3 (ClockOscillator)
> - JP1 removed (don't force PORESET)
> - JP2 removed (ETH4/2 RMII)
> - JP3 removed (ETH3 RMII)
> - JP4 removed (HRCW from FLASH)
> -
> - on board Oscillator: 66M
> -
> -
> -2. Memory Map
> -
> -2.1 The memory map should look pretty much like this:
> -
> - 0x0000_0000 0x7fff_ffff DDR 2G
> - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
> - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
> - 0xc000_0000 0xdfff_ffff Empty 512M
> - 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
> - 0xe020_0000 0xe02f_ffff Empty 1M
> - 0xe030_0000 0xe03f_ffff PCI IO 1M
> - 0xe040_0000 0xefff_ffff Empty 252M
> - 0xf400_0000 0xf7ff_ffff Empty 64M
> - 0xf800_0000 0xf800_7fff BCSR on CS1 32K
> - 0xf800_8000 0xf800_ffff PIB CS2 32K
> - 0xf801_0000 0xf801_7fff PIB CS3 32K
> - 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
> -
> -
> -3. Definitions
> -
> -3.1 Explanation of NEW definitions in:
> -
> - include/configs/MPC832XEPB.h
> -
> - CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
> - CONFIG_MPC832x MPC832x specific
> - CONFIG_MPC832XEMDS MPC832XEMDS board specific
> -
> -4. Compilation
> -
> - Assuming you're using BASH shell:
> -
> - export CROSS_COMPILE=your-cross-compile-prefix
> - cd u-boot
> - make distclean
> - make MPC832XEMDS_config
> - make
> -
> - MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
> -
> - 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
> -
> - 2)To Make U-Boot image support PCI 33MHz, use
> - Make MPC832XEMDS_HOST_33_config
> -
> - 3)To Make U-Boot image support PCI 66MHz, use
> - Make MPC832XEMDS_HOST_66M_config
> -
> -5. Downloading and Flashing Images
> -
> -5.0 Download over network:
> -
> - tftp 10000 u-boot.bin
> -
> -5.1 Reflash U-boot Image using U-boot
> -
> - tftp 20000 u-boot.bin
> - protect off fe000000 fe0fffff
> - erase fe000000 fe0fffff
> - cp.b 20000 fe000000 xxxx
> -
> -You have to supply the correct byte count with 'xxxx' from the TFTP result log.
> -Maybe 3ffff will work too, that corresponds to the erased sectors.
> -
> -
> -6. Notes
> - 1) The console baudrate for MPC832XEMDS is 115200bps.
> diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
> deleted file mode 100644
> index adf4254..0000000
> --- a/board/freescale/mpc832xemds/mpc832xemds.c
> +++ /dev/null
> @@ -1,166 +0,0 @@
> -/*
> - * Copyright (C) 2006 Freescale Semiconductor, Inc.
> - *
> - * Dave Liu <daveliu@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <i2c.h>
> -#include <miiphy.h>
> -#include <command.h>
> -#if defined(CONFIG_PCI)
> -#include <pci.h>
> -#endif
> -#include <asm/mmu.h>
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <libfdt.h>
> -#endif
> -#if defined(CONFIG_PQ_MDS_PIB)
> -#include "../common/pq-mds-pib.h"
> -#endif
> -
> -const qe_iop_conf_t qe_iop_conf_tab[] = {
> - /* ETH3 */
> - {1, 0, 1, 0, 1}, /* TxD0 */
> - {1, 1, 1, 0, 1}, /* TxD1 */
> - {1, 2, 1, 0, 1}, /* TxD2 */
> - {1, 3, 1, 0, 1}, /* TxD3 */
> - {1, 9, 1, 0, 1}, /* TxER */
> - {1, 12, 1, 0, 1}, /* TxEN */
> - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
> -
> - {1, 4, 2, 0, 1}, /* RxD0 */
> - {1, 5, 2, 0, 1}, /* RxD1 */
> - {1, 6, 2, 0, 1}, /* RxD2 */
> - {1, 7, 2, 0, 1}, /* RxD3 */
> - {1, 8, 2, 0, 1}, /* RxER */
> - {1, 10, 2, 0, 1}, /* RxDV */
> - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
> - {1, 11, 2, 0, 1}, /* COL */
> - {1, 13, 2, 0, 1}, /* CRS */
> -
> - /* ETH4 */
> - {1, 18, 1, 0, 1}, /* TxD0 */
> - {1, 19, 1, 0, 1}, /* TxD1 */
> - {1, 20, 1, 0, 1}, /* TxD2 */
> - {1, 21, 1, 0, 1}, /* TxD3 */
> - {1, 27, 1, 0, 1}, /* TxER */
> - {1, 30, 1, 0, 1}, /* TxEN */
> - {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
> -
> - {1, 22, 2, 0, 1}, /* RxD0 */
> - {1, 23, 2, 0, 1}, /* RxD1 */
> - {1, 24, 2, 0, 1}, /* RxD2 */
> - {1, 25, 2, 0, 1}, /* RxD3 */
> - {1, 26, 1, 0, 1}, /* RxER */
> - {1, 28, 2, 0, 1}, /* Rx_DV */
> - {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
> - {1, 29, 2, 0, 1}, /* COL */
> - {1, 31, 2, 0, 1}, /* CRS */
> -
> - {3, 4, 3, 0, 2}, /* MDIO */
> - {3, 5, 1, 0, 2}, /* MDC */
> -
> - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
> -};
> -
> -int board_early_init_f(void)
> -{
> - volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
> -
> - /* Enable flash write */
> - bcsr[9] &= ~0x08;
> -
> - return 0;
> -}
> -
> -int board_early_init_r(void)
> -{
> -#ifdef CONFIG_PQ_MDS_PIB
> - pib_init();
> -#endif
> - return 0;
> -}
> -
> -int fixed_sdram(void);
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
> -
> - msize = fixed_sdram();
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return (msize * 1024 * 1024);
> -}
> -
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> - u32 ddr_size;
> - u32 ddr_size_log2;
> -
> - msize = CONFIG_SYS_DDR_SIZE;
> - for (ddr_size = msize << 20, ddr_size_log2 = 0;
> - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
> - if (ddr_size & 1) {
> - return -1;
> - }
> - }
> - im->sysconf.ddrlaw[0].ar =
> - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> -#if (CONFIG_SYS_DDR_SIZE != 128)
> -#warning Currenly any ddr size other than 128 is not supported
> -#endif
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
> - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
> - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - __asm__ __volatile__ ("sync");
> - udelay(200);
> -
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - __asm__ __volatile__ ("sync");
> - return msize;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Board: Freescale MPC832XEMDS\n");
> - return 0;
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
> deleted file mode 100644
> index e8b2b11..0000000
> --- a/board/freescale/mpc832xemds/pci.c
> +++ /dev/null
> @@ -1,146 +0,0 @@
> -/*
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -/*
> - * PCI Configuration space access support for MPC83xx PCI Bridge
> - */
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <asm/fsl_i2c.h>
> -#include "../common/pq-mds-pib.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static struct pci_region pci1_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -static struct pci_region pci2_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI2_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
> - size: CONFIG_SYS_PCI2_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_IO_BASE,
> - phys_start: CONFIG_SYS_PCI2_IO_PHYS,
> - size: CONFIG_SYS_PCI2_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
> - size: CONFIG_SYS_PCI2_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -#endif
> -
> -void pci_init_board(void)
> -#ifdef CONFIG_PCISLAVE
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
> - struct pci_region *reg[] = { pci1_regions };
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> -
> - mpc83xx_pci_init(1, reg);
> -
> - /*
> - * Configure PCI Inbound Translation Windows
> - */
> - pci_ctrl[0].pitar0 = 0x0;
> - pci_ctrl[0].pibar0 = 0x0;
> - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
> - PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
> -
> - pci_ctrl[0].pitar1 = 0x0;
> - pci_ctrl[0].pibar1 = 0x0;
> - pci_ctrl[0].piebar1 = 0x0;
> - pci_ctrl[0].piwar1 &= ~PIWAR_EN;
> -
> - pci_ctrl[0].pitar2 = 0x0;
> - pci_ctrl[0].pibar2 = 0x0;
> - pci_ctrl[0].piebar2 = 0x0;
> - pci_ctrl[0].piwar2 &= ~PIWAR_EN;
> -
> - /* Unlock the configuration bit */
> - mpc83xx_pcislave_unlock(0);
> - printf("PCI: Agent mode enabled\n");
> -}
> -#else
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> -#ifndef CONFIG_MPC83XX_PCI2
> - struct pci_region *reg[] = { pci1_regions };
> -#else
> - struct pci_region *reg[] = { pci1_regions, pci2_regions };
> -#endif
> -
> - /* initialize the PCA9555PW IO expander on the PIB board */
> - pib_init();
> -
> -#if defined(CONFIG_PCI_66M)
> - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
> - printf("PCI clock is 66MHz\n");
> -#elif defined(CONFIG_PCI_33M)
> - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
> - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
> - printf("PCI clock is 33MHz\n");
> -#else
> - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
> - printf("PCI clock is 66MHz\n");
> -#endif
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
> -
> - udelay(2000);
> -
> -#ifndef CONFIG_MPC83XX_PCI2
> - mpc83xx_pci_init(1, reg);
> -#else
> - mpc83xx_pci_init(2, reg);
> -#endif
> -}
> -#endif /* CONFIG_PCISLAVE */
> diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
> deleted file mode 100644
> index 51f0b34..0000000
> --- a/board/freescale/mpc8349emds/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8349EMDS
> -
> -config SYS_BOARD
> - default "mpc8349emds"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8349EMDS"
> -
> -endif
> diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
> deleted file mode 100644
> index 141e77a..0000000
> --- a/board/freescale/mpc8349emds/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MPC8349EMDS BOARD
> -M: Kim Phillips <kim.phillips@freescale.com>
> -S: Maintained
> -F: board/freescale/mpc8349emds/
> -F: include/configs/MPC8349EMDS.h
> -F: configs/MPC8349EMDS_defconfig
> diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
> deleted file mode 100644
> index 5c315f9..0000000
> --- a/board/freescale/mpc8349emds/Makefile
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y += mpc8349emds.o
> -obj-$(CONFIG_PCI) += pci.o
> -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
> diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
> deleted file mode 100644
> index aae003d..0000000
> --- a/board/freescale/mpc8349emds/ddr.c
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -/*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -
> -#include <fsl_ddr_sdram.h>
> -#include <fsl_ddr_dimm_params.h>
> -
> -struct board_specific_parameters {
> - u32 n_ranks;
> - u32 datarate_mhz_high;
> - u32 clk_adjust;
> - u32 cpo;
> - u32 write_data_delay;
> - u32 force_2t;
> -};
> -
> -/*
> - * This table contains all valid speeds we want to override with board
> - * specific parameters. datarate_mhz_high values need to be in ascending order
> - * for each n_ranks group.
> - */
> -static const struct board_specific_parameters udimm0[] = {
> - /*
> - * memory controller 0
> - * num| hi| clk| cpo|wrdata|2T
> - * ranks| mhz|adjst| | delay|
> - */
> - {2, 300, 4, 4, 2, 0},
> - {2, 365, 4, 6, 2, 0},
> - {2, 450, 4, 7, 2, 0},
> - {2, 850, 4, 31, 2, 0},
> - {1, 300, 4, 4, 2, 0},
> - {1, 365, 4, 6, 2, 0},
> - {1, 450, 4, 7, 2, 0},
> - {1, 850, 4, 31, 2, 0},
> - {}
> -};
> -
> -void fsl_ddr_board_options(memctl_options_t *popts,
> - dimm_params_t *pdimm,
> - unsigned int ctrl_num)
> -{
> - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> - unsigned int i;
> - ulong ddr_freq;
> -
> - if (ctrl_num != 0) /* we have only one controller */
> - return;
> - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
> - if (pdimm[i].n_ranks)
> - break;
> - }
> - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
> - return;
> -
> - pbsp = udimm0;
> -
> - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
> - * freqency and n_banks specified in board_specific_parameters table.
> - */
> - ddr_freq = get_ddr_freq(0) / 1000000;
> - while (pbsp->datarate_mhz_high) {
> - if (pbsp->n_ranks == pdimm[i].n_ranks) {
> - if (ddr_freq <= pbsp->datarate_mhz_high) {
> - popts->clk_adjust = pbsp->clk_adjust;
> - popts->cpo_override = pbsp->cpo;
> - popts->write_data_delay =
> - pbsp->write_data_delay;
> - popts->twot_en = pbsp->force_2t;
> - goto found;
> - }
> - pbsp_highest = pbsp;
> - }
> - pbsp++;
> - }
> -
> - if (pbsp_highest) {
> - printf("Error: board specific timing not found "
> - "for data rate %lu MT/s!\n"
> - "Trying to use the highest speed (%u) parameters\n",
> - ddr_freq, pbsp_highest->datarate_mhz_high);
> - popts->clk_adjust = pbsp_highest->clk_adjust;
> - popts->cpo_override = pbsp_highest->cpo;
> - popts->write_data_delay = pbsp_highest->write_data_delay;
> - popts->twot_en = pbsp_highest->force_2t;
> - } else {
> - panic("DIMM is not supported by this board");
> - }
> -
> -found:
> - /*
> - * Factors to consider for half-strength driver enable:
> - * - number of DIMMs installed
> - */
> - popts->half_strength_driver_enable = 0;
> - popts->dqs_config = 0; /* only true DQS signal is used on board */
> -}
> diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
> deleted file mode 100644
> index 02b5040..0000000
> --- a/board/freescale/mpc8349emds/mpc8349emds.c
> +++ /dev/null
> @@ -1,285 +0,0 @@
> -/*
> - * (C) Copyright 2006
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <asm/mpc8349_pci.h>
> -#include <i2c.h>
> -#include <spi.h>
> -#include <miiphy.h>
> -#ifdef CONFIG_SYS_FSL_DDR2
> -#include <fsl_ddr_sdram.h>
> -#else
> -#include <spd_sdram.h>
> -#endif
> -
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <libfdt.h>
> -#endif
> -
> -int fixed_sdram(void);
> -void sdram_init(void);
> -
> -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
> -void ddr_enable_ecc(unsigned int dram_size);
> -#endif
> -
> -int board_early_init_f (void)
> -{
> - volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
> -
> - /* Enable flash write */
> - bcsr[1] &= ~0x01;
> -
> -#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
> - /* Use USB PHY on SYS board */
> - bcsr[5] |= 0x02;
> -#endif
> -
> - return 0;
> -}
> -
> -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
> -
> -phys_size_t initdram (int board_type)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - phys_size_t msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
> -#if defined(CONFIG_SPD_EEPROM)
> -#ifndef CONFIG_SYS_FSL_DDR2
> - msize = spd_sdram() * 1024 * 1024;
> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> - ddr_enable_ecc(msize);
> -#endif
> -#else
> - msize = fsl_ddr_sdram();
> -#endif
> -#else
> - msize = fixed_sdram() * 1024 * 1024;
> -#endif
> - /*
> - * Initialize SDRAM if it is on local bus.
> - */
> - sdram_init();
> -
> - /* return total bus SDRAM size(bytes) -- DDR */
> - return msize;
> -}
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE;
> - u32 ddr_size = msize << 20; /* DDR size in bytes */
> - u32 ddr_size_log2 = __ilog2(ddr_size);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> -
> -#if (CONFIG_SYS_DDR_SIZE != 256)
> -#warning Currenly any ddr size other than 256 is not supported
> -#endif
> -#ifdef CONFIG_DDR_II
> - im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
> - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
> - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
> -#else
> -
> -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
> -#warning Chip select bounds is only configurable in 16MB increments
> -#endif
> - im->ddr.csbnds[2].csbnds =
> - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
> - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
> - CSBNDS_EA_SHIFT) & CSBNDS_EA);
> - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
> -
> - /* currently we use only one CS, so disable the other banks */
> - im->ddr.cs_config[0] = 0;
> - im->ddr.cs_config[1] = 0;
> - im->ddr.cs_config[3] = 0;
> -
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> -
> - im->ddr.sdram_cfg =
> - SDRAM_CFG_SREN
> -#if defined(CONFIG_DDR_2T_TIMING)
> - | SDRAM_CFG_2T_EN
> -#endif
> - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
> -#if defined (CONFIG_DDR_32BIT)
> - /* for 32-bit mode burst length is 8 */
> - im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
> -#endif
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> -
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> -#endif
> - udelay(200);
> -
> - /* enable DDR controller */
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - return msize;
> -}
> -#endif/*!CONFIG_SYS_SPD_EEPROM*/
> -
> -
> -int checkboard (void)
> -{
> - /*
> - * Warning: do not read the BCSR registers here
> - *
> - * There is a timing bug in the 8349E and 8349EA BCSR code
> - * version 1.2 (read from BCSR 11) that will cause the CFI
> - * flash initialization code to overwrite BCSR 0, disabling
> - * the serial ports and gigabit ethernet
> - */
> -
> - puts("Board: Freescale MPC8349EMDS\n");
> - return 0;
> -}
> -
> -/*
> - * if MPC8349EMDS is soldered with SDRAM
> - */
> -#if defined(CONFIG_SYS_BR2_PRELIM) \
> - && defined(CONFIG_SYS_OR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
> -/*
> - * Initialize SDRAM memory on the Local Bus.
> - */
> -
> -void sdram_init(void)
> -{
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile fsl_lbc_t *lbc = &immap->im_lbc;
> - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
> -
> - /*
> - * Setup SDRAM Base and Option Registers, already done in cpu_init.c
> - */
> -
> - /* setup mtrpt, lsrt and lbcr for LB bus */
> - lbc->lbcr = CONFIG_SYS_LBC_LBCR;
> - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
> - lbc->lsrt = CONFIG_SYS_LBC_LSRT;
> - asm("sync");
> -
> - /*
> - * Configure the SDRAM controller Machine Mode Register.
> - */
> - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
> -
> - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
> - asm("sync");
> - /*1 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*2 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*3 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*4 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*5 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*6 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*7 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*8 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x58636733; mode register write operation */
> - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -}
> -#else
> -void sdram_init(void)
> -{
> -}
> -#endif
> -
> -/*
> - * The following are used to control the SPI chip selects for the SPI command.
> - */
> -#ifdef CONFIG_MPC8XXX_SPI
> -
> -#define SPI_CS_MASK 0x80000000
> -
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> - return bus == 0 && cs == 0;
> -}
> -
> -void spi_cs_activate(struct spi_slave *slave)
> -{
> - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
> -
> - iopd->dat &= ~SPI_CS_MASK;
> -}
> -
> -void spi_cs_deactivate(struct spi_slave *slave)
> -{
> - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
> -
> - iopd->dat |= SPI_CS_MASK;
> -}
> -#endif /* CONFIG_HARD_SPI */
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
> deleted file mode 100644
> index 9f7324f..0000000
> --- a/board/freescale/mpc8349emds/pci.c
> +++ /dev/null
> @@ -1,192 +0,0 @@
> -/*
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <asm/fsl_i2c.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static struct pci_region pci1_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -static struct pci_region pci2_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI2_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
> - size: CONFIG_SYS_PCI2_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_IO_BASE,
> - phys_start: CONFIG_SYS_PCI2_IO_PHYS,
> - size: CONFIG_SYS_PCI2_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
> - size: CONFIG_SYS_PCI2_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -#endif
> -
> -#ifndef CONFIG_PCISLAVE
> -void pib_init(void)
> -{
> - u8 val8, orig_i2c_bus;
> - /*
> - * Assign PIB PMC slot to desired PCI bus
> - */
> - /* Switch temporarily to I2C bus #2 */
> - orig_i2c_bus = i2c_get_bus_num();
> - i2c_set_bus_num(1);
> -
> - val8 = 0;
> - i2c_write(0x23, 0x6, 1, &val8, 1);
> - i2c_write(0x23, 0x7, 1, &val8, 1);
> - val8 = 0xff;
> - i2c_write(0x23, 0x2, 1, &val8, 1);
> - i2c_write(0x23, 0x3, 1, &val8, 1);
> -
> - val8 = 0;
> - i2c_write(0x26, 0x6, 1, &val8, 1);
> - val8 = 0x34;
> - i2c_write(0x26, 0x7, 1, &val8, 1);
> -#if defined(PCI_64BIT)
> - val8 = 0xf4; /* PMC2:PCI1/64-bit */
> -#elif defined(PCI_ALL_PCI1)
> - val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
> -#elif defined(PCI_ONE_PCI1)
> - val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
> -#else
> - val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
> -#endif
> - i2c_write(0x26, 0x2, 1, &val8, 1);
> - val8 = 0xff;
> - i2c_write(0x26, 0x3, 1, &val8, 1);
> - val8 = 0;
> - i2c_write(0x27, 0x6, 1, &val8, 1);
> - i2c_write(0x27, 0x7, 1, &val8, 1);
> - val8 = 0xff;
> - i2c_write(0x27, 0x2, 1, &val8, 1);
> - val8 = 0xef;
> - i2c_write(0x27, 0x3, 1, &val8, 1);
> - asm("eieio");
> -
> -#if defined(PCI_64BIT)
> - printf("PCI1: 64-bit on PMC2\n");
> -#elif defined(PCI_ALL_PCI1)
> - printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
> -#elif defined(PCI_ONE_PCI1)
> - printf("PCI1: 32-bit on PMC1\n");
> - printf("PCI2: 32-bit on PMC2, PMC3\n");
> -#else
> - printf("PCI1: 32-bit on PMC1, PMC2\n");
> - printf("PCI2: 32-bit on PMC3\n");
> -#endif
> - /* Reset to original I2C bus */
> - i2c_set_bus_num(orig_i2c_bus);
> -}
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> -#ifndef CONFIG_MPC83XX_PCI2
> - struct pci_region *reg[] = { pci1_regions };
> -#else
> - struct pci_region *reg[] = { pci1_regions, pci2_regions };
> -#endif
> -
> - /* initialize the PCA9555PW IO expander on the PIB board */
> - pib_init();
> -
> - /* Enable all 8 PCI_CLK_OUTPUTS */
> - clk->occr = 0xff000000;
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> -
> - udelay(2000);
> -
> -#ifndef CONFIG_MPC83XX_PCI2
> - mpc83xx_pci_init(1, reg);
> -#else
> - mpc83xx_pci_init(2, reg);
> -#endif
> -}
> -
> -#else
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
> - struct pci_region *reg[] = { pci1_regions };
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> -
> - mpc83xx_pci_init(1, reg);
> -
> - /* Configure PCI Inbound Translation Windows (3 1MB windows) */
> - pci_ctrl->pitar0 = 0x0;
> - pci_ctrl->pibar0 = 0x0;
> - pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
> - PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
> -
> - pci_ctrl->pitar1 = 0x0;
> - pci_ctrl->pibar1 = 0x0;
> - pci_ctrl->piebar1 = 0x0;
> - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
> - PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
> -
> - pci_ctrl->pitar2 = 0x0;
> - pci_ctrl->pibar2 = 0x0;
> - pci_ctrl->piebar2 = 0x0;
> - pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
> - PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
> -
> - /* Unlock the configuration bit */
> - mpc83xx_pcislave_unlock(0);
> - printf("PCI: Agent mode enabled\n");
> -}
> -#endif /* CONFIG_PCISLAVE */
> diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
> deleted file mode 100644
> index ce3fffd..0000000
> --- a/board/freescale/mpc8349itx/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC8349ITX
> -
> -config SYS_BOARD
> - default "mpc8349itx"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC8349ITX"
> -
> -endif
> diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
> deleted file mode 100644
> index d0388ad..0000000
> --- a/board/freescale/mpc8349itx/MAINTAINERS
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -MPC8349ITX BOARD
> -#M: -
> -S: Maintained
> -F: board/freescale/mpc8349itx/
> -F: include/configs/MPC8349ITX.h
> -F: configs/MPC8349ITX_defconfig
> -F: configs/MPC8349ITX_LOWBOOT_defconfig
> -F: configs/MPC8349ITXGP_defconfig
> diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
> deleted file mode 100644
> index e9092ad..0000000
> --- a/board/freescale/mpc8349itx/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# Copyright (C) Freescale Semiconductor, Inc. 2006.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y += mpc8349itx.o
> -obj-$(CONFIG_PCI) += pci.o
> diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
> deleted file mode 100644
> index 48bbd50..0000000
> --- a/board/freescale/mpc8349itx/README
> +++ /dev/null
> @@ -1,187 +0,0 @@
> -Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
> ----------------------------------------------------
> -
> -1. Board Description
> -
> - The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
> - the Freescale MPC8349E processor in a Mini-ITX form factor.
> -
> - The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
> -
> - A) One 8MB on-board flash EEPROM chip, instead of two.
> - B) No SATA controller
> - C) No Compact Flash slot
> - D) No Mini-PCI slot
> - E) No Vitesse 7385 5-port Ethernet switch
> - F) No 4-port USB Type-A interface
> -
> -2. Board Switches and Jumpers
> -
> -2.0 Descriptions for all of the board jumpers can be found in the User
> - Guide. Of particular interest to U-Boot developers is jumper J22:
> -
> - Pos. Name Default Description
> - -----------------------------------------------------------------------
> - A LGPL0 ON (0) HRCW source, bit 0
> - B LGPL1 ON (0) HRCW source, bit 1
> - C LGPL3 ON (0) HRCW source, bit 2
> - D LGPL5 OFF (1) PCI_SYNC_OUT frequency
> - E BOOT1 ON (0) Flash EEPROM boot device
> - F PCI_M66EN ON (0) PCI 66MHz enable
> - G I2C-WP ON (0) I2C EEPROM write protection
> - H F_WP OFF (1) Flash EEPROM write protection
> -
> - Jumper J22.E is only for the ITX, and it decides the configuration
> - of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
> - U4 is located at address FE000000 and flash chip U7 is at FE800000.
> - If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
> -
> - For U-Boot development, J22.E can be used to switch back-and-forth
> - between two U-Boot images.
> -
> -3. Memory Map
> -
> -3.1. The memory map should look pretty much like this:
> -
> - 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
> - 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
> - 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
> - 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
> - 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
> - 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
> - 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
> - 0xF001_0000 - 0xF001_FFFF Local bus expansion slot
> - 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
> - 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
> - 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
> -
> -3.2 Flash EEPROM layout.
> -
> - On the ITX, jumper J22.E is used to determine which flash chips are
> - at which address. When J22.E is switched, addresses from FE000000
> - to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
> -
> - On the ITX, at the normal boot address (aka HIGHBOOT):
> -
> - FE00_0000 HRCW
> - FE70_0000 Alternative U-Boot image
> - FE80_0000 Alternative HRCW
> - FEF0_0000 U-Boot image
> - FEFF_FFFF End of flash
> -
> - On the ITX, at the low boot address (LOWBOOT)
> -
> - FE00_0000 HRCW and U-Boot image
> - FE04_0000 U-Boot environment variables
> - FE80_0000 Alternative HRCW and U-Boot image
> - FEFF_FFFF End of flash
> -
> - On the ITX-GP, the only option is LOWBOOT and there is only one chip
> -
> - FE00_0000 HRCW and U-Boot image
> - FE04_0000 U-Boot environment variables
> - F7FF_FFFF End of flash
> -
> -4. Definitions
> -
> -4.1 Explanation of NEW definitions in:
> -
> - include/configs/MPC8349ITX.h
> -
> - CONFIG_MPC83xx MPC83xx family
> - CONFIG_MPC8349 MPC8349 specific
> - CONFIG_MPC8349ITX MPC8349E-mITX
> - CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
> -
> -5. Compilation
> -
> - Assuming you're using BASH shell:
> -
> - export CROSS_COMPILE=your-cross-compile-prefix
> - cd u-boot
> - make distclean
> -
> - make MPC8349ITX_config
> - or:
> - make MPC8349ITXGP_config
> - or:
> - make MPC8349ITX_LOWBOOT_config
> -
> - make
> -
> -6. Downloading and Flashing Images
> -
> -6.1 Download via tftp:
> -
> - tftp $loadaddr <uboot>
> -
> - where "<uboot>" is the path and filename, on the TFTP server, of
> - the U-Boot image.
> -
> -6.1 Reflash U-Boot Image using U-Boot
> -
> - setenv uboot <uboot>
> - run tftpflash
> -
> - where "<uboot>" is the path and filename, on the TFTP server, of
> - the U-Boot image.
> -
> -6.2 Using the HRCW to switch between two different U-Boot images on the ITX
> -
> - Because the ITX has 16MB of flash, it is possible to keep two U-Boot
> - images in flash, and use the HRCW to specify which one is to be used
> - when the board boots. This trick is especially effective with a
> - hardware debugger that can override the HRCW, such as the BDI-2000.
> -
> - When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
> - at address FE000000. When the BMS bit is 1, the ITX will boot the
> - image at address FEF00000.
> -
> - Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
> - change the BMS bit whenever you want to boot the other image.
> -
> - Step-by-step instructions:
> -
> - 1) Build an ITX image to be loaded at FEF00000
> -
> - make distclean
> - make MPC8349ITX_config
> - make
> -
> - 2) Take the u-boot.bin image and flash it at FEF00000.
> -
> - tftp $loadaddr u-boot.bin
> - protect off all
> - erase FEF00000 +$filesize
> - cp.b $loadaddr FEF00000 $filesize
> -
> - 3) Build an ITX image to be loaded at FE000000
> -
> - make distclean
> - make MPC8349ITX_LOWBOOT_config
> - make
> -
> - 4) Take the u-boot.bin image and flash it at FE000000.
> -
> - tftp $loadaddr u-boot.bin
> - protect off FE000000 +$filesize
> - erase FE000000 +$filesize
> - cp.b $loadaddr FE000000 $filesize
> -
> - The HRCW in flash is currently set to boot the image at FE000000.
> -
> - If you have a hardware debugger, configure it to set the HRCW to
> - B460A000 04040000 if you want to boot the image at FEF00000, or set
> - it to B060A000 04040000 if you want to boot the image at FE000000.
> -
> - To change the HRCW in flash to boot the image at FEF00000, use these
> - U-Boot commands:
> -
> - cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
> - mw.b 1020 b4 8 ; modify BMS bit
> - protect off FE000000 +10000
> - erase FE000000 +10000
> - cp.b 1000 FE000000 10000
> -
> -7. Notes
> - 1) The console baudrate for MPC8349EITX is 115200bps.
> diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
> deleted file mode 100644
> index 22a1d99..0000000
> --- a/board/freescale/mpc8349itx/mpc8349itx.c
> +++ /dev/null
> @@ -1,390 +0,0 @@
> -/*
> - * Copyright (C) Freescale Semiconductor, Inc. 2006.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <i2c.h>
> -#include <miiphy.h>
> -#include <vsc7385.h>
> -#ifdef CONFIG_PCI
> -#include <asm/mpc8349_pci.h>
> -#include <pci.h>
> -#endif
> -#include <spd_sdram.h>
> -#include <asm/mmu.h>
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <libfdt.h>
> -#endif
> -
> -#ifndef CONFIG_SPD_EEPROM
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - /* The size of RAM, in bytes */
> - u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
> - u32 ddr_size_log2 = __ilog2(ddr_size);
> -
> - im->sysconf.ddrlaw[0].ar =
> - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
> -
> -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
> -#warning Chip select bounds is only configurable in 16MB increments
> -#endif
> - im->ddr.csbnds[0].csbnds =
> - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
> - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
> - CSBNDS_EA_SHIFT) & CSBNDS_EA);
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> -
> - /* Only one CS for DDR */
> - im->ddr.cs_config[1] = 0;
> - im->ddr.cs_config[2] = 0;
> - im->ddr.cs_config[3] = 0;
> -
> - debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
> - debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
> -
> - debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
> - debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
> -
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
> - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
> - im->ddr.sdram_mode =
> - (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
> - im->ddr.sdram_interval =
> - (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
> - SDRAM_INTERVAL_BSTOPRE_SHIFT);
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
> -
> - udelay(200);
> -
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> -
> - debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
> - debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
> - debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
> - debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
> - debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
> -
> - return CONFIG_SYS_DDR_SIZE;
> -}
> -#endif
> -
> -#ifdef CONFIG_PCI
> -/*
> - * Initialize PCI Devices, report devices found
> - */
> -#ifndef CONFIG_PCI_PNP
> -static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
> - {
> - PCI_ANY_ID,
> - PCI_ANY_ID,
> - PCI_ANY_ID,
> - PCI_ANY_ID,
> - 0x0f,
> - PCI_ANY_ID,
> - pci_cfgfunc_config_device,
> - {
> - PCI_ENET0_IOADDR,
> - PCI_ENET0_MEMADDR,
> - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
> - },
> - {}
> -}
> -#endif
> -
> -volatile static struct pci_controller hose[] = {
> - {
> -#ifndef CONFIG_PCI_PNP
> - config_table:pci_mpc83xxmitx_config_table,
> -#endif
> - },
> - {
> -#ifndef CONFIG_PCI_PNP
> - config_table:pci_mpc83xxmitx_config_table,
> -#endif
> - }
> -};
> -#endif /* CONFIG_PCI */
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -#ifdef CONFIG_DDR_ECC
> - volatile ddr83xx_t *ddr = &im->ddr;
> -#endif
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
> -#ifdef CONFIG_SPD_EEPROM
> - msize = spd_sdram();
> -#else
> - msize = fixed_sdram();
> -#endif
> -
> -#ifdef CONFIG_DDR_ECC
> - if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
> - /* Unlike every other board, on the 83xx spd_sdram() returns
> - megabytes instead of just bytes. That's why we need to
> - multiple by 1MB when calling ddr_enable_ecc(). */
> - ddr_enable_ecc(msize * 1048576);
> -#endif
> -
> - /* return total bus RAM size(bytes) */
> - return msize * 1024 * 1024;
> -}
> -
> -int checkboard(void)
> -{
> -#ifdef CONFIG_MPC8349ITX
> - puts("Board: Freescale MPC8349E-mITX\n");
> -#else
> - puts("Board: Freescale MPC8349E-mITX-GP\n");
> -#endif
> -
> - return 0;
> -}
> -
> -/*
> - * Implement a work-around for a hardware problem with compact
> - * flash.
> - *
> - * Program the UPM if compact flash is enabled.
> - */
> -int misc_init_f(void)
> -{
> -#ifdef CONFIG_VSC7385_ENET
> - volatile u32 *vsc7385_cpuctrl;
> -
> - /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
> - default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
> - means it is 0 when the IRQ is not active. This makes the wire-AND
> - logic always assert IRQ7 to CPU even if there is no request from the
> - switch. Since the compact flash and the switch share the same IRQ,
> - the Linux kernel will think that the compact flash is requesting irq
> - and get stuck when it tries to clear the IRQ. Thus we need to set
> - the L2_IRQ0 and L2_IRQ1 to active low.
> -
> - The following code sets the L1_IRQ and L2_IRQ polarity to active low.
> - Without this code, compact flash will not work in Linux because
> - unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
> - don't enable compact flash for U-Boot.
> - */
> -
> - vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
> - *vsc7385_cpuctrl |= 0x0c;
> -#endif
> -
> -#ifdef CONFIG_COMPACT_FLASH
> - /* UPM Table Configuration Code */
> - static uint UPMATable[] = {
> - 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
> - 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
> - 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
> - 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
> - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
> - };
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
> - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
> -
> - /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
> - GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
> - */
> - immap->im_lbc.mamr = 0x08404440;
> -
> - upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
> -
> - puts("UPMA: Configured for compact flash\n");
> -#endif
> -
> - return 0;
> -}
> -
> -/*
> - * Miscellaneous late-boot configurations
> - *
> - * Make sure the EEPROM has the HRCW correctly programmed.
> - * Make sure the RTC is correctly programmed.
> - *
> - * The MPC8349E-mITX can be configured to load the HRCW from
> - * EEPROM instead of flash. This is controlled via jumpers
> - * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
> - * jumpered), but if they're set to 001 or 010, then the HRCW is
> - * read from the "I2C EEPROM".
> - *
> - * This function makes sure that the I2C EEPROM is programmed
> - * correctly.
> - *
> - * If a VSC7385 microcode image is present, then upload it.
> - */
> -int misc_init_r(void)
> -{
> - int rc = 0;
> -
> -#if defined(CONFIG_SYS_I2C)
> - unsigned int orig_bus = i2c_get_bus_num();
> - u8 i2c_data;
> -
> -#ifdef CONFIG_SYS_I2C_RTC_ADDR
> - u8 ds1339_data[17];
> -#endif
> -
> -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
> - static u8 eeprom_data[] = /* HRCW data */
> - {
> - 0xAA, 0x55, 0xAA, /* Preamble */
> - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
> - 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
> - (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
> - (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
> - (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
> - CONFIG_SYS_HRCW_LOW & 0xFF,
> - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
> - 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
> - (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
> - (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
> - (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
> - CONFIG_SYS_HRCW_HIGH & 0xFF
> - };
> -
> - u8 data[sizeof(eeprom_data)];
> -#endif
> -
> - printf("Board revision: ");
> - i2c_set_bus_num(1);
> - if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
> - printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
> - else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
> - printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
> - else {
> - printf("Unknown\n");
> - rc = 1;
> - }
> -
> -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
> - i2c_set_bus_num(0);
> -
> - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
> - if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
> - if (i2c_write
> - (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
> - sizeof(eeprom_data)) != 0) {
> - puts("Failure writing the HRCW to EEPROM via I2C.\n");
> - rc = 1;
> - }
> - }
> - } else {
> - puts("Failure reading the HRCW from EEPROM via I2C.\n");
> - rc = 1;
> - }
> -#endif
> -
> -#ifdef CONFIG_SYS_I2C_RTC_ADDR
> - i2c_set_bus_num(1);
> -
> - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
> - == 0) {
> -
> - /* Work-around for MPC8349E-mITX bug #13601.
> - If the RTC does not contain valid register values, the DS1339
> - Linux driver will not work.
> - */
> -
> - /* Make sure status register bits 6-2 are zero */
> - ds1339_data[0x0f] &= ~0x7c;
> -
> - /* Check for a valid day register value */
> - ds1339_data[0x03] &= ~0xf8;
> - if (ds1339_data[0x03] == 0) {
> - ds1339_data[0x03] = 1;
> - }
> -
> - /* Check for a valid date register value */
> - ds1339_data[0x04] &= ~0xc0;
> - if ((ds1339_data[0x04] == 0) ||
> - ((ds1339_data[0x04] & 0x0f) > 9) ||
> - (ds1339_data[0x04] >= 0x32)) {
> - ds1339_data[0x04] = 1;
> - }
> -
> - /* Check for a valid month register value */
> - ds1339_data[0x05] &= ~0x60;
> -
> - if ((ds1339_data[0x05] == 0) ||
> - ((ds1339_data[0x05] & 0x0f) > 9) ||
> - ((ds1339_data[0x05] >= 0x13)
> - && (ds1339_data[0x05] <= 0x19))) {
> - ds1339_data[0x05] = 1;
> - }
> -
> - /* Enable Oscillator and rate select */
> - ds1339_data[0x0e] = 0x1c;
> -
> - /* Work-around for MPC8349E-mITX bug #13330.
> - Ensure that the RTC control register contains the value 0x1c.
> - This affects SATA performance.
> - */
> -
> - if (i2c_write
> - (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
> - sizeof(ds1339_data))) {
> - puts("Failure writing to the RTC via I2C.\n");
> - rc = 1;
> - }
> - } else {
> - puts("Failure reading from the RTC via I2C.\n");
> - rc = 1;
> - }
> -#endif
> -
> - i2c_set_bus_num(orig_bus);
> -#endif
> -
> -#ifdef CONFIG_VSC7385_IMAGE
> - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> - CONFIG_VSC7385_IMAGE_SIZE)) {
> - puts("Failure uploading VSC7385 microcode.\n");
> - rc = 1;
> - }
> -#endif
> -
> - return rc;
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
> deleted file mode 100644
> index afc9df0..0000000
> --- a/board/freescale/mpc8349itx/pci.c
> +++ /dev/null
> @@ -1,105 +0,0 @@
> -/*
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <asm/fsl_i2c.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static struct pci_region pci1_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -static struct pci_region pci2_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI2_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
> - size: CONFIG_SYS_PCI2_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_IO_BASE,
> - phys_start: CONFIG_SYS_PCI2_IO_PHYS,
> - size: CONFIG_SYS_PCI2_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
> - size: CONFIG_SYS_PCI2_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -#endif
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> -#ifndef CONFIG_MPC83XX_PCI2
> - struct pci_region *reg[] = { pci1_regions };
> -#else
> - struct pci_region *reg[] = { pci1_regions, pci2_regions };
> -#endif
> - u8 reg8;
> -
> -#if defined(CONFIG_SYS_I2C)
> - i2c_set_bus_num(1);
> - /* Read the PCI_M66EN jumper setting */
> - if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
> - (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
> - if (reg8 & I2C_8574_PCI66)
> - clk->occr = 0xff000000; /* 66 MHz PCI */
> - else
> - clk->occr = 0xff600001; /* 33 MHz PCI */
> - } else {
> - clk->occr = 0xff600001; /* 33 MHz PCI */
> - }
> -#else
> - clk->occr = 0xff000000; /* 66 MHz PCI */
> -#endif
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
> -
> - udelay(2000);
> -
> -#ifndef CONFIG_MPC83XX_PCI2
> - mpc83xx_pci_init(1, reg);
> -#else
> - mpc83xx_pci_init(2, reg);
> -#endif
> -}
> diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig
> deleted file mode 100644
> index 20d29db..0000000
> --- a/board/freescale/mpc837xemds/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MPC837XEMDS
> -
> -config SYS_BOARD
> - default "mpc837xemds"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "MPC837XEMDS"
> -
> -endif
> diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
> deleted file mode 100644
> index 6ff1346..0000000
> --- a/board/freescale/mpc837xemds/MAINTAINERS
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -MPC837XEMDS BOARD
> -M: Dave Liu <daveliu@freescale.com>
> -S: Maintained
> -F: board/freescale/mpc837xemds/
> -F: include/configs/MPC837XEMDS.h
> -F: configs/MPC837XEMDS_defconfig
> -F: configs/MPC837XEMDS_HOST_defconfig
> diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
> deleted file mode 100644
> index 70b2147..0000000
> --- a/board/freescale/mpc837xemds/Makefile
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y += mpc837xemds.o
> -obj-$(CONFIG_PCI) += pci.o
> diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README
> deleted file mode 100644
> index faf21c9..0000000
> --- a/board/freescale/mpc837xemds/README
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -Freescale MPC837xEMDS Board
> ------------------------------------------
> -1. Board Switches and Jumpers
> -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
> - For some reason, the HW designers describe the switch settings
> - in terms of 0 and 1, and then map that to physical switches where
> - the label "On" refers to logic 0 and "Off" is logic 1.
> -
> - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
> - bits may contribute to signals that are numbered based at 0,
> - and some of those signals may be high-bit-number-0 too. Heed
> - well the names and labels and do not get confused.
> -
> - "Off" == 1
> - "On" == 0
> -
> - SW4[8] is the bit labeled 8 on Switch 4.
> - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
> - SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
> - and bits labeled 8 is set as "Off".
> -
> -1.1 For the MPC837xEMDS Processor Board
> -
> - First, make sure the board default setting is consistent with the
> - document shipped with your board. Then apply the following setting:
> - SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
> - SW4[1-8]= 0000_0110 (core PLL setting)
> - SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
> - SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
> - SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
> - J3 2-3, TSEC1 LVDD1 with 2.5V
> - J6 2-3, TSEC2 LVDD2 with 2.5V
> - J9 2-3, CLKIN from osc on board
> - J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
> - J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
> - mounted, HRCW load from BCSR.
> -
> - on board Oscillator: 66M
> -
> -2. Memory Map
> -
> -2.1. The memory map should look pretty much like this:
> -
> - 0x0000_0000 0x7fff_ffff DDR 2G
> - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
> - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
> - 0xc000_0000 0xdfff_ffff Empty 512M
> - 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
> - 0xe010_0000 0xe02f_ffff Empty 2M
> - 0xe030_0000 0xe03f_ffff PCI IO 1M
> - 0xe040_0000 0xe05f_ffff Empty 2M
> - 0xe060_0000 0xe060_7fff NAND Flash 32K
> - 0xf400_0000 0xf7ff_ffff Empty 64M
> - 0xf800_0000 0xf800_7fff BCSR on CS1 32K
> - 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
> -
> -3. Definitions
> -
> -3.1 Explanation of NEW definitions in:
> -
> - include/configs/MPC837XEMDS.h
> -
> - CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
> - CONFIG_MPC837x MPC837x specific
> - CONFIG_MPC837XEMDS MPC837XEMDS board specific
> -
> -4. Compilation
> -
> - Assuming you're using BASH shell:
> -
> - export CROSS_COMPILE=your-cross-compile-prefix
> - cd u-boot
> - make distclean
> - make MPC837XEMDS_config
> - make
> -
> -5. Downloading and Flashing Images
> -
> -5.0 Download over serial line using Kermit:
> -
> - loadb
> - [Drop to kermit:
> - ^\c
> - send <u-boot-bin-image>
> - c
> - ]
> -
> -
> - Or via tftp:
> -
> - tftp 40000 u-boot.bin
> -
> -5.1 Reflash U-boot Image using U-boot
> -
> - tftp 40000 u-boot.bin
> - protect off fe000000 fe1fffff
> - erase fe000000 fe1fffff
> -
> - cp.b 40000 fe000000 xxxx
> -
> -You have to supply the correct byte count with 'xxxx' from the TFTP result log.
> -
> -6. Notes
> - 1) The console baudrate for MPC837XEMDS is 115200bps.
> diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
> deleted file mode 100644
> index 572913c..0000000
> --- a/board/freescale/mpc837xemds/mpc837xemds.c
> +++ /dev/null
> @@ -1,346 +0,0 @@
> -/*
> - * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
> - * Dave Liu <daveliu@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <hwconfig.h>
> -#include <i2c.h>
> -#include <asm/io.h>
> -#include <asm/fsl_mpc83xx_serdes.h>
> -#include <spd_sdram.h>
> -#include <tsec.h>
> -#include <libfdt.h>
> -#include <fdt_support.h>
> -#include <fsl_esdhc.h>
> -#include <fsl_mdio.h>
> -#include <phy.h>
> -#include "pci.h"
> -#include "../common/pq-mds-pib.h"
> -
> -int board_early_init_f(void)
> -{
> - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
> -
> - /* Enable flash write */
> - bcsr[0x9] &= ~0x04;
> - /* Clear all of the interrupt of BCSR */
> - bcsr[0xe] = 0xff;
> -
> -#ifdef CONFIG_FSL_SERDES
> - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> - u32 spridr = in_be32(&immr->sysconf.spridr);
> -
> - /* we check only part num, and don't look for CPU revisions */
> - switch (PARTID_NO_E(spridr)) {
> - case SPR_8377:
> - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> - break;
> - case SPR_8378:
> - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
> - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
> - break;
> - case SPR_8379:
> - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> - break;
> - default:
> - printf("serdes not configured: unknown CPU part number: "
> - "%04x\n", spridr >> 16);
> - break;
> - }
> -#endif /* CONFIG_FSL_SERDES */
> - return 0;
> -}
> -
> -#ifdef CONFIG_FSL_ESDHC
> -int board_mmc_init(bd_t *bd)
> -{
> - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
> - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
> -
> - if (!hwconfig("esdhc"))
> - return 0;
> -
> - /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
> - bcsr[0xc] |= 0x4c;
> -
> - /* Set proper bits in SICR to allow SD signals through */
> - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
> - clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
> - SICRH_GPIO2_E_SD | SICRH_SPI_SD);
> -
> - return fsl_esdhc_mmc_init(bd);
> -}
> -#endif
> -
> -#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
> -int board_eth_init(bd_t *bd)
> -{
> - struct fsl_pq_mdio_info mdio_info;
> - struct tsec_info_struct tsec_info[2];
> - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
> - u32 rcwh = in_be32(&im->reset.rcwh);
> - u32 tsec_mode;
> - int num = 0;
> -
> - /* New line after Net: */
> - printf("\n");
> -
> -#ifdef CONFIG_TSEC1
> - SET_STD_TSEC_INFO(tsec_info[num], 1);
> -
> - printf(CONFIG_TSEC1_NAME ": ");
> -
> - tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
> - if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
> - printf("RGMII\n");
> - /* this is default, no need to fixup */
> - } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
> - printf("SGMII\n");
> - tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
> - tsec_info[num].flags = TSEC_GIGABIT;
> - } else {
> - printf("unsupported PHY type\n");
> - }
> - num++;
> -#endif
> -#ifdef CONFIG_TSEC2
> - SET_STD_TSEC_INFO(tsec_info[num], 2);
> -
> - printf(CONFIG_TSEC2_NAME ": ");
> -
> - tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
> - if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
> - printf("RGMII\n");
> - /* this is default, no need to fixup */
> - } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
> - printf("SGMII\n");
> - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
> - tsec_info[num].flags = TSEC_GIGABIT;
> - } else {
> - printf("unsupported PHY type\n");
> - }
> - num++;
> -#endif
> -
> - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
> - mdio_info.name = DEFAULT_MII_NAME;
> - fsl_pq_mdio_init(bd, &mdio_info);
> -
> - return tsec_eth_init(bd, tsec_info, num);
> -}
> -
> -static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
> - int phy_addr)
> -{
> - const u32 *ph;
> - int off;
> - int err;
> -
> - off = fdt_path_offset(blob, alias);
> - if (off < 0) {
> - printf("WARNING: could not find %s alias: %s.\n", alias,
> - fdt_strerror(off));
> - return;
> - }
> -
> - err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
> -
> - if (err) {
> - printf("WARNING: could not set phy-connection-type for %s: "
> - "%s.\n", alias, fdt_strerror(err));
> - return;
> - }
> -
> - ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
> - if (!ph) {
> - printf("WARNING: could not get phy-handle for %s.\n",
> - alias);
> - return;
> - }
> -
> - off = fdt_node_offset_by_phandle(blob, *ph);
> - if (off < 0) {
> - printf("WARNING: could not get phy node for %s: %s\n", alias,
> - fdt_strerror(off));
> - return;
> - }
> -
> - phy_addr = cpu_to_fdt32(phy_addr);
> - err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
> - if (err < 0) {
> - printf("WARNING: could not set phy node's reg for %s: "
> - "%s.\n", alias, fdt_strerror(err));
> - return;
> - }
> -}
> -
> -static void ft_tsec_fixup(void *blob, bd_t *bd)
> -{
> - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
> - u32 rcwh = in_be32(&im->reset.rcwh);
> - u32 tsec_mode;
> -
> -#ifdef CONFIG_TSEC1
> - tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
> - if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
> - __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
> -#endif
> -
> -#ifdef CONFIG_TSEC2
> - tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
> - if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
> - __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
> -#endif
> -}
> -#else
> -static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
> -#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
> -
> -int board_early_init_r(void)
> -{
> -#ifdef CONFIG_PQ_MDS_PIB
> - pib_init();
> -#endif
> - return 0;
> -}
> -
> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> -extern void ddr_enable_ecc(unsigned int dram_size);
> -#endif
> -int fixed_sdram(void);
> -
> -phys_size_t initdram(int board_type)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
> - return -1;
> -
> -#if defined(CONFIG_SPD_EEPROM)
> - msize = spd_sdram();
> -#else
> - msize = fixed_sdram();
> -#endif
> -
> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> - /* Initialize DDR ECC byte */
> - ddr_enable_ecc(msize * 1024 * 1024);
> -#endif
> -
> - /* return total bus DDR size(bytes) */
> - return (msize * 1024 * 1024);
> -}
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> - u32 msize_log2 = __ilog2(msize);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
> -
> -#if (CONFIG_SYS_DDR_SIZE != 512)
> -#warning Currenly any ddr size other than 512 is not supported
> -#endif
> - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
> - udelay(50000);
> -
> - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
> - udelay(1000);
> -
> - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
> - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
> - udelay(1000);
> -
> - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
> - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - __asm__ __volatile__("sync");
> - udelay(1000);
> -
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - udelay(2000);
> - return CONFIG_SYS_DDR_SIZE;
> -}
> -#endif /*!CONFIG_SYS_SPD_EEPROM */
> -
> -int checkboard(void)
> -{
> - puts("Board: Freescale MPC837xEMDS\n");
> - return 0;
> -}
> -
> -#ifdef CONFIG_PCI
> -int board_pci_host_broken(void)
> -{
> - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
> - const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
> -
> - /* It's always OK in case of external arbiter. */
> - if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
> - return 0;
> -
> - if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
> - return 1;
> -
> - return 0;
> -}
> -
> -static void ft_pci_fixup(void *blob, bd_t *bd)
> -{
> - const char *status = "broken (no arbiter)";
> - int off;
> - int err;
> -
> - off = fdt_path_offset(blob, "pci0");
> - if (off < 0) {
> - printf("WARNING: could not find pci0 alias: %s.\n",
> - fdt_strerror(off));
> - return;
> - }
> -
> - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
> - if (err) {
> - printf("WARNING: could not set status for pci0: %s.\n",
> - fdt_strerror(err));
> - return;
> - }
> -}
> -#endif
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - ft_cpu_setup(blob, bd);
> - ft_tsec_fixup(blob, bd);
> - fdt_fixup_dr_usb(blob, bd);
> - fdt_fixup_esdhc(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> - if (board_pci_host_broken())
> - ft_pci_fixup(blob, bd);
> - ft_pcie_fixup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif /* CONFIG_OF_BOARD_SETUP */
> diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
> deleted file mode 100644
> index 39c40e5..0000000
> --- a/board/freescale/mpc837xemds/pci.c
> +++ /dev/null
> @@ -1,147 +0,0 @@
> -/*
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <fdt_support.h>
> -#include <asm/fsl_i2c.h>
> -#include <asm/fsl_mpc83xx_serdes.h>
> -
> -static struct pci_region pci_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI_MEM_PHYS,
> - size: CONFIG_SYS_PCI_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
> - size: CONFIG_SYS_PCI_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> - {
> - bus_start: CONFIG_SYS_PCI_IO_BASE,
> - phys_start: CONFIG_SYS_PCI_IO_PHYS,
> - size: CONFIG_SYS_PCI_IO_SIZE,
> - flags: PCI_REGION_IO
> - }
> -};
> -
> -static struct pci_region pcie_regions_0[] = {
> - {
> - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
> - .size = CONFIG_SYS_PCIE1_MEM_SIZE,
> - .flags = PCI_REGION_MEM,
> - },
> - {
> - .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
> - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
> - .size = CONFIG_SYS_PCIE1_IO_SIZE,
> - .flags = PCI_REGION_IO,
> - },
> -};
> -
> -static struct pci_region pcie_regions_1[] = {
> - {
> - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
> - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
> - .size = CONFIG_SYS_PCIE2_MEM_SIZE,
> - .flags = PCI_REGION_MEM,
> - },
> - {
> - .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
> - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
> - .size = CONFIG_SYS_PCIE2_IO_SIZE,
> - .flags = PCI_REGION_IO,
> - },
> -};
> -
> -static int is_pex_x2(void)
> -{
> - const char *pex_x2 = getenv("pex_x2");
> -
> - if (pex_x2 && !strcmp(pex_x2, "yes"))
> - return 1;
> - return 0;
> -}
> -
> -void pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile sysconf83xx_t *sysconf = &immr->sysconf;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - volatile law83xx_t *pcie_law = sysconf->pcielaw;
> - struct pci_region *reg[] = { pci_regions };
> - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
> - u32 spridr = in_be32(&immr->sysconf.spridr);
> - int pex2 = is_pex_x2();
> -
> - if (board_pci_host_broken())
> - goto skip_pci;
> -
> - /* Enable all 5 PCI_CLK_OUTPUTS */
> - clk->occr |= 0xf8000000;
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
> -
> - udelay(2000);
> -
> - mpc83xx_pci_init(1, reg);
> -skip_pci:
> - /* There is no PEX in MPC8379 parts. */
> - if (PARTID_NO_E(spridr) == SPR_8379)
> - return;
> -
> - if (pex2)
> - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> - else
> - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
> - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> -
> - /* Configure the clock for PCIE controller */
> - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
> - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
> -
> - /* Deassert the resets in the control register */
> - out_be32(&sysconf->pecr1, 0xE0008000);
> - if (!pex2)
> - out_be32(&sysconf->pecr2, 0xE0008000);
> - udelay(2000);
> -
> - /* Configure PCI Express Local Access Windows */
> - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
> - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
> -
> - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
> - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
> -
> - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
> -}
> -
> -void ft_pcie_fixup(void *blob, bd_t *bd)
> -{
> - const char *status = "disabled (PCIE1 is x2)";
> -
> - if (!is_pex_x2())
> - return;
> -
> - do_fixup_by_path(blob, "pci2", "status", status,
> - strlen(status) + 1, 1);
> -}
> diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h
> deleted file mode 100644
> index fd7a916..0000000
> --- a/board/freescale/mpc837xemds/pci.h
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#ifndef __BOARD_MPC837XEMDS_PCI_H
> -#define __BOARD_MPC837XEMDS_PCI_H
> -
> -extern void ft_pcie_fixup(void *blob, bd_t *bd);
> -
> -#endif /* __BOARD_MPC837XEMDS_PCI_H */
> diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
> deleted file mode 100644
> index 64717ec..0000000
> --- a/configs/MPC8308RDB_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8308RDB=y
> diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
> deleted file mode 100644
> index ca6c304..0000000
> --- a/configs/MPC8313ERDB_33_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8313ERDB=y
> diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
> deleted file mode 100644
> index 974bdf9..0000000
> --- a/configs/MPC8313ERDB_66_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8313ERDB=y
> diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
> deleted file mode 100644
> index ba81885..0000000
> --- a/configs/MPC8313ERDB_NAND_33_defconfig
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -CONFIG_SPL=y
> -CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8313ERDB=y
> diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
> deleted file mode 100644
> index afe8740..0000000
> --- a/configs/MPC8313ERDB_NAND_66_defconfig
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -CONFIG_SPL=y
> -CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8313ERDB=y
> diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
> deleted file mode 100644
> index ebebbed..0000000
> --- a/configs/MPC8315ERDB_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8315ERDB=y
> diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
> deleted file mode 100644
> index 7c03842..0000000
> --- a/configs/MPC8323ERDB_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8323ERDB=y
> diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
> deleted file mode 100644
> index e1ba08d..0000000
> --- a/configs/MPC832XEMDS_ATM_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC832XEMDS=y
> diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
> deleted file mode 100644
> index 55df0f6..0000000
> --- a/configs/MPC832XEMDS_HOST_33_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC832XEMDS=y
> diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
> deleted file mode 100644
> index 1ceee68..0000000
> --- a/configs/MPC832XEMDS_HOST_66_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC832XEMDS=y
> diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
> deleted file mode 100644
> index ef67be5..0000000
> --- a/configs/MPC832XEMDS_SLAVE_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC832XEMDS=y
> diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
> deleted file mode 100644
> index 0398472..0000000
> --- a/configs/MPC832XEMDS_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC832XEMDS=y
> diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
> deleted file mode 100644
> index f6af218..0000000
> --- a/configs/MPC8349EMDS_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8349EMDS=y
> diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
> deleted file mode 100644
> index f853309..0000000
> --- a/configs/MPC8349ITXGP_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8349ITX=y
> diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
> deleted file mode 100644
> index 5321801..0000000
> --- a/configs/MPC8349ITX_LOWBOOT_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8349ITX=y
> diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
> deleted file mode 100644
> index 83f25ae..0000000
> --- a/configs/MPC8349ITX_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC8349ITX=y
> diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
> deleted file mode 100644
> index d3be43a..0000000
> --- a/configs/MPC837XEMDS_HOST_defconfig
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="PCI"
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC837XEMDS=y
> diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
> deleted file mode 100644
> index d3b7c1d..0000000
> --- a/configs/MPC837XEMDS_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC837XEMDS=y
> diff --git a/doc/README.scrapyard b/doc/README.scrapyard
> index 59d2142..b8c9f9c 100644
> --- a/doc/README.scrapyard
> +++ b/doc/README.scrapyard
> @@ -12,6 +12,14 @@ The list should be sorted in reverse chronological order.
>
> Board Arch CPU Commit Removed Last known maintainer/contact
> =================================================================================================
> +MPC8308RDB powerpc mpc83xx - - Ilya Yanok <yanok@emcraft.com>
> +MPC8313ERDB powerpc mpc83xx - -
> +MPC8315ERDB powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
> +MPC8323ERDB powerpc mpc83xx - - Michael Barkowski <michael.barkowski@freescale.com>
> +MPC832XEMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
> +MPC8349EMDS powerpc mpc83xx - - Kim Phillips <kim.phillips@freescale.com>
> +MPC8349ITX powerpc mpc83xx - -
> +MPC837XEMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
> korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
> galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
> W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
> diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
> deleted file mode 100644
> index bf974fd..0000000
> --- a/include/configs/MPC8308RDB.h
> +++ /dev/null
> @@ -1,582 +0,0 @@
> -/*
> - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
> - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> - *
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 family */
> -#define CONFIG_MPC830x 1 /* MPC830x family */
> -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
> -#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -
> -#define CONFIG_MISC_INIT_R
> -
> -/* new uImage format support */
> -#define CONFIG_FIT 1
> -#define CONFIG_FIT_VERBOSE 1
> -
> -#define CONFIG_MMC 1
> -
> -#ifdef CONFIG_MMC
> -#define CONFIG_FSL_ESDHC
> -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
> -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> -#define CONFIG_SYS_FSL_ESDHC_USE_PIO
> -
> -#define CONFIG_CMD_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_CMD_FAT
> -#define CONFIG_DOS_PARTITION
> -#endif
> -
> -/*
> - * On-board devices
> - *
> - * TSEC1 is SoC TSEC
> - * TSEC2 is VSC switch
> - */
> -#define CONFIG_TSEC1
> -#define CONFIG_VSC7385_ENET
> -
> -/*
> - * System Clock Setup
> - */
> -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
> -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
> -
> -/*
> - * Hardware Reset Configuration Word
> - * if CLKIN is 66.66MHz, then
> - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
> - * We choose the A type silicon as default, so the core is 400Mhz.
> - */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_SVCOD_DIV_2 |\
> - HRCWL_CSB_TO_CLKIN_4X1 |\
> - HRCWL_CORE_TO_CSB_3X1)
> -/*
> - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
> - * in 8308's HRCWH according to the manual, but original Freescale's
> - * code has them and I've expirienced some problems using the board
> - * with BDI3000 attached when I've tried to set these bits to zero
> - * (UART doesn't work after the 'reset run' command).
> - */
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_RL_EXT_LEGACY |\
> - HRCWH_TSEC1M_IN_RGMII |\
> - HRCWH_TSEC2M_IN_RGMII |\
> - HRCWH_BIG_ENDIAN)
> -
> -/*
> - * System IO Config
> - */
> -#define CONFIG_SYS_SICRH (\
> - SICRH_ESDHC_A_SD |\
> - SICRH_ESDHC_B_SD |\
> - SICRH_ESDHC_C_SD |\
> - SICRH_GPIO_A_TSEC2 |\
> - SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
> - SICRH_IEEE1588_A_GPIO |\
> - SICRH_USB |\
> - SICRH_GTM_GPIO |\
> - SICRH_IEEE1588_B_GPIO |\
> - SICRH_ETSEC2_CRS |\
> - SICRH_GPIOSEL_1 |\
> - SICRH_TMROBI_V3P3 |\
> - SICRH_TSOBI1_V2P5 |\
> - SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
> -#define CONFIG_SYS_SICRL (\
> - SICRL_SPI_PF0 |\
> - SICRL_UART_PF0 |\
> - SICRL_IRQ_PF0 |\
> - SICRL_I2C2_PF0 |\
> - SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
> -
> -/*
> - * IMMR new address
> - */
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -/*
> - * SERDES
> - */
> -#define CONFIG_FSL_SERDES
> -#define CONFIG_FSL_SERDES1 0xe3000
> -
> -/*
> - * Arbiter Setup
> - */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
> -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
> - | DDRCDR_PZ_LOZ \
> - | DDRCDR_NZ_LOZ \
> - | DDRCDR_ODT \
> - | DDRCDR_Q_DRN)
> - /* 0x7b880001 */
> -/*
> - * Manually set up DDR parameters
> - * consist of two chips HY5PS12621BFP-C4 from HYNIX
> - */
> -
> -#define CONFIG_SYS_DDR_SIZE 128 /* MB */
> -
> -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ODT_RD_NEVER \
> - | CSCONFIG_ODT_WR_ONLY_CURRENT \
> - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
> - /* 0x80010102 */
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00220802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (6 << TIMING_CFG1_REFREC_SHIFT) \
> - | (2 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x27256222 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (4 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x121048c5 */
> -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x03600100 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_DBW_32)
> - /* 0x43080000 */
> -
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
> -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x0232 << SDRAM_MODE_SD_SHIFT))
> - /* ODT 150ohm CL=3, AL=1 on SDRAM */
> -#define CONFIG_SYS_DDR_MODE2 0x00000000
> -
> -/*
> - * Memory test
> - */
> -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x07f00000
> -
> -/*
> - * The reserved memory
> - */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Initial RAM Base Address Setup
> - */
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * Local Bus Configuration & Clock Setup
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
> -#define CONFIG_SYS_LBC_LBCR 0x00040000
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> -
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> -/* Window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_UPM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET)
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -/* 127 64KB sectors and 8 8KB top sectors per device */
> -#define CONFIG_SYS_MAX_FLASH_SECT 135
> -
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -/*
> - * NAND Flash on the Local Bus
> - */
> -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
> -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
> -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
> - | BR_DECC_CHK_GEN /* Use HW ECC */ \
> - | BR_PS_8 /* 8 bit Port */ \
> - | BR_MS_FCM /* MSEL = FCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
> - | OR_FCM_CSCT \
> - | OR_FCM_CST \
> - | OR_FCM_CHT \
> - | OR_FCM_SCY_1 \
> - | OR_FCM_TRLX \
> - | OR_FCM_EHTR)
> - /* 0xFFFF8396 */
> -
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -#ifdef CONFIG_VSC7385_ENET
> -#define CONFIG_TSEC2
> - /* VSC7385 Base address on CS2 */
> -#define CONFIG_SYS_VSC7385_BASE 0xF0000000
> -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
> -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
> - | BR_PS_8 /* 8-bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> - /* 0xF0000801 */
> -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_SETA \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET)
> - /* 0xFFFE09FF */
> -/* Access window base at VSC7385 base */
> -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
> -/* Access window size 128K */
> -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
> -/* The flash address and size of the VSC7385 firmware image */
> -#define CONFIG_VSC7385_IMAGE 0xFE7FE000
> -#define CONFIG_VSC7385_IMAGE_SIZE 8192
> -#endif
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
> -
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* Pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
> -
> -/*
> - * SPI on header J8
> - *
> - * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
> - * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
> - */
> -#ifdef CONFIG_MPC8XXX_SPI
> -#define CONFIG_CMD_SPI
> -#define CONFIG_USE_SPIFLASH
> -#define CONFIG_SPI_FLASH
> -#define CONFIG_SPI_FLASH_SPANSION
> -#define CONFIG_CMD_SF
> -#endif
> -
> -/*
> - * Board info - revision and where boot from
> - */
> -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
> -
> -/*
> - * Config on-board RTC
> - */
> -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCIE1_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
> -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
> -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
> -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
> -
> -/* enable PCIE clock */
> -#define CONFIG_SYS_SCCR_PCIEXP1CM 1
> -
> -#define CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_PCIE
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
> -
> -/*
> - * TSEC
> - */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/*
> - * TSEC ethernet configuration
> - */
> -#define CONFIG_MII 1 /* MII PHY management */
> -#define CONFIG_TSEC1_NAME "eTSEC0"
> -#define CONFIG_TSEC2_NAME "eTSEC1"
> -#define TSEC1_PHY_ADDR 2
> -#define TSEC2_PHY_ADDR 1
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: eTSEC[0-1] */
> -#define CONFIG_ETHPRIME "eTSEC0"
> -
> -/*
> - * Environment
> - */
> -#define CONFIG_ENV_IS_IN_FLASH 1
> -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
> - CONFIG_SYS_MONITOR_LEN)
> -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
> -#define CONFIG_ENV_SIZE 0x2000
> -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_MII
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_PCI
> -#define CONFIG_CMD_PING
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -
> -/* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> -/* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
> -
> -/*
> - * Core HID Setup
> - */
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE | \
> - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -/*
> - * MMU Setup
> - */
> -
> -/* DDR: cache cacheable */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
> - BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
> - BATU_VS | BATU_VP)
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -
> -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
> - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
> - BATU_VP)
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -
> -/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
> - BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
> - BATU_VS | BATU_VP)
> -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
> - BATL_CACHEINHIBIT | \
> - BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -
> -/* Stack in dcache: cacheable, no memory coherence */
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
> - BATU_VS | BATU_VP)
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "consoledev=ttyS0\0" \
> - "nfsargs=setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=${serverip}:${rootpath}\0" \
> - "ramargs=setenv bootargs root=/dev/ram rw\0" \
> - "addip=setenv bootargs ${bootargs} " \
> - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> - ":${hostname}:${netdev}:off panic=1\0" \
> - "addtty=setenv bootargs ${bootargs}" \
> - " console=${consoledev},${baudrate}\0" \
> - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
> - "addmisc=setenv bootargs ${bootargs}\0" \
> - "kernel_addr=FE080000\0" \
> - "fdt_addr=FE280000\0" \
> - "ramdisk_addr=FE290000\0" \
> - "u-boot=mpc8308rdb/u-boot.bin\0" \
> - "kernel_addr_r=1000000\0" \
> - "fdt_addr_r=C00000\0" \
> - "hostname=mpc8308rdb\0" \
> - "bootfile=mpc8308rdb/uImage\0" \
> - "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
> - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
> - "flash_self=run ramargs addip addtty addmtd addmisc;" \
> - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
> - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
> - "bootm ${kernel_addr} - ${fdt_addr}\0" \
> - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
> - "tftp ${fdt_addr_r} ${fdtfile};" \
> - "run nfsargs addip addtty addmtd addmisc;" \
> - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> - "bootcmd=run flash_self\0" \
> - "load=tftp ${loadaddr} ${u-boot}\0" \
> - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
> - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
> - " +${filesize};cp.b ${fileaddr} " \
> - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
> - "upd=run load update\0" \
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
> deleted file mode 100644
> index dd81229..0000000
> --- a/include/configs/MPC8313ERDB.h
> +++ /dev/null
> @@ -1,719 +0,0 @@
> -/*
> - * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -/*
> - * mpc8313epb board configuration file
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1
> -#define CONFIG_MPC831x 1
> -#define CONFIG_MPC8313 1
> -#define CONFIG_MPC8313ERDB 1
> -
> -#ifdef CONFIG_NAND
> -#define CONFIG_SPL_INIT_MINIMAL
> -#define CONFIG_SPL_SERIAL_SUPPORT
> -#define CONFIG_SPL_NAND_SUPPORT
> -#define CONFIG_SPL_FLUSH_IMAGE
> -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
> -#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
> -
> -#ifdef CONFIG_SPL_BUILD
> -#define CONFIG_NS16550_MIN_FUNCTIONS
> -#endif
> -
> -#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
> -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
> -#define CONFIG_SPL_MAX_SIZE (4 * 1024)
> -#define CONFIG_SPL_PAD_TO 0x4000
> -
> -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
> -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
> -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
> -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
> -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
> -
> -#ifdef CONFIG_SPL_BUILD
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
> -#endif
> -
> -#endif /* CONFIG_NAND */
> -
> -#ifndef CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -#endif
> -
> -#ifndef CONFIG_SYS_MONITOR_BASE
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -#endif
> -
> -#define CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_FSL_ELBC 1
> -
> -#define CONFIG_MISC_INIT_R
> -
> -/*
> - * On-board devices
> - *
> - * TSEC1 is VSC switch
> - * TSEC2 is SoC TSEC
> - */
> -#define CONFIG_VSC7385_ENET
> -#define CONFIG_TSEC2
> -
> -#ifdef CONFIG_SYS_66MHZ
> -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
> -#elif defined(CONFIG_SYS_33MHZ)
> -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
> -#else
> -#error Unknown oscillator frequency.
> -#endif
> -
> -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
> -
> -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
> -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */
> -
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
> -#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
> -#endif
> -
> -#define CONFIG_SYS_MEMTEST_START 0x00001000
> -#define CONFIG_SYS_MEMTEST_END 0x07f00000
> -
> -/* Early revs of this board will lock up hard when attempting
> - * to access the PMC registers, unless a JTAG debugger is
> - * connected, or some resistor modifications are made.
> - */
> -#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
> -
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
> -
> -/*
> - * Device configurations
> - */
> -
> -/* Vitesse 7385 */
> -
> -#ifdef CONFIG_VSC7385_ENET
> -
> -#define CONFIG_TSEC1
> -
> -/* The flash address and size of the VSC7385 firmware image */
> -#define CONFIG_VSC7385_IMAGE 0xFE7FE000
> -#define CONFIG_VSC7385_IMAGE_SIZE 8192
> -
> -#endif
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -
> -/*
> - * Manually set up DDR parameters, as this board does not
> - * seem to have the SPD connected to I2C.
> - */
> -#define CONFIG_SYS_DDR_SIZE 128 /* MB */
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ODT_RD_NEVER \
> - | CSCONFIG_ODT_WR_ONLY_CURRENT \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> - /* 0x80010102 */
> -
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00220802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (10 << TIMING_CFG1_REFREC_SHIFT) \
> - | (3 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x3835a322 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (5 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x129048c6 */ /* P9-45,may need tuning */
> -#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x05100500 */
> -#if defined(CONFIG_DDR_2T_TIMING)
> -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_DBW_32 \
> - | SDRAM_CFG_2T_EN)
> - /* 0x43088000 */
> -#else
> -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_DBW_32)
> - /* 0x43080000 */
> -#endif
> -#define CONFIG_SYS_SDRAM_CFG2 0x00401000
> -/* set burst length to 8 for 32-bit data path */
> -#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x0632 << SDRAM_MODE_SD_SHIFT))
> - /* 0x44480632 */
> -#define CONFIG_SYS_DDR_MODE_2 0x8000C000
> -
> -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> - /*0x02000000*/
> -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
> - | DDRCDR_PZ_NOMZ \
> - | DDRCDR_NZ_NOMZ \
> - | DDRCDR_M_ODR)
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
> -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
> -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
> -
> -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_9 \
> - | OR_GPCM_EHTR \
> - | OR_GPCM_EAD)
> - /* 0xFF006FF7 TODO SLOW 16 MB flash size */
> - /* window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> - /* 16 MB window size */
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
> -
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
> - !defined(CONFIG_SPL_BUILD)
> -#define CONFIG_SYS_RAMBOOT
> -#endif
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Local Bus LCRR and LBCR regs
> - */
> -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
> -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
> - | (0xFF << LBCR_BMT_SHIFT) \
> - | 0xF) /* 0x0004ff0f */
> -
> - /* LB refresh timer prescal, 266MHz/32 */
> -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
> -
> -/* drivers/mtd/nand/nand.c */
> -#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
> -#define CONFIG_SYS_NAND_BASE 0xFFF00000
> -#else
> -#define CONFIG_SYS_NAND_BASE 0xE2800000
> -#endif
> -
> -#define CONFIG_MTD_DEVICE
> -#define CONFIG_MTD_PARTITION
> -#define CONFIG_CMD_MTDPARTS
> -#define MTDIDS_DEFAULT "nand0=e2800000.flash"
> -#define MTDPARTS_DEFAULT \
> - "mtdparts=e2800000.flash:512k(uboot),128k(env),3m at 1m(kernel),-(fs)"
> -
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_MTD_NAND_VERIFY_WRITE
> -#define CONFIG_CMD_NAND 1
> -#define CONFIG_NAND_FSL_ELBC 1
> -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
> -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
> -
> -
> -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
> - | BR_DECC_CHK_GEN /* Use HW ECC */ \
> - | BR_PS_8 /* 8 bit port */ \
> - | BR_MS_FCM /* MSEL = FCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_NAND_OR_PRELIM \
> - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
> - | OR_FCM_CSCT \
> - | OR_FCM_CST \
> - | OR_FCM_CHT \
> - | OR_FCM_SCY_1 \
> - | OR_FCM_TRLX \
> - | OR_FCM_EHTR)
> - /* 0xFFFF8396 */
> -
> -#ifdef CONFIG_NAND
> -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
> -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
> -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
> -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
> -#else
> -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
> -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
> -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
> -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
> -#endif
> -
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
> -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
> -
> -/* local bus write LED / read status buffer (BCSR) mapping */
> -#define CONFIG_SYS_BCSR_ADDR 0xFA000000
> -#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
> - /* map at 0xFA000000 on LCS3 */
> -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
> - | BR_PS_8 /* 8 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> - /* 0xFA000801 */
> -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFFFF8FF7 */
> -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
> -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -/* Vitesse 7385 */
> -
> -#ifdef CONFIG_VSC7385_ENET
> -
> - /* VSC7385 Base address on LCS2 */
> -#define CONFIG_SYS_VSC7385_BASE 0xF0000000
> -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
> -
> -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
> - | BR_PS_8 /* 8 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_SETA \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFFFE09FF */
> -
> - /* Access window base at VSC7385 base */
> -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
> -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
> -
> -#endif
> -
> -/* pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -#define CONFIG_MPC83XX_GPIO 1
> -#define CONFIG_CMD_GPIO 1
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
> -
> -/*
> - * TSEC
> - */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -
> -#define CONFIG_GMII /* MII PHY management */
> -
> -#ifdef CONFIG_TSEC1
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define TSEC1_PHY_ADDR 0x1c
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC1_PHYIDX 0
> -#endif
> -
> -#ifdef CONFIG_TSEC2
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define TSEC2_PHY_ADDR 4
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -#define TSEC2_PHYIDX 0
> -#endif
> -
> -
> -/* Options are: TSEC[0-1] */
> -#define CONFIG_ETHPRIME "TSEC1"
> -
> -/*
> - * Configure on-board RTC
> - */
> -#define CONFIG_RTC_DS1337
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> -
> -/*
> - * Environment
> - */
> -#if defined(CONFIG_NAND)
> - #define CONFIG_ENV_IS_IN_NAND 1
> - #define CONFIG_ENV_OFFSET (512 * 1024)
> - #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
> - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> - #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
> - #define CONFIG_ENV_OFFSET_REDUND \
> - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
> -#elif !defined(CONFIG_SYS_RAMBOOT)
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
> - #define CONFIG_ENV_SIZE 0x2000
> -
> -/* Address and size of Redundant Environment Sector */
> -#else
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_MII
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_PCI
> -
> -#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -#define CONFIG_CMDLINE_EDITING 1
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE \
> - (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux*/
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
> -
> -#ifdef CONFIG_SYS_66MHZ
> -
> -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
> -/* 0x62040000 */
> -#define CONFIG_SYS_HRCW_LOW (\
> - 0x20000000 /* reserved, must be set */ |\
> - HRCWL_DDRCM |\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_CSB_TO_CLKIN_2X1 |\
> - HRCWL_CORE_TO_CSB_2X1)
> -
> -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
> -
> -#elif defined(CONFIG_SYS_33MHZ)
> -
> -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
> -/* 0x65040000 */
> -#define CONFIG_SYS_HRCW_LOW (\
> - 0x20000000 /* reserved, must be set */ |\
> - HRCWL_DDRCM |\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_CSB_TO_CLKIN_5X1 |\
> - HRCWL_CORE_TO_CSB_2X1)
> -
> -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
> -
> -#endif
> -
> -#define CONFIG_SYS_HRCW_HIGH_BASE (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_TSEC1M_IN_RGMII |\
> - HRCWH_TSEC2M_IN_RGMII |\
> - HRCWH_BIG_ENDIAN)
> -
> -#ifdef CONFIG_NAND
> -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
> - HRCWH_FROM_0XFFF00100 |\
> - HRCWH_ROM_LOC_NAND_SP_8BIT |\
> - HRCWH_RL_EXT_NAND)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_RL_EXT_LEGACY)
> -#endif
> -
> -/* System IO Config */
> -#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
> - /* Enable Internal USB Phy and GPIO on LCD Connector */
> -#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
> -
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE | \
> - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
> -
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR @ 0x00000000 */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* PCI @ 0x80000000 */
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* PCI2 not supported on 8313 */
> -#define CONFIG_SYS_IBAT3L (0)
> -#define CONFIG_SYS_IBAT3U (0)
> -#define CONFIG_SYS_IBAT4L (0)
> -#define CONFIG_SYS_IBAT4U (0)
> -
> -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
> -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
> -
> -#define CONFIG_SYS_IBAT7L (0)
> -#define CONFIG_SYS_IBAT7U (0)
> -
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -
> -/*
> - * Environment Configuration
> - */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_NETDEV "eth1"
> -
> -#define CONFIG_HOSTNAME mpc8313erdb
> -#define CONFIG_ROOTPATH "/nfs/root/path"
> -#define CONFIG_BOOTFILE "uImage"
> - /* U-Boot image on TFTP server */
> -#define CONFIG_UBOOTPATH "u-boot.bin"
> -#define CONFIG_FDTFILE "mpc8313erdb.dtb"
> -
> - /* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 800000
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=" CONFIG_NETDEV "\0" \
> - "ethprime=TSEC1\0" \
> - "uboot=" CONFIG_UBOOTPATH "\0" \
> - "tftpflash=tftpboot $loadaddr $uboot; " \
> - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize; " \
> - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=" CONFIG_FDTFILE "\0" \
> - "console=ttyS0\0" \
> - "setbootargs=setenv bootargs " \
> - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
> - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
> - "$netdev:off " \
> - "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv rootdev /dev/nfs;" \
> - "run setbootargs;" \
> - "run setipargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv rootdev /dev/ram;" \
> - "run setbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
> deleted file mode 100644
> index 98e9072..0000000
> --- a/include/configs/MPC8315ERDB.h
> +++ /dev/null
> @@ -1,659 +0,0 @@
> -/*
> - * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
> - *
> - * Dave Liu <daveliu@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
> -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
> -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
> -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
> -
> -#ifndef CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -#endif
> -
> -#ifndef CONFIG_SYS_MONITOR_BASE
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -#endif
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 family */
> -#define CONFIG_MPC831x 1 /* MPC831x CPU family */
> -#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
> -#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
> -
> -/*
> - * System Clock Setup
> - */
> -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
> -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
> -
> -/*
> - * Hardware Reset Configuration Word
> - * if CLKIN is 66.66MHz, then
> - * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
> - */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_SVCOD_DIV_2 |\
> - HRCWL_CSB_TO_CLKIN_2X1 |\
> - HRCWL_CORE_TO_CSB_3X1)
> -#define CONFIG_SYS_HRCW_HIGH_BASE (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_TSEC1M_IN_RGMII |\
> - HRCWH_TSEC2M_IN_RGMII |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LALE_NORMAL)
> -
> -#ifdef CONFIG_NAND_SPL
> -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
> - HRCWH_FROM_0XFFF00100 |\
> - HRCWH_ROM_LOC_NAND_SP_8BIT |\
> - HRCWH_RL_EXT_NAND)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_RL_EXT_LEGACY)
> -#endif
> -
> -/*
> - * System IO Config
> - */
> -#define CONFIG_SYS_SICRH 0x00000000
> -#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
> -
> -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
> -#define CONFIG_HWCONFIG
> -
> -/*
> - * IMMR new address
> - */
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -/*
> - * Arbiter Setup
> - */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
> -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
> - | DDRCDR_PZ_LOZ \
> - | DDRCDR_NZ_LOZ \
> - | DDRCDR_ODT \
> - | DDRCDR_Q_DRN)
> - /* 0x7b880001 */
> -/*
> - * Manually set up DDR parameters
> - * consist of two chips HY5PS12621BFP-C4 from HYNIX
> - */
> -#define CONFIG_SYS_DDR_SIZE 128 /* MB */
> -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ODT_RD_NEVER \
> - | CSCONFIG_ODT_WR_ONLY_CURRENT \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> - /* 0x80010102 */
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00220802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (6 << TIMING_CFG1_REFREC_SHIFT) \
> - | (2 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x27256222 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (4 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x121048c5 */
> -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x03600100 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_DBW_32)
> - /* 0x43080000 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
> -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x0232 << SDRAM_MODE_SD_SHIFT))
> - /* ODT 150ohm CL=3, AL=1 on SDRAM */
> -#define CONFIG_SYS_DDR_MODE2 0x00000000
> -
> -/*
> - * Memory test
> - */
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x00140000
> -
> -/*
> - * The reserved memory
> - */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Initial RAM Base Address Setup
> - */
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * Local Bus Configuration & Clock Setup
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
> -#define CONFIG_SYS_LBC_LBCR 0x00040000
> -#define CONFIG_FSL_ELBC 1
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> -
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> - /* Window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
> -
> -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_UPM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -/* 127 64KB sectors and 8 8KB top sectors per device */
> -#define CONFIG_SYS_MAX_FLASH_SECT 135
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -/*
> - * NAND Flash on the Local Bus
> - */
> -
> -#ifdef CONFIG_NAND_SPL
> -#define CONFIG_SYS_NAND_BASE 0xFFF00000
> -#else
> -#define CONFIG_SYS_NAND_BASE 0xE0600000
> -#endif
> -
> -#define CONFIG_MTD_DEVICE
> -#define CONFIG_MTD_PARTITION
> -#define CONFIG_CMD_MTDPARTS
> -#define MTDIDS_DEFAULT "nand0=e0600000.flash"
> -#define MTDPARTS_DEFAULT \
> - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m at 1m(kernel),-(fs)"
> -
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_MTD_NAND_VERIFY_WRITE 1
> -#define CONFIG_CMD_NAND 1
> -#define CONFIG_NAND_FSL_ELBC 1
> -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
> -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
> -
> -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
> -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
> -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
> -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
> -
> -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
> - | BR_DECC_CHK_GEN /* Use HW ECC */ \
> - | BR_PS_8 /* 8 bit port */ \
> - | BR_MS_FCM /* MSEL = FCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_NAND_OR_PRELIM \
> - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
> - | OR_FCM_CSCT \
> - | OR_FCM_CST \
> - | OR_FCM_CHT \
> - | OR_FCM_SCY_1 \
> - | OR_FCM_TRLX \
> - | OR_FCM_EHTR)
> - /* 0xFFFF8396 */
> -
> -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
> -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
> -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
> -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
> -
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
> -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
> -
> -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
> - !defined(CONFIG_NAND_SPL)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* Pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
> -
> -/*
> - * Board info - revision and where boot from
> - */
> -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
> -
> -/*
> - * Config on-board RTC
> - */
> -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
> -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
> -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
> -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
> -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
> -
> -#define CONFIG_SYS_PCIE1_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
> -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
> -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
> -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
> -
> -#define CONFIG_SYS_PCIE2_BASE 0xC0000000
> -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
> -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
> -#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
> -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
> -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
> -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
> -
> -#define CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_PCIE
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#define CONFIG_EEPRO100
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -
> -#define CONFIG_HAS_FSL_DR_USB
> -#define CONFIG_SYS_SCCR_USBDRCM 3
> -
> -#define CONFIG_CMD_USB
> -#define CONFIG_USB_STORAGE
> -#define CONFIG_USB_EHCI
> -#define CONFIG_USB_EHCI_FSL
> -#define CONFIG_USB_PHY_TYPE "utmi"
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -
> -/*
> - * TSEC
> - */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/*
> - * TSEC ethernet configuration
> - */
> -#define CONFIG_MII 1 /* MII PHY management */
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "eTSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "eTSEC1"
> -#define TSEC1_PHY_ADDR 0
> -#define TSEC2_PHY_ADDR 1
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: eTSEC[0-1] */
> -#define CONFIG_ETHPRIME "eTSEC1"
> -
> -/*
> - * SATA
> - */
> -#define CONFIG_LIBATA
> -#define CONFIG_FSL_SATA
> -
> -#define CONFIG_SYS_SATA_MAX_DEVICE 2
> -#define CONFIG_SATA1
> -#define CONFIG_SYS_SATA1_OFFSET 0x18000
> -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
> -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
> -#define CONFIG_SATA2
> -#define CONFIG_SYS_SATA2_OFFSET 0x19000
> -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
> -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
> -
> -#ifdef CONFIG_FSL_SATA
> -#define CONFIG_LBA48
> -#define CONFIG_CMD_SATA
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_CMD_EXT2
> -#endif
> -
> -/*
> - * Environment
> - */
> -#if !defined(CONFIG_SYS_RAMBOOT)
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
> - #define CONFIG_ENV_SIZE 0x2000
> -#else
> - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_MII
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_PCI
> -
> -#if defined(CONFIG_SYS_RAMBOOT)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#if defined(CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
> -
> -/*
> - * Core HID Setup
> - */
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE | \
> - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -/*
> - * MMU Setup
> - */
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR: cache cacheable */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_128M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -
> -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
> - | BATU_BL_8M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -
> -/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
> - | BATU_BL_32M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -
> -/* Stack in dcache: cacheable, no memory coherence */
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -
> -/* PCI MEM space: cacheable */
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -
> -/* PCI MMIO space: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -
> -#define CONFIG_SYS_IBAT6L 0
> -#define CONFIG_SYS_IBAT6U 0
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -
> -#define CONFIG_SYS_IBAT7L 0
> -#define CONFIG_SYS_IBAT7U 0
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=1000000\0" \
> - "ramdiskfile=ramfs.83xx\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=mpc8315erdb.dtb\0" \
> - "usb_phy_type=utmi\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
> deleted file mode 100644
> index 65a63e2..0000000
> --- a/include/configs/MPC8323ERDB.h
> +++ /dev/null
> @@ -1,555 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License version 2 as published
> - * by the Free Software Foundation.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 family */
> -#define CONFIG_QE 1 /* Has QE */
> -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -
> -#define CONFIG_PCI 1
> -
> -/*
> - * System Clock Setup
> - */
> -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
> -
> -#ifndef CONFIG_SYS_CLK_FREQ
> -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
> -#endif
> -
> -/*
> - * Hardware Reset Configuration Word
> - */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_VCO_1X2 |\
> - HRCWL_CSB_TO_CLKIN_2X1 |\
> - HRCWL_CORE_TO_CSB_2_5X1 |\
> - HRCWL_CE_PLL_VCO_DIV_2 |\
> - HRCWL_CE_PLL_DIV_1X1 |\
> - HRCWL_CE_TO_PLL_1X3)
> -
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LALE_NORMAL)
> -
> -/*
> - * System IO Config
> - */
> -#define CONFIG_SYS_SICRL 0x00000000
> -
> -/*
> - * IMMR new address
> - */
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -/*
> - * System performance
> - */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
> -/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
> -#define CONFIG_SYS_SPCR_OPT 1
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -
> -#undef CONFIG_SPD_EEPROM
> -#if defined(CONFIG_SPD_EEPROM)
> -/* Determine DDR configuration from I2C interface
> - */
> -#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
> -#else
> -/* Manually set up DDR parameters
> - */
> -#define CONFIG_SYS_DDR_SIZE 64 /* MB */
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_9)
> - /* 0x80010101 */
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00220802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (3 << TIMING_CFG1_REFREC_SHIFT) \
> - | (2 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x26253222 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (31 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x1f9048c7 */
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> - /* 0x02000000 */
> -#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x0232 << SDRAM_MODE_SD_SHIFT))
> - /* 0x44480232 */
> -#define CONFIG_SYS_DDR_MODE2 0x8000c000
> -#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x03200064 */
> -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
> -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_32_BE)
> - /* 0x43080000 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
> -#endif
> -
> -/*
> - * Memory test
> - */
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x03f00000
> -
> -/*
> - * The reserved memory
> - */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Initial RAM Base Address Setup
> - */
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * Local Bus Configuration & Clock Setup
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
> -#define CONFIG_SYS_LBC_LBCR 0x00000000
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> - /* Window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFE006FF7 */
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
> -
> -/*
> - * Config on-board EEPROM
> - */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
> -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_PCI_SKIP_HOST_BRIDGE
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#undef CONFIG_EEPRO100
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * QE UEC ethernet configuration
> - */
> -#define CONFIG_UEC_ETH
> -#define CONFIG_ETHPRIME "UEC0"
> -
> -#define CONFIG_UEC_ETH1 /* ETH3 */
> -
> -#ifdef CONFIG_UEC_ETH1
> -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
> -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
> -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
> -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
> -#define CONFIG_SYS_UEC1_PHY_ADDR 4
> -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
> -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
> -#endif
> -
> -#define CONFIG_UEC_ETH2 /* ETH4 */
> -
> -#ifdef CONFIG_UEC_ETH2
> -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
> -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
> -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
> -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
> -#define CONFIG_SYS_UEC2_PHY_ADDR 0
> -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
> -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
> -#endif
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x20000
> - #define CONFIG_ENV_SIZE 0x2000
> -#else
> - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_EEPROM
> -#define CONFIG_CMD_ASKENV
> -
> -#if defined(CONFIG_PCI)
> - #define CONFIG_CMD_PCI
> -#endif
> -#if defined(CONFIG_SYS_RAMBOOT)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#if (CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux */
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -/*
> - * Core HID Setup
> - */
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE)
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -/*
> - * MMU Setup
> - */
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR: cache cacheable */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -
> -/* IMMRBAR & PCI IO: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
> - | BATU_BL_4M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -
> -/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
> - | BATU_BL_32M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -
> -#define CONFIG_SYS_IBAT3L (0)
> -#define CONFIG_SYS_IBAT3U (0)
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -
> -/* Stack in dcache: cacheable, no memory coherence */
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -
> -#ifdef CONFIG_PCI
> -/* PCI MEM space: cacheable */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -/* PCI MMIO space: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#else
> -#define CONFIG_SYS_IBAT5L (0)
> -#define CONFIG_SYS_IBAT5U (0)
> -#define CONFIG_SYS_IBAT6L (0)
> -#define CONFIG_SYS_IBAT6U (0)
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#endif
> -
> -/* Nothing in BAT7 */
> -#define CONFIG_SYS_IBAT7L (0)
> -#define CONFIG_SYS_IBAT7U (0)
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -
> -#if (CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
> -#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
> -
> -/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
> - * (see CONFIG_SYS_I2C_EEPROM) */
> - /* MAC address offset in I2C EEPROM */
> -#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
> -
> -#define CONFIG_NETDEV "eth1"
> -
> -#define CONFIG_HOSTNAME mpc8323erdb
> -#define CONFIG_ROOTPATH "/nfsroot"
> -#define CONFIG_BOOTFILE "uImage"
> - /* U-Boot image on TFTP server */
> -#define CONFIG_UBOOTPATH "u-boot.bin"
> -#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
> -#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
> -
> - /* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 800000
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=" CONFIG_NETDEV "\0" \
> - "uboot=" CONFIG_UBOOTPATH "\0" \
> - "tftpflash=tftp $loadaddr $uboot;" \
> - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize; " \
> - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=" CONFIG_FDTFILE "\0" \
> - "ramdiskaddr=1000000\0" \
> - "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
> - "console=ttyS0\0" \
> - "setbootargs=setenv bootargs " \
> - "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
> - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
> - "$netdev:off "\
> - "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv rootdev /dev/nfs;" \
> - "run setbootargs;" \
> - "run setipargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv rootdev /dev/ram;" \
> - "run setbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
> deleted file mode 100644
> index 1735b3c..0000000
> --- a/include/configs/MPC832XEMDS.h
> +++ /dev/null
> @@ -1,624 +0,0 @@
> -/*
> - * Copyright (C) 2006 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 family */
> -#define CONFIG_QE 1 /* Has QE */
> -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
> -#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -
> -/*
> - * System Clock Setup
> - */
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
> -#else
> -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
> -#endif
> -
> -#ifndef CONFIG_SYS_CLK_FREQ
> -#define CONFIG_SYS_CLK_FREQ 66000000
> -#endif
> -
> -/*
> - * Hardware Reset Configuration Word
> - */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_2X1 |\
> - HRCWL_VCO_1X2 |\
> - HRCWL_CSB_TO_CLKIN_2X1 |\
> - HRCWL_CORE_TO_CSB_2X1 |\
> - HRCWL_CE_PLL_VCO_DIV_2 |\
> - HRCWL_CE_PLL_DIV_1X1 |\
> - HRCWL_CE_TO_PLL_1X3)
> -
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_AGENT |\
> - HRCWH_PCI1_ARBITER_DISABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0XFFF00100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LALE_NORMAL)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LALE_NORMAL)
> -#endif
> -
> -/*
> - * System IO Config
> - */
> -#define CONFIG_SYS_SICRL 0x00000000
> -
> -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
> -#define CONFIG_BOARD_EARLY_INIT_R
> -
> -/*
> - * IMMR new address
> - */
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
> -
> -#undef CONFIG_SPD_EEPROM
> -#if defined(CONFIG_SPD_EEPROM)
> -/* Determine DDR configuration from I2C interface
> - */
> -#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
> -#else
> -/* Manually set up DDR parameters
> - */
> -#define CONFIG_SYS_DDR_SIZE 128 /* MB */
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_AP \
> - | CSCONFIG_ODT_WR_CFG \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> - /* 0x80840102 */
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00220802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (13 << TIMING_CFG1_REFREC_SHIFT) \
> - | (3 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x3935D322 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (31 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x0F9048CA */
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> - /* 0x02000000 */
> -#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x0232 << SDRAM_MODE_SD_SHIFT))
> - /* 0x44400232 */
> -#define CONFIG_SYS_DDR_MODE2 0x8000c000
> -#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x03200064 */
> -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
> -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
> - | SDRAM_CFG_SDRAM_TYPE_DDR2 \
> - | SDRAM_CFG_32_BE)
> - /* 0x43080000 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
> -#endif
> -
> -/*
> - * Memory test
> - */
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x00100000
> -
> -/*
> - * The reserved memory
> - */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Initial RAM Base Address Setup
> - */
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * Local Bus Configuration & Clock Setup
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
> -#define CONFIG_SYS_LBC_LBCR 0x00000000
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> - /* Window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xfe006ff7 */
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -
> -/*
> - * BCSR on the Local Bus
> - */
> -#define CONFIG_SYS_BCSR 0xF8000000
> - /* Access window base at BCSR base */
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFFFFE9F7 */
> -
> -/*
> - * Windows to access PIB via local bus
> - */
> - /* PIB window base 0xF8008000 */
> -#define CONFIG_SYS_PIB_BASE 0xF8008000
> -#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
> -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
> -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
> -
> -/*
> - * CS2 on Local Bus, to PIB
> - */
> -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> - /* 0xF8008801 */
> -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xffffe9f7 */
> -
> -/*
> - * CS3 on Local Bus, to PIB
> - */
> -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
> - CONFIG_SYS_PIB_WINDOW_SIZE) \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> - /* 0xF8010801 */
> -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xffffe9f7 */
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
> -
> -/*
> - * Config on-board RTC
> - */
> -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
> -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
> -
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -#define CONFIG_83XX_PCI_STREAMING
> -
> -#undef CONFIG_EEPRO100
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * QE UEC ethernet configuration
> - */
> -#define CONFIG_UEC_ETH
> -#define CONFIG_ETHPRIME "UEC0"
> -
> -#define CONFIG_UEC_ETH1 /* ETH3 */
> -
> -#ifdef CONFIG_UEC_ETH1
> -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
> -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
> -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
> -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
> -#define CONFIG_SYS_UEC1_PHY_ADDR 3
> -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
> -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
> -#endif
> -
> -#define CONFIG_UEC_ETH2 /* ETH4 */
> -
> -#ifdef CONFIG_UEC_ETH2
> -#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
> -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
> -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
> -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
> -#define CONFIG_SYS_UEC2_PHY_ADDR 4
> -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
> -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
> -#endif
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x20000
> - #define CONFIG_ENV_SIZE 0x2000
> -#else
> - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_ASKENV
> -
> -#if defined(CONFIG_PCI)
> - #define CONFIG_CMD_PCI
> -#endif
> -
> -#if defined(CONFIG_SYS_RAMBOOT)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#if defined(CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux */
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -/*
> - * Core HID Setup
> - */
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE)
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -/*
> - * MMU Setup
> - */
> -
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR: cache cacheable */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -
> -/* IMMRBAR & PCI IO: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
> - | BATU_BL_4M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -
> -/* BCSR: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -
> -/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
> - | BATU_BL_32M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -
> -#define CONFIG_SYS_IBAT4L (0)
> -#define CONFIG_SYS_IBAT4U (0)
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -
> -/* Stack in dcache: cacheable, no memory coherence */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -
> -#ifdef CONFIG_PCI
> -/* PCI MEM space: cacheable */
> -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -/* PCI MMIO space: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -#else
> -#define CONFIG_SYS_IBAT6L (0)
> -#define CONFIG_SYS_IBAT6U (0)
> -#define CONFIG_SYS_IBAT7L (0)
> -#define CONFIG_SYS_IBAT7U (0)
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */ #define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_UEC_ETH)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=1000000\0" \
> - "ramdiskfile=ramfs.83xx\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=mpc832x_mds.dtb\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
> deleted file mode 100644
> index 6b7d648..0000000
> --- a/include/configs/MPC8349EMDS.h
> +++ /dev/null
> @@ -1,810 +0,0 @@
> -/*
> - * (C) Copyright 2006-2010
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -/*
> - * mpc8349emds board configuration file
> - *
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 Family */
> -#define CONFIG_MPC834x 1 /* MPC834x family */
> -#define CONFIG_MPC8349 1 /* MPC8349 specific */
> -#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -
> -#define CONFIG_PCI_66M
> -#ifdef CONFIG_PCI_66M
> -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
> -#else
> -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
> -#endif
> -
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_PCI
> -#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
> -#endif /* CONFIG_PCISLAVE */
> -
> -#ifndef CONFIG_SYS_CLK_FREQ
> -#ifdef CONFIG_PCI_66M
> -#define CONFIG_SYS_CLK_FREQ 66000000
> -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
> -#else
> -#define CONFIG_SYS_CLK_FREQ 33000000
> -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
> -#endif
> -#endif
> -
> -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
> -
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x00100000
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_DDR_ECC /* support DDR ECC function */
> -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
> -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
> -
> -/*
> - * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
> - * undefine it to use old spd_sdram.c
> - */
> -#define CONFIG_SYS_FSL_DDR2
> -#ifdef CONFIG_SYS_FSL_DDR2
> -#define CONFIG_SYS_FSL_DDRC_GEN2
> -#define CONFIG_SYS_SPD_BUS_NUM 0
> -#define SPD_EEPROM_ADDRESS1 0x52
> -#define SPD_EEPROM_ADDRESS2 0x51
> -#define CONFIG_NUM_DDR_CONTROLLERS 1
> -#define CONFIG_DIMM_SLOTS_PER_CTLR 2
> -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
> -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
> -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
> -#endif
> -
> -/*
> - * 32-bit data path mode.
> - *
> - * Please note that using this mode for devices with the real density of 64-bit
> - * effectively reduces the amount of available memory due to the effect of
> - * wrapping around while translating address to row/columns, for example in the
> - * 256MB module the upper 128MB get aliased with contents of the lower
> - * 128MB); normally this define should be used for devices with real 32-bit
> - * data path.
> - */
> -#undef CONFIG_DDR_32BIT
> -
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
> - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
> -#undef CONFIG_DDR_2T_TIMING
> -
> -/*
> - * DDRCDR - DDR Control Driver Register
> - */
> -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
> -
> -#if defined(CONFIG_SPD_EEPROM)
> -/*
> - * Determine DDR configuration from I2C interface.
> - */
> -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
> -#else
> -/*
> - * Manually set up DDR parameters
> - */
> -#define CONFIG_SYS_DDR_SIZE 256 /* MB */
> -#if defined(CONFIG_DDR_II)
> -#define CONFIG_SYS_DDRCDR 0x80080001
> -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
> -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
> -#define CONFIG_SYS_DDR_TIMING_0 0x00220802
> -#define CONFIG_SYS_DDR_TIMING_1 0x38357322
> -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
> -#define CONFIG_SYS_DDR_MODE 0x47d00432
> -#define CONFIG_SYS_DDR_MODE2 0x8000c000
> -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
> -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
> -#else
> -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> -#define CONFIG_SYS_DDR_TIMING_1 0x36332321
> -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
> -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
> -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
> -
> -#if defined(CONFIG_DDR_32BIT)
> -/* set burst length to 8 for 32-bit data path */
> - /* DLL,normal,seq,4/2.5, 8 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000023
> -#else
> -/* the default burst length is 4 - for 64-bit data path */
> - /* DLL,normal,seq,4/2.5, 4 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000022
> -#endif
> -#endif
> -#endif
> -
> -/*
> - * SDRAM on the Local Bus
> - */
> -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
> -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
> -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_UPM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> -
> - /* window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -/*
> - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
> - */
> -#define CONFIG_SYS_BCSR 0xE2400000
> - /* Access window base at BCSR base */
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> - /* 0x00000801 */
> -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_CLEAR \
> - | OR_GPCM_EHTR_CLEAR)
> - /* 0xFFFFE8F0 */
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Local Bus LCRR and LBCR regs
> - * LCRR: DLL bypass, Clock divider is 4
> - * External Local Bus rate is
> - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
> -#define CONFIG_SYS_LBC_LBCR 0x00000000
> -
> -/*
> - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
> - * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
> - */
> -#undef CONFIG_SYS_LB_SDRAM
> -
> -#ifdef CONFIG_SYS_LB_SDRAM
> -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
> -/*
> - * Base Register 2 and Option Register 2 configure SDRAM.
> - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
> - *
> - * For BR2, need:
> - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
> - * port-size = 32-bits = BR2[19:20] = 11
> - * no parity checking = BR2[21:22] = 00
> - * SDRAM for MSEL = BR2[24:26] = 011
> - * Valid = BR[31] = 1
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
> - */
> -
> -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
> - | BR_PS_32 /* 32-bit port */ \
> - | BR_MS_SDRAM /* MSEL = SDRAM */ \
> - | BR_V) /* Valid */
> - /* 0xF0001861 */
> -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
> -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
> -
> -/*
> - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
> - *
> - * For OR2, need:
> - * 64MB mask for AM, OR2[0:7] = 1111 1100
> - * XAM, OR2[17:18] = 11
> - * 9 columns OR2[19-21] = 010
> - * 13 rows OR2[23-25] = 100
> - * EAD set for extra time OR[31] = 1
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
> - */
> -
> -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
> - | OR_SDRAM_XAM \
> - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
> - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
> - | OR_SDRAM_EAD)
> - /* 0xFC006901 */
> -
> - /* LB sdram refresh timer, about 6us */
> -#define CONFIG_SYS_LBC_LSRT 0x32000000
> - /* LB refresh timer prescal, 266MHz/32 */
> -#define CONFIG_SYS_LBC_MRTPR 0x20000000
> -
> -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
> - | LSDMR_BSMA1516 \
> - | LSDMR_RFCR8 \
> - | LSDMR_PRETOACT6 \
> - | LSDMR_ACTTORW3 \
> - | LSDMR_BL8 \
> - | LSDMR_WRC3 \
> - | LSDMR_CL3)
> -
> -/*
> - * SDRAM Controller configuration sequence.
> - */
> -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
> -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
> -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
> -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
> -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
> -#endif
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
> -
> -/* SPI */
> -#define CONFIG_MPC8XXX_SPI
> -#undef CONFIG_SOFT_SPI /* SPI bit-banged */
> -
> -/* GPIOs. Used as SPI chip selects */
> -#define CONFIG_SYS_GPIO1_PRELIM
> -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
> -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
> -
> -/* TSEC */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/* USB */
> -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
> -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
> -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
> -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
> -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
> -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
> -
> -#if defined(CONFIG_PCI)
> -
> -#define PCI_ONE_PCI1
> -#if defined(PCI_64BIT)
> -#undef PCI_ALL_PCI1
> -#undef PCI_TWO_PCI1
> -#undef PCI_ONE_PCI1
> -#endif
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -#define CONFIG_83XX_PCI_STREAMING
> -
> -#undef CONFIG_EEPRO100
> -#undef CONFIG_TULIP
> -
> -#if !defined(CONFIG_PCI_PNP)
> - #define PCI_ENET0_IOADDR 0xFIXME
> - #define PCI_ENET0_MEMADDR 0xFIXME
> - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
> -#endif
> -
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * TSEC configuration
> - */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -
> -#define CONFIG_GMII 1 /* MII PHY management */
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> -#define TSEC1_PHY_ADDR 0
> -#define TSEC2_PHY_ADDR 1
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: TSEC[0-1] */
> -#define CONFIG_ETHPRIME "TSEC0"
> -
> -#endif /* CONFIG_TSEC_ENET */
> -
> -/*
> - * Configure on-board RTC
> - */
> -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
> - #define CONFIG_ENV_SIZE 0x2000
> -
> -/* Address and size of Redundant Environment Sector */
> -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
> -
> -#else
> - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_MII
> -
> -#if defined(CONFIG_PCI)
> - #define CONFIG_CMD_PCI
> -#endif
> -
> -#if defined(CONFIG_SYS_RAMBOOT)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#if defined(CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux*/
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
> -
> -#if 1 /*528/264*/
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN |\
> - HRCWL_VCO_1X2 |\
> - HRCWL_CORE_TO_CSB_2X1)
> -#elif 0 /*396/132*/
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN |\
> - HRCWL_VCO_1X4 |\
> - HRCWL_CORE_TO_CSB_3X1)
> -#elif 0 /*264/132*/
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN |\
> - HRCWL_VCO_1X4 |\
> - HRCWL_CORE_TO_CSB_2X1)
> -#elif 0 /*132/132*/
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN |\
> - HRCWL_VCO_1X4 |\
> - HRCWL_CORE_TO_CSB_1X1)
> -#elif 0 /*264/264 */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN |\
> - HRCWL_VCO_1X4 |\
> - HRCWL_CORE_TO_CSB_1X1)
> -#endif
> -
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_AGENT |\
> - HRCWH_64_BIT_PCI |\
> - HRCWH_PCI1_ARBITER_DISABLE |\
> - HRCWH_PCI2_ARBITER_DISABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_TSEC1M_IN_GMII |\
> - HRCWH_TSEC2M_IN_GMII)
> -#else
> -#if defined(PCI_64BIT)
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_64_BIT_PCI |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_PCI2_ARBITER_DISABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_TSEC1M_IN_GMII |\
> - HRCWH_TSEC2M_IN_GMII)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_32_BIT_PCI |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_PCI2_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_TSEC1M_IN_GMII |\
> - HRCWH_TSEC2M_IN_GMII)
> -#endif /* PCI_64BIT */
> -#endif /* CONFIG_PCISLAVE */
> -
> -/*
> - * System performance
> - */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
> -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
> -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
> -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
> -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
> -
> -/* System IO Config */
> -#define CONFIG_SYS_SICRH 0
> -#define CONFIG_SYS_SICRL SICRL_LDP_A
> -
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
> - | HID0_ENABLE_INSTRUCTION_CACHE)
> -
> -/* #define CONFIG_SYS_HID0_FINAL (\
> - HID0_ENABLE_INSTRUCTION_CACHE |\
> - HID0_ENABLE_M_BIT |\
> - HID0_ENABLE_ADDRESS_BROADCAST) */
> -
> -
> -#define CONFIG_SYS_HID2 HID2_HBE
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR @ 0x00000000 */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* PCI @ 0x80000000 */
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#else
> -#define CONFIG_SYS_IBAT1L (0)
> -#define CONFIG_SYS_IBAT1U (0)
> -#define CONFIG_SYS_IBAT2L (0)
> -#define CONFIG_SYS_IBAT2U (0)
> -#endif
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#else
> -#define CONFIG_SYS_IBAT3L (0)
> -#define CONFIG_SYS_IBAT3U (0)
> -#define CONFIG_SYS_IBAT4L (0)
> -#define CONFIG_SYS_IBAT4U (0)
> -#endif
> -
> -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
> -#define CONFIG_SYS_IBAT6L (0xF0000000 \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT6U (0xF0000000 \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -#define CONFIG_SYS_IBAT7L (0)
> -#define CONFIG_SYS_IBAT7U (0)
> -
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_HAS_ETH0
> -#endif
> -
> -#define CONFIG_HOSTNAME mpc8349emds
> -#define CONFIG_ROOTPATH "/nfsroot/rootfs"
> -#define CONFIG_BOOTFILE "uImage"
> -
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_PREBOOT "echo;" \
> - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
> - "echo"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "hostname=mpc8349emds\0" \
> - "nfsargs=setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=${serverip}:${rootpath}\0" \
> - "ramargs=setenv bootargs root=/dev/ram rw\0" \
> - "addip=setenv bootargs ${bootargs} " \
> - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> - ":${hostname}:${netdev}:off panic=1\0" \
> - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
> - "flash_nfs=run nfsargs addip addtty;" \
> - "bootm ${kernel_addr}\0" \
> - "flash_self=run ramargs addip addtty;" \
> - "bootm ${kernel_addr} ${ramdisk_addr}\0" \
> - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
> - "bootm\0" \
> - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
> - "update=protect off fe000000 fe03ffff; " \
> - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
> - "upd=run load update\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=mpc834x_mds.dtb\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND "run flash_self"
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
> deleted file mode 100644
> index 398918a..0000000
> --- a/include/configs/MPC8349ITX.h
> +++ /dev/null
> @@ -1,806 +0,0 @@
> -/*
> - * Copyright (C) Freescale Semiconductor, Inc. 2006.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -/*
> - MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
> -
> - Memory map:
> -
> - 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
> - 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
> - 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
> - 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
> - 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
> - 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
> - 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
> - 0xF001_0000-0xF001_FFFF Local bus expansion slot
> - 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
> - 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
> - 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
> -
> - I2C address list:
> - Align. Board
> - Bus Addr Part No. Description Length Location
> - ----------------------------------------------------------------
> - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
> -
> - I2C1 0x20 PCF8574 I2C Expander 0 U8
> - I2C1 0x21 PCF8574 I2C Expander 0 U10
> - I2C1 0x38 PCF8574A I2C Expander 0 U8
> - I2C1 0x39 PCF8574A I2C Expander 0 U10
> - I2C1 0x51 (DDR) DDR EEPROM 1 U1
> - I2C1 0x68 DS1339 RTC 1 U68
> -
> - Note that a given board has *either* a pair of 8574s or a pair of 8574As.
> -*/
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
> -#define CONFIG_SYS_LOWBOOT
> -#endif
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
> -#define CONFIG_MPC8349 /* MPC8349 specific */
> -
> -#ifndef CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_TEXT_BASE 0xFEF00000
> -#endif
> -
> -#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
> -
> -#define CONFIG_MISC_INIT_F
> -#define CONFIG_MISC_INIT_R
> -
> -/*
> - * On-board devices
> - */
> -
> -#ifdef CONFIG_MPC8349ITX
> -/* The CF card interface on the back of the board */
> -#define CONFIG_COMPACT_FLASH
> -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
> -#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
> -#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
> -#endif
> -
> -#define CONFIG_PCI
> -#define CONFIG_RTC_DS1337
> -#define CONFIG_SYS_I2C
> -#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
> -
> -/*
> - * Device configurations
> - */
> -
> -/* I2C */
> -#ifdef CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -
> -#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
> -#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
> -
> -#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
> -#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
> -#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
> -#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
> -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
> -
> -/* Don't probe these addresses: */
> -#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
> - {1, CONFIG_SYS_I2C_8574_ADDR2}, \
> - {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
> - {1, CONFIG_SYS_I2C_8574A_ADDR2} }
> -/* Bit definitions for the 8574[A] I2C expander */
> - /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
> -#define I2C_8574_REVISION 0x03
> -#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
> -#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
> -#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
> -#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
> -
> -#endif
> -
> -/* Compact Flash */
> -#ifdef CONFIG_COMPACT_FLASH
> -
> -#define CONFIG_SYS_IDE_MAXBUS 1
> -#define CONFIG_SYS_IDE_MAXDEVICE 1
> -
> -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
> -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
> -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
> -#define CONFIG_SYS_ATA_REG_OFFSET 0
> -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
> -#define CONFIG_SYS_ATA_STRIDE 2
> -
> -/* If a CF card is not inserted, time out quickly */
> -#define ATA_RESET_TIME 1
> -
> -#endif
> -
> -/*
> - * SATA
> - */
> -#ifdef CONFIG_SATA_SIL3114
> -
> -#define CONFIG_SYS_SATA_MAX_DEVICE 4
> -#define CONFIG_LIBATA
> -#define CONFIG_LBA48
> -
> -#endif
> -
> -#ifdef CONFIG_SYS_USB_HOST
> -/*
> - * Support USB
> - */
> -#define CONFIG_CMD_USB
> -#define CONFIG_USB_STORAGE
> -#define CONFIG_USB_EHCI
> -#define CONFIG_USB_EHCI_FSL
> -
> -/* Current USB implementation supports the only USB controller,
> - * so we have to choose between the MPH or the DR ones */
> -#if 1
> -#define CONFIG_HAS_FSL_MPH_USB
> -#else
> -#define CONFIG_HAS_FSL_DR_USB
> -#endif
> -
> -#endif
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_83XX_DDR_USES_CS0
> -#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x2000
> -
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
> - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
> -
> -#define CONFIG_VERY_BIG_RAM
> -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
> -
> -#ifdef CONFIG_SYS_I2C
> -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
> -#endif
> -
> -/* No SPD? Then manually set up DDR parameters */
> -#ifndef CONFIG_SPD_EEPROM
> - #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
> - #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> -
> - #define CONFIG_SYS_DDR_TIMING_1 0x26242321
> - #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
> -#endif
> -
> -/*
> - *Flash on the Local Bus
> - */
> -
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -/* 127 64KB sectors + 8 8KB sectors per device */
> -#define CONFIG_SYS_MAX_FLASH_SECT 135
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> -
> -/* The ITX has two flash chips, but the ITX-GP has only one. To support both
> -boards, we say we have two, but don't display a message if we find only one. */
> -#define CONFIG_SYS_FLASH_QUIET_TEST
> -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
> -#define CONFIG_SYS_FLASH_BANKS_LIST \
> - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
> -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> -/* Vitesse 7385 */
> -
> -#ifdef CONFIG_VSC7385_ENET
> -
> -#define CONFIG_TSEC2
> -
> -/* The flash address and size of the VSC7385 firmware image */
> -#define CONFIG_VSC7385_IMAGE 0xFEFFE000
> -#define CONFIG_VSC7385_IMAGE_SIZE 8192
> -
> -#endif
> -
> -/*
> - * BRx, ORx, LBLAWBARx, and LBLAWARx
> - */
> -
> -/* Flash */
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 \
> - | BR_MS_GPCM \
> - | BR_V)
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_UPM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
> -
> -/* Vitesse 7385 */
> -
> -#define CONFIG_SYS_VSC7385_BASE 0xF8000000
> -
> -#ifdef CONFIG_VSC7385_ENET
> -
> -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_SETA \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> -
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
> -
> -#endif
> -
> -/* LED */
> -
> -#define CONFIG_SYS_LED_BASE 0xF9000000
> -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_9 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> -
> -/* Compact Flash */
> -
> -#ifdef CONFIG_COMPACT_FLASH
> -
> -#define CONFIG_SYS_CF_BASE 0xF0000000
> -
> -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
> - | BR_PS_16 \
> - | BR_MS_UPMA \
> - | BR_V)
> -#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
> -
> -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
> -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
> -
> -#endif
> -
> -/*
> - * U-Boot memory configuration
> - */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Local Bus LCRR and LBCR regs
> - * LCRR: DLL bypass, Clock divider is 4
> - * External Local Bus rate is
> - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
> -#define CONFIG_SYS_LBC_LBCR 0x00000000
> -
> - /* LB sdram refresh timer, about 6us */
> -#define CONFIG_SYS_LBC_LSRT 0x32000000
> - /* LB refresh timer prescal, 266MHz/32*/
> -#define CONFIG_SYS_LBC_MRTPR 0x20000000
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_CONSOLE ttyS0
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
> -
> -/* pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/*
> - * PCI
> - */
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -
> -#define CONFIG_MPC83XX_PCI2
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE \
> - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -#define CONFIG_SYS_PCI2_MEM_BASE \
> - (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
> -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
> -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_MMIO_BASE \
> - (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
> -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
> -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI2_IO_PHYS \
> - (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
> -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
> -#endif
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#ifndef CONFIG_PCI_PNP
> - #define PCI_ENET0_IOADDR 0x00000000
> - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
> - #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
> -#endif
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -
> -#endif
> -
> -#define CONFIG_PCI_66M
> -#ifdef CONFIG_PCI_66M
> -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
> -#else
> -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
> -#endif
> -
> -/* TSEC */
> -
> -#ifdef CONFIG_TSEC_ENET
> -
> -#define CONFIG_MII
> -#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
> -
> -#define CONFIG_TSEC1
> -
> -#ifdef CONFIG_TSEC1
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
> -#define TSEC1_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#endif
> -
> -#ifdef CONFIG_TSEC2
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -
> -#define TSEC2_PHY_ADDR 4
> -#define TSEC2_PHYIDX 0
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -#endif
> -
> -#define CONFIG_ETHPRIME "Freescale TSEC"
> -
> -#endif
> -
> -/*
> - * Environment
> - */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#ifndef CONFIG_SYS_RAMBOOT
> - #define CONFIG_ENV_IS_IN_FLASH
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
> - #define CONFIG_ENV_SIZE 0x2000
> -#else
> - #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
> - #undef CONFIG_FLASH_CFI_DRIVER
> - #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_CACHE
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_IRQ
> -#define CONFIG_CMD_NET
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_SDRAM
> -
> -#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
> - || defined(CONFIG_USB_STORAGE)
> - #define CONFIG_DOS_PARTITION
> - #define CONFIG_CMD_FAT
> - #define CONFIG_SUPPORT_VFAT
> -#endif
> -
> -#ifdef CONFIG_COMPACT_FLASH
> - #define CONFIG_CMD_IDE
> -#endif
> -
> -#ifdef CONFIG_SATA_SIL3114
> - #define CONFIG_CMD_SATA
> -#endif
> -
> -#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
> - #define CONFIG_CMD_EXT2
> -#endif
> -
> -#ifdef CONFIG_PCI
> - #define CONFIG_CMD_PCI
> -#endif
> -
> -#ifdef CONFIG_SYS_I2C
> - #define CONFIG_CMD_I2C
> -#endif
> -
> -/* Watchdog */
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_CMDLINE_EDITING /* Command-line editing */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
> -
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#ifdef CONFIG_MPC8349ITX
> -#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
> -#else
> -#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux*/
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_CSB_TO_CLKIN_4X1 |\
> - HRCWL_VCO_1X2 |\
> - HRCWL_CORE_TO_CSB_2X1)
> -
> -#ifdef CONFIG_SYS_LOWBOOT
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_32_BIT_PCI |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_PCI2_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_TSEC1M_IN_GMII |\
> - HRCWH_TSEC2M_IN_GMII)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_32_BIT_PCI |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_PCI2_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0XFFF00100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_TSEC1M_IN_GMII |\
> - HRCWH_TSEC2M_IN_GMII)
> -#endif
> -
> -/*
> - * System performance
> - */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
> -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
> -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
> -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
> -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
> -#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
> -#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
> -
> -/*
> - * System IO Config
> - */
> -/* Needed for gigabit to work on TSEC 1 */
> -#define CONFIG_SYS_SICRH SICRH_TSOBI1
> - /* USB DR as device + USB MPH as host */
> -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
> -
> -#define CONFIG_SYS_HID0_INIT 0x00000000
> -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
> -
> -#define CONFIG_SYS_HID2 HID2_HBE
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR */
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* PCI */
> -#ifdef CONFIG_PCI
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#else
> -#define CONFIG_SYS_IBAT1L 0
> -#define CONFIG_SYS_IBAT1U 0
> -#define CONFIG_SYS_IBAT2L 0
> -#define CONFIG_SYS_IBAT2U 0
> -#endif
> -
> -#ifdef CONFIG_MPC83XX_PCI2
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#else
> -#define CONFIG_SYS_IBAT3L 0
> -#define CONFIG_SYS_IBAT3U 0
> -#define CONFIG_SYS_IBAT4L 0
> -#define CONFIG_SYS_IBAT4U 0
> -#endif
> -
> -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
> -#define CONFIG_SYS_IBAT6L (0xF0000000 \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT6U (0xF0000000 \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -
> -#define CONFIG_SYS_IBAT7L 0
> -#define CONFIG_SYS_IBAT7U 0
> -
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -
> -/*
> - * Environment Configuration
> - */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_NETDEV "eth0"
> -
> -#ifdef CONFIG_MPC8349ITX
> -#define CONFIG_HOSTNAME "mpc8349emitx"
> -#else
> -#define CONFIG_HOSTNAME "mpc8349emitxgp"
> -#endif
> -
> -/* Default path and filenames */
> -#define CONFIG_ROOTPATH "/nfsroot/rootfs"
> -#define CONFIG_BOOTFILE "uImage"
> - /* U-Boot image on TFTP server */
> -#define CONFIG_UBOOTPATH "u-boot.bin"
> -
> -#ifdef CONFIG_MPC8349ITX
> -#define CONFIG_FDTFILE "mpc8349emitx.dtb"
> -#else
> -#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
> -#endif
> -
> -#define CONFIG_BOOTDELAY 6
> -
> -#define CONFIG_BOOTARGS \
> - "root=/dev/nfs rw" \
> - " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
> - " ip=" __stringify(CONFIG_IPADDR) ":" \
> - __stringify(CONFIG_SERVERIP) ":" \
> - __stringify(CONFIG_GATEWAYIP) ":" \
> - __stringify(CONFIG_NETMASK) ":" \
> - CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
> - " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "console=" __stringify(CONFIG_CONSOLE) "\0" \
> - "netdev=" CONFIG_NETDEV "\0" \
> - "uboot=" CONFIG_UBOOTPATH "\0" \
> - "tftpflash=tftpboot $loadaddr $uboot; " \
> - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize; " \
> - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " +$filesize; " \
> - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
> - " $filesize\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=" CONFIG_FDTFILE "\0"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
> - " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
> - " console=$console,$baudrate $othbootargs; " \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw" \
> - " console=$console,$baudrate $othbootargs; " \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#endif
> diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
> deleted file mode 100644
> index 832c10f..0000000
> --- a/include/configs/MPC837XEMDS.h
> +++ /dev/null
> @@ -1,719 +0,0 @@
> -/*
> - * Copyright (C) 2007 Freescale Semiconductor, Inc.
> - * Dave Liu <daveliu@freescale.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 family */
> -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
> -#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFE000000
> -
> -/*
> - * System Clock Setup
> - */
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
> -#else
> -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
> -#endif
> -
> -#ifndef CONFIG_SYS_CLK_FREQ
> -#define CONFIG_SYS_CLK_FREQ 66000000
> -#endif
> -
> -/*
> - * Hardware Reset Configuration Word
> - * if CLKIN is 66MHz, then
> - * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
> - */
> -#define CONFIG_SYS_HRCW_LOW (\
> - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> - HRCWL_DDR_TO_SCB_CLK_1X1 |\
> - HRCWL_SVCOD_DIV_2 |\
> - HRCWL_CSB_TO_CLKIN_6X1 |\
> - HRCWL_CORE_TO_CSB_1_5X1)
> -
> -#ifdef CONFIG_PCISLAVE
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_AGENT |\
> - HRCWH_PCI1_ARBITER_DISABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0XFFF00100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_RL_EXT_LEGACY |\
> - HRCWH_TSEC1M_IN_RGMII |\
> - HRCWH_TSEC2M_IN_RGMII |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LDP_CLEAR)
> -#else
> -#define CONFIG_SYS_HRCW_HIGH (\
> - HRCWH_PCI_HOST |\
> - HRCWH_PCI1_ARBITER_ENABLE |\
> - HRCWH_CORE_ENABLE |\
> - HRCWH_FROM_0X00000100 |\
> - HRCWH_BOOTSEQ_DISABLE |\
> - HRCWH_SW_WATCHDOG_DISABLE |\
> - HRCWH_ROM_LOC_LOCAL_16BIT |\
> - HRCWH_RL_EXT_LEGACY |\
> - HRCWH_TSEC1M_IN_RGMII |\
> - HRCWH_TSEC2M_IN_RGMII |\
> - HRCWH_BIG_ENDIAN |\
> - HRCWH_LDP_CLEAR)
> -#endif
> -
> -/* Arbiter Configuration Register */
> -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
> -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
> -
> -/* System Priority Control Register */
> -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
> -
> -/*
> - * IP blocks clock configuration
> - */
> -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
> -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
> -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
> -
> -/*
> - * System IO Config
> - */
> -#define CONFIG_SYS_SICRH 0x00000000
> -#define CONFIG_SYS_SICRL 0x00000000
> -
> -/*
> - * Output Buffer Impedance
> - */
> -#define CONFIG_SYS_OBIR 0x31100000
> -
> -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
> -#define CONFIG_BOARD_EARLY_INIT_R
> -#define CONFIG_HWCONFIG
> -
> -/*
> - * IMMR new address
> - */
> -#define CONFIG_SYS_IMMR 0xE0000000
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
> -#define CONFIG_SYS_83XX_DDR_USES_CS0
> -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
> - | DDRCDR_ODT \
> - | DDRCDR_Q_DRN)
> - /* 0x80080001 */ /* ODT 150ohm on SoC */
> -
> -#undef CONFIG_DDR_ECC /* support DDR ECC function */
> -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
> -
> -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
> -#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
> -
> -#if defined(CONFIG_SPD_EEPROM)
> -#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
> -#else
> -/*
> - * Manually set up DDR parameters
> - * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
> - * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
> - */
> -#define CONFIG_SYS_DDR_SIZE 512 /* MB */
> -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
> -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
> - | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
> - | CSCONFIG_ROW_BIT_14 \
> - | CSCONFIG_COL_BIT_10)
> - /* 0x80010202 */
> -#define CONFIG_SYS_DDR_TIMING_3 0x00000000
> -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
> - | (0 << TIMING_CFG0_WRT_SHIFT) \
> - | (0 << TIMING_CFG0_RRT_SHIFT) \
> - | (0 << TIMING_CFG0_WWT_SHIFT) \
> - | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
> - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
> - | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
> - /* 0x00620802 */
> -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
> - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
> - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
> - | (5 << TIMING_CFG1_CASLAT_SHIFT) \
> - | (13 << TIMING_CFG1_REFREC_SHIFT) \
> - | (3 << TIMING_CFG1_WRREC_SHIFT) \
> - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
> - | (2 << TIMING_CFG1_WRTORD_SHIFT))
> - /* 0x3935d322 */
> -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
> - | (6 << TIMING_CFG2_CPO_SHIFT) \
> - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
> - | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
> - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
> - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
> - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
> - /* 0x131088c8 */
> -#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
> - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
> - /* 0x03E00100 */
> -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
> -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
> -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
> - | (0x1432 << SDRAM_MODE_SD_SHIFT))
> - /* ODT 150ohm CL=3, AL=1 on SDRAM */
> -#define CONFIG_SYS_DDR_MODE2 0x00000000
> -#endif
> -
> -/*
> - * Memory test
> - */
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
> -#define CONFIG_SYS_MEMTEST_END 0x00140000
> -
> -/*
> - * The reserved memory
> - */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
> -
> -/*
> - * Initial RAM Base Address Setup
> - */
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * Local Bus Configuration & Clock Setup
> - */
> -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
> -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
> -#define CONFIG_SYS_LBC_LBCR 0x00000000
> -#define CONFIG_FSL_ELBC 1
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
> -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
> -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
> -
> - /* Window base at flash base */
> -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
> -
> -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
> - | BR_PS_16 /* 16 bit port */ \
> - | BR_MS_GPCM /* MSEL = GPCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
> - | OR_UPM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_ACS_DIV2 \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFE000FF7 */
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -/*
> - * BCSR on the Local Bus
> - */
> -#define CONFIG_SYS_BCSR 0xF8000000
> - /* Access window base at BCSR base */
> -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
> -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
> - | BR_PS_8 \
> - | BR_MS_GPCM \
> - | BR_V)
> - /* 0xF8000801 */
> -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
> - | OR_GPCM_XAM \
> - | OR_GPCM_CSNT \
> - | OR_GPCM_XACS \
> - | OR_GPCM_SCY_15 \
> - | OR_GPCM_TRLX_SET \
> - | OR_GPCM_EHTR_SET \
> - | OR_GPCM_EAD)
> - /* 0xFFFFE9F7 */
> -
> -/*
> - * NAND Flash on the Local Bus
> - */
> -#define CONFIG_CMD_NAND 1
> -#define CONFIG_MTD_NAND_VERIFY_WRITE 1
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_NAND_FSL_ELBC 1
> -
> -#define CONFIG_SYS_NAND_BASE 0xE0600000
> -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
> - | BR_DECC_CHK_GEN /* Use HW ECC */ \
> - | BR_PS_8 /* 8 bit port */ \
> - | BR_MS_FCM /* MSEL = FCM */ \
> - | BR_V) /* valid */
> -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
> - | OR_FCM_BCTLD \
> - | OR_FCM_CST \
> - | OR_FCM_CHT \
> - | OR_FCM_SCY_1 \
> - | OR_FCM_RST \
> - | OR_FCM_TRLX \
> - | OR_FCM_EHTR)
> - /* 0xFFFF919E */
> -
> -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
> -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -/* Use the HUSH parser */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* Pass open firmware flat tree */
> -#define CONFIG_OF_LIBFDT 1
> -#define CONFIG_OF_BOARD_SETUP 1
> -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
> -
> -/*
> - * Config on-board RTC
> - */
> -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
> -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
> -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
> -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
> -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
> -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
> -
> -#define CONFIG_SYS_PCIE1_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
> -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
> -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
> -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
> -
> -#define CONFIG_SYS_PCIE2_BASE 0xC0000000
> -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
> -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
> -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
> -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
> -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
> -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#ifndef __ASSEMBLY__
> -extern int board_pci_host_broken(void);
> -#endif
> -#define CONFIG_PCIE
> -#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
> -
> -#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
> -#define CONFIG_CMD_USB
> -#define CONFIG_USB_STORAGE
> -#define CONFIG_USB_EHCI
> -#define CONFIG_USB_EHCI_FSL
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -
> -#undef CONFIG_EEPRO100
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * TSEC
> - */
> -#define CONFIG_TSEC_ENET /* TSEC ethernet support */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/*
> - * TSEC ethernet configuration
> - */
> -#define CONFIG_MII 1 /* MII PHY management */
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "eTSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "eTSEC1"
> -#define TSEC1_PHY_ADDR 2
> -#define TSEC2_PHY_ADDR 3
> -#define TSEC1_PHY_ADDR_SGMII 8
> -#define TSEC2_PHY_ADDR_SGMII 4
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
> -
> -/* Options are: TSEC[0-1] */
> -#define CONFIG_ETHPRIME "eTSEC1"
> -
> -/* SERDES */
> -#define CONFIG_FSL_SERDES
> -#define CONFIG_FSL_SERDES1 0xe3000
> -#define CONFIG_FSL_SERDES2 0xe3100
> -
> -/*
> - * SATA
> - */
> -#define CONFIG_LIBATA
> -#define CONFIG_FSL_SATA
> -
> -#define CONFIG_SYS_SATA_MAX_DEVICE 2
> -#define CONFIG_SATA1
> -#define CONFIG_SYS_SATA1_OFFSET 0x18000
> -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
> -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
> -#define CONFIG_SATA2
> -#define CONFIG_SYS_SATA2_OFFSET 0x19000
> -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
> -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
> -
> -#ifdef CONFIG_FSL_SATA
> -#define CONFIG_LBA48
> -#define CONFIG_CMD_SATA
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_CMD_EXT2
> -#endif
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> - #define CONFIG_ENV_IS_IN_FLASH 1
> - #define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
> - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
> - #define CONFIG_ENV_SIZE 0x2000
> -#else
> - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
> - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
> - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
> - #define CONFIG_ENV_SIZE 0x2000
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_MII
> -#define CONFIG_CMD_DATE
> -
> -#if defined(CONFIG_PCI)
> - #define CONFIG_CMD_PCI
> -#endif
> -
> -#if defined(CONFIG_SYS_RAMBOOT)
> - #undef CONFIG_CMD_SAVEENV
> - #undef CONFIG_CMD_LOADS
> -#endif
> -
> -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
> -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -#define CONFIG_MMC 1
> -
> -#ifdef CONFIG_MMC
> -#define CONFIG_FSL_ESDHC
> -#define CONFIG_FSL_ESDHC_PIN_MUX
> -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
> -#define CONFIG_CMD_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -#define CONFIG_DOS_PARTITION
> -#endif
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -#if defined(CONFIG_CMD_KGDB)
> - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> -#else
> - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#endif
> -
> - /* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> - /* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
> -
> -/*
> - * Core HID Setup
> - */
> -#define CONFIG_SYS_HID0_INIT 0x000000000
> -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
> - HID0_ENABLE_INSTRUCTION_CACHE)
> -#define CONFIG_SYS_HID2 HID2_HBE
> -
> -/*
> - * MMU Setup
> - */
> -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
> -
> -/* DDR: cache cacheable */
> -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
> -
> -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
> -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
> -
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
> -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
> -
> -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
> - | BATU_BL_8M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
> -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
> -
> -/* BCSR: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
> -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
> -
> -/* FLASH: icache cacheable, but dcache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
> - | BATU_BL_32M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
> -
> -/* Stack in dcache: cacheable, no memory coherence */
> -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
> -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
> - | BATU_BL_128K \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
> -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
> -
> -#ifdef CONFIG_PCI
> -/* PCI MEM space: cacheable */
> -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
> - | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -/* PCI MMIO space: cache-inhibit and guarded */
> -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
> - | BATL_PP_RW \
> - | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
> - | BATU_BL_256M \
> - | BATU_VS \
> - | BATU_VP)
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -#else
> -#define CONFIG_SYS_IBAT6L (0)
> -#define CONFIG_SYS_IBAT6U (0)
> -#define CONFIG_SYS_IBAT7L (0)
> -#define CONFIG_SYS_IBAT7U (0)
> -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
> -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
> -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
> -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#define CONFIG_ENV_OVERWRITE
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
> -
> -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
> -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=1000000\0" \
> - "ramdiskfile=ramfs.83xx\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=mpc8379_mds.dtb\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
> -
> -#endif /* __CONFIG_H */
>
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards
2015-03-17 6:07 ` Sinan Akman
@ 2015-03-17 12:28 ` Masahiro Yamada
2015-03-17 14:46 ` Sinan Akman
2015-03-17 13:15 ` Tom Rini
1 sibling, 1 reply; 22+ messages in thread
From: Masahiro Yamada @ 2015-03-17 12:28 UTC (permalink / raw)
To: u-boot
2015-03-17 15:07 GMT+09:00 Sinan Akman <sinan@writeme.com>:
>
> Hi Masahiro
>
> On 03/16/2015 11:28 PM, Masahiro Yamada wrote:
>>
>> Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
>> MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
>
>
> I had sent an e-mail on that few weeks ago :
>
> http://lists.denx.de/pipermail/u-boot/2015-February/203613.html
>
> I am receiving the boards from FSL and I would like to
> take over the maintainership of MPC8323ERDB and MPC8308RDB
> boards. I should have them in about a week.
>
> Could you please delay the removal of those two boards
> to give me a bit time to test generic board changes on the
> actual board. I really like to keep those boards supported.
I marked 7/7 as Deferred.
BTW, please stop full-quote against a big patch.
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards
2015-03-17 12:28 ` Masahiro Yamada
@ 2015-03-17 14:46 ` Sinan Akman
0 siblings, 0 replies; 22+ messages in thread
From: Sinan Akman @ 2015-03-17 14:46 UTC (permalink / raw)
To: u-boot
On 03/17/2015 08:28 AM, Masahiro Yamada wrote:
> [...]
>
> I marked 7/7 as Deferred.
Thanks much Masahiro. As per Tom's other e-mail
I'll be sending the patches soon.
> BTW, please stop full-quote against a big patch.
Oh I apologise for this. It was already late when
I realized. I'll sure pay more attention.
Regards
Sinan Akman
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards
2015-03-17 6:07 ` Sinan Akman
2015-03-17 12:28 ` Masahiro Yamada
@ 2015-03-17 13:15 ` Tom Rini
1 sibling, 0 replies; 22+ messages in thread
From: Tom Rini @ 2015-03-17 13:15 UTC (permalink / raw)
To: u-boot
On Tue, Mar 17, 2015 at 02:07:34AM -0400, Sinan Akman wrote:
> Hi Masahiro
>
> On 03/16/2015 11:28 PM, Masahiro Yamada wrote:
> >Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
> >MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
>
> I had sent an e-mail on that few weeks ago :
>
> http://lists.denx.de/pipermail/u-boot/2015-February/203613.html
>
> I am receiving the boards from FSL and I would like to
> take over the maintainership of MPC8323ERDB and MPC8308RDB
> boards. I should have them in about a week.
>
> Could you please delay the removal of those two boards
> to give me a bit time to test generic board changes on the
> actual board. I really like to keep those boards supported.
Can you please start with a patch that adds yourself to MAINTAINERS?
Thanks. And based on other mpc83xx boards having already been converted
to generic board doing the switch now and making sure it compiles is
probably OK enough for now.
--
Tom
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD (was: [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards)
2015-03-17 3:28 ` [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards Masahiro Yamada
2015-03-17 6:07 ` Sinan Akman
@ 2015-03-17 17:00 ` Kim Phillips
2015-03-17 19:18 ` Tom Rini
1 sibling, 1 reply; 22+ messages in thread
From: Kim Phillips @ 2015-03-17 17:00 UTC (permalink / raw)
To: u-boot
On Tue, 17 Mar 2015 12:28:10 +0900
Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
> Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
> MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
>
> They have not been converted to Generic Board, so should be removed.
> (See doc/README.generic-board for details.)
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Ilya Yanok <yanok@emcraft.com>
> Cc: Dave Liu <daveliu@freescale.com>
> Cc: Michael Barkowski <michael.barkowski@freescale.com>
> Cc: Kim Phillips <kim.phillips@freescale.com>
Nacked-by: Kim Phillips <kim.phillips@freescale.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD (was: [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards)
2015-03-17 17:00 ` [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD (was: [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards) Kim Phillips
@ 2015-03-17 19:18 ` Tom Rini
2015-03-17 19:41 ` [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD Sinan Akman
0 siblings, 1 reply; 22+ messages in thread
From: Tom Rini @ 2015-03-17 19:18 UTC (permalink / raw)
To: u-boot
On Tue, Mar 17, 2015 at 12:00:45PM -0500, Kim Phillips wrote:
> On Tue, 17 Mar 2015 12:28:10 +0900
> Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
>
> > Remove MPC8308RDB, MPC8313ERDB, MPC8315ERDB, MPC8323ERDB,
> > MPC832XEMDS, MPC8349EMDS, MPC8349ITX, and MPC837XEMDS.
> >
> > They have not been converted to Generic Board, so should be removed.
> > (See doc/README.generic-board for details.)
> >
> > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> > Cc: Ilya Yanok <yanok@emcraft.com>
> > Cc: Dave Liu <daveliu@freescale.com>
> > Cc: Michael Barkowski <michael.barkowski@freescale.com>
> > Cc: Kim Phillips <kim.phillips@freescale.com>
>
> Nacked-by: Kim Phillips <kim.phillips@freescale.com>
>
> From 39cb4e8eb7f768778ada3aed2e1419c88fe3adda Mon Sep 17 00:00:00 2001
> From: Kim Phillips <kim.phillips@freescale.com>
> Date: Tue, 17 Mar 2015 11:44:20 -0500
> Subject: [PATCH] mpc83xx: preempt premature board support removal by setting
> GENERIC_BOARD
>
> Boards that haven't been converted to GENERIC_BOARD does
> *not* mean they should be removed.
>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
I'll apply this shortly. But we've been saying for a long while that
things need converint to GENERIC_BOARD and stuff that doesn't get
converted is getting removed (since we've got even bigger things coming
along and if we can't convince people to do and test the "small" things
why do the larger things on those platforms). So please push up the
chain that some time needs to be spent on mpc83xx support upstream, at
least for basic testing. Thanks.
--
Tom
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH] mpc83xx: preempt premature board support removal by setting GENERIC_BOARD
2015-03-17 19:18 ` Tom Rini
@ 2015-03-17 19:41 ` Sinan Akman
0 siblings, 0 replies; 22+ messages in thread
From: Sinan Akman @ 2015-03-17 19:41 UTC (permalink / raw)
To: u-boot
Hi Tom
On 03/17/2015 03:18 PM, Tom Rini wrote:
> [...]
>>
>> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
>
> I'll apply this shortly. But we've been saying for a long while that
> things need converint to GENERIC_BOARD and stuff that doesn't get
> converted is getting removed (since we've got even bigger things coming
> along and if we can't convince people to do and test the "small" things
> why do the larger things on those platforms). So please push up the
> chain that some time needs to be spent on mpc83xx support upstream, at
> least for basic testing. Thanks.
As indicated I will be taking up on two boards now and I can
help out with some others (particularly for quick tests etc.)
if this proves to be helpful.
Hope this helps everyone.
Regards
Sinan Akman
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards
2015-03-17 3:28 [U-Boot] [PATCH 0/7] powerpc: drop some non-generic boards Masahiro Yamada
` (6 preceding siblings ...)
2015-03-17 3:28 ` [U-Boot] [PATCH 7/7] powerpc: mpc83xx: remove non-generic freescale boards Masahiro Yamada
@ 2015-03-17 6:10 ` Sinan Akman
7 siblings, 0 replies; 22+ messages in thread
From: Sinan Akman @ 2015-03-17 6:10 UTC (permalink / raw)
To: u-boot
On 03/16/2015 11:28 PM, Masahiro Yamada wrote:
>
> There are still many non-generic boards (=unmaintained boards)
> remaining. This series removes some of them.
>
> If somebody wants to keep them, please speak up!
> (I am CCing the board maintainers.)
Indeed, I would like to keep mpc8323rdb and mpc8308rdb.
I can take the maintainership as the current maintainers
haven't responded for some time. Please see my other e-mail.
Thanks
Sinan Akman
^ permalink raw reply [flat|nested] 22+ messages in thread