ATSAMA5D big endian work

ATSAMA5D big endian work

[Ben Dooks]

I have been testing the ATSAMA5D36 xplained board with big endian and
the following are the fixes to get the system working.

[PATCH 01/13] ARM: at91: Add big endian configuration for ATSAMA5D devices

[Ben Dooks]

The ATSAMA5D devices are based on Cortex-A5 which should work in big
endian configuration. Add ARCH_SUPPORTS_BIG_ENDIAN if these SoCs are
configured so we can run the system big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard
CC: Russell King <linux@arm.linux.org.uk>
---
 arch/arm/mach-at91/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c74a443..05212fb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,6 +18,7 @@ config HAVE_AT91_H32MX
 
 config SOC_SAMA5
 	bool
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ATMEL_AIC5_IRQ
 	select COMMON_CLK_AT91
 	select CPU_V7
-- 
2.1.4

[PATCH 01/13] ARM: at91: Add big endian configuration for ATSAMA5D devices

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:53 Wed 18 Mar     , Ben Dooks wrote:
> The ATSAMA5D devices are based on Cortex-A5 which should work in big
> endian configuration. Add ARCH_SUPPORTS_BIG_ENDIAN if these SoCs are
> configured so we can run the system big endian.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Jean-Christophe Plagniol-Villard
missing e-mail
> CC: Russell King <linux@arm.linux.org.uk>
> ---
>  arch/arm/mach-at91/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index c74a443..05212fb 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -18,6 +18,7 @@ config HAVE_AT91_H32MX
>  
>  config SOC_SAMA5
>  	bool
> +	select ARCH_SUPPORTS_BIG_ENDIAN
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

on the whole patch serie

Best Regards,
J.

[PATCH 02/13] tty: serial: atmel: fix big-endian on ARMv7 devices

Add support for using this driver on ARMv7 devices configured for
big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.cz>
CC: linux-serial@vger.kernel.org
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
---
 drivers/tty/serial/atmel_serial.c | 62 ++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 4e959c4..40ef95f 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -88,36 +88,44 @@ static void atmel_stop_rx(struct uart_port *port);
 
 #define ATMEL_ISR_PASS_LIMIT	256
 
+#ifdef CONFIG_AVR32
+#define __atserial_writel	__raw_writel
+#define __atserial_readl	__raw_readl
+#else
+#define __atserial_writel	writel_relaxed
+#define __atserial_readl	readl_relaxed
+#endif
+
 /* UART registers. CR is write-only, hence no GET macro */
-#define UART_PUT_CR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_CR)
-#define UART_GET_MR(port)	__raw_readl((port)->membase + ATMEL_US_MR)
-#define UART_PUT_MR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_MR)
-#define UART_PUT_IER(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_IER)
-#define UART_PUT_IDR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_IDR)
-#define UART_GET_IMR(port)	__raw_readl((port)->membase + ATMEL_US_IMR)
-#define UART_GET_CSR(port)	__raw_readl((port)->membase + ATMEL_US_CSR)
-#define UART_GET_CHAR(port)	__raw_readl((port)->membase + ATMEL_US_RHR)
-#define UART_PUT_CHAR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_THR)
-#define UART_GET_BRGR(port)	__raw_readl((port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_BRGR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_RTOR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_RTOR)
-#define UART_PUT_TTGR(port, v)	__raw_writel(v, (port)->membase + ATMEL_US_TTGR)
-#define UART_GET_IP_NAME(port)	__raw_readl((port)->membase + ATMEL_US_NAME)
-#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
+#define UART_PUT_CR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_CR)
+#define UART_GET_MR(port)	__atserial_readl((port)->membase + ATMEL_US_MR)
+#define UART_PUT_MR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_MR)
+#define UART_PUT_IER(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_IER)
+#define UART_PUT_IDR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_IDR)
+#define UART_GET_IMR(port)	__atserial_readl((port)->membase + ATMEL_US_IMR)
+#define UART_GET_CSR(port)	__atserial_readl((port)->membase + ATMEL_US_CSR)
+#define UART_GET_CHAR(port)	__atserial_readl((port)->membase + ATMEL_US_RHR)
+#define UART_PUT_CHAR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_THR)
+#define UART_GET_BRGR(port)	__atserial_readl((port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_BRGR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_RTOR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_RTOR)
+#define UART_PUT_TTGR(port, v)	__atserial_writel(v, (port)->membase + ATMEL_US_TTGR)
+#define UART_GET_IP_NAME(port)	__atserial_readl((port)->membase + ATMEL_US_NAME)
+#define UART_GET_IP_VERSION(port) __atserial_readl((port)->membase + ATMEL_US_VERSION)
 
  /* PDC registers */
-#define UART_PUT_PTCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
-#define UART_GET_PTSR(port)	__raw_readl((port)->membase + ATMEL_PDC_PTSR)
-
-#define UART_PUT_RPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
-#define UART_GET_RPR(port)	__raw_readl((port)->membase + ATMEL_PDC_RPR)
-#define UART_PUT_RCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
-#define UART_PUT_RNPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
-#define UART_PUT_RNCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
-
-#define UART_PUT_TPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
-#define UART_PUT_TCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
-#define UART_GET_TCR(port)	__raw_readl((port)->membase + ATMEL_PDC_TCR)
+#define UART_PUT_PTCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_PTCR)
+#define UART_GET_PTSR(port)	__atserial_readl((port)->membase + ATMEL_PDC_PTSR)
+
+#define UART_PUT_RPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RPR)
+#define UART_GET_RPR(port)	__atserial_readl((port)->membase + ATMEL_PDC_RPR)
+#define UART_PUT_RCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RCR)
+#define UART_PUT_RNPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RNPR)
+#define UART_PUT_RNCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RNCR)
+
+#define UART_PUT_TPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_TPR)
+#define UART_PUT_TCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_TCR)
+#define UART_GET_TCR(port)	__atserial_readl((port)->membase + ATMEL_PDC_TCR)
 
 struct atmel_dma_buffer {
 	unsigned char	*buf;
-- 
2.1.4

[PATCH 02/13] tty: serial: atmel: fix big-endian on ARMv7 devices

[Ben Dooks]

Add support for using this driver on ARMv7 devices configured for
big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.cz>
CC: linux-serial at vger.kernel.org
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
---
 drivers/tty/serial/atmel_serial.c | 62 ++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 4e959c4..40ef95f 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -88,36 +88,44 @@ static void atmel_stop_rx(struct uart_port *port);
 
 #define ATMEL_ISR_PASS_LIMIT	256
 
+#ifdef CONFIG_AVR32
+#define __atserial_writel	__raw_writel
+#define __atserial_readl	__raw_readl
+#else
+#define __atserial_writel	writel_relaxed
+#define __atserial_readl	readl_relaxed
+#endif
+
 /* UART registers. CR is write-only, hence no GET macro */
-#define UART_PUT_CR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_CR)
-#define UART_GET_MR(port)	__raw_readl((port)->membase + ATMEL_US_MR)
-#define UART_PUT_MR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_MR)
-#define UART_PUT_IER(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_IER)
-#define UART_PUT_IDR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_IDR)
-#define UART_GET_IMR(port)	__raw_readl((port)->membase + ATMEL_US_IMR)
-#define UART_GET_CSR(port)	__raw_readl((port)->membase + ATMEL_US_CSR)
-#define UART_GET_CHAR(port)	__raw_readl((port)->membase + ATMEL_US_RHR)
-#define UART_PUT_CHAR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_THR)
-#define UART_GET_BRGR(port)	__raw_readl((port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_BRGR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_RTOR(port,v)	__raw_writel(v, (port)->membase + ATMEL_US_RTOR)
-#define UART_PUT_TTGR(port, v)	__raw_writel(v, (port)->membase + ATMEL_US_TTGR)
-#define UART_GET_IP_NAME(port)	__raw_readl((port)->membase + ATMEL_US_NAME)
-#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
+#define UART_PUT_CR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_CR)
+#define UART_GET_MR(port)	__atserial_readl((port)->membase + ATMEL_US_MR)
+#define UART_PUT_MR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_MR)
+#define UART_PUT_IER(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_IER)
+#define UART_PUT_IDR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_IDR)
+#define UART_GET_IMR(port)	__atserial_readl((port)->membase + ATMEL_US_IMR)
+#define UART_GET_CSR(port)	__atserial_readl((port)->membase + ATMEL_US_CSR)
+#define UART_GET_CHAR(port)	__atserial_readl((port)->membase + ATMEL_US_RHR)
+#define UART_PUT_CHAR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_THR)
+#define UART_GET_BRGR(port)	__atserial_readl((port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_BRGR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_RTOR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_US_RTOR)
+#define UART_PUT_TTGR(port, v)	__atserial_writel(v, (port)->membase + ATMEL_US_TTGR)
+#define UART_GET_IP_NAME(port)	__atserial_readl((port)->membase + ATMEL_US_NAME)
+#define UART_GET_IP_VERSION(port) __atserial_readl((port)->membase + ATMEL_US_VERSION)
 
  /* PDC registers */
-#define UART_PUT_PTCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
-#define UART_GET_PTSR(port)	__raw_readl((port)->membase + ATMEL_PDC_PTSR)
-
-#define UART_PUT_RPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
-#define UART_GET_RPR(port)	__raw_readl((port)->membase + ATMEL_PDC_RPR)
-#define UART_PUT_RCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
-#define UART_PUT_RNPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
-#define UART_PUT_RNCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
-
-#define UART_PUT_TPR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
-#define UART_PUT_TCR(port,v)	__raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
-#define UART_GET_TCR(port)	__raw_readl((port)->membase + ATMEL_PDC_TCR)
+#define UART_PUT_PTCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_PTCR)
+#define UART_GET_PTSR(port)	__atserial_readl((port)->membase + ATMEL_PDC_PTSR)
+
+#define UART_PUT_RPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RPR)
+#define UART_GET_RPR(port)	__atserial_readl((port)->membase + ATMEL_PDC_RPR)
+#define UART_PUT_RCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RCR)
+#define UART_PUT_RNPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RNPR)
+#define UART_PUT_RNCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_RNCR)
+
+#define UART_PUT_TPR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_TPR)
+#define UART_PUT_TCR(port,v)	__atserial_writel(v, (port)->membase + ATMEL_PDC_TCR)
+#define UART_GET_TCR(port)	__atserial_readl((port)->membase + ATMEL_PDC_TCR)
 
 struct atmel_dma_buffer {
 	unsigned char	*buf;
-- 
2.1.4

Re: [PATCH 02/13] tty: serial: atmel: fix big-endian on ARMv7 devices

[Greg Kroah-Hartman]

On Wed, Mar 18, 2015 at 03:53:01PM +0000, Ben Dooks wrote:
> Add support for using this driver on ARMv7 devices configured for
> big endian.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Jiri Slaby <jslaby@suse.cz>
> CC: linux-serial@vger.kernel.org
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> ---
>  drivers/tty/serial/atmel_serial.c | 62 ++++++++++++++++++++++-----------------
>  1 file changed, 35 insertions(+), 27 deletions(-)

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 02/13] tty: serial: atmel: fix big-endian on ARMv7 devices

[Greg Kroah-Hartman]

On Wed, Mar 18, 2015 at 03:53:01PM +0000, Ben Dooks wrote:
> Add support for using this driver on ARMv7 devices configured for
> big endian.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Jiri Slaby <jslaby@suse.cz>
> CC: linux-serial at vger.kernel.org
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> ---
>  drivers/tty/serial/atmel_serial.c | 62 ++++++++++++++++++++++-----------------
>  1 file changed, 35 insertions(+), 27 deletions(-)

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

[PATCH 03/13] ARM: at91: use readl/writel relaxed instead of __raw for big endian

[Ben Dooks]

Add support for low-level uart debug when the system is running in
big endian mode by changing to use the readl_relaxed and writel_relaxed
calls instead of the __raw variants.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-at91/include/mach/uncompress.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4ebb609..596696b 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -112,7 +112,7 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
 	u32 cidr, socid;
 
-	cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
+	cidr = readl_relaxed(dbgu_base + AT91_DBGU_CIDR);
 	socid = cidr & ~AT91_CIDR_VERSION;
 
 	switch (socid) {
@@ -140,7 +140,7 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 		return uarts_sam9x5;
 
 	case ARCH_ID_SAMA5:
-		cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
+		cidr = readl_relaxed(dbgu_base + AT91_DBGU_EXID);
 		if (cidr & ARCH_EXID_SAMA5D3)
 			return uarts_sama5d3;
 		else if (cidr & ARCH_EXID_SAMA5D4)
@@ -180,7 +180,7 @@ static inline void arch_decomp_setup(void)
 		/* physical address */
 		at91_uart = (void __iomem *)usarts[i];
 
-		if (__raw_readl(at91_uart + ATMEL_US_BRGR))
+		if (readl_relaxed(at91_uart + ATMEL_US_BRGR))
 			return;
 		i++;
 	} while (usarts[i]);
@@ -200,9 +200,9 @@ static void putc(int c)
 	if (!at91_uart)
 		return;
 
-	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
+	while (!(readl_relaxed(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
 		barrier();
-	__raw_writel(c, at91_uart + ATMEL_US_THR);
+	writel_relaxed(c, at91_uart + ATMEL_US_THR);
 }
 
 static inline void flush(void)
@@ -211,7 +211,7 @@ static inline void flush(void)
 		return;
 
 	/* wait for transmission to complete */
-	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
+	while (!(readl_relaxed(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
 		barrier();
 }
 
-- 
2.1.4

[PATCH 04/13] ARM: at91: setup.c: use endian agnostic IO functions

[Ben Dooks]

Use the endian agnostic IO accessors in setup.c to avoid issues if
running on an big endian capable cpu

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
---
 arch/arm/mach-at91/setup.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4e58bc9..7bf81fd 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -46,7 +46,7 @@ static void __init soc_detect(u32 dbgu_base)
 {
 	u32 cidr, socid;
 
-	cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
+	cidr = readl_relaxed(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 	socid = cidr & ~AT91_CIDR_VERSION;
 
 	switch (socid) {
@@ -96,7 +96,7 @@ static void __init soc_detect(u32 dbgu_base)
 		break;
 
 	case ARCH_ID_SAMA5:
-		at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+		at91_soc_initdata.exid = readl_relaxed(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 		if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 			at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 		}
@@ -121,7 +121,7 @@ static void __init soc_detect(u32 dbgu_base)
 
 	/* sub version of soc */
 	if (!at91_soc_initdata.exid)
-		at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+		at91_soc_initdata.exid = readl_relaxed(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 
 	if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 		switch (at91_soc_initdata.exid) {
@@ -183,12 +183,12 @@ static void __init alt_soc_detect(u32 dbgu_base)
 	u32 cidr, socid;
 
 	/* SoC ID */
-	cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
+	cidr = readl_relaxed(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 	socid = cidr & ~AT91_CIDR_VERSION;
 
 	switch (socid) {
 	case ARCH_ID_SAMA5:
-		at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+		at91_soc_initdata.exid = readl_relaxed(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 		if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 			at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 		} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
@@ -204,7 +204,7 @@ static void __init alt_soc_detect(u32 dbgu_base)
 
 	/* sub version of soc */
 	if (!at91_soc_initdata.exid)
-		at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+		at91_soc_initdata.exid = readl_relaxed(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 
 	if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 		switch (at91_soc_initdata.exid) {
-- 
2.1.4

[PATCH 05/13] ARM: at91: debug: fix debug in big endian mode

[Ben Dooks]

Add appropriate endian swaps for when the CPU is in big endian

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
---
 arch/arm/include/debug/at91.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index c3c45e6..0217f8d 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -40,12 +40,14 @@
 
 	.macro	waituart,rd,rx
 1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
+ARM_BE8(rev	\rd, \rd)
 	tst	\rd, #AT91_DBGU_TXRDY			@ DBGU_TXRDY = 1 when ready to transmit
 	beq	1001b
 	.endm
 
 	.macro	busyuart,rd,rx
 1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
+ARM_BE8(rev	\rd, \rd)
 	tst	\rd, #AT91_DBGU_TXEMPTY			@ DBGU_TXEMPTY = 1 when transmission complete
 	beq	1001b
 	.endm
-- 
2.1.4

[PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Ben Dooks]

Fix the use of __raw IO accessor with the readl/writel_relaxed versions
to allow the code to be used on a system running in big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Daniel Lezcano <daniel.lezcano@linaro.org>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Linux Kernel <linux-kernel@vger.kernel.org>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
---
 drivers/clocksource/timer-atmel-pit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index b5b4d45..c0304ff 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
 
 static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
 {
-	return __raw_readl(base + reg_offset);
+	return readl_relaxed(base + reg_offset);
 }
 
 static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
 {
-	__raw_writel(value, base + reg_offset);
+	writel_relaxed(value, base + reg_offset);
 }
 
 /*
-- 
2.1.4

[PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Ben Dooks]

Fix the use of __raw IO accessor with the readl/writel_relaxed versions
to allow the code to be used on a system running in big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Daniel Lezcano <daniel.lezcano@linaro.org>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Linux Kernel <linux-kernel@vger.kernel.org>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
---
 drivers/clocksource/timer-atmel-pit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index b5b4d45..c0304ff 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
 
 static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
 {
-	return __raw_readl(base + reg_offset);
+	return readl_relaxed(base + reg_offset);
 }
 
 static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
 {
-	__raw_writel(value, base + reg_offset);
+	writel_relaxed(value, base + reg_offset);
 }
 
 /*
-- 
2.1.4

Re: [PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a écrit :
> Fix the use of __raw IO accessor with the readl/writel_relaxed versions
> to allow the code to be used on a system running in big endian.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Linux Kernel <linux-kernel@vger.kernel.org>
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Yes:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Daniel, do you want to take it?


> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>  drivers/clocksource/timer-atmel-pit.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
> index b5b4d45..c0304ff 100644
> --- a/drivers/clocksource/timer-atmel-pit.c
> +++ b/drivers/clocksource/timer-atmel-pit.c
> @@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
>  
>  static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
>  {
> -	return __raw_readl(base + reg_offset);
> +	return readl_relaxed(base + reg_offset);
>  }
>  
>  static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
>  {
> -	__raw_writel(value, base + reg_offset);
> +	writel_relaxed(value, base + reg_offset);
>  }
>  
>  /*
> 


-- 
Nicolas Ferre

[PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a ?crit :
> Fix the use of __raw IO accessor with the readl/writel_relaxed versions
> to allow the code to be used on a system running in big endian.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Linux Kernel <linux-kernel@vger.kernel.org>
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Yes:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Daniel, do you want to take it?


> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>  drivers/clocksource/timer-atmel-pit.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
> index b5b4d45..c0304ff 100644
> --- a/drivers/clocksource/timer-atmel-pit.c
> +++ b/drivers/clocksource/timer-atmel-pit.c
> @@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
>  
>  static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
>  {
> -	return __raw_readl(base + reg_offset);
> +	return readl_relaxed(base + reg_offset);
>  }
>  
>  static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
>  {
> -	__raw_writel(value, base + reg_offset);
> +	writel_relaxed(value, base + reg_offset);
>  }
>  
>  /*
> 


-- 
Nicolas Ferre

Re: [PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Daniel Lezcano]

On 03/23/2015 12:27 PM, Nicolas Ferre wrote:
> Le 18/03/2015 16:53, Ben Dooks a écrit :
>> Fix the use of __raw IO accessor with the readl/writel_relaxed versions
>> to allow the code to be used on a system running in big endian.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> --
>> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
>> CC: Thomas Gleixner <tglx@linutronix.de>
>> CC: Linux Kernel <linux-kernel@vger.kernel.org>
>> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
>> CC: Andrew Victor <linux@maxim.org.za>
>> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Yes:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Daniel, do you want to take it?

Yep.

>> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
>> ---
>>   drivers/clocksource/timer-atmel-pit.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
>> index b5b4d45..c0304ff 100644
>> --- a/drivers/clocksource/timer-atmel-pit.c
>> +++ b/drivers/clocksource/timer-atmel-pit.c
>> @@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
>>
>>   static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
>>   {
>> -	return __raw_readl(base + reg_offset);
>> +	return readl_relaxed(base + reg_offset);
>>   }
>>
>>   static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
>>   {
>> -	__raw_writel(value, base + reg_offset);
>> +	writel_relaxed(value, base + reg_offset);
>>   }
>>
>>   /*
>>
>
>


-- 
  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

[PATCH 06/13] ARM: at91: PIT: make IO endian agnostic

[Daniel Lezcano]

On 03/23/2015 12:27 PM, Nicolas Ferre wrote:
> Le 18/03/2015 16:53, Ben Dooks a ?crit :
>> Fix the use of __raw IO accessor with the readl/writel_relaxed versions
>> to allow the code to be used on a system running in big endian.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> --
>> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
>> CC: Thomas Gleixner <tglx@linutronix.de>
>> CC: Linux Kernel <linux-kernel@vger.kernel.org>
>> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
>> CC: Andrew Victor <linux@maxim.org.za>
>> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Yes:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Daniel, do you want to take it?

Yep.

>> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
>> ---
>>   drivers/clocksource/timer-atmel-pit.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
>> index b5b4d45..c0304ff 100644
>> --- a/drivers/clocksource/timer-atmel-pit.c
>> +++ b/drivers/clocksource/timer-atmel-pit.c
>> @@ -61,12 +61,12 @@ static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clk
>>
>>   static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
>>   {
>> -	return __raw_readl(base + reg_offset);
>> +	return readl_relaxed(base + reg_offset);
>>   }
>>
>>   static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
>>   {
>> -	__raw_writel(value, base + reg_offset);
>> +	writel_relaxed(value, base + reg_offset);
>>   }
>>
>>   /*
>>
>
>


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

[PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Ben Dooks]

Change the __raw read and write to use readl/writel_relaxed to make the
code endian agnostic.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Daniel Lezcano <daniel.lezcano@linaro.org>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Linux Kernel <linux-kernel@vger.kernel.org>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
---
 drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
 1 file changed, 37 insertions(+), 29 deletions(-)

diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 8bdbc45..0f819dd3 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -41,6 +41,14 @@
 
 static void __iomem *tcaddr;
 
+#ifdef CONFIG_AVR32
+#define tcb_readl	__raw_readl
+#define tcb_writel	__raw_writel
+#else
+#define tcb_readl	readl_relaxed
+#define tcb_writel	writel_relaxed
+#endif
+
 static cycle_t tc_get_cycles(struct clocksource *cs)
 {
 	unsigned long	flags;
@@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
 	raw_local_irq_save(flags);
 	do {
-		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
+		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
 
 	raw_local_irq_restore(flags);
 	return (upper << 16) | lower;
@@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
 static cycle_t tc_get_cycles32(struct clocksource *cs)
 {
-	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
 }
 
 static struct clocksource clksrc = {
@@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
 	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
 			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
-		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 		clk_disable(tcd->clk);
 	}
 
@@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 		clk_enable(tcd->clk);
 
 		/* slow clock, count up to RC, then irq and restart */
-		__raw_writel(timer_clock
+		tcb_writel(timer_clock
 				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 
 		/* Enable clock and interrupts on RC compare */
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
 		/* go go gadget! */
-		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 				regs + ATMEL_TC_REG(2, CCR));
 		break;
 
@@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 		clk_enable(tcd->clk);
 
 		/* slow clock, count up to RC, then irq and stop */
-		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
+		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
 				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
 		/* set_next_event() configures and starts the timer */
 		break;
@@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 {
-	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 
 	/* go go gadget! */
-	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 			tcaddr + ATMEL_TC_REG(2, CCR));
 	return 0;
 }
@@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
 	struct tc_clkevt_device	*dev = handle;
 	unsigned int		sr;
 
-	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
 	if (sr & ATMEL_TC_CPCS) {
 		dev->clkevt.event_handler(&dev->clkevt);
 		return IRQ_HANDLED;
@@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
 	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP		/* free-run */
 			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
 			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
 			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
 	/* channel 1:  waveform mode, input TIOA0 */
-	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
+	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP,		/* free-run */
 			tcaddr + ATMEL_TC_REG(1, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 
 	/* chain channel 0 to channel 1*/
-	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
 	/* channel 0:  waveform mode, input mclk/8 */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP,		/* free-run */
 			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
 	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static int __init tcb_clksrc_init(void)
-- 
2.1.4

[PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Ben Dooks]

Change the __raw read and write to use readl/writel_relaxed to make the
code endian agnostic.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Daniel Lezcano <daniel.lezcano@linaro.org>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Linux Kernel <linux-kernel@vger.kernel.org>
CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
---
 drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
 1 file changed, 37 insertions(+), 29 deletions(-)

diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 8bdbc45..0f819dd3 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -41,6 +41,14 @@
 
 static void __iomem *tcaddr;
 
+#ifdef CONFIG_AVR32
+#define tcb_readl	__raw_readl
+#define tcb_writel	__raw_writel
+#else
+#define tcb_readl	readl_relaxed
+#define tcb_writel	writel_relaxed
+#endif
+
 static cycle_t tc_get_cycles(struct clocksource *cs)
 {
 	unsigned long	flags;
@@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
 	raw_local_irq_save(flags);
 	do {
-		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
+		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
 
 	raw_local_irq_restore(flags);
 	return (upper << 16) | lower;
@@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
 
 static cycle_t tc_get_cycles32(struct clocksource *cs)
 {
-	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
 }
 
 static struct clocksource clksrc = {
@@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
 	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
 			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
-		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 		clk_disable(tcd->clk);
 	}
 
@@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 		clk_enable(tcd->clk);
 
 		/* slow clock, count up to RC, then irq and restart */
-		__raw_writel(timer_clock
+		tcb_writel(timer_clock
 				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 
 		/* Enable clock and interrupts on RC compare */
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
 		/* go go gadget! */
-		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 				regs + ATMEL_TC_REG(2, CCR));
 		break;
 
@@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 		clk_enable(tcd->clk);
 
 		/* slow clock, count up to RC, then irq and stop */
-		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
+		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
 				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 				regs + ATMEL_TC_REG(2, CMR));
-		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
 		/* set_next_event() configures and starts the timer */
 		break;
@@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
 
 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 {
-	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
 
 	/* go go gadget! */
-	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 			tcaddr + ATMEL_TC_REG(2, CCR));
 	return 0;
 }
@@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
 	struct tc_clkevt_device	*dev = handle;
 	unsigned int		sr;
 
-	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
 	if (sr & ATMEL_TC_CPCS) {
 		dev->clkevt.event_handler(&dev->clkevt);
 		return IRQ_HANDLED;
@@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
 	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP		/* free-run */
 			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
 			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
 			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
 	/* channel 1:  waveform mode, input TIOA0 */
-	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
+	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP,		/* free-run */
 			tcaddr + ATMEL_TC_REG(1, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 
 	/* chain channel 0 to channel 1*/
-	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
 	/* channel 0:  waveform mode, input mclk/8 */
-	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
+	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
 			| ATMEL_TC_WAVE
 			| ATMEL_TC_WAVESEL_UP,		/* free-run */
 			tcaddr + ATMEL_TC_REG(0, CMR));
-	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
-	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
+	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
 	/* then reset all the timers */
-	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static int __init tcb_clksrc_init(void)
-- 
2.1.4

Re: [PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Daniel Lezcano]

On 03/18/2015 04:53 PM, Ben Dooks wrote:
> Change the __raw read and write to use readl/writel_relaxed to make the
> code endian agnostic.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Nicolas,

what about this one ? Do you ack it ?

Thanks

   -- Daniel

> --
> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Linux Kernel <linux-kernel@vger.kernel.org>
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>   drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
>   1 file changed, 37 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
> index 8bdbc45..0f819dd3 100644
> --- a/drivers/clocksource/tcb_clksrc.c
> +++ b/drivers/clocksource/tcb_clksrc.c
> @@ -41,6 +41,14 @@
>
>   static void __iomem *tcaddr;
>
> +#ifdef CONFIG_AVR32
> +#define tcb_readl	__raw_readl
> +#define tcb_writel	__raw_writel
> +#else
> +#define tcb_readl	readl_relaxed
> +#define tcb_writel	writel_relaxed
> +#endif
> +
>   static cycle_t tc_get_cycles(struct clocksource *cs)
>   {
>   	unsigned long	flags;
> @@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>
>   	raw_local_irq_save(flags);
>   	do {
> -		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
> -		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
> -	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
> +		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
> +		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
> +	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>
>   	raw_local_irq_restore(flags);
>   	return (upper << 16) | lower;
> @@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>
>   static cycle_t tc_get_cycles32(struct clocksource *cs)
>   {
> -	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
> +	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>   }
>
>   static struct clocksource clksrc = {
> @@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>
>   	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
>   			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
> -		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
> -		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
> +		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
> +		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>   		clk_disable(tcd->clk);
>   	}
>
> @@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>   		clk_enable(tcd->clk);
>
>   		/* slow clock, count up to RC, then irq and restart */
> -		__raw_writel(timer_clock
> +		tcb_writel(timer_clock
>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>   				regs + ATMEL_TC_REG(2, CMR));
> -		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
> +		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>
>   		/* Enable clock and interrupts on RC compare */
> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>
>   		/* go go gadget! */
> -		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
> +		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>   				regs + ATMEL_TC_REG(2, CCR));
>   		break;
>
> @@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>   		clk_enable(tcd->clk);
>
>   		/* slow clock, count up to RC, then irq and stop */
> -		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
> +		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>   				regs + ATMEL_TC_REG(2, CMR));
> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>
>   		/* set_next_event() configures and starts the timer */
>   		break;
> @@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>
>   static int tc_next_event(unsigned long delta, struct clock_event_device *d)
>   {
> -	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
> +	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>
>   	/* go go gadget! */
> -	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
> +	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>   			tcaddr + ATMEL_TC_REG(2, CCR));
>   	return 0;
>   }
> @@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
>   	struct tc_clkevt_device	*dev = handle;
>   	unsigned int		sr;
>
> -	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
> +	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
>   	if (sr & ATMEL_TC_CPCS) {
>   		dev->clkevt.event_handler(&dev->clkevt);
>   		return IRQ_HANDLED;
> @@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
>   static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
>   {
>   	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP		/* free-run */
>   			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
>   			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
>   			tcaddr + ATMEL_TC_REG(0, CMR));
> -	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
> -	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
> +	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
> +	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>
>   	/* channel 1:  waveform mode, input TIOA0 */
> -	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
> +	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>   			tcaddr + ATMEL_TC_REG(1, CMR));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>
>   	/* chain channel 0 to channel 1*/
> -	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
> +	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>   	/* then reset all the timers */
> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>   }
>
>   static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
>   {
>   	/* channel 0:  waveform mode, input mclk/8 */
> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>   			tcaddr + ATMEL_TC_REG(0, CMR));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>
>   	/* then reset all the timers */
> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>   }
>
>   static int __init tcb_clksrc_init(void)
>


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[PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Daniel Lezcano]

On 03/18/2015 04:53 PM, Ben Dooks wrote:
> Change the __raw read and write to use readl/writel_relaxed to make the
> code endian agnostic.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Nicolas,

what about this one ? Do you ack it ?

Thanks

   -- Daniel

> --
> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Linux Kernel <linux-kernel@vger.kernel.org>
> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>   drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
>   1 file changed, 37 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
> index 8bdbc45..0f819dd3 100644
> --- a/drivers/clocksource/tcb_clksrc.c
> +++ b/drivers/clocksource/tcb_clksrc.c
> @@ -41,6 +41,14 @@
>
>   static void __iomem *tcaddr;
>
> +#ifdef CONFIG_AVR32
> +#define tcb_readl	__raw_readl
> +#define tcb_writel	__raw_writel
> +#else
> +#define tcb_readl	readl_relaxed
> +#define tcb_writel	writel_relaxed
> +#endif
> +
>   static cycle_t tc_get_cycles(struct clocksource *cs)
>   {
>   	unsigned long	flags;
> @@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>
>   	raw_local_irq_save(flags);
>   	do {
> -		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
> -		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
> -	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
> +		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
> +		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
> +	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>
>   	raw_local_irq_restore(flags);
>   	return (upper << 16) | lower;
> @@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>
>   static cycle_t tc_get_cycles32(struct clocksource *cs)
>   {
> -	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
> +	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>   }
>
>   static struct clocksource clksrc = {
> @@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>
>   	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
>   			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
> -		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
> -		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
> +		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
> +		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>   		clk_disable(tcd->clk);
>   	}
>
> @@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>   		clk_enable(tcd->clk);
>
>   		/* slow clock, count up to RC, then irq and restart */
> -		__raw_writel(timer_clock
> +		tcb_writel(timer_clock
>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>   				regs + ATMEL_TC_REG(2, CMR));
> -		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
> +		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>
>   		/* Enable clock and interrupts on RC compare */
> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>
>   		/* go go gadget! */
> -		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
> +		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>   				regs + ATMEL_TC_REG(2, CCR));
>   		break;
>
> @@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>   		clk_enable(tcd->clk);
>
>   		/* slow clock, count up to RC, then irq and stop */
> -		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
> +		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>   				regs + ATMEL_TC_REG(2, CMR));
> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>
>   		/* set_next_event() configures and starts the timer */
>   		break;
> @@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>
>   static int tc_next_event(unsigned long delta, struct clock_event_device *d)
>   {
> -	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
> +	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>
>   	/* go go gadget! */
> -	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
> +	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>   			tcaddr + ATMEL_TC_REG(2, CCR));
>   	return 0;
>   }
> @@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
>   	struct tc_clkevt_device	*dev = handle;
>   	unsigned int		sr;
>
> -	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
> +	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
>   	if (sr & ATMEL_TC_CPCS) {
>   		dev->clkevt.event_handler(&dev->clkevt);
>   		return IRQ_HANDLED;
> @@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
>   static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
>   {
>   	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP		/* free-run */
>   			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
>   			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
>   			tcaddr + ATMEL_TC_REG(0, CMR));
> -	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
> -	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
> +	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
> +	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>
>   	/* channel 1:  waveform mode, input TIOA0 */
> -	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
> +	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>   			tcaddr + ATMEL_TC_REG(1, CMR));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>
>   	/* chain channel 0 to channel 1*/
> -	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
> +	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>   	/* then reset all the timers */
> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>   }
>
>   static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
>   {
>   	/* channel 0:  waveform mode, input mclk/8 */
> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>   			| ATMEL_TC_WAVE
>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>   			tcaddr + ATMEL_TC_REG(0, CMR));
> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>
>   	/* then reset all the timers */
> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>   }
>
>   static int __init tcb_clksrc_init(void)
>


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Re: [PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Nicolas Ferre]

Le 26/03/2015 10:55, Daniel Lezcano a écrit :
> On 03/18/2015 04:53 PM, Ben Dooks wrote:
>> Change the __raw read and write to use readl/writel_relaxed to make the
>> code endian agnostic.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Nicolas,
> 
> what about this one ? Do you ack it ?

Yes:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

We were discussing about having a common macro for this... But we will
think more about it later.

So, let's go for it.

Bye,


>> --
>> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
>> CC: Thomas Gleixner <tglx@linutronix.de>
>> CC: Linux Kernel <linux-kernel@vger.kernel.org>
>> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
>> CC: Andrew Victor <linux@maxim.org.za>
>> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
>> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
>> ---
>>   drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
>>   1 file changed, 37 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
>> index 8bdbc45..0f819dd3 100644
>> --- a/drivers/clocksource/tcb_clksrc.c
>> +++ b/drivers/clocksource/tcb_clksrc.c
>> @@ -41,6 +41,14 @@
>>
>>   static void __iomem *tcaddr;
>>
>> +#ifdef CONFIG_AVR32
>> +#define tcb_readl	__raw_readl
>> +#define tcb_writel	__raw_writel
>> +#else
>> +#define tcb_readl	readl_relaxed
>> +#define tcb_writel	writel_relaxed
>> +#endif
>> +
>>   static cycle_t tc_get_cycles(struct clocksource *cs)
>>   {
>>   	unsigned long	flags;
>> @@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>>
>>   	raw_local_irq_save(flags);
>>   	do {
>> -		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
>> -		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> -	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>> +		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
>> +		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> +	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>>
>>   	raw_local_irq_restore(flags);
>>   	return (upper << 16) | lower;
>> @@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>>
>>   static cycle_t tc_get_cycles32(struct clocksource *cs)
>>   {
>> -	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> +	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>>   }
>>
>>   static struct clocksource clksrc = {
>> @@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>
>>   	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
>>   			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
>> -		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
>> -		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>> +		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
>> +		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>>   		clk_disable(tcd->clk);
>>   	}
>>
>> @@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>   		clk_enable(tcd->clk);
>>
>>   		/* slow clock, count up to RC, then irq and restart */
>> -		__raw_writel(timer_clock
>> +		tcb_writel(timer_clock
>>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>>   				regs + ATMEL_TC_REG(2, CMR));
>> -		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>> +		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>>
>>   		/* Enable clock and interrupts on RC compare */
>> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>>
>>   		/* go go gadget! */
>> -		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>> +		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>>   				regs + ATMEL_TC_REG(2, CCR));
>>   		break;
>>
>> @@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>   		clk_enable(tcd->clk);
>>
>>   		/* slow clock, count up to RC, then irq and stop */
>> -		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
>> +		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
>>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>>   				regs + ATMEL_TC_REG(2, CMR));
>> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>>
>>   		/* set_next_event() configures and starts the timer */
>>   		break;
>> @@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>
>>   static int tc_next_event(unsigned long delta, struct clock_event_device *d)
>>   {
>> -	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>> +	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>>
>>   	/* go go gadget! */
>> -	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>> +	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>>   			tcaddr + ATMEL_TC_REG(2, CCR));
>>   	return 0;
>>   }
>> @@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
>>   	struct tc_clkevt_device	*dev = handle;
>>   	unsigned int		sr;
>>
>> -	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
>> +	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
>>   	if (sr & ATMEL_TC_CPCS) {
>>   		dev->clkevt.event_handler(&dev->clkevt);
>>   		return IRQ_HANDLED;
>> @@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
>>   static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
>>   {
>>   	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
>> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
>> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP		/* free-run */
>>   			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
>>   			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
>>   			tcaddr + ATMEL_TC_REG(0, CMR));
>> -	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
>> -	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>> +	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
>> +	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>>
>>   	/* channel 1:  waveform mode, input TIOA0 */
>> -	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>> +	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>>   			tcaddr + ATMEL_TC_REG(1, CMR));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>>
>>   	/* chain channel 0 to channel 1*/
>> -	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>> +	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>>   	/* then reset all the timers */
>> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>>   }
>>
>>   static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
>>   {
>>   	/* channel 0:  waveform mode, input mclk/8 */
>> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
>> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>>   			tcaddr + ATMEL_TC_REG(0, CMR));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>>
>>   	/* then reset all the timers */
>> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>>   }
>>
>>   static int __init tcb_clksrc_init(void)
>>
> 
> 


-- 
Nicolas Ferre

[PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Nicolas Ferre]

Le 26/03/2015 10:55, Daniel Lezcano a ?crit :
> On 03/18/2015 04:53 PM, Ben Dooks wrote:
>> Change the __raw read and write to use readl/writel_relaxed to make the
>> code endian agnostic.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Nicolas,
> 
> what about this one ? Do you ack it ?

Yes:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

We were discussing about having a common macro for this... But we will
think more about it later.

So, let's go for it.

Bye,


>> --
>> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
>> CC: Thomas Gleixner <tglx@linutronix.de>
>> CC: Linux Kernel <linux-kernel@vger.kernel.org>
>> CC: Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
>> CC: Andrew Victor <linux@maxim.org.za>
>> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
>> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
>> ---
>>   drivers/clocksource/tcb_clksrc.c | 66 ++++++++++++++++++++++------------------
>>   1 file changed, 37 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
>> index 8bdbc45..0f819dd3 100644
>> --- a/drivers/clocksource/tcb_clksrc.c
>> +++ b/drivers/clocksource/tcb_clksrc.c
>> @@ -41,6 +41,14 @@
>>
>>   static void __iomem *tcaddr;
>>
>> +#ifdef CONFIG_AVR32
>> +#define tcb_readl	__raw_readl
>> +#define tcb_writel	__raw_writel
>> +#else
>> +#define tcb_readl	readl_relaxed
>> +#define tcb_writel	writel_relaxed
>> +#endif
>> +
>>   static cycle_t tc_get_cycles(struct clocksource *cs)
>>   {
>>   	unsigned long	flags;
>> @@ -48,9 +56,9 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>>
>>   	raw_local_irq_save(flags);
>>   	do {
>> -		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
>> -		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> -	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>> +		upper = tcb_readl(tcaddr + ATMEL_TC_REG(1, CV));
>> +		lower = tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> +	} while (upper != tcb_readl(tcaddr + ATMEL_TC_REG(1, CV)));
>>
>>   	raw_local_irq_restore(flags);
>>   	return (upper << 16) | lower;
>> @@ -58,7 +66,7 @@ static cycle_t tc_get_cycles(struct clocksource *cs)
>>
>>   static cycle_t tc_get_cycles32(struct clocksource *cs)
>>   {
>> -	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> +	return tcb_readl(tcaddr + ATMEL_TC_REG(0, CV));
>>   }
>>
>>   static struct clocksource clksrc = {
>> @@ -98,8 +106,8 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>
>>   	if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
>>   			|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
>> -		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
>> -		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>> +		tcb_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
>> +		tcb_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
>>   		clk_disable(tcd->clk);
>>   	}
>>
>> @@ -112,16 +120,16 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>   		clk_enable(tcd->clk);
>>
>>   		/* slow clock, count up to RC, then irq and restart */
>> -		__raw_writel(timer_clock
>> +		tcb_writel(timer_clock
>>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>>   				regs + ATMEL_TC_REG(2, CMR));
>> -		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>> +		tcb_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
>>
>>   		/* Enable clock and interrupts on RC compare */
>> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>>
>>   		/* go go gadget! */
>> -		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>> +		tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>>   				regs + ATMEL_TC_REG(2, CCR));
>>   		break;
>>
>> @@ -129,10 +137,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>   		clk_enable(tcd->clk);
>>
>>   		/* slow clock, count up to RC, then irq and stop */
>> -		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
>> +		tcb_writel(timer_clock | ATMEL_TC_CPCSTOP
>>   				| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
>>   				regs + ATMEL_TC_REG(2, CMR));
>> -		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>> +		tcb_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
>>
>>   		/* set_next_event() configures and starts the timer */
>>   		break;
>> @@ -144,10 +152,10 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
>>
>>   static int tc_next_event(unsigned long delta, struct clock_event_device *d)
>>   {
>> -	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>> +	tcb_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
>>
>>   	/* go go gadget! */
>> -	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>> +	tcb_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
>>   			tcaddr + ATMEL_TC_REG(2, CCR));
>>   	return 0;
>>   }
>> @@ -169,7 +177,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
>>   	struct tc_clkevt_device	*dev = handle;
>>   	unsigned int		sr;
>>
>> -	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
>> +	sr = tcb_readl(dev->regs + ATMEL_TC_REG(2, SR));
>>   	if (sr & ATMEL_TC_CPCS) {
>>   		dev->clkevt.event_handler(&dev->clkevt);
>>   		return IRQ_HANDLED;
>> @@ -221,43 +229,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
>>   static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
>>   {
>>   	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
>> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
>> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP		/* free-run */
>>   			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
>>   			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
>>   			tcaddr + ATMEL_TC_REG(0, CMR));
>> -	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
>> -	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>> +	tcb_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
>> +	tcb_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>>
>>   	/* channel 1:  waveform mode, input TIOA0 */
>> -	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>> +	tcb_writel(ATMEL_TC_XC1			/* input: TIOA0 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>>   			tcaddr + ATMEL_TC_REG(1, CMR));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
>>
>>   	/* chain channel 0 to channel 1*/
>> -	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>> +	tcb_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
>>   	/* then reset all the timers */
>> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>>   }
>>
>>   static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
>>   {
>>   	/* channel 0:  waveform mode, input mclk/8 */
>> -	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
>> +	tcb_writel(mck_divisor_idx			/* likely divide-by-8 */
>>   			| ATMEL_TC_WAVE
>>   			| ATMEL_TC_WAVESEL_UP,		/* free-run */
>>   			tcaddr + ATMEL_TC_REG(0, CMR));
>> -	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> -	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>> +	tcb_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
>> +	tcb_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
>>
>>   	/* then reset all the timers */
>> -	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>> +	tcb_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
>>   }
>>
>>   static int __init tcb_clksrc_init(void)
>>
> 
> 


-- 
Nicolas Ferre

Re: [PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Ben Dooks]

On 26/03/15 11:08, Nicolas Ferre wrote:
> Le 26/03/2015 10:55, Daniel Lezcano a écrit :
>> On 03/18/2015 04:53 PM, Ben Dooks wrote:
>>> Change the __raw read and write to use readl/writel_relaxed to make the
>>> code endian agnostic.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> Nicolas,
>>
>> what about this one ? Do you ack it ?
> 
> Yes:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> We were discussing about having a common macro for this... But we will
> think more about it later.
> 
> So, let's go for it.

I will be sending out a series for this soon, I think I've got all
the items sorted.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH 07/13] clocksource: tcb_clksrc: make IO endian agnostic

[Ben Dooks]

On 26/03/15 11:08, Nicolas Ferre wrote:
> Le 26/03/2015 10:55, Daniel Lezcano a ?crit :
>> On 03/18/2015 04:53 PM, Ben Dooks wrote:
>>> Change the __raw read and write to use readl/writel_relaxed to make the
>>> code endian agnostic.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> Nicolas,
>>
>> what about this one ? Do you ack it ?
> 
> Yes:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> We were discussing about having a common macro for this... But we will
> think more about it later.
> 
> So, let's go for it.

I will be sending out a series for this soon, I think I've got all
the items sorted.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH 08/13] rtc: at91rm9200: make IO endian agnostic

[Ben Dooks]

Change the __raw IO calls to readl/write_relaxed which makes the driver
endian agnostic to run properly on big endian systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Alessandro Zummo <a.zummo@towertech.it>
CC: rtc-linux at googlegroups.com
CC: linux-arm-kernel at lists.infradead.org
CC: Andrew Victor <linux@maxim.org.za>
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
---
 drivers/rtc/rtc-at91rm9200.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index b4f7744..4106abc 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -37,9 +37,9 @@
 #include "rtc-at91rm9200.h"
 
 #define at91_rtc_read(field) \
-	__raw_readl(at91_rtc_regs + field)
+	readl_relaxed(at91_rtc_regs + field)
 #define at91_rtc_write(field, val) \
-	__raw_writel((val), at91_rtc_regs + field)
+	writel_relaxed((val), at91_rtc_regs + field)
 
 #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
 
-- 
2.1.4

[rtc-linux] [PATCH 08/13] rtc: at91rm9200: make IO endian agnostic

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:53 Wed 18 Mar     , Ben Dooks wrote:
> Change the __raw IO calls to readl/write_relaxed which makes the driver
> endian agnostic to run properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Alessandro Zummo <a.zummo@towertech.it>
> CC: rtc-linux at googlegroups.com
> CC: linux-arm-kernel at lists.infradead.org
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>  drivers/rtc/rtc-at91rm9200.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
> index b4f7744..4106abc 100644
> --- a/drivers/rtc/rtc-at91rm9200.c
> +++ b/drivers/rtc/rtc-at91rm9200.c
> @@ -37,9 +37,9 @@
>  #include "rtc-at91rm9200.h"
>  
>  #define at91_rtc_read(field) \
> -	__raw_readl(at91_rtc_regs + field)
> +	readl_relaxed(at91_rtc_regs + field)
>  #define at91_rtc_write(field, val) \
> -	__raw_writel((val), at91_rtc_regs + field)
> +	writel_relaxed((val), at91_rtc_regs + field)

I'm not against it but the SoC using it are Little only

Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Best Regards,
J.
>  
>  #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
>  
> -- 
> 2.1.4
> 
> -- 
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[rtc-linux] [PATCH 08/13] rtc: at91rm9200: make IO endian agnostic

[Ben Dooks]

On 19/03/15 09:02, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:53 Wed 18 Mar     , Ben Dooks wrote:
>> Change the __raw IO calls to readl/write_relaxed which makes the driver
>> endian agnostic to run properly on big endian systems.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> --
>> CC: Alessandro Zummo <a.zummo@towertech.it>
>> CC: rtc-linux at googlegroups.com
>> CC: linux-arm-kernel at lists.infradead.org
>> CC: Andrew Victor <linux@maxim.org.za>
>> CC: Nicolas Ferre <nicolas.ferre@atmel.com>
>> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
>> ---
>>  drivers/rtc/rtc-at91rm9200.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
>> index b4f7744..4106abc 100644
>> --- a/drivers/rtc/rtc-at91rm9200.c
>> +++ b/drivers/rtc/rtc-at91rm9200.c
>> @@ -37,9 +37,9 @@
>>  #include "rtc-at91rm9200.h"
>>  
>>  #define at91_rtc_read(field) \
>> -	__raw_readl(at91_rtc_regs + field)
>> +	readl_relaxed(at91_rtc_regs + field)
>>  #define at91_rtc_write(field, val) \
>> -	__raw_writel((val), at91_rtc_regs + field)
>> +	writel_relaxed((val), at91_rtc_regs + field)
> 
> I'm not against it but the SoC using it are Little only

It is used by the SAMA5D36 which is Cortex-A5 with big endian
support.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH 08/13] rtc: at91rm9200: make IO endian agnostic

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a ?crit :
> Change the __raw IO calls to readl/write_relaxed which makes the driver
> endian agnostic to run properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Alessandro Zummo <a.zummo@towertech.it>
> CC: rtc-linux at googlegroups.com
> CC: linux-arm-kernel at lists.infradead.org
> CC: Andrew Victor <linux@maxim.org.za>
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Yes, that seems neat:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks!

> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> ---
>  drivers/rtc/rtc-at91rm9200.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
> index b4f7744..4106abc 100644
> --- a/drivers/rtc/rtc-at91rm9200.c
> +++ b/drivers/rtc/rtc-at91rm9200.c
> @@ -37,9 +37,9 @@
>  #include "rtc-at91rm9200.h"
>  
>  #define at91_rtc_read(field) \
> -	__raw_readl(at91_rtc_regs + field)
> +	readl_relaxed(at91_rtc_regs + field)
>  #define at91_rtc_write(field, val) \
> -	__raw_writel((val), at91_rtc_regs + field)
> +	writel_relaxed((val), at91_rtc_regs + field)
>  
>  #define AT91_RTC_EPOCH		1900UL	/* just like arch/arm/common/rtctime.c */
>  
> 


-- 
Nicolas Ferre

[PATCH 09/13] spi: atmel: use endian agnostic IO

[Ben Dooks]

Use the endian agnositc IO functions instead of the __raw ones for when
the driver is in use on big-endian systems.

Signed-off-by: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>
--
CC: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org> (supporter:ATMEL SPI DRIVER)
CC: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> (maintainer:SPI SUBSYSTEM)
CC: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:SPI SUBSYSTEM)
---
 drivers/spi/spi-atmel.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 06de340..a2f40b1 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -180,11 +180,17 @@
 	  | SPI_BF(name, value))
 
 /* Register access macros */
+#ifdef CONFIG_AVR32
 #define spi_readl(port, reg) \
 	__raw_readl((port)->regs + SPI_##reg)
 #define spi_writel(port, reg, value) \
 	__raw_writel((value), (port)->regs + SPI_##reg)
-
+#else
+#define spi_readl(port, reg) \
+	readl_relaxed((port)->regs + SPI_##reg)
+#define spi_writel(port, reg, value) \
+	writel_relaxed((value), (port)->regs + SPI_##reg)
+#endif
 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  * cache operations; better heuristics consider wordsize and bitrate.
  */
-- 
2.1.4

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[PATCH 09/13] spi: atmel: use endian agnostic IO

[Ben Dooks]

Use the endian agnositc IO functions instead of the __raw ones for when
the driver is in use on big-endian systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Nicolas Ferre <nicolas.ferre@atmel.com> (supporter:ATMEL SPI DRIVER)
CC: Mark Brown <broonie@kernel.org> (maintainer:SPI SUBSYSTEM)
CC: linux-spi at vger.kernel.org (open list:SPI SUBSYSTEM)
---
 drivers/spi/spi-atmel.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 06de340..a2f40b1 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -180,11 +180,17 @@
 	  | SPI_BF(name, value))
 
 /* Register access macros */
+#ifdef CONFIG_AVR32
 #define spi_readl(port, reg) \
 	__raw_readl((port)->regs + SPI_##reg)
 #define spi_writel(port, reg, value) \
 	__raw_writel((value), (port)->regs + SPI_##reg)
-
+#else
+#define spi_readl(port, reg) \
+	readl_relaxed((port)->regs + SPI_##reg)
+#define spi_writel(port, reg, value) \
+	writel_relaxed((value), (port)->regs + SPI_##reg)
+#endif
 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  * cache operations; better heuristics consider wordsize and bitrate.
  */
-- 
2.1.4

Re: [PATCH 09/13] spi: atmel: use endian agnostic IO

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 408 bytes --]

On Wed, Mar 18, 2015 at 03:53:08PM +0000, Ben Dooks wrote:
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>

I'm not CCed on either the cover letter or the rest of the series: are
there any dependencies here or is it safe to apply this by itself?

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[PATCH 09/13] spi: atmel: use endian agnostic IO

[Mark Brown]

On Wed, Mar 18, 2015 at 03:53:08PM +0000, Ben Dooks wrote:
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

I'm not CCed on either the cover letter or the rest of the series: are
there any dependencies here or is it safe to apply this by itself?
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Re: [PATCH 09/13] spi: atmel: use endian agnostic IO

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a écrit :
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>

Looks good to me:
Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Mark,
There is no dependency on the series, so you can take this one right now.

Bye.

> --
> CC: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org> (supporter:ATMEL SPI DRIVER)
> CC: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> (maintainer:SPI SUBSYSTEM)
> CC: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:SPI SUBSYSTEM)
> ---
>  drivers/spi/spi-atmel.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 06de340..a2f40b1 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -180,11 +180,17 @@
>  	  | SPI_BF(name, value))
>  
>  /* Register access macros */
> +#ifdef CONFIG_AVR32
>  #define spi_readl(port, reg) \
>  	__raw_readl((port)->regs + SPI_##reg)
>  #define spi_writel(port, reg, value) \
>  	__raw_writel((value), (port)->regs + SPI_##reg)
> -
> +#else
> +#define spi_readl(port, reg) \
> +	readl_relaxed((port)->regs + SPI_##reg)
> +#define spi_writel(port, reg, value) \
> +	writel_relaxed((value), (port)->regs + SPI_##reg)
> +#endif
>  /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
>   * cache operations; better heuristics consider wordsize and bitrate.
>   */
> 


-- 
Nicolas Ferre
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[PATCH 09/13] spi: atmel: use endian agnostic IO

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a ?crit :
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Looks good to me:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Mark,
There is no dependency on the series, so you can take this one right now.

Bye.

> --
> CC: Nicolas Ferre <nicolas.ferre@atmel.com> (supporter:ATMEL SPI DRIVER)
> CC: Mark Brown <broonie@kernel.org> (maintainer:SPI SUBSYSTEM)
> CC: linux-spi at vger.kernel.org (open list:SPI SUBSYSTEM)
> ---
>  drivers/spi/spi-atmel.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 06de340..a2f40b1 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -180,11 +180,17 @@
>  	  | SPI_BF(name, value))
>  
>  /* Register access macros */
> +#ifdef CONFIG_AVR32
>  #define spi_readl(port, reg) \
>  	__raw_readl((port)->regs + SPI_##reg)
>  #define spi_writel(port, reg, value) \
>  	__raw_writel((value), (port)->regs + SPI_##reg)
> -
> +#else
> +#define spi_readl(port, reg) \
> +	readl_relaxed((port)->regs + SPI_##reg)
> +#define spi_writel(port, reg, value) \
> +	writel_relaxed((value), (port)->regs + SPI_##reg)
> +#endif
>  /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
>   * cache operations; better heuristics consider wordsize and bitrate.
>   */
> 


-- 
Nicolas Ferre

Re: [PATCH 09/13] spi: atmel: use endian agnostic IO

[Mark Brown]

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On Wed, Mar 18, 2015 at 03:53:08PM +0000, Ben Dooks wrote:
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>
> --
> CC: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org> (supporter:ATMEL SPI DRIVER)
> CC: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> (maintainer:SPI SUBSYSTEM)
> CC: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:SPI SUBSYSTEM)

Applied, thanks.  If you don't want things to go into the message then
they should be after --- not --.

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[PATCH 09/13] spi: atmel: use endian agnostic IO

[Mark Brown]

On Wed, Mar 18, 2015 at 03:53:08PM +0000, Ben Dooks wrote:
> Use the endian agnositc IO functions instead of the __raw ones for when
> the driver is in use on big-endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Nicolas Ferre <nicolas.ferre@atmel.com> (supporter:ATMEL SPI DRIVER)
> CC: Mark Brown <broonie@kernel.org> (maintainer:SPI SUBSYSTEM)
> CC: linux-spi at vger.kernel.org (open list:SPI SUBSYSTEM)

Applied, thanks.  If you don't want things to go into the message then
they should be after --- not --.
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[PATCH 10/13] usb: gadget: atmel_usba: use endian agnostic IO on ARM

[Ben Dooks]

Change from using the __raw IO accesors to the endian agnostic versions
of readl/writel_relaxed when not on AVR32. This fixes issues with running
big endian on ARMv7.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Felipe Balbi <balbi@ti.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: linux-usb at vger.kernel.org
---
 drivers/usb/gadget/udc/atmel_usba_udc.c |  4 ++--
 drivers/usb/gadget/udc/atmel_usba_udc.h | 22 ++++++++++++++++------
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
index d79cb35..be2f503 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
@@ -152,7 +152,7 @@ static int regs_dbg_open(struct inode *inode, struct file *file)
 
 	spin_lock_irq(&udc->lock);
 	for (i = 0; i < inode->i_size / 4; i++)
-		data[i] = __raw_readl(udc->regs + i * 4);
+		data[i] = usba_io_readl(udc->regs + i * 4);
 	spin_unlock_irq(&udc->lock);
 
 	file->private_data = data;
@@ -1249,7 +1249,7 @@ static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
 		if (crq->wLength != cpu_to_le16(sizeof(status)))
 			goto stall;
 		ep->state = DATA_STAGE_IN;
-		__raw_writew(status, ep->fifo);
+		usba_io_writew(status, ep->fifo);
 		usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
 		break;
 	}
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.h b/drivers/usb/gadget/udc/atmel_usba_udc.h
index 497cd18..92bd486 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.h
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.h
@@ -191,18 +191,28 @@
 	 | USBA_BF(name, value))
 
 /* Register access macros */
+#ifdef CONFIG_AVR32
+#define usba_io_readl	__raw_readl
+#define usba_io_writel	__raw_writel
+#define usba_io_writew	__raw_writew
+#else
+#define usba_io_readl	readl_relaxed
+#define usba_io_writel	writel_relaxed
+#define usba_io_writew	writew_relaxed
+#endif
+
 #define usba_readl(udc, reg)					\
-	__raw_readl((udc)->regs + USBA_##reg)
+	usba_io_readl((udc)->regs + USBA_##reg)
 #define usba_writel(udc, reg, value)				\
-	__raw_writel((value), (udc)->regs + USBA_##reg)
+	usba_io_writel((value), (udc)->regs + USBA_##reg)
 #define usba_ep_readl(ep, reg)					\
-	__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
+	usba_io_readl((ep)->ep_regs + USBA_EPT_##reg)
 #define usba_ep_writel(ep, reg, value)				\
-	__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
+	usba_io_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
 #define usba_dma_readl(ep, reg)					\
-	__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
+	usba_io_readl((ep)->dma_regs + USBA_DMA_##reg)
 #define usba_dma_writel(ep, reg, value)				\
-	__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
+	usba_io_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
 
 /* Calculate base address for a given endpoint or DMA controller */
 #define USBA_EPT_BASE(x)	(0x100 + (x) * 0x20)
-- 
2.1.4

[PATCH 10/13] usb: gadget: atmel_usba: use endian agnostic IO on ARM

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a ?crit :
> Change from using the __raw IO accesors to the endian agnostic versions
> of readl/writel_relaxed when not on AVR32. This fixes issues with running
> big endian on ARMv7.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Felipe, for the record:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks, bye.

> CC: Felipe Balbi <balbi@ti.com>
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: linux-usb at vger.kernel.org
> ---
>  drivers/usb/gadget/udc/atmel_usba_udc.c |  4 ++--
>  drivers/usb/gadget/udc/atmel_usba_udc.h | 22 ++++++++++++++++------
>  2 files changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
> index d79cb35..be2f503 100644
> --- a/drivers/usb/gadget/udc/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
> @@ -152,7 +152,7 @@ static int regs_dbg_open(struct inode *inode, struct file *file)
>  
>  	spin_lock_irq(&udc->lock);
>  	for (i = 0; i < inode->i_size / 4; i++)
> -		data[i] = __raw_readl(udc->regs + i * 4);
> +		data[i] = usba_io_readl(udc->regs + i * 4);
>  	spin_unlock_irq(&udc->lock);
>  
>  	file->private_data = data;
> @@ -1249,7 +1249,7 @@ static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
>  		if (crq->wLength != cpu_to_le16(sizeof(status)))
>  			goto stall;
>  		ep->state = DATA_STAGE_IN;
> -		__raw_writew(status, ep->fifo);
> +		usba_io_writew(status, ep->fifo);
>  		usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
>  		break;
>  	}
> diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.h b/drivers/usb/gadget/udc/atmel_usba_udc.h
> index 497cd18..92bd486 100644
> --- a/drivers/usb/gadget/udc/atmel_usba_udc.h
> +++ b/drivers/usb/gadget/udc/atmel_usba_udc.h
> @@ -191,18 +191,28 @@
>  	 | USBA_BF(name, value))
>  
>  /* Register access macros */
> +#ifdef CONFIG_AVR32
> +#define usba_io_readl	__raw_readl
> +#define usba_io_writel	__raw_writel
> +#define usba_io_writew	__raw_writew
> +#else
> +#define usba_io_readl	readl_relaxed
> +#define usba_io_writel	writel_relaxed
> +#define usba_io_writew	writew_relaxed
> +#endif
> +
>  #define usba_readl(udc, reg)					\
> -	__raw_readl((udc)->regs + USBA_##reg)
> +	usba_io_readl((udc)->regs + USBA_##reg)
>  #define usba_writel(udc, reg, value)				\
> -	__raw_writel((value), (udc)->regs + USBA_##reg)
> +	usba_io_writel((value), (udc)->regs + USBA_##reg)
>  #define usba_ep_readl(ep, reg)					\
> -	__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
> +	usba_io_readl((ep)->ep_regs + USBA_EPT_##reg)
>  #define usba_ep_writel(ep, reg, value)				\
> -	__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
> +	usba_io_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
>  #define usba_dma_readl(ep, reg)					\
> -	__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
> +	usba_io_readl((ep)->dma_regs + USBA_DMA_##reg)
>  #define usba_dma_writel(ep, reg, value)				\
> -	__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
> +	usba_io_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
>  
>  /* Calculate base address for a given endpoint or DMA controller */
>  #define USBA_EPT_BASE(x)	(0x100 + (x) * 0x20)
> 


-- 
Nicolas Ferre

[PATCH 10/13] usb: gadget: atmel_usba: use endian agnostic IO on ARM

[Felipe Balbi]

On Thu, Mar 19, 2015 at 05:46:47PM +0100, Nicolas Ferre wrote:
> Le 18/03/2015 16:53, Ben Dooks a ?crit :
> > Change from using the __raw IO accesors to the endian agnostic versions
> > of readl/writel_relaxed when not on AVR32. This fixes issues with running
> > big endian on ARMv7.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > --
> > CC: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> Felipe, for the record:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

sorry, it's already in my immutable branch :-(

-- 
balbi
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[PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Ben Dooks]

Change __raw accesors to  endian agnostic versions to allow the driver
to work properly on big endian systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Wolfgang Grandegger <wg@grandegger.com>
CC: Marc Kleine-Budde <mkl@pengutronix.de>
CC: linux-can@vger.kernel.org
CC: netdev@vger.kernel.org
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 drivers/net/can/at91_can.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index eeb4b8b..f4e40aa 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
 
 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
 {
-	return __raw_readl(priv->reg_base + reg);
+	return readl_relaxed(priv->reg_base + reg);
 }
 
 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
 		u32 value)
 {
-	__raw_writel(value, priv->reg_base + reg);
+	writel_relaxed(value, priv->reg_base + reg);
 }
 
 static inline void set_mb_mode_prio(const struct at91_priv *priv,
-- 
2.1.4

[PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Ben Dooks]

Change __raw accesors to  endian agnostic versions to allow the driver
to work properly on big endian systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Wolfgang Grandegger <wg@grandegger.com>
CC: Marc Kleine-Budde <mkl@pengutronix.de>
CC: linux-can at vger.kernel.org
CC: netdev at vger.kernel.org
CC: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 drivers/net/can/at91_can.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index eeb4b8b..f4e40aa 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
 
 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
 {
-	return __raw_readl(priv->reg_base + reg);
+	return readl_relaxed(priv->reg_base + reg);
 }
 
 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
 		u32 value)
 {
-	__raw_writel(value, priv->reg_base + reg);
+	writel_relaxed(value, priv->reg_base + reg);
 }
 
 static inline void set_mb_mode_prio(const struct at91_priv *priv,
-- 
2.1.4

Re: [PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a écrit :
> Change __raw accesors to  endian agnostic versions to allow the driver
> to work properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Wolfgang Grandegger <wg@grandegger.com>
> CC: Marc Kleine-Budde <mkl@pengutronix.de>
> CC: linux-can@vger.kernel.org
> CC: netdev@vger.kernel.org
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Sure!
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks, bye.


> ---
>  drivers/net/can/at91_can.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
> index eeb4b8b..f4e40aa 100644
> --- a/drivers/net/can/at91_can.c
> +++ b/drivers/net/can/at91_can.c
> @@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
>  
>  static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
>  {
> -	return __raw_readl(priv->reg_base + reg);
> +	return readl_relaxed(priv->reg_base + reg);
>  }
>  
>  static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
>  		u32 value)
>  {
> -	__raw_writel(value, priv->reg_base + reg);
> +	writel_relaxed(value, priv->reg_base + reg);
>  }
>  
>  static inline void set_mb_mode_prio(const struct at91_priv *priv,
> 


-- 
Nicolas Ferre

[PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a ?crit :
> Change __raw accesors to  endian agnostic versions to allow the driver
> to work properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Wolfgang Grandegger <wg@grandegger.com>
> CC: Marc Kleine-Budde <mkl@pengutronix.de>
> CC: linux-can at vger.kernel.org
> CC: netdev at vger.kernel.org
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Sure!
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks, bye.


> ---
>  drivers/net/can/at91_can.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
> index eeb4b8b..f4e40aa 100644
> --- a/drivers/net/can/at91_can.c
> +++ b/drivers/net/can/at91_can.c
> @@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
>  
>  static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
>  {
> -	return __raw_readl(priv->reg_base + reg);
> +	return readl_relaxed(priv->reg_base + reg);
>  }
>  
>  static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
>  		u32 value)
>  {
> -	__raw_writel(value, priv->reg_base + reg);
> +	writel_relaxed(value, priv->reg_base + reg);
>  }
>  
>  static inline void set_mb_mode_prio(const struct at91_priv *priv,
> 


-- 
Nicolas Ferre

Re: [PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Nicolas Ferre]

Le 18/03/2015 16:53, Ben Dooks a écrit :
> Change __raw accesors to  endian agnostic versions to allow the driver
> to work properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Wolfgang Grandegger <wg@grandegger.com>
> CC: Marc Kleine-Budde <mkl@pengutronix.de>
> CC: linux-can@vger.kernel.org
> CC: netdev@vger.kernel.org
> CC: Nicolas Ferre <nicolas.ferre@atmel.com>

Sure!
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks, bye.


> ---
>  drivers/net/can/at91_can.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
> index eeb4b8b..f4e40aa 100644
> --- a/drivers/net/can/at91_can.c
> +++ b/drivers/net/can/at91_can.c
> @@ -291,13 +291,13 @@ static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
>  
>  static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
>  {
> -	return __raw_readl(priv->reg_base + reg);
> +	return readl_relaxed(priv->reg_base + reg);
>  }
>  
>  static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
>  		u32 value)
>  {
> -	__raw_writel(value, priv->reg_base + reg);
> +	writel_relaxed(value, priv->reg_base + reg);
>  }
>  
>  static inline void set_mb_mode_prio(const struct at91_priv *priv,
> 


-- 
Nicolas Ferre

Re: [PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Marc Kleine-Budde]

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On 03/18/2015 04:53 PM, Ben Dooks wrote:
> Change __raw accesors to  endian agnostic versions to allow the driver
> to work properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

applied to can-next.

Thanks,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |



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[PATCH 11/13] can: at91_can: use endian agnostic IO accessors

[Marc Kleine-Budde]

On 03/18/2015 04:53 PM, Ben Dooks wrote:
> Change __raw accesors to  endian agnostic versions to allow the driver
> to work properly on big endian systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

applied to can-next.

Thanks,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


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[PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Dooks]

Change the __raw IO functions to endian agnostic relaxed ones to allow
the driver to function on big endian ARM systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Ludovic Desroches <ludovic.desroches@atmel.com>
CC: Chris Ball <chris@printf.net>
CC: Ulf Hansson <ulf.hansson@linaro.org>
CC: linux-mmc@vger.kernel.org
---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index c97001e..711bb53 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32
+#define atmci_readl(port,reg)			\
 	__raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)			\
+	readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)			\
+	writel_relaxed((value), (port)->regs + reg)
+#endif
 
 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 #ifdef CONFIG_AVR32
-- 
2.1.4

[PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Dooks]

Change the __raw IO functions to endian agnostic relaxed ones to allow
the driver to function on big endian ARM systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
--
CC: Ludovic Desroches <ludovic.desroches@atmel.com>
CC: Chris Ball <chris@printf.net>
CC: Ulf Hansson <ulf.hansson@linaro.org>
CC: linux-mmc at vger.kernel.org
---
 drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index c97001e..711bb53 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -135,10 +135,17 @@
 #define ATMCI_REGS_SIZE		0x100
 
 /* Register access macros */
-#define atmci_readl(port,reg)				\
+#ifdef CONFIG_AVR32
+#define atmci_readl(port,reg)			\
 	__raw_readl((port)->regs + reg)
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
+#else
+#define atmci_readl(port,reg)			\
+	readl_relaxed((port)->regs + reg)
+#define atmci_writel(port,reg,value)			\
+	writel_relaxed((value), (port)->regs + reg)
+#endif
 
 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 #ifdef CONFIG_AVR32
-- 
2.1.4

Re: [Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Hutchings]

On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc@vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE		0x100
>  
>  /* Register access macros */
> -#define atmci_readl(port,reg)				\
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)			\
>  	__raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)			\
>  	__raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)			\
> +	readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)			\
> +	writel_relaxed((value), (port)->regs + reg)
> +#endif

This pattern is repeated in a lot of drivers; is it worth defining
atmel_{read,write}l_relaxed() in a common header?

#ifdef CONFIG_AVR32

/* CPU and peripherals are both big-endian, so don't byte-swap */
#define atmel_readl_relaxed(addr)		__raw_readl(addr)
#define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)

#else

/* Peripherals are little-endian, so byte-swap if CPU isn't */
#define atmel_readl_relaxed(addr)		readl_relaxed(addr)
#define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)

#endif

Ben.

>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32

[Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Hutchings]

On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc at vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE		0x100
>  
>  /* Register access macros */
> -#define atmci_readl(port,reg)				\
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)			\
>  	__raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)			\
>  	__raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)			\
> +	readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)			\
> +	writel_relaxed((value), (port)->regs + reg)
> +#endif

This pattern is repeated in a lot of drivers; is it worth defining
atmel_{read,write}l_relaxed() in a common header?

#ifdef CONFIG_AVR32

/* CPU and peripherals are both big-endian, so don't byte-swap */
#define atmel_readl_relaxed(addr)		__raw_readl(addr)
#define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)

#else

/* Peripherals are little-endian, so byte-swap if CPU isn't */
#define atmel_readl_relaxed(addr)		readl_relaxed(addr)
#define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)

#endif

Ben.

>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32

Re: [Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Dooks]

On 19/03/15 14:22, Ben Hutchings wrote:
> On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
>> Change the __raw IO functions to endian agnostic relaxed ones to allow
>> the driver to function on big endian ARM systems.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> --
>> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
>> CC: Chris Ball <chris@printf.net>
>> CC: Ulf Hansson <ulf.hansson@linaro.org>
>> CC: linux-mmc@vger.kernel.org
>> ---
>>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
>> index c97001e..711bb53 100644
>> --- a/drivers/mmc/host/atmel-mci-regs.h
>> +++ b/drivers/mmc/host/atmel-mci-regs.h
>> @@ -135,10 +135,17 @@
>>  #define ATMCI_REGS_SIZE		0x100
>>  
>>  /* Register access macros */
>> -#define atmci_readl(port,reg)				\
>> +#ifdef CONFIG_AVR32
>> +#define atmci_readl(port,reg)			\
>>  	__raw_readl((port)->regs + reg)
>>  #define atmci_writel(port,reg,value)			\
>>  	__raw_writel((value), (port)->regs + reg)
>> +#else
>> +#define atmci_readl(port,reg)			\
>> +	readl_relaxed((port)->regs + reg)
>> +#define atmci_writel(port,reg,value)			\
>> +	writel_relaxed((value), (port)->regs + reg)
>> +#endif
> 
> This pattern is repeated in a lot of drivers; is it worth defining
> atmel_{read,write}l_relaxed() in a common header?
> 
> #ifdef CONFIG_AVR32
> 
> /* CPU and peripherals are both big-endian, so don't byte-swap */
> #define atmel_readl_relaxed(addr)		__raw_readl(addr)
> #define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)
> 
> #else
> 
> /* Peripherals are little-endian, so byte-swap if CPU isn't */
> #define atmel_readl_relaxed(addr)		readl_relaxed(addr)
> #define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)
> 
> #endif
> 
> Ben.

Hi, I think it will probably be a good idea to have an avr32/at91
read/write functions however I will put this forward as a separate
series as it will require both avr32 and at91 maintainers as well
as driver updates.

how about:
	atmel_readl_onchip{b,w,l}
	atmel_writel_onchip{b,w,l}


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ben Dooks]

On 19/03/15 14:22, Ben Hutchings wrote:
> On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
>> Change the __raw IO functions to endian agnostic relaxed ones to allow
>> the driver to function on big endian ARM systems.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> --
>> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
>> CC: Chris Ball <chris@printf.net>
>> CC: Ulf Hansson <ulf.hansson@linaro.org>
>> CC: linux-mmc at vger.kernel.org
>> ---
>>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
>> index c97001e..711bb53 100644
>> --- a/drivers/mmc/host/atmel-mci-regs.h
>> +++ b/drivers/mmc/host/atmel-mci-regs.h
>> @@ -135,10 +135,17 @@
>>  #define ATMCI_REGS_SIZE		0x100
>>  
>>  /* Register access macros */
>> -#define atmci_readl(port,reg)				\
>> +#ifdef CONFIG_AVR32
>> +#define atmci_readl(port,reg)			\
>>  	__raw_readl((port)->regs + reg)
>>  #define atmci_writel(port,reg,value)			\
>>  	__raw_writel((value), (port)->regs + reg)
>> +#else
>> +#define atmci_readl(port,reg)			\
>> +	readl_relaxed((port)->regs + reg)
>> +#define atmci_writel(port,reg,value)			\
>> +	writel_relaxed((value), (port)->regs + reg)
>> +#endif
> 
> This pattern is repeated in a lot of drivers; is it worth defining
> atmel_{read,write}l_relaxed() in a common header?
> 
> #ifdef CONFIG_AVR32
> 
> /* CPU and peripherals are both big-endian, so don't byte-swap */
> #define atmel_readl_relaxed(addr)		__raw_readl(addr)
> #define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)
> 
> #else
> 
> /* Peripherals are little-endian, so byte-swap if CPU isn't */
> #define atmel_readl_relaxed(addr)		readl_relaxed(addr)
> #define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)
> 
> #endif
> 
> Ben.

Hi, I think it will probably be a good idea to have an avr32/at91
read/write functions however I will put this forward as a separate
series as it will require both avr32 and at91 maintainers as well
as driver updates.

how about:
	atmel_readl_onchip{b,w,l}
	atmel_writel_onchip{b,w,l}


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Hans-Christian Egtvedt]

Around Tue 24 Mar 2015 12:53:41 +0000 or thereabout, Ben Dooks wrote:
> On 19/03/15 14:22, Ben Hutchings wrote:
>> On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
>>> Change the __raw IO functions to endian agnostic relaxed ones to allow
>>> the driver to function on big endian ARM systems.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> --
>>> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
>>> CC: Chris Ball <chris@printf.net>
>>> CC: Ulf Hansson <ulf.hansson@linaro.org>
>>> CC: linux-mmc@vger.kernel.org
>>> ---
>>>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
>>> index c97001e..711bb53 100644
>>> --- a/drivers/mmc/host/atmel-mci-regs.h
>>> +++ b/drivers/mmc/host/atmel-mci-regs.h
>>> @@ -135,10 +135,17 @@
>>>  #define ATMCI_REGS_SIZE		0x100
>>>  
>>>  /* Register access macros */
>>> -#define atmci_readl(port,reg)				\
>>> +#ifdef CONFIG_AVR32
>>> +#define atmci_readl(port,reg)			\
>>>  	__raw_readl((port)->regs + reg)
>>>  #define atmci_writel(port,reg,value)			\
>>>  	__raw_writel((value), (port)->regs + reg)
>>> +#else
>>> +#define atmci_readl(port,reg)			\
>>> +	readl_relaxed((port)->regs + reg)
>>> +#define atmci_writel(port,reg,value)			\
>>> +	writel_relaxed((value), (port)->regs + reg)
>>> +#endif
>> 
>> This pattern is repeated in a lot of drivers; is it worth defining
>> atmel_{read,write}l_relaxed() in a common header?
>> 
>> #ifdef CONFIG_AVR32
>> 
>> /* CPU and peripherals are both big-endian, so don't byte-swap */
>> #define atmel_readl_relaxed(addr)		__raw_readl(addr)
>> #define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)
>> 
>> #else
>> 
>> /* Peripherals are little-endian, so byte-swap if CPU isn't */
>> #define atmel_readl_relaxed(addr)		readl_relaxed(addr)
>> #define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)
>> 
>> #endif
>> 
>> Ben.
> 
> Hi, I think it will probably be a good idea to have an avr32/at91
> read/write functions however I will put this forward as a separate
> series as it will require both avr32 and at91 maintainers as well
> as driver updates.
> 
> how about:
> 	atmel_readl_onchip{b,w,l}
> 	atmel_writel_onchip{b,w,l}

Common is good, will make it easier for developers to understand why it is
like this as well.

-- 
Hans-Christian Egtvedt

[Linux-kernel] [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Hans-Christian Egtvedt]

Around Tue 24 Mar 2015 12:53:41 +0000 or thereabout, Ben Dooks wrote:
> On 19/03/15 14:22, Ben Hutchings wrote:
>> On Wed, 2015-03-18 at 15:53 +0000, Ben Dooks wrote:
>>> Change the __raw IO functions to endian agnostic relaxed ones to allow
>>> the driver to function on big endian ARM systems.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> --
>>> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
>>> CC: Chris Ball <chris@printf.net>
>>> CC: Ulf Hansson <ulf.hansson@linaro.org>
>>> CC: linux-mmc at vger.kernel.org
>>> ---
>>>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
>>> index c97001e..711bb53 100644
>>> --- a/drivers/mmc/host/atmel-mci-regs.h
>>> +++ b/drivers/mmc/host/atmel-mci-regs.h
>>> @@ -135,10 +135,17 @@
>>>  #define ATMCI_REGS_SIZE		0x100
>>>  
>>>  /* Register access macros */
>>> -#define atmci_readl(port,reg)				\
>>> +#ifdef CONFIG_AVR32
>>> +#define atmci_readl(port,reg)			\
>>>  	__raw_readl((port)->regs + reg)
>>>  #define atmci_writel(port,reg,value)			\
>>>  	__raw_writel((value), (port)->regs + reg)
>>> +#else
>>> +#define atmci_readl(port,reg)			\
>>> +	readl_relaxed((port)->regs + reg)
>>> +#define atmci_writel(port,reg,value)			\
>>> +	writel_relaxed((value), (port)->regs + reg)
>>> +#endif
>> 
>> This pattern is repeated in a lot of drivers; is it worth defining
>> atmel_{read,write}l_relaxed() in a common header?
>> 
>> #ifdef CONFIG_AVR32
>> 
>> /* CPU and peripherals are both big-endian, so don't byte-swap */
>> #define atmel_readl_relaxed(addr)		__raw_readl(addr)
>> #define atmel_writel_relaxed(value, addr)	__raw_writel(value, addr)
>> 
>> #else
>> 
>> /* Peripherals are little-endian, so byte-swap if CPU isn't */
>> #define atmel_readl_relaxed(addr)		readl_relaxed(addr)
>> #define atmel_writel_relaxed(value, addr)	writel_relaxed(value, addr)
>> 
>> #endif
>> 
>> Ben.
> 
> Hi, I think it will probably be a good idea to have an avr32/at91
> read/write functions however I will put this forward as a separate
> series as it will require both avr32 and at91 maintainers as well
> as driver updates.
> 
> how about:
> 	atmel_readl_onchip{b,w,l}
> 	atmel_writel_onchip{b,w,l}

Common is good, will make it easier for developers to understand why it is
like this as well.

-- 
Hans-Christian Egtvedt

Re: [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ludovic Desroches]

On Wed, Mar 18, 2015 at 03:53:11PM +0000, Ben Dooks wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>

Thanks
> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc@vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE		0x100
>  
>  /* Register access macros */
> -#define atmci_readl(port,reg)				\
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)			\
>  	__raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)			\
>  	__raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)			\
> +	readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)			\
> +	writel_relaxed((value), (port)->regs + reg)
> +#endif
>  
>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32
> -- 
> 2.1.4
> 

[PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ludovic Desroches]

On Wed, Mar 18, 2015 at 03:53:11PM +0000, Ben Dooks wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>

Thanks
> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc at vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE		0x100
>  
>  /* Register access macros */
> -#define atmci_readl(port,reg)				\
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)			\
>  	__raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)			\
>  	__raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)			\
> +	readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)			\
> +	writel_relaxed((value), (port)->regs + reg)
> +#endif
>  
>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32
> -- 
> 2.1.4
> 

Re: [PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ulf Hansson]

On 18 March 2015 at 16:53, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Thanks! Applied.

Kind regards
Uffe


> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc@vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE                0x100
>
>  /* Register access macros */
> -#define atmci_readl(port,reg)                          \
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)                  \
>         __raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)                   \
>         __raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)                  \
> +       readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)                   \
> +       writel_relaxed((value), (port)->regs + reg)
> +#endif
>
>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32
> --
> 2.1.4
>

[PATCH 12/13] mmc: atmel-mci: use endian agnostic IO

[Ulf Hansson]

On 18 March 2015 at 16:53, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> Change the __raw IO functions to endian agnostic relaxed ones to allow
> the driver to function on big endian ARM systems.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Thanks! Applied.

Kind regards
Uffe


> --
> CC: Ludovic Desroches <ludovic.desroches@atmel.com>
> CC: Chris Ball <chris@printf.net>
> CC: Ulf Hansson <ulf.hansson@linaro.org>
> CC: linux-mmc at vger.kernel.org
> ---
>  drivers/mmc/host/atmel-mci-regs.h | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index c97001e..711bb53 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -135,10 +135,17 @@
>  #define ATMCI_REGS_SIZE                0x100
>
>  /* Register access macros */
> -#define atmci_readl(port,reg)                          \
> +#ifdef CONFIG_AVR32
> +#define atmci_readl(port,reg)                  \
>         __raw_readl((port)->regs + reg)
>  #define atmci_writel(port,reg,value)                   \
>         __raw_writel((value), (port)->regs + reg)
> +#else
> +#define atmci_readl(port,reg)                  \
> +       readl_relaxed((port)->regs + reg)
> +#define atmci_writel(port,reg,value)                   \
> +       writel_relaxed((value), (port)->regs + reg)
> +#endif
>
>  /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
>  #ifdef CONFIG_AVR32
> --
> 2.1.4
>

ATSAMA5D big endian work

[Alexandre Belloni]

Hi,

On 18/03/2015 at 15:52:59 +0000, Ben Dooks wrote :
> I have been testing the ATSAMA5D36 xplained board with big endian and
> the following are the fixes to get the system working.
> 

The series looks good to me, we will drop patches 3 and 4 as the files
doesn't exist anymore.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

ATSAMA5D big endian work

[Ben Dooks]

On 18/03/15 18:30, Alexandre Belloni wrote:
> Hi,
> 
> On 18/03/2015 at 15:52:59 +0000, Ben Dooks wrote :
>> I have been testing the ATSAMA5D36 xplained board with big endian and
>> the following are the fixes to get the system working.
>>
> 
> The series looks good to me, we will drop patches 3 and 4 as the files
> doesn't exist anymore.

Where can I find a repository with these changes in?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

ATSAMA5D big endian work

[Alexandre Belloni]

On 19/03/2015 at 09:34:43 +0000, Ben Dooks wrote :
> On 18/03/15 18:30, Alexandre Belloni wrote:
> > Hi,
> > 
> > On 18/03/2015 at 15:52:59 +0000, Ben Dooks wrote :
> >> I have been testing the ATSAMA5D36 xplained board with big endian and
> >> the following are the fixes to get the system working.
> >>
> > 
> > The series looks good to me, we will drop patches 3 and 4 as the files
> > doesn't exist anymore.
> 
> Where can I find a repository with these changes in?
> 

You can use this branch until Nicolas merges my patches:

https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2

The remaining __raw_writel and __raw_readl are in pm.h

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

ATSAMA5D big endian work

[Ben Dooks]

On 19/03/15 13:30, Alexandre Belloni wrote:
> On 19/03/2015 at 09:34:43 +0000, Ben Dooks wrote :
>> On 18/03/15 18:30, Alexandre Belloni wrote:
>>> Hi,
>>>
>>> On 18/03/2015 at 15:52:59 +0000, Ben Dooks wrote :
>>>> I have been testing the ATSAMA5D36 xplained board with big endian and
>>>> the following are the fixes to get the system working.
>>>>
>>>
>>> The series looks good to me, we will drop patches 3 and 4 as the files
>>> doesn't exist anymore.
>>
>> Where can I find a repository with these changes in?
>>
> 
> You can use this branch until Nicolas merges my patches:
> 
> https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2
> 
> The remaining __raw_writel and __raw_readl are in pm.h

Ok, should I submit my next series for inclusion in to your tree?


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

ATSAMA5D big endian work

[Alexandre Belloni]

Hi,

On 20/03/2015 at 16:58:39 +0000, Ben Dooks wrote :
> > You can use this branch until Nicolas merges my patches:
> > 
> > https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2
> > 
> > The remaining __raw_writel and __raw_readl are in pm.h
> 
> Ok, should I submit my next series for inclusion in to your tree?
> 

I've sent all my series and Nicolas is supposed to take them soon so I
think the best would be to wait a bit. IF you want, I'll ping you when
everything is in.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

ATSAMA5D big endian work

[Ben Dooks]

On 20/03/15 17:19, Alexandre Belloni wrote:
> Hi,
> 
> On 20/03/2015 at 16:58:39 +0000, Ben Dooks wrote :
>>> You can use this branch until Nicolas merges my patches:
>>>
>>> https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2
>>>
>>> The remaining __raw_writel and __raw_readl are in pm.h
>>
>> Ok, should I submit my next series for inclusion in to your tree?
>>
> 
> I've sent all my series and Nicolas is supposed to take them soon so I
> think the best would be to wait a bit. IF you want, I'll ping you when
> everything is in.

Ok, I'll try and re-base on and test with your series in prep.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

ATSAMA5D big endian work

[Nicolas Ferre]

Le 20/03/2015 18:29, Ben Dooks a ?crit :
> On 20/03/15 17:19, Alexandre Belloni wrote:
>> Hi,
>>
>> On 20/03/2015 at 16:58:39 +0000, Ben Dooks wrote :
>>>> You can use this branch until Nicolas merges my patches:
>>>>
>>>> https://github.com/alexandrebelloni/linux/tree/at91_4.1_04_cleanup2
>>>>
>>>> The remaining __raw_writel and __raw_readl are in pm.h
>>>
>>> Ok, should I submit my next series for inclusion in to your tree?
>>>
>>
>> I've sent all my series and Nicolas is supposed to take them soon so I
>> think the best would be to wait a bit. IF you want, I'll ping you when
>> everything is in.
> 
> Ok, I'll try and re-base on and test with your series in prep.

Ben, Alex,

I've just updated my branch at91-next that stands on my git tree
(https://git.kernel.org/cgit/linux/kernel/git/nferre/linux-at91.git/).

It includes at91-cleanup3 + at91-multiplatform + at91-cleanup4 that are
not yet included in arm-soc (nor linux-next).

So, you can start from this if you want to rebase your work. In the
meantime, we can continue to push obvious changes to subsystem
maintainers and think about Ben Hutchings' idea...

Thanks a lot, bye.
-- 
Nicolas Ferre

[Linux-kernel] ATSAMA5D big endian work

[Ben Dooks]

On 18/03/15 15:52, Ben Dooks wrote:
> I have been testing the ATSAMA5D36 xplained board with big endian and
> the following are the fixes to get the system working.

As a note, I am still having issues with the macb driver (DMA HRESP
faults) which don't happen on the Xilinx version of this. Since I
have no data on the block I could do with some feedback from ATMEL
on this.

I still have yet to fix the NAND driver, but do not have any time
today to re-visit this.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius