[PATCH 0/5] Finish gen6/7 ppgtt dynamic page allocations

[PATCH 0/5] Finish gen6/7 ppgtt dynamic page allocations

[Michel Thierry]

The first 2 patches are fixes from the previous patchset, reported by static
analysis tools, while the last 2 patches complete the required work for gen6/7.

I've also started changing the authorship of the patches as suggested by Daniel.

Michel Thierry (5):
  drm/i915: Prevent out of range pt in gen6_for_each_pde
  drm/i915: i915_dma_map_single returns positive error codes
  drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages
  drm/i915: Finish gen6/7 dynamic page table allocation
  drm/i915: Add dynamic page trace events

 drivers/gpu/drm/i915/i915_gem.c     |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 164 +++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/i915_gem_gtt.h |   8 +-
 drivers/gpu/drm/i915/i915_trace.h   |  99 ++++++++++++++++++++++
 4 files changed, 239 insertions(+), 34 deletions(-)

-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/5] drm/i915: Prevent out of range pt in gen6_for_each_pde

[Michel Thierry]

Found by static analysis tool, this was harmless as the pt was not
used out of scope though.

Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 75e29f7..a85bd5c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -327,9 +327,9 @@ struct i915_hw_ppgtt {
  * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
  */
 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
-	for (iter = gen6_pde_index(start), pt = (pd)->page_table[iter]; \
-	     length > 0 && iter < I915_PDES; \
-	     pt = (pd)->page_table[++iter], \
+	for (iter = gen6_pde_index(start); \
+	     pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
+	     iter++, \
 	     temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
 	     temp = min_t(unsigned, temp, length), \
 	     start += temp, length -= temp)
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/5] drm/i915: i915_dma_map_single returns positive error codes

[Michel Thierry]

i915_dma_map_single relies on dma_mapping_error, which returns positive
error codes. Found by static checker.

Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 645c363..79ade6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -348,7 +348,7 @@ static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
 		goto fail_page;
 
 	ret = i915_dma_map_single(pt, dev);
-	if (ret)
+	if (ret != 0)
 		goto fail_dma;
 
 	return pt;
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/5] drm/i915: i915_dma_map_single returns positive error codes

[Dan Carpenter]

On Tue, Mar 24, 2015 at 03:46:20PM +0000, Michel Thierry wrote:
> i915_dma_map_single relies on dma_mapping_error, which returns positive
> error codes. Found by static checker.
> 
> Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
> ("drm/i915: Track GEN6 page table usage").
> 

Please give me reporter credit so I can justify my paycheck to my boss.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

> Cc: Dan Carpenter <dan.carpenter@oracle.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 645c363..79ade6f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -348,7 +348,7 @@ static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
>  		goto fail_page;
>  
>  	ret = i915_dma_map_single(pt, dev);
> -	if (ret)
> +	if (ret != 0)

Heh.  What is this?  :P  You just added a double negative.  Just change
to return negative error codes on failure.

regards,
dan carpenter

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/5] drm/i915: i915_dma_map_single returns positive error codes

[Dan Carpenter]

On Tue, Mar 24, 2015 at 06:57:13PM +0300, Dan Carpenter wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 645c363..79ade6f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -348,7 +348,7 @@ static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
> >  		goto fail_page;
> >  
> >  	ret = i915_dma_map_single(pt, dev);
> > -	if (ret)
> > +	if (ret != 0)
> 
> Heh.  What is this?  :P  You just added a double negative.  Just change
> to return negative error codes on failure.

Oops.  I left out a word.  That should say "Just change
i915_dma_map_page_single() to negative error codes on failure."

Currently, it returns 0 on success and 1 on failure which is
non-standard.

regards,
dan carpenter

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/5] drm/i915: i915_dma_map_single returns positive error codes

[Michel Thierry]

On 3/24/2015 4:03 PM, Dan Carpenter wrote:
> On Tue, Mar 24, 2015 at 06:57:13PM +0300, Dan Carpenter wrote:
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> index 645c363..79ade6f 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> @@ -348,7 +348,7 @@ static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
>>>   		goto fail_page;
>>>   
>>>   	ret = i915_dma_map_single(pt, dev);
>>> -	if (ret)
>>> +	if (ret != 0)
>> Heh.  What is this?  :P  You just added a double negative.  Just change
>> to return negative error codes on failure.
> Oops.  I left out a word.  That should say "Just change
> i915_dma_map_page_single() to negative error codes on failure."
>
> Currently, it returns 0 on success and 1 on failure which is
> non-standard.
Ok, the function is returning the value straight from dma_mapping_error(),
I'll change i915_dma_map_page_single() to return -ENOMEM when 
dma_mapping_error doesn't return 0.

Thanks,

-Michel
> regards,
> dan carpenter
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2] drm/i915: Fix i915_dma_map_single positive error code

[Michel Thierry]

i915_dma_map_single relies on dma_mapping_error, which returns positive
error codes. Found by static checker.

Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").

v2: Return negative error code and rename commit title. (Dan)

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 645c363..6bb31c8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -311,7 +311,10 @@ static inline int i915_dma_map_page_single(struct page *page,
 	struct device *device = &dev->pdev->dev;
 
 	*daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
-	return dma_mapping_error(device, *daddr);
+	if (dma_mapping_error(device, *daddr))
+		return -ENOMEM;
+
+	return 0;
 }
 
 static void unmap_and_free_pt(struct i915_page_table_entry *pt,
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915: Fix i915_dma_map_single positive error code

[Daniel Vetter]

On Tue, Mar 24, 2015 at 04:44:38PM +0000, Michel Thierry wrote:
> i915_dma_map_single relies on dma_mapping_error, which returns positive
> error codes. Found by static checker.
> 
> Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
> ("drm/i915: Track GEN6 page table usage").
> 
> v2: Return negative error code and rename commit title. (Dan)
> 
> Cc: Dan Carpenter <dan.carpenter@oracle.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>

Still missing the reported-by. Giving credit where it's due is important,
especially when they work for other companies than Intel.
-Daniel

> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 645c363..6bb31c8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -311,7 +311,10 @@ static inline int i915_dma_map_page_single(struct page *page,
>  	struct device *device = &dev->pdev->dev;
>  
>  	*daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
> -	return dma_mapping_error(device, *daddr);
> +	if (dma_mapping_error(device, *daddr))
> +		return -ENOMEM;
> +
> +	return 0;
>  }
>  
>  static void unmap_and_free_pt(struct i915_page_table_entry *pt,
> -- 
> 2.1.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2] drm/i915: Fix i915_dma_map_single positive error code

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6041
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              269/269              268/269
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                 -1              338/338              337/338
BYT                                  287/287              287/287
HSW                                  362/362              362/362
BDW                                  310/310              310/310
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gen3_render_linear_blits      FAIL(1)PASS(2)      FAIL(2)
*IVB  igt@gem_storedw_batches_loop@normal      PASS(2)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3] drm/i915: Fix i915_dma_map_single positive error code

[Michel Thierry]

i915_dma_map_single relies on dma_mapping_error, which returns positive
error codes. Found by static checker.

Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").

v2: Return negative error code and renamed commit title. (Dan)
v3: Missing reported-by tag (Daniel)

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 645c363..6bb31c8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -311,7 +311,10 @@ static inline int i915_dma_map_page_single(struct page *page,
 	struct device *device = &dev->pdev->dev;
 
 	*daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
-	return dma_mapping_error(device, *daddr);
+	if (dma_mapping_error(device, *daddr))
+		return -ENOMEM;
+
+	return 0;
 }
 
 static void unmap_and_free_pt(struct i915_page_table_entry *pt,
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3] drm/i915: Fix i915_dma_map_single positive error code

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6041
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              269/269              268/269
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                 -1              338/338              337/338
BYT                                  287/287              287/287
HSW                                  362/362              362/362
BDW                                  310/310              310/310
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gen3_render_linear_blits      FAIL(1)PASS(2)      FAIL(2)
*IVB  igt@gem_storedw_batches_loop@normal      PASS(2)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/5] drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages

[Michel Thierry]

We are already unmapping them in gen6_ppgtt_free. This function became
redundant since commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
("drm/i915: Create page table allocators").

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 79ade6f..6effa61 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1152,16 +1152,6 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 		kunmap_atomic(pt_vaddr);
 }
 
-static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
-{
-	int i;
-
-	for (i = 0; i < ppgtt->num_pd_entries; i++)
-		pci_unmap_page(ppgtt->base.dev->pdev,
-			       ppgtt->pd.page_table[i]->daddr,
-			       4096, PCI_DMA_BIDIRECTIONAL);
-}
-
 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
  * are switching between contexts with the same LRCA, we also must do a force
  * restore.
@@ -1212,7 +1202,6 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 
 	drm_mm_remove_node(&ppgtt->node);
 
-	gen6_ppgtt_unmap_pages(ppgtt);
 	gen6_ppgtt_free(ppgtt);
 }
 
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/5] drm/i915: Finish gen6/7 dynamic page table allocation

[Michel Thierry]

This patch continues on the idea from "Track GEN6 page table usage".
From here on, in the steady state, PDEs are all pointing to the scratch
page table (as recommended in the spec). When an object is allocated in
the VA range, the code will determine if we need to allocate a page for
the page table. Similarly when the object is destroyed, we will remove,
and free the page table pointing the PDE back to the scratch page.

Following patches will work to unify the code a bit as we bring in GEN8
support. GEN6 and GEN8 are different enough that I had a hard time to
get to this point with as much common code as I do.

The aliasing PPGTT must pre-allocate all of the page tables. There are a
few reasons for this. Two trivial ones: aliasing ppgtt goes through the
ggtt paths, so it's hard to maintain, we currently do not restore the
default context (assuming the previous force reload is indeed
necessary). Most importantly though, the only way (it seems from
empirical evidence) to invalidate the CS TLBs on non-render ring is to
either use ring sync (which requires actually stopping the rings in
order to synchronize when the sync completes vs. where you are in
execution), or to reload DCLV.  Since without full PPGTT we do not ever
reload the DCLV register, there is no good way to achieve this. The
simplest solution is just to not support dynamic page table
creation/destruction in the aliasing PPGTT.

We could always reload DCLV, but this seems like quite a bit of excess
overhead only to save at most 2MB-4k of memory for the aliasing PPGTT
page tables.

v2: Make the page table bitmap declared inside the function (Chris)
Simplify the way scratching address space works.
Move the alloc/teardown tracepoints up a level in the call stack so that
both all implementations get the trace.

v3: Updated trace event to spit out a name

v4: Aliasing ppgtt is now initialized differently (in setup global gtt)

v5: Rebase to latest code. Also removed unnecessary aliasing ppgtt check
for trace, as it is no longer possible after the PPGTT cleanup patch series
of a couple of months ago (Daniel).

v6: Implement changes from code review (Daniel):
 - allocate/teardown_va_range calls added.
 - Add a scratch page allocation helper (only need the address).
 - Move trace events to a new patch.
 - Use updated mark_tlbs_dirty.
 - Moved pt preallocation for aliasing ppgtt into gen6_ppgtt_init.

v7: teardown_va_range removed (Daniel).
    In init, gen6_ppgtt_clear_range call is only needed for aliasing ppgtt.

v8: Rebase after s/page_tables/page_table/.

v9: Remove unnecessary scratch flag in page_table struct, future patches
can just compare against ppgtt->scratch_pt, and alloc_pt_scratch becomes
redundant. Initialize scratch_pt and pt. (Mika)

v10: Clean up aliasing ppgtt init error path and prevent leaking the
ppgtt obj when init fails. (Mika)
Updated commit author. (Daniel)

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v4+)
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 146 +++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_gem_gtt.h |   2 +
 2 files changed, 129 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6effa61..0952736 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -343,7 +343,7 @@ static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
 	if (!pt->used_ptes)
 		goto fail_bitmap;
 
-	pt->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+	pt->page = alloc_page(GFP_KERNEL);
 	if (!pt->page)
 		goto fail_page;
 
@@ -378,7 +378,7 @@ fail_bitmap:
  * Return: 0 if allocation succeeded.
  */
 static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count,
-		  struct drm_device *dev)
+			  struct drm_device *dev)
 {
 	int i, ret;
 
@@ -1162,13 +1162,70 @@ static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
 }
 
+static void gen6_initialize_pt(struct i915_address_space *vm,
+		struct i915_page_table_entry *pt)
+{
+	gen6_pte_t *pt_vaddr, scratch_pte;
+	int i;
+
+	WARN_ON(vm->scratch.addr == 0);
+
+	scratch_pte = vm->pte_encode(vm->scratch.addr,
+			I915_CACHE_LLC, true, 0);
+
+	pt_vaddr = kmap_atomic(pt->page);
+
+	for (i = 0; i < GEN6_PTES; i++)
+		pt_vaddr[i] = scratch_pte;
+
+	kunmap_atomic(pt_vaddr);
+}
+
 static int gen6_alloc_va_range(struct i915_address_space *vm,
 			       uint64_t start, uint64_t length)
 {
+	DECLARE_BITMAP(new_page_tables, I915_PDES);
+	struct drm_device *dev = vm->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_hw_ppgtt *ppgtt =
 				container_of(vm, struct i915_hw_ppgtt, base);
 	struct i915_page_table_entry *pt;
+	const uint32_t start_save = start, length_save = length;
 	uint32_t pde, temp;
+	int ret;
+
+	WARN_ON(upper_32_bits(start));
+
+	bitmap_zero(new_page_tables, I915_PDES);
+
+	/* The allocation is done in two stages so that we can bail out with
+	 * minimal amount of pain. The first stage finds new page tables that
+	 * need allocation. The second stage marks use ptes within the page
+	 * tables.
+	 */
+	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
+		if (pt != ppgtt->scratch_pt) {
+			WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
+			continue;
+		}
+
+		/* We've already allocated a page table */
+		WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
+
+		pt = alloc_pt_single(dev);
+		if (IS_ERR(pt)) {
+			ret = PTR_ERR(pt);
+			goto unwind_out;
+		}
+
+		gen6_initialize_pt(vm, pt);
+
+		ppgtt->pd.page_table[pde] = pt;
+		set_bit(pde, new_page_tables);
+	}
+
+	start = start_save;
+	length = length_save;
 
 	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
 		DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
@@ -1177,21 +1234,46 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 		bitmap_set(tmp_bitmap, gen6_pte_index(start),
 			   gen6_pte_count(start, length));
 
-		bitmap_or(pt->used_ptes, pt->used_ptes, tmp_bitmap,
+		if (test_and_clear_bit(pde, new_page_tables))
+			gen6_write_pde(&ppgtt->pd, pde, pt);
+
+		bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
 				GEN6_PTES);
 	}
 
+	WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
+
+	/* Make sure write is complete before other code can use this page
+	 * table. Also require for WC mapped PTEs */
+	readl(dev_priv->gtt.gsm);
+
 	mark_tlbs_dirty(ppgtt);
 	return 0;
+
+unwind_out:
+	for_each_set_bit(pde, new_page_tables, I915_PDES) {
+		struct i915_page_table_entry *pt = ppgtt->pd.page_table[pde];
+
+		ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
+		unmap_and_free_pt(pt, vm->dev);
+	}
+
+	mark_tlbs_dirty(ppgtt);
+	return ret;
 }
 
 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 {
 	int i;
 
-	for (i = 0; i < ppgtt->num_pd_entries; i++)
-		unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev);
+	for (i = 0; i < ppgtt->num_pd_entries; i++) {
+		struct i915_page_table_entry *pt = ppgtt->pd.page_table[i];
+
+		if (pt != ppgtt->scratch_pt)
+			unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev);
+	}
 
+	unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
 	unmap_and_free_pd(&ppgtt->pd);
 }
 
@@ -1217,6 +1299,12 @@ static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
 	 * size. We allocate at the top of the GTT to avoid fragmentation.
 	 */
 	BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
+	ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
+	if (IS_ERR(ppgtt->scratch_pt))
+		return PTR_ERR(ppgtt->scratch_pt);
+
+	gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
+
 alloc:
 	ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 						  &ppgtt->node, GEN6_PD_SIZE,
@@ -1247,6 +1335,7 @@ alloc:
 	return 0;
 
 err_out:
+	unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
 	return ret;
 }
 
@@ -1258,18 +1347,20 @@ static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
 	if (ret)
 		return ret;
 
-	ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries,
-			ppgtt->base.dev);
+	return 0;
+}
 
-	if (ret) {
-		drm_mm_remove_node(&ppgtt->node);
-		return ret;
-	}
+static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
+				  uint64_t start, uint64_t length)
+{
+	struct i915_page_table_entry *unused;
+	uint32_t pde, temp;
 
-	return 0;
+	gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
+		ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
 }
 
-static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing)
 {
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1292,6 +1383,17 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	if (ret)
 		return ret;
 
+	if (aliasing) {
+		/* preallocate all pts */
+		ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries,
+				ppgtt->base.dev);
+
+		if (ret) {
+			gen6_ppgtt_cleanup(&ppgtt->base);
+			return ret;
+		}
+	}
+
 	ppgtt->base.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
@@ -1306,7 +1408,10 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
 		ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
 
-	ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
+	if (aliasing)
+		ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
+	else
+		gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
 
 	gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
 
@@ -1320,7 +1425,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 	return 0;
 }
 
-static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt,
+		bool aliasing)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -1328,7 +1434,7 @@ static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 	ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 
 	if (INTEL_INFO(dev)->gen < 8)
-		return gen6_ppgtt_init(ppgtt);
+		return gen6_ppgtt_init(ppgtt, aliasing);
 	else
 		return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 }
@@ -1337,7 +1443,7 @@ int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = 0;
 
-	ret = __hw_ppgtt_init(dev, ppgtt);
+	ret = __hw_ppgtt_init(dev, ppgtt, false);
 	if (ret == 0) {
 		kref_init(&ppgtt->ref);
 		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
@@ -1972,9 +2078,11 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
 		if (!ppgtt)
 			return -ENOMEM;
 
-		ret = __hw_ppgtt_init(dev, ppgtt);
-		if (ret != 0)
+		ret = __hw_ppgtt_init(dev, ppgtt, true);
+		if (ret) {
+			kfree(ppgtt);
 			return ret;
+		}
 
 		dev_priv->mm.aliasing_ppgtt = ppgtt;
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index a85bd5c..ddff6cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -308,6 +308,8 @@ struct i915_hw_ppgtt {
 		struct i915_page_directory_entry pd;
 	};
 
+	struct i915_page_table_entry *scratch_pt;
+
 	struct drm_i915_file_private *file_priv;
 
 	gen6_pte_t __iomem *pd_addr;
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 5/5] drm/i915: Add dynamic page trace events

[Michel Thierry]

Traces for page directories and tables allocation and map.

v2: Removed references to teardown.
v3: bitmap_scnprintf has been deprecated.
v4: Replace bitmap_scnprintf with scnprintf correctly, and get right
range lengths. (Mika)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c     |  2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  5 ++
 drivers/gpu/drm/i915/i915_trace.h   | 99 +++++++++++++++++++++++++++++++++++++
 3 files changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 08feb54..99dc0da 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3538,6 +3538,8 @@ search_free:
 
 	/*  allocate before insert / bind */
 	if (vma->vm->allocate_va_range) {
+		trace_i915_va_alloc(vma->vm, vma->node.start, vma->node.size,
+				VM_TO_TRACE_NAME(vma->vm));
 		ret = vma->vm->allocate_va_range(vma->vm,
 						vma->node.start,
 						vma->node.size);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0952736..1bb2736 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1222,6 +1222,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 
 		ppgtt->pd.page_table[pde] = pt;
 		set_bit(pde, new_page_tables);
+		trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
 	}
 
 	start = start_save;
@@ -1237,6 +1238,10 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 		if (test_and_clear_bit(pde, new_page_tables))
 			gen6_write_pde(&ppgtt->pd, pde, pt);
 
+		trace_i915_page_table_entry_map(vm, pde, pt,
+					 gen6_pte_index(start),
+					 gen6_pte_count(start, length),
+					 GEN6_PTES);
 		bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
 				GEN6_PTES);
 	}
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index f004d3d..b3070a4 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -156,6 +156,105 @@ TRACE_EVENT(i915_vma_unbind,
 		      __entry->obj, __entry->offset, __entry->size, __entry->vm)
 );
 
+#define VM_TO_TRACE_NAME(vm) \
+	(i915_is_ggtt(vm) ? "G" : \
+		      "P")
+
+DECLARE_EVENT_CLASS(i915_va,
+	TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
+	TP_ARGS(vm, start, length, name),
+
+	TP_STRUCT__entry(
+		__field(struct i915_address_space *, vm)
+		__field(u64, start)
+		__field(u64, end)
+		__string(name, name)
+	),
+
+	TP_fast_assign(
+		__entry->vm = vm;
+		__entry->start = start;
+		__entry->end = start + length - 1;
+		__assign_str(name, name);
+	),
+
+	TP_printk("vm=%p (%s), 0x%llx-0x%llx",
+		  __entry->vm, __get_str(name),  __entry->start, __entry->end)
+);
+
+DEFINE_EVENT(i915_va, i915_va_alloc,
+	     TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
+	     TP_ARGS(vm, start, length, name)
+);
+
+DECLARE_EVENT_CLASS(i915_page_table_entry,
+	TP_PROTO(struct i915_address_space *vm, u32 pde, u64 start, u64 pde_shift),
+	TP_ARGS(vm, pde, start, pde_shift),
+
+	TP_STRUCT__entry(
+		__field(struct i915_address_space *, vm)
+		__field(u32, pde)
+		__field(u64, start)
+		__field(u64, end)
+	),
+
+	TP_fast_assign(
+		__entry->vm = vm;
+		__entry->pde = pde;
+		__entry->start = start;
+		__entry->end = ((start + (1ULL << pde_shift)) & ~((1ULL << pde_shift)-1)) - 1;
+	),
+
+	TP_printk("vm=%p, pde=%d (0x%llx-0x%llx)",
+		  __entry->vm, __entry->pde, __entry->start, __entry->end)
+);
+
+DEFINE_EVENT(i915_page_table_entry, i915_page_table_entry_alloc,
+	     TP_PROTO(struct i915_address_space *vm, u32 pde, u64 start, u64 pde_shift),
+	     TP_ARGS(vm, pde, start, pde_shift)
+);
+
+/* Avoid extra math because we only support two sizes. The format is defined by
+ * bitmap_scnprintf. Each 32 bits is 8 HEX digits followed by comma */
+#define TRACE_PT_SIZE(bits) \
+	((((bits) == 1024) ? 288 : 144) + 1)
+
+DECLARE_EVENT_CLASS(i915_page_table_entry_update,
+	TP_PROTO(struct i915_address_space *vm, u32 pde,
+		 struct i915_page_table_entry *pt, u32 first, u32 count, u32 bits),
+	TP_ARGS(vm, pde, pt, first, count, bits),
+
+	TP_STRUCT__entry(
+		__field(struct i915_address_space *, vm)
+		__field(u32, pde)
+		__field(u32, first)
+		__field(u32, last)
+		__dynamic_array(char, cur_ptes, TRACE_PT_SIZE(bits))
+	),
+
+	TP_fast_assign(
+		__entry->vm = vm;
+		__entry->pde = pde;
+		__entry->first = first;
+		__entry->last = first + count - 1;
+		scnprintf(__get_str(cur_ptes),
+			  TRACE_PT_SIZE(bits),
+			  "%*pb",
+			  bits,
+			  pt->used_ptes);
+	),
+
+	TP_printk("vm=%p, pde=%d, updating %u:%u\t%s",
+		  __entry->vm, __entry->pde, __entry->last, __entry->first,
+		  __get_str(cur_ptes))
+);
+
+DEFINE_EVENT(i915_page_table_entry_update, i915_page_table_entry_map,
+	TP_PROTO(struct i915_address_space *vm, u32 pde,
+		 struct i915_page_table_entry *pt, u32 first, u32 count, u32 bits),
+	TP_ARGS(vm, pde, pt, first, count, bits)
+);
+
 TRACE_EVENT(i915_gem_object_change_domain,
 	    TP_PROTO(struct drm_i915_gem_object *obj, u32 old_read, u32 old_write),
 	    TP_ARGS(obj, old_read, old_write),
-- 
2.1.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915: Add dynamic page trace events

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6040
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -3              269/269              266/269
ILK                 -1              303/303              302/303
SNB                                  304/304              304/304
IVB                 -1              338/338              337/338
BYT                                  287/287              287/287
HSW                                  362/362              362/362
BDW                                  310/310              310/310
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gem_userptr_blits@coherency-sync      CRASH(1)PASS(2)      CRASH(1)PASS(1)
*PNV  igt@gen3_render_linear_blits      PASS(2)      FAIL(1)PASS(1)
 PNV  igt@gem_userptr_blits@minor-unsync-interruptible      DMESG_WARN(1)PASS(1)      DMESG_WARN(2)
*ILK  igt@gem_seqno_wrap      PASS(3)      DMESG_WARN(1)PASS(1)
*IVB  igt@gem_storedw_batches_loop@secure-dispatch      PASS(2)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/5] Finish gen6/7 ppgtt dynamic page allocations

[Mika Kuoppala]

Michel Thierry <michel.thierry@intel.com> writes:

> The first 2 patches are fixes from the previous patchset, reported by static
> analysis tools, while the last 2 patches complete the required work for gen6/7.
>
> I've also started changing the authorship of the patches as suggested by Daniel.
>
> Michel Thierry (5):
>   drm/i915: Prevent out of range pt in gen6_for_each_pde
>   drm/i915: i915_dma_map_single returns positive error codes
>   drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages
>   drm/i915: Finish gen6/7 dynamic page table allocation
>   drm/i915: Add dynamic page trace events
>

Daniel,

We have tossed the Finish gen6/7 one around in irc quite a lot.

Patches 1, 2v3, 3, 4, 5:
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

>  drivers/gpu/drm/i915/i915_gem.c     |   2 +
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 164 +++++++++++++++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_gem_gtt.h |   8 +-
>  drivers/gpu/drm/i915/i915_trace.h   |  99 ++++++++++++++++++++++
>  4 files changed, 239 insertions(+), 34 deletions(-)
>
> -- 
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/5] Finish gen6/7 ppgtt dynamic page allocations

[Daniel Vetter]

On Thu, Mar 26, 2015 at 05:43:51PM +0200, Mika Kuoppala wrote:
> Michel Thierry <michel.thierry@intel.com> writes:
> 
> > The first 2 patches are fixes from the previous patchset, reported by static
> > analysis tools, while the last 2 patches complete the required work for gen6/7.
> >
> > I've also started changing the authorship of the patches as suggested by Daniel.
> >
> > Michel Thierry (5):
> >   drm/i915: Prevent out of range pt in gen6_for_each_pde
> >   drm/i915: i915_dma_map_single returns positive error codes
> >   drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages
> >   drm/i915: Finish gen6/7 dynamic page table allocation
> >   drm/i915: Add dynamic page trace events
> >
> 
> Daniel,
> 
> We have tossed the Finish gen6/7 one around in irc quite a lot.
> 
> Patches 1, 2v3, 3, 4, 5:
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

All merged, thanks for patches&review.

btw since you're having all these discussions: Are you taking notes for
some nice kerneldoc polish on top of all these patches?

Thanks, Daniel
> 
> >  drivers/gpu/drm/i915/i915_gem.c     |   2 +
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 164 +++++++++++++++++++++++++++++-------
> >  drivers/gpu/drm/i915/i915_gem_gtt.h |   8 +-
> >  drivers/gpu/drm/i915/i915_trace.h   |  99 ++++++++++++++++++++++
> >  4 files changed, 239 insertions(+), 34 deletions(-)
> >
> > -- 
> > 2.1.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/5] Finish gen6/7 ppgtt dynamic page allocations

[Mika Kuoppala]

Daniel Vetter <daniel@ffwll.ch> writes:

> On Thu, Mar 26, 2015 at 05:43:51PM +0200, Mika Kuoppala wrote:
>> Michel Thierry <michel.thierry@intel.com> writes:
>> 
>> > The first 2 patches are fixes from the previous patchset, reported by static
>> > analysis tools, while the last 2 patches complete the required work for gen6/7.
>> >
>> > I've also started changing the authorship of the patches as suggested by Daniel.
>> >
>> > Michel Thierry (5):
>> >   drm/i915: Prevent out of range pt in gen6_for_each_pde
>> >   drm/i915: i915_dma_map_single returns positive error codes
>> >   drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages
>> >   drm/i915: Finish gen6/7 dynamic page table allocation
>> >   drm/i915: Add dynamic page trace events
>> >
>> 
>> Daniel,
>> 
>> We have tossed the Finish gen6/7 one around in irc quite a lot.
>> 
>> Patches 1, 2v3, 3, 4, 5:
>> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
>
> All merged, thanks for patches&review.
>
> btw since you're having all these discussions: Are you taking notes for
> some nice kerneldoc polish on top of all these patches?
>

I have something saved yes. However mostly they are irc logs where
I am chasing my own tail in a strong coffee induced stupor.

But after the gen8 parts, including 48bit have landed, we should
see if any naming/cleanups are needed and after that do
the kerneldoc polish.

I feel like I have overused my naming rebase quota already at
this stage.

- Mika

> Thanks, Daniel
>> 
>> >  drivers/gpu/drm/i915/i915_gem.c     |   2 +
>> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 164 +++++++++++++++++++++++++++++-------
>> >  drivers/gpu/drm/i915/i915_gem_gtt.h |   8 +-
>> >  drivers/gpu/drm/i915/i915_trace.h   |  99 ++++++++++++++++++++++
>> >  4 files changed, 239 insertions(+), 34 deletions(-)
>> >
>> > -- 
>> > 2.1.1
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx