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* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
@ 2015-04-08 13:20 Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common Sanchayan Maity
                   ` (6 more replies)
  0 siblings, 7 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

Hello,

This is the second version of the patchset which adds support for the 
Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested 
using the serial loader over UART.

First patch in the series refactors the DDR related code for use by both
the tower board and colibri modules. It also introduces a DDR3 based
JEDEC timing structure.

Second third and fourth patch in this series are improvement patches
related to RTC, SoC/CPU detection and caches.

Fifth patch introduces USB support for Vybrid modules. Much of the code
is similar to the ehci-mx6 driver. One open question here would be is
there a better way to take care of this similarity and perhaps share the
code base among the two drivers? Both host and client modes are working
and DFU has also been tested. Currently, we restrict the ports to be in
one of host and client mode.

Sixth patch adds the actual support for the Colibri modules.

Comments and feedback are most welcome.

The patchset is based and tested on the latest master branch as of
this writing.

Discussion on the version 1 of the patchset can be found at the below 
link:
https://www.mail-archive.com/u-boot at lists.denx.de/msg168136.html

Changes since v1:
- Rework the USB driver to use register offsets using the regular 
struct {} method
- Some cleanups and fixes in the sixth patch for the colibri_vf.h file 
which takes care of environment variables in uboot
- Purge some useless defines in the fifth and sixth patch which were 
related to USB.

- Sanchayan.

Sanchayan Maity (4):
  ARM: vf610: Move DDR3 initialization to imx-common
  ARM: vf610: Add SoC and CPU type detection
  usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
  ARM: vf610: Initial integration for Colibri VF50/VF61

Stefan Agner (2):
  ARM: vf610: Enable external 32KHz oscillator
  ARM: vf610: Enable caches

 arch/arm/Kconfig                              |   5 +
 arch/arm/cpu/armv7/vf610/generic.c            |  45 ++-
 arch/arm/imx-common/Makefile                  |   3 +
 arch/arm/imx-common/ddrmc-vf610.c             | 278 ++++++++++++++++++
 arch/arm/include/asm/arch-vf610/crm_regs.h    |  11 +
 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h |  72 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |  36 ++-
 arch/arm/include/asm/arch-vf610/regs-usbphy.h |  31 +++
 board/freescale/vf610twr/vf610twr.c           | 295 +++++---------------
 board/toradex/colibri_vf/Kconfig              |  18 ++
 board/toradex/colibri_vf/MAINTAINERS          |   6 +
 board/toradex/colibri_vf/Makefile             |   7 +
 board/toradex/colibri_vf/colibri_vf.c         | 387 ++++++++++++++++++++++++++
 board/toradex/colibri_vf/imximage.cfg         |  17 ++
 configs/colibri_vf_defconfig                  |   3 +
 drivers/usb/host/Makefile                     |   1 +
 drivers/usb/host/ehci-vf.c                    | 196 +++++++++++++
 include/configs/colibri_vf.h                  | 271 ++++++++++++++++++
 18 files changed, 1447 insertions(+), 235 deletions(-)
 create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
 create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
 create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
 create mode 100644 board/toradex/colibri_vf/Kconfig
 create mode 100644 board/toradex/colibri_vf/MAINTAINERS
 create mode 100644 board/toradex/colibri_vf/Makefile
 create mode 100644 board/toradex/colibri_vf/colibri_vf.c
 create mode 100644 board/toradex/colibri_vf/imximage.cfg
 create mode 100644 configs/colibri_vf_defconfig
 create mode 100644 drivers/usb/host/ehci-vf.c
 create mode 100644 include/configs/colibri_vf.h

-- 
2.3.5

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 2/6] ARM: vf610: Enable external 32KHz oscillator Sanchayan Maity
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/imx-common/Makefile                  |   3 +
 arch/arm/imx-common/ddrmc-vf610.c             | 278 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h |  72 +++++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   4 +-
 board/freescale/vf610twr/vf610twr.c           | 282 +++++---------------------
 5 files changed, 408 insertions(+), 231 deletions(-)
 create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
 create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 0000000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+
+void ddrmc_setup_iomux(void)
+{
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A14__DDR_A_14,
+		VF610_PAD_DDR_A13__DDR_A_13,
+		VF610_PAD_DDR_A12__DDR_A_12,
+		VF610_PAD_DDR_A11__DDR_A_11,
+		VF610_PAD_DDR_A10__DDR_A_10,
+		VF610_PAD_DDR_A9__DDR_A_9,
+		VF610_PAD_DDR_A8__DDR_A_8,
+		VF610_PAD_DDR_A7__DDR_A_7,
+		VF610_PAD_DDR_A6__DDR_A_6,
+		VF610_PAD_DDR_A5__DDR_A_5,
+		VF610_PAD_DDR_A4__DDR_A_4,
+		VF610_PAD_DDR_A3__DDR_A_3,
+		VF610_PAD_DDR_A2__DDR_A_2,
+		VF610_PAD_DDR_A1__DDR_A_1,
+		VF610_PAD_DDR_A0__DDR_A_0,
+		VF610_PAD_DDR_BA2__DDR_BA_2,
+		VF610_PAD_DDR_BA1__DDR_BA_1,
+		VF610_PAD_DDR_BA0__DDR_BA_0,
+		VF610_PAD_DDR_CAS__DDR_CAS_B,
+		VF610_PAD_DDR_CKE__DDR_CKE_0,
+		VF610_PAD_DDR_CLK__DDR_CLK_0,
+		VF610_PAD_DDR_CS__DDR_CS_B_0,
+		VF610_PAD_DDR_D15__DDR_D_15,
+		VF610_PAD_DDR_D14__DDR_D_14,
+		VF610_PAD_DDR_D13__DDR_D_13,
+		VF610_PAD_DDR_D12__DDR_D_12,
+		VF610_PAD_DDR_D11__DDR_D_11,
+		VF610_PAD_DDR_D10__DDR_D_10,
+		VF610_PAD_DDR_D9__DDR_D_9,
+		VF610_PAD_DDR_D8__DDR_D_8,
+		VF610_PAD_DDR_D7__DDR_D_7,
+		VF610_PAD_DDR_D6__DDR_D_6,
+		VF610_PAD_DDR_D5__DDR_D_5,
+		VF610_PAD_DDR_D4__DDR_D_4,
+		VF610_PAD_DDR_D3__DDR_D_3,
+		VF610_PAD_DDR_D2__DDR_D_2,
+		VF610_PAD_DDR_D1__DDR_D_1,
+		VF610_PAD_DDR_D0__DDR_D_0,
+		VF610_PAD_DDR_DQM1__DDR_DQM_1,
+		VF610_PAD_DDR_DQM0__DDR_DQM_0,
+		VF610_PAD_DDR_DQS1__DDR_DQS_1,
+		VF610_PAD_DDR_DQS0__DDR_DQS_0,
+		VF610_PAD_DDR_RAS__DDR_RAS_B,
+		VF610_PAD_DDR_WE__DDR_WE_B,
+		VF610_PAD_DDR_ODT1__DDR_ODT_0,
+		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+		VF610_PAD_DDR_RESETB,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+
+	/* LPDDR2 only parameter */
+	writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY50_DDR3_MODE |
+		   DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+
+	/* Processor Pad ODT settings */
+	writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
+}
+
+static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+
+	if (lvl->wrlvl_reg_en) {
+		writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
+		writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
+		writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
+	}
+
+	if (lvl->rdlvl_reg_en) {
+		cr102 |= DDRMC_CR102_RDLVL_REG_EN;
+		cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
+		cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
+	}
+
+	if (lvl->rdlvl_gt_reg_en) {
+		cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
+		cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
+		cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
+	}
+
+	writel(cr102, &ddrmr->cr[102]);
+	writel(cr105, &ddrmr->cr[105]);
+	writel(cr106, &ddrmr->cr[106]);
+	writel(cr110, &ddrmr->cr[110]);
+}
+
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+						  struct ddrmc_lvl_info *lvl,
+						  int col_diff, int row_diff)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(timings->wrlat) |
+		   DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
+		   DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
+		   DDRMC_CR14_TWTR(timings->twtr) |
+		   DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(timings->tmrd) |
+		   DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
+		   DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(timings->tckesr) |
+		   DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
+		   DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) |
+		   DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(timings->tref) |
+		   DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(timings->txsnr) |
+		   DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(timings->cksrx) |
+		   DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		   DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) |
+		   DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(timings->zqcl) |
+		   DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(timings->aprebit) |
+		   DDRMC_CR73_COL_DIFF(col_diff) |
+		   DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		   DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+		   &ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		   DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		   DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_Q_FULLNESS(7) |
+		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
+		   DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
+
+	if (lvl != NULL)
+		ddrmc_ctrl_lvl_init(lvl);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(0) |
+		   DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) |
+		   DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+		   DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+		   DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		   DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+		   DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) |
+		   DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
+	writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
+	writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
+		   DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		   DDRMC_CR139_PHY_WRLV_DLL(3) |
+		   DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
+	writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
+	writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+		   DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
+	writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+		   DDRMC_CR144_PHY_RDLV_DLL(3) |
+		   DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
+	writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
+	writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
+	writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
+	writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
+	writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		   DDRMC_CR154_PAD_ZQ_MODE(1) |
+		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
+		   DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+	writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+		   DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
+
+	ddrmc_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	while (!(readl(&ddrmr->cr[80]) && 0x100))
+		udelay(10);
+}
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
new file mode 100644
index 0000000..6730cde
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2015
+ * Toradex, Inc.
+ *
+ * Authors: Stefan Agner
+ *          Sanchayan Maity
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_VF610_DDRMC_H
+#define __ASM_ARCH_VF610_DDRMC_H
+
+struct ddrmc_lvl_info {
+	u16 wrlvl_reg_en;
+	u16 wrlvl_dl_0;
+	u16 wrlvl_dl_1;
+	u16 rdlvl_gt_reg_en;
+	u16 rdlvl_gt_dl_0;
+	u16 rdlvl_gt_dl_1;
+	u16 rdlvl_reg_en;
+	u16 rdlvl_dl_0;
+	u16 rdlvl_dl_1;
+};
+
+struct ddr3_jedec_timings {
+	u8 tinit;
+	u32 trst_pwron;
+	u32 cke_inactive;
+	u8 wrlat;
+	u8 caslat_lin;
+	u8 trc;
+	u8 trrd;
+	u8 tccd;
+	u8 tfaw;
+	u8 trp;
+	u8 twtr;
+	u8 tras_min;
+	u8 tmrd;
+	u8 trtp;
+	u32 tras_max;
+	u8 tmod;
+	u8 tckesr;
+	u8 tcke;
+	u8 trcd_int;
+	u8 tdal;
+	u16 tdll;
+	u8 trp_ab;
+	u16 tref;
+	u8 trfc;
+	u8 tpdex;
+	u8 txpdll;
+	u8 txsnr;
+	u16 txsr;
+	u8 cksrx;
+	u8 cksre;
+	u16 zqcl;
+	u16 zqinit;
+	u8 zqcs;
+	u8 ref_per_zq;
+	u8 aprebit;
+	u8 wlmrd;
+	u8 wldqsen;
+};
+
+void ddrmc_setup_iomux(void);
+void ddrmc_phy_init(void);
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+						  struct ddrmc_lvl_info *lvl,
+						  int col_diff, int row_diff);
+
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 6b10bdf..866b303 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -196,8 +196,8 @@
 #define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
 #define DDRMC_CR97_WRLVL_EN				(1 << 24)
-#define DDRMC_CR98_WRLVL_DL_0				(0)
-#define DDRMC_CR99_WRLVL_DL_1				(0)
+#define DDRMC_CR98_WRLVL_DL_0(v)			((v) & 0xffff)
+#define DDRMC_CR99_WRLVL_DL_1(v)			((v) & 0xffff)
 #define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
 #define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
 #define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index b634965..eb27542 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
@@ -27,240 +28,63 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
 			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
 
-void setup_iomux_ddr(void)
+int dram_init(void)
 {
-	static const iomux_v3_cfg_t ddr_pads[] = {
-		VF610_PAD_DDR_A15__DDR_A_15,
-		VF610_PAD_DDR_A14__DDR_A_14,
-		VF610_PAD_DDR_A13__DDR_A_13,
-		VF610_PAD_DDR_A12__DDR_A_12,
-		VF610_PAD_DDR_A11__DDR_A_11,
-		VF610_PAD_DDR_A10__DDR_A_10,
-		VF610_PAD_DDR_A9__DDR_A_9,
-		VF610_PAD_DDR_A8__DDR_A_8,
-		VF610_PAD_DDR_A7__DDR_A_7,
-		VF610_PAD_DDR_A6__DDR_A_6,
-		VF610_PAD_DDR_A5__DDR_A_5,
-		VF610_PAD_DDR_A4__DDR_A_4,
-		VF610_PAD_DDR_A3__DDR_A_3,
-		VF610_PAD_DDR_A2__DDR_A_2,
-		VF610_PAD_DDR_A1__DDR_A_1,
-		VF610_PAD_DDR_A0__DDR_A_0,
-		VF610_PAD_DDR_BA2__DDR_BA_2,
-		VF610_PAD_DDR_BA1__DDR_BA_1,
-		VF610_PAD_DDR_BA0__DDR_BA_0,
-		VF610_PAD_DDR_CAS__DDR_CAS_B,
-		VF610_PAD_DDR_CKE__DDR_CKE_0,
-		VF610_PAD_DDR_CLK__DDR_CLK_0,
-		VF610_PAD_DDR_CS__DDR_CS_B_0,
-		VF610_PAD_DDR_D15__DDR_D_15,
-		VF610_PAD_DDR_D14__DDR_D_14,
-		VF610_PAD_DDR_D13__DDR_D_13,
-		VF610_PAD_DDR_D12__DDR_D_12,
-		VF610_PAD_DDR_D11__DDR_D_11,
-		VF610_PAD_DDR_D10__DDR_D_10,
-		VF610_PAD_DDR_D9__DDR_D_9,
-		VF610_PAD_DDR_D8__DDR_D_8,
-		VF610_PAD_DDR_D7__DDR_D_7,
-		VF610_PAD_DDR_D6__DDR_D_6,
-		VF610_PAD_DDR_D5__DDR_D_5,
-		VF610_PAD_DDR_D4__DDR_D_4,
-		VF610_PAD_DDR_D3__DDR_D_3,
-		VF610_PAD_DDR_D2__DDR_D_2,
-		VF610_PAD_DDR_D1__DDR_D_1,
-		VF610_PAD_DDR_D0__DDR_D_0,
-		VF610_PAD_DDR_DQM1__DDR_DQM_1,
-		VF610_PAD_DDR_DQM0__DDR_DQM_0,
-		VF610_PAD_DDR_DQS1__DDR_DQS_1,
-		VF610_PAD_DDR_DQS0__DDR_DQS_0,
-		VF610_PAD_DDR_RAS__DDR_RAS_B,
-		VF610_PAD_DDR_WE__DDR_WE_B,
-		VF610_PAD_DDR_ODT1__DDR_ODT_0,
-		VF610_PAD_DDR_ODT0__DDR_ODT_1,
-		VF610_PAD_DDR_RESETB,
+	struct ddrmc_lvl_info lvl = {
+		.wrlvl_reg_en = 1,
+		.wrlvl_dl_0 = 0,
+		.wrlvl_dl_1 = 0,
+		.rdlvl_gt_reg_en = 1,
+		.rdlvl_gt_dl_0 = 4,
+		.rdlvl_gt_dl_1 = 4,
+		.rdlvl_reg_en = 1,
+		.rdlvl_dl_0 = 0,
+		.rdlvl_dl_1 = 0,
 	};
 
-	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
-
-void ddr_phy_init(void)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
-
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
-
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
-
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
-
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
-
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
-
-	/* LPDDR2 only parameter */
-	writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
-
-	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
-		&ddrmr->phy[50]);
-
-	/* Processor Pad ODT settings */
-	writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
-}
-
-void ddr_ctrl_init(void)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
-
-	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
-	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
-	writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
-
-	writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]);
-	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
-	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
-		&ddrmr->cr[13]);
-	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
-		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
-	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
-	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
-		&ddrmr->cr[17]);
-	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
-
-	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
-	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
-
-	writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]);
-	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
-	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
-
-	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
-	writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
-	writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
-	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
-
-	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
-	writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]);
-	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
-	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
-
-	writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
-	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
-		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
-
-	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
-	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
-		&ddrmr->cr[48]);
-
-	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
-	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
-	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
-
-	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
-	writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
-
-	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
-		DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
-	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
-		DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
-		&ddrmr->cr[74]);
-	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
-		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
-	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
-		DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
-	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
-		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
-	writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
-		&ddrmr->cr[78]);
-	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
-
-	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
-
-	writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
-	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
-	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
-
-	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
-	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
-	writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
-	writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
-	writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
-
-	writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
-		&ddrmr->cr[102]);
-
-	writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
-	writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
-	writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
-	writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
-	writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
-
-	writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0),
-		&ddrmr->cr[117]);
-	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
-		&ddrmr->cr[118]);
-
-	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
-		&ddrmr->cr[120]);
-	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
-		&ddrmr->cr[121]);
-	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
-		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
-	writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
-		DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
-	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
-
-	writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
-	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
-		&ddrmr->cr[132]);
-	writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
-	writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
-		&ddrmr->cr[138]);
-	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
-		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
-		&ddrmr->cr[139]);
-	writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
-	writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
-		&ddrmr->cr[143]);
-	writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
-		DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),
-		&ddrmr->cr[144]);
-	writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
-	writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
-	writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
-	writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
-	writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
-		DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
-
-	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
-		DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
-	writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2),
-		&ddrmr->cr[155]);
-	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
-	writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
-		DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
-
-	ddr_phy_init();
-
-	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
-
-	udelay(200);
-}
+	static const struct ddr3_jedec_timings timings = {
+		.tinit           = 5,
+		.trst_pwron      = 80000,
+		.cke_inactive    = 200000,
+		.wrlat           = 5,
+		.caslat_lin      = 12,
+		.trc             = 21,
+		.trrd            = 4,
+		.tccd            = 4,
+		.tfaw            = 20,
+		.trp             = 6,
+		.twtr            = 4,
+		.tras_min        = 15,
+		.tmrd            = 4,
+		.trtp            = 4,
+		.tras_max        = 28080,
+		.tmod            = 12,
+		.tckesr          = 4,
+		.tcke            = 3,
+		.trcd_int        = 6,
+		.tdal            = 12,
+		.tdll            = 512,
+		.trp_ab          = 6,
+		.tref            = 3120,
+		.trfc            = 44,
+		.tpdex           = 3,
+		.txpdll          = 10,
+		.txsnr           = 48,
+		.txsr            = 468,
+		.cksrx           = 5,
+		.cksre           = 5,
+		.zqcl            = 256,
+		.zqinit          = 512,
+		.zqcs            = 64,
+		.ref_per_zq      = 64,
+		.aprebit         = 10,
+		.wlmrd           = 40,
+		.wldqsen         = 25,
+	};
 
-int dram_init(void)
-{
-	setup_iomux_ddr();
+	ddrmc_setup_iomux();
 
-	ddr_ctrl_init();
+	ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 	return 0;
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 2/6] ARM: vf610: Enable external 32KHz oscillator
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 3/6] ARM: vf610: Add SoC and CPU type detection Sanchayan Maity
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

From: Stefan Agner <stefan@agner.ch>

Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h |  1 +
 arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++++++++++-
 board/freescale/vf610twr/vf610twr.c        | 13 ++++++++++++-
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
 #define QSPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00044000)
 #define IOMUXC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00048000)
 #define ANADIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00050000)
-#define SCSCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
 
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN            0x1
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
@@ -448,6 +451,12 @@ struct mscm_ir {
 	u16 rsvd3[848];
 };
 
+/* SCSC */
+struct scsc_reg {
+	u32 sirc_ctr;
+	u32 sosc_ctr;
+};
+
 #endif	/* __ASSEMBLER__*/
 
 #endif	/* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
 		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
 		CCM_CCGR2_QSPI0_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
-		CCM_CCGR3_ANADIG_CTRL_MASK);
+		CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 		CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+	 * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
 	return 0;
 }
 
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 3/6] ARM: vf610: Add SoC and CPU type detection
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 2/6] ARM: vf610: Enable external 32KHz oscillator Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches Sanchayan Maity
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/cpu/armv7/vf610/generic.c         | 29 +++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-vf610/imx-regs.h | 12 ++++++++++++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+static char soc_type[] = "xx0";
+
 #ifdef CONFIG_MXC_OCOTP
 void enable_ocotp_clk(unsigned char enable)
 {
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
 
 int print_cpuinfo(void)
 {
-	printf("CPU:   Freescale Vybrid VF610 at %d MHz\n",
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
+	       soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	printf("Reset cause: %s\n", get_reset_cause());
 
 	return 0;
 }
 #endif
 
+int arch_cpu_init(void)
+{
+	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+	soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
+	soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char soc[6];
+
+	strcat(soc, "vf");
+	strcat(soc, soc_type);
+	setenv("soc", soc);
+
+	return 0;
+}
+#endif
+
 int cpu_eth_init(bd_t *bis)
 {
 	int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
 	u32 sosc_ctr;
 };
 
+/* MSCM */
+struct mscm {
+	u32 cpxtype;
+	u32 cpxnum;
+	u32 cpxmaster;
+	u32 cpxcount;
+	u32 cpxcfg0;
+	u32 cpxcfg1;
+	u32 cpxcfg2;
+	u32 cpxcfg3;
+};
+
 #endif	/* __ASSEMBLER__*/
 
 #endif	/* __ASM_ARCH_IMX_REGS_H__ */
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
                   ` (2 preceding siblings ...)
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 3/6] ARM: vf610: Add SoC and CPU type detection Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's Sanchayan Maity
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

From: Stefan Agner <stefan@agner.ch>

Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/cpu/armv7/vf610/generic.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
 #endif
 	return 0;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+	enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+	dcache_enable();
+	icache_enable();
+
+    /* Enable caching on OCRAM */
+	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
                   ` (3 preceding siblings ...)
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-12 23:29   ` Marek Vasut
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61 Sanchayan Maity
  2015-04-11 16:46 ` [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Marek Vasut
  6 siblings, 1 reply; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h    |  10 ++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |   4 +
 arch/arm/include/asm/arch-vf610/regs-usbphy.h |  31 ++++
 drivers/usb/host/Makefile                     |   1 +
 drivers/usb/host/ehci-vf.c                    | 196 ++++++++++++++++++++++++++
 5 files changed, 242 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
 create mode 100644 drivers/usb/host/ehci-vf.c

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..bc6db2a 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -189,6 +189,7 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
@@ -207,14 +208,23 @@ struct anadig_reg {
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
 #define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 #define CCM_CCGR10_NFC_CTRL_MASK		0x3
 
+#define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
 #define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
 #define ANADIG_PLL5_CTRL_DIV_SELECT		1
+#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
 #define ANADIG_PLL2_CTRL_DIV_SELECT		1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
 #define SAI2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00031000)
 #define SAI3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00032000)
 #define CRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR     (AIPS0_BASE_ADDR + 0x00034000)
 #define PDB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00036000)
 #define PIT_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00037000)
 #define FTM0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
 #define QSPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00044000)
 #define IOMUXC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00048000)
 #define ANADIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00050000)
+#define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
 #define DDR_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0002E000)
 #define ESDHC0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00031000)
 #define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
diff --git a/arch/arm/include/asm/arch-vf610/regs-usbphy.h b/arch/arm/include/asm/arch-vf610/regs-usbphy.h
new file mode 100644
index 0000000..b1b8876
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/regs-usbphy.h
@@ -0,0 +1,31 @@
+/*
+ * Freescale Vybrid USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#include <asm/imx-common/regs-common.h>
+
+struct vf_usbphy_regs {
+	mxs_reg_32(hw_usbphy_pwd)
+	mxs_reg_32(hw_usbphy_tx)
+	mxs_reg_32(hw_usbphy_rx)
+	mxs_reg_32(hw_usbphy_ctrl)
+	mxs_reg_32(hw_usbphy_status)
+	mxs_reg_32(hw_usbphy_debug)
+	mxs_reg_32(hw_usbphy_debug0_status)
+	mxs_reg_32(hw_usbphy_debug1)
+	mxs_reg_32(hw_usbphy_version)
+	mxs_reg_32(hw_usbphy_ip)
+};
+
+#define USBPHY_CTRL_ENUTMILEVEL2		(1 << 14)
+#define USBPHY_CTRL_ENUTMILEVEL3		(1 << 15)
+#define USBPHY_CTRL_OTG_ID              (1 << 27)
+#define USBPHY_CTRL_CLKGATE				(1 << 30)
+#define USBPHY_CTRL_SFTRST				(1 << 31)
+
+#endif	/* __REGS_USBPHY_H__ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6f34b..4bd9321 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
new file mode 100644
index 0000000..cbd3c8c
--- /dev/null
+++ b/drivers/usb/host/ehci-vf.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
+ * Copyright (C) 2015 Toradex AG
+ *
+ * Based on ehci-mx6 and ehci-mxs driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/regs-usbphy.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <usb/ehci-fsl.h>
+
+#include "ehci.h"
+
+#define ANADIG_PLL_CTRL_EN_USB_CLKS     (1 << 6)
+
+#define USB_NC_REG_OFFSET				0x00000800
+
+#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
+
+/* USBCMD */
+#define UCMD_RUN_STOP		(1 << 0) /* controller run/stop */
+#define UCMD_RESET			(1 << 1) /* controller reset */
+
+struct ehci_vf_port {
+	uint32_t                 usb_regs;
+	struct vf_usbphy_regs   *phy_regs;
+	struct anadig_reg       *pll;
+	uint32_t                 pll_en_bits;
+};
+
+static const struct ehci_vf_port vf_port[] = {
+	{
+		USBC0_BASE_ADDR,
+		(struct vf_usbphy_regs *)USB_PHY0_BASE_ADDR,
+		(struct anadig_reg *)ANADIG_BASE_ADDR,
+		ANADIG_PLL3_CTRL_ENABLE | ANADIG_PLL3_CTRL_POWERDOWN
+		| ANADIG_PLL_CTRL_EN_USB_CLKS,
+	},
+	{
+		USBC1_BASE_ADDR,
+		(struct vf_usbphy_regs *)USB_PHY1_BASE_ADDR,
+		(struct anadig_reg *)ANADIG_BASE_ADDR,
+		ANADIG_PLL7_CTRL_ENABLE | ANADIG_PLL7_CTRL_POWERDOWN
+		| ANADIG_PLL_CTRL_EN_USB_CLKS,
+	},
+};
+
+static void usb_internal_phy_clock_gate(int index)
+{
+	const struct ehci_vf_port *port;
+
+	port = &vf_port[index];
+	writel(USBPHY_CTRL_CLKGATE, &port->phy_regs->hw_usbphy_ctrl_clr);
+}
+
+static void usb_power_config(int index)
+{
+	u32 reg;
+	const struct ehci_vf_port *port;
+
+	port = &vf_port[index];
+
+	switch (index) {
+	case 0:
+			reg = readl(&port->pll->pll3_ctrl);
+			reg &= ~ANADIG_PLL3_CTRL_BYPASS;
+			writel(reg, &port->pll->pll3_ctrl);
+
+			reg = readl(&port->pll->pll3_ctrl);
+			reg |= port->pll_en_bits;
+			writel(reg, &port->pll->pll3_ctrl);
+		break;
+	case 1:
+			reg = readl(&port->pll->pll7_ctrl);
+			reg &= ~ANADIG_PLL7_CTRL_BYPASS;
+			writel(reg, &port->pll->pll7_ctrl);
+
+			reg = readl(&port->pll->pll7_ctrl);
+			reg |= port->pll_en_bits;
+			writel(reg, &port->pll->pll7_ctrl);
+		break;
+	default:
+		return;
+	}
+}
+
+static void usb_phy_enable(int index, struct usb_ehci *ehci)
+{
+	u32 val;
+	void __iomem *usb_cmd;
+	const struct ehci_vf_port *port;
+
+	port = &vf_port[index];
+	usb_cmd = (void __iomem *)&ehci->usbcmd;
+
+	/* Stop then Reset */
+	val = readl(usb_cmd);
+	val &= ~UCMD_RUN_STOP;
+	writel(val, usb_cmd);
+	while (readl(usb_cmd) & UCMD_RUN_STOP)
+		;
+
+	val = readl(usb_cmd);
+	val |= UCMD_RESET;
+	writel(val, usb_cmd);
+	while (readl(usb_cmd) & UCMD_RESET)
+		;
+
+	/* Reset USBPHY module */
+	writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
+	udelay(10);
+
+	/* Remove CLKGATE and SFTRST */
+	writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST,
+	       &port->phy_regs->hw_usbphy_ctrl_clr);
+	udelay(10);
+
+	/* Power up the PHY */
+	writel(0, &port->phy_regs->hw_usbphy_pwd);
+
+	/* enable FS/LS device */
+	writel(USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3,
+	       &port->phy_regs->hw_usbphy_ctrl_set);
+}
+
+static void usb_oc_config(int index)
+{
+	u32 val;
+	const struct ehci_vf_port *port;
+
+	port = &vf_port[index];
+
+	val = readl(&port->usb_regs + USB_NC_REG_OFFSET);
+	val |= UCTRL_OVER_CUR_POL;
+	writel(val, &port->usb_regs + USB_NC_REG_OFFSET);
+
+	val = readl(&port->usb_regs + USB_NC_REG_OFFSET);
+	val |= UCTRL_OVER_CUR_DIS;
+	writel(val, &port->usb_regs + USB_NC_REG_OFFSET);
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	struct usb_ehci *ehci;
+	const struct ehci_vf_port *port;
+
+	if (index >= ARRAY_SIZE(vf_port))
+		return -EINVAL;
+
+	if (init == USB_INIT_DEVICE && index == 1)
+		return -ENODEV;
+	if (init == USB_INIT_HOST && index == 0)
+		return -ENODEV;
+
+	port = &vf_port[index];
+
+	ehci = (struct usb_ehci *)(port->usb_regs);
+
+	usb_power_config(index);
+	usb_oc_config(index);
+	usb_internal_phy_clock_gate(index);
+	usb_phy_enable(index, ehci);
+
+	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+	if (init == USB_INIT_DEVICE) {
+		setbits_le32(&ehci->usbmode, CM_DEVICE);
+		writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+		setbits_le32(&ehci->portsc, USB_EN);
+	} else if (init == USB_INIT_HOST) {
+		setbits_le32(&ehci->usbmode, CM_HOST);
+		writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+		setbits_le32(&ehci->portsc, USB_EN);
+	}
+
+	return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+	return 0;
+}
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
                   ` (4 preceding siblings ...)
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's Sanchayan Maity
@ 2015-04-08 13:20 ` Sanchayan Maity
  2015-04-11 16:46 ` [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Marek Vasut
  6 siblings, 0 replies; 22+ messages in thread
From: Sanchayan Maity @ 2015-04-08 13:20 UTC (permalink / raw)
  To: u-boot

This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.

- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
  - for VF50, use PLL2 as memory clock (synchronous mode)
  - for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
- USB host and client support

Tested on Colibri VF50/VF61 booting using serial loader over UART.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
 arch/arm/Kconfig                           |   5 +
 arch/arm/include/asm/arch-vf610/imx-regs.h |   5 +
 board/toradex/colibri_vf/Kconfig           |  18 ++
 board/toradex/colibri_vf/MAINTAINERS       |   6 +
 board/toradex/colibri_vf/Makefile          |   7 +
 board/toradex/colibri_vf/colibri_vf.c      | 387 +++++++++++++++++++++++++++++
 board/toradex/colibri_vf/imximage.cfg      |  17 ++
 configs/colibri_vf_defconfig               |   3 +
 include/configs/colibri_vf.h               | 271 ++++++++++++++++++++
 9 files changed, 719 insertions(+)
 create mode 100644 board/toradex/colibri_vf/Kconfig
 create mode 100644 board/toradex/colibri_vf/MAINTAINERS
 create mode 100644 board/toradex/colibri_vf/Makefile
 create mode 100644 board/toradex/colibri_vf/colibri_vf.c
 create mode 100644 board/toradex/colibri_vf/imximage.cfg
 create mode 100644 configs/colibri_vf_defconfig
 create mode 100644 include/configs/colibri_vf.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80b0d34..e32a942 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -608,6 +608,10 @@ config TARGET_VF610TWR
 	bool "Support vf610twr"
 	select CPU_V7
 
+config TARGET_COLIBRI_VF
+	bool "Support Colibri VF50/61"
+	select CPU_V7
+
 config ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7
@@ -864,6 +868,7 @@ source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
+source "board/toradex/colibri_vf/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 26057fe..a7d765a 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -267,6 +267,11 @@
 #define SRC_SRSR_WDOG_M4				(0x1 << 4)
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT            24
+#define SRC_SBMR2_BMOD_FUSES            0x0
+#define SRC_SBMR2_BMOD_SERIAL           0x1
+#define SRC_SBMR2_BMOD_RCON             0x2
 
 /* Slow Clock Source Controller Module (SCSC) */
 #define SCSC_SOSC_CTR_SOSC_EN            0x1
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
new file mode 100644
index 0000000..2c3cb30
--- /dev/null
+++ b/board/toradex/colibri_vf/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_COLIBRI_VF
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "colibri_vf"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_SOC
+	default "vf610"
+
+config SYS_CONFIG_NAME
+	default "colibri_vf"
+
+endif
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
new file mode 100644
index 0000000..551c575
--- /dev/null
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -0,0 +1,6 @@
+Colibri VFxx
+M:	Stefan Agner <stefan.agner@toradex.com>
+S:	Maintained
+F:	board/toradex/colibri_vf/
+F:	include/configs/colibri_vf.h
+F:	configs/colibri_vf_defconfig
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
new file mode 100644
index 0000000..c7e5134
--- /dev/null
+++ b/board/toradex/colibri_vf/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= colibri_vf.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
new file mode 100644
index 0000000..3667779
--- /dev/null
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr.c:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <g_dnl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+int dram_init(void)
+{
+	static const struct ddr3_jedec_timings timings = {
+		.tinit           = 5,
+		.trst_pwron      = 80000,
+		.cke_inactive    = 200000,
+		.wrlat           = 5,
+		.caslat_lin      = 12,
+		.trc             = 21,
+		.trrd            = 4,
+		.tccd            = 4,
+		.tfaw            = 20,
+		.trp             = 6,
+		.twtr            = 4,
+		.tras_min        = 15,
+		.tmrd            = 4,
+		.trtp            = 4,
+		.tras_max        = 28080,
+		.tmod            = 12,
+		.tckesr          = 4,
+		.tcke            = 3,
+		.trcd_int        = 6,
+		.tdal            = 12,
+		.tdll            = 512,
+		.trp_ab          = 6,
+		.tref            = 3120,
+		.trfc            = 64,
+		.tpdex           = 3,
+		.txpdll          = 10,
+		.txsnr           = 48,
+		.txsr            = 468,
+		.cksrx           = 5,
+		.cksre           = 5,
+		.zqcl            = 256,
+		.zqinit          = 512,
+		.zqcs            = 64,
+		.ref_per_zq      = 64,
+		.aprebit         = 10,
+		.wlmrd           = 40,
+		.wldqsen         = 25,
+	};
+
+	ddrmc_setup_iomux();
+
+	ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	static const iomux_v3_cfg_t enet0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c0_pads[] = {
+		VF610_PAD_PTB14__I2C0_SCL,
+		VF610_PAD_PTB15__I2C0_SDA,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+	static const iomux_v3_cfg_t nfc_pads[] = {
+		VF610_PAD_PTD23__NF_IO7,
+		VF610_PAD_PTD22__NF_IO6,
+		VF610_PAD_PTD21__NF_IO5,
+		VF610_PAD_PTD20__NF_IO4,
+		VF610_PAD_PTD19__NF_IO3,
+		VF610_PAD_PTD18__NF_IO2,
+		VF610_PAD_PTD17__NF_IO1,
+		VF610_PAD_PTD16__NF_IO0,
+		VF610_PAD_PTB24__NF_WE_B,
+		VF610_PAD_PTB25__NF_CE0_B,
+		VF610_PAD_PTB27__NF_RE_B,
+		VF610_PAD_PTC26__NF_RB_B,
+		VF610_PAD_PTC27__NF_ALE,
+		VF610_PAD_PTC28__NF_CLE
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t esdhc1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static inline int is_colibri_vf61(void)
+{
+	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+	/*
+	 * Detect board type by Level 2 Cache: VF50 don't have any
+	 * Level 2 Cache.
+	 */
+	return !!mscm->cpxcfg1;
+}
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+	u32 pfd_clk_sel, ddr_clk_sel;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+			CCM_CCGR0_UART0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+			CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK |
+			CCM_CCGR1_USBC0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+			CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+			CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+			CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+			CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+			CCM_CCGR7_SDHC1_CTRL_MASK | CCM_CCGR7_USBC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+			CCM_CCGR10_NFC_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
+			ANADIG_PLL7_CTRL_POWERDOWN |
+			ANADIG_PLL7_CTRL_DIV_SELECT,
+			ANADIG_PLL7_CTRL_ENABLE);
+	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+			ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
+			ANADIG_PLL5_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+			ANADIG_PLL3_CTRL_POWERDOWN |
+			ANADIG_PLL3_CTRL_DIV_SELECT,
+			ANADIG_PLL3_CTRL_ENABLE);
+
+	if (is_colibri_vf61()) {
+		clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+				ANADIG_PLL2_CTRL_POWERDOWN,
+				ANADIG_PLL2_CTRL_ENABLE |
+				ANADIG_PLL2_CTRL_DIV_SELECT);
+	}
+
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+			ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+			CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+
+	/* See "Typical PLL Configuration" */
+	if (is_colibri_vf61()) {
+		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
+		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
+	} else {
+		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
+		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
+	}
+
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
+			CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
+			CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
+			CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
+			CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
+			ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
+			CCM_CCSR_SYS_CLK_SEL(4));
+
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+			CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+			CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+			CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
+			CCM_CSCMR1_NFC_CLK_SEL(0));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+			CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+			CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+			CCM_CSCDR2_NFC_EN);
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+			CCM_CSCDR3_NFC_PRE_DIV(5));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+			CCM_CSCMR2_RMII_CLK_SEL(2));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+	setup_iomux_i2c();
+#ifdef CONFIG_NAND_VF610_NFC
+	setup_iomux_nfc();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+
+	/* Default memory arguments */
+	if (!getenv("memargs")) {
+		switch (gd->ram_size) {
+		case 0x08000000:
+			/* 128 MB */
+			setenv("memargs", "mem=128M");
+			break;
+		case 0x10000000:
+			/* 256 MB */
+			setenv("memargs", "mem=256M");
+			break;
+		default:
+			printf("Failed detecting RAM size.\n");
+		}
+	}
+
+	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
+			== SRC_SBMR2_BMOD_SERIAL) {
+		printf("Serial Downloader recovery mode, disable autoboot\n");
+		setenv("bootdelay", "-1");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+int board_init(void)
+{
+	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+	 * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+
+	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_colibri_vf61())
+		puts("Board: Colibri VF61\n");
+	else
+		puts("Board: Colibri VF50\n");
+
+	return 0;
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	put_unaligned(CONFIG_TRDX_VID, &dev->idVendor);
+
+	if (is_colibri_vf61())
+		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
+	else
+		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
+
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg
new file mode 100644
index 0000000..8c52886
--- /dev/null
+++ b/board/toradex/colibri_vf/imximage.cfg
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
new file mode 100644
index 0000000..cef5a9e
--- /dev/null
+++ b/configs/colibri_vf_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_COLIBRI_VF=y
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
new file mode 100644
index 0000000..7d205de
--- /dev/null
+++ b/include/configs/colibri_vf.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex VF50/VF61 module.
+ *
+ * Based on vf610twr.h:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE			UART0_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_CMD_ASKENV
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=vf610_nfc"
+#define MTDPARTS_DEFAULT	"mtdparts=vf610_nfc:"		\
+				"128k(vf-bcb)ro,"		\
+				"1408k(u-boot)ro,"		\
+				"512k(u-boot-env),"		\
+				"-(ubi)"
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET1_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_LOADADDR			0x80008000
+#define CONFIG_FDTADDR			0x84000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_SYS_TEXT_BASE		0x3f408000
+#define CONFIG_BOARD_SIZE_LIMIT		524288
+
+#define SD_BOOTCMD \
+	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
+	"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
+	"nfsboot=run setup; " \
+	"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+	"dhcp ${kernel_addr_r} && "	\
+	"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD	\
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+	"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+	"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} "   \
+	"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+	"ubi part ubi && ubifsmount ubi0:rootfs && " \
+	"ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
+	"ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+
+#define DFU_ALT_NAND_INFO	"vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x84000000\0" \
+	"kernel_file=zImage\0" \
+	"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
+	"fdt_board=eval-v3\0" \
+	"defargs=\0" \
+	"console=ttyLP0\0" \
+	"setup=setenv setupargs " \
+	"console=tty1 console=${console}" \
+	",${baudrate}n8 ${memargs}\0" \
+	"setsdupdate=mmc rescan && set interface mmc && " \
+	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+	"source ${loadaddr}\0" \
+	"setusbupdate=usb start && set interface usb && " \
+	"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+	"source ${loadaddr}\0" \
+	"setupdate=run setsdupdate || run setusbupdate\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	SD_BOOTCMD \
+	NFS_BOOTCMD \
+	UBI_BOOTCMD
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"Colibri VFxx # "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_RANGE		(4 * 64 * 2048)
+#define CONFIG_ENV_OFFSET		(12 * 64 * 2048)
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/* USB Host support */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_VF
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* USB Client Support */
+#define CONFIG_USB_GADGET
+#define CONFIG_CI_UDC
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_TRDX_VID                   0x1B67
+#define CONFIG_TRDX_PID_COLIBRI_VF50      0x0016
+#define CONFIG_TRDX_PID_COLIBRI_VF61      0x0017
+#define CONFIG_TRDX_PID_COLIBRI_VF61IT    0x0018
+#define CONFIG_TRDX_PID_COLIBRI_VF50IT    0x0019
+#define CONFIG_G_DNL_MANUFACTURER         "Toradex"
+#define CONFIG_G_DNL_VENDOR_NUM           CONFIG_TRDX_VID
+#define CONFIG_G_DNL_PRODUCT_NUM          CONFIG_TRDX_PID_COLIBRI_VF50
+
+/* USB DFU */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024)
+
+/* USB Storage */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#endif /* __CONFIG_H */
-- 
2.3.5

^ permalink raw reply related	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
                   ` (5 preceding siblings ...)
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61 Sanchayan Maity
@ 2015-04-11 16:46 ` Marek Vasut
  2015-04-12  5:33   ` maitysanchayan at gmail.com
  6 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2015-04-11 16:46 UTC (permalink / raw)
  To: u-boot

On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> Hello,
> 
> This is the second version of the patchset which adds support for the
> Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
> using the serial loader over UART.

Hi!

Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way, we
can solve 5/6 separately, since it might need some further dicussion. I
don't want that patch to block the rest of the series though.

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-11 16:46 ` [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Marek Vasut
@ 2015-04-12  5:33   ` maitysanchayan at gmail.com
  2015-04-12 23:28     ` Marek Vasut
  0 siblings, 1 reply; 22+ messages in thread
From: maitysanchayan at gmail.com @ 2015-04-12  5:33 UTC (permalink / raw)
  To: u-boot

Hi,

On 15-04-11 18:46:15, Marek Vasut wrote:
> On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > Hello,
> > 
> > This is the second version of the patchset which adds support for the
> > Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
> > using the serial loader over UART.
> 
> Hi!
> 
> Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way, we
> can solve 5/6 separately, since it might need some further dicussion. I
> don't want that patch to block the rest of the series though.

The sixth patch has some minor dependencies on the fifth patch like some 
#defines and configuration we enable for Colibri. In case the fifth 
patch will require some more discussion and time, then I guess I will 
need to rework the sixth patch and then everything related to USB can 
go in a later patch. The rework will be minor. So the v3 will be without 
USB support and USB will go in later once this gets applied. Perhaps we
will send the USB along with some more other featureset addition like
gpio support for Vybrid which my colleague did recently along with some
driver model/dt stuff.

By the way, where the fifth patch is concerned, is it related to the 
discussion Fabio pointed out in the discussion on first version of the 
patch? uboot trying to get rid of the 'no register access via offset' 
rule? Anything required I can rework accordingly.

Thanks & Regards,
Sanchayan Maity.

> 
> Best regards,
> Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-12  5:33   ` maitysanchayan at gmail.com
@ 2015-04-12 23:28     ` Marek Vasut
  2015-04-13  1:36       ` Fabio Estevam
  2015-04-13  6:21       ` maitysanchayan at gmail.com
  0 siblings, 2 replies; 22+ messages in thread
From: Marek Vasut @ 2015-04-12 23:28 UTC (permalink / raw)
  To: u-boot

On Sunday, April 12, 2015 at 07:33:41 AM, maitysanchayan at gmail.com wrote:
> Hi,
> 
> On 15-04-11 18:46:15, Marek Vasut wrote:
> > On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > > Hello,
> > > 
> > > This is the second version of the patchset which adds support for the
> > > Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
> > > using the serial loader over UART.
> > 
> > Hi!
> > 
> > Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way, we
> > can solve 5/6 separately, since it might need some further dicussion. I
> > don't want that patch to block the rest of the series though.
> 
> The sixth patch has some minor dependencies on the fifth patch like some
> #defines and configuration we enable for Colibri. In case the fifth
> patch will require some more discussion and time, then I guess I will
> need to rework the sixth patch and then everything related to USB can
> go in a later patch. The rework will be minor. So the v3 will be without
> USB support

Well, if you want to rework the 6th patch, that'd be very nice of you :)

> and USB will go in later once this gets applied. Perhaps we
> will send the USB along with some more other featureset addition like
> gpio support for Vybrid which my colleague did recently along with some
> driver model/dt stuff.

My impression is that the USB is just a matter of figuring out where the
PHY registers go -- whether in arch/arm/include/imx-common or into
include/usb/ . I'd be more inclined for the later, since the PHY regs
looks like chipidea IP specific thing, but I might be wrong.

> By the way, where the fifth patch is concerned, is it related to the
> discussion Fabio pointed out in the discussion on first version of the
> patch? uboot trying to get rid of the 'no register access via offset'
> rule? Anything required I can rework accordingly.

I was concerned about the placement of the PHY reg definition. I didn't
hear from Fabio on the result of this decision and I don't really mind
that either way.

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
  2015-04-08 13:20 ` [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's Sanchayan Maity
@ 2015-04-12 23:29   ` Marek Vasut
  2015-04-13  5:37     ` maitysanchayan at gmail.com
  0 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2015-04-12 23:29 UTC (permalink / raw)
  To: u-boot

On Wednesday, April 08, 2015 at 03:20:09 PM, Sanchayan Maity wrote:
> This driver adds support for the USB peripheral on Freescale Vybrid
> SoC's.
> 
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
>  arch/arm/include/asm/arch-vf610/crm_regs.h    |  10 ++
>  arch/arm/include/asm/arch-vf610/imx-regs.h    |   4 +
>  arch/arm/include/asm/arch-vf610/regs-usbphy.h |  31 ++++
>  drivers/usb/host/Makefile                     |   1 +
>  drivers/usb/host/ehci-vf.c                    | 196
> ++++++++++++++++++++++++++ 5 files changed, 242 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
>  create mode 100644 drivers/usb/host/ehci-vf.c

A general hint, you can replace sequences of code like this:

var = readl(foo);
var |= BIT_BAR;
writel(var, addr);

with

setbits_le32(var, BIT_BAR);

Same applies for clearing -- clrbits_le32() and both setting and
clearing -- clrsetbits_le32().

Thanks!

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-12 23:28     ` Marek Vasut
@ 2015-04-13  1:36       ` Fabio Estevam
  2015-04-13  3:41         ` Marek Vasut
  2015-04-13  6:21       ` maitysanchayan at gmail.com
  1 sibling, 1 reply; 22+ messages in thread
From: Fabio Estevam @ 2015-04-13  1:36 UTC (permalink / raw)
  To: u-boot

Hi Marek,

On Sun, Apr 12, 2015 at 8:28 PM, Marek Vasut <marex@denx.de> wrote:

> I was concerned about the placement of the PHY reg definition. I didn't
> hear from Fabio on the result of this decision and I don't really mind
> that either way.

I thought that maybe we should relax about the 'register access via
offset is forbidden' rule for new code submission, as according to Tom
he would like to see this going away in the future:
https://www.marc.info/?l=u-boot&m=142609602127309&w=2

Regards,

Fabio Estevam

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-13  1:36       ` Fabio Estevam
@ 2015-04-13  3:41         ` Marek Vasut
  0 siblings, 0 replies; 22+ messages in thread
From: Marek Vasut @ 2015-04-13  3:41 UTC (permalink / raw)
  To: u-boot

On Monday, April 13, 2015 at 03:36:56 AM, Fabio Estevam wrote:
> Hi Marek,
> 
> On Sun, Apr 12, 2015 at 8:28 PM, Marek Vasut <marex@denx.de> wrote:
> > I was concerned about the placement of the PHY reg definition. I didn't
> > hear from Fabio on the result of this decision and I don't really mind
> > that either way.
> 
> I thought that maybe we should relax about the 'register access via
> offset is forbidden' rule for new code submission, as according to Tom
> he would like to see this going away in the future:
> https://www.marc.info/?l=u-boot&m=142609602127309&w=2

Hi,

OK, I'm fine with that. But this discussion is not about the register access,
but about placing register definition which is common to three different SoC
families into the correct place. Did I miss something please ?

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
  2015-04-12 23:29   ` Marek Vasut
@ 2015-04-13  5:37     ` maitysanchayan at gmail.com
  2015-04-13  5:49       ` Marek Vasut
  0 siblings, 1 reply; 22+ messages in thread
From: maitysanchayan at gmail.com @ 2015-04-13  5:37 UTC (permalink / raw)
  To: u-boot

Hello,

On 15-04-13 01:29:39, Marek Vasut wrote:
> On Wednesday, April 08, 2015 at 03:20:09 PM, Sanchayan Maity wrote:
> > This driver adds support for the USB peripheral on Freescale Vybrid
> > SoC's.
> > 
> > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> > ---
> >  arch/arm/include/asm/arch-vf610/crm_regs.h    |  10 ++
> >  arch/arm/include/asm/arch-vf610/imx-regs.h    |   4 +
> >  arch/arm/include/asm/arch-vf610/regs-usbphy.h |  31 ++++
> >  drivers/usb/host/Makefile                     |   1 +
> >  drivers/usb/host/ehci-vf.c                    | 196
> > ++++++++++++++++++++++++++ 5 files changed, 242 insertions(+)
> >  create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
> >  create mode 100644 drivers/usb/host/ehci-vf.c
> 
> A general hint, you can replace sequences of code like this:
> 
> var = readl(foo);
> var |= BIT_BAR;
> writel(var, addr);
> 
> with
> 
> setbits_le32(var, BIT_BAR);
> 
> Same applies for clearing -- clrbits_le32() and both setting and
> clearing -- clrsetbits_le32().

Sorry about that. It is something which I use in the sixth patch 
as well in the board files but it skipped my mind while doing this 
driver. Will take care of it in v3 which seems imminent.

Noted, thanks :).

- Sanchayan.

> 
> Thanks!
> 
> Best regards,
> Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
  2015-04-13  5:37     ` maitysanchayan at gmail.com
@ 2015-04-13  5:49       ` Marek Vasut
  0 siblings, 0 replies; 22+ messages in thread
From: Marek Vasut @ 2015-04-13  5:49 UTC (permalink / raw)
  To: u-boot

On Monday, April 13, 2015 at 07:37:42 AM, maitysanchayan at gmail.com wrote:
> Hello,
> 
> On 15-04-13 01:29:39, Marek Vasut wrote:
> > On Wednesday, April 08, 2015 at 03:20:09 PM, Sanchayan Maity wrote:
> > > This driver adds support for the USB peripheral on Freescale Vybrid
> > > SoC's.
> > > 
> > > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> > > ---
> > > 
> > >  arch/arm/include/asm/arch-vf610/crm_regs.h    |  10 ++
> > >  arch/arm/include/asm/arch-vf610/imx-regs.h    |   4 +
> > >  arch/arm/include/asm/arch-vf610/regs-usbphy.h |  31 ++++
> > >  drivers/usb/host/Makefile                     |   1 +
> > >  drivers/usb/host/ehci-vf.c                    | 196
> > > 
> > > ++++++++++++++++++++++++++ 5 files changed, 242 insertions(+)
> > > 
> > >  create mode 100644 arch/arm/include/asm/arch-vf610/regs-usbphy.h
> > >  create mode 100644 drivers/usb/host/ehci-vf.c
> > 
> > A general hint, you can replace sequences of code like this:
> > 
> > var = readl(foo);
> > var |= BIT_BAR;
> > writel(var, addr);
> > 
> > with
> > 
> > setbits_le32(var, BIT_BAR);
> > 
> > Same applies for clearing -- clrbits_le32() and both setting and
> > clearing -- clrsetbits_le32().
> 
> Sorry about that. It is something which I use in the sixth patch
> as well in the board files but it skipped my mind while doing this
> driver. Will take care of it in v3 which seems imminent.
> 
> Noted, thanks :).

Thank you :)

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-12 23:28     ` Marek Vasut
  2015-04-13  1:36       ` Fabio Estevam
@ 2015-04-13  6:21       ` maitysanchayan at gmail.com
  2015-04-13  8:44         ` Marek Vasut
  1 sibling, 1 reply; 22+ messages in thread
From: maitysanchayan at gmail.com @ 2015-04-13  6:21 UTC (permalink / raw)
  To: u-boot

Hello,

On 15-04-13 01:28:07, Marek Vasut wrote:
> On Sunday, April 12, 2015 at 07:33:41 AM, maitysanchayan at gmail.com wrote:
> > Hi,
> > 
> > On 15-04-11 18:46:15, Marek Vasut wrote:
> > > On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > > > Hello,
> > > > 
> > > > This is the second version of the patchset which adds support for the
> > > > Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
> > > > using the serial loader over UART.
> > > 
> > > Hi!
> > > 
> > > Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way, we
> > > can solve 5/6 separately, since it might need some further dicussion. I
> > > don't want that patch to block the rest of the series though.
> > 
> > The sixth patch has some minor dependencies on the fifth patch like some
> > #defines and configuration we enable for Colibri. In case the fifth
> > patch will require some more discussion and time, then I guess I will
> > need to rework the sixth patch and then everything related to USB can
> > go in a later patch. The rework will be minor. So the v3 will be without
> > USB support
> 
> Well, if you want to rework the 6th patch, that'd be very nice of you :)

Yes sure. Will put the USB support in the end or not, the first patches 
can go in atleast since there seem to be no complaints on them so far.

> 
> > and USB will go in later once this gets applied. Perhaps we
> > will send the USB along with some more other featureset addition like
> > gpio support for Vybrid which my colleague did recently along with some
> > driver model/dt stuff.
> 
> My impression is that the USB is just a matter of figuring out where the
> PHY registers go -- whether in arch/arm/include/imx-common or into
> include/usb/ . I'd be more inclined for the later, since the PHY regs
> looks like chipidea IP specific thing, but I might be wrong.

I would say it looks like chipidea specific but I have not looked at IPs 
other than Freescale controllers to be sure.

> 
> > By the way, where the fifth patch is concerned, is it related to the
> > discussion Fabio pointed out in the discussion on first version of the
> > patch? uboot trying to get rid of the 'no register access via offset'
> > rule? Anything required I can rework accordingly.
> 
> I was concerned about the placement of the PHY reg definition. I didn't
> hear from Fabio on the result of this decision and I don't really mind
> that either way.

Ok. So I assume the driver can resort to the way it was in the first 
version while being changed with regards to three points 1. Use of 
clrsetbits_ related functions 2. Register phy definitions going in 
either of imx-common/ or include/usb/ with chipidea name. 3. No need to 
use offset accesses with the struct{} in light of the discussion Fabio 
pointed out.

> 
> Best regards,
> Marek Vasut

Thanks & Regards,
Sanchayan.

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-13  6:21       ` maitysanchayan at gmail.com
@ 2015-04-13  8:44         ` Marek Vasut
  2015-04-13  8:50           ` Peter Chen
  0 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2015-04-13  8:44 UTC (permalink / raw)
  To: u-boot

On Monday, April 13, 2015 at 08:21:27 AM, maitysanchayan at gmail.com wrote:
> Hello,
> 
> On 15-04-13 01:28:07, Marek Vasut wrote:
> > On Sunday, April 12, 2015 at 07:33:41 AM, maitysanchayan at gmail.com wrote:
> > > Hi,
> > > 
> > > On 15-04-11 18:46:15, Marek Vasut wrote:
> > > > On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > > > > Hello,
> > > > > 
> > > > > This is the second version of the patchset which adds support for
> > > > > the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been
> > > > > tested using the serial loader over UART.
> > > > 
> > > > Hi!
> > > > 
> > > > Stefano, maybe you can pick 1,2,3,4,6 right away for next? This way,
> > > > we can solve 5/6 separately, since it might need some further
> > > > dicussion. I don't want that patch to block the rest of the series
> > > > though.
> > > 
> > > The sixth patch has some minor dependencies on the fifth patch like
> > > some #defines and configuration we enable for Colibri. In case the
> > > fifth patch will require some more discussion and time, then I guess I
> > > will need to rework the sixth patch and then everything related to USB
> > > can go in a later patch. The rework will be minor. So the v3 will be
> > > without USB support
> > 
> > Well, if you want to rework the 6th patch, that'd be very nice of you :)
> 
> Yes sure. Will put the USB support in the end or not, the first patches
> can go in atleast since there seem to be no complaints on them so far.
> 
> > > and USB will go in later once this gets applied. Perhaps we
> > > will send the USB along with some more other featureset addition like
> > > gpio support for Vybrid which my colleague did recently along with some
> > > driver model/dt stuff.
> > 
> > My impression is that the USB is just a matter of figuring out where the
> > PHY registers go -- whether in arch/arm/include/imx-common or into
> > include/usb/ . I'd be more inclined for the later, since the PHY regs
> > looks like chipidea IP specific thing, but I might be wrong.
> 
> I would say it looks like chipidea specific but I have not looked at IPs
> other than Freescale controllers to be sure.

I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who might
chime in whether the PHY is CI-specific or IMX-specific.

> > > By the way, where the fifth patch is concerned, is it related to the
> > > discussion Fabio pointed out in the discussion on first version of the
> > > patch? uboot trying to get rid of the 'no register access via offset'
> > > rule? Anything required I can rework accordingly.
> > 
> > I was concerned about the placement of the PHY reg definition. I didn't
> > hear from Fabio on the result of this decision and I don't really mind
> > that either way.
> 
> Ok. So I assume the driver can resort to the way it was in the first
> version while being changed with regards to three points 1. Use of
> clrsetbits_ related functions 2. Register phy definitions going in
> either of imx-common/ or include/usb/ with chipidea name. 3. No need to
> use offset accesses with the struct{} in light of the discussion Fabio
> pointed out.

Yup, that'd be nice. Thanks!

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-13  8:44         ` Marek Vasut
@ 2015-04-13  8:50           ` Peter Chen
  2015-04-13  8:52             ` Marek Vasut
  0 siblings, 1 reply; 22+ messages in thread
From: Peter Chen @ 2015-04-13  8:50 UTC (permalink / raw)
  To: u-boot


 
> >
> > On 15-04-13 01:28:07, Marek Vasut wrote:
> > > On Sunday, April 12, 2015 at 07:33:41 AM, maitysanchayan at gmail.com
> wrote:
> > > > Hi,
> > > >
> > > > On 15-04-11 18:46:15, Marek Vasut wrote:
> > > > > On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > > > > > Hello,
> > > > > >
> > > > > > This is the second version of the patchset which adds support
> > > > > > for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up
> > > > > > has been tested using the serial loader over UART.
> > > > >
> > > > > Hi!
> > > > >
> > > > > Stefano, maybe you can pick 1,2,3,4,6 right away for next? This
> > > > > way, we can solve 5/6 separately, since it might need some
> > > > > further dicussion. I don't want that patch to block the rest of
> > > > > the series though.
> > > >
> > > > The sixth patch has some minor dependencies on the fifth patch
> > > > like some #defines and configuration we enable for Colibri. In
> > > > case the fifth patch will require some more discussion and time,
> > > > then I guess I will need to rework the sixth patch and then
> > > > everything related to USB can go in a later patch. The rework will
> > > > be minor. So the v3 will be without USB support
> > >
> > > Well, if you want to rework the 6th patch, that'd be very nice of
> > > you :)
> >
> > Yes sure. Will put the USB support in the end or not, the first
> > patches can go in atleast since there seem to be no complaints on them so far.
> >
> > > > and USB will go in later once this gets applied. Perhaps we will
> > > > send the USB along with some more other featureset addition like
> > > > gpio support for Vybrid which my colleague did recently along with
> > > > some driver model/dt stuff.
> > >
> > > My impression is that the USB is just a matter of figuring out where
> > > the PHY registers go -- whether in arch/arm/include/imx-common or
> > > into include/usb/ . I'd be more inclined for the later, since the
> > > PHY regs looks like chipidea IP specific thing, but I might be wrong.
> >
> > I would say it looks like chipidea specific but I have not looked at
> > IPs other than Freescale controllers to be sure.
> 
> I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who might chime in
> whether the PHY is CI-specific or IMX-specific.
> 

Which PHY? Vybrid? In Linux kernel, it belongs to mxs PHY.
The same controller can integrate different PHYs.

Peter

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-13  8:50           ` Peter Chen
@ 2015-04-13  8:52             ` Marek Vasut
  2015-04-14  9:06               ` Peter Chen
  0 siblings, 1 reply; 22+ messages in thread
From: Marek Vasut @ 2015-04-13  8:52 UTC (permalink / raw)
  To: u-boot

On Monday, April 13, 2015 at 10:50:27 AM, Peter Chen wrote:
> > > On 15-04-13 01:28:07, Marek Vasut wrote:
> > > > On Sunday, April 12, 2015 at 07:33:41 AM, maitysanchayan at gmail.com
> > 
> > wrote:
> > > > > Hi,
> > > > > 
> > > > > On 15-04-11 18:46:15, Marek Vasut wrote:
> > > > > > On Wednesday, April 08, 2015 at 03:20:04 PM, Sanchayan Maity wrote:
> > > > > > > Hello,
> > > > > > > 
> > > > > > > This is the second version of the patchset which adds support
> > > > > > > for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up
> > > > > > > has been tested using the serial loader over UART.
> > > > > > 
> > > > > > Hi!
> > > > > > 
> > > > > > Stefano, maybe you can pick 1,2,3,4,6 right away for next? This
> > > > > > way, we can solve 5/6 separately, since it might need some
> > > > > > further dicussion. I don't want that patch to block the rest of
> > > > > > the series though.
> > > > > 
> > > > > The sixth patch has some minor dependencies on the fifth patch
> > > > > like some #defines and configuration we enable for Colibri. In
> > > > > case the fifth patch will require some more discussion and time,
> > > > > then I guess I will need to rework the sixth patch and then
> > > > > everything related to USB can go in a later patch. The rework will
> > > > > be minor. So the v3 will be without USB support
> > > > 
> > > > Well, if you want to rework the 6th patch, that'd be very nice of
> > > > you :)
> > > 
> > > Yes sure. Will put the USB support in the end or not, the first
> > > patches can go in atleast since there seem to be no complaints on them
> > > so far.
> > > 
> > > > > and USB will go in later once this gets applied. Perhaps we will
> > > > > send the USB along with some more other featureset addition like
> > > > > gpio support for Vybrid which my colleague did recently along with
> > > > > some driver model/dt stuff.
> > > > 
> > > > My impression is that the USB is just a matter of figuring out where
> > > > the PHY registers go -- whether in arch/arm/include/imx-common or
> > > > into include/usb/ . I'd be more inclined for the later, since the
> > > > PHY regs looks like chipidea IP specific thing, but I might be wrong.
> > > 
> > > I would say it looks like chipidea specific but I have not looked at
> > > IPs other than Freescale controllers to be sure.
> > 
> > I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who might
> > chime in whether the PHY is CI-specific or IMX-specific.
> 
> Which PHY? Vybrid? In Linux kernel, it belongs to mxs PHY.
> The same controller can integrate different PHYs.

Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on other
SoCs not manufactured by Freescale ?

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-13  8:52             ` Marek Vasut
@ 2015-04-14  9:06               ` Peter Chen
  2015-04-14 10:18                 ` maitysanchayan at gmail.com
  0 siblings, 1 reply; 22+ messages in thread
From: Peter Chen @ 2015-04-14  9:06 UTC (permalink / raw)
  To: u-boot


 
> > > > > > >
> > > > > > > Hi!
> > > > > > >
> > > > > > > Stefano, maybe you can pick 1,2,3,4,6 right away for next?
> > > > > > > This way, we can solve 5/6 separately, since it might need
> > > > > > > some further dicussion. I don't want that patch to block the
> > > > > > > rest of the series though.
> > > > > >
> > > > > > The sixth patch has some minor dependencies on the fifth patch
> > > > > > like some #defines and configuration we enable for Colibri. In
> > > > > > case the fifth patch will require some more discussion and
> > > > > > time, then I guess I will need to rework the sixth patch and
> > > > > > then everything related to USB can go in a later patch. The
> > > > > > rework will be minor. So the v3 will be without USB support
> > > > >
> > > > > Well, if you want to rework the 6th patch, that'd be very nice
> > > > > of you :)
> > > >
> > > > Yes sure. Will put the USB support in the end or not, the first
> > > > patches can go in atleast since there seem to be no complaints on
> > > > them so far.
> > > >
> > > > > > and USB will go in later once this gets applied. Perhaps we
> > > > > > will send the USB along with some more other featureset
> > > > > > addition like gpio support for Vybrid which my colleague did
> > > > > > recently along with some driver model/dt stuff.
> > > > >
> > > > > My impression is that the USB is just a matter of figuring out
> > > > > where the PHY registers go -- whether in
> > > > > arch/arm/include/imx-common or into include/usb/ . I'd be more
> > > > > inclined for the later, since the PHY regs looks like chipidea IP specific
> thing, but I might be wrong.
> > > >
> > > > I would say it looks like chipidea specific but I have not looked
> > > > at IPs other than Freescale controllers to be sure.
> > >
> > > I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who
> > > might chime in whether the PHY is CI-specific or IMX-specific.
> >
> > Which PHY? Vybrid? In Linux kernel, it belongs to mxs PHY.
> > The same controller can integrate different PHYs.
> 
> Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on other
> SoCs not manufactured by Freescale ?
> 
 
This mxs PHY is from SigmaTel, I only see this PHY is used at FSL SoCs, but not sure
if others use it.

Peter  

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-14  9:06               ` Peter Chen
@ 2015-04-14 10:18                 ` maitysanchayan at gmail.com
  2015-04-15  5:41                   ` Marek Vasut
  0 siblings, 1 reply; 22+ messages in thread
From: maitysanchayan at gmail.com @ 2015-04-14 10:18 UTC (permalink / raw)
  To: u-boot

Hello,

On 15-04-14 09:06:27, Peter Chen wrote:
> 
>  
> > > > > > > >
> > > > > > > > Hi!
> > > > > > > >
> > > > > > > > Stefano, maybe you can pick 1,2,3,4,6 right away for next?
> > > > > > > > This way, we can solve 5/6 separately, since it might need
> > > > > > > > some further dicussion. I don't want that patch to block the
> > > > > > > > rest of the series though.
> > > > > > >
> > > > > > > The sixth patch has some minor dependencies on the fifth patch
> > > > > > > like some #defines and configuration we enable for Colibri. In
> > > > > > > case the fifth patch will require some more discussion and
> > > > > > > time, then I guess I will need to rework the sixth patch and
> > > > > > > then everything related to USB can go in a later patch. The
> > > > > > > rework will be minor. So the v3 will be without USB support
> > > > > >
> > > > > > Well, if you want to rework the 6th patch, that'd be very nice
> > > > > > of you :)
> > > > >
> > > > > Yes sure. Will put the USB support in the end or not, the first
> > > > > patches can go in atleast since there seem to be no complaints on
> > > > > them so far.
> > > > >
> > > > > > > and USB will go in later once this gets applied. Perhaps we
> > > > > > > will send the USB along with some more other featureset
> > > > > > > addition like gpio support for Vybrid which my colleague did
> > > > > > > recently along with some driver model/dt stuff.
> > > > > >
> > > > > > My impression is that the USB is just a matter of figuring out
> > > > > > where the PHY registers go -- whether in
> > > > > > arch/arm/include/imx-common or into include/usb/ . I'd be more
> > > > > > inclined for the later, since the PHY regs looks like chipidea IP specific
> > thing, but I might be wrong.
> > > > >
> > > > > I would say it looks like chipidea specific but I have not looked
> > > > > at IPs other than Freescale controllers to be sure.
> > > >
> > > > I think it's CI-specific indeed, thus include/usb/ . +CC Peter, who
> > > > might chime in whether the PHY is CI-specific or IMX-specific.
> > >
> > > Which PHY? Vybrid? In Linux kernel, it belongs to mxs PHY.
> > > The same controller can integrate different PHYs.
> > 
> > Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on other
> > SoCs not manufactured by Freescale ?
> > 
>  
> This mxs PHY is from SigmaTel, I only see this PHY is used at FSL SoCs, but not sure
> if others use it.

So Chipidea IP with the SigmaTel phy. It might be better to have the 
regs-usbphy.h viz. register phy definitions in imx-common then since it 
is not clear if SoC's other than Freescale's use the same phy.

Marek, what do you think?

- Sanchayan.

>
> Peter

^ permalink raw reply	[flat|nested] 22+ messages in thread
* [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules
  2015-04-14 10:18                 ` maitysanchayan at gmail.com
@ 2015-04-15  5:41                   ` Marek Vasut
  0 siblings, 0 replies; 22+ messages in thread
From: Marek Vasut @ 2015-04-15  5:41 UTC (permalink / raw)
  To: u-boot

On Tuesday, April 14, 2015 at 12:18:46 PM, maitysanchayan at gmail.com wrote:
> Hello,

Hi!

[...]

> > > Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on
> > > other SoCs not manufactured by Freescale ?
> > 
> > This mxs PHY is from SigmaTel, I only see this PHY is used at FSL SoCs,
> > but not sure if others use it.
> 
> So Chipidea IP with the SigmaTel phy. It might be better to have the
> regs-usbphy.h viz. register phy definitions in imx-common then since it
> is not clear if SoC's other than Freescale's use the same phy.
> 
> Marek, what do you think?

I agree, let's do it.

Thanks!

Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 22+ messages in thread
end of thread, other threads:[~2015-04-15  5:41 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-08 13:20 [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Sanchayan Maity
2015-04-08 13:20 ` [U-Boot] [PATCH v2 1/6] ARM: vf610: Move DDR3 initialization to imx-common Sanchayan Maity
2015-04-08 13:20 ` [U-Boot] [PATCH v2 2/6] ARM: vf610: Enable external 32KHz oscillator Sanchayan Maity
2015-04-08 13:20 ` [U-Boot] [PATCH v2 3/6] ARM: vf610: Add SoC and CPU type detection Sanchayan Maity
2015-04-08 13:20 ` [U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches Sanchayan Maity
2015-04-08 13:20 ` [U-Boot] [PATCH v2 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's Sanchayan Maity
2015-04-12 23:29   ` Marek Vasut
2015-04-13  5:37     ` maitysanchayan at gmail.com
2015-04-13  5:49       ` Marek Vasut
2015-04-08 13:20 ` [U-Boot] [PATCH v2 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61 Sanchayan Maity
2015-04-11 16:46 ` [U-Boot] [PATCH v2 0/6] Add support for Colibri Vybrid Modules Marek Vasut
2015-04-12  5:33   ` maitysanchayan at gmail.com
2015-04-12 23:28     ` Marek Vasut
2015-04-13  1:36       ` Fabio Estevam
2015-04-13  3:41         ` Marek Vasut
2015-04-13  6:21       ` maitysanchayan at gmail.com
2015-04-13  8:44         ` Marek Vasut
2015-04-13  8:50           ` Peter Chen
2015-04-13  8:52             ` Marek Vasut
2015-04-14  9:06               ` Peter Chen
2015-04-14 10:18                 ` maitysanchayan at gmail.com
2015-04-15  5:41                   ` Marek Vasut

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