* [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
@ 2015-04-15 13:24 Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
` (20 more replies)
0 siblings, 21 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
This patch series generate seven ACPI tables for machine virt on ARM.
The set of generated tables are:
- RSDP
- RSDT
- MADT
- GTDT
- FADT
- DSDT
- MCFG (For PCIe host bridge)
These tables are created dynamically using the function of aml-build.c,
taking into account the needed information passed from the virt machine model.
When the generation is finalized, it use fw_cfg to expose the tables to guest.
You can fetch this from following repo:
http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v5
And this patchset refers to Alexander Spyridakis's patches which are sent to
qemu-devel mailing list before.
http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
startup test and attach virtio-net-pci, e1000:
xp, windows2008, sles11 on X86
Fedora Linux kernel on ARM64
Note:
As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
Fedora Linux kernel from following address:
https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
changes since v4:
* use trace_* instead of DPRINTF (Igor & Alex)
* use standard QEMU style for structs (Michael)
* add "-no-acpi" option support for arm
* use extractNN for bits operation (Alex)
* use AmlReadAndWrite enum for rw flags (Igor)
* s/uint64_t/uint32_t/ (Igor)
* use enum for interrupt flag (Igor)
* simplify aml_device use in DSDT (Alex)
* share RSDT table generating code with x86 (Igor)
* remove unnecessary 1 in MCFG table generating code (Alex & Peter)
* use string for ToUUID macro (Igor)
* aml_or and aml_and use two args (Igor)
* add comments on UUID (Michael)
* change PCI MMIO region non-cacheable (Peter)
* fix wrong io map (Peter)
* add several reviewed-by's from Alex, thanks
changes since v3:
* rebase on upstream qemu
* fix _HID of CPU (Heyi Guo)
* Add PCIe host bridge
changes since v2:
* rebase on Igor Mammedov's new branch ASL_API_v3
* use rsdt instead of xsdt according to Igor Mammedov's suggestion
changes since v1:
* fix bug found by Laszlo
* move common helpers into dedictated file and change generating
table order according to Igor's comments
* fix copyright and function name according to Michael's comments
Shannon Zhao (20):
hw/i386: Move ACPI header definitions in an arch-independent location
hw/i386/acpi-build: move generic acpi building helpers into dedictated
file
hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
ARM
hw/acpi/aml-build: Add aml_memory32_fixed() term
hw/acpi/aml-build: Add aml_interrupt() term
hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
hw/arm/virt-acpi-build: Generate MADT table
hw/arm/virt-acpi-build: Generate GTDT table
hw/arm/virt-acpi-build: Generate RSDT table
hw/arm/virt-acpi-build: Generate RSDP table
hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
hw/acpi/aml-build: Add ToUUID macro
hw/acpi/aml-build: Add aml_or() term
hw/acpi/aml-build: Add aml_not() term
hw/acpi/aml-build: Add aml_else() term
hw/acpi/aml-build: Add aml_create_dword_field() term
hw/acpi/aml-build: Add aml_dword_io() term
hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
default-configs/arm-softmmu.mak | 1 +
default-configs/i386-softmmu.mak | 3 +
default-configs/mips-softmmu.mak | 3 +
default-configs/mips64-softmmu.mak | 3 +
default-configs/mips64el-softmmu.mak | 3 +
default-configs/mipsel-softmmu.mak | 3 +
default-configs/x86_64-softmmu.mak | 3 +
hw/acpi/Makefile.objs | 5 +-
hw/acpi/aml-build.c | 234 ++++++++++++-
hw/arm/Makefile.objs | 1 +
hw/arm/virt-acpi-build.c | 650 +++++++++++++++++++++++++++++++++++
hw/arm/virt.c | 78 ++++-
hw/i2c/Makefile.objs | 2 +-
hw/i386/acpi-build.c | 103 +-----
hw/i386/acpi-defs.h | 368 --------------------
include/hw/acpi/acpi-defs.h | 482 ++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 94 +++++
include/hw/arm/virt-acpi-build.h | 81 +++++
qemu-options.hx | 2 +-
tests/bios-tables-test.c | 2 +-
trace-events | 3 +
21 files changed, 1641 insertions(+), 483 deletions(-)
create mode 100644 hw/arm/virt-acpi-build.c
delete mode 100644 hw/i386/acpi-defs.h
create mode 100644 include/hw/acpi/acpi-defs.h
create mode 100644 include/hw/arm/virt-acpi-build.h
--
2.0.4
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 01/20] hw/i386: Move ACPI header definitions in an arch-independent location
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file Shannon Zhao
` (19 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
The ACPI related header file acpi-defs.h, includes definitions that
apply on other architectures as well. Move it in `include/hw/acpi/`
to sanely include it from other architectures.
Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/i386/acpi-build.c | 2 +-
hw/i386/acpi-defs.h | 368 --------------------------------------------
include/hw/acpi/acpi-defs.h | 368 ++++++++++++++++++++++++++++++++++++++++++++
tests/bios-tables-test.c | 2 +-
4 files changed, 370 insertions(+), 370 deletions(-)
delete mode 100644 hw/i386/acpi-defs.h
create mode 100644 include/hw/acpi/acpi-defs.h
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d0a5c85..83644e4 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -33,7 +33,7 @@
#include "hw/i386/pc.h"
#include "target-i386/cpu.h"
#include "hw/timer/hpet.h"
-#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
deleted file mode 100644
index c4468f8..0000000
--- a/hw/i386/acpi-defs.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef QEMU_ACPI_DEFS_H
-#define QEMU_ACPI_DEFS_H
-
-enum {
- ACPI_FADT_F_WBINVD,
- ACPI_FADT_F_WBINVD_FLUSH,
- ACPI_FADT_F_PROC_C1,
- ACPI_FADT_F_P_LVL2_UP,
- ACPI_FADT_F_PWR_BUTTON,
- ACPI_FADT_F_SLP_BUTTON,
- ACPI_FADT_F_FIX_RTC,
- ACPI_FADT_F_RTC_S4,
- ACPI_FADT_F_TMR_VAL_EXT,
- ACPI_FADT_F_DCK_CAP,
- ACPI_FADT_F_RESET_REG_SUP,
- ACPI_FADT_F_SEALED_CASE,
- ACPI_FADT_F_HEADLESS,
- ACPI_FADT_F_CPU_SW_SLP,
- ACPI_FADT_F_PCI_EXP_WAK,
- ACPI_FADT_F_USE_PLATFORM_CLOCK,
- ACPI_FADT_F_S4_RTC_STS_VALID,
- ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
- ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
- ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
- ACPI_FADT_F_HW_REDUCED_ACPI,
- ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
-};
-
-/*
- * ACPI 2.0 Generic Address Space definition.
- */
-struct Acpi20GenericAddress {
- uint8_t address_space_id;
- uint8_t register_bit_width;
- uint8_t register_bit_offset;
- uint8_t reserved;
- uint64_t address;
-} QEMU_PACKED;
-typedef struct Acpi20GenericAddress Acpi20GenericAddress;
-
-struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
- uint64_t signature; /* ACPI signature, contains "RSD PTR " */
- uint8_t checksum; /* To make sum of struct == 0 */
- uint8_t oem_id [6]; /* OEM identification */
- uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
- uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
- uint32_t length; /* XSDT Length in bytes including hdr */
- uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
- uint8_t extended_checksum; /* Checksum of entire table */
- uint8_t reserved [3]; /* Reserved field must be 0 */
-} QEMU_PACKED;
-typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
-
-/* Table structure from Linux kernel (the ACPI tables are under the
- BSD license) */
-
-
-#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
- uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
- uint32_t length; /* Length of table, in bytes, including header */ \
- uint8_t revision; /* ACPI Specification minor version # */ \
- uint8_t checksum; /* To make sum of entire table == 0 */ \
- uint8_t oem_id [6]; /* OEM identification */ \
- uint8_t oem_table_id [8]; /* OEM table identification */ \
- uint32_t oem_revision; /* OEM revision number */ \
- uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
- uint32_t asl_compiler_revision; /* ASL compiler revision number */
-
-
-struct AcpiTableHeader /* ACPI common table header */
-{
- ACPI_TABLE_HEADER_DEF
-} QEMU_PACKED;
-typedef struct AcpiTableHeader AcpiTableHeader;
-
-/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
- */
-struct AcpiFadtDescriptorRev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t firmware_ctrl; /* Physical address of FACS */
- uint32_t dsdt; /* Physical address of DSDT */
- uint8_t model; /* System Interrupt Model */
- uint8_t reserved1; /* Reserved */
- uint16_t sci_int; /* System vector of SCI interrupt */
- uint32_t smi_cmd; /* Port address of SMI command port */
- uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- uint8_t reserved2; /* Reserved - must be zero */
- uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
- uint8_t reserved3; /* Reserved */
- uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- uint16_t flush_size; /* Size of area read to flush caches */
- uint16_t flush_stride; /* Stride used in flushing caches */
- uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
- uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- uint8_t century; /* Index to century in RTC CMOS RAM */
- uint8_t reserved4; /* Reserved */
- uint8_t reserved4a; /* Reserved */
- uint8_t reserved4b; /* Reserved */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-struct AcpiRsdtDescriptorRev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t table_offset_entry[0]; /* Array of pointers to other */
- /* ACPI tables */
-} QEMU_PACKED;
-typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-struct AcpiFacsDescriptorRev1
-{
- uint32_t signature; /* ACPI Signature */
- uint32_t length; /* Length of structure, in bytes */
- uint32_t hardware_signature; /* Hardware configuration signature */
- uint32_t firmware_waking_vector; /* ACPI OS waking vector */
- uint32_t global_lock; /* Global Lock */
- uint32_t flags;
- uint8_t resverved3 [40]; /* Reserved - must be zero */
-} QEMU_PACKED;
-typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
-
-/*
- * Differentiated System Description Table (DSDT)
- */
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define ACPI_DUAL_PIC 0
-#define ACPI_MULTIPLE_APIC 1
-
-/* Master MADT */
-
-struct AcpiMultipleApicTable
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t local_apic_address; /* Physical address of local APIC */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
-
-/* Values for Type in APIC sub-headers */
-
-#define ACPI_APIC_PROCESSOR 0
-#define ACPI_APIC_IO 1
-#define ACPI_APIC_XRUPT_OVERRIDE 2
-#define ACPI_APIC_NMI 3
-#define ACPI_APIC_LOCAL_NMI 4
-#define ACPI_APIC_ADDRESS_OVERRIDE 5
-#define ACPI_APIC_IO_SAPIC 6
-#define ACPI_APIC_LOCAL_SAPIC 7
-#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
- uint8_t type; \
- uint8_t length;
-
-/* Sub-structures for MADT */
-
-struct AcpiMadtProcessorApic
-{
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint8_t local_apic_id; /* Processor's local APIC id */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
-
-struct AcpiMadtIoApic
-{
- ACPI_SUB_HEADER_DEF
- uint8_t io_apic_id; /* I/O APIC ID */
- uint8_t reserved; /* Reserved - must be zero */
- uint32_t address; /* APIC physical address */
- uint32_t interrupt; /* Global system interrupt where INTI
- * lines start */
-} QEMU_PACKED;
-typedef struct AcpiMadtIoApic AcpiMadtIoApic;
-
-struct AcpiMadtIntsrcovr {
- ACPI_SUB_HEADER_DEF
- uint8_t bus;
- uint8_t source;
- uint32_t gsi;
- uint16_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
-
-struct AcpiMadtLocalNmi {
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint16_t flags; /* MPS INTI flags */
- uint8_t lint; /* Local APIC LINT# */
-} QEMU_PACKED;
-typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
-
-/*
- * HPET Description Table
- */
-struct Acpi20Hpet {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t timer_block_id;
- Acpi20GenericAddress addr;
- uint8_t hpet_number;
- uint16_t min_tick;
- uint8_t page_protect;
-} QEMU_PACKED;
-typedef struct Acpi20Hpet Acpi20Hpet;
-
-/*
- * SRAT (NUMA topology description) table
- */
-
-struct AcpiSystemResourceAffinityTable
-{
- ACPI_TABLE_HEADER_DEF
- uint32_t reserved1;
- uint32_t reserved2[2];
-} QEMU_PACKED;
-typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
-
-#define ACPI_SRAT_PROCESSOR 0
-#define ACPI_SRAT_MEMORY 1
-
-struct AcpiSratProcessorAffinity
-{
- ACPI_SUB_HEADER_DEF
- uint8_t proximity_lo;
- uint8_t local_apic_id;
- uint32_t flags;
- uint8_t local_sapic_eid;
- uint8_t proximity_hi[3];
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
-
-struct AcpiSratMemoryAffinity
-{
- ACPI_SUB_HEADER_DEF
- uint8_t proximity[4];
- uint16_t reserved1;
- uint64_t base_addr;
- uint64_t range_length;
- uint32_t reserved2;
- uint32_t flags;
- uint32_t reserved3[2];
-} QEMU_PACKED;
-typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
-
-/* PCI fw r3.0 MCFG table. */
-/* Subtable */
-struct AcpiMcfgAllocation {
- uint64_t address; /* Base address, processor-relative */
- uint16_t pci_segment; /* PCI segment group number */
- uint8_t start_bus_number; /* Starting PCI Bus number */
- uint8_t end_bus_number; /* Final PCI Bus number */
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
-
-struct AcpiTableMcfg {
- ACPI_TABLE_HEADER_DEF;
- uint8_t reserved[8];
- AcpiMcfgAllocation allocation[0];
-} QEMU_PACKED;
-typedef struct AcpiTableMcfg AcpiTableMcfg;
-
-/*
- * TCPA Description Table
- */
-struct Acpi20Tcpa {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint16_t platform_class;
- uint32_t log_area_minimum_length;
- uint64_t log_area_start_address;
-} QEMU_PACKED;
-typedef struct Acpi20Tcpa Acpi20Tcpa;
-
-/* DMAR - DMA Remapping table r2.2 */
-struct AcpiTableDmar {
- ACPI_TABLE_HEADER_DEF
- uint8_t host_address_width; /* Maximum DMA physical addressability */
- uint8_t flags;
- uint8_t reserved[10];
-} QEMU_PACKED;
-typedef struct AcpiTableDmar AcpiTableDmar;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INTR_REMAP 1
-#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
-
-/* Values for sub-structure type for DMAR */
-enum {
- ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
- ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
- ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
- ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
- ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
- ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
-};
-
-/*
- * Sub-structures for DMAR
- */
-/* Type 0: Hardware Unit Definition */
-struct AcpiDmarHardwareUnit {
- uint16_t type;
- uint16_t length;
- uint8_t flags;
- uint8_t reserved;
- uint16_t pci_segment; /* The PCI Segment associated with this unit */
- uint64_t address; /* Base address of remapping hardware register-set */
-} QEMU_PACKED;
-typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INCLUDE_PCI_ALL 1
-
-#endif
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
new file mode 100644
index 0000000..c4468f8
--- /dev/null
+++ b/include/hw/acpi/acpi-defs.h
@@ -0,0 +1,368 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef QEMU_ACPI_DEFS_H
+#define QEMU_ACPI_DEFS_H
+
+enum {
+ ACPI_FADT_F_WBINVD,
+ ACPI_FADT_F_WBINVD_FLUSH,
+ ACPI_FADT_F_PROC_C1,
+ ACPI_FADT_F_P_LVL2_UP,
+ ACPI_FADT_F_PWR_BUTTON,
+ ACPI_FADT_F_SLP_BUTTON,
+ ACPI_FADT_F_FIX_RTC,
+ ACPI_FADT_F_RTC_S4,
+ ACPI_FADT_F_TMR_VAL_EXT,
+ ACPI_FADT_F_DCK_CAP,
+ ACPI_FADT_F_RESET_REG_SUP,
+ ACPI_FADT_F_SEALED_CASE,
+ ACPI_FADT_F_HEADLESS,
+ ACPI_FADT_F_CPU_SW_SLP,
+ ACPI_FADT_F_PCI_EXP_WAK,
+ ACPI_FADT_F_USE_PLATFORM_CLOCK,
+ ACPI_FADT_F_S4_RTC_STS_VALID,
+ ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
+ ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
+ ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
+ ACPI_FADT_F_HW_REDUCED_ACPI,
+ ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
+};
+
+/*
+ * ACPI 2.0 Generic Address Space definition.
+ */
+struct Acpi20GenericAddress {
+ uint8_t address_space_id;
+ uint8_t register_bit_width;
+ uint8_t register_bit_offset;
+ uint8_t reserved;
+ uint64_t address;
+} QEMU_PACKED;
+typedef struct Acpi20GenericAddress Acpi20GenericAddress;
+
+struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
+ uint64_t signature; /* ACPI signature, contains "RSD PTR " */
+ uint8_t checksum; /* To make sum of struct == 0 */
+ uint8_t oem_id [6]; /* OEM identification */
+ uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
+ uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
+ uint32_t length; /* XSDT Length in bytes including hdr */
+ uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
+ uint8_t extended_checksum; /* Checksum of entire table */
+ uint8_t reserved [3]; /* Reserved field must be 0 */
+} QEMU_PACKED;
+typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+ BSD license) */
+
+
+#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
+ uint32_t length; /* Length of table, in bytes, including header */ \
+ uint8_t revision; /* ACPI Specification minor version # */ \
+ uint8_t checksum; /* To make sum of entire table == 0 */ \
+ uint8_t oem_id [6]; /* OEM identification */ \
+ uint8_t oem_table_id [8]; /* OEM table identification */ \
+ uint32_t oem_revision; /* OEM revision number */ \
+ uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
+ uint32_t asl_compiler_revision; /* ASL compiler revision number */
+
+
+struct AcpiTableHeader /* ACPI common table header */
+{
+ ACPI_TABLE_HEADER_DEF
+} QEMU_PACKED;
+typedef struct AcpiTableHeader AcpiTableHeader;
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+struct AcpiFadtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t firmware_ctrl; /* Physical address of FACS */
+ uint32_t dsdt; /* Physical address of DSDT */
+ uint8_t model; /* System Interrupt Model */
+ uint8_t reserved1; /* Reserved */
+ uint16_t sci_int; /* System vector of SCI interrupt */
+ uint32_t smi_cmd; /* Port address of SMI command port */
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
+ uint8_t reserved2; /* Reserved - must be zero */
+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
+ uint8_t reserved3; /* Reserved */
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
+ uint16_t flush_size; /* Size of area read to flush caches */
+ uint16_t flush_stride; /* Stride used in flushing caches */
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+ uint8_t reserved4; /* Reserved */
+ uint8_t reserved4a; /* Reserved */
+ uint8_t reserved4b; /* Reserved */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+struct AcpiRsdtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t table_offset_entry[0]; /* Array of pointers to other */
+ /* ACPI tables */
+} QEMU_PACKED;
+typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+struct AcpiFacsDescriptorRev1
+{
+ uint32_t signature; /* ACPI Signature */
+ uint32_t length; /* Length of structure, in bytes */
+ uint32_t hardware_signature; /* Hardware configuration signature */
+ uint32_t firmware_waking_vector; /* ACPI OS waking vector */
+ uint32_t global_lock; /* Global Lock */
+ uint32_t flags;
+ uint8_t resverved3 [40]; /* Reserved - must be zero */
+} QEMU_PACKED;
+typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
+
+/*
+ * Differentiated System Description Table (DSDT)
+ */
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define ACPI_DUAL_PIC 0
+#define ACPI_MULTIPLE_APIC 1
+
+/* Master MADT */
+
+struct AcpiMultipleApicTable
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t local_apic_address; /* Physical address of local APIC */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
+
+/* Values for Type in APIC sub-headers */
+
+#define ACPI_APIC_PROCESSOR 0
+#define ACPI_APIC_IO 1
+#define ACPI_APIC_XRUPT_OVERRIDE 2
+#define ACPI_APIC_NMI 3
+#define ACPI_APIC_LOCAL_NMI 4
+#define ACPI_APIC_ADDRESS_OVERRIDE 5
+#define ACPI_APIC_IO_SAPIC 6
+#define ACPI_APIC_LOCAL_SAPIC 7
+#define ACPI_APIC_XRUPT_SOURCE 8
+#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
+ uint8_t type; \
+ uint8_t length;
+
+/* Sub-structures for MADT */
+
+struct AcpiMadtProcessorApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint8_t local_apic_id; /* Processor's local APIC id */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
+
+struct AcpiMadtIoApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t io_apic_id; /* I/O APIC ID */
+ uint8_t reserved; /* Reserved - must be zero */
+ uint32_t address; /* APIC physical address */
+ uint32_t interrupt; /* Global system interrupt where INTI
+ * lines start */
+} QEMU_PACKED;
+typedef struct AcpiMadtIoApic AcpiMadtIoApic;
+
+struct AcpiMadtIntsrcovr {
+ ACPI_SUB_HEADER_DEF
+ uint8_t bus;
+ uint8_t source;
+ uint32_t gsi;
+ uint16_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
+
+struct AcpiMadtLocalNmi {
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint16_t flags; /* MPS INTI flags */
+ uint8_t lint; /* Local APIC LINT# */
+} QEMU_PACKED;
+typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+
+/*
+ * HPET Description Table
+ */
+struct Acpi20Hpet {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t timer_block_id;
+ Acpi20GenericAddress addr;
+ uint8_t hpet_number;
+ uint16_t min_tick;
+ uint8_t page_protect;
+} QEMU_PACKED;
+typedef struct Acpi20Hpet Acpi20Hpet;
+
+/*
+ * SRAT (NUMA topology description) table
+ */
+
+struct AcpiSystemResourceAffinityTable
+{
+ ACPI_TABLE_HEADER_DEF
+ uint32_t reserved1;
+ uint32_t reserved2[2];
+} QEMU_PACKED;
+typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+
+#define ACPI_SRAT_PROCESSOR 0
+#define ACPI_SRAT_MEMORY 1
+
+struct AcpiSratProcessorAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity_lo;
+ uint8_t local_apic_id;
+ uint32_t flags;
+ uint8_t local_sapic_eid;
+ uint8_t proximity_hi[3];
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
+
+struct AcpiSratMemoryAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity[4];
+ uint16_t reserved1;
+ uint64_t base_addr;
+ uint64_t range_length;
+ uint32_t reserved2;
+ uint32_t flags;
+ uint32_t reserved3[2];
+} QEMU_PACKED;
+typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
+
+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct AcpiMcfgAllocation {
+ uint64_t address; /* Base address, processor-relative */
+ uint16_t pci_segment; /* PCI segment group number */
+ uint8_t start_bus_number; /* Starting PCI Bus number */
+ uint8_t end_bus_number; /* Final PCI Bus number */
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
+
+struct AcpiTableMcfg {
+ ACPI_TABLE_HEADER_DEF;
+ uint8_t reserved[8];
+ AcpiMcfgAllocation allocation[0];
+} QEMU_PACKED;
+typedef struct AcpiTableMcfg AcpiTableMcfg;
+
+/*
+ * TCPA Description Table
+ */
+struct Acpi20Tcpa {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint16_t platform_class;
+ uint32_t log_area_minimum_length;
+ uint64_t log_area_start_address;
+} QEMU_PACKED;
+typedef struct Acpi20Tcpa Acpi20Tcpa;
+
+/* DMAR - DMA Remapping table r2.2 */
+struct AcpiTableDmar {
+ ACPI_TABLE_HEADER_DEF
+ uint8_t host_address_width; /* Maximum DMA physical addressability */
+ uint8_t flags;
+ uint8_t reserved[10];
+} QEMU_PACKED;
+typedef struct AcpiTableDmar AcpiTableDmar;
+
+/* Masks for Flags field above */
+#define ACPI_DMAR_INTR_REMAP 1
+#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
+
+/* Values for sub-structure type for DMAR */
+enum {
+ ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
+ ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
+ ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
+ ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
+ ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
+ ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
+};
+
+/*
+ * Sub-structures for DMAR
+ */
+/* Type 0: Hardware Unit Definition */
+struct AcpiDmarHardwareUnit {
+ uint16_t type;
+ uint16_t length;
+ uint8_t flags;
+ uint8_t reserved;
+ uint16_t pci_segment; /* The PCI Segment associated with this unit */
+ uint64_t address; /* Base address of remapping hardware register-set */
+} QEMU_PACKED;
+typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
+
+/* Masks for Flags field above */
+#define ACPI_DMAR_INCLUDE_PCI_ALL 1
+
+#endif
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 735ac61..7e85dc4 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -17,7 +17,7 @@
#include "qemu-common.h"
#include "libqtest.h"
#include "qemu/compiler.h"
-#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi-defs.h"
#include "hw/i386/smbios.h"
#include "qemu/bitmap.h"
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
` (18 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Move generic acpi building helpers into dedictated file and this
can be shared with other machines.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 58 ++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 77 ---------------------------------------------
include/hw/acpi/aml-build.h | 29 +++++++++++++++++
3 files changed, 87 insertions(+), 77 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index d7945f6..8d01959 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -26,6 +26,7 @@
#include <string.h>
#include "hw/acpi/aml-build.h"
#include "qemu/bswap.h"
+#include "hw/acpi/bios-linker-loader.h"
static GArray *build_alloc_array(void)
{
@@ -891,3 +892,60 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}
+
+void
+build_header(GArray *linker, GArray *table_data,
+ AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
+{
+ memcpy(&h->signature, sig, 4);
+ h->length = cpu_to_le32(len);
+ h->revision = rev;
+ memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
+ memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
+ memcpy(h->oem_table_id + 4, sig, 4);
+ h->oem_revision = cpu_to_le32(1);
+ memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
+ h->asl_compiler_revision = cpu_to_le32(1);
+ h->checksum = 0;
+ /* Checksum to be filled in by Guest linker */
+ bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
+ table_data->data, h, len, &h->checksum);
+}
+
+void *acpi_data_push(GArray *table_data, unsigned size)
+{
+ unsigned off = table_data->len;
+ g_array_set_size(table_data, off + size);
+ return table_data->data + off;
+}
+
+unsigned acpi_data_len(GArray *table)
+{
+#if GLIB_CHECK_VERSION(2, 22, 0)
+ assert(g_array_get_element_size(table) == 1);
+#endif
+ return table->len;
+}
+
+void acpi_add_table(GArray *table_offsets, GArray *table_data)
+{
+ uint32_t offset = cpu_to_le32(table_data->len);
+ g_array_append_val(table_offsets, offset);
+}
+
+void acpi_build_tables_init(AcpiBuildTables *tables)
+{
+ tables->rsdp = g_array_new(false, true /* clear */, 1);
+ tables->table_data = g_array_new(false, true /* clear */, 1);
+ tables->tcpalog = g_array_new(false, true /* clear */, 1);
+ tables->linker = bios_linker_loader_init();
+}
+
+void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
+{
+ void *linker_data = bios_linker_loader_cleanup(tables->linker);
+ g_free(linker_data);
+ g_array_free(tables->rsdp, true);
+ g_array_free(tables->table_data, true);
+ g_array_free(tables->tcpalog, mfre);
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 83644e4..7b5210e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -70,9 +70,6 @@
#define ACPI_BUILD_TABLE_SIZE 0x20000
-/* Reserve RAM space for tables: add another order of magnitude. */
-#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
-
/* #define DEBUG_ACPI_BUILD */
#ifdef DEBUG_ACPI_BUILD
#define ACPI_BUILD_DPRINTF(fmt, ...) \
@@ -267,51 +264,8 @@ static void acpi_get_pci_info(PcPciInfo *info)
NULL);
}
-#define ACPI_BUILD_APPNAME "Bochs"
-#define ACPI_BUILD_APPNAME6 "BOCHS "
-#define ACPI_BUILD_APPNAME4 "BXPC"
-
-#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
-#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
-#define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
-
-static void
-build_header(GArray *linker, GArray *table_data,
- AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
-{
- memcpy(&h->signature, sig, 4);
- h->length = cpu_to_le32(len);
- h->revision = rev;
- memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
- memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
- memcpy(h->oem_table_id + 4, sig, 4);
- h->oem_revision = cpu_to_le32(1);
- memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
- h->asl_compiler_revision = cpu_to_le32(1);
- h->checksum = 0;
- /* Checksum to be filled in by Guest linker */
- bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
- table_data->data, h, len, &h->checksum);
-}
-
-/* End here */
#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
-static inline void *acpi_data_push(GArray *table_data, unsigned size)
-{
- unsigned off = table_data->len;
- g_array_set_size(table_data, off + size);
- return table_data->data + off;
-}
-
-static unsigned acpi_data_len(GArray *table)
-{
-#if GLIB_CHECK_VERSION(2, 22, 0)
- assert(g_array_get_element_size(table) == 1);
-#endif
- return table->len;
-}
-
static void acpi_align_size(GArray *blob, unsigned align)
{
/* Align size to multiple of given size. This reduces the chance
@@ -320,12 +274,6 @@ static void acpi_align_size(GArray *blob, unsigned align)
g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
}
-static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
-{
- uint32_t offset = cpu_to_le32(table_data->len);
- g_array_append_val(table_offsets, offset);
-}
-
/* FACS */
static void
build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
@@ -1296,31 +1244,6 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
}
typedef
-struct AcpiBuildTables {
- GArray *table_data;
- GArray *rsdp;
- GArray *tcpalog;
- GArray *linker;
-} AcpiBuildTables;
-
-static inline void acpi_build_tables_init(AcpiBuildTables *tables)
-{
- tables->rsdp = g_array_new(false, true /* clear */, 1);
- tables->table_data = g_array_new(false, true /* clear */, 1);
- tables->tcpalog = g_array_new(false, true /* clear */, 1);
- tables->linker = bios_linker_loader_init();
-}
-
-static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
-{
- void *linker_data = bios_linker_loader_cleanup(tables->linker);
- g_free(linker_data);
- g_array_free(tables->rsdp, true);
- g_array_free(tables->table_data, true);
- g_array_free(tables->tcpalog, mfre);
-}
-
-typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
ram_addr_t table_ram;
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 17d3beb..1705001 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -4,6 +4,18 @@
#include <stdint.h>
#include <glib.h>
#include "qemu/compiler.h"
+#include "hw/acpi/acpi-defs.h"
+
+/* Reserve RAM space for tables: add another order of magnitude. */
+#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
+
+#define ACPI_BUILD_APPNAME "Bochs"
+#define ACPI_BUILD_APPNAME6 "BOCHS "
+#define ACPI_BUILD_APPNAME4 "BXPC"
+
+#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
+#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
+#define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
typedef enum {
AML_NO_OPCODE = 0,/* has only data */
@@ -93,6 +105,14 @@ typedef enum {
aml_ReadWrite = 1,
} AmlReadAndWrite;
+typedef
+struct AcpiBuildTables {
+ GArray *table_data;
+ GArray *rsdp;
+ GArray *tcpalog;
+ GArray *linker;
+} AcpiBuildTables;
+
/**
* init_aml_allocator:
*
@@ -188,4 +208,13 @@ Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
+void
+build_header(GArray *linker, GArray *table_data,
+ AcpiTableHeader *h, const char *sig, int len, uint8_t rev);
+void *acpi_data_push(GArray *table_data, unsigned size);
+unsigned acpi_data_len(GArray *table);
+void acpi_add_table(GArray *table_offsets, GArray *table_data);
+void acpi_build_tables_init(AcpiBuildTables *tables);
+void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre);
+
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
` (17 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
- FADT: Generic information about the machine
- GTDT: Generic timer description table
- MADT: Multiple APIC description table
- DSDT: Holds all information about system devices/peripherals, pointed by FADT
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/Makefile.objs | 1 +
hw/arm/virt-acpi-build.c | 191 +++++++++++++++++++++++++++++++++++++++
include/hw/arm/virt-acpi-build.h | 70 ++++++++++++++
qemu-options.hx | 2 +-
trace-events | 3 +
5 files changed, 266 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/virt-acpi-build.c
create mode 100644 include/hw/arm/virt-acpi-build.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2577f68..a1bfb19 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
new file mode 100644
index 0000000..c5a3cf9
--- /dev/null
+++ b/hw/arm/virt-acpi-build.c
@@ -0,0 +1,191 @@
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * ARM virt ACPI generation
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/arm/virt-acpi-build.h"
+#include <stddef.h>
+#include <glib.h>
+#include "qemu-common.h"
+#include "qemu/bitmap.h"
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "qemu/error-report.h"
+#include "trace.h"
+#include "qom/cpu.h"
+#include "target-arm/cpu.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "hw/loader.h"
+#include "hw/hw.h"
+
+#include "hw/acpi/aml-build.h"
+
+#include "qapi/qmp/qint.h"
+#include "qom/qom-qobject.h"
+#include "exec/ram_addr.h"
+
+typedef
+struct AcpiBuildState {
+ /* Copy of table in RAM (for patching). */
+ ram_addr_t table_ram;
+ ram_addr_t rsdp_ram;
+ ram_addr_t linker_ram;
+ /* Is table patched? */
+ uint8_t patched;
+ VirtGuestInfo *guest_info;
+} AcpiBuildState;
+
+static
+void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
+{
+ GArray *table_offsets;
+
+ table_offsets = g_array_new(false, true /* clear */,
+ sizeof(uint32_t));
+
+ bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
+ 64, false /* high memory */);
+
+ /*
+ * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
+ * RSDP
+ * RSDT
+ * FADT
+ * GTDT
+ * MADT
+ * DSDT
+ */
+
+ /* Cleanup memory that's no longer used. */
+ g_array_free(table_offsets, true);
+}
+
+static void acpi_ram_update(ram_addr_t ram, GArray *data)
+{
+ uint32_t size = acpi_data_len(data);
+
+ /* Make sure RAM size is correct - in case it got changed
+ * e.g. by migration */
+ qemu_ram_resize(ram, size, &error_abort);
+
+ memcpy(qemu_get_ram_ptr(ram), data->data, size);
+ cpu_physical_memory_set_dirty_range_nocode(ram, size);
+}
+
+static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
+{
+ AcpiBuildState *build_state = build_opaque;
+ AcpiBuildTables tables;
+
+ /* No state to update or already patched? Nothing to do. */
+ if (!build_state || build_state->patched) {
+ return;
+ }
+ build_state->patched = 1;
+
+ acpi_build_tables_init(&tables);
+
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ acpi_ram_update(build_state->table_ram, tables.table_data);
+ acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
+ acpi_ram_update(build_state->linker_ram, tables.linker);
+
+
+ acpi_build_tables_cleanup(&tables, true);
+}
+
+static void virt_acpi_build_reset(void *build_opaque)
+{
+ AcpiBuildState *build_state = build_opaque;
+ build_state->patched = 0;
+}
+
+static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
+ const char *name, uint64_t max_size)
+{
+ return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
+ name, virt_acpi_build_update, build_state);
+}
+
+static const VMStateDescription vmstate_virt_acpi_build = {
+ .name = "virt_acpi_build",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(patched, AcpiBuildState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+void virt_acpi_setup(VirtGuestInfo *guest_info)
+{
+ AcpiBuildTables tables;
+ AcpiBuildState *build_state;
+
+ if (!guest_info->fw_cfg) {
+ trace_virt_acpi_setup();
+ return;
+ }
+
+ if (!acpi_enabled) {
+ trace_virt_acpi_setup();
+ return;
+ }
+
+ build_state = g_malloc0(sizeof *build_state);
+ build_state->guest_info = guest_info;
+
+ acpi_build_tables_init(&tables);
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ /* Now expose it all to Guest */
+ build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_MAX_SIZE);
+ assert(build_state->table_ram != RAM_ADDR_MAX);
+
+ build_state->linker_ram =
+ acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
+
+ fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
+ tables.tcpalog->data, acpi_data_len(tables.tcpalog));
+
+ build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
+ ACPI_BUILD_RSDP_FILE, 0);
+
+ qemu_register_reset(virt_acpi_build_reset, build_state);
+ virt_acpi_build_reset(build_state);
+ vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
+
+ /* Cleanup tables but don't free the memory: we track it
+ * in build_state.
+ */
+ acpi_build_tables_cleanup(&tables, false);
+}
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
new file mode 100644
index 0000000..ece67a2
--- /dev/null
+++ b/include/hw/arm/virt-acpi-build.h
@@ -0,0 +1,70 @@
+/*
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_VIRT_ACPI_BUILD_H
+#define QEMU_VIRT_ACPI_BUILD_H
+
+#include "qemu-common.h"
+
+typedef struct MemMap {
+ hwaddr addr;
+ hwaddr size;
+} MemMap;
+
+typedef struct AcpiGtdtInfo {
+ uint32_t timer_virt;
+ uint32_t timer_s_el1;
+ uint32_t timer_ns_el1;
+ uint32_t timer_ns_el2;
+} AcpiGtdtInfo;
+
+typedef struct AcpiMadtInfo {
+ const MemMap *gic_cpu_memmap;
+ const MemMap *gic_dist_memmap;
+} AcpiMadtInfo;
+
+typedef struct AcpiDsdtInfo {
+ const MemMap *uart_memmap;
+ const int *uart_irq;
+ const MemMap *virtio_mmio_memmap;
+ const int *virtio_mmio_irq;
+ int virtio_mmio_num;
+ const MemMap *rtc_memmap;
+ const int *rtc_irq;
+ const MemMap *flash_memmap;
+} AcpiDsdtInfo;
+
+typedef struct VirtGuestInfo {
+ int smp_cpus;
+ int max_cpus;
+ FWCfgState *fw_cfg;
+ AcpiMadtInfo *madt_info;
+ AcpiDsdtInfo *dsdt_info;
+ AcpiGtdtInfo *gtdt_info;
+} VirtGuestInfo;
+
+
+typedef struct VirtGuestInfoState {
+ VirtGuestInfo info;
+ Notifier machine_done;
+} VirtGuestInfoState;
+
+void virt_acpi_setup(VirtGuestInfo *guest_info);
+
+#endif
diff --git a/qemu-options.hx b/qemu-options.hx
index 319d971..82bcc9b 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1352,7 +1352,7 @@ be needed to boot from old floppy disks.
ETEXI
DEF("no-acpi", 0, QEMU_OPTION_no_acpi,
- "-no-acpi disable ACPI\n", QEMU_ARCH_I386)
+ "-no-acpi disable ACPI\n", QEMU_ARCH_I386 | QEMU_ARCH_ARM)
STEXI
@item -no-acpi
@findex -no-acpi
diff --git a/trace-events b/trace-events
index 30eba92..0c7d2ff 100644
--- a/trace-events
+++ b/trace-events
@@ -1590,3 +1590,6 @@ i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA ch
cpu_set_state(int cpu_index, uint8_t state) "setting cpu %d state to %" PRIu8
cpu_halt(int cpu_index) "halting cpu %d"
cpu_unhalt(int cpu_index) "unhalting cpu %d"
+
+# hw/arm/virt-acpi-build.c
+virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (2 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
` (16 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_memory32_fixed() for describing device mmio region in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 27 +++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 2 ++
2 files changed, 29 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 8d01959..61407b7 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -26,6 +26,7 @@
#include <string.h>
#include "hw/acpi/aml-build.h"
#include "qemu/bswap.h"
+#include "qemu/bitops.h"
#include "hw/acpi/bios-linker-loader.h"
static GArray *build_alloc_array(void)
@@ -505,6 +506,32 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
return var;
}
+/*
+ * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
+ */
+Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
+ AmlReadAndWrite read_and_write)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
+ build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
+ build_append_byte(var->buf, read_and_write); /* Write status, 1 rw 0 ro */
+
+ /* Range base address */
+ build_append_byte(var->buf, extract32(addr, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(addr, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(addr, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(addr, 24, 8)); /* bits[31:24] */
+
+ /* Range length */
+ build_append_byte(var->buf, extract32(size, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(size, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(size, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(size, 24, 8)); /* bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 1705001..154823b 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -162,6 +162,8 @@ Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
+Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
+ AmlReadAndWrite read_and_write);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (3 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
` (15 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 28 +++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 50 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 61407b7..babe4d6 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -532,6 +532,34 @@ Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
return var;
}
+/*
+ * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
+ */
+Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
+ AmlLevelAndEdge level_and_edge,
+ AmlActiveHighAndLow high_and_low,
+ AmlExclusiveAndShared exclusive_and_shared,
+ AmlWakeCap wake_capable, uint32_t irq)
+{
+ Aml *var = aml_alloc();
+ uint8_t irq_flags = con_and_pro | (level_and_edge << 1)
+ | (high_and_low << 2) | (exclusive_and_shared << 3)
+ | (wake_capable << 4);
+
+ build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
+ build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
+ build_append_byte(var->buf, irq_flags); /* Interrupt Vector Information. */
+ build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
+
+ /* Interrupt Number */
+ build_append_byte(var->buf, extract32(irq, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(irq, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(irq, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(irq, 24, 8)); /* bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 154823b..5b60744 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -105,6 +105,51 @@ typedef enum {
aml_ReadWrite = 1,
} AmlReadAndWrite;
+/*
+ * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition
+ * Interrupt Vector Flags Bits[0] Consumer/Producer
+ */
+typedef enum {
+ aml_consumer_producer = 0,
+ aml_consumer = 1,
+} AmlConsumerAndProducer;
+
+/*
+ * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition
+ * _HE field definition
+ */
+typedef enum {
+ aml_level = 0,
+ aml_edge = 1,
+} AmlLevelAndEdge;
+
+/*
+ * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition
+ * _LL field definition
+ */
+typedef enum {
+ aml_active_high = 0,
+ aml_active_low = 1,
+} AmlActiveHighAndLow;
+
+/*
+ * ACPI 1.0b: Table 6-28 Extended Interrupt Descriptor Definition
+ * _SHR field definition
+ */
+typedef enum {
+ aml_exclusive = 0,
+ aml_shared = 1,
+} AmlExclusiveAndShared;
+
+/*
+ * ACPI 5.1: Table 6-203 Extended Interrupt Descriptor Definition
+ * _WKC field definition
+ */
+typedef enum {
+ aml_not_wake_capable = 0,
+ aml_wake_capable = 1,
+} AmlWakeCap;
+
typedef
struct AcpiBuildTables {
GArray *table_data;
@@ -164,6 +209,11 @@ Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
AmlReadAndWrite read_and_write);
+Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
+ AmlLevelAndEdge level_and_edge,
+ AmlActiveHighAndLow high_and_low,
+ AmlExclusiveAndShared exclusive_and_shared,
+ AmlWakeCap wake_capable, uint32_t irq);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (4 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-05-04 9:58 ` Igor Mammedov
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
` (14 subsequent siblings)
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described using the Resource Template for the 32-Bit Fixed Memory
Range and the Extended Interrupt Descriptors.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index c5a3cf9..d044880 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -50,6 +50,130 @@
#include "qom/qom-qobject.h"
#include "exec/ram_addr.h"
+static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
+{
+ uint16_t i;
+
+ for (i = 0; i < max_cpus; i++) {
+ Aml *dev = aml_device("C%03x", i);
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+ Aml *crs = aml_resource_template();
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ }
+}
+
+static void acpi_dsdt_add_uart(Aml *scope, const MemMap *uart_memmap,
+ const int *uart_irq)
+{
+ Aml *dev = aml_device("COM0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(uart_memmap->addr,
+ uart_memmap->size, aml_ReadWrite));
+ aml_append(crs,
+ aml_interrupt(aml_consumer, aml_level, aml_active_high,
+ aml_exclusive, aml_not_wake_capable, *uart_irq + 32));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_rtc(Aml *scope, const MemMap *rtc_memmap,
+ const int *rtc_irq)
+{
+ Aml *dev = aml_device("RTC0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(rtc_memmap->addr,
+ rtc_memmap->size, aml_ReadWrite));
+ aml_append(crs,
+ aml_interrupt(aml_consumer, aml_level, aml_active_high,
+ aml_exclusive, aml_not_wake_capable, *rtc_irq + 32));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_flash(Aml *scope, const MemMap *flash_memmap)
+{
+ Aml *dev, *crs;
+ hwaddr base = flash_memmap->addr;
+ hwaddr size = flash_memmap->size;
+
+ dev = aml_device("FLS0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+
+ dev = aml_device("FLS1");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base + size, size, aml_ReadWrite));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
+ const int *mmio_irq, int num)
+{
+ hwaddr base = virtio_mmio_memmap->addr;
+ hwaddr size = virtio_mmio_memmap->size;
+ int irq = *mmio_irq + 32;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ Aml *dev = aml_device("VR%02u", i);
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
+ aml_append(crs,
+ aml_interrupt(aml_consumer, aml_level, aml_active_high,
+ aml_exclusive, aml_not_wake_capable, irq + i));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ base += size;
+ }
+}
+
+/* DSDT */
+static void
+build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ Aml *scope, *dsdt;
+ AcpiDsdtInfo *info = guest_info->dsdt_info;
+
+ dsdt = init_aml_allocator();
+ /* Reserve space for header */
+ acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
+
+ scope = aml_scope("\\_SB");
+ acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
+ acpi_dsdt_add_uart(scope, info->uart_memmap, info->uart_irq);
+ acpi_dsdt_add_rtc(scope, info->rtc_memmap, info->rtc_irq);
+ acpi_dsdt_add_flash(scope, info->flash_memmap);
+ acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
+ info->virtio_mmio_irq, info->virtio_mmio_num);
+ aml_append(dsdt, scope);
+
+ /* copy AML table into ACPI tables blob and patch header there */
+ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
+ build_header(linker, table_data,
+ (void *)(table_data->data + table_data->len - dsdt->buf->len),
+ "DSDT", dsdt->buf->len, 1);
+ free_aml_allocator();
+}
+
typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
@@ -65,6 +189,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -82,6 +207,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
* DSDT
*/
+ /* DSDT is pointed to by FADT */
+ build_dsdt(tables_blob, tables->linker, guest_info);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (5 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
` (13 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 31 ++++++++++++
include/hw/acpi/acpi-defs.h | 115 ++++++++++++++++++++++++++++++--------------
2 files changed, 109 insertions(+), 37 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index d044880..c72a9c8 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -146,6 +146,31 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
}
}
+/* FADT */
+static void
+build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
+{
+ AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
+
+ /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
+ fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
+ fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
+ (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
+
+ /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
+ fadt->minor_revision = 0x1;
+
+ fadt->dsdt = cpu_to_le32(dsdt);
+ /* DSDT address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &fadt->dsdt,
+ sizeof fadt->dsdt);
+
+ build_header(linker, table_data,
+ (void *)fadt, "FACP", sizeof(*fadt), 5);
+}
+
/* DSDT */
static void
build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -189,6 +214,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ unsigned dsdt;
GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
@@ -208,8 +234,13 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
*/
/* DSDT is pointed to by FADT */
+ dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, guest_info);
+ /* FADT MADT GTDT pointed to by RSDT */
+ acpi_add_table(table_offsets, tables_blob);
+ build_fadt(tables_blob, tables->linker, dsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index c4468f8..bac981d 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -88,46 +88,49 @@ struct AcpiTableHeader /* ACPI common table header */
typedef struct AcpiTableHeader AcpiTableHeader;
/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ * ACPI Fixed ACPI Description Table (FADT)
*/
+#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t firmware_ctrl; /* Physical address of FACS */ \
+ uint32_t dsdt; /* Physical address of DSDT */ \
+ uint8_t model; /* System Interrupt Model */ \
+ uint8_t reserved1; /* Reserved */ \
+ uint16_t sci_int; /* System vector of SCI interrupt */ \
+ uint32_t smi_cmd; /* Port address of SMI command port */ \
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ \
+ uint8_t reserved2; /* Reserved - must be zero */ \
+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
+ uint8_t reserved3; /* Reserved */ \
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
+ uint16_t flush_size; /* Size of area read to flush caches */ \
+ uint16_t flush_stride; /* Stride used in flushing caches */ \
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+
struct AcpiFadtDescriptorRev1
{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t firmware_ctrl; /* Physical address of FACS */
- uint32_t dsdt; /* Physical address of DSDT */
- uint8_t model; /* System Interrupt Model */
- uint8_t reserved1; /* Reserved */
- uint16_t sci_int; /* System vector of SCI interrupt */
- uint32_t smi_cmd; /* Port address of SMI command port */
- uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- uint8_t reserved2; /* Reserved - must be zero */
- uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
- uint8_t reserved3; /* Reserved */
- uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- uint16_t flush_size; /* Size of area read to flush caches */
- uint16_t flush_stride; /* Stride used in flushing caches */
- uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
- uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- uint8_t century; /* Index to century in RTC CMOS RAM */
+ ACPI_FADT_COMMON_DEF
uint8_t reserved4; /* Reserved */
uint8_t reserved4a; /* Reserved */
uint8_t reserved4b; /* Reserved */
@@ -135,6 +138,44 @@ struct AcpiFadtDescriptorRev1
} QEMU_PACKED;
typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+struct AcpiGenericAddress {
+ uint8_t space_id; /* Address space where struct or register exists */
+ uint8_t bit_width; /* Size in bits of given register */
+ uint8_t bit_offset; /* Bit offset within the register */
+ uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
+ uint64_t address; /* 64-bit address of struct or register */
+} QEMU_PACKED;
+
+struct AcpiFadtDescriptorRev5_1 {
+ ACPI_FADT_COMMON_DEF
+ uint16_t boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
+ uint8_t reserved; /* Reserved, must be zero */
+ uint32_t flags; /* Miscellaneous flag bits (see below for individual flags) */
+ struct AcpiGenericAddress reset_register; /* 64-bit address of the Reset register */
+ uint8_t reset_value; /* Value to write to the reset_register port to reset the system */
+ uint16_t arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
+ uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
+ uint64_t Xfacs; /* 64-bit physical address of FACS */
+ uint64_t Xdsdt; /* 64-bit physical address of DSDT */
+ struct AcpiGenericAddress xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
+ struct AcpiGenericAddress xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
+ struct AcpiGenericAddress xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
+ struct AcpiGenericAddress xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
+ struct AcpiGenericAddress xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
+ struct AcpiGenericAddress xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
+ struct AcpiGenericAddress xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
+ struct AcpiGenericAddress xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
+ struct AcpiGenericAddress sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
+ struct AcpiGenericAddress sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
+} QEMU_PACKED;
+
+typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
+
+enum {
+ ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0,
+ ACPI_FADT_ARM_PSCI_USE_HVC = 1,
+};
+
/*
* ACPI 1.0 Root System Description Table (RSDT)
*/
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (6 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-05-04 10:21 ` Igor Mammedov
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
` (12 subsequent siblings)
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++-
include/hw/arm/virt-acpi-build.h | 2 ++
3 files changed, 100 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index c72a9c8..94cced0 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -50,6 +50,20 @@
#include "qom/qom-qobject.h"
#include "exec/ram_addr.h"
+typedef struct VirtAcpiCpuInfo {
+ DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
+} VirtAcpiCpuInfo;
+
+static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
+{
+ CPUState *cpu;
+
+ memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
+ CPU_FOREACH(cpu) {
+ set_bit(cpu->cpu_index, cpuinfo->found_cpus);
+ }
+}
+
static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
{
uint16_t i;
@@ -146,6 +160,47 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
}
}
+/* MADT */
+static void
+build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
+ VirtAcpiCpuInfo *cpuinfo)
+{
+ int madt_start = table_data->len;
+ const struct AcpiMadtInfo *info = guest_info->madt_info;
+ AcpiMultipleApicTable *madt;
+ AcpiMadtGenericDistributor *gicd;
+ int i;
+
+ madt = acpi_data_push(table_data, sizeof *madt);
+ madt->local_apic_address = info->gic_cpu_memmap->addr;
+ madt->flags = cpu_to_le32(1);
+
+ for (i = 0; i < guest_info->max_cpus; i++) {
+ AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
+ sizeof *gicc);
+ gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
+ gicc->length = sizeof(*gicc);
+ gicc->base_address = info->gic_cpu_memmap->addr;
+ gicc->cpu_interface_number = i;
+ gicc->arm_mpidr = i;
+ gicc->uid = i;
+ if (test_bit(i, cpuinfo->found_cpus)) {
+ gicc->flags = cpu_to_le32(1);
+ } else {
+ gicc->flags = cpu_to_le32(0);
+ }
+ }
+
+ gicd = acpi_data_push(table_data, sizeof *gicd);
+ gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
+ gicd->length = sizeof(*gicd);
+ gicd->base_address = info->gic_dist_memmap->addr;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + madt_start), "APIC",
+ table_data->len - madt_start, 1);
+}
+
/* FADT */
static void
build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
@@ -215,8 +270,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
unsigned dsdt;
+ VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
+ virt_acpi_get_cpu_info(&cpuinfo);
+
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -241,6 +299,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, dsdt);
+ acpi_add_table(table_offsets, tables_blob);
+ build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index bac981d..4092dc3 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -236,7 +236,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_IO_SAPIC 6
#define ACPI_APIC_LOCAL_SAPIC 7
#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+#define ACPI_APIC_LOCAL_X2APIC 9
+#define ACPI_APIC_LOCAL_X2APIC_NMI 10
+#define ACPI_APIC_GENERIC_INTERRUPT 11
+#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
+#define ACPI_APIC_GENERIC_MSI_FRAME 13
+#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
+#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -284,6 +290,36 @@ struct AcpiMadtLocalNmi {
} QEMU_PACKED;
typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+struct AcpiMadtGenericInterrupt {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t cpu_interface_number;
+ uint32_t uid;
+ uint32_t flags;
+ uint32_t parking_version;
+ uint32_t performance_interrupt;
+ uint64_t parked_address;
+ uint64_t base_address;
+ uint64_t gicv_base_address;
+ uint64_t gich_base_address;
+ uint32_t vgic_interrupt;
+ uint64_t gicr_base_address;
+ uint64_t arm_mpidr;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
+
+struct AcpiMadtGenericDistributor {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t gic_id;
+ uint64_t base_address;
+ uint32_t global_irq_base;
+ uint32_t reserved2;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
+
/*
* HPET Description Table
*/
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index ece67a2..8f0b4a7 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -22,6 +22,8 @@
#include "qemu-common.h"
+#define VIRT_ACPI_CPU_ID_LIMIT 8
+
typedef struct MemMap {
hwaddr addr;
hwaddr size;
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 09/20] hw/arm/virt-acpi-build: Generate GTDT table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (7 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
` (11 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 30 ++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 94cced0..7d37357 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -160,6 +160,33 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
}
}
+/* GTDT */
+static void
+build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ int gtdt_start = table_data->len;
+ const struct AcpiGtdtInfo *info = guest_info->gtdt_info;
+ AcpiGenericTimerTable *gtdt;
+
+ gtdt = acpi_data_push(table_data, sizeof *gtdt);
+ /* The interrupt values are the same with the device tree when adding 16 */
+ gtdt->secure_el1_interrupt = info->timer_s_el1;
+ gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el1_interrupt = info->timer_ns_el1;
+ gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->virtual_timer_interrupt = info->timer_virt;
+ gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el2_interrupt = info->timer_ns_el2;
+ gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + gtdt_start), "GTDT",
+ table_data->len - gtdt_start, 1);
+}
+
/* MADT */
static void
build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
@@ -302,6 +329,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+ acpi_add_table(table_offsets, tables_blob);
+ build_gtdt(tables_blob, tables->linker, guest_info);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 4092dc3..7fc0870 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -321,6 +321,43 @@ struct AcpiMadtGenericDistributor {
typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
/*
+ * Generic Timer Description Table (GTDT)
+ */
+
+#define ACPI_GTDT_INTERRUPT_MODE (1 << 0)
+#define ACPI_GTDT_INTERRUPT_POLARITY (1 << 1)
+#define ACPI_GTDT_ALWAYS_ON (1 << 2)
+
+/* Triggering */
+
+#define ACPI_LEVEL_SENSITIVE ((uint8_t) 0x00)
+#define ACPI_EDGE_SENSITIVE ((uint8_t) 0x01)
+
+/* Polarity */
+
+#define ACPI_ACTIVE_HIGH ((uint8_t) 0x00)
+#define ACPI_ACTIVE_LOW ((uint8_t) 0x01)
+#define ACPI_ACTIVE_BOTH ((uint8_t) 0x02)
+
+struct AcpiGenericTimerTable {
+ ACPI_TABLE_HEADER_DEF
+ uint64_t counter_block_addresss;
+ uint32_t reserved;
+ uint32_t secure_el1_interrupt;
+ uint32_t secure_el1_flags;
+ uint32_t non_secure_el1_interrupt;
+ uint32_t non_secure_el1_flags;
+ uint32_t virtual_timer_interrupt;
+ uint32_t virtual_timer_flags;
+ uint32_t non_secure_el2_interrupt;
+ uint32_t non_secure_el2_flags;
+ uint64_t counter_read_block_address;
+ uint32_t platform_timer_count;
+ uint32_t platform_timer_offset;
+} QEMU_PACKED;
+typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
+
+/*
* HPET Description Table
*/
struct Acpi20Hpet {
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (8 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
@ 2015-04-15 13:24 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
` (10 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86.
Here we still use RSDT as UEFI puts ACPI tables below 4G address space,
and UEFI ignore the RSDT or XSDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 24 ++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 3 +++
hw/i386/acpi-build.c | 24 ------------------------
include/hw/acpi/aml-build.h | 2 ++
4 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index babe4d6..b99bb13 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1004,3 +1004,27 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
g_array_free(tables->table_data, true);
g_array_free(tables->tcpalog, mfre);
}
+
+/* Build rsdt table */
+void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
+{
+ AcpiRsdtDescriptorRev1 *rsdt;
+ size_t rsdt_len;
+ int i;
+ const int table_data_len = (sizeof(uint32_t) * table_offsets->len);
+
+ rsdt_len = sizeof(*rsdt) + table_data_len;
+ rsdt = acpi_data_push(table_data, rsdt_len);
+ memcpy(rsdt->table_offset_entry, table_offsets->data, table_data_len);
+ for (i = 0; i < table_offsets->len; ++i) {
+ /* rsdt->table_offset_entry to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &rsdt->table_offset_entry[i],
+ sizeof(uint32_t));
+ }
+ build_header(linker, table_data,
+ (void *)rsdt, "RSDT", rsdt_len, 1);
+}
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 7d37357..abe2abf 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -332,6 +332,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker, guest_info);
+ /* RSDT is pointed to by RSDP */
+ build_rsdt(tables_blob, tables->linker, table_offsets);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 7b5210e..a04bbe7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1195,30 +1195,6 @@ build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
misc->dsdt_size, 1);
}
-/* Build final rsdt table */
-static void
-build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
-{
- AcpiRsdtDescriptorRev1 *rsdt;
- size_t rsdt_len;
- int i;
-
- rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
- rsdt = acpi_data_push(table_data, rsdt_len);
- memcpy(rsdt->table_offset_entry, table_offsets->data,
- sizeof(uint32_t) * table_offsets->len);
- for (i = 0; i < table_offsets->len; ++i) {
- /* rsdt->table_offset_entry to be filled by Guest linker */
- bios_linker_loader_add_pointer(linker,
- ACPI_BUILD_TABLE_FILE,
- ACPI_BUILD_TABLE_FILE,
- table_data, &rsdt->table_offset_entry[i],
- sizeof(uint32_t));
- }
- build_header(linker, table_data,
- (void *)rsdt, "RSDT", rsdt_len, 1);
-}
-
static GArray *
build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 5b60744..d1b9fe7 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -268,5 +268,7 @@ unsigned acpi_data_len(GArray *table);
void acpi_add_table(GArray *table_offsets, GArray *table_data);
void acpi_build_tables_init(AcpiBuildTables *tables);
void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre);
+void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets);
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 11/20] hw/arm/virt-acpi-build: Generate RSDP table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (9 preceding siblings ...)
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
` (9 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index abe2abf..aa4acc6 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -160,6 +160,35 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
}
}
+/* RSDP */
+static GArray *
+build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
+{
+ AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
+
+ bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
+ true /* fseg memory */);
+
+ memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
+ memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
+ rsdp->length = cpu_to_le32(sizeof(*rsdp));
+ rsdp->revision = 0x02;
+
+ /* Point to RSDT */
+ rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
+ /* Address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ rsdp_table, &rsdp->rsdt_physical_address,
+ sizeof rsdp->rsdt_physical_address);
+ rsdp->checksum = 0;
+ /* Checksum to be filled by Guest linker */
+ bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
+ rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
+
+ return rsdp_table;
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -296,7 +325,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
- unsigned dsdt;
+ unsigned dsdt, rsdt;
VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
@@ -333,8 +362,12 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
build_gtdt(tables_blob, tables->linker, guest_info);
/* RSDT is pointed to by RSDP */
+ rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
+ /* RSDP is in FSEG memory, so allocate it separately */
+ build_rsdp(tables->rsdp, tables->linker, rsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (10 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
` (8 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add PCIe info struct, prepare for building PCIe table.
And generate MCFG table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 21 +++++++++++++++++++++
include/hw/arm/virt-acpi-build.h | 9 +++++++++
2 files changed, 30 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index aa4acc6..85e8242 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -189,6 +189,24 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
return rsdp_table;
}
+static void
+build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ AcpiTableMcfg *mcfg;
+ AcpiPcieInfo *info = guest_info->pcie_info;
+ int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
+
+ mcfg = acpi_data_push(table_data, len);
+ mcfg->allocation[0].address = cpu_to_le64(info->pcie_ecam.addr);
+
+ /* Only a single allocation so no need to play with segments */
+ mcfg->allocation[0].pci_segment = cpu_to_le16(0);
+ mcfg->allocation[0].start_bus_number = 0;
+ mcfg->allocation[0].end_bus_number = info->nr_pcie_buses - 1;
+
+ build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1);
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -361,6 +379,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker, guest_info);
+ acpi_add_table(table_offsets, tables_blob);
+ build_mcfg(tables_blob, tables->linker, guest_info);
+
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index 8f0b4a7..572864a 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -52,6 +52,14 @@ typedef struct AcpiDsdtInfo {
const MemMap *flash_memmap;
} AcpiDsdtInfo;
+typedef struct AcpiPcieInfo {
+ const int *pcie_irq;
+ MemMap pcie_mmio;
+ MemMap pcie_ioport;
+ MemMap pcie_ecam;
+ int nr_pcie_buses;
+} AcpiPcieInfo;
+
typedef struct VirtGuestInfo {
int smp_cpus;
int max_cpus;
@@ -59,6 +67,7 @@ typedef struct VirtGuestInfo {
AcpiMadtInfo *madt_info;
AcpiDsdtInfo *dsdt_info;
AcpiGtdtInfo *gtdt_info;
+ AcpiPcieInfo *pcie_info;
} VirtGuestInfo;
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (11 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-28 6:54 ` Igor Mammedov
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
` (7 subsequent siblings)
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 40 ++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index b99bb13..316d5a5 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -25,6 +25,7 @@
#include <stdbool.h>
#include <string.h>
#include "hw/acpi/aml-build.h"
+#include "qemu-common.h"
#include "qemu/bswap.h"
#include "qemu/bitops.h"
#include "hw/acpi/bios-linker-loader.h"
@@ -948,6 +949,45 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
addr_trans, len, flags);
}
+/*
+ * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
+ * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+ * call aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
+ */
+Aml *aml_touuid(const char *uuid)
+{
+ int i;
+ long int val;
+ char *end;
+ const char *start = uuid;
+ Aml *UUID = aml_buffer();
+
+ val = strtol(start, &end, 16);
+ g_assert((end - start) == 8);
+ build_append_int_noprefix(UUID->buf, val, 4);
+ start = end + 1;
+ val = strtol(start, &end, 16);
+ g_assert((end - start) == 4);
+ build_append_int_noprefix(UUID->buf, val, 2);
+ start = end + 1;
+ val = strtol(start, &end, 16);
+ g_assert((end - start) == 4);
+ build_append_int_noprefix(UUID->buf, val, 2);
+ start = end + 1;
+ val = strtol(start, &end, 16);
+ g_assert((end - start) == 4);
+ build_append_int_noprefix(UUID->buf, (val >> 8) & 0xFF, 1);
+ build_append_int_noprefix(UUID->buf, val & 0xFF, 1);
+ start = end + 1;
+ val = strtol(start, &end, 16);
+ g_assert((end - start) == 12);
+ for (i = 40; i >= 0; i -= 8) {
+ build_append_int_noprefix(UUID->buf, (val >> i) & 0xFF, 1);
+ }
+
+ return UUID;
+}
+
void
build_header(GArray *linker, GArray *table_data,
AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index d1b9fe7..b41fd0c 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -259,6 +259,7 @@ Aml *aml_buffer(void);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
+Aml *aml_touuid(const char *uuid);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (12 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-28 6:56 ` Igor Mammedov
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
` (6 subsequent siblings)
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_or() term and expose build_append_int_noprefix
as it wiil be used by creating a buffer.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 12 +++++++++++-
include/hw/acpi/aml-build.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 316d5a5..cd4ffe2 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -242,7 +242,7 @@ static void build_extop_package(GArray *package, uint8_t op)
build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
}
-static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
+void build_append_int_noprefix(GArray *table, uint64_t value, int size)
{
int i;
@@ -456,6 +456,16 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
return var;
}
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
+Aml *aml_or(Aml *arg1, Aml *arg2)
+{
+ Aml *var = aml_opcode(0x7D /* OrOp */);
+ aml_append(var, arg1);
+ aml_append(var, arg2);
+ build_append_byte(var->buf, 0x00 /* NullNameOp */);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
Aml *aml_notify(Aml *arg1, Aml *arg2)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index b41fd0c..61c1a03 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -202,6 +202,7 @@ Aml *aml_int(const uint64_t val);
Aml *aml_arg(int pos);
Aml *aml_store(Aml *val, Aml *target);
Aml *aml_and(Aml *arg1, Aml *arg2);
+Aml *aml_or(Aml *arg1, Aml *arg2);
Aml *aml_notify(Aml *arg1, Aml *arg2);
Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
@@ -260,6 +261,7 @@ Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(const char *uuid);
+void build_append_int_noprefix(GArray *table, uint64_t value, int size);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (13 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-05-05 2:45 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
` (5 subsequent siblings)
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/acpi/aml-build.c | 9 +++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index cd4ffe2..139099f 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -608,6 +608,15 @@ Aml *aml_irq_no_flags(uint8_t irq)
return var;
}
+/* ACPI 1.0: 16.2.3 Operators: DefLNot */
+Aml *aml_not(Aml *arg)
+{
+ Aml *var = aml_opcode(0x92 /* LNotOp */);
+ aml_append(var, arg);
+ build_append_int(var->buf, 0x00); /* NullNameOp */
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
Aml *aml_equal(Aml *arg1, Aml *arg2)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 61c1a03..08b3fbd 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -224,6 +224,7 @@ Aml *aml_named_field(const char *name, unsigned length);
Aml *aml_reserved_field(unsigned length);
Aml *aml_local(int num);
Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
+Aml *aml_not(Aml *arg);
Aml *aml_equal(Aml *arg1, Aml *arg2);
Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...) GCC_FMT_ATTR(4, 5);
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (14 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
` (4 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/acpi/aml-build.c | 7 +++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 139099f..179acda 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -634,6 +634,13 @@ Aml *aml_if(Aml *predicate)
return var;
}
+/* ACPI 1.0: 16.2.3 Operators: DefElse */
+Aml *aml_else(void)
+{
+ Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
Aml *aml_method(const char *name, int arg_count)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 08b3fbd..c322d17 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -256,6 +256,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_method(const char *name, int arg_count);
Aml *aml_if(Aml *predicate);
+Aml *aml_else(void);
Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(void);
Aml *aml_resource_template(void);
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (15 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
` (3 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/acpi/aml-build.c | 11 +++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 179acda..eb5b44f 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -726,6 +726,17 @@ Aml *aml_field(const char *name, AmlFieldFlags flags)
return var;
}
+/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefCreateDWordField */
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x8A); /* CreateDWordFieldOp */
+ aml_append(var, srcbuf);
+ aml_append(var, index);
+ build_append_namestring(var->buf, "%s", name);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
Aml *aml_string(const char *name_format, ...)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index c322d17..72c2396 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -261,6 +261,7 @@ Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(void);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(const char *uuid);
void build_append_int_noprefix(GArray *table, uint64_t value, int size);
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 18/20] hw/acpi/aml-build: Add aml_dword_io() term
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (16 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
` (2 subsequent siblings)
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/acpi/aml-build.c | 18 ++++++++++++++++++
include/hw/acpi/aml-build.h | 5 +++++
2 files changed, 23 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index eb5b44f..fe8fd17 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -947,6 +947,24 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
}
/*
+ * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Descriptor
+ *
+ * More verbose description at:
+ * ACPI 5.0: 19.5.33 DWordIO (DWord IO Resource Descriptor Macro)
+ */
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len)
+
+{
+ return aml_dword_as_desc(aml_io_range, min_fixed, max_fixed, dec,
+ addr_gran, addr_min, addr_max, addr_trans, len,
+ isa_ranges);
+}
+
+/*
* ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
*
* More verbose description at:
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 72c2396..ec38fc1 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -238,6 +238,11 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t addr_gran, uint16_t addr_min,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len);
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len);
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlCacheble cacheable,
AmlReadAndWrite read_and_write,
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (17 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-28 8:42 ` Igor Mammedov
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
2015-04-28 2:49 ` [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add PCIe controller in ACPI DSDT table, so the guest can detect
the PCIe.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 85e8242..ceec405 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -49,6 +49,8 @@
#include "qapi/qmp/qint.h"
#include "qom/qom-qobject.h"
#include "exec/ram_addr.h"
+#include "hw/pci/pcie_host.h"
+#include "hw/pci/pci.h"
typedef struct VirtAcpiCpuInfo {
DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
@@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
}
}
+static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
+{
+ Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
+ int i, bus_no;
+ int irq = *info->pcie_irq + 32;
+
+ Aml *dev = aml_device("%s", "PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
+ aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
+
+ /* Declare the PCI Routing Table. */
+ Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
+ for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ int gsi = (i + bus_no) % PCI_NUM_PINS;
+ Aml *pkg = aml_package(4);
+ aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
+ aml_append(pkg, aml_int(i));
+ aml_append(pkg, aml_name("GSI%d", gsi));
+ aml_append(pkg, aml_int(0));
+ aml_append(rt_pkg, pkg);
+ }
+ }
+ aml_append(dev, aml_name_decl("_PRT", rt_pkg));
+
+ /* Create GSI link device */
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ Aml *dev_gsi = aml_device("GSI%d", i);
+ aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
+ aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_interrupt(aml_consumer, aml_level, aml_active_high,
+ aml_exclusive, aml_not_wake_capable, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_PRS", crs));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_interrupt(aml_consumer, aml_level, aml_active_high,
+ aml_exclusive, aml_not_wake_capable, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_CRS", crs));
+ method = aml_method("_SRS", 1);
+ aml_append(dev_gsi, method);
+ aml_append(dev, dev_gsi);
+ }
+
+ method = aml_method("_CBA", 0);
+ aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0);
+ Aml *rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
+ 0x0000, 0x0000, info->nr_pcie_buses - 1,
+ 0x0000, info->nr_pcie_buses));
+ aml_append(rbuf,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
+ aml_non_cacheable, aml_ReadWrite,
+ 0x0000, info->pcie_mmio.addr,
+ info->pcie_mmio.addr + info->pcie_mmio.size - 1,
+ 0x0000, info->pcie_mmio.size));
+ aml_append(rbuf,
+ aml_dword_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0x0000, 0x0000, info->pcie_ioport.size - 1,
+ info->pcie_ioport.addr, info->pcie_ioport.size));
+
+ aml_append(method, aml_name_decl("RBUF", rbuf));
+ aml_append(method, aml_return(rbuf));
+ aml_append(dev, method);
+
+ /* Declare an _OSC (OS Control Handoff) method */
+ aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
+ aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
+ method = aml_method("_OSC", 4);
+ aml_append(method,
+ aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ /* PCI Firmware Specification 3.0
+ * 4.5.1. _OSC Interface for PCI Host Bridge Devices
+ * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
+ * identified by the Universal Unique IDentifier (UUID)
+ * 33db4d5b-1ff7-401c-9657-7441c03dd766
+ */
+ UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+ aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+ aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
+ aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
+ aml_name("CTRL")));
+
+ ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
+ aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
+ aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
+ aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
+ aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
+ aml_append(ifctx, aml_return(aml_arg(3)));
+ aml_append(method, ifctx);
+
+ elsectx = aml_else();
+ aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
+ aml_name("CDW1")));
+ aml_append(elsectx, aml_return(aml_arg(3)));
+ aml_append(method, elsectx);
+ aml_append(dev, method);
+
+ method = aml_method("_DSM", 4);
+
+ /* PCI Firmware Specification 3.0
+ * 4.6.1. _DSM for PCI Express Slot Information
+ * The UUID in _DSM in this context is
+ * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
+ */
+ UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
+ buf = aml_buffer();
+ build_append_int_noprefix(buf->buf, 0x01, 1);
+ aml_append(ifctx1, aml_return(buf));
+ aml_append(ifctx, ifctx1);
+ aml_append(method, ifctx);
+
+ buf = aml_buffer();
+ build_append_int_noprefix(buf->buf, 0x00, 1);
+ aml_append(method, aml_return(buf));
+ aml_append(dev, method);
+
+ Aml *dev_rp0 = aml_device("%s", "RP0");
+ aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, dev_rp0);
+ aml_append(scope, dev);
+}
+
/* RSDP */
static GArray *
build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
@@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
acpi_dsdt_add_flash(scope, info->flash_memmap);
acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
info->virtio_mmio_irq, info->virtio_mmio_num);
+ acpi_dsdt_add_pci(scope, guest_info->pcie_info);
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Qemu-devel] [PATCH v5 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (18 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
@ 2015-04-15 13:25 ` Shannon Zhao
2015-04-28 2:49 ` [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
20 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-15 13:25 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Expose the needed device information to the table generation
insfrastructure and register a machine_init_done notify to
call virt_acpi_build().
Add CONFIG_ACPI to arm-softmmu.mak.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
default-configs/i386-softmmu.mak | 3 ++
default-configs/mips-softmmu.mak | 3 ++
default-configs/mips64-softmmu.mak | 3 ++
default-configs/mips64el-softmmu.mak | 3 ++
default-configs/mipsel-softmmu.mak | 3 ++
default-configs/x86_64-softmmu.mak | 3 ++
hw/acpi/Makefile.objs | 5 ++-
hw/arm/virt.c | 78 ++++++++++++++++++++++++++++++++----
hw/i2c/Makefile.objs | 2 +-
10 files changed, 94 insertions(+), 10 deletions(-)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a767e4b..74f1db3 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -101,3 +101,4 @@ CONFIG_ALLWINNER_A10=y
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
+CONFIG_ACPI=y
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 6a74e00..d2de500 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak
index cce2c81..c96d42d 100644
--- a/default-configs/mips-softmmu.mak
+++ b/default-configs/mips-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak
index 7a88a08..d229f9e 100644
--- a/default-configs/mips64-softmmu.mak
+++ b/default-configs/mips64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
index 095de43..ea31b8b 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak
index 0e25108..9a4462e 100644
--- a/default-configs/mipsel-softmmu.mak
+++ b/default-configs/mipsel-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 46b87dd..11019b6 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index b9fefa7..511771a 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,5 +1,6 @@
-common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o cpu_hotplug.o
-common-obj-$(CONFIG_ACPI) += memory_hotplug.o
+common-obj-$(CONFIG_ACPI_CORE) += core.o piix4.o ich9.o pcihp.o
+common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
+common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
common-obj-$(CONFIG_ACPI) += aml-build.o
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b652b07..e968ad5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -43,6 +43,7 @@
#include "qemu/bitops.h"
#include "qemu/error-report.h"
#include "hw/pci-host/gpex.h"
+#include "hw/arm/virt-acpi-build.h"
#define NUM_VIRTIO_TRANSPORTS 32
@@ -60,6 +61,11 @@
#define GIC_FDT_IRQ_PPI_CPU_START 8
#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
+#define ARCH_TIMER_VIRT_IRQ 11
+#define ARCH_TIMER_S_EL1_IRQ 13
+#define ARCH_TIMER_NS_EL1_IRQ 14
+#define ARCH_TIMER_NS_EL2_IRQ 10
+
enum {
VIRT_FLASH,
VIRT_MEM,
@@ -149,6 +155,29 @@ static const int a15irqmap[] = {
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
};
+static AcpiMadtInfo madt_info = {
+ (MemMap *)&a15memmap[VIRT_GIC_CPU],
+ (MemMap *)&a15memmap[VIRT_GIC_DIST]
+};
+
+static AcpiDsdtInfo dsdt_info = {
+ (MemMap *)&a15memmap[VIRT_UART],
+ .uart_irq = &a15irqmap[VIRT_UART],
+ (MemMap *)&a15memmap[VIRT_MMIO],
+ .virtio_mmio_irq = &a15irqmap[VIRT_MMIO],
+ .virtio_mmio_num = NUM_VIRTIO_TRANSPORTS,
+ (MemMap *)&a15memmap[VIRT_RTC],
+ .rtc_irq = &a15irqmap[VIRT_RTC],
+ (MemMap *)&a15memmap[VIRT_FLASH],
+};
+
+static AcpiGtdtInfo gtdt_info = {
+ ARCH_TIMER_VIRT_IRQ + 16,
+ ARCH_TIMER_S_EL1_IRQ + 16,
+ ARCH_TIMER_NS_EL1_IRQ + 16,
+ ARCH_TIMER_NS_EL2_IRQ + 16
+};
+
static VirtBoardInfo machines[] = {
{
.cpu_model = "cortex-a15",
@@ -289,10 +318,10 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
"arm,armv7-timer");
}
qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 11, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 10, irqflags);
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
}
static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
@@ -633,8 +662,8 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
0x7 /* PCI irq */);
}
-static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
- uint32_t gic_phandle)
+static AcpiPcieInfo *create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
+ uint32_t gic_phandle)
{
hwaddr base = vbi->memmap[VIRT_PCIE].base;
hwaddr size = vbi->memmap[VIRT_PCIE].size;
@@ -654,6 +683,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
DeviceState *dev;
char *nodename;
int i;
+ AcpiPcieInfo *pcie_info;
base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
@@ -709,6 +739,18 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
create_pcie_irq_map(vbi, gic_phandle, irq, nodename);
g_free(nodename);
+
+ pcie_info = g_malloc0(sizeof *pcie_info);
+ pcie_info->pcie_mmio.addr = base_mmio;
+ pcie_info->pcie_mmio.size = size_mmio;
+ pcie_info->pcie_ioport.addr = base_ioport;
+ pcie_info->pcie_ioport.size = size_ioport;
+ pcie_info->pcie_ecam.addr = base_ecam;
+ pcie_info->pcie_ecam.size = size_ecam;
+ pcie_info->nr_pcie_buses = nr_pcie_buses;
+ pcie_info->pcie_irq = &a15irqmap[VIRT_PCIE];
+
+ return pcie_info;
}
static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
@@ -719,6 +761,15 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
return board->fdt;
}
+static
+void virt_guest_info_machine_done(Notifier *notifier, void *data)
+{
+ VirtGuestInfoState *guest_info_state = container_of(notifier,
+ VirtGuestInfoState,
+ machine_done);
+ virt_acpi_setup(&guest_info_state->info);
+}
+
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms = VIRT_MACHINE(machine);
@@ -728,6 +779,8 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
const char *cpu_model = machine->cpu_model;
VirtBoardInfo *vbi;
+ VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
+ VirtGuestInfo *guest_info = &guest_info_state->info;
uint32_t gic_phandle;
char **cpustr;
@@ -812,7 +865,7 @@ static void machvirt_init(MachineState *machine)
create_rtc(vbi, pic);
- create_pcie(vbi, pic, gic_phandle);
+ guest_info->pcie_info = create_pcie(vbi, pic, gic_phandle);
/* Create mmio transports, so the user can create virtio backends
* (which will be automatically plugged in to the transports). If
@@ -821,6 +874,7 @@ static void machvirt_init(MachineState *machine)
create_virtio_devices(vbi, pic);
create_fw_cfg(vbi);
+ rom_set_fw(fw_cfg_find());
vbi->bootinfo.ram_size = machine->ram_size;
vbi->bootinfo.kernel_filename = machine->kernel_filename;
@@ -831,6 +885,16 @@ static void machvirt_init(MachineState *machine)
vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
vbi->bootinfo.get_dtb = machvirt_dtb;
vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
+
+ guest_info->smp_cpus = smp_cpus;
+ guest_info->max_cpus = max_cpus;
+ guest_info->fw_cfg = fw_cfg_find();
+ guest_info->madt_info = &madt_info;
+ guest_info->dsdt_info = &dsdt_info;
+ guest_info->gtdt_info = >dt_info;
+ guest_info_state->machine_done.notify = virt_guest_info_machine_done;
+ qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
+
arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
}
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 648278e..c94e6e6 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,6 +1,6 @@
common-obj-y += core.o smbus.o smbus_eeprom.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
-common-obj-$(CONFIG_ACPI) += smbus_ich9.o
+common-obj-$(CONFIG_ACPI_CORE) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
--
2.0.4
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (19 preceding siblings ...)
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
@ 2015-04-28 2:49 ` Shannon Zhao
2015-04-28 5:20 ` Michael S. Tsirkin
20 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 2:49 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, peter.huangpeng, shannon.zhao
On 2015/4/15 21:24, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patch series generate seven ACPI tables for machine virt on ARM.
> The set of generated tables are:
> - RSDP
> - RSDT
> - MADT
> - GTDT
> - FADT
> - DSDT
> - MCFG (For PCIe host bridge)
>
> These tables are created dynamically using the function of aml-build.c,
> taking into account the needed information passed from the virt machine model.
> When the generation is finalized, it use fw_cfg to expose the tables to guest.
>
> You can fetch this from following repo:
> http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v5
>
> And this patchset refers to Alexander Spyridakis's patches which are sent to
> qemu-devel mailing list before.
> http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
>
> Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
> ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
> startup test and attach virtio-net-pci, e1000:
>
> xp, windows2008, sles11 on X86
> Fedora Linux kernel on ARM64
>
> Note:
> As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
> Fedora Linux kernel from following address:
> https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
>
> changes since v4:
> * use trace_* instead of DPRINTF (Igor & Alex)
> * use standard QEMU style for structs (Michael)
> * add "-no-acpi" option support for arm
> * use extractNN for bits operation (Alex)
> * use AmlReadAndWrite enum for rw flags (Igor)
> * s/uint64_t/uint32_t/ (Igor)
> * use enum for interrupt flag (Igor)
> * simplify aml_device use in DSDT (Alex)
> * share RSDT table generating code with x86 (Igor)
> * remove unnecessary 1 in MCFG table generating code (Alex & Peter)
> * use string for ToUUID macro (Igor)
> * aml_or and aml_and use two args (Igor)
> * add comments on UUID (Michael)
> * change PCI MMIO region non-cacheable (Peter)
> * fix wrong io map (Peter)
> * add several reviewed-by's from Alex, thanks
>
> changes since v3:
> * rebase on upstream qemu
> * fix _HID of CPU (Heyi Guo)
> * Add PCIe host bridge
>
> changes since v2:
> * rebase on Igor Mammedov's new branch ASL_API_v3
> * use rsdt instead of xsdt according to Igor Mammedov's suggestion
>
> changes since v1:
> * fix bug found by Laszlo
> * move common helpers into dedictated file and change generating
> table order according to Igor's comments
> * fix copyright and function name according to Michael's comments
>
> Shannon Zhao (20):
> hw/i386: Move ACPI header definitions in an arch-independent location
> hw/i386/acpi-build: move generic acpi building helpers into dedictated
> file
> hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
> ARM
> hw/acpi/aml-build: Add aml_memory32_fixed() term
> hw/acpi/aml-build: Add aml_interrupt() term
> hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
> hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
> hw/arm/virt-acpi-build: Generate MADT table
> hw/arm/virt-acpi-build: Generate GTDT table
> hw/arm/virt-acpi-build: Generate RSDT table
> hw/arm/virt-acpi-build: Generate RSDP table
> hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
> hw/acpi/aml-build: Add ToUUID macro
> hw/acpi/aml-build: Add aml_or() term
> hw/acpi/aml-build: Add aml_not() term
> hw/acpi/aml-build: Add aml_else() term
> hw/acpi/aml-build: Add aml_create_dword_field() term
> hw/acpi/aml-build: Add aml_dword_io() term
> hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
> hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
>
> default-configs/arm-softmmu.mak | 1 +
> default-configs/i386-softmmu.mak | 3 +
> default-configs/mips-softmmu.mak | 3 +
> default-configs/mips64-softmmu.mak | 3 +
> default-configs/mips64el-softmmu.mak | 3 +
> default-configs/mipsel-softmmu.mak | 3 +
> default-configs/x86_64-softmmu.mak | 3 +
> hw/acpi/Makefile.objs | 5 +-
> hw/acpi/aml-build.c | 234 ++++++++++++-
> hw/arm/Makefile.objs | 1 +
> hw/arm/virt-acpi-build.c | 650 +++++++++++++++++++++++++++++++++++
> hw/arm/virt.c | 78 ++++-
> hw/i2c/Makefile.objs | 2 +-
> hw/i386/acpi-build.c | 103 +-----
> hw/i386/acpi-defs.h | 368 --------------------
> include/hw/acpi/acpi-defs.h | 482 ++++++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 94 +++++
> include/hw/arm/virt-acpi-build.h | 81 +++++
> qemu-options.hx | 2 +-
> tests/bios-tables-test.c | 2 +-
> trace-events | 3 +
> 21 files changed, 1641 insertions(+), 483 deletions(-)
> create mode 100644 hw/arm/virt-acpi-build.c
> delete mode 100644 hw/i386/acpi-defs.h
> create mode 100644 include/hw/acpi/acpi-defs.h
> create mode 100644 include/hw/arm/virt-acpi-build.h
>
Ping？
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-04-28 2:49 ` [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
@ 2015-04-28 5:20 ` Michael S. Tsirkin
2015-04-28 6:13 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Michael S. Tsirkin @ 2015-04-28 5:20 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, Apr 28, 2015 at 10:49:42AM +0800, Shannon Zhao wrote:
> On 2015/4/15 21:24, Shannon Zhao wrote:
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > This patch series generate seven ACPI tables for machine virt on ARM.
> > The set of generated tables are:
> > - RSDP
> > - RSDT
> > - MADT
> > - GTDT
> > - FADT
> > - DSDT
> > - MCFG (For PCIe host bridge)
> >
> > These tables are created dynamically using the function of aml-build.c,
> > taking into account the needed information passed from the virt machine model.
> > When the generation is finalized, it use fw_cfg to expose the tables to guest.
> >
> > You can fetch this from following repo:
> > http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v5
> >
> > And this patchset refers to Alexander Spyridakis's patches which are sent to
> > qemu-devel mailing list before.
> > http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
> >
> > Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
> > ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
> > startup test and attach virtio-net-pci, e1000:
> >
> > xp, windows2008, sles11 on X86
> > Fedora Linux kernel on ARM64
> >
> > Note:
> > As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
> > Fedora Linux kernel from following address:
> > https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
> >
> > changes since v4:
> > * use trace_* instead of DPRINTF (Igor & Alex)
> > * use standard QEMU style for structs (Michael)
> > * add "-no-acpi" option support for arm
> > * use extractNN for bits operation (Alex)
> > * use AmlReadAndWrite enum for rw flags (Igor)
> > * s/uint64_t/uint32_t/ (Igor)
> > * use enum for interrupt flag (Igor)
> > * simplify aml_device use in DSDT (Alex)
> > * share RSDT table generating code with x86 (Igor)
> > * remove unnecessary 1 in MCFG table generating code (Alex & Peter)
> > * use string for ToUUID macro (Igor)
> > * aml_or and aml_and use two args (Igor)
> > * add comments on UUID (Michael)
> > * change PCI MMIO region non-cacheable (Peter)
> > * fix wrong io map (Peter)
> > * add several reviewed-by's from Alex, thanks
> >
> > changes since v3:
> > * rebase on upstream qemu
> > * fix _HID of CPU (Heyi Guo)
> > * Add PCIe host bridge
> >
> > changes since v2:
> > * rebase on Igor Mammedov's new branch ASL_API_v3
> > * use rsdt instead of xsdt according to Igor Mammedov's suggestion
> >
> > changes since v1:
> > * fix bug found by Laszlo
> > * move common helpers into dedictated file and change generating
> > table order according to Igor's comments
> > * fix copyright and function name according to Michael's comments
> >
> > Shannon Zhao (20):
> > hw/i386: Move ACPI header definitions in an arch-independent location
> > hw/i386/acpi-build: move generic acpi building helpers into dedictated
> > file
> > hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
> > ARM
> > hw/acpi/aml-build: Add aml_memory32_fixed() term
> > hw/acpi/aml-build: Add aml_interrupt() term
> > hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
> > hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
> > hw/arm/virt-acpi-build: Generate MADT table
> > hw/arm/virt-acpi-build: Generate GTDT table
> > hw/arm/virt-acpi-build: Generate RSDT table
> > hw/arm/virt-acpi-build: Generate RSDP table
> > hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
> > hw/acpi/aml-build: Add ToUUID macro
> > hw/acpi/aml-build: Add aml_or() term
> > hw/acpi/aml-build: Add aml_not() term
> > hw/acpi/aml-build: Add aml_else() term
> > hw/acpi/aml-build: Add aml_create_dword_field() term
> > hw/acpi/aml-build: Add aml_dword_io() term
> > hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
> > hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
> >
> > default-configs/arm-softmmu.mak | 1 +
> > default-configs/i386-softmmu.mak | 3 +
> > default-configs/mips-softmmu.mak | 3 +
> > default-configs/mips64-softmmu.mak | 3 +
> > default-configs/mips64el-softmmu.mak | 3 +
> > default-configs/mipsel-softmmu.mak | 3 +
> > default-configs/x86_64-softmmu.mak | 3 +
> > hw/acpi/Makefile.objs | 5 +-
> > hw/acpi/aml-build.c | 234 ++++++++++++-
> > hw/arm/Makefile.objs | 1 +
> > hw/arm/virt-acpi-build.c | 650 +++++++++++++++++++++++++++++++++++
> > hw/arm/virt.c | 78 ++++-
> > hw/i2c/Makefile.objs | 2 +-
> > hw/i386/acpi-build.c | 103 +-----
> > hw/i386/acpi-defs.h | 368 --------------------
> > include/hw/acpi/acpi-defs.h | 482 ++++++++++++++++++++++++++
> > include/hw/acpi/aml-build.h | 94 +++++
> > include/hw/arm/virt-acpi-build.h | 81 +++++
> > qemu-options.hx | 2 +-
> > tests/bios-tables-test.c | 2 +-
> > trace-events | 3 +
> > 21 files changed, 1641 insertions(+), 483 deletions(-)
> > create mode 100644 hw/arm/virt-acpi-build.c
> > delete mode 100644 hw/i386/acpi-defs.h
> > create mode 100644 include/hw/acpi/acpi-defs.h
> > create mode 100644 include/hw/arm/virt-acpi-build.h
> >
>
> Ping？
I merged first 2 patches in my tree, plan to send pull request soon.
> --
> Thanks,
> Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-04-28 5:20 ` Michael S. Tsirkin
@ 2015-04-28 6:13 ` Shannon Zhao
2015-04-28 6:56 ` Michael S. Tsirkin
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 6:13 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/28 13:20, Michael S. Tsirkin wrote:
> On Tue, Apr 28, 2015 at 10:49:42AM +0800, Shannon Zhao wrote:
>> On 2015/4/15 21:24, Shannon Zhao wrote:
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> This patch series generate seven ACPI tables for machine virt on ARM.
>>> The set of generated tables are:
>>> - RSDP
>>> - RSDT
>>> - MADT
>>> - GTDT
>>> - FADT
>>> - DSDT
>>> - MCFG (For PCIe host bridge)
>>>
>>> These tables are created dynamically using the function of aml-build.c,
>>> taking into account the needed information passed from the virt machine model.
>>> When the generation is finalized, it use fw_cfg to expose the tables to guest.
>>>
>>> You can fetch this from following repo:
>>> http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v5
>>>
>>> And this patchset refers to Alexander Spyridakis's patches which are sent to
>>> qemu-devel mailing list before.
>>> http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
>>>
>>> Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
>>> ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
>>> startup test and attach virtio-net-pci, e1000:
>>>
>>> xp, windows2008, sles11 on X86
>>> Fedora Linux kernel on ARM64
>>>
>>> Note:
>>> As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
>>> Fedora Linux kernel from following address:
>>> https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
>>>
>>> changes since v4:
>>> * use trace_* instead of DPRINTF (Igor & Alex)
>>> * use standard QEMU style for structs (Michael)
>>> * add "-no-acpi" option support for arm
>>> * use extractNN for bits operation (Alex)
>>> * use AmlReadAndWrite enum for rw flags (Igor)
>>> * s/uint64_t/uint32_t/ (Igor)
>>> * use enum for interrupt flag (Igor)
>>> * simplify aml_device use in DSDT (Alex)
>>> * share RSDT table generating code with x86 (Igor)
>>> * remove unnecessary 1 in MCFG table generating code (Alex & Peter)
>>> * use string for ToUUID macro (Igor)
>>> * aml_or and aml_and use two args (Igor)
>>> * add comments on UUID (Michael)
>>> * change PCI MMIO region non-cacheable (Peter)
>>> * fix wrong io map (Peter)
>>> * add several reviewed-by's from Alex, thanks
>>>
>>> changes since v3:
>>> * rebase on upstream qemu
>>> * fix _HID of CPU (Heyi Guo)
>>> * Add PCIe host bridge
>>>
>>> changes since v2:
>>> * rebase on Igor Mammedov's new branch ASL_API_v3
>>> * use rsdt instead of xsdt according to Igor Mammedov's suggestion
>>>
>>> changes since v1:
>>> * fix bug found by Laszlo
>>> * move common helpers into dedictated file and change generating
>>> table order according to Igor's comments
>>> * fix copyright and function name according to Michael's comments
>>>
>>> Shannon Zhao (20):
>>> hw/i386: Move ACPI header definitions in an arch-independent location
>>> hw/i386/acpi-build: move generic acpi building helpers into dedictated
>>> file
>>> hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
>>> ARM
>>> hw/acpi/aml-build: Add aml_memory32_fixed() term
>>> hw/acpi/aml-build: Add aml_interrupt() term
>>> hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
>>> hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
>>> hw/arm/virt-acpi-build: Generate MADT table
>>> hw/arm/virt-acpi-build: Generate GTDT table
>>> hw/arm/virt-acpi-build: Generate RSDT table
>>> hw/arm/virt-acpi-build: Generate RSDP table
>>> hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
>>> hw/acpi/aml-build: Add ToUUID macro
>>> hw/acpi/aml-build: Add aml_or() term
>>> hw/acpi/aml-build: Add aml_not() term
>>> hw/acpi/aml-build: Add aml_else() term
>>> hw/acpi/aml-build: Add aml_create_dword_field() term
>>> hw/acpi/aml-build: Add aml_dword_io() term
>>> hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
>>> hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
>>>
>>> default-configs/arm-softmmu.mak | 1 +
>>> default-configs/i386-softmmu.mak | 3 +
>>> default-configs/mips-softmmu.mak | 3 +
>>> default-configs/mips64-softmmu.mak | 3 +
>>> default-configs/mips64el-softmmu.mak | 3 +
>>> default-configs/mipsel-softmmu.mak | 3 +
>>> default-configs/x86_64-softmmu.mak | 3 +
>>> hw/acpi/Makefile.objs | 5 +-
>>> hw/acpi/aml-build.c | 234 ++++++++++++-
>>> hw/arm/Makefile.objs | 1 +
>>> hw/arm/virt-acpi-build.c | 650 +++++++++++++++++++++++++++++++++++
>>> hw/arm/virt.c | 78 ++++-
>>> hw/i2c/Makefile.objs | 2 +-
>>> hw/i386/acpi-build.c | 103 +-----
>>> hw/i386/acpi-defs.h | 368 --------------------
>>> include/hw/acpi/acpi-defs.h | 482 ++++++++++++++++++++++++++
>>> include/hw/acpi/aml-build.h | 94 +++++
>>> include/hw/arm/virt-acpi-build.h | 81 +++++
>>> qemu-options.hx | 2 +-
>>> tests/bios-tables-test.c | 2 +-
>>> trace-events | 3 +
>>> 21 files changed, 1641 insertions(+), 483 deletions(-)
>>> create mode 100644 hw/arm/virt-acpi-build.c
>>> delete mode 100644 hw/i386/acpi-defs.h
>>> create mode 100644 include/hw/acpi/acpi-defs.h
>>> create mode 100644 include/hw/arm/virt-acpi-build.h
>>>
>>
>> Ping？
>
> I merged first 2 patches in my tree, plan to send pull request soon.
>
Michael, Thanks.
BTW, in your opinion whoes tree could the other patches be merged through?
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-04-28 6:54 ` Igor Mammedov
2015-04-28 7:46 ` Shannon Zhao
2015-04-28 8:08 ` Shannon Zhao
0 siblings, 2 replies; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 6:54 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Wed, 15 Apr 2015 21:25:02 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add ToUUID macro, this is useful for generating PCIe ACPI table.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 40 ++++++++++++++++++++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 41 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index b99bb13..316d5a5 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -25,6 +25,7 @@
> #include <stdbool.h>
> #include <string.h>
> #include "hw/acpi/aml-build.h"
> +#include "qemu-common.h"
why do you need this hunk?
> #include "qemu/bswap.h"
> #include "qemu/bitops.h"
> #include "hw/acpi/bios-linker-loader.h"
> @@ -948,6 +949,45 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> addr_trans, len, flags);
> }
>
> +/*
> + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
> + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> + * call aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> + */
> +Aml *aml_touuid(const char *uuid)
> +{
> + int i;
> + long int val;
unsigned long long int ???
> + char *end;
> + const char *start = uuid;
> + Aml *UUID = aml_buffer();
s/UUID/var/
> +
> + val = strtol(start, &end, 16);
may be use strtoull()
> + g_assert((end - start) == 8);
> + build_append_int_noprefix(UUID->buf, val, 4);
> + start = end + 1;
> + val = strtol(start, &end, 16);
> + g_assert((end - start) == 4);
> + build_append_int_noprefix(UUID->buf, val, 2);
> + start = end + 1;
> + val = strtol(start, &end, 16);
> + g_assert((end - start) == 4);
> + build_append_int_noprefix(UUID->buf, val, 2);
this corresponds to -gghh- part of UUID according to spec
it would be better if you add pattern mentioned in spec
in this function and then put comments marking places
which handle specific part of it.
> + start = end + 1;
> + val = strtol(start, &end, 16);
> + g_assert((end - start) == 4);
> + build_append_int_noprefix(UUID->buf, (val >> 8) & 0xFF, 1);
> + build_append_int_noprefix(UUID->buf, val & 0xFF, 1);
add comment to it that according to spec bytes here are flipped around
that's why special treatment.
> + start = end + 1;
> + val = strtol(start, &end, 16);
> + g_assert((end - start) == 12);
> + for (i = 40; i >= 0; i -= 8) {
> + build_append_int_noprefix(UUID->buf, (val >> i) & 0xFF, 1);
> + }
> +
btw:
whole thing might be simpler if an intermediate conversion is avoided,
just pack buffer as in spec byte by byte:
/* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
assert(strlen(uuid) == ...);
build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
...
easy to validate just by looking at "UUID Buffer Format" table in spec
> + return UUID;
> +}
> +
> void
> build_header(GArray *linker, GArray *table_data,
> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index d1b9fe7..b41fd0c 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -259,6 +259,7 @@ Aml *aml_buffer(void);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlFieldFlags flags);
> Aml *aml_varpackage(uint32_t num_elements);
> +Aml *aml_touuid(const char *uuid);
>
> void
> build_header(GArray *linker, GArray *table_data,
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-04-28 6:13 ` Shannon Zhao
@ 2015-04-28 6:56 ` Michael S. Tsirkin
0 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2015-04-28 6:56 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, Apr 28, 2015 at 02:13:29PM +0800, Shannon Zhao wrote:
> On 2015/4/28 13:20, Michael S. Tsirkin wrote:
> > On Tue, Apr 28, 2015 at 10:49:42AM +0800, Shannon Zhao wrote:
> >> On 2015/4/15 21:24, Shannon Zhao wrote:
> >>> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>>
> >>> This patch series generate seven ACPI tables for machine virt on ARM.
> >>> The set of generated tables are:
> >>> - RSDP
> >>> - RSDT
> >>> - MADT
> >>> - GTDT
> >>> - FADT
> >>> - DSDT
> >>> - MCFG (For PCIe host bridge)
> >>>
> >>> These tables are created dynamically using the function of aml-build.c,
> >>> taking into account the needed information passed from the virt machine model.
> >>> When the generation is finalized, it use fw_cfg to expose the tables to guest.
> >>>
> >>> You can fetch this from following repo:
> >>> http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v5
> >>>
> >>> And this patchset refers to Alexander Spyridakis's patches which are sent to
> >>> qemu-devel mailing list before.
> >>> http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
> >>>
> >>> Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
> >>> ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
> >>> startup test and attach virtio-net-pci, e1000:
> >>>
> >>> xp, windows2008, sles11 on X86
> >>> Fedora Linux kernel on ARM64
> >>>
> >>> Note:
> >>> As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
> >>> Fedora Linux kernel from following address:
> >>> https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
> >>>
> >>> changes since v4:
> >>> * use trace_* instead of DPRINTF (Igor & Alex)
> >>> * use standard QEMU style for structs (Michael)
> >>> * add "-no-acpi" option support for arm
> >>> * use extractNN for bits operation (Alex)
> >>> * use AmlReadAndWrite enum for rw flags (Igor)
> >>> * s/uint64_t/uint32_t/ (Igor)
> >>> * use enum for interrupt flag (Igor)
> >>> * simplify aml_device use in DSDT (Alex)
> >>> * share RSDT table generating code with x86 (Igor)
> >>> * remove unnecessary 1 in MCFG table generating code (Alex & Peter)
> >>> * use string for ToUUID macro (Igor)
> >>> * aml_or and aml_and use two args (Igor)
> >>> * add comments on UUID (Michael)
> >>> * change PCI MMIO region non-cacheable (Peter)
> >>> * fix wrong io map (Peter)
> >>> * add several reviewed-by's from Alex, thanks
> >>>
> >>> changes since v3:
> >>> * rebase on upstream qemu
> >>> * fix _HID of CPU (Heyi Guo)
> >>> * Add PCIe host bridge
> >>>
> >>> changes since v2:
> >>> * rebase on Igor Mammedov's new branch ASL_API_v3
> >>> * use rsdt instead of xsdt according to Igor Mammedov's suggestion
> >>>
> >>> changes since v1:
> >>> * fix bug found by Laszlo
> >>> * move common helpers into dedictated file and change generating
> >>> table order according to Igor's comments
> >>> * fix copyright and function name according to Michael's comments
> >>>
> >>> Shannon Zhao (20):
> >>> hw/i386: Move ACPI header definitions in an arch-independent location
> >>> hw/i386/acpi-build: move generic acpi building helpers into dedictated
> >>> file
> >>> hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
> >>> ARM
> >>> hw/acpi/aml-build: Add aml_memory32_fixed() term
> >>> hw/acpi/aml-build: Add aml_interrupt() term
> >>> hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
> >>> hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
> >>> hw/arm/virt-acpi-build: Generate MADT table
> >>> hw/arm/virt-acpi-build: Generate GTDT table
> >>> hw/arm/virt-acpi-build: Generate RSDT table
> >>> hw/arm/virt-acpi-build: Generate RSDP table
> >>> hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
> >>> hw/acpi/aml-build: Add ToUUID macro
> >>> hw/acpi/aml-build: Add aml_or() term
> >>> hw/acpi/aml-build: Add aml_not() term
> >>> hw/acpi/aml-build: Add aml_else() term
> >>> hw/acpi/aml-build: Add aml_create_dword_field() term
> >>> hw/acpi/aml-build: Add aml_dword_io() term
> >>> hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
> >>> hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
> >>>
> >>> default-configs/arm-softmmu.mak | 1 +
> >>> default-configs/i386-softmmu.mak | 3 +
> >>> default-configs/mips-softmmu.mak | 3 +
> >>> default-configs/mips64-softmmu.mak | 3 +
> >>> default-configs/mips64el-softmmu.mak | 3 +
> >>> default-configs/mipsel-softmmu.mak | 3 +
> >>> default-configs/x86_64-softmmu.mak | 3 +
> >>> hw/acpi/Makefile.objs | 5 +-
> >>> hw/acpi/aml-build.c | 234 ++++++++++++-
> >>> hw/arm/Makefile.objs | 1 +
> >>> hw/arm/virt-acpi-build.c | 650 +++++++++++++++++++++++++++++++++++
> >>> hw/arm/virt.c | 78 ++++-
> >>> hw/i2c/Makefile.objs | 2 +-
> >>> hw/i386/acpi-build.c | 103 +-----
> >>> hw/i386/acpi-defs.h | 368 --------------------
> >>> include/hw/acpi/acpi-defs.h | 482 ++++++++++++++++++++++++++
> >>> include/hw/acpi/aml-build.h | 94 +++++
> >>> include/hw/arm/virt-acpi-build.h | 81 +++++
> >>> qemu-options.hx | 2 +-
> >>> tests/bios-tables-test.c | 2 +-
> >>> trace-events | 3 +
> >>> 21 files changed, 1641 insertions(+), 483 deletions(-)
> >>> create mode 100644 hw/arm/virt-acpi-build.c
> >>> delete mode 100644 hw/i386/acpi-defs.h
> >>> create mode 100644 include/hw/acpi/acpi-defs.h
> >>> create mode 100644 include/hw/arm/virt-acpi-build.h
> >>>
> >>
> >> Ping？
> >
> > I merged first 2 patches in my tree, plan to send pull request soon.
> >
>
> Michael, Thanks.
> BTW, in your opinion whoes tree could the other patches be merged through?
Peter's ARM tree.
> --
> Thanks,
> Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-04-28 6:56 ` Igor Mammedov
2015-04-28 7:12 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 6:56 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Wed, 15 Apr 2015 21:25:03 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add aml_or() term and expose build_append_int_noprefix
> as it wiil be used by creating a buffer.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 12 +++++++++++-
> include/hw/acpi/aml-build.h | 2 ++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 316d5a5..cd4ffe2 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -242,7 +242,7 @@ static void build_extop_package(GArray *package, uint8_t op)
> build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
> }
>
> -static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
> +void build_append_int_noprefix(GArray *table, uint64_t value, int size)
> {
> int i;
>
> @@ -456,6 +456,16 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
> +Aml *aml_or(Aml *arg1, Aml *arg2)
> +{
> + Aml *var = aml_opcode(0x7D /* OrOp */);
> + aml_append(var, arg1);
> + aml_append(var, arg2);
> + build_append_byte(var->buf, 0x00 /* NullNameOp */);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
> Aml *aml_notify(Aml *arg1, Aml *arg2)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index b41fd0c..61c1a03 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -202,6 +202,7 @@ Aml *aml_int(const uint64_t val);
> Aml *aml_arg(int pos);
> Aml *aml_store(Aml *val, Aml *target);
> Aml *aml_and(Aml *arg1, Aml *arg2);
> +Aml *aml_or(Aml *arg1, Aml *arg2);
> Aml *aml_notify(Aml *arg1, Aml *arg2);
> Aml *aml_call1(const char *method, Aml *arg1);
> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> @@ -260,6 +261,7 @@ Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlFieldFlags flags);
> Aml *aml_varpackage(uint32_t num_elements);
> Aml *aml_touuid(const char *uuid);
> +void build_append_int_noprefix(GArray *table, uint64_t value, int size);
why does it exports internal function and
why it's related to this patch in particular?
>
> void
> build_header(GArray *linker, GArray *table_data,
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-28 6:56 ` Igor Mammedov
@ 2015-04-28 7:12 ` Shannon Zhao
0 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 7:12 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 14:56, Igor Mammedov wrote:
> On Wed, 15 Apr 2015 21:25:03 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add aml_or() term and expose build_append_int_noprefix
>> as it wiil be used by creating a buffer.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/acpi/aml-build.c | 12 +++++++++++-
>> include/hw/acpi/aml-build.h | 2 ++
>> 2 files changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 316d5a5..cd4ffe2 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -242,7 +242,7 @@ static void build_extop_package(GArray *package, uint8_t op)
>> build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
>> }
>>
>> -static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
>> +void build_append_int_noprefix(GArray *table, uint64_t value, int size)
>> {
>> int i;
>>
>> @@ -456,6 +456,16 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
>> return var;
>> }
>>
>> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
>> +Aml *aml_or(Aml *arg1, Aml *arg2)
>> +{
>> + Aml *var = aml_opcode(0x7D /* OrOp */);
>> + aml_append(var, arg1);
>> + aml_append(var, arg2);
>> + build_append_byte(var->buf, 0x00 /* NullNameOp */);
>> + return var;
>> +}
>> +
>> /* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
>> Aml *aml_notify(Aml *arg1, Aml *arg2)
>> {
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index b41fd0c..61c1a03 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -202,6 +202,7 @@ Aml *aml_int(const uint64_t val);
>> Aml *aml_arg(int pos);
>> Aml *aml_store(Aml *val, Aml *target);
>> Aml *aml_and(Aml *arg1, Aml *arg2);
>> +Aml *aml_or(Aml *arg1, Aml *arg2);
>> Aml *aml_notify(Aml *arg1, Aml *arg2);
>> Aml *aml_call1(const char *method, Aml *arg1);
>> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
>> @@ -260,6 +261,7 @@ Aml *aml_resource_template(void);
>> Aml *aml_field(const char *name, AmlFieldFlags flags);
>> Aml *aml_varpackage(uint32_t num_elements);
>> Aml *aml_touuid(const char *uuid);
>> +void build_append_int_noprefix(GArray *table, uint64_t value, int size);
> why does it exports internal function and
This will be used for adding elements to buffer like in ptach 19/20.
+ buf = aml_buffer();
+ build_append_int_noprefix(buf->buf, 0x01, 1);
> why it's related to this patch in particular?
I should move this to another patch.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 6:54 ` Igor Mammedov
@ 2015-04-28 7:46 ` Shannon Zhao
2015-04-28 8:15 ` Igor Mammedov
2015-04-28 8:08 ` Shannon Zhao
1 sibling, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 7:46 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 14:54, Igor Mammedov wrote:
> On Wed, 15 Apr 2015 21:25:02 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add ToUUID macro, this is useful for generating PCIe ACPI table.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/acpi/aml-build.c | 40 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 2 files changed, 41 insertions(+)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index b99bb13..316d5a5 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -25,6 +25,7 @@
>> #include <stdbool.h>
>> #include <string.h>
>> #include "hw/acpi/aml-build.h"
>> +#include "qemu-common.h"
> why do you need this hunk?
>
strtol needs stdlib.h. I should include it directly rather than
including qemu-common.h.
>> #include "qemu/bswap.h"
>> #include "qemu/bitops.h"
>> #include "hw/acpi/bios-linker-loader.h"
>> @@ -948,6 +949,45 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
>> addr_trans, len, flags);
>> }
>>
>> +/*
>> + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
>> + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
>> + * call aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
>> + */
>> +Aml *aml_touuid(const char *uuid)
>> +{
>> + int i;
>> + long int val;
> unsigned long long int ???
>
>
>> + char *end;
>> + const char *start = uuid;
>> + Aml *UUID = aml_buffer();
> s/UUID/var/
>
>> +
>> + val = strtol(start, &end, 16);
> may be use strtoull()
>
>> + g_assert((end - start) == 8);
>> + build_append_int_noprefix(UUID->buf, val, 4);
>> + start = end + 1;
>> + val = strtol(start, &end, 16);
>> + g_assert((end - start) == 4);
>> + build_append_int_noprefix(UUID->buf, val, 2);
>> + start = end + 1;
>> + val = strtol(start, &end, 16);
>> + g_assert((end - start) == 4);
>> + build_append_int_noprefix(UUID->buf, val, 2);
> this corresponds to -gghh- part of UUID according to spec
> it would be better if you add pattern mentioned in spec
> in this function and then put comments marking places
> which handle specific part of it.
>
>> + start = end + 1;
>> + val = strtol(start, &end, 16);
>> + g_assert((end - start) == 4);
>> + build_append_int_noprefix(UUID->buf, (val >> 8) & 0xFF, 1);
>> + build_append_int_noprefix(UUID->buf, val & 0xFF, 1);
> add comment to it that according to spec bytes here are flipped around
> that's why special treatment.
>
>> + start = end + 1;
>> + val = strtol(start, &end, 16);
>> + g_assert((end - start) == 12);
>> + for (i = 40; i >= 0; i -= 8) {
>> + build_append_int_noprefix(UUID->buf, (val >> i) & 0xFF, 1);
>> + }
>> +
> btw:
> whole thing might be simpler if an intermediate conversion is avoided,
> just pack buffer as in spec byte by byte:
>
> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> assert(strlen(uuid) == ...);
> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
> ...
>
> easy to validate just by looking at "UUID Buffer Format" table in spec
>
>> + return UUID;
>> +}
>> +
>> void
>> build_header(GArray *linker, GArray *table_data,
>> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index d1b9fe7..b41fd0c 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -259,6 +259,7 @@ Aml *aml_buffer(void);
>> Aml *aml_resource_template(void);
>> Aml *aml_field(const char *name, AmlFieldFlags flags);
>> Aml *aml_varpackage(uint32_t num_elements);
>> +Aml *aml_touuid(const char *uuid);
>>
>> void
>> build_header(GArray *linker, GArray *table_data,
>
>
> .
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 6:54 ` Igor Mammedov
2015-04-28 7:46 ` Shannon Zhao
@ 2015-04-28 8:08 ` Shannon Zhao
1 sibling, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 8:08 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 14:54, Igor Mammedov wrote:
> btw:
> whole thing might be simpler if an intermediate conversion is avoided,
> just pack buffer as in spec byte by byte:
>
> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> assert(strlen(uuid) == ...);
> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
> ...
use build_append_byte(var->buf, HEX2BYTE(uuid + (3 * 2)); /* dd */ ?
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 7:46 ` Shannon Zhao
@ 2015-04-28 8:15 ` Igor Mammedov
2015-04-28 8:52 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 8:15 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Tue, 28 Apr 2015 15:46:22 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/28 14:54, Igor Mammedov wrote:
> > On Wed, 15 Apr 2015 21:25:02 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>
> >> Add ToUUID macro, this is useful for generating PCIe ACPI table.
> >>
> >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> ---
> >> hw/acpi/aml-build.c | 40 ++++++++++++++++++++++++++++++++++++++++
> >> include/hw/acpi/aml-build.h | 1 +
> >> 2 files changed, 41 insertions(+)
> >>
> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> index b99bb13..316d5a5 100644
> >> --- a/hw/acpi/aml-build.c
> >> +++ b/hw/acpi/aml-build.c
> >> @@ -25,6 +25,7 @@
> >> #include <stdbool.h>
> >> #include <string.h>
> >> #include "hw/acpi/aml-build.h"
> >> +#include "qemu-common.h"
> > why do you need this hunk?
> >
>
> strtol needs stdlib.h. I should include it directly rather than
> including qemu-common.h.
>
> >> #include "qemu/bswap.h"
> >> #include "qemu/bitops.h"
> >> #include "hw/acpi/bios-linker-loader.h"
> >> @@ -948,6 +949,45 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> >> addr_trans, len, flags);
> >> }
> >>
> >> +/*
> >> + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
> >> + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> >> + * call aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> >> + */
> >> +Aml *aml_touuid(const char *uuid)
> >> +{
> >> + int i;
> >> + long int val;
> > unsigned long long int ???
> >
> >
> >> + char *end;
> >> + const char *start = uuid;
> >> + Aml *UUID = aml_buffer();
> > s/UUID/var/
> >
> >> +
> >> + val = strtol(start, &end, 16);
> > may be use strtoull()
> >
> >> + g_assert((end - start) == 8);
> >> + build_append_int_noprefix(UUID->buf, val, 4);
> >> + start = end + 1;
> >> + val = strtol(start, &end, 16);
> >> + g_assert((end - start) == 4);
> >> + build_append_int_noprefix(UUID->buf, val, 2);
> >> + start = end + 1;
> >> + val = strtol(start, &end, 16);
> >> + g_assert((end - start) == 4);
> >> + build_append_int_noprefix(UUID->buf, val, 2);
> > this corresponds to -gghh- part of UUID according to spec
> > it would be better if you add pattern mentioned in spec
> > in this function and then put comments marking places
> > which handle specific part of it.
> >
> >> + start = end + 1;
> >> + val = strtol(start, &end, 16);
> >> + g_assert((end - start) == 4);
> >> + build_append_int_noprefix(UUID->buf, (val >> 8) & 0xFF, 1);
> >> + build_append_int_noprefix(UUID->buf, val & 0xFF, 1);
> > add comment to it that according to spec bytes here are flipped around
> > that's why special treatment.
> >
> >> + start = end + 1;
> >> + val = strtol(start, &end, 16);
> >> + g_assert((end - start) == 12);
> >> + for (i = 40; i >= 0; i -= 8) {
> >> + build_append_int_noprefix(UUID->buf, (val >> i) & 0xFF, 1);
> >> + }
> >> +
> > btw:
> > whole thing might be simpler if an intermediate conversion is avoided,
> > just pack buffer as in spec byte by byte:
> >
> > /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> > assert(strlen(uuid) == ...);
> > build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
>
> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
>
> > build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
>
> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
if you mean hyphens /-/ then they are not encoded,
but you surely can add checks for them to make sure that
UUID format is as expected.
>
> > ...
> >
> > easy to validate just by looking at "UUID Buffer Format" table in spec
> >
> >> + return UUID;
> >> +}
> >> +
> >> void
> >> build_header(GArray *linker, GArray *table_data,
> >> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
> >> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> >> index d1b9fe7..b41fd0c 100644
> >> --- a/include/hw/acpi/aml-build.h
> >> +++ b/include/hw/acpi/aml-build.h
> >> @@ -259,6 +259,7 @@ Aml *aml_buffer(void);
> >> Aml *aml_resource_template(void);
> >> Aml *aml_field(const char *name, AmlFieldFlags flags);
> >> Aml *aml_varpackage(uint32_t num_elements);
> >> +Aml *aml_touuid(const char *uuid);
> >>
> >> void
> >> build_header(GArray *linker, GArray *table_data,
> >
> >
> > .
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
@ 2015-04-28 8:42 ` Igor Mammedov
2015-04-28 8:47 ` Michael S. Tsirkin
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 8:42 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Wed, 15 Apr 2015 21:25:08 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add PCIe controller in ACPI DSDT table, so the guest can detect
> the PCIe.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 152 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 85e8242..ceec405 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -49,6 +49,8 @@
> #include "qapi/qmp/qint.h"
> #include "qom/qom-qobject.h"
> #include "exec/ram_addr.h"
> +#include "hw/pci/pcie_host.h"
> +#include "hw/pci/pci.h"
>
> typedef struct VirtAcpiCpuInfo {
> DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> }
> }
>
> +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
> +{
> + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
> + int i, bus_no;
> + int irq = *info->pcie_irq + 32;
> +
> + Aml *dev = aml_device("%s", "PCI0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> +
> + /* Declare the PCI Routing Table. */
> + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
> + for (i = 0; i < PCI_NUM_PINS; i++) {
> + int gsi = (i + bus_no) % PCI_NUM_PINS;
> + Aml *pkg = aml_package(4);
> + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
> + aml_append(pkg, aml_int(i));
> + aml_append(pkg, aml_name("GSI%d", gsi));
> + aml_append(pkg, aml_int(0));
> + aml_append(rt_pkg, pkg);
> + }
> + }
> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> +
> + /* Create GSI link device */
> + for (i = 0; i < PCI_NUM_PINS; i++) {
> + Aml *dev_gsi = aml_device("GSI%d", i);
> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> + aml_exclusive, aml_not_wake_capable, irq + i));
> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> + aml_exclusive, aml_not_wake_capable, irq + i));
> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> + method = aml_method("_SRS", 1);
> + aml_append(dev_gsi, method);
> + aml_append(dev, dev_gsi);
> + }
> +
> + method = aml_method("_CBA", 0);
> + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
> + aml_append(dev, method);
> +
> + method = aml_method("_CRS", 0);
> + Aml *rbuf = aml_resource_template();
> + aml_append(rbuf,
> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
> + 0x0000, info->nr_pcie_buses));
> + aml_append(rbuf,
> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> + aml_non_cacheable, aml_ReadWrite,
> + 0x0000, info->pcie_mmio.addr,
> + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
> + 0x0000, info->pcie_mmio.size));
> + aml_append(rbuf,
> + aml_dword_io(aml_min_fixed, aml_max_fixed,
> + aml_pos_decode, aml_entire_range,
> + 0x0000, 0x0000, info->pcie_ioport.size - 1,
> + info->pcie_ioport.addr, info->pcie_ioport.size));
> +
> + aml_append(method, aml_name_decl("RBUF", rbuf));
> + aml_append(method, aml_return(rbuf));
> + aml_append(dev, method);
> +
> + /* Declare an _OSC (OS Control Handoff) method */
> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> + method = aml_method("_OSC", 4);
> + aml_append(method,
> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> +
> + /* PCI Firmware Specification 3.0
> + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
> + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
> + * identified by the Universal Unique IDentifier (UUID)
> + * 33db4d5b-1ff7-401c-9657-7441c03dd766
> + */
> + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> + aml_append(ifctx,
> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> + aml_append(ifctx,
> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
> + aml_name("CTRL")));
> +
> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
> + aml_name("CDW1")));
> + aml_append(ifctx, ifctx1);
> +
> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
> + aml_name("CDW1")));
> + aml_append(ifctx, ifctx1);
> +
> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> + aml_append(ifctx, aml_return(aml_arg(3)));
> + aml_append(method, ifctx);
> +
> + elsectx = aml_else();
> + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
> + aml_name("CDW1")));
> + aml_append(elsectx, aml_return(aml_arg(3)));
> + aml_append(method, elsectx);
> + aml_append(dev, method);
> +
> + method = aml_method("_DSM", 4);
> +
> + /* PCI Firmware Specification 3.0
> + * 4.6.1. _DSM for PCI Express Slot Information
> + * The UUID in _DSM in this context is
> + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
> + */
> + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> + buf = aml_buffer();
> + build_append_int_noprefix(buf->buf, 0x01, 1);
pls, do not modify internal buffer of Aml objects outside API,
and do not export build_append_int_noprefix().
Looking at spec _DSM returns bitfield buffer.
for purposes you are using here i.e. set bit 1 to 1 or 0
it's sufficient to use aml_int(1) or aml_int(0) as they are
folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
However if you need to manipulate specific bitfields checkout
CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
Probably that's what you are looking for.
Also aml_buffer() needs to be modified to handle BufferSize
see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
so that space for bitfields could be reserved
/* as workaround/hack one can add several aml_int(0) into it to
reserve needed amount of bytes */
> + aml_append(ifctx1, aml_return(buf));
> + aml_append(ifctx, ifctx1);
> + aml_append(method, ifctx);
> +
> + buf = aml_buffer();
> + build_append_int_noprefix(buf->buf, 0x00, 1);
> + aml_append(method, aml_return(buf));
> + aml_append(dev, method);
> +
> + Aml *dev_rp0 = aml_device("%s", "RP0");
> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, dev_rp0);
> + aml_append(scope, dev);
> +}
> +
> /* RSDP */
> static GArray *
> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> acpi_dsdt_add_flash(scope, info->flash_memmap);
> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> info->virtio_mmio_irq, info->virtio_mmio_num);
> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> +
> aml_append(dsdt, scope);
>
> /* copy AML table into ACPI tables blob and patch header there */
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 8:42 ` Igor Mammedov
@ 2015-04-28 8:47 ` Michael S. Tsirkin
2015-04-28 9:06 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Michael S. Tsirkin @ 2015-04-28 8:47 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, Apr 28, 2015 at 10:42:25AM +0200, Igor Mammedov wrote:
> On Wed, 15 Apr 2015 21:25:08 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > Add PCIe controller in ACPI DSDT table, so the guest can detect
> > the PCIe.
> >
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> > ---
> > hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 152 insertions(+)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index 85e8242..ceec405 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -49,6 +49,8 @@
> > #include "qapi/qmp/qint.h"
> > #include "qom/qom-qobject.h"
> > #include "exec/ram_addr.h"
> > +#include "hw/pci/pcie_host.h"
> > +#include "hw/pci/pci.h"
> >
> > typedef struct VirtAcpiCpuInfo {
> > DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> > @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> > }
> > }
> >
> > +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
> > +{
> > + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
> > + int i, bus_no;
> > + int irq = *info->pcie_irq + 32;
> > +
> > + Aml *dev = aml_device("%s", "PCI0");
> > + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> > + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> > + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> > + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> > + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> > + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> > + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> > +
> > + /* Declare the PCI Routing Table. */
> > + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> > + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
> > + for (i = 0; i < PCI_NUM_PINS; i++) {
> > + int gsi = (i + bus_no) % PCI_NUM_PINS;
> > + Aml *pkg = aml_package(4);
> > + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
> > + aml_append(pkg, aml_int(i));
> > + aml_append(pkg, aml_name("GSI%d", gsi));
> > + aml_append(pkg, aml_int(0));
> > + aml_append(rt_pkg, pkg);
> > + }
> > + }
> > + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> > +
> > + /* Create GSI link device */
> > + for (i = 0; i < PCI_NUM_PINS; i++) {
> > + Aml *dev_gsi = aml_device("GSI%d", i);
> > + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> > + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> > + aml_exclusive, aml_not_wake_capable, irq + i));
> > + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> > + aml_exclusive, aml_not_wake_capable, irq + i));
> > + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> > + method = aml_method("_SRS", 1);
> > + aml_append(dev_gsi, method);
> > + aml_append(dev, dev_gsi);
> > + }
> > +
> > + method = aml_method("_CBA", 0);
> > + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
> > + aml_append(dev, method);
> > +
> > + method = aml_method("_CRS", 0);
> > + Aml *rbuf = aml_resource_template();
> > + aml_append(rbuf,
> > + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> > + 0x0000, 0x0000, info->nr_pcie_buses - 1,
> > + 0x0000, info->nr_pcie_buses));
> > + aml_append(rbuf,
> > + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> > + aml_non_cacheable, aml_ReadWrite,
> > + 0x0000, info->pcie_mmio.addr,
> > + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
> > + 0x0000, info->pcie_mmio.size));
> > + aml_append(rbuf,
> > + aml_dword_io(aml_min_fixed, aml_max_fixed,
> > + aml_pos_decode, aml_entire_range,
> > + 0x0000, 0x0000, info->pcie_ioport.size - 1,
> > + info->pcie_ioport.addr, info->pcie_ioport.size));
> > +
> > + aml_append(method, aml_name_decl("RBUF", rbuf));
> > + aml_append(method, aml_return(rbuf));
> > + aml_append(dev, method);
> > +
> > + /* Declare an _OSC (OS Control Handoff) method */
> > + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> > + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> > + method = aml_method("_OSC", 4);
> > + aml_append(method,
> > + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> > +
> > + /* PCI Firmware Specification 3.0
> > + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
> > + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
> > + * identified by the Universal Unique IDentifier (UUID)
> > + * 33db4d5b-1ff7-401c-9657-7441c03dd766
> > + */
> > + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
> > + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> > + aml_append(ifctx,
> > + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> > + aml_append(ifctx,
> > + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> > + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> > + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> > + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
> > + aml_name("CTRL")));
> > +
> > + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> > + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
> > + aml_name("CDW1")));
> > + aml_append(ifctx, ifctx1);
> > +
> > + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> > + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
> > + aml_name("CDW1")));
> > + aml_append(ifctx, ifctx1);
> > +
> > + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> > + aml_append(ifctx, aml_return(aml_arg(3)));
> > + aml_append(method, ifctx);
> > +
> > + elsectx = aml_else();
> > + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
> > + aml_name("CDW1")));
> > + aml_append(elsectx, aml_return(aml_arg(3)));
> > + aml_append(method, elsectx);
> > + aml_append(dev, method);
> > +
> > + method = aml_method("_DSM", 4);
> > +
> > + /* PCI Firmware Specification 3.0
> > + * 4.6.1. _DSM for PCI Express Slot Information
> > + * The UUID in _DSM in this context is
> > + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
> > + */
> > + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> > + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> > + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> > + buf = aml_buffer();
> > + build_append_int_noprefix(buf->buf, 0x01, 1);
> pls, do not modify internal buffer of Aml objects outside API,
> and do not export build_append_int_noprefix().
>
> Looking at spec _DSM returns bitfield buffer.
> for purposes you are using here i.e. set bit 1 to 1 or 0
> it's sufficient to use aml_int(1) or aml_int(0) as they are
> folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
>
> However if you need to manipulate specific bitfields checkout
> CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
> Probably that's what you are looking for.
>
> Also aml_buffer() needs to be modified to handle BufferSize
> see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
> so that space for bitfields could be reserved
> /* as workaround/hack one can add several aml_int(0) into it to
> reserve needed amount of bytes */
I dislike abusing aml_int like this, makes code hard to follow.
Best just do it properly.
Internally you can call append_byte.
>
> > + aml_append(ifctx1, aml_return(buf));
> > + aml_append(ifctx, ifctx1);
> > + aml_append(method, ifctx);
> > +
> > + buf = aml_buffer();
> > + build_append_int_noprefix(buf->buf, 0x00, 1);
> > + aml_append(method, aml_return(buf));
> > + aml_append(dev, method);
> > +
> > + Aml *dev_rp0 = aml_device("%s", "RP0");
> > + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> > + aml_append(dev, dev_rp0);
> > + aml_append(scope, dev);
> > +}
> > +
> > /* RSDP */
> > static GArray *
> > build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> > @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> > acpi_dsdt_add_flash(scope, info->flash_memmap);
> > acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> > info->virtio_mmio_irq, info->virtio_mmio_num);
> > + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> > +
> > aml_append(dsdt, scope);
> >
> > /* copy AML table into ACPI tables blob and patch header there */
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 8:15 ` Igor Mammedov
@ 2015-04-28 8:52 ` Shannon Zhao
2015-04-28 9:35 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 8:52 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 16:15, Igor Mammedov wrote:
>>> btw:
>>> > > whole thing might be simpler if an intermediate conversion is avoided,
>>> > > just pack buffer as in spec byte by byte:
>>> > >
>>> > > /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
>>> > > assert(strlen(uuid) == ...);
>>> > > build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
>> >
>> > use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
>> >
>>> > > build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
>> >
>> > use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
> if you mean hyphens /-/ then they are not encoded,
> but you surely can add checks for them to make sure that
> UUID format is as expected.
>
I mean uuid[3] points to b not dd. Maybe use following way:
static uint8_t Hex2Byte(char *src)
{
int hi = Hex2Digit(*src++);
int lo = Hex2Digit(*src);
if ((hi < 0) || (lo < 0))
return -1;
return (hi << 4) | lo;
}
g_assert((strlen(uuid) == 36) && (uuid[8] == '-') && (uuid[13] == '-')
&& (uuid[18] == '-') && (uuid[23] == '-'));
build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
build_append_byte(var->buf, Hex2Byte(uuid + (2 * 2))); /* cc */
build_append_byte(var->buf, Hex2Byte(uuid + (1 * 2))); /* bb */
build_append_byte(var->buf, Hex2Byte(uuid + (0 * 2))); /* aa */
build_append_byte(var->buf, Hex2Byte(uuid + (5 * 2 + 1))); /* ff */
build_append_byte(var->buf, Hex2Byte(uuid + (4 * 2 + 1))); /* ee */
build_append_byte(var->buf, Hex2Byte(uuid + (7 * 2 + 2))); /* hh */
build_append_byte(var->buf, Hex2Byte(uuid + (6 * 2 + 2))); /* gg */
build_append_byte(var->buf, Hex2Byte(uuid + (8 * 2 + 3))); /* ii */
build_append_byte(var->buf, Hex2Byte(uuid + (9 * 2 + 3))); /* jj */
build_append_byte(var->buf, Hex2Byte(uuid + (10 * 2 + 4))); /* kk */
build_append_byte(var->buf, Hex2Byte(uuid + (11 * 2 + 4))); /* ll */
build_append_byte(var->buf, Hex2Byte(uuid + (12 * 2 + 4))); /* mm */
build_append_byte(var->buf, Hex2Byte(uuid + (13 * 2 + 4))); /* nn */
build_append_byte(var->buf, Hex2Byte(uuid + (14 * 2 + 4))); /* oo */
build_append_byte(var->buf, Hex2Byte(uuid + (15 * 2 + 4))); /* pp */
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 8:47 ` Michael S. Tsirkin
@ 2015-04-28 9:06 ` Shannon Zhao
2015-04-28 9:54 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 9:06 UTC (permalink / raw)
To: Michael S. Tsirkin, Igor Mammedov
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 16:47, Michael S. Tsirkin wrote:
> On Tue, Apr 28, 2015 at 10:42:25AM +0200, Igor Mammedov wrote:
>> On Wed, 15 Apr 2015 21:25:08 +0800
>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> Add PCIe controller in ACPI DSDT table, so the guest can detect
>>> the PCIe.
>>>
>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> ---
>>> hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 152 insertions(+)
>>>
>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>> index 85e8242..ceec405 100644
>>> --- a/hw/arm/virt-acpi-build.c
>>> +++ b/hw/arm/virt-acpi-build.c
>>> @@ -49,6 +49,8 @@
>>> #include "qapi/qmp/qint.h"
>>> #include "qom/qom-qobject.h"
>>> #include "exec/ram_addr.h"
>>> +#include "hw/pci/pcie_host.h"
>>> +#include "hw/pci/pci.h"
>>>
>>> typedef struct VirtAcpiCpuInfo {
>>> DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
>>> @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
>>> }
>>> }
>>>
>>> +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
>>> +{
>>> + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
>>> + int i, bus_no;
>>> + int irq = *info->pcie_irq + 32;
>>> +
>>> + Aml *dev = aml_device("%s", "PCI0");
>>> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
>>> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
>>> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
>>> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
>>> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
>>> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
>>> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
>>> +
>>> + /* Declare the PCI Routing Table. */
>>> + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
>>> + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>>> + int gsi = (i + bus_no) % PCI_NUM_PINS;
>>> + Aml *pkg = aml_package(4);
>>> + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
>>> + aml_append(pkg, aml_int(i));
>>> + aml_append(pkg, aml_name("GSI%d", gsi));
>>> + aml_append(pkg, aml_int(0));
>>> + aml_append(rt_pkg, pkg);
>>> + }
>>> + }
>>> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
>>> +
>>> + /* Create GSI link device */
>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>>> + Aml *dev_gsi = aml_device("GSI%d", i);
>>> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
>>> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
>>> + crs = aml_resource_template();
>>> + aml_append(crs,
>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>>> + aml_exclusive, aml_not_wake_capable, irq + i));
>>> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
>>> + crs = aml_resource_template();
>>> + aml_append(crs,
>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>>> + aml_exclusive, aml_not_wake_capable, irq + i));
>>> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
>>> + method = aml_method("_SRS", 1);
>>> + aml_append(dev_gsi, method);
>>> + aml_append(dev, dev_gsi);
>>> + }
>>> +
>>> + method = aml_method("_CBA", 0);
>>> + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
>>> + aml_append(dev, method);
>>> +
>>> + method = aml_method("_CRS", 0);
>>> + Aml *rbuf = aml_resource_template();
>>> + aml_append(rbuf,
>>> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
>>> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
>>> + 0x0000, info->nr_pcie_buses));
>>> + aml_append(rbuf,
>>> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
>>> + aml_non_cacheable, aml_ReadWrite,
>>> + 0x0000, info->pcie_mmio.addr,
>>> + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
>>> + 0x0000, info->pcie_mmio.size));
>>> + aml_append(rbuf,
>>> + aml_dword_io(aml_min_fixed, aml_max_fixed,
>>> + aml_pos_decode, aml_entire_range,
>>> + 0x0000, 0x0000, info->pcie_ioport.size - 1,
>>> + info->pcie_ioport.addr, info->pcie_ioport.size));
>>> +
>>> + aml_append(method, aml_name_decl("RBUF", rbuf));
>>> + aml_append(method, aml_return(rbuf));
>>> + aml_append(dev, method);
>>> +
>>> + /* Declare an _OSC (OS Control Handoff) method */
>>> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
>>> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
>>> + method = aml_method("_OSC", 4);
>>> + aml_append(method,
>>> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
>>> +
>>> + /* PCI Firmware Specification 3.0
>>> + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
>>> + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
>>> + * identified by the Universal Unique IDentifier (UUID)
>>> + * 33db4d5b-1ff7-401c-9657-7441c03dd766
>>> + */
>>> + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>>> + aml_append(ifctx,
>>> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
>>> + aml_append(ifctx,
>>> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
>>> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
>>> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
>>> + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
>>> + aml_name("CTRL")));
>>> +
>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
>>> + aml_name("CDW1")));
>>> + aml_append(ifctx, ifctx1);
>>> +
>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
>>> + aml_name("CDW1")));
>>> + aml_append(ifctx, ifctx1);
>>> +
>>> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
>>> + aml_append(ifctx, aml_return(aml_arg(3)));
>>> + aml_append(method, ifctx);
>>> +
>>> + elsectx = aml_else();
>>> + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
>>> + aml_name("CDW1")));
>>> + aml_append(elsectx, aml_return(aml_arg(3)));
>>> + aml_append(method, elsectx);
>>> + aml_append(dev, method);
>>> +
>>> + method = aml_method("_DSM", 4);
>>> +
>>> + /* PCI Firmware Specification 3.0
>>> + * 4.6.1. _DSM for PCI Express Slot Information
>>> + * The UUID in _DSM in this context is
>>> + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
>>> + */
>>> + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>>> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
>>> + buf = aml_buffer();
>>> + build_append_int_noprefix(buf->buf, 0x01, 1);
>> pls, do not modify internal buffer of Aml objects outside API,
>> and do not export build_append_int_noprefix().
>>
>> Looking at spec _DSM returns bitfield buffer.
>> for purposes you are using here i.e. set bit 1 to 1 or 0
>> it's sufficient to use aml_int(1) or aml_int(0) as they are
>> folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
>>
>> However if you need to manipulate specific bitfields checkout
>> CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
>> Probably that's what you are looking for.
>>
>> Also aml_buffer() needs to be modified to handle BufferSize
>> see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
>> so that space for bitfields could be reserved
>> /* as workaround/hack one can add several aml_int(0) into it to
>> reserve needed amount of bytes */
>
> I dislike abusing aml_int like this, makes code hard to follow.
> Best just do it properly.
> Internally you can call append_byte.
>
I agree we could use append_byte to reserve BufferSize of bytes.
But we still need a function to initialize the buffer. A new function
wraps build_append_int_noprefix()?
>>
>>> + aml_append(ifctx1, aml_return(buf));
>>> + aml_append(ifctx, ifctx1);
>>> + aml_append(method, ifctx);
>>> +
>>> + buf = aml_buffer();
>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
>>> + aml_append(method, aml_return(buf));
>>> + aml_append(dev, method);
>>> +
>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
>>> + aml_append(dev, dev_rp0);
>>> + aml_append(scope, dev);
>>> +}
>>> +
>>> /* RSDP */
>>> static GArray *
>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
>>> info->virtio_mmio_irq, info->virtio_mmio_num);
>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>>> +
>>> aml_append(dsdt, scope);
>>>
>>> /* copy AML table into ACPI tables blob and patch header there */
>
> .
>
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 8:52 ` Shannon Zhao
@ 2015-04-28 9:35 ` Igor Mammedov
2015-04-28 9:48 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 9:35 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Tue, 28 Apr 2015 16:52:19 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/28 16:15, Igor Mammedov wrote:
> >>> btw:
> >>> > > whole thing might be simpler if an intermediate conversion is avoided,
> >>> > > just pack buffer as in spec byte by byte:
> >>> > >
> >>> > > /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> >>> > > assert(strlen(uuid) == ...);
> >>> > > build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
> >> >
> >> > use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
> >> >
> >>> > > build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
> >> >
> >> > use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
> > if you mean hyphens /-/ then they are not encoded,
> > but you surely can add checks for them to make sure that
> > UUID format is as expected.
> >
>
> I mean uuid[3] points to b not dd. Maybe use following way:
>
> static uint8_t Hex2Byte(char *src)
or even better:
Hex2Byte(char *src, byte_idx)
and do pointer arithmetic inside
[...]
> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
...
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 9:35 ` Igor Mammedov
@ 2015-04-28 9:48 ` Shannon Zhao
2015-04-29 13:41 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 9:48 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 17:35, Igor Mammedov wrote:
> On Tue, 28 Apr 2015 16:52:19 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> On 2015/4/28 16:15, Igor Mammedov wrote:
>>>>> btw:
>>>>>>> whole thing might be simpler if an intermediate conversion is avoided,
>>>>>>> just pack buffer as in spec byte by byte:
>>>>>>>
>>>>>>> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
>>>>>>> assert(strlen(uuid) == ...);
>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
>>>>>
>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
>>>>>
>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
>>>>>
>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
>>> if you mean hyphens /-/ then they are not encoded,
>>> but you surely can add checks for them to make sure that
>>> UUID format is as expected.
>>>
>>
>> I mean uuid[3] points to b not dd. Maybe use following way:
>>
>> static uint8_t Hex2Byte(char *src)
> or even better:
> Hex2Byte(char *src, byte_idx)
> and do pointer arithmetic inside
>
> [...]
>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
> build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
> build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
> ...
>
Yes, it's better to first four bytes. But there are hyphens /-/, for
offset 04, 05 and etc it doesn't work. We can't use following expression:
build_append_byte(var->buf, Hex2Byte(uuid, 5)); /* ff - at offset 04 */
build_append_byte(var->buf, Hex2Byte(uuid, 4)); /* ee - at offset 05 */
...
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 9:06 ` Shannon Zhao
@ 2015-04-28 9:54 ` Igor Mammedov
2015-04-28 12:57 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 9:54 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, 28 Apr 2015 17:06:00 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/28 16:47, Michael S. Tsirkin wrote:
> > On Tue, Apr 28, 2015 at 10:42:25AM +0200, Igor Mammedov wrote:
> >> On Wed, 15 Apr 2015 21:25:08 +0800
> >> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >>
> >>> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>>
> >>> Add PCIe controller in ACPI DSDT table, so the guest can detect
> >>> the PCIe.
> >>>
> >>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >>> ---
> >>> hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 152 insertions(+)
> >>>
> >>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> >>> index 85e8242..ceec405 100644
> >>> --- a/hw/arm/virt-acpi-build.c
> >>> +++ b/hw/arm/virt-acpi-build.c
> >>> @@ -49,6 +49,8 @@
> >>> #include "qapi/qmp/qint.h"
> >>> #include "qom/qom-qobject.h"
> >>> #include "exec/ram_addr.h"
> >>> +#include "hw/pci/pcie_host.h"
> >>> +#include "hw/pci/pci.h"
> >>>
> >>> typedef struct VirtAcpiCpuInfo {
> >>> DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> >>> @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> >>> }
> >>> }
> >>>
> >>> +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
> >>> +{
> >>> + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
> >>> + int i, bus_no;
> >>> + int irq = *info->pcie_irq + 32;
> >>> +
> >>> + Aml *dev = aml_device("%s", "PCI0");
> >>> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> >>> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> >>> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> >>> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> >>> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> >>> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> >>> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> >>> +
> >>> + /* Declare the PCI Routing Table. */
> >>> + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> >>> + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
> >>> + for (i = 0; i < PCI_NUM_PINS; i++) {
> >>> + int gsi = (i + bus_no) % PCI_NUM_PINS;
> >>> + Aml *pkg = aml_package(4);
> >>> + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
> >>> + aml_append(pkg, aml_int(i));
> >>> + aml_append(pkg, aml_name("GSI%d", gsi));
> >>> + aml_append(pkg, aml_int(0));
> >>> + aml_append(rt_pkg, pkg);
> >>> + }
> >>> + }
> >>> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> >>> +
> >>> + /* Create GSI link device */
> >>> + for (i = 0; i < PCI_NUM_PINS; i++) {
> >>> + Aml *dev_gsi = aml_device("GSI%d", i);
> >>> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> >>> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> >>> + crs = aml_resource_template();
> >>> + aml_append(crs,
> >>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> >>> + aml_exclusive, aml_not_wake_capable, irq + i));
> >>> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> >>> + crs = aml_resource_template();
> >>> + aml_append(crs,
> >>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> >>> + aml_exclusive, aml_not_wake_capable, irq + i));
> >>> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> >>> + method = aml_method("_SRS", 1);
> >>> + aml_append(dev_gsi, method);
> >>> + aml_append(dev, dev_gsi);
> >>> + }
> >>> +
> >>> + method = aml_method("_CBA", 0);
> >>> + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
> >>> + aml_append(dev, method);
> >>> +
> >>> + method = aml_method("_CRS", 0);
> >>> + Aml *rbuf = aml_resource_template();
> >>> + aml_append(rbuf,
> >>> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> >>> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
> >>> + 0x0000, info->nr_pcie_buses));
> >>> + aml_append(rbuf,
> >>> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> >>> + aml_non_cacheable, aml_ReadWrite,
> >>> + 0x0000, info->pcie_mmio.addr,
> >>> + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
> >>> + 0x0000, info->pcie_mmio.size));
> >>> + aml_append(rbuf,
> >>> + aml_dword_io(aml_min_fixed, aml_max_fixed,
> >>> + aml_pos_decode, aml_entire_range,
> >>> + 0x0000, 0x0000, info->pcie_ioport.size - 1,
> >>> + info->pcie_ioport.addr, info->pcie_ioport.size));
> >>> +
> >>> + aml_append(method, aml_name_decl("RBUF", rbuf));
> >>> + aml_append(method, aml_return(rbuf));
> >>> + aml_append(dev, method);
> >>> +
> >>> + /* Declare an _OSC (OS Control Handoff) method */
> >>> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> >>> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> >>> + method = aml_method("_OSC", 4);
> >>> + aml_append(method,
> >>> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> >>> +
> >>> + /* PCI Firmware Specification 3.0
> >>> + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
> >>> + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
> >>> + * identified by the Universal Unique IDentifier (UUID)
> >>> + * 33db4d5b-1ff7-401c-9657-7441c03dd766
> >>> + */
> >>> + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
> >>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> >>> + aml_append(ifctx,
> >>> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> >>> + aml_append(ifctx,
> >>> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> >>> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> >>> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> >>> + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
> >>> + aml_name("CTRL")));
> >>> +
> >>> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> >>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
> >>> + aml_name("CDW1")));
> >>> + aml_append(ifctx, ifctx1);
> >>> +
> >>> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> >>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
> >>> + aml_name("CDW1")));
> >>> + aml_append(ifctx, ifctx1);
> >>> +
> >>> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> >>> + aml_append(ifctx, aml_return(aml_arg(3)));
> >>> + aml_append(method, ifctx);
> >>> +
> >>> + elsectx = aml_else();
> >>> + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
> >>> + aml_name("CDW1")));
> >>> + aml_append(elsectx, aml_return(aml_arg(3)));
> >>> + aml_append(method, elsectx);
> >>> + aml_append(dev, method);
> >>> +
> >>> + method = aml_method("_DSM", 4);
> >>> +
> >>> + /* PCI Firmware Specification 3.0
> >>> + * 4.6.1. _DSM for PCI Express Slot Information
> >>> + * The UUID in _DSM in this context is
> >>> + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
> >>> + */
> >>> + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> >>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> >>> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> >>> + buf = aml_buffer();
> >>> + build_append_int_noprefix(buf->buf, 0x01, 1);
> >> pls, do not modify internal buffer of Aml objects outside API,
> >> and do not export build_append_int_noprefix().
> >>
> >> Looking at spec _DSM returns bitfield buffer.
> >> for purposes you are using here i.e. set bit 1 to 1 or 0
> >> it's sufficient to use aml_int(1) or aml_int(0) as they are
> >> folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
> >>
> >> However if you need to manipulate specific bitfields checkout
> >> CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
> >> Probably that's what you are looking for.
> >>
> >> Also aml_buffer() needs to be modified to handle BufferSize
> >> see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
> >> so that space for bitfields could be reserved
> >> /* as workaround/hack one can add several aml_int(0) into it to
> >> reserve needed amount of bytes */
> >
> > I dislike abusing aml_int like this, makes code hard to follow.
> > Best just do it properly.
> > Internally you can call append_byte.
> >
>
> I agree we could use append_byte to reserve BufferSize of bytes.
> But we still need a function to initialize the buffer. A new function
> wraps build_append_int_noprefix()?
just extend aml_buffer(BufferSize) and then use any appropriate
internal functions inside API.
Outside you'll call:
buf = aml_buffer(1);
aml_append(method, aml_name_decl("RET", buf);
aml_createbitfield("RET", 0, "FNEN"/* non 0 functions supported */);
...
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
...
/* create bit field for every supported function if supported */
...
aml_append(method, aml_return(aml_name("RET")));
>
> >>
> >>> + aml_append(ifctx1, aml_return(buf));
> >>> + aml_append(ifctx, ifctx1);
> >>> + aml_append(method, ifctx);
> >>> +
> >>> + buf = aml_buffer();
> >>> + build_append_int_noprefix(buf->buf, 0x00, 1);
> >>> + aml_append(method, aml_return(buf));
> >>> + aml_append(dev, method);
> >>> +
> >>> + Aml *dev_rp0 = aml_device("%s", "RP0");
> >>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> >>> + aml_append(dev, dev_rp0);
> >>> + aml_append(scope, dev);
> >>> +}
> >>> +
> >>> /* RSDP */
> >>> static GArray *
> >>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> >>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> >>> acpi_dsdt_add_flash(scope, info->flash_memmap);
> >>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> >>> info->virtio_mmio_irq, info->virtio_mmio_num);
> >>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> >>> +
> >>> aml_append(dsdt, scope);
> >>>
> >>> /* copy AML table into ACPI tables blob and patch header there */
> >
> > .
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 9:54 ` Igor Mammedov
@ 2015-04-28 12:57 ` Shannon Zhao
2015-04-28 15:13 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-28 12:57 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/28 17:54, Igor Mammedov wrote:
> On Tue, 28 Apr 2015 17:06:00 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> On 2015/4/28 16:47, Michael S. Tsirkin wrote:
>>> On Tue, Apr 28, 2015 at 10:42:25AM +0200, Igor Mammedov wrote:
>>>> On Wed, 15 Apr 2015 21:25:08 +0800
>>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>>>
>>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>>
>>>>> Add PCIe controller in ACPI DSDT table, so the guest can detect
>>>>> the PCIe.
>>>>>
>>>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>>> ---
>>>>> hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
>>>>> 1 file changed, 152 insertions(+)
>>>>>
>>>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>>>> index 85e8242..ceec405 100644
>>>>> --- a/hw/arm/virt-acpi-build.c
>>>>> +++ b/hw/arm/virt-acpi-build.c
>>>>> @@ -49,6 +49,8 @@
>>>>> #include "qapi/qmp/qint.h"
>>>>> #include "qom/qom-qobject.h"
>>>>> #include "exec/ram_addr.h"
>>>>> +#include "hw/pci/pcie_host.h"
>>>>> +#include "hw/pci/pci.h"
>>>>>
>>>>> typedef struct VirtAcpiCpuInfo {
>>>>> DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
>>>>> @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
>>>>> }
>>>>> }
>>>>>
>>>>> +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
>>>>> +{
>>>>> + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
>>>>> + int i, bus_no;
>>>>> + int irq = *info->pcie_irq + 32;
>>>>> +
>>>>> + Aml *dev = aml_device("%s", "PCI0");
>>>>> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
>>>>> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
>>>>> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
>>>>> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
>>>>> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
>>>>> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
>>>>> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
>>>>> +
>>>>> + /* Declare the PCI Routing Table. */
>>>>> + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
>>>>> + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
>>>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>>>>> + int gsi = (i + bus_no) % PCI_NUM_PINS;
>>>>> + Aml *pkg = aml_package(4);
>>>>> + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
>>>>> + aml_append(pkg, aml_int(i));
>>>>> + aml_append(pkg, aml_name("GSI%d", gsi));
>>>>> + aml_append(pkg, aml_int(0));
>>>>> + aml_append(rt_pkg, pkg);
>>>>> + }
>>>>> + }
>>>>> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
>>>>> +
>>>>> + /* Create GSI link device */
>>>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>>>>> + Aml *dev_gsi = aml_device("GSI%d", i);
>>>>> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
>>>>> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
>>>>> + crs = aml_resource_template();
>>>>> + aml_append(crs,
>>>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>>>>> + aml_exclusive, aml_not_wake_capable, irq + i));
>>>>> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
>>>>> + crs = aml_resource_template();
>>>>> + aml_append(crs,
>>>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>>>>> + aml_exclusive, aml_not_wake_capable, irq + i));
>>>>> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
>>>>> + method = aml_method("_SRS", 1);
>>>>> + aml_append(dev_gsi, method);
>>>>> + aml_append(dev, dev_gsi);
>>>>> + }
>>>>> +
>>>>> + method = aml_method("_CBA", 0);
>>>>> + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
>>>>> + aml_append(dev, method);
>>>>> +
>>>>> + method = aml_method("_CRS", 0);
>>>>> + Aml *rbuf = aml_resource_template();
>>>>> + aml_append(rbuf,
>>>>> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
>>>>> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
>>>>> + 0x0000, info->nr_pcie_buses));
>>>>> + aml_append(rbuf,
>>>>> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
>>>>> + aml_non_cacheable, aml_ReadWrite,
>>>>> + 0x0000, info->pcie_mmio.addr,
>>>>> + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
>>>>> + 0x0000, info->pcie_mmio.size));
>>>>> + aml_append(rbuf,
>>>>> + aml_dword_io(aml_min_fixed, aml_max_fixed,
>>>>> + aml_pos_decode, aml_entire_range,
>>>>> + 0x0000, 0x0000, info->pcie_ioport.size - 1,
>>>>> + info->pcie_ioport.addr, info->pcie_ioport.size));
>>>>> +
>>>>> + aml_append(method, aml_name_decl("RBUF", rbuf));
>>>>> + aml_append(method, aml_return(rbuf));
>>>>> + aml_append(dev, method);
>>>>> +
>>>>> + /* Declare an _OSC (OS Control Handoff) method */
>>>>> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
>>>>> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
>>>>> + method = aml_method("_OSC", 4);
>>>>> + aml_append(method,
>>>>> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
>>>>> +
>>>>> + /* PCI Firmware Specification 3.0
>>>>> + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
>>>>> + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
>>>>> + * identified by the Universal Unique IDentifier (UUID)
>>>>> + * 33db4d5b-1ff7-401c-9657-7441c03dd766
>>>>> + */
>>>>> + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
>>>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>>>>> + aml_append(ifctx,
>>>>> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
>>>>> + aml_append(ifctx,
>>>>> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
>>>>> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
>>>>> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
>>>>> + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
>>>>> + aml_name("CTRL")));
>>>>> +
>>>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
>>>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
>>>>> + aml_name("CDW1")));
>>>>> + aml_append(ifctx, ifctx1);
>>>>> +
>>>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
>>>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
>>>>> + aml_name("CDW1")));
>>>>> + aml_append(ifctx, ifctx1);
>>>>> +
>>>>> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
>>>>> + aml_append(ifctx, aml_return(aml_arg(3)));
>>>>> + aml_append(method, ifctx);
>>>>> +
>>>>> + elsectx = aml_else();
>>>>> + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
>>>>> + aml_name("CDW1")));
>>>>> + aml_append(elsectx, aml_return(aml_arg(3)));
>>>>> + aml_append(method, elsectx);
>>>>> + aml_append(dev, method);
>>>>> +
>>>>> + method = aml_method("_DSM", 4);
>>>>> +
>>>>> + /* PCI Firmware Specification 3.0
>>>>> + * 4.6.1. _DSM for PCI Express Slot Information
>>>>> + * The UUID in _DSM in this context is
>>>>> + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
>>>>> + */
>>>>> + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
>>>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>>>>> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
>>>>> + buf = aml_buffer();
>>>>> + build_append_int_noprefix(buf->buf, 0x01, 1);
>>>> pls, do not modify internal buffer of Aml objects outside API,
>>>> and do not export build_append_int_noprefix().
>>>>
>>>> Looking at spec _DSM returns bitfield buffer.
>>>> for purposes you are using here i.e. set bit 1 to 1 or 0
>>>> it's sufficient to use aml_int(1) or aml_int(0) as they are
>>>> folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
>>>>
>>>> However if you need to manipulate specific bitfields checkout
>>>> CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
>>>> Probably that's what you are looking for.
>>>>
>>>> Also aml_buffer() needs to be modified to handle BufferSize
>>>> see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
>>>> so that space for bitfields could be reserved
>>>> /* as workaround/hack one can add several aml_int(0) into it to
>>>> reserve needed amount of bytes */
>>>
>>> I dislike abusing aml_int like this, makes code hard to follow.
>>> Best just do it properly.
>>> Internally you can call append_byte.
>>>
>>
>> I agree we could use append_byte to reserve BufferSize of bytes.
>> But we still need a function to initialize the buffer. A new function
>> wraps build_append_int_noprefix()?
> just extend aml_buffer(BufferSize) and then use any appropriate
> internal functions inside API.
>
> Outside you'll call:
>
> buf = aml_buffer(1);
> aml_append(method, aml_name_decl("RET", buf);
> aml_createbitfield("RET", 0, "FNEN"/* non 0 functions supported */);
> ...
Here I need to set the value of buffer to 1 or 0, we could
createbitfield, but if we want to set the value to non one or zero and
the BufferSize is large, how could we do? CreateByteField? It's a little
complex for user.
> ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
> ...
> /* create bit field for every supported function if supported */
> ...
> aml_append(method, aml_return(aml_name("RET")));
>
>
>>
>>>>
>>>>> + aml_append(ifctx1, aml_return(buf));
>>>>> + aml_append(ifctx, ifctx1);
>>>>> + aml_append(method, ifctx);
>>>>> +
>>>>> + buf = aml_buffer();
>>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
>>>>> + aml_append(method, aml_return(buf));
>>>>> + aml_append(dev, method);
>>>>> +
>>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
>>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
>>>>> + aml_append(dev, dev_rp0);
>>>>> + aml_append(scope, dev);
>>>>> +}
>>>>> +
>>>>> /* RSDP */
>>>>> static GArray *
>>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
>>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
>>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
>>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
>>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>>>>> +
>>>>> aml_append(dsdt, scope);
>>>>>
>>>>> /* copy AML table into ACPI tables blob and patch header there */
>>>
>>> .
>>>
>>
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 12:57 ` Shannon Zhao
@ 2015-04-28 15:13 ` Igor Mammedov
2015-04-28 15:54 ` Michael S. Tsirkin
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-28 15:13 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, 28 Apr 2015 20:57:25 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/28 17:54, Igor Mammedov wrote:
> > On Tue, 28 Apr 2015 17:06:00 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> On 2015/4/28 16:47, Michael S. Tsirkin wrote:
> >>> On Tue, Apr 28, 2015 at 10:42:25AM +0200, Igor Mammedov wrote:
> >>>> On Wed, 15 Apr 2015 21:25:08 +0800
> >>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >>>>
> >>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>>>>
> >>>>> Add PCIe controller in ACPI DSDT table, so the guest can detect
> >>>>> the PCIe.
> >>>>>
> >>>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >>>>> ---
> >>>>> hw/arm/virt-acpi-build.c | 152 +++++++++++++++++++++++++++++++++++++++++++++++
> >>>>> 1 file changed, 152 insertions(+)
> >>>>>
> >>>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> >>>>> index 85e8242..ceec405 100644
> >>>>> --- a/hw/arm/virt-acpi-build.c
> >>>>> +++ b/hw/arm/virt-acpi-build.c
> >>>>> @@ -49,6 +49,8 @@
> >>>>> #include "qapi/qmp/qint.h"
> >>>>> #include "qom/qom-qobject.h"
> >>>>> #include "exec/ram_addr.h"
> >>>>> +#include "hw/pci/pcie_host.h"
> >>>>> +#include "hw/pci/pci.h"
> >>>>>
> >>>>> typedef struct VirtAcpiCpuInfo {
> >>>>> DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> >>>>> @@ -160,6 +162,154 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> >>>>> }
> >>>>> }
> >>>>>
> >>>>> +static void acpi_dsdt_add_pci(Aml *scope, AcpiPcieInfo *info)
> >>>>> +{
> >>>>> + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
> >>>>> + int i, bus_no;
> >>>>> + int irq = *info->pcie_irq + 32;
> >>>>> +
> >>>>> + Aml *dev = aml_device("%s", "PCI0");
> >>>>> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> >>>>> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> >>>>> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> >>>>> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> >>>>> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> >>>>> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> >>>>> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> >>>>> +
> >>>>> + /* Declare the PCI Routing Table. */
> >>>>> + Aml *rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> >>>>> + for (bus_no = 0; bus_no < info->nr_pcie_buses; bus_no++) {
> >>>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
> >>>>> + int gsi = (i + bus_no) % PCI_NUM_PINS;
> >>>>> + Aml *pkg = aml_package(4);
> >>>>> + aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
> >>>>> + aml_append(pkg, aml_int(i));
> >>>>> + aml_append(pkg, aml_name("GSI%d", gsi));
> >>>>> + aml_append(pkg, aml_int(0));
> >>>>> + aml_append(rt_pkg, pkg);
> >>>>> + }
> >>>>> + }
> >>>>> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> >>>>> +
> >>>>> + /* Create GSI link device */
> >>>>> + for (i = 0; i < PCI_NUM_PINS; i++) {
> >>>>> + Aml *dev_gsi = aml_device("GSI%d", i);
> >>>>> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> >>>>> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> >>>>> + crs = aml_resource_template();
> >>>>> + aml_append(crs,
> >>>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> >>>>> + aml_exclusive, aml_not_wake_capable, irq + i));
> >>>>> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> >>>>> + crs = aml_resource_template();
> >>>>> + aml_append(crs,
> >>>>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> >>>>> + aml_exclusive, aml_not_wake_capable, irq + i));
> >>>>> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> >>>>> + method = aml_method("_SRS", 1);
> >>>>> + aml_append(dev_gsi, method);
> >>>>> + aml_append(dev, dev_gsi);
> >>>>> + }
> >>>>> +
> >>>>> + method = aml_method("_CBA", 0);
> >>>>> + aml_append(method, aml_return(aml_int(info->pcie_ecam.addr)));
> >>>>> + aml_append(dev, method);
> >>>>> +
> >>>>> + method = aml_method("_CRS", 0);
> >>>>> + Aml *rbuf = aml_resource_template();
> >>>>> + aml_append(rbuf,
> >>>>> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> >>>>> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
> >>>>> + 0x0000, info->nr_pcie_buses));
> >>>>> + aml_append(rbuf,
> >>>>> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> >>>>> + aml_non_cacheable, aml_ReadWrite,
> >>>>> + 0x0000, info->pcie_mmio.addr,
> >>>>> + info->pcie_mmio.addr + info->pcie_mmio.size - 1,
> >>>>> + 0x0000, info->pcie_mmio.size));
> >>>>> + aml_append(rbuf,
> >>>>> + aml_dword_io(aml_min_fixed, aml_max_fixed,
> >>>>> + aml_pos_decode, aml_entire_range,
> >>>>> + 0x0000, 0x0000, info->pcie_ioport.size - 1,
> >>>>> + info->pcie_ioport.addr, info->pcie_ioport.size));
> >>>>> +
> >>>>> + aml_append(method, aml_name_decl("RBUF", rbuf));
> >>>>> + aml_append(method, aml_return(rbuf));
> >>>>> + aml_append(dev, method);
> >>>>> +
> >>>>> + /* Declare an _OSC (OS Control Handoff) method */
> >>>>> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> >>>>> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> >>>>> + method = aml_method("_OSC", 4);
> >>>>> + aml_append(method,
> >>>>> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> >>>>> +
> >>>>> + /* PCI Firmware Specification 3.0
> >>>>> + * 4.5.1. _OSC Interface for PCI Host Bridge Devices
> >>>>> + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
> >>>>> + * identified by the Universal Unique IDentifier (UUID)
> >>>>> + * 33db4d5b-1ff7-401c-9657-7441c03dd766
> >>>>> + */
> >>>>> + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
> >>>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> >>>>> + aml_append(ifctx,
> >>>>> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> >>>>> + aml_append(ifctx,
> >>>>> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> >>>>> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> >>>>> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> >>>>> + aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
> >>>>> + aml_name("CTRL")));
> >>>>> +
> >>>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> >>>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
> >>>>> + aml_name("CDW1")));
> >>>>> + aml_append(ifctx, ifctx1);
> >>>>> +
> >>>>> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> >>>>> + aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
> >>>>> + aml_name("CDW1")));
> >>>>> + aml_append(ifctx, ifctx1);
> >>>>> +
> >>>>> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> >>>>> + aml_append(ifctx, aml_return(aml_arg(3)));
> >>>>> + aml_append(method, ifctx);
> >>>>> +
> >>>>> + elsectx = aml_else();
> >>>>> + aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
> >>>>> + aml_name("CDW1")));
> >>>>> + aml_append(elsectx, aml_return(aml_arg(3)));
> >>>>> + aml_append(method, elsectx);
> >>>>> + aml_append(dev, method);
> >>>>> +
> >>>>> + method = aml_method("_DSM", 4);
> >>>>> +
> >>>>> + /* PCI Firmware Specification 3.0
> >>>>> + * 4.6.1. _DSM for PCI Express Slot Information
> >>>>> + * The UUID in _DSM in this context is
> >>>>> + * {E5C937D0-3553-4d7a-9117-EA4D19C3434D}
> >>>>> + */
> >>>>> + UUID = aml_touuid("E5C937D0-3553-4d7a-9117-EA4D19C3434D");
> >>>>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> >>>>> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> >>>>> + buf = aml_buffer();
> >>>>> + build_append_int_noprefix(buf->buf, 0x01, 1);
> >>>> pls, do not modify internal buffer of Aml objects outside API,
> >>>> and do not export build_append_int_noprefix().
> >>>>
> >>>> Looking at spec _DSM returns bitfield buffer.
> >>>> for purposes you are using here i.e. set bit 1 to 1 or 0
> >>>> it's sufficient to use aml_int(1) or aml_int(0) as they are
> >>>> folded in OneOp /0x1/ and ZeroOp /0x0/ opcodes.
> >>>>
> >>>> However if you need to manipulate specific bitfields checkout
> >>>> CreateBitField /ACPI5.0: 19.5.18 CreateBitField (Create 1-Bit Buffer Field)/
> >>>> Probably that's what you are looking for.
> >>>>
> >>>> Also aml_buffer() needs to be modified to handle BufferSize
> >>>> see /ACPI5.0: 19.5.10 Buffer (Declare Buffer Object)/
> >>>> so that space for bitfields could be reserved
> >>>> /* as workaround/hack one can add several aml_int(0) into it to
> >>>> reserve needed amount of bytes */
> >>>
> >>> I dislike abusing aml_int like this, makes code hard to follow.
> >>> Best just do it properly.
> >>> Internally you can call append_byte.
> >>>
> >>
> >> I agree we could use append_byte to reserve BufferSize of bytes.
> >> But we still need a function to initialize the buffer. A new function
> >> wraps build_append_int_noprefix()?
> > just extend aml_buffer(BufferSize) and then use any appropriate
> > internal functions inside API.
> >
> > Outside you'll call:
> >
> > buf = aml_buffer(1);
> > aml_append(method, aml_name_decl("RET", buf);
> > aml_createbitfield("RET", 0, "FNEN"/* non 0 functions supported */);
> > ...
>
> Here I need to set the value of buffer to 1 or 0, we could
> createbitfield, but if we want to set the value to non one or zero and
> the BufferSize is large, how could we do? CreateByteField? It's a little
> complex for user.
that's what one would have to do writing it in ASL if bits
are flipped on/off dynamically.
In ASL you also can declare buffer with static initializer
Buffer (0x01) { 0x03 }
and compiler is smart enough to set appropriate bits but it doesn't
allow you to do so with large values. For example:
Buffer (0x01) { 0xAABBCCDD }
gives error:
Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
If one wants to manipulate specific fields in Buffer, ASL has
a bunch of CreateFOOField operators, so lets follow spec and use
API consistently to avoid confusion.
BTW:
packaging value as int (even without prefix) is wrong since
its LE encoding will shuffle bytes and you won't get bits in
positions that you expect if value is more than 1 byte.
>
> > ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> > aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
> > ...
> > /* create bit field for every supported function if supported */
> > ...
> > aml_append(method, aml_return(aml_name("RET")));
> >
> >
> >>
> >>>>
> >>>>> + aml_append(ifctx1, aml_return(buf));
> >>>>> + aml_append(ifctx, ifctx1);
> >>>>> + aml_append(method, ifctx);
> >>>>> +
> >>>>> + buf = aml_buffer();
> >>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
> >>>>> + aml_append(method, aml_return(buf));
> >>>>> + aml_append(dev, method);
> >>>>> +
> >>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
> >>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> >>>>> + aml_append(dev, dev_rp0);
> >>>>> + aml_append(scope, dev);
> >>>>> +}
> >>>>> +
> >>>>> /* RSDP */
> >>>>> static GArray *
> >>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> >>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> >>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
> >>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> >>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
> >>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> >>>>> +
> >>>>> aml_append(dsdt, scope);
> >>>>>
> >>>>> /* copy AML table into ACPI tables blob and patch header there */
> >>>
> >>> .
> >>>
> >>
> >>
> >
> >
> > .
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 15:13 ` Igor Mammedov
@ 2015-04-28 15:54 ` Michael S. Tsirkin
2015-04-29 3:12 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Michael S. Tsirkin @ 2015-04-28 15:54 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Tue, Apr 28, 2015 at 05:13:10PM +0200, Igor Mammedov wrote:
> > Here I need to set the value of buffer to 1 or 0, we could
> > createbitfield, but if we want to set the value to non one or zero and
> > the BufferSize is large, how could we do? CreateByteField? It's a little
> > complex for user.
> that's what one would have to do writing it in ASL if bits
> are flipped on/off dynamically.
>
> In ASL you also can declare buffer with static initializer
>
> Buffer (0x01) { 0x03 }
>
> and compiler is smart enough to set appropriate bits but it doesn't
> allow you to do so with large values. For example:
>
> Buffer (0x01) { 0xAABBCCDD }
>
> gives error:
> Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
>
> If one wants to manipulate specific fields in Buffer, ASL has
> a bunch of CreateFOOField operators, so lets follow spec and use
> API consistently to avoid confusion.
>
> BTW:
> packaging value as int (even without prefix) is wrong since
> its LE encoding will shuffle bytes and you won't get bits in
> positions that you expect if value is more than 1 byte.
I don't care about ASL, we are writing in C
But AML is same:
DefBuffer := BufferOp PkgLength BufferSize ByteList
BufferOp := 0x11
BufferSize := TermArg => Integer
So really just a bytelist.
We don't have any users for aml_buffer, maybe just add
const uint8_t *bytes, unsigned len as parameters.
Would that be enough?
> >
> > > ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> > > aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
> > > ...
> > > /* create bit field for every supported function if supported */
> > > ...
> > > aml_append(method, aml_return(aml_name("RET")));
> > >
> > >
> > >>
> > >>>>
> > >>>>> + aml_append(ifctx1, aml_return(buf));
> > >>>>> + aml_append(ifctx, ifctx1);
> > >>>>> + aml_append(method, ifctx);
> > >>>>> +
> > >>>>> + buf = aml_buffer();
> > >>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
> > >>>>> + aml_append(method, aml_return(buf));
> > >>>>> + aml_append(dev, method);
> > >>>>> +
> > >>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
> > >>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> > >>>>> + aml_append(dev, dev_rp0);
> > >>>>> + aml_append(scope, dev);
> > >>>>> +}
> > >>>>> +
> > >>>>> /* RSDP */
> > >>>>> static GArray *
> > >>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> > >>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> > >>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
> > >>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> > >>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
> > >>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> > >>>>> +
> > >>>>> aml_append(dsdt, scope);
> > >>>>>
> > >>>>> /* copy AML table into ACPI tables blob and patch header there */
> > >>>
> > >>> .
> > >>>
> > >>
> > >>
> > >
> > >
> > > .
> > >
> >
> >
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-28 15:54 ` Michael S. Tsirkin
@ 2015-04-29 3:12 ` Shannon Zhao
2015-04-29 8:47 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-29 3:12 UTC (permalink / raw)
To: Michael S. Tsirkin, Igor Mammedov
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/28 23:54, Michael S. Tsirkin wrote:
> On Tue, Apr 28, 2015 at 05:13:10PM +0200, Igor Mammedov wrote:
>>> Here I need to set the value of buffer to 1 or 0, we could
>>> createbitfield, but if we want to set the value to non one or zero and
>>> the BufferSize is large, how could we do? CreateByteField? It's a little
>>> complex for user.
>> that's what one would have to do writing it in ASL if bits
>> are flipped on/off dynamically.
>>
>> In ASL you also can declare buffer with static initializer
>>
>> Buffer (0x01) { 0x03 }
>>
>> and compiler is smart enough to set appropriate bits but it doesn't
>> allow you to do so with large values. For example:
>>
>> Buffer (0x01) { 0xAABBCCDD }
>>
>> gives error:
>> Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
>>
>> If one wants to manipulate specific fields in Buffer, ASL has
>> a bunch of CreateFOOField operators, so lets follow spec and use
>> API consistently to avoid confusion.
>>
>> BTW:
>> packaging value as int (even without prefix) is wrong since
>> its LE encoding will shuffle bytes and you won't get bits in
>> positions that you expect if value is more than 1 byte.
>
> I don't care about ASL, we are writing in C
> But AML is same:
> DefBuffer := BufferOp PkgLength BufferSize ByteList
> BufferOp := 0x11
> BufferSize := TermArg => Integer
>
> So really just a bytelist.
> We don't have any users for aml_buffer, maybe just add
> const uint8_t *bytes, unsigned len as parameters.
>
Agree. It's consistent with the spec. If want to modify the value, could
use CreateFOOField.
So use following fuction to initialize Buffer?
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
{
int i;
Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
for (i = 0; i < buffer_size; i++) {
build_append_byte(var->buf, *(byte_list + i));
}
return var;
}
> Would that be enough?
>
>
>>>
>>>> ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
>>>> aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
>>>> ...
>>>> /* create bit field for every supported function if supported */
>>>> ...
>>>> aml_append(method, aml_return(aml_name("RET")));
>>>>
>>>>
>>>>>
>>>>>>>
>>>>>>>> + aml_append(ifctx1, aml_return(buf));
>>>>>>>> + aml_append(ifctx, ifctx1);
>>>>>>>> + aml_append(method, ifctx);
>>>>>>>> +
>>>>>>>> + buf = aml_buffer();
>>>>>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
>>>>>>>> + aml_append(method, aml_return(buf));
>>>>>>>> + aml_append(dev, method);
>>>>>>>> +
>>>>>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
>>>>>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
>>>>>>>> + aml_append(dev, dev_rp0);
>>>>>>>> + aml_append(scope, dev);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> /* RSDP */
>>>>>>>> static GArray *
>>>>>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
>>>>>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>>>>>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
>>>>>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
>>>>>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
>>>>>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>>>>>>>> +
>>>>>>>> aml_append(dsdt, scope);
>>>>>>>>
>>>>>>>> /* copy AML table into ACPI tables blob and patch header there */
>>>>>>
>>>>>> .
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>> .
>>>>
>>>
>>>
>
> .
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-29 3:12 ` Shannon Zhao
@ 2015-04-29 8:47 ` Igor Mammedov
2015-04-29 13:37 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-04-29 8:47 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Wed, 29 Apr 2015 11:12:04 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/28 23:54, Michael S. Tsirkin wrote:
> > On Tue, Apr 28, 2015 at 05:13:10PM +0200, Igor Mammedov wrote:
> >>> Here I need to set the value of buffer to 1 or 0, we could
> >>> createbitfield, but if we want to set the value to non one or zero and
> >>> the BufferSize is large, how could we do? CreateByteField? It's a little
> >>> complex for user.
> >> that's what one would have to do writing it in ASL if bits
> >> are flipped on/off dynamically.
> >>
> >> In ASL you also can declare buffer with static initializer
> >>
> >> Buffer (0x01) { 0x03 }
> >>
> >> and compiler is smart enough to set appropriate bits but it doesn't
> >> allow you to do so with large values. For example:
> >>
> >> Buffer (0x01) { 0xAABBCCDD }
> >>
> >> gives error:
> >> Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
> >>
> >> If one wants to manipulate specific fields in Buffer, ASL has
> >> a bunch of CreateFOOField operators, so lets follow spec and use
> >> API consistently to avoid confusion.
> >>
> >> BTW:
> >> packaging value as int (even without prefix) is wrong since
> >> its LE encoding will shuffle bytes and you won't get bits in
> >> positions that you expect if value is more than 1 byte.
> >
> > I don't care about ASL, we are writing in C
> > But AML is same:
> > DefBuffer := BufferOp PkgLength BufferSize ByteList
> > BufferOp := 0x11
> > BufferSize := TermArg => Integer
> >
> > So really just a bytelist.
> > We don't have any users for aml_buffer, maybe just add
> > const uint8_t *bytes, unsigned len as parameters.
> >
>
> Agree. It's consistent with the spec. If want to modify the value, could
> use CreateFOOField.
>
> So use following fuction to initialize Buffer?
>
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
> Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
> {
> int i;
> Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
> for (i = 0; i < buffer_size; i++) {
> build_append_byte(var->buf, *(byte_list + i));
> }
> return var;
> }
maybe
Aml *aml_buffer_initialized(int buffer_size, uint8_t *byte_list);
Aml *aml_buffer(int buffer_size);
the second one is needed for implementing code like:
Name(BUFF, Buffer(4){}) // Create SerialBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT) // STAT = Status (Byte)
CreateWordField(BUFF, 0x02, DATA) // DATA = Data (Byte)
and could reuse aml_buffer_initialized() to reserve space.
>
> > Would that be enough?
> >
> >
> >>>
> >>>> ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> >>>> aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
> >>>> ...
> >>>> /* create bit field for every supported function if supported */
> >>>> ...
> >>>> aml_append(method, aml_return(aml_name("RET")));
> >>>>
> >>>>
> >>>>>
> >>>>>>>
> >>>>>>>> + aml_append(ifctx1, aml_return(buf));
> >>>>>>>> + aml_append(ifctx, ifctx1);
> >>>>>>>> + aml_append(method, ifctx);
> >>>>>>>> +
> >>>>>>>> + buf = aml_buffer();
> >>>>>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
> >>>>>>>> + aml_append(method, aml_return(buf));
> >>>>>>>> + aml_append(dev, method);
> >>>>>>>> +
> >>>>>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
> >>>>>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> >>>>>>>> + aml_append(dev, dev_rp0);
> >>>>>>>> + aml_append(scope, dev);
> >>>>>>>> +}
> >>>>>>>> +
> >>>>>>>> /* RSDP */
> >>>>>>>> static GArray *
> >>>>>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> >>>>>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> >>>>>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
> >>>>>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> >>>>>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
> >>>>>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> >>>>>>>> +
> >>>>>>>> aml_append(dsdt, scope);
> >>>>>>>>
> >>>>>>>> /* copy AML table into ACPI tables blob and patch header there */
> >>>>>>
> >>>>>> .
> >>>>>>
> >>>>>
> >>>>>
> >>>>
> >>>>
> >>>> .
> >>>>
> >>>
> >>>
> >
> > .
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-29 8:47 ` Igor Mammedov
@ 2015-04-29 13:37 ` Shannon Zhao
2015-04-29 13:58 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-29 13:37 UTC (permalink / raw)
To: Igor Mammedov, Shannon Zhao
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall
On 2015/4/29 16:47, Igor Mammedov wrote:
> On Wed, 29 Apr 2015 11:12:04 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> On 2015/4/28 23:54, Michael S. Tsirkin wrote:
>>> On Tue, Apr 28, 2015 at 05:13:10PM +0200, Igor Mammedov wrote:
>>>>> Here I need to set the value of buffer to 1 or 0, we could
>>>>> createbitfield, but if we want to set the value to non one or zero and
>>>>> the BufferSize is large, how could we do? CreateByteField? It's a little
>>>>> complex for user.
>>>> that's what one would have to do writing it in ASL if bits
>>>> are flipped on/off dynamically.
>>>>
>>>> In ASL you also can declare buffer with static initializer
>>>>
>>>> Buffer (0x01) { 0x03 }
>>>>
>>>> and compiler is smart enough to set appropriate bits but it doesn't
>>>> allow you to do so with large values. For example:
>>>>
>>>> Buffer (0x01) { 0xAABBCCDD }
>>>>
>>>> gives error:
>>>> Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
>>>>
>>>> If one wants to manipulate specific fields in Buffer, ASL has
>>>> a bunch of CreateFOOField operators, so lets follow spec and use
>>>> API consistently to avoid confusion.
>>>>
>>>> BTW:
>>>> packaging value as int (even without prefix) is wrong since
>>>> its LE encoding will shuffle bytes and you won't get bits in
>>>> positions that you expect if value is more than 1 byte.
>>>
>>> I don't care about ASL, we are writing in C
>>> But AML is same:
>>> DefBuffer := BufferOp PkgLength BufferSize ByteList
>>> BufferOp := 0x11
>>> BufferSize := TermArg => Integer
>>>
>>> So really just a bytelist.
>>> We don't have any users for aml_buffer, maybe just add
>>> const uint8_t *bytes, unsigned len as parameters.
>>>
>>
>> Agree. It's consistent with the spec. If want to modify the value, could
>> use CreateFOOField.
>>
>> So use following fuction to initialize Buffer?
>>
>> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
>> Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
>> {
>> int i;
>> Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
>> for (i = 0; i < buffer_size; i++) {
>> build_append_byte(var->buf, *(byte_list + i));
>> }
>> return var;
>> }
> maybe
>
> Aml *aml_buffer_initialized(int buffer_size, uint8_t *byte_list);
> Aml *aml_buffer(int buffer_size);
>
> the second one is needed for implementing code like:
> Name(BUFF, Buffer(4){}) // Create SerialBus data buffer as BUFF
> CreateByteField(BUFF, 0x00, STAT) // STAT = Status (Byte)
> CreateWordField(BUFF, 0x02, DATA) // DATA = Data (Byte)
>
> and could reuse aml_buffer_initialized() to reserve space.
>
maybe we could use only one. For the uninitialized buffer we can pass
byte_list as NULL and within aml_buffer check byte_list, if byte_list is
NULL, just reserve space.
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
{
int i;
Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
for (i = 0; i < buffer_size; i++) {
if (byte_list == NULL)
build_append_byte(var->buf, 0);
else
build_append_byte(var->buf, *(byte_list + i));
}
return var;
}
>>
>>> Would that be enough?
>>>
>>>
>>>>>
>>>>>> ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
>>>>>> aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
>>>>>> ...
>>>>>> /* create bit field for every supported function if supported */
>>>>>> ...
>>>>>> aml_append(method, aml_return(aml_name("RET")));
>>>>>>
>>>>>>
>>>>>>>
>>>>>>>>>
>>>>>>>>>> + aml_append(ifctx1, aml_return(buf));
>>>>>>>>>> + aml_append(ifctx, ifctx1);
>>>>>>>>>> + aml_append(method, ifctx);
>>>>>>>>>> +
>>>>>>>>>> + buf = aml_buffer();
>>>>>>>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
>>>>>>>>>> + aml_append(method, aml_return(buf));
>>>>>>>>>> + aml_append(dev, method);
>>>>>>>>>> +
>>>>>>>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
>>>>>>>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
>>>>>>>>>> + aml_append(dev, dev_rp0);
>>>>>>>>>> + aml_append(scope, dev);
>>>>>>>>>> +}
>>>>>>>>>> +
>>>>>>>>>> /* RSDP */
>>>>>>>>>> static GArray *
>>>>>>>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
>>>>>>>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>>>>>>>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
>>>>>>>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
>>>>>>>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
>>>>>>>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>>>>>>>>>> +
>>>>>>>>>> aml_append(dsdt, scope);
>>>>>>>>>>
>>>>>>>>>> /* copy AML table into ACPI tables blob and patch header there */
>>>>>>>>
>>>>>>>> .
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>> .
>>>>>>
>>>>>
>>>>>
>>>
>>> .
>>>
>>
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-28 9:48 ` Shannon Zhao
@ 2015-04-29 13:41 ` Shannon Zhao
2015-05-04 9:22 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-04-29 13:41 UTC (permalink / raw)
To: Shannon Zhao, Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall
On 2015/4/28 17:48, Shannon Zhao wrote:
> On 2015/4/28 17:35, Igor Mammedov wrote:
>> On Tue, 28 Apr 2015 16:52:19 +0800
>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>
>>> On 2015/4/28 16:15, Igor Mammedov wrote:
>>>>>> btw:
>>>>>>>> whole thing might be simpler if an intermediate conversion is avoided,
>>>>>>>> just pack buffer as in spec byte by byte:
>>>>>>>>
>>>>>>>> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
>>>>>>>> assert(strlen(uuid) == ...);
>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
>>>>>>
>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
>>>>>>
>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
>>>>>>
>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
>>>> if you mean hyphens /-/ then they are not encoded,
>>>> but you surely can add checks for them to make sure that
>>>> UUID format is as expected.
>>>>
>>>
>>> I mean uuid[3] points to b not dd. Maybe use following way:
>>>
>>> static uint8_t Hex2Byte(char *src)
>> or even better:
>> Hex2Byte(char *src, byte_idx)
>> and do pointer arithmetic inside
>>
>> [...]
>>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
>> build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
>> build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
>> ...
>>
> Yes, it's better to first four bytes. But there are hyphens /-/, for
> offset 04, 05 and etc it doesn't work. We can't use following expression:
>
> build_append_byte(var->buf, Hex2Byte(uuid, 5)); /* ff - at offset 04 */
> build_append_byte(var->buf, Hex2Byte(uuid, 4)); /* ee - at offset 05 */
> ...
>
>
So about the implementation of this macro, I think I'd like to use
following approach. This lets Hex2Byte do what it should only do and
still has a clear look of UUID. What do you think about?
static uint8_t Hex2Byte(char *src)
{
int hi = Hex2Digit(*src++);
int lo = Hex2Digit(*src);
if ((hi < 0) || (lo < 0))
return -1;
return (hi << 4) | lo;
}
g_assert((strlen(uuid) == 36) && (uuid[8] == '-') && (uuid[13] == '-')
&& (uuid[18] == '-') && (uuid[23] == '-'));
build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
build_append_byte(var->buf, Hex2Byte(uuid + (2 * 2))); /* cc */
build_append_byte(var->buf, Hex2Byte(uuid + (1 * 2))); /* bb */
build_append_byte(var->buf, Hex2Byte(uuid + (0 * 2))); /* aa */
build_append_byte(var->buf, Hex2Byte(uuid + (5 * 2 + 1))); /* ff */
build_append_byte(var->buf, Hex2Byte(uuid + (4 * 2 + 1))); /* ee */
build_append_byte(var->buf, Hex2Byte(uuid + (7 * 2 + 2))); /* hh */
build_append_byte(var->buf, Hex2Byte(uuid + (6 * 2 + 2))); /* gg */
build_append_byte(var->buf, Hex2Byte(uuid + (8 * 2 + 3))); /* ii */
build_append_byte(var->buf, Hex2Byte(uuid + (9 * 2 + 3))); /* jj */
build_append_byte(var->buf, Hex2Byte(uuid + (10 * 2 + 4))); /* kk */
build_append_byte(var->buf, Hex2Byte(uuid + (11 * 2 + 4))); /* ll */
build_append_byte(var->buf, Hex2Byte(uuid + (12 * 2 + 4))); /* mm */
build_append_byte(var->buf, Hex2Byte(uuid + (13 * 2 + 4))); /* nn */
build_append_byte(var->buf, Hex2Byte(uuid + (14 * 2 + 4))); /* oo */
build_append_byte(var->buf, Hex2Byte(uuid + (15 * 2 + 4))); /* pp */
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-29 13:37 ` Shannon Zhao
@ 2015-04-29 13:58 ` Igor Mammedov
0 siblings, 0 replies; 56+ messages in thread
From: Igor Mammedov @ 2015-04-29 13:58 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, Michael S. Tsirkin, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, Shannon Zhao, pbonzini, lersek, christoffer.dall
On Wed, 29 Apr 2015 21:37:11 +0800
Shannon Zhao <shannon.zhao@linaro.org> wrote:
>
>
> On 2015/4/29 16:47, Igor Mammedov wrote:
> > On Wed, 29 Apr 2015 11:12:04 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> On 2015/4/28 23:54, Michael S. Tsirkin wrote:
> >>> On Tue, Apr 28, 2015 at 05:13:10PM +0200, Igor Mammedov wrote:
> >>>>> Here I need to set the value of buffer to 1 or 0, we could
> >>>>> createbitfield, but if we want to set the value to non one or zero and
> >>>>> the BufferSize is large, how could we do? CreateByteField? It's a little
> >>>>> complex for user.
> >>>> that's what one would have to do writing it in ASL if bits
> >>>> are flipped on/off dynamically.
> >>>>
> >>>> In ASL you also can declare buffer with static initializer
> >>>>
> >>>> Buffer (0x01) { 0x03 }
> >>>>
> >>>> and compiler is smart enough to set appropriate bits but it doesn't
> >>>> allow you to do so with large values. For example:
> >>>>
> >>>> Buffer (0x01) { 0xAABBCCDD }
> >>>>
> >>>> gives error:
> >>>> Error 6139 - Constant out of range ^ (0xAABBCCDD, allowable: 0x0-0xFF)
> >>>>
> >>>> If one wants to manipulate specific fields in Buffer, ASL has
> >>>> a bunch of CreateFOOField operators, so lets follow spec and use
> >>>> API consistently to avoid confusion.
> >>>>
> >>>> BTW:
> >>>> packaging value as int (even without prefix) is wrong since
> >>>> its LE encoding will shuffle bytes and you won't get bits in
> >>>> positions that you expect if value is more than 1 byte.
> >>>
> >>> I don't care about ASL, we are writing in C
> >>> But AML is same:
> >>> DefBuffer := BufferOp PkgLength BufferSize ByteList
> >>> BufferOp := 0x11
> >>> BufferSize := TermArg => Integer
> >>>
> >>> So really just a bytelist.
> >>> We don't have any users for aml_buffer, maybe just add
> >>> const uint8_t *bytes, unsigned len as parameters.
> >>>
> >>
> >> Agree. It's consistent with the spec. If want to modify the value, could
> >> use CreateFOOField.
> >>
> >> So use following fuction to initialize Buffer?
> >>
> >> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
> >> Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
> >> {
> >> int i;
> >> Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
> >> for (i = 0; i < buffer_size; i++) {
> >> build_append_byte(var->buf, *(byte_list + i));
> >> }
> >> return var;
> >> }
> > maybe
> >
> > Aml *aml_buffer_initialized(int buffer_size, uint8_t *byte_list);
> > Aml *aml_buffer(int buffer_size);
> >
> > the second one is needed for implementing code like:
> > Name(BUFF, Buffer(4){}) // Create SerialBus data buffer as BUFF
> > CreateByteField(BUFF, 0x00, STAT) // STAT = Status (Byte)
> > CreateWordField(BUFF, 0x02, DATA) // DATA = Data (Byte)
> >
> > and could reuse aml_buffer_initialized() to reserve space.
> >
>
> maybe we could use only one. For the uninitialized buffer we can pass
> byte_list as NULL and within aml_buffer check byte_list, if byte_list is
> NULL, just reserve space.
works for me with doc comment
>
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
> Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
> {
> int i;
> Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
>
> for (i = 0; i < buffer_size; i++) {
> if (byte_list == NULL)
> build_append_byte(var->buf, 0);
> else
> build_append_byte(var->buf, *(byte_list + i));
> }
>
> return var;
> }
>
> >>
> >>> Would that be enough?
> >>>
> >>>
> >>>>>
> >>>>>> ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> >>>>>> aml_append(ifctx1, aml_store(aml_name("FNEN", aml_int(1)));
> >>>>>> ...
> >>>>>> /* create bit field for every supported function if supported */
> >>>>>> ...
> >>>>>> aml_append(method, aml_return(aml_name("RET")));
> >>>>>>
> >>>>>>
> >>>>>>>
> >>>>>>>>>
> >>>>>>>>>> + aml_append(ifctx1, aml_return(buf));
> >>>>>>>>>> + aml_append(ifctx, ifctx1);
> >>>>>>>>>> + aml_append(method, ifctx);
> >>>>>>>>>> +
> >>>>>>>>>> + buf = aml_buffer();
> >>>>>>>>>> + build_append_int_noprefix(buf->buf, 0x00, 1);
> >>>>>>>>>> + aml_append(method, aml_return(buf));
> >>>>>>>>>> + aml_append(dev, method);
> >>>>>>>>>> +
> >>>>>>>>>> + Aml *dev_rp0 = aml_device("%s", "RP0");
> >>>>>>>>>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> >>>>>>>>>> + aml_append(dev, dev_rp0);
> >>>>>>>>>> + aml_append(scope, dev);
> >>>>>>>>>> +}
> >>>>>>>>>> +
> >>>>>>>>>> /* RSDP */
> >>>>>>>>>> static GArray *
> >>>>>>>>>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> >>>>>>>>>> @@ -318,6 +468,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> >>>>>>>>>> acpi_dsdt_add_flash(scope, info->flash_memmap);
> >>>>>>>>>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> >>>>>>>>>> info->virtio_mmio_irq, info->virtio_mmio_num);
> >>>>>>>>>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
> >>>>>>>>>> +
> >>>>>>>>>> aml_append(dsdt, scope);
> >>>>>>>>>>
> >>>>>>>>>> /* copy AML table into ACPI tables blob and patch header there */
> >>>>>>>>
> >>>>>>>> .
> >>>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>
> >>>>>>
> >>>>>> .
> >>>>>>
> >>>>>
> >>>>>
> >>>
> >>> .
> >>>
> >>
> >>
> >
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-29 13:41 ` Shannon Zhao
@ 2015-05-04 9:22 ` Igor Mammedov
2015-05-04 9:30 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-05-04 9:22 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall
On Wed, 29 Apr 2015 21:41:39 +0800
Shannon Zhao <shannon.zhao@linaro.org> wrote:
>
>
> On 2015/4/28 17:48, Shannon Zhao wrote:
> > On 2015/4/28 17:35, Igor Mammedov wrote:
> >> On Tue, 28 Apr 2015 16:52:19 +0800
> >> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >>
> >>> On 2015/4/28 16:15, Igor Mammedov wrote:
> >>>>>> btw:
> >>>>>>>> whole thing might be simpler if an intermediate conversion is avoided,
> >>>>>>>> just pack buffer as in spec byte by byte:
> >>>>>>>>
> >>>>>>>> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> >>>>>>>> assert(strlen(uuid) == ...);
> >>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
> >>>>>>
> >>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
> >>>>>>
> >>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
> >>>>>>
> >>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
> >>>> if you mean hyphens /-/ then they are not encoded,
> >>>> but you surely can add checks for them to make sure that
> >>>> UUID format is as expected.
> >>>>
> >>>
> >>> I mean uuid[3] points to b not dd. Maybe use following way:
> >>>
> >>> static uint8_t Hex2Byte(char *src)
> >> or even better:
> >> Hex2Byte(char *src, byte_idx)
> >> and do pointer arithmetic inside
> >>
> >> [...]
> >>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
> >> build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
> >> build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
> >> ...
> >>
> > Yes, it's better to first four bytes. But there are hyphens /-/, for
> > offset 04, 05 and etc it doesn't work. We can't use following expression:
> >
> > build_append_byte(var->buf, Hex2Byte(uuid, 5)); /* ff - at offset 04 */
> > build_append_byte(var->buf, Hex2Byte(uuid, 4)); /* ee - at offset 05 */
> > ...
> >
> >
>
> So about the implementation of this macro, I think I'd like to use
> following approach. This lets Hex2Byte do what it should only do and
> still has a clear look of UUID. What do you think about?
>
> static uint8_t Hex2Byte(char *src)
> {
> int hi = Hex2Digit(*src++);
> int lo = Hex2Digit(*src);
>
> if ((hi < 0) || (lo < 0))
> return -1;
just make Hex2Digit() assert on wrong input.
>
> return (hi << 4) | lo;
> }
>
> g_assert((strlen(uuid) == 36) && (uuid[8] == '-') && (uuid[13] == '-')
> && (uuid[18] == '-') && (uuid[23] == '-'));
>
> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
^^^^^
I'd make it one number, instead of forcing reader to do math
every time he/she looks at this code.
> build_append_byte(var->buf, Hex2Byte(uuid + (2 * 2))); /* cc */
> build_append_byte(var->buf, Hex2Byte(uuid + (1 * 2))); /* bb */
> build_append_byte(var->buf, Hex2Byte(uuid + (0 * 2))); /* aa */
>
> build_append_byte(var->buf, Hex2Byte(uuid + (5 * 2 + 1))); /* ff */
> build_append_byte(var->buf, Hex2Byte(uuid + (4 * 2 + 1))); /* ee */
>
> build_append_byte(var->buf, Hex2Byte(uuid + (7 * 2 + 2))); /* hh */
> build_append_byte(var->buf, Hex2Byte(uuid + (6 * 2 + 2))); /* gg */
>
> build_append_byte(var->buf, Hex2Byte(uuid + (8 * 2 + 3))); /* ii */
> build_append_byte(var->buf, Hex2Byte(uuid + (9 * 2 + 3))); /* jj */
>
> build_append_byte(var->buf, Hex2Byte(uuid + (10 * 2 + 4))); /* kk */
> build_append_byte(var->buf, Hex2Byte(uuid + (11 * 2 + 4))); /* ll */
> build_append_byte(var->buf, Hex2Byte(uuid + (12 * 2 + 4))); /* mm */
> build_append_byte(var->buf, Hex2Byte(uuid + (13 * 2 + 4))); /* nn */
> build_append_byte(var->buf, Hex2Byte(uuid + (14 * 2 + 4))); /* oo */
> build_append_byte(var->buf, Hex2Byte(uuid + (15 * 2 + 4))); /* pp */
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-05-04 9:22 ` Igor Mammedov
@ 2015-05-04 9:30 ` Shannon Zhao
2015-05-04 10:53 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-05-04 9:30 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall
On 2015/5/4 17:22, Igor Mammedov wrote:
> On Wed, 29 Apr 2015 21:41:39 +0800
> Shannon Zhao <shannon.zhao@linaro.org> wrote:
>
>>
>>
>> On 2015/4/28 17:48, Shannon Zhao wrote:
>>> On 2015/4/28 17:35, Igor Mammedov wrote:
>>>> On Tue, 28 Apr 2015 16:52:19 +0800
>>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>>>
>>>>> On 2015/4/28 16:15, Igor Mammedov wrote:
>>>>>>>> btw:
>>>>>>>>>> whole thing might be simpler if an intermediate conversion is avoided,
>>>>>>>>>> just pack buffer as in spec byte by byte:
>>>>>>>>>>
>>>>>>>>>> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
>>>>>>>>>> assert(strlen(uuid) == ...);
>>>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
>>>>>>>>
>>>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
>>>>>>>>
>>>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
>>>>>>>>
>>>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
>>>>>> if you mean hyphens /-/ then they are not encoded,
>>>>>> but you surely can add checks for them to make sure that
>>>>>> UUID format is as expected.
>>>>>>
>>>>>
>>>>> I mean uuid[3] points to b not dd. Maybe use following way:
>>>>>
>>>>> static uint8_t Hex2Byte(char *src)
>>>> or even better:
>>>> Hex2Byte(char *src, byte_idx)
>>>> and do pointer arithmetic inside
>>>>
>>>> [...]
>>>>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
>>>> build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
>>>> build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
>>>> ...
>>>>
>>> Yes, it's better to first four bytes. But there are hyphens /-/, for
>>> offset 04, 05 and etc it doesn't work. We can't use following expression:
>>>
>>> build_append_byte(var->buf, Hex2Byte(uuid, 5)); /* ff - at offset 04 */
>>> build_append_byte(var->buf, Hex2Byte(uuid, 4)); /* ee - at offset 05 */
>>> ...
>>>
>>>
>>
>> So about the implementation of this macro, I think I'd like to use
>> following approach. This lets Hex2Byte do what it should only do and
>> still has a clear look of UUID. What do you think about?
>>
>> static uint8_t Hex2Byte(char *src)
>> {
>> int hi = Hex2Digit(*src++);
>> int lo = Hex2Digit(*src);
>>
>> if ((hi < 0) || (lo < 0))
>> return -1;
> just make Hex2Digit() assert on wrong input.
>
Ok.
>>
>> return (hi << 4) | lo;
>> }
>>
>> g_assert((strlen(uuid) == 36) && (uuid[8] == '-') && (uuid[13] == '-')
>> && (uuid[18] == '-') && (uuid[23] == '-'));
>>
>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
> ^^^^^
> I'd make it one number, instead of forcing reader to do math
> every time he/she looks at this code.
>
Ok, will do this. And about other patches in this series could you offer
your comments?
Thanks,
Shannon
>
>> build_append_byte(var->buf, Hex2Byte(uuid + (2 * 2))); /* cc */
>> build_append_byte(var->buf, Hex2Byte(uuid + (1 * 2))); /* bb */
>> build_append_byte(var->buf, Hex2Byte(uuid + (0 * 2))); /* aa */
>>
>> build_append_byte(var->buf, Hex2Byte(uuid + (5 * 2 + 1))); /* ff */
>> build_append_byte(var->buf, Hex2Byte(uuid + (4 * 2 + 1))); /* ee */
>>
>> build_append_byte(var->buf, Hex2Byte(uuid + (7 * 2 + 2))); /* hh */
>> build_append_byte(var->buf, Hex2Byte(uuid + (6 * 2 + 2))); /* gg */
>>
>> build_append_byte(var->buf, Hex2Byte(uuid + (8 * 2 + 3))); /* ii */
>> build_append_byte(var->buf, Hex2Byte(uuid + (9 * 2 + 3))); /* jj */
>>
>> build_append_byte(var->buf, Hex2Byte(uuid + (10 * 2 + 4))); /* kk */
>> build_append_byte(var->buf, Hex2Byte(uuid + (11 * 2 + 4))); /* ll */
>> build_append_byte(var->buf, Hex2Byte(uuid + (12 * 2 + 4))); /* mm */
>> build_append_byte(var->buf, Hex2Byte(uuid + (13 * 2 + 4))); /* nn */
>> build_append_byte(var->buf, Hex2Byte(uuid + (14 * 2 + 4))); /* oo */
>> build_append_byte(var->buf, Hex2Byte(uuid + (15 * 2 + 4))); /* pp */
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
@ 2015-05-04 9:58 ` Igor Mammedov
2015-05-04 11:11 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-05-04 9:58 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Wed, 15 Apr 2015 21:24:55 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> DSDT consists of the usual common table header plus a definition
> block in AML encoding which describes all devices in the platform.
>
> After initializing DSDT with header information the namespace is
> created which is followed by the device encodings. The devices are
> described using the Resource Template for the 32-Bit Fixed Memory
> Range and the Extended Interrupt Descriptors.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 128 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index c5a3cf9..d044880 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -50,6 +50,130 @@
> #include "qom/qom-qobject.h"
> #include "exec/ram_addr.h"
>
> +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> +{
> + uint16_t i;
> +
> + for (i = 0; i < max_cpus; i++) {
> + Aml *dev = aml_device("C%03x", i);
> + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> + Aml *crs = aml_resource_template();
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + }
> +}
Is maxcpus a correct here? Usually maxcpus includes non present CPUs
as well but there is no STA method that tells whether it's present or not.
> +
> +static void acpi_dsdt_add_uart(Aml *scope, const MemMap *uart_memmap,
> + const int *uart_irq)
> +{
> + Aml *dev = aml_device("COM0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(uart_memmap->addr,
> + uart_memmap->size, aml_ReadWrite));
> + aml_append(crs,
> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> + aml_exclusive, aml_not_wake_capable, *uart_irq + 32));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_rtc(Aml *scope, const MemMap *rtc_memmap,
> + const int *rtc_irq)
> +{
> + Aml *dev = aml_device("RTC0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(rtc_memmap->addr,
> + rtc_memmap->size, aml_ReadWrite));
> + aml_append(crs,
> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> + aml_exclusive, aml_not_wake_capable, *rtc_irq + 32));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_flash(Aml *scope, const MemMap *flash_memmap)
> +{
> + Aml *dev, *crs;
> + hwaddr base = flash_memmap->addr;
> + hwaddr size = flash_memmap->size;
> +
> + dev = aml_device("FLS0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +
> + dev = aml_device("FLS1");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
> + crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(base + size, size, aml_ReadWrite));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> + const int *mmio_irq, int num)
> +{
> + hwaddr base = virtio_mmio_memmap->addr;
> + hwaddr size = virtio_mmio_memmap->size;
> + int irq = *mmio_irq + 32;
> + int i;
> +
> + for (i = 0; i < num; i++) {
> + Aml *dev = aml_device("VR%02u", i);
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
> + aml_append(crs,
> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
> + aml_exclusive, aml_not_wake_capable, irq + i));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + base += size;
> + }
> +}
> +
> +/* DSDT */
> +static void
> +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> +{
> + Aml *scope, *dsdt;
> + AcpiDsdtInfo *info = guest_info->dsdt_info;
> +
> + dsdt = init_aml_allocator();
> + /* Reserve space for header */
> + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
> +
> + scope = aml_scope("\\_SB");
> + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
> + acpi_dsdt_add_uart(scope, info->uart_memmap, info->uart_irq);
> + acpi_dsdt_add_rtc(scope, info->rtc_memmap, info->rtc_irq);
> + acpi_dsdt_add_flash(scope, info->flash_memmap);
> + acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> + info->virtio_mmio_irq, info->virtio_mmio_num);
> + aml_append(dsdt, scope);
> +
> + /* copy AML table into ACPI tables blob and patch header there */
> + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
> + build_header(linker, table_data,
> + (void *)(table_data->data + table_data->len - dsdt->buf->len),
> + "DSDT", dsdt->buf->len, 1);
shouldn't revision be 5?
> + free_aml_allocator();
> +}
> +
> typedef
> struct AcpiBuildState {
> /* Copy of table in RAM (for patching). */
> @@ -65,6 +189,7 @@ static
> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> + GArray *tables_blob = tables->table_data;
>
> table_offsets = g_array_new(false, true /* clear */,
> sizeof(uint32_t));
> @@ -82,6 +207,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> * DSDT
> */
>
> + /* DSDT is pointed to by FADT */
> + build_dsdt(tables_blob, tables->linker, guest_info);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-05-04 10:21 ` Igor Mammedov
2015-05-04 11:16 ` Shannon Zhao
0 siblings, 1 reply; 56+ messages in thread
From: Igor Mammedov @ 2015-05-04 10:21 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Wed, 15 Apr 2015 21:24:57 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> MADT describes GIC enabled ARM platforms. The GICC and GICD
> subtables are used to define the GIC regions.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++++++++++++++++
> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++-
> include/hw/arm/virt-acpi-build.h | 2 ++
> 3 files changed, 100 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index c72a9c8..94cced0 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -50,6 +50,20 @@
> #include "qom/qom-qobject.h"
> #include "exec/ram_addr.h"
>
> +typedef struct VirtAcpiCpuInfo {
> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> +} VirtAcpiCpuInfo;
> +
> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
> +{
> + CPUState *cpu;
> +
> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
> + CPU_FOREACH(cpu) {
> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
> + }
> +}
> +
> static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> {
> uint16_t i;
> @@ -146,6 +160,47 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
> }
> }
>
> +/* MADT */
> +static void
> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
> + VirtAcpiCpuInfo *cpuinfo)
> +{
> + int madt_start = table_data->len;
> + const struct AcpiMadtInfo *info = guest_info->madt_info;
> + AcpiMultipleApicTable *madt;
> + AcpiMadtGenericDistributor *gicd;
> + int i;
> +
> + madt = acpi_data_push(table_data, sizeof *madt);
> + madt->local_apic_address = info->gic_cpu_memmap->addr;
should be safe to drop this since OSPM must ignore this field if
gicc provides base_address.
> + madt->flags = cpu_to_le32(1);
is it correct?
Looking at 5.1 spec it's x86 specific PCAT_COMPAT flag,
why do you use it for ARM?
> +
> + for (i = 0; i < guest_info->max_cpus; i++) {
> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
> + sizeof *gicc);
> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
> + gicc->length = sizeof(*gicc);
> + gicc->base_address = info->gic_cpu_memmap->addr;
> + gicc->cpu_interface_number = i;
> + gicc->arm_mpidr = i;
> + gicc->uid = i;
> + if (test_bit(i, cpuinfo->found_cpus)) {
> + gicc->flags = cpu_to_le32(1);
#define ACPI_GICC_ENABLED 1
> + } else {
> + gicc->flags = cpu_to_le32(0);
> + }
not necessary else clause, field is zeroed by default.
> + }
> +
> + gicd = acpi_data_push(table_data, sizeof *gicd);
> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
> + gicd->length = sizeof(*gicd);
> + gicd->base_address = info->gic_dist_memmap->addr;
> +
> + build_header(linker, table_data,
> + (void *)(table_data->data + madt_start), "APIC",
> + table_data->len - madt_start, 1);
wrong revision?
> +}
> +
> /* FADT */
> static void
> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
> @@ -215,8 +270,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> unsigned dsdt;
> + VirtAcpiCpuInfo cpuinfo;
> GArray *tables_blob = tables->table_data;
>
> + virt_acpi_get_cpu_info(&cpuinfo);
> +
> table_offsets = g_array_new(false, true /* clear */,
> sizeof(uint32_t));
>
> @@ -241,6 +299,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_fadt(tables_blob, tables->linker, dsdt);
>
> + acpi_add_table(table_offsets, tables_blob);
> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index bac981d..4092dc3 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -236,7 +236,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
> #define ACPI_APIC_IO_SAPIC 6
> #define ACPI_APIC_LOCAL_SAPIC 7
> #define ACPI_APIC_XRUPT_SOURCE 8
> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
> +#define ACPI_APIC_LOCAL_X2APIC 9
> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
> +#define ACPI_APIC_GENERIC_INTERRUPT 11
> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>
> /*
> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
> @@ -284,6 +290,36 @@ struct AcpiMadtLocalNmi {
> } QEMU_PACKED;
> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>
> +struct AcpiMadtGenericInterrupt {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t cpu_interface_number;
> + uint32_t uid;
> + uint32_t flags;
> + uint32_t parking_version;
> + uint32_t performance_interrupt;
> + uint64_t parked_address;
> + uint64_t base_address;
> + uint64_t gicv_base_address;
> + uint64_t gich_base_address;
> + uint32_t vgic_interrupt;
> + uint64_t gicr_base_address;
> + uint64_t arm_mpidr;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
> +
> +struct AcpiMadtGenericDistributor {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t gic_id;
> + uint64_t base_address;
> + uint32_t global_irq_base;
> + uint32_t reserved2;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
> +
> /*
> * HPET Description Table
> */
> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> index ece67a2..8f0b4a7 100644
> --- a/include/hw/arm/virt-acpi-build.h
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -22,6 +22,8 @@
>
> #include "qemu-common.h"
>
> +#define VIRT_ACPI_CPU_ID_LIMIT 8
> +
> typedef struct MemMap {
> hwaddr addr;
> hwaddr size;
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-05-04 9:30 ` Shannon Zhao
@ 2015-05-04 10:53 ` Igor Mammedov
0 siblings, 0 replies; 56+ messages in thread
From: Igor Mammedov @ 2015-05-04 10:53 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, lersek, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, alex.bennee, christoffer.dall
On Mon, 04 May 2015 17:30:20 +0800
Shannon Zhao <shannon.zhao@linaro.org> wrote:
>
>
> On 2015/5/4 17:22, Igor Mammedov wrote:
> > On Wed, 29 Apr 2015 21:41:39 +0800
> > Shannon Zhao <shannon.zhao@linaro.org> wrote:
> >
> >>
> >>
> >> On 2015/4/28 17:48, Shannon Zhao wrote:
> >>> On 2015/4/28 17:35, Igor Mammedov wrote:
> >>>> On Tue, 28 Apr 2015 16:52:19 +0800
> >>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >>>>
> >>>>> On 2015/4/28 16:15, Igor Mammedov wrote:
> >>>>>>>> btw:
> >>>>>>>>>> whole thing might be simpler if an intermediate conversion is avoided,
> >>>>>>>>>> just pack buffer as in spec byte by byte:
> >>>>>>>>>>
> >>>>>>>>>> /* format: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp */
> >>>>>>>>>> assert(strlen(uuid) == ...);
> >>>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[3]); /* dd */
> >>>>>>>>
> >>>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 7); ?
> >>>>>>>>
> >>>>>>>>>> build_append_byte(var->buf, HEX2BYTE(uuid[2]); /* cc */
> >>>>>>>>
> >>>>>>>> use build_append_byte(var->buf, HEX2BYTE(uuid + 5); ?
> >>>>>> if you mean hyphens /-/ then they are not encoded,
> >>>>>> but you surely can add checks for them to make sure that
> >>>>>> UUID format is as expected.
> >>>>>>
> >>>>>
> >>>>> I mean uuid[3] points to b not dd. Maybe use following way:
> >>>>>
> >>>>> static uint8_t Hex2Byte(char *src)
> >>>> or even better:
> >>>> Hex2Byte(char *src, byte_idx)
> >>>> and do pointer arithmetic inside
> >>>>
> >>>> [...]
> >>>>> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
> >>>> build_append_byte(var->buf, Hex2Byte(uuid, 3)); /* dd - at offset 00 */
> >>>> build_append_byte(var->buf, Hex2Byte(uuid, 2)); /* cc - at offset 01 */
> >>>> ...
> >>>>
> >>> Yes, it's better to first four bytes. But there are hyphens /-/, for
> >>> offset 04, 05 and etc it doesn't work. We can't use following expression:
> >>>
> >>> build_append_byte(var->buf, Hex2Byte(uuid, 5)); /* ff - at offset 04 */
> >>> build_append_byte(var->buf, Hex2Byte(uuid, 4)); /* ee - at offset 05 */
> >>> ...
> >>>
> >>>
> >>
> >> So about the implementation of this macro, I think I'd like to use
> >> following approach. This lets Hex2Byte do what it should only do and
> >> still has a clear look of UUID. What do you think about?
> >>
> >> static uint8_t Hex2Byte(char *src)
> >> {
> >> int hi = Hex2Digit(*src++);
> >> int lo = Hex2Digit(*src);
> >>
> >> if ((hi < 0) || (lo < 0))
> >> return -1;
> > just make Hex2Digit() assert on wrong input.
> >
>
> Ok.
>
> >>
> >> return (hi << 4) | lo;
> >> }
> >>
> >> g_assert((strlen(uuid) == 36) && (uuid[8] == '-') && (uuid[13] == '-')
> >> && (uuid[18] == '-') && (uuid[23] == '-'));
> >>
> >> build_append_byte(var->buf, Hex2Byte(uuid + (3 * 2))); /* dd */
> > ^^^^^
> > I'd make it one number, instead of forcing reader to do math
> > every time he/she looks at this code.
> >
>
> Ok, will do this. And about other patches in this series could you offer
> your comments?
the rest of AML patches looks good, I'll give them RB on next respin.
>
> Thanks,
> Shannon
>
> >
> >> build_append_byte(var->buf, Hex2Byte(uuid + (2 * 2))); /* cc */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (1 * 2))); /* bb */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (0 * 2))); /* aa */
> >>
> >> build_append_byte(var->buf, Hex2Byte(uuid + (5 * 2 + 1))); /* ff */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (4 * 2 + 1))); /* ee */
> >>
> >> build_append_byte(var->buf, Hex2Byte(uuid + (7 * 2 + 2))); /* hh */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (6 * 2 + 2))); /* gg */
> >>
> >> build_append_byte(var->buf, Hex2Byte(uuid + (8 * 2 + 3))); /* ii */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (9 * 2 + 3))); /* jj */
> >>
> >> build_append_byte(var->buf, Hex2Byte(uuid + (10 * 2 + 4))); /* kk */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (11 * 2 + 4))); /* ll */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (12 * 2 + 4))); /* mm */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (13 * 2 + 4))); /* nn */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (14 * 2 + 4))); /* oo */
> >> build_append_byte(var->buf, Hex2Byte(uuid + (15 * 2 + 4))); /* pp */
> >
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-05-04 9:58 ` Igor Mammedov
@ 2015-05-04 11:11 ` Shannon Zhao
2015-05-04 13:04 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-05-04 11:11 UTC (permalink / raw)
To: Igor Mammedov, Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall
On 2015/5/4 17:58, Igor Mammedov wrote:
> On Wed, 15 Apr 2015 21:24:55 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> DSDT consists of the usual common table header plus a definition
>> block in AML encoding which describes all devices in the platform.
>>
>> After initializing DSDT with header information the namespace is
>> created which is followed by the device encodings. The devices are
>> described using the Resource Template for the 32-Bit Fixed Memory
>> Range and the Extended Interrupt Descriptors.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 128 insertions(+)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index c5a3cf9..d044880 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -50,6 +50,130 @@
>> #include "qom/qom-qobject.h"
>> #include "exec/ram_addr.h"
>>
>> +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
>> +{
>> + uint16_t i;
>> +
>> + for (i = 0; i < max_cpus; i++) {
>> + Aml *dev = aml_device("C%03x", i);
>> + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
>> + Aml *crs = aml_resource_template();
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> + }
>> +}
> Is maxcpus a correct here? Usually maxcpus includes non present CPUs
> as well but there is no STA method that tells whether it's present or not.
>
5.2.12.14 GICC Structure
"In the GICC interrupt model, logical processors are required to have a
Processor Device object in the DSDT"
Here we create Processor Device object for all possible CPUs and in MADT
the gicc->flags tells whether it's present or not. And this flags is for
kernel booting initialization, not for dynamic configuration.
BTW, ARM doesn't support vCPU hotplug now. If we want to support hotplug
later, we should add _STA method for each Processor.
>> +
>> +static void acpi_dsdt_add_uart(Aml *scope, const MemMap *uart_memmap,
>> + const int *uart_irq)
>> +{
>> + Aml *dev = aml_device("COM0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + Aml *crs = aml_resource_template();
>> + aml_append(crs, aml_memory32_fixed(uart_memmap->addr,
>> + uart_memmap->size, aml_ReadWrite));
>> + aml_append(crs,
>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>> + aml_exclusive, aml_not_wake_capable, *uart_irq + 32));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_rtc(Aml *scope, const MemMap *rtc_memmap,
>> + const int *rtc_irq)
>> +{
>> + Aml *dev = aml_device("RTC0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + Aml *crs = aml_resource_template();
>> + aml_append(crs, aml_memory32_fixed(rtc_memmap->addr,
>> + rtc_memmap->size, aml_ReadWrite));
>> + aml_append(crs,
>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>> + aml_exclusive, aml_not_wake_capable, *rtc_irq + 32));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_flash(Aml *scope, const MemMap *flash_memmap)
>> +{
>> + Aml *dev, *crs;
>> + hwaddr base = flash_memmap->addr;
>> + hwaddr size = flash_memmap->size;
>> +
>> + dev = aml_device("FLS0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + crs = aml_resource_template();
>> + aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +
>> + dev = aml_device("FLS1");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
>> + crs = aml_resource_template();
>> + aml_append(crs, aml_memory32_fixed(base + size, size, aml_ReadWrite));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
>> + const int *mmio_irq, int num)
>> +{
>> + hwaddr base = virtio_mmio_memmap->addr;
>> + hwaddr size = virtio_mmio_memmap->size;
>> + int irq = *mmio_irq + 32;
>> + int i;
>> +
>> + for (i = 0; i < num; i++) {
>> + Aml *dev = aml_device("VR%02u", i);
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
>> +
>> + Aml *crs = aml_resource_template();
>> + aml_append(crs, aml_memory32_fixed(base, size, aml_ReadWrite));
>> + aml_append(crs,
>> + aml_interrupt(aml_consumer, aml_level, aml_active_high,
>> + aml_exclusive, aml_not_wake_capable, irq + i));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> + base += size;
>> + }
>> +}
>> +
>> +/* DSDT */
>> +static void
>> +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> +{
>> + Aml *scope, *dsdt;
>> + AcpiDsdtInfo *info = guest_info->dsdt_info;
>> +
>> + dsdt = init_aml_allocator();
>> + /* Reserve space for header */
>> + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
>> +
>> + scope = aml_scope("\\_SB");
>> + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
>> + acpi_dsdt_add_uart(scope, info->uart_memmap, info->uart_irq);
>> + acpi_dsdt_add_rtc(scope, info->rtc_memmap, info->rtc_irq);
>> + acpi_dsdt_add_flash(scope, info->flash_memmap);
>> + acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
>> + info->virtio_mmio_irq, info->virtio_mmio_num);
>> + aml_append(dsdt, scope);
>> +
>> + /* copy AML table into ACPI tables blob and patch header there */
>> + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
>> + build_header(linker, table_data,
>> + (void *)(table_data->data + table_data->len - dsdt->buf->len),
>> + "DSDT", dsdt->buf->len, 1);
> shouldn't revision be 5?
>
Thanks, will fix.
>> + free_aml_allocator();
>> +}
>> +
>> typedef
>> struct AcpiBuildState {
>> /* Copy of table in RAM (for patching). */
>> @@ -65,6 +189,7 @@ static
>> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> {
>> GArray *table_offsets;
>> + GArray *tables_blob = tables->table_data;
>>
>> table_offsets = g_array_new(false, true /* clear */,
>> sizeof(uint32_t));
>> @@ -82,6 +207,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> * DSDT
>> */
>>
>> + /* DSDT is pointed to by FADT */
>> + build_dsdt(tables_blob, tables->linker, guest_info);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table
2015-05-04 10:21 ` Igor Mammedov
@ 2015-05-04 11:16 ` Shannon Zhao
0 siblings, 0 replies; 56+ messages in thread
From: Shannon Zhao @ 2015-05-04 11:16 UTC (permalink / raw)
To: Igor Mammedov, Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall
On 2015/5/4 18:21, Igor Mammedov wrote:
> On Wed, 15 Apr 2015 21:24:57 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> MADT describes GIC enabled ARM platforms. The GICC and GICD
>> subtables are used to define the GIC regions.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++-
>> include/hw/arm/virt-acpi-build.h | 2 ++
>> 3 files changed, 100 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index c72a9c8..94cced0 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -50,6 +50,20 @@
>> #include "qom/qom-qobject.h"
>> #include "exec/ram_addr.h"
>>
>> +typedef struct VirtAcpiCpuInfo {
>> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
>> +} VirtAcpiCpuInfo;
>> +
>> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
>> +{
>> + CPUState *cpu;
>> +
>> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
>> + CPU_FOREACH(cpu) {
>> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
>> + }
>> +}
>> +
>> static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
>> {
>> uint16_t i;
>> @@ -146,6 +160,47 @@ static void acpi_dsdt_add_virtio(Aml *scope, const MemMap *virtio_mmio_memmap,
>> }
>> }
>>
>> +/* MADT */
>> +static void
>> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
>> + VirtAcpiCpuInfo *cpuinfo)
>> +{
>> + int madt_start = table_data->len;
>> + const struct AcpiMadtInfo *info = guest_info->madt_info;
>> + AcpiMultipleApicTable *madt;
>> + AcpiMadtGenericDistributor *gicd;
>> + int i;
>> +
>> + madt = acpi_data_push(table_data, sizeof *madt);
>> + madt->local_apic_address = info->gic_cpu_memmap->addr;
> should be safe to drop this since OSPM must ignore this field if
> gicc provides base_address.
>
Ok.
>> + madt->flags = cpu_to_le32(1);
> is it correct?
> Looking at 5.1 spec it's x86 specific PCAT_COMPAT flag,
> why do you use it for ARM?
>
Oh, will fix. Thanks.
>> +
>> + for (i = 0; i < guest_info->max_cpus; i++) {
>> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
>> + sizeof *gicc);
>> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
>> + gicc->length = sizeof(*gicc);
>> + gicc->base_address = info->gic_cpu_memmap->addr;
>> + gicc->cpu_interface_number = i;
>> + gicc->arm_mpidr = i;
>> + gicc->uid = i;
>> + if (test_bit(i, cpuinfo->found_cpus)) {
>> + gicc->flags = cpu_to_le32(1);
> #define ACPI_GICC_ENABLED 1
>
>> + } else {
>> + gicc->flags = cpu_to_le32(0);
>> + }
> not necessary else clause, field is zeroed by default.
>
Ok, will remove.
>> + }
>> +
>> + gicd = acpi_data_push(table_data, sizeof *gicd);
>> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
>> + gicd->length = sizeof(*gicd);
>> + gicd->base_address = info->gic_dist_memmap->addr;
>> +
>> + build_header(linker, table_data,
>> + (void *)(table_data->data + madt_start), "APIC",
>> + table_data->len - madt_start, 1);
> wrong revision?
>
Thanks, will fix this including other patches.
>> +}
>> +
>> /* FADT */
>> static void
>> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
>> @@ -215,8 +270,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> {
>> GArray *table_offsets;
>> unsigned dsdt;
>> + VirtAcpiCpuInfo cpuinfo;
>> GArray *tables_blob = tables->table_data;
>>
>> + virt_acpi_get_cpu_info(&cpuinfo);
>> +
>> table_offsets = g_array_new(false, true /* clear */,
>> sizeof(uint32_t));
>>
>> @@ -241,6 +299,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> acpi_add_table(table_offsets, tables_blob);
>> build_fadt(tables_blob, tables->linker, dsdt);
>>
>> + acpi_add_table(table_offsets, tables_blob);
>> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>> index bac981d..4092dc3 100644
>> --- a/include/hw/acpi/acpi-defs.h
>> +++ b/include/hw/acpi/acpi-defs.h
>> @@ -236,7 +236,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>> #define ACPI_APIC_IO_SAPIC 6
>> #define ACPI_APIC_LOCAL_SAPIC 7
>> #define ACPI_APIC_XRUPT_SOURCE 8
>> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
>> +#define ACPI_APIC_LOCAL_X2APIC 9
>> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
>> +#define ACPI_APIC_GENERIC_INTERRUPT 11
>> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
>> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>>
>> /*
>> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>> @@ -284,6 +290,36 @@ struct AcpiMadtLocalNmi {
>> } QEMU_PACKED;
>> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>>
>> +struct AcpiMadtGenericInterrupt {
>> + ACPI_SUB_HEADER_DEF
>> + uint16_t reserved;
>> + uint32_t cpu_interface_number;
>> + uint32_t uid;
>> + uint32_t flags;
>> + uint32_t parking_version;
>> + uint32_t performance_interrupt;
>> + uint64_t parked_address;
>> + uint64_t base_address;
>> + uint64_t gicv_base_address;
>> + uint64_t gich_base_address;
>> + uint32_t vgic_interrupt;
>> + uint64_t gicr_base_address;
>> + uint64_t arm_mpidr;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
>> +
>> +struct AcpiMadtGenericDistributor {
>> + ACPI_SUB_HEADER_DEF
>> + uint16_t reserved;
>> + uint32_t gic_id;
>> + uint64_t base_address;
>> + uint32_t global_irq_base;
>> + uint32_t reserved2;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
>> +
>> /*
>> * HPET Description Table
>> */
>> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
>> index ece67a2..8f0b4a7 100644
>> --- a/include/hw/arm/virt-acpi-build.h
>> +++ b/include/hw/arm/virt-acpi-build.h
>> @@ -22,6 +22,8 @@
>>
>> #include "qemu-common.h"
>>
>> +#define VIRT_ACPI_CPU_ID_LIMIT 8
>> +
>> typedef struct MemMap {
>> hwaddr addr;
>> hwaddr size;
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-05-04 11:11 ` Shannon Zhao
@ 2015-05-04 13:04 ` Igor Mammedov
0 siblings, 0 replies; 56+ messages in thread
From: Igor Mammedov @ 2015-05-04 13:04 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall
On Mon, 04 May 2015 19:11:39 +0800
Shannon Zhao <shannon.zhao@linaro.org> wrote:
>
>
> On 2015/5/4 17:58, Igor Mammedov wrote:
> > On Wed, 15 Apr 2015 21:24:55 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>
> >> DSDT consists of the usual common table header plus a definition
> >> block in AML encoding which describes all devices in the platform.
> >>
> >> After initializing DSDT with header information the namespace is
> >> created which is followed by the device encodings. The devices are
> >> described using the Resource Template for the 32-Bit Fixed Memory
> >> Range and the Extended Interrupt Descriptors.
> >>
> >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> ---
> >> hw/arm/virt-acpi-build.c | 128
> >> +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed,
> >> 128 insertions(+)
> >>
> >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> >> index c5a3cf9..d044880 100644
> >> --- a/hw/arm/virt-acpi-build.c
> >> +++ b/hw/arm/virt-acpi-build.c
> >> @@ -50,6 +50,130 @@
> >> #include "qom/qom-qobject.h"
> >> #include "exec/ram_addr.h"
> >>
> >> +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> >> +{
> >> + uint16_t i;
> >> +
> >> + for (i = 0; i < max_cpus; i++) {
> >> + Aml *dev = aml_device("C%03x", i);
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("ACPI0007")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> >> + Aml *crs = aml_resource_template();
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> + }
> >> +}
> > Is maxcpus a correct here? Usually maxcpus includes non present CPUs
> > as well but there is no STA method that tells whether it's present
> > or not.
> >
> 5.2.12.14 GICC Structure
> "In the GICC interrupt model, logical processors are required to have
> a Processor Device object in the DSDT"
>
> Here we create Processor Device object for all possible CPUs and in
> MADT the gicc->flags tells whether it's present or not. And this
> flags is for kernel booting initialization, not for dynamic
> configuration.
>
> BTW, ARM doesn't support vCPU hotplug now. If we want to support
> hotplug later, we should add _STA method for each Processor.
lack of _STA in current code implicitly means present, while flag
in MADT could say not present.
Since currently cpu hotplug is not supported for ARM,
pls use smp_cpus instead of max_cpus and create only device objects
and MADT entries only for present CPUs.
>
> >> +
> >> +static void acpi_dsdt_add_uart(Aml *scope, const MemMap
> >> *uart_memmap,
> >> + const int *uart_irq)
> >> +{
> >> + Aml *dev = aml_device("COM0");
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("ARMH0011")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> >> +
> >> + Aml *crs = aml_resource_template();
> >> + aml_append(crs, aml_memory32_fixed(uart_memmap->addr,
> >> + uart_memmap->size,
> >> aml_ReadWrite));
> >> + aml_append(crs,
> >> + aml_interrupt(aml_consumer, aml_level,
> >> aml_active_high,
> >> + aml_exclusive, aml_not_wake_capable, *uart_irq +
> >> 32));
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> +}
> >> +
> >> +static void acpi_dsdt_add_rtc(Aml *scope, const MemMap
> >> *rtc_memmap,
> >> + const int *rtc_irq)
> >> +{
> >> + Aml *dev = aml_device("RTC0");
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("LNRO0013")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> >> +
> >> + Aml *crs = aml_resource_template();
> >> + aml_append(crs, aml_memory32_fixed(rtc_memmap->addr,
> >> + rtc_memmap->size,
> >> aml_ReadWrite));
> >> + aml_append(crs,
> >> + aml_interrupt(aml_consumer, aml_level,
> >> aml_active_high,
> >> + aml_exclusive, aml_not_wake_capable, *rtc_irq +
> >> 32));
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> +}
> >> +
> >> +static void acpi_dsdt_add_flash(Aml *scope, const MemMap
> >> *flash_memmap) +{
> >> + Aml *dev, *crs;
> >> + hwaddr base = flash_memmap->addr;
> >> + hwaddr size = flash_memmap->size;
> >> +
> >> + dev = aml_device("FLS0");
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("LNRO0015")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> >> +
> >> + crs = aml_resource_template();
> >> + aml_append(crs, aml_memory32_fixed(base, size,
> >> aml_ReadWrite));
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> +
> >> + dev = aml_device("FLS1");
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("LNRO0015")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
> >> + crs = aml_resource_template();
> >> + aml_append(crs, aml_memory32_fixed(base + size, size,
> >> aml_ReadWrite));
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> +}
> >> +
> >> +static void acpi_dsdt_add_virtio(Aml *scope, const MemMap
> >> *virtio_mmio_memmap,
> >> + const int *mmio_irq,
> >> int num) +{
> >> + hwaddr base = virtio_mmio_memmap->addr;
> >> + hwaddr size = virtio_mmio_memmap->size;
> >> + int irq = *mmio_irq + 32;
> >> + int i;
> >> +
> >> + for (i = 0; i < num; i++) {
> >> + Aml *dev = aml_device("VR%02u", i);
> >> + aml_append(dev, aml_name_decl("_HID",
> >> aml_string("LNRO0005")));
> >> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> >> +
> >> + Aml *crs = aml_resource_template();
> >> + aml_append(crs, aml_memory32_fixed(base, size,
> >> aml_ReadWrite));
> >> + aml_append(crs,
> >> + aml_interrupt(aml_consumer, aml_level,
> >> aml_active_high,
> >> + aml_exclusive, aml_not_wake_capable, irq + i));
> >> + aml_append(dev, aml_name_decl("_CRS", crs));
> >> + aml_append(scope, dev);
> >> + base += size;
> >> + }
> >> +}
> >> +
> >> +/* DSDT */
> >> +static void
> >> +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo
> >> *guest_info) +{
> >> + Aml *scope, *dsdt;
> >> + AcpiDsdtInfo *info = guest_info->dsdt_info;
> >> +
> >> + dsdt = init_aml_allocator();
> >> + /* Reserve space for header */
> >> + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
> >> +
> >> + scope = aml_scope("\\_SB");
> >> + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
> >> + acpi_dsdt_add_uart(scope, info->uart_memmap, info->uart_irq);
> >> + acpi_dsdt_add_rtc(scope, info->rtc_memmap, info->rtc_irq);
> >> + acpi_dsdt_add_flash(scope, info->flash_memmap);
> >> + acpi_dsdt_add_virtio(scope, info->virtio_mmio_memmap,
> >> + info->virtio_mmio_irq, info->virtio_mmio_num);
> >> + aml_append(dsdt, scope);
> >> +
> >> + /* copy AML table into ACPI tables blob and patch header
> >> there */
> >> + g_array_append_vals(table_data, dsdt->buf->data,
> >> dsdt->buf->len);
> >> + build_header(linker, table_data,
> >> + (void *)(table_data->data + table_data->len -
> >> dsdt->buf->len),
> >> + "DSDT", dsdt->buf->len, 1);
> > shouldn't revision be 5?
> >
>
> Thanks, will fix.
>
> >> + free_aml_allocator();
> >> +}
> >> +
> >> typedef
> >> struct AcpiBuildState {
> >> /* Copy of table in RAM (for patching). */
> >> @@ -65,6 +189,7 @@ static
> >> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables
> >> *tables) {
> >> GArray *table_offsets;
> >> + GArray *tables_blob = tables->table_data;
> >>
> >> table_offsets = g_array_new(false, true /* clear */,
> >> sizeof(uint32_t));
> >> @@ -82,6 +207,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info,
> >> AcpiBuildTables *tables)
> >> * DSDT
> >> */
> >>
> >> + /* DSDT is pointed to by FADT */
> >> + build_dsdt(tables_blob, tables->linker, guest_info);
> >> +
> >> /* Cleanup memory that's no longer used. */
> >> g_array_free(table_offsets, true);
> >> }
> >
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
@ 2015-05-05 2:45 ` Shannon Zhao
2015-05-05 8:26 ` Igor Mammedov
0 siblings, 1 reply; 56+ messages in thread
From: Shannon Zhao @ 2015-05-05 2:45 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, peter.huangpeng, shannon.zhao
On 2015/4/15 21:25, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/acpi/aml-build.c | 9 +++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index cd4ffe2..139099f 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -608,6 +608,15 @@ Aml *aml_irq_no_flags(uint8_t irq)
> return var;
> }
>
> +/* ACPI 1.0: 16.2.3 Operators: DefLNot */
> +Aml *aml_not(Aml *arg)
> +{
> + Aml *var = aml_opcode(0x92 /* LNotOp */);
> + aml_append(var, arg);
> + build_append_int(var->buf, 0x00); /* NullNameOp */
This is not necessary to append 0, will remove it at next version.
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
> Aml *aml_equal(Aml *arg1, Aml *arg2)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 61c1a03..08b3fbd 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -224,6 +224,7 @@ Aml *aml_named_field(const char *name, unsigned length);
> Aml *aml_reserved_field(unsigned length);
> Aml *aml_local(int num);
> Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> +Aml *aml_not(Aml *arg);
> Aml *aml_equal(Aml *arg1, Aml *arg2);
> Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
> const char *name_format, ...) GCC_FMT_ATTR(4, 5);
>
--
Shannon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term
2015-05-05 2:45 ` Shannon Zhao
@ 2015-05-05 8:26 ` Igor Mammedov
0 siblings, 0 replies; 56+ messages in thread
From: Igor Mammedov @ 2015-05-05 8:26 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Tue, 5 May 2015 10:45:06 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/15 21:25, Shannon Zhao wrote:
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> > Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> > ---
> > hw/acpi/aml-build.c | 9 +++++++++
> > include/hw/acpi/aml-build.h | 1 +
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > index cd4ffe2..139099f 100644
> > --- a/hw/acpi/aml-build.c
> > +++ b/hw/acpi/aml-build.c
> > @@ -608,6 +608,15 @@ Aml *aml_irq_no_flags(uint8_t irq)
> > return var;
> > }
> >
> > +/* ACPI 1.0: 16.2.3 Operators: DefLNot */
> > +Aml *aml_not(Aml *arg)
> > +{
> > + Aml *var = aml_opcode(0x92 /* LNotOp */);
> > + aml_append(var, arg);
> > + build_append_int(var->buf, 0x00); /* NullNameOp */
>
> This is not necessary to append 0, will remove it at next version.
also make it aml_lnot()
>
> > + return var;
> > +}
> > +
> > /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
> > Aml *aml_equal(Aml *arg1, Aml *arg2)
> > {
> > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> > index 61c1a03..08b3fbd 100644
> > --- a/include/hw/acpi/aml-build.h
> > +++ b/include/hw/acpi/aml-build.h
> > @@ -224,6 +224,7 @@ Aml *aml_named_field(const char *name, unsigned length);
> > Aml *aml_reserved_field(unsigned length);
> > Aml *aml_local(int num);
> > Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> > +Aml *aml_not(Aml *arg);
> > Aml *aml_equal(Aml *arg1, Aml *arg2);
> > Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
> > const char *name_format, ...) GCC_FMT_ATTR(4, 5);
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2015-05-05 8:27 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-15 13:24 [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
2015-05-04 9:58 ` Igor Mammedov
2015-05-04 11:11 ` Shannon Zhao
2015-05-04 13:04 ` Igor Mammedov
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
2015-05-04 10:21 ` Igor Mammedov
2015-05-04 11:16 ` Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
2015-04-15 13:24 ` [Qemu-devel] [PATCH v5 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
2015-04-28 6:54 ` Igor Mammedov
2015-04-28 7:46 ` Shannon Zhao
2015-04-28 8:15 ` Igor Mammedov
2015-04-28 8:52 ` Shannon Zhao
2015-04-28 9:35 ` Igor Mammedov
2015-04-28 9:48 ` Shannon Zhao
2015-04-29 13:41 ` Shannon Zhao
2015-05-04 9:22 ` Igor Mammedov
2015-05-04 9:30 ` Shannon Zhao
2015-05-04 10:53 ` Igor Mammedov
2015-04-28 8:08 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
2015-04-28 6:56 ` Igor Mammedov
2015-04-28 7:12 ` Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
2015-05-05 2:45 ` Shannon Zhao
2015-05-05 8:26 ` Igor Mammedov
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
2015-04-28 8:42 ` Igor Mammedov
2015-04-28 8:47 ` Michael S. Tsirkin
2015-04-28 9:06 ` Shannon Zhao
2015-04-28 9:54 ` Igor Mammedov
2015-04-28 12:57 ` Shannon Zhao
2015-04-28 15:13 ` Igor Mammedov
2015-04-28 15:54 ` Michael S. Tsirkin
2015-04-29 3:12 ` Shannon Zhao
2015-04-29 8:47 ` Igor Mammedov
2015-04-29 13:37 ` Shannon Zhao
2015-04-29 13:58 ` Igor Mammedov
2015-04-15 13:25 ` [Qemu-devel] [PATCH v5 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
2015-04-28 2:49 ` [Qemu-devel] [PATCH v5 00/20] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-04-28 5:20 ` Michael S. Tsirkin
2015-04-28 6:13 ` Shannon Zhao
2015-04-28 6:56 ` Michael S. Tsirkin
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