* [PATCH 0/3] drm/i915/bxt: add workarounds
@ 2015-04-10 12:12 Nick Hoath
2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Nick Hoath @ 2015-04-10 12:12 UTC (permalink / raw)
To: intel-gfx
Add bxt specific workarounds.
Nick Hoath (3):
drm/i915/bxt: Add WaDisableThreadStallDopClockGating
drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing
drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
--
2.1.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating 2015-04-10 12:12 [PATCH 0/3] drm/i915/bxt: add workarounds Nick Hoath @ 2015-04-10 12:12 ` Nick Hoath 2015-04-29 12:16 ` Imre Deak 2015-04-10 12:12 ` [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Nick Hoath 2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath 2 siblings, 1 reply; 15+ messages in thread From: Nick Hoath @ 2015-04-10 12:12 UTC (permalink / raw) To: intel-gfx Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 883e11f..5aad253 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1038,8 +1038,15 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) static int bxt_init_workarounds(struct intel_engine_cs *ring) { + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + gen9_init_workarounds(ring); + /* WaDisableThreadStallDopClockGating:bxt */ + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, + STALL_DOP_GATING_DISABLE); + return 0; } -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating 2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath @ 2015-04-29 12:16 ` Imre Deak 2015-05-04 8:32 ` Daniel Vetter 0 siblings, 1 reply; 15+ messages in thread From: Imre Deak @ 2015-04-29 12:16 UTC (permalink / raw) To: Nick Hoath; +Cc: intel-gfx On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 883e11f..5aad253 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1038,8 +1038,15 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) > > static int bxt_init_workarounds(struct intel_engine_cs *ring) > { > + struct drm_device *dev = ring->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + > gen9_init_workarounds(ring); > > + /* WaDisableThreadStallDopClockGating:bxt */ > + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > + STALL_DOP_GATING_DISABLE); > + > return 0; > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating 2015-04-29 12:16 ` Imre Deak @ 2015-05-04 8:32 ` Daniel Vetter 0 siblings, 0 replies; 15+ messages in thread From: Daniel Vetter @ 2015-05-04 8:32 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Wed, Apr 29, 2015 at 03:16:29PM +0300, Imre Deak wrote: > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > > Reviewed-by: Imre Deak <imre.deak@intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 2015-04-10 12:12 [PATCH 0/3] drm/i915/bxt: add workarounds Nick Hoath 2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath @ 2015-04-10 12:12 ` Nick Hoath 2015-04-29 12:26 ` Imre Deak 2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath 2 siblings, 1 reply; 15+ messages in thread From: Nick Hoath @ 2015-04-10 12:12 UTC (permalink / raw) To: intel-gfx Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 91eef06..d34432b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells { #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 #define GEN7_MAX_PS_THREAD_DEP (8<<12) #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) #define GEN9_HALF_SLICE_CHICKEN5 0xe188 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5aad253..eebee73 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); + /* WaDisableSbeCacheDispatchPortSharing:bxt */ + if (INTEL_REVID(dev) <= BXT_REVID_B0) { + WA_SET_BIT_MASKED( + GEN7_HALF_SLICE_CHICKEN1, + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); + } + return 0; } -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 2015-04-10 12:12 ` [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Nick Hoath @ 2015-04-29 12:26 ` Imre Deak 2015-05-05 14:24 ` Nick Hoath 0 siblings, 1 reply; 15+ messages in thread From: Imre Deak @ 2015-04-29 12:26 UTC (permalink / raw) To: Nick Hoath; +Cc: intel-gfx On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 91eef06..d34432b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells { > #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 > #define GEN7_MAX_PS_THREAD_DEP (8<<12) > #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) > +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) > #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > > #define GEN9_HALF_SLICE_CHICKEN5 0xe188 > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 5aad253..eebee73 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > STALL_DOP_GATING_DISABLE); > > + /* WaDisableSbeCacheDispatchPortSharing:bxt */ > + if (INTEL_REVID(dev) <= BXT_REVID_B0) { > + WA_SET_BIT_MASKED( > + GEN7_HALF_SLICE_CHICKEN1, > + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > + } > + This looks ok, but according to the WA DB it should also be added for SKL (<=F0) in gen9_init_workarounds. > return 0; > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 2015-04-29 12:26 ` Imre Deak @ 2015-05-05 14:24 ` Nick Hoath 2015-05-06 11:51 ` Imre Deak 0 siblings, 1 reply; 15+ messages in thread From: Nick Hoath @ 2015-05-05 14:24 UTC (permalink / raw) To: Deak, Imre; +Cc: intel-gfx On 29/04/2015 13:26, Deak, Imre wrote: > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 91eef06..d34432b 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells { >> #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 >> #define GEN7_MAX_PS_THREAD_DEP (8<<12) >> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) >> +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) >> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) >> >> #define GEN9_HALF_SLICE_CHICKEN5 0xe188 >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index 5aad253..eebee73 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, >> STALL_DOP_GATING_DISABLE); >> >> + /* WaDisableSbeCacheDispatchPortSharing:bxt */ >> + if (INTEL_REVID(dev) <= BXT_REVID_B0) { >> + WA_SET_BIT_MASKED( >> + GEN7_HALF_SLICE_CHICKEN1, >> + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); >> + } >> + > > This looks ok, but according to the WA DB it should also be added for > SKL (<=F0) in gen9_init_workarounds. > That would work against the concept of keeping these patches as bisectable as possible - Enabling these WAs for other SoCs should be done as another patch/patchset. >> return 0; >> } >> > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 2015-05-05 14:24 ` Nick Hoath @ 2015-05-06 11:51 ` Imre Deak 2015-05-06 14:07 ` Daniel Vetter 0 siblings, 1 reply; 15+ messages in thread From: Imre Deak @ 2015-05-06 11:51 UTC (permalink / raw) To: Nick Hoath; +Cc: intel-gfx On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote: > On 29/04/2015 13:26, Deak, Imre wrote: > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 1 + > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ > >> 2 files changed, 8 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index 91eef06..d34432b 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells { > >> #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 > >> #define GEN7_MAX_PS_THREAD_DEP (8<<12) > >> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) > >> +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) > >> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > >> > >> #define GEN9_HALF_SLICE_CHICKEN5 0xe188 > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> index 5aad253..eebee73 100644 > >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > >> STALL_DOP_GATING_DISABLE); > >> > >> + /* WaDisableSbeCacheDispatchPortSharing:bxt */ > >> + if (INTEL_REVID(dev) <= BXT_REVID_B0) { > >> + WA_SET_BIT_MASKED( > >> + GEN7_HALF_SLICE_CHICKEN1, > >> + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > >> + } > >> + > > > > This looks ok, but according to the WA DB it should also be added for > > SKL (<=F0) in gen9_init_workarounds. > > > > That would work against the concept of keeping these patches as > bisectable as possible - Enabling these WAs for other SoCs should be > done as another patch/patchset. Ok, agreed about bisectability. But it's worth adding a code comment about SKL or at least mention it in the commit log, so we know we have to follow up on it. Also I'd still put this to gen9_init_workarounds with a platform check, since you'll need to move it there anyway and so you could reduce the diff of the follow-up patch. Either way this is: Reviewed-by: Imre Deak <imre.deak@intel.com> > > >> return 0; > >> } > >> > > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing 2015-05-06 11:51 ` Imre Deak @ 2015-05-06 14:07 ` Daniel Vetter 0 siblings, 0 replies; 15+ messages in thread From: Daniel Vetter @ 2015-05-06 14:07 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Wed, May 06, 2015 at 02:51:47PM +0300, Imre Deak wrote: > On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote: > > On 29/04/2015 13:26, Deak, Imre wrote: > > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > > >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > > >> --- > > >> drivers/gpu/drm/i915/i915_reg.h | 1 + > > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ > > >> 2 files changed, 8 insertions(+) > > >> > > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > >> index 91eef06..d34432b 100644 > > >> --- a/drivers/gpu/drm/i915/i915_reg.h > > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > > >> @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells { > > >> #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 > > >> #define GEN7_MAX_PS_THREAD_DEP (8<<12) > > >> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) > > >> +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) > > >> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > > >> > > >> #define GEN9_HALF_SLICE_CHICKEN5 0xe188 > > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> index 5aad253..eebee73 100644 > > >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > > >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > > >> STALL_DOP_GATING_DISABLE); > > >> > > >> + /* WaDisableSbeCacheDispatchPortSharing:bxt */ > > >> + if (INTEL_REVID(dev) <= BXT_REVID_B0) { > > >> + WA_SET_BIT_MASKED( > > >> + GEN7_HALF_SLICE_CHICKEN1, > > >> + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > > >> + } > > >> + > > > > > > This looks ok, but according to the WA DB it should also be added for > > > SKL (<=F0) in gen9_init_workarounds. > > > > > > > That would work against the concept of keeping these patches as > > bisectable as possible - Enabling these WAs for other SoCs should be > > done as another patch/patchset. > > Ok, agreed about bisectability. But it's worth adding a code comment > about SKL or at least mention it in the commit log, so we know we have > to follow up on it. Also I'd still put this to gen9_init_workarounds > with a platform check, since you'll need to move it there anyway and so > you could reduce the diff of the follow-up patch. Either way this is: > > Reviewed-by: Imre Deak <imre.deak@intel.com> Queued for -next, thanks for the patch. Imre, can you please supply the skl versions of these? Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-04-10 12:12 [PATCH 0/3] drm/i915/bxt: add workarounds Nick Hoath 2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath 2015-04-10 12:12 ` [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Nick Hoath @ 2015-04-10 12:12 ` Nick Hoath 2015-04-14 11:39 ` shuang.he 2015-04-29 13:02 ` Imre Deak 2 siblings, 2 replies; 15+ messages in thread From: Nick Hoath @ 2015-04-10 12:12 UTC (permalink / raw) To: intel-gfx Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eebee73..cc62e5c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } + /* WaForceContextSaveRestoreNonCoherent:bxt */ + WA_SET_BIT_MASKED(HDC_CHICKEN0, + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + return 0; } -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath @ 2015-04-14 11:39 ` shuang.he 2015-04-29 13:02 ` Imre Deak 1 sibling, 0 replies; 15+ messages in thread From: shuang.he @ 2015-04-14 11:39 UTC (permalink / raw) To: shuang.he, ethan.gao, intel-gfx, nicholas.hoath Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6173 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB -34 313/313 279/313 IVB 337/337 337/337 BYT 286/286 286/286 HSW 395/395 395/395 BDW 321/321 321/321 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *SNB igt@gem_mmap_gtt@read-no-prefault PASS(5) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_cursor_crc@cursor-size-change DMESG_WARN(5)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@bo-too-big DMESG_WARN(5)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@bo-too-big-interruptible DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip_event_leak DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@nonexisting-fb DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@nonexisting-fb-interruptible DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting *SNB igt@kms_flip_tiling@flip-changes-tiling DMESG_WARN(6)PASS(3) FAIL(1)DMESG_WARN(1) SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@kms_rotation_crc@primary-rotation DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@cursor DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@cursor-dpms DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@debugfs-forcewake-user DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@dpms-non-lpsp DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@drm-resources-equal DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@fences DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@fences-dpms DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@gem-execbuf DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@gem-idle DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@gem-mmap-cpu DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@gem-mmap-gtt DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@gem-pread DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@i2c DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@modeset-non-lpsp DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@pci-d3-state DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@reg-read-ioctl DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting SNB igt@pm_rpm@rte DMESG_WARN(6)PASS(3) DMESG_WARN(2) (dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath 2015-04-14 11:39 ` shuang.he @ 2015-04-29 13:02 ` Imre Deak 2015-05-06 16:01 ` Nick Hoath 1 sibling, 1 reply; 15+ messages in thread From: Imre Deak @ 2015-04-29 13:02 UTC (permalink / raw) To: Nick Hoath; +Cc: intel-gfx On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index eebee73..cc62e5c 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > } > > + /* WaForceContextSaveRestoreNonCoherent:bxt */ > + WA_SET_BIT_MASKED(HDC_CHICKEN0, > + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); > + Looks ok, but again it needs to be added for SKL (all steppings) in gen9_init_workarounds. > return 0; > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-04-29 13:02 ` Imre Deak @ 2015-05-06 16:01 ` Nick Hoath 2015-05-06 16:32 ` Imre Deak 0 siblings, 1 reply; 15+ messages in thread From: Nick Hoath @ 2015-05-06 16:01 UTC (permalink / raw) To: Deak, Imre; +Cc: intel-gfx On 29/04/2015 14:02, Deak, Imre wrote: > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> >> --- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index eebee73..cc62e5c 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) >> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); >> } >> >> + /* WaForceContextSaveRestoreNonCoherent:bxt */ >> + WA_SET_BIT_MASKED(HDC_CHICKEN0, >> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); >> + > > Looks ok, but again it needs to be added for SKL (all steppings) in > gen9_init_workarounds. The same argument as for patch 2/3 applies? > >> return 0; >> } >> > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-05-06 16:01 ` Nick Hoath @ 2015-05-06 16:32 ` Imre Deak 2015-05-07 6:39 ` Daniel Vetter 0 siblings, 1 reply; 15+ messages in thread From: Imre Deak @ 2015-05-06 16:32 UTC (permalink / raw) To: Nick Hoath; +Cc: intel-gfx On Wed, 2015-05-06 at 17:01 +0100, Nick Hoath wrote: > On 29/04/2015 14:02, Deak, Imre wrote: > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > >> --- > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> index eebee73..cc62e5c 100644 > >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > >> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > >> } > >> > >> + /* WaForceContextSaveRestoreNonCoherent:bxt */ > >> + WA_SET_BIT_MASKED(HDC_CHICKEN0, > >> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); > >> + > > > > Looks ok, but again it needs to be added for SKL (all steppings) in > > gen9_init_workarounds. > > The same argument as for patch 2/3 applies? Yes, applying this on SKL as a follow up is ok: Reviewed-by: Imre Deak <imre.deak@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent 2015-05-06 16:32 ` Imre Deak @ 2015-05-07 6:39 ` Daniel Vetter 0 siblings, 0 replies; 15+ messages in thread From: Daniel Vetter @ 2015-05-07 6:39 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Wed, May 06, 2015 at 07:32:08PM +0300, Imre Deak wrote: > On Wed, 2015-05-06 at 17:01 +0100, Nick Hoath wrote: > > On 29/04/2015 14:02, Deak, Imre wrote: > > > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote: > > >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > > >> --- > > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > > >> 1 file changed, 5 insertions(+) > > >> > > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> index eebee73..cc62e5c 100644 > > >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> @@ -1054,6 +1054,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > > >> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > > >> } > > >> > > >> + /* WaForceContextSaveRestoreNonCoherent:bxt */ > > >> + WA_SET_BIT_MASKED(HDC_CHICKEN0, > > >> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); > > >> + > > > > > > Looks ok, but again it needs to be added for SKL (all steppings) in > > > gen9_init_workarounds. > > > > The same argument as for patch 2/3 applies? > > Yes, applying this on SKL as a follow up is ok: > > Reviewed-by: Imre Deak <imre.deak@intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-05-07 6:37 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-04-10 12:12 [PATCH 0/3] drm/i915/bxt: add workarounds Nick Hoath 2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath 2015-04-29 12:16 ` Imre Deak 2015-05-04 8:32 ` Daniel Vetter 2015-04-10 12:12 ` [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Nick Hoath 2015-04-29 12:26 ` Imre Deak 2015-05-05 14:24 ` Nick Hoath 2015-05-06 11:51 ` Imre Deak 2015-05-06 14:07 ` Daniel Vetter 2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath 2015-04-14 11:39 ` shuang.he 2015-04-29 13:02 ` Imre Deak 2015-05-06 16:01 ` Nick Hoath 2015-05-06 16:32 ` Imre Deak 2015-05-07 6:39 ` Daniel Vetter
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