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* [PATCH 0/9] MIPS: dump_tlb improvements
@ 2015-05-13 10:50 ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, Steven J. Hill, David Daney

This patchset improves dump_tlb.c to use proper hazard macros (for which
new macros are added for tlb reads), and to take into account the global
bit, the EHINV invalid bit, RI & XI bits, and XPA.

Patch 1 also adds a MIPS specific SysRq operation ('x') to dump the TLBs
on running CPUs. This is mainly for debug purposes, however I've
included it for completeness as an RFC patch, in case others find it
helpful.

Patches 2 & 3 add and make use of tlbr related hazard macros (which are
technically distinct, though identically implemented, to tlbw hazards).

Patches 4-6 improve the TLB entry matching so as to more closely match
which entries hardware treats as matching (taking the global and EHINV
bits into account).

Patches 7-8 improve the TLB printing to handle RI & XI bits (which show
up in the physical address at the moment), and XPA (where the top of the
physical address needs to be read from EntryLo registers with mfhc0).

Finally patch 9 is a trivial correction in a comment, that I noticed
while grepping around for XPA bits.

James Hogan (9):
  MIPS: Add SysRq operation to dump TLBs on all CPUs
  MIPS: hazards: Add hazard macros for tlb read
  MIPS: dump_tlb: Use tlbr hazard macros
  MIPS: dump_tlb: Refactor TLB matching
  MIPS: dump_tlb: Take global bit into account
  MIPS: dump_tlb: Take EHINV bit into account
  MIPS: dump_tlb: Take RI/XI bits into account
  MIPS: dump_tlb: Take XPA into account
  MIPS: tlb-r4k: Fix PG_ELPA comment

 arch/mips/include/asm/hazards.h  |  52 ++++++++++++++++++++
 arch/mips/include/asm/mipsregs.h |  11 +++++
 arch/mips/kernel/Makefile        |   1 +
 arch/mips/kernel/sysrq.c         |  77 +++++++++++++++++++++++++++++
 arch/mips/lib/dump_tlb.c         | 103 ++++++++++++++++++++++++---------------
 arch/mips/mm/tlb-r4k.c           |   2 +-
 drivers/tty/sysrq.c              |   1 +
 7 files changed, 207 insertions(+), 40 deletions(-)
 create mode 100644 arch/mips/kernel/sysrq.c

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
-- 
2.3.6

^ permalink raw reply	[flat|nested] 33+ messages in thread
* [PATCH 0/9] MIPS: dump_tlb improvements
@ 2015-05-13 10:50 ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, Steven J. Hill, David Daney

This patchset improves dump_tlb.c to use proper hazard macros (for which
new macros are added for tlb reads), and to take into account the global
bit, the EHINV invalid bit, RI & XI bits, and XPA.

Patch 1 also adds a MIPS specific SysRq operation ('x') to dump the TLBs
on running CPUs. This is mainly for debug purposes, however I've
included it for completeness as an RFC patch, in case others find it
helpful.

Patches 2 & 3 add and make use of tlbr related hazard macros (which are
technically distinct, though identically implemented, to tlbw hazards).

Patches 4-6 improve the TLB entry matching so as to more closely match
which entries hardware treats as matching (taking the global and EHINV
bits into account).

Patches 7-8 improve the TLB printing to handle RI & XI bits (which show
up in the physical address at the moment), and XPA (where the top of the
physical address needs to be read from EntryLo registers with mfhc0).

Finally patch 9 is a trivial correction in a comment, that I noticed
while grepping around for XPA bits.

James Hogan (9):
  MIPS: Add SysRq operation to dump TLBs on all CPUs
  MIPS: hazards: Add hazard macros for tlb read
  MIPS: dump_tlb: Use tlbr hazard macros
  MIPS: dump_tlb: Refactor TLB matching
  MIPS: dump_tlb: Take global bit into account
  MIPS: dump_tlb: Take EHINV bit into account
  MIPS: dump_tlb: Take RI/XI bits into account
  MIPS: dump_tlb: Take XPA into account
  MIPS: tlb-r4k: Fix PG_ELPA comment

 arch/mips/include/asm/hazards.h  |  52 ++++++++++++++++++++
 arch/mips/include/asm/mipsregs.h |  11 +++++
 arch/mips/kernel/Makefile        |   1 +
 arch/mips/kernel/sysrq.c         |  77 +++++++++++++++++++++++++++++
 arch/mips/lib/dump_tlb.c         | 103 ++++++++++++++++++++++++---------------
 arch/mips/mm/tlb-r4k.c           |   2 +-
 drivers/tty/sysrq.c              |   1 +
 7 files changed, 207 insertions(+), 40 deletions(-)
 create mode 100644 arch/mips/kernel/sysrq.c

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
-- 
2.3.6

^ permalink raw reply	[flat|nested] 33+ messages in thread
* [PATCH RFC 1/9] MIPS: Add SysRq operation to dump TLBs on all CPUs
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
using the 'x' trigger key.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
This was mainly for debug purposes, however I've included it for
completeness as an RFC patch, in case others find it helpful.
---
 arch/mips/kernel/Makefile |  1 +
 arch/mips/kernel/sysrq.c  | 77 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/tty/sysrq.c       |  1 +
 3 files changed, 79 insertions(+)
 create mode 100644 arch/mips/kernel/sysrq.c

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d3d2ff2d76dc..a2debcbedb6d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_MIPS32_O32)	+= binfmt_elfo32.o scall64-o32.o
 
 obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_PROC_FS)		+= proc.o
+obj-$(CONFIG_MAGIC_SYSRQ)	+= sysrq.o
 
 obj-$(CONFIG_64BIT)		+= cpu-bugs64.o
 
diff --git a/arch/mips/kernel/sysrq.c b/arch/mips/kernel/sysrq.c
new file mode 100644
index 000000000000..5b539f5fc9d9
--- /dev/null
+++ b/arch/mips/kernel/sysrq.c
@@ -0,0 +1,77 @@
+/*
+ * MIPS specific sysrq operations.
+ *
+ * Copyright (C) 2015 Imagination Technologies Ltd.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/sysrq.h>
+#include <linux/workqueue.h>
+
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
+#include <asm/tlbdebug.h>
+
+/*
+ * Dump TLB entries on all CPUs.
+ */
+
+static DEFINE_SPINLOCK(show_lock);
+
+static void sysrq_tlbdump_single(void *dummy)
+{
+	const int field = 2 * sizeof(unsigned long);
+	unsigned long flags;
+
+	spin_lock_irqsave(&show_lock, flags);
+
+	pr_info("CPU%d:\n", smp_processor_id());
+	pr_info("Index	: %0x\n", read_c0_index());
+	pr_info("Pagemask: %0x\n", read_c0_pagemask());
+	pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
+	pr_info("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
+	pr_info("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+	pr_info("Wired   : %0x\n", read_c0_wired());
+	pr_info("Pagegrain: %0x\n", read_c0_pagegrain());
+	if (cpu_has_htw) {
+		pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
+		pr_info("PWSize  : %0*lx\n", field, read_c0_pwsize());
+		pr_info("PWCtl   : %0x\n", read_c0_pwctl());
+	}
+	pr_info("\n");
+	dump_tlb_all();
+	pr_info("\n");
+
+	spin_unlock_irqrestore(&show_lock, flags);
+}
+
+#ifdef CONFIG_SMP
+static void sysrq_tlbdump_othercpus(struct work_struct *dummy)
+{
+	smp_call_function(sysrq_tlbdump_single, NULL, 0);
+}
+
+static DECLARE_WORK(sysrq_tlbdump, sysrq_tlbdump_othercpus);
+#endif
+
+static void sysrq_handle_tlbdump(int key)
+{
+	sysrq_tlbdump_single(NULL);
+#ifdef CONFIG_SMP
+	schedule_work(&sysrq_tlbdump);
+#endif
+}
+
+static struct sysrq_key_op sysrq_tlbdump_op = {
+	.handler        = sysrq_handle_tlbdump,
+	.help_msg       = "show-tlbs(x)",
+	.action_msg     = "Show TLB entries",
+	.enable_mask	= SYSRQ_ENABLE_DUMP,
+};
+
+static int __init mips_sysrq_init(void)
+{
+	return register_sysrq_key('x', &sysrq_tlbdump_op);
+}
+arch_initcall(mips_sysrq_init);
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 843f2cdc280b..8ba52e56bb8b 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -463,6 +463,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
 	/* v: May be registered for frame buffer console restore */
 	NULL,				/* v */
 	&sysrq_showstate_blocked_op,	/* w */
+	/* x: May be registered on mips for TLB dump */
 	/* x: May be registered on ppc/powerpc for xmon */
 	/* x: May be registered on sparc64 for global PMU dump */
 	NULL,				/* x */
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH RFC 1/9] MIPS: Add SysRq operation to dump TLBs on all CPUs
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
using the 'x' trigger key.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
This was mainly for debug purposes, however I've included it for
completeness as an RFC patch, in case others find it helpful.
---
 arch/mips/kernel/Makefile |  1 +
 arch/mips/kernel/sysrq.c  | 77 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/tty/sysrq.c       |  1 +
 3 files changed, 79 insertions(+)
 create mode 100644 arch/mips/kernel/sysrq.c

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d3d2ff2d76dc..a2debcbedb6d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_MIPS32_O32)	+= binfmt_elfo32.o scall64-o32.o
 
 obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_PROC_FS)		+= proc.o
+obj-$(CONFIG_MAGIC_SYSRQ)	+= sysrq.o
 
 obj-$(CONFIG_64BIT)		+= cpu-bugs64.o
 
diff --git a/arch/mips/kernel/sysrq.c b/arch/mips/kernel/sysrq.c
new file mode 100644
index 000000000000..5b539f5fc9d9
--- /dev/null
+++ b/arch/mips/kernel/sysrq.c
@@ -0,0 +1,77 @@
+/*
+ * MIPS specific sysrq operations.
+ *
+ * Copyright (C) 2015 Imagination Technologies Ltd.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/sysrq.h>
+#include <linux/workqueue.h>
+
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
+#include <asm/tlbdebug.h>
+
+/*
+ * Dump TLB entries on all CPUs.
+ */
+
+static DEFINE_SPINLOCK(show_lock);
+
+static void sysrq_tlbdump_single(void *dummy)
+{
+	const int field = 2 * sizeof(unsigned long);
+	unsigned long flags;
+
+	spin_lock_irqsave(&show_lock, flags);
+
+	pr_info("CPU%d:\n", smp_processor_id());
+	pr_info("Index	: %0x\n", read_c0_index());
+	pr_info("Pagemask: %0x\n", read_c0_pagemask());
+	pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
+	pr_info("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
+	pr_info("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+	pr_info("Wired   : %0x\n", read_c0_wired());
+	pr_info("Pagegrain: %0x\n", read_c0_pagegrain());
+	if (cpu_has_htw) {
+		pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
+		pr_info("PWSize  : %0*lx\n", field, read_c0_pwsize());
+		pr_info("PWCtl   : %0x\n", read_c0_pwctl());
+	}
+	pr_info("\n");
+	dump_tlb_all();
+	pr_info("\n");
+
+	spin_unlock_irqrestore(&show_lock, flags);
+}
+
+#ifdef CONFIG_SMP
+static void sysrq_tlbdump_othercpus(struct work_struct *dummy)
+{
+	smp_call_function(sysrq_tlbdump_single, NULL, 0);
+}
+
+static DECLARE_WORK(sysrq_tlbdump, sysrq_tlbdump_othercpus);
+#endif
+
+static void sysrq_handle_tlbdump(int key)
+{
+	sysrq_tlbdump_single(NULL);
+#ifdef CONFIG_SMP
+	schedule_work(&sysrq_tlbdump);
+#endif
+}
+
+static struct sysrq_key_op sysrq_tlbdump_op = {
+	.handler        = sysrq_handle_tlbdump,
+	.help_msg       = "show-tlbs(x)",
+	.action_msg     = "Show TLB entries",
+	.enable_mask	= SYSRQ_ENABLE_DUMP,
+};
+
+static int __init mips_sysrq_init(void)
+{
+	return register_sysrq_key('x', &sysrq_tlbdump_op);
+}
+arch_initcall(mips_sysrq_init);
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 843f2cdc280b..8ba52e56bb8b 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -463,6 +463,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
 	/* v: May be registered for frame buffer console restore */
 	NULL,				/* v */
 	&sysrq_showstate_blocked_op,	/* w */
+	/* x: May be registered on mips for TLB dump */
 	/* x: May be registered on ppc/powerpc for xmon */
 	/* x: May be registered on sparc64 for global PMU dump */
 	NULL,				/* x */
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Add hazard macros to <asm/hazards.h> for the following hazards around
tlbr (TLB read) instructions, which are used in TLB dumping code and
some KVM TLB management code:

- mtc0_tlbr_hazard
  Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
  all cases on the assumption that tlbr always has similar data user
  timings to tlbw.

- tlb_read_hazard
  Between tlbr and mfc0 (various TLB registers). This is copied from
  tlbw_use_hazard in all cases on the assumption that tlbr has similar
  data writer characteristics to tlbw, and mfc0 has similar data user
  characteristics to loads and stores.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
and mfc0 had similar data writer timings to loads and stores. Are there
particular other cores that should be checked too?
---
 arch/mips/include/asm/hazards.h | 52 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4087b47ad1cb..7b99efd31074 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -31,9 +31,15 @@
 #define __mtc0_tlbw_hazard						\
 	___ehb
 
+#define __mtc0_tlbr_hazard						\
+	___ehb
+
 #define __tlbw_use_hazard						\
 	___ehb
 
+#define __tlb_read_hazard						\
+	___ehb
+
 #define __tlb_probe_hazard						\
 	___ehb
 
@@ -80,12 +86,23 @@ do {									\
 	___ssnop;							\
 	___ehb
 
+#define __mtc0_tlbr_hazard						\
+	___ssnop;							\
+	___ssnop;							\
+	___ehb
+
 #define __tlbw_use_hazard						\
 	___ssnop;							\
 	___ssnop;							\
 	___ssnop;							\
 	___ehb
 
+#define __tlb_read_hazard						\
+	___ssnop;							\
+	___ssnop;							\
+	___ssnop;							\
+	___ehb
+
 #define __tlb_probe_hazard						\
 	___ssnop;							\
 	___ssnop;							\
@@ -147,8 +164,12 @@ do {									\
 
 #define __mtc0_tlbw_hazard
 
+#define __mtc0_tlbr_hazard
+
 #define __tlbw_use_hazard
 
+#define __tlb_read_hazard
+
 #define __tlb_probe_hazard
 
 #define __irq_enable_hazard
@@ -166,8 +187,12 @@ do {									\
  */
 #define __mtc0_tlbw_hazard
 
+#define __mtc0_tlbr_hazard
+
 #define __tlbw_use_hazard
 
+#define __tlb_read_hazard
+
 #define __tlb_probe_hazard
 
 #define __irq_enable_hazard
@@ -196,11 +221,20 @@ do {									\
 	nop;								\
 	nop
 
+#define __mtc0_tlbr_hazard						\
+	nop;								\
+	nop
+
 #define __tlbw_use_hazard						\
 	nop;								\
 	nop;								\
 	nop
 
+#define __tlb_read_hazard						\
+	nop;								\
+	nop;								\
+	nop
+
 #define __tlb_probe_hazard						\
 	nop;								\
 	nop;								\
@@ -267,7 +301,9 @@ do {									\
 #define _ssnop ___ssnop
 #define	_ehb ___ehb
 #define mtc0_tlbw_hazard __mtc0_tlbw_hazard
+#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
 #define tlbw_use_hazard __tlbw_use_hazard
+#define tlb_read_hazard __tlb_read_hazard
 #define tlb_probe_hazard __tlb_probe_hazard
 #define irq_enable_hazard __irq_enable_hazard
 #define irq_disable_hazard __irq_disable_hazard
@@ -300,6 +336,14 @@ do {									\
 } while (0)
 
 
+#define mtc0_tlbr_hazard()						\
+do {									\
+	__asm__ __volatile__(						\
+	__stringify(__mtc0_tlbr_hazard)					\
+	);								\
+} while (0)
+
+
 #define tlbw_use_hazard()						\
 do {									\
 	__asm__ __volatile__(						\
@@ -308,6 +352,14 @@ do {									\
 } while (0)
 
 
+#define tlb_read_hazard()						\
+do {									\
+	__asm__ __volatile__(						\
+	__stringify(__tlb_read_hazard)					\
+	);								\
+} while (0)
+
+
 #define tlb_probe_hazard()						\
 do {									\
 	__asm__ __volatile__(						\
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Add hazard macros to <asm/hazards.h> for the following hazards around
tlbr (TLB read) instructions, which are used in TLB dumping code and
some KVM TLB management code:

- mtc0_tlbr_hazard
  Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
  all cases on the assumption that tlbr always has similar data user
  timings to tlbw.

- tlb_read_hazard
  Between tlbr and mfc0 (various TLB registers). This is copied from
  tlbw_use_hazard in all cases on the assumption that tlbr has similar
  data writer characteristics to tlbw, and mfc0 has similar data user
  characteristics to loads and stores.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
and mfc0 had similar data writer timings to loads and stores. Are there
particular other cores that should be checked too?
---
 arch/mips/include/asm/hazards.h | 52 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4087b47ad1cb..7b99efd31074 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -31,9 +31,15 @@
 #define __mtc0_tlbw_hazard						\
 	___ehb
 
+#define __mtc0_tlbr_hazard						\
+	___ehb
+
 #define __tlbw_use_hazard						\
 	___ehb
 
+#define __tlb_read_hazard						\
+	___ehb
+
 #define __tlb_probe_hazard						\
 	___ehb
 
@@ -80,12 +86,23 @@ do {									\
 	___ssnop;							\
 	___ehb
 
+#define __mtc0_tlbr_hazard						\
+	___ssnop;							\
+	___ssnop;							\
+	___ehb
+
 #define __tlbw_use_hazard						\
 	___ssnop;							\
 	___ssnop;							\
 	___ssnop;							\
 	___ehb
 
+#define __tlb_read_hazard						\
+	___ssnop;							\
+	___ssnop;							\
+	___ssnop;							\
+	___ehb
+
 #define __tlb_probe_hazard						\
 	___ssnop;							\
 	___ssnop;							\
@@ -147,8 +164,12 @@ do {									\
 
 #define __mtc0_tlbw_hazard
 
+#define __mtc0_tlbr_hazard
+
 #define __tlbw_use_hazard
 
+#define __tlb_read_hazard
+
 #define __tlb_probe_hazard
 
 #define __irq_enable_hazard
@@ -166,8 +187,12 @@ do {									\
  */
 #define __mtc0_tlbw_hazard
 
+#define __mtc0_tlbr_hazard
+
 #define __tlbw_use_hazard
 
+#define __tlb_read_hazard
+
 #define __tlb_probe_hazard
 
 #define __irq_enable_hazard
@@ -196,11 +221,20 @@ do {									\
 	nop;								\
 	nop
 
+#define __mtc0_tlbr_hazard						\
+	nop;								\
+	nop
+
 #define __tlbw_use_hazard						\
 	nop;								\
 	nop;								\
 	nop
 
+#define __tlb_read_hazard						\
+	nop;								\
+	nop;								\
+	nop
+
 #define __tlb_probe_hazard						\
 	nop;								\
 	nop;								\
@@ -267,7 +301,9 @@ do {									\
 #define _ssnop ___ssnop
 #define	_ehb ___ehb
 #define mtc0_tlbw_hazard __mtc0_tlbw_hazard
+#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
 #define tlbw_use_hazard __tlbw_use_hazard
+#define tlb_read_hazard __tlb_read_hazard
 #define tlb_probe_hazard __tlb_probe_hazard
 #define irq_enable_hazard __irq_enable_hazard
 #define irq_disable_hazard __irq_disable_hazard
@@ -300,6 +336,14 @@ do {									\
 } while (0)
 
 
+#define mtc0_tlbr_hazard()						\
+do {									\
+	__asm__ __volatile__(						\
+	__stringify(__mtc0_tlbr_hazard)					\
+	);								\
+} while (0)
+
+
 #define tlbw_use_hazard()						\
 do {									\
 	__asm__ __volatile__(						\
@@ -308,6 +352,14 @@ do {									\
 } while (0)
 
 
+#define tlb_read_hazard()						\
+do {									\
+	__asm__ __volatile__(						\
+	__stringify(__tlb_read_hazard)					\
+	);								\
+} while (0)
+
+
 #define tlb_probe_hazard()						\
 do {									\
 	__asm__ __volatile__(						\
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Use the new tlb read hazard macros from <asm/hazards.h> rather than the
local BARRIER() macro which uses 7 ops regardless of the kernel
configuration.

We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
register and the tlbr, and tlb_read_hazard for the hazard between the
tlbr and the mfc0 of the TLB registers written by tlbr.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 32b9f21bfd85..a62dfacb60f7 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -7,6 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/mm.h>
 
+#include <asm/hazards.h>
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -40,12 +41,6 @@ static inline const char *msk2str(unsigned int mask)
 	return "";
 }
 
-#define BARRIER()					\
-	__asm__ __volatile__(				\
-		".set\tnoreorder\n\t"			\
-		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
-		".set\treorder");
-
 static void dump_tlb(int first, int last)
 {
 	unsigned long s_entryhi, entryhi, asid;
@@ -59,9 +54,9 @@ static void dump_tlb(int first, int last)
 
 	for (i = first; i <= last; i++) {
 		write_c0_index(i);
-		BARRIER();
+		mtc0_tlbr_hazard();
 		tlb_read();
-		BARRIER();
+		tlb_read_hazard();
 		pagemask = read_c0_pagemask();
 		entryhi	 = read_c0_entryhi();
 		entrylo0 = read_c0_entrylo0();
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Use the new tlb read hazard macros from <asm/hazards.h> rather than the
local BARRIER() macro which uses 7 ops regardless of the kernel
configuration.

We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
register and the tlbr, and tlb_read_hazard for the hazard between the
tlbr and the mfc0 of the TLB registers written by tlbr.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 32b9f21bfd85..a62dfacb60f7 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -7,6 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/mm.h>
 
+#include <asm/hazards.h>
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -40,12 +41,6 @@ static inline const char *msk2str(unsigned int mask)
 	return "";
 }
 
-#define BARRIER()					\
-	__asm__ __volatile__(				\
-		".set\tnoreorder\n\t"			\
-		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
-		".set\treorder");
-
 static void dump_tlb(int first, int last)
 {
 	unsigned long s_entryhi, entryhi, asid;
@@ -59,9 +54,9 @@ static void dump_tlb(int first, int last)
 
 	for (i = first; i <= last; i++) {
 		write_c0_index(i);
-		BARRIER();
+		mtc0_tlbr_hazard();
 		tlb_read();
-		BARRIER();
+		tlb_read_hazard();
 		pagemask = read_c0_pagemask();
 		entryhi	 = read_c0_entryhi();
 		entrylo0 = read_c0_entrylo0();
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 4/9] MIPS: dump_tlb: Refactor TLB matching
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Refactor the TLB matching code in dump_tlb() slightly so that the
conditions which can cause a TLB entry to be skipped can be more easily
extended. This should prevent the match condition getting unwieldy once
it is updated to take further conditions into account.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 65 ++++++++++++++++++++++++++----------------------
 1 file changed, 35 insertions(+), 30 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index a62dfacb60f7..17d05caa776d 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -46,6 +46,11 @@ static void dump_tlb(int first, int last)
 	unsigned long s_entryhi, entryhi, asid;
 	unsigned long long entrylo0, entrylo1;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
+#ifdef CONFIG_32BIT
+	int width = 8;
+#else
+	int width = 11;
+#endif
 
 	s_pagemask = read_c0_pagemask();
 	s_entryhi = read_c0_entryhi();
@@ -62,38 +67,38 @@ static void dump_tlb(int first, int last)
 		entrylo0 = read_c0_entrylo0();
 		entrylo1 = read_c0_entrylo1();
 
-		/* Unused entries have a virtual address of CKSEG0.  */
-		if ((entryhi & ~0x1ffffUL) != CKSEG0
-		    && (entryhi & 0xff) == asid) {
-#ifdef CONFIG_32BIT
-			int width = 8;
-#else
-			int width = 11;
-#endif
-			/*
-			 * Only print entries in use
-			 */
-			printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
+		/*
+		 * Prior to tlbinv, unused entries have a virtual address of
+		 * CKSEG0.
+		 */
+		if ((entryhi & ~0x1ffffUL) == CKSEG0)
+			continue;
+		if ((entryhi & 0xff) != asid)
+			continue;
 
-			c0 = (entrylo0 >> 3) & 7;
-			c1 = (entrylo1 >> 3) & 7;
+		/*
+		 * Only print entries in use
+		 */
+		printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
 
-			printk("va=%0*lx asid=%02lx\n",
-			       width, (entryhi & ~0x1fffUL),
-			       entryhi & 0xff);
-			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
-			       width,
-			       (entrylo0 << 6) & PAGE_MASK, c0,
-			       (entrylo0 & 4) ? 1 : 0,
-			       (entrylo0 & 2) ? 1 : 0,
-			       (entrylo0 & 1) ? 1 : 0);
-			printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-			       width,
-			       (entrylo1 << 6) & PAGE_MASK, c1,
-			       (entrylo1 & 4) ? 1 : 0,
-			       (entrylo1 & 2) ? 1 : 0,
-			       (entrylo1 & 1) ? 1 : 0);
-		}
+		c0 = (entrylo0 >> 3) & 7;
+		c1 = (entrylo1 >> 3) & 7;
+
+		printk("va=%0*lx asid=%02lx\n",
+		       width, (entryhi & ~0x1fffUL),
+		       entryhi & 0xff);
+		printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
+		       width,
+		       (entrylo0 << 6) & PAGE_MASK, c0,
+		       (entrylo0 & 4) ? 1 : 0,
+		       (entrylo0 & 2) ? 1 : 0,
+		       (entrylo0 & 1) ? 1 : 0);
+		printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
+		       width,
+		       (entrylo1 << 6) & PAGE_MASK, c1,
+		       (entrylo1 & 4) ? 1 : 0,
+		       (entrylo1 & 2) ? 1 : 0,
+		       (entrylo1 & 1) ? 1 : 0);
 	}
 	printk("\n");
 
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 4/9] MIPS: dump_tlb: Refactor TLB matching
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

Refactor the TLB matching code in dump_tlb() slightly so that the
conditions which can cause a TLB entry to be skipped can be more easily
extended. This should prevent the match condition getting unwieldy once
it is updated to take further conditions into account.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 65 ++++++++++++++++++++++++++----------------------
 1 file changed, 35 insertions(+), 30 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index a62dfacb60f7..17d05caa776d 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -46,6 +46,11 @@ static void dump_tlb(int first, int last)
 	unsigned long s_entryhi, entryhi, asid;
 	unsigned long long entrylo0, entrylo1;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
+#ifdef CONFIG_32BIT
+	int width = 8;
+#else
+	int width = 11;
+#endif
 
 	s_pagemask = read_c0_pagemask();
 	s_entryhi = read_c0_entryhi();
@@ -62,38 +67,38 @@ static void dump_tlb(int first, int last)
 		entrylo0 = read_c0_entrylo0();
 		entrylo1 = read_c0_entrylo1();
 
-		/* Unused entries have a virtual address of CKSEG0.  */
-		if ((entryhi & ~0x1ffffUL) != CKSEG0
-		    && (entryhi & 0xff) == asid) {
-#ifdef CONFIG_32BIT
-			int width = 8;
-#else
-			int width = 11;
-#endif
-			/*
-			 * Only print entries in use
-			 */
-			printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
+		/*
+		 * Prior to tlbinv, unused entries have a virtual address of
+		 * CKSEG0.
+		 */
+		if ((entryhi & ~0x1ffffUL) == CKSEG0)
+			continue;
+		if ((entryhi & 0xff) != asid)
+			continue;
 
-			c0 = (entrylo0 >> 3) & 7;
-			c1 = (entrylo1 >> 3) & 7;
+		/*
+		 * Only print entries in use
+		 */
+		printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
 
-			printk("va=%0*lx asid=%02lx\n",
-			       width, (entryhi & ~0x1fffUL),
-			       entryhi & 0xff);
-			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
-			       width,
-			       (entrylo0 << 6) & PAGE_MASK, c0,
-			       (entrylo0 & 4) ? 1 : 0,
-			       (entrylo0 & 2) ? 1 : 0,
-			       (entrylo0 & 1) ? 1 : 0);
-			printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-			       width,
-			       (entrylo1 << 6) & PAGE_MASK, c1,
-			       (entrylo1 & 4) ? 1 : 0,
-			       (entrylo1 & 2) ? 1 : 0,
-			       (entrylo1 & 1) ? 1 : 0);
-		}
+		c0 = (entrylo0 >> 3) & 7;
+		c1 = (entrylo1 >> 3) & 7;
+
+		printk("va=%0*lx asid=%02lx\n",
+		       width, (entryhi & ~0x1fffUL),
+		       entryhi & 0xff);
+		printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
+		       width,
+		       (entrylo0 << 6) & PAGE_MASK, c0,
+		       (entrylo0 & 4) ? 1 : 0,
+		       (entrylo0 & 2) ? 1 : 0,
+		       (entrylo0 & 1) ? 1 : 0);
+		printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
+		       width,
+		       (entrylo1 << 6) & PAGE_MASK, c1,
+		       (entrylo1 & 4) ? 1 : 0,
+		       (entrylo1 & 2) ? 1 : 0,
+		       (entrylo1 & 1) ? 1 : 0);
 	}
 	printk("\n");
 
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

The TLB only matches the ASID when the global bit isn't set, so
dump_tlb() shouldn't really be skipping global entries just because the
ASID doesn't match. Fix the condition to read the TLB entry's global bit
from EntryLo0. Note that after a TLB read the global bits in both
EntryLo registers reflect the same global bit in the TLB entry.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 17d05caa776d..70e0a6bdb322 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
 		 */
 		if ((entryhi & ~0x1ffffUL) == CKSEG0)
 			continue;
-		if ((entryhi & 0xff) != asid)
+		/* ASID takes effect in absense of global bit */
+		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
 			continue;
 
 		/*
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

The TLB only matches the ASID when the global bit isn't set, so
dump_tlb() shouldn't really be skipping global entries just because the
ASID doesn't match. Fix the condition to read the TLB entry's global bit
from EntryLo0. Note that after a TLB read the global bits in both
EntryLo registers reflect the same global bit in the TLB entry.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 17d05caa776d..70e0a6bdb322 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
 		 */
 		if ((entryhi & ~0x1ffffUL) == CKSEG0)
 			continue;
-		if ((entryhi & 0xff) != asid)
+		/* ASID takes effect in absense of global bit */
+		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
 			continue;
 
 		/*
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 6/9] MIPS: dump_tlb: Take EHINV bit into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

The EHINV bit in EntryHi allows a TLB entry to be properly marked
invalid so that EntryHi doesn't have to be set to a unique value to
avoid machine check exceptions due to multiple matching entries.

Unfortunately dump_tlb() doesn't take this into account so it will print
all the uninteresting invalid TLB entries if the current ASID happens to
be 00. Therefore add a condition to skip entries which are marked
invalid with the EHINV bit.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 70e0a6bdb322..f58962c11c75 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -67,6 +67,9 @@ static void dump_tlb(int first, int last)
 		entrylo0 = read_c0_entrylo0();
 		entrylo1 = read_c0_entrylo1();
 
+		/* EHINV bit marks entire entry as invalid */
+		if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
+			continue;
 		/*
 		 * Prior to tlbinv, unused entries have a virtual address of
 		 * CKSEG0.
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 6/9] MIPS: dump_tlb: Take EHINV bit into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan

The EHINV bit in EntryHi allows a TLB entry to be properly marked
invalid so that EntryHi doesn't have to be set to a unique value to
avoid machine check exceptions due to multiple matching entries.

Unfortunately dump_tlb() doesn't take this into account so it will print
all the uninteresting invalid TLB entries if the current ASID happens to
be 00. Therefore add a condition to skip entries which are marked
invalid with the EHINV bit.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 70e0a6bdb322..f58962c11c75 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -67,6 +67,9 @@ static void dump_tlb(int first, int last)
 		entrylo0 = read_c0_entrylo0();
 		entrylo1 = read_c0_entrylo1();
 
+		/* EHINV bit marks entire entry as invalid */
+		if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
+			continue;
 		/*
 		 * Prior to tlbinv, unused entries have a virtual address of
 		 * CKSEG0.
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 7/9] MIPS: dump_tlb: Take RI/XI bits into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, David Daney

The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:

Index: 253 pgmask=16kb va=77b18000 asid=75
        [pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]

The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.

Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:

Index: 226 pgmask=16kb va=77be0000 asid=79
        [ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/include/asm/mipsregs.h | 11 +++++++++++
 arch/mips/lib/dump_tlb.c         | 27 ++++++++++++++++++++-------
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 764e2756b54d..22b10e044532 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -589,6 +589,17 @@
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
+/* EntryLo bit definitions */
+#ifdef CONFIG_64BIT
+/* as read by dmfc0 */
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 63)
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 62)
+#else
+/* as read by mfc0 */
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 31)
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 30)
+#endif
+
 /* CMGCRBase bit definitions */
 #define MIPS_CMGCRB_BASE	11
 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index f58962c11c75..b918646d6c8d 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -44,7 +44,7 @@ static inline const char *msk2str(unsigned int mask)
 static void dump_tlb(int first, int last)
 {
 	unsigned long s_entryhi, entryhi, asid;
-	unsigned long long entrylo0, entrylo1;
+	unsigned long long entrylo0, entrylo1, pa;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
 #ifdef CONFIG_32BIT
 	int width = 8;
@@ -91,15 +91,28 @@ static void dump_tlb(int first, int last)
 		printk("va=%0*lx asid=%02lx\n",
 		       width, (entryhi & ~0x1fffUL),
 		       entryhi & 0xff);
-		printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
-		       width,
-		       (entrylo0 << 6) & PAGE_MASK, c0,
+		/* RI/XI are in awkward places, so mask them off separately */
+		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		pa = (pa << 6) & PAGE_MASK;
+		printk("\t[");
+		if (cpu_has_rixi)
+			printk("ri=%d xi=%d ",
+			       (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
+			       (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
+		printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
+		       width, pa, c0,
 		       (entrylo0 & 4) ? 1 : 0,
 		       (entrylo0 & 2) ? 1 : 0,
 		       (entrylo0 & 1) ? 1 : 0);
-		printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-		       width,
-		       (entrylo1 << 6) & PAGE_MASK, c1,
+		/* RI/XI are in awkward places, so mask them off separately */
+		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		pa = (pa << 6) & PAGE_MASK;
+		if (cpu_has_rixi)
+			printk("ri=%d xi=%d ",
+			       (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
+			       (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
+		printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
+		       width, pa, c1,
 		       (entrylo1 & 4) ? 1 : 0,
 		       (entrylo1 & 2) ? 1 : 0,
 		       (entrylo1 & 1) ? 1 : 0);
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 7/9] MIPS: dump_tlb: Take RI/XI bits into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, David Daney

The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:

Index: 253 pgmask=16kb va=77b18000 asid=75
        [pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]

The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.

Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:

Index: 226 pgmask=16kb va=77be0000 asid=79
        [ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/include/asm/mipsregs.h | 11 +++++++++++
 arch/mips/lib/dump_tlb.c         | 27 ++++++++++++++++++++-------
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 764e2756b54d..22b10e044532 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -589,6 +589,17 @@
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
+/* EntryLo bit definitions */
+#ifdef CONFIG_64BIT
+/* as read by dmfc0 */
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 63)
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 62)
+#else
+/* as read by mfc0 */
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 31)
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 30)
+#endif
+
 /* CMGCRBase bit definitions */
 #define MIPS_CMGCRB_BASE	11
 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index f58962c11c75..b918646d6c8d 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -44,7 +44,7 @@ static inline const char *msk2str(unsigned int mask)
 static void dump_tlb(int first, int last)
 {
 	unsigned long s_entryhi, entryhi, asid;
-	unsigned long long entrylo0, entrylo1;
+	unsigned long long entrylo0, entrylo1, pa;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
 #ifdef CONFIG_32BIT
 	int width = 8;
@@ -91,15 +91,28 @@ static void dump_tlb(int first, int last)
 		printk("va=%0*lx asid=%02lx\n",
 		       width, (entryhi & ~0x1fffUL),
 		       entryhi & 0xff);
-		printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
-		       width,
-		       (entrylo0 << 6) & PAGE_MASK, c0,
+		/* RI/XI are in awkward places, so mask them off separately */
+		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		pa = (pa << 6) & PAGE_MASK;
+		printk("\t[");
+		if (cpu_has_rixi)
+			printk("ri=%d xi=%d ",
+			       (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
+			       (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
+		printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
+		       width, pa, c0,
 		       (entrylo0 & 4) ? 1 : 0,
 		       (entrylo0 & 2) ? 1 : 0,
 		       (entrylo0 & 1) ? 1 : 0);
-		printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-		       width,
-		       (entrylo1 << 6) & PAGE_MASK, c1,
+		/* RI/XI are in awkward places, so mask them off separately */
+		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		pa = (pa << 6) & PAGE_MASK;
+		if (cpu_has_rixi)
+			printk("ri=%d xi=%d ",
+			       (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
+			       (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
+		printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
+		       width, pa, c1,
 		       (entrylo1 & 4) ? 1 : 0,
 		       (entrylo1 & 2) ? 1 : 0,
 		       (entrylo1 & 1) ? 1 : 0);
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 8/9] MIPS: dump_tlb: Take XPA into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, Steven J. Hill

XPA extends the physical addresses on MIPS32, including the EntryLo
registers. Update dump_tlb() to concatenate the PFNX field from the high
end of the EntryLo registers (as read by mfhc0).

The width of physical and virtual addresses are also separated to show
only 8 nibbles of virtual but 11 nibbles of physical with XPA.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index b918646d6c8d..0be4b8f8a666 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -47,9 +47,13 @@ static void dump_tlb(int first, int last)
 	unsigned long long entrylo0, entrylo1, pa;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
 #ifdef CONFIG_32BIT
-	int width = 8;
+	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
+	int pwidth = xpa ? 11 : 8;
+	int vwidth = 8;
 #else
-	int width = 11;
+	bool xpa = false;
+	int pwidth = 11;
+	int vwidth = 11;
 #endif
 
 	s_pagemask = read_c0_pagemask();
@@ -89,10 +93,12 @@ static void dump_tlb(int first, int last)
 		c1 = (entrylo1 >> 3) & 7;
 
 		printk("va=%0*lx asid=%02lx\n",
-		       width, (entryhi & ~0x1fffUL),
+		       vwidth, (entryhi & ~0x1fffUL),
 		       entryhi & 0xff);
 		/* RI/XI are in awkward places, so mask them off separately */
 		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		if (xpa)
+			pa |= (unsigned long long)readx_c0_entrylo0() << 30;
 		pa = (pa << 6) & PAGE_MASK;
 		printk("\t[");
 		if (cpu_has_rixi)
@@ -100,19 +106,21 @@ static void dump_tlb(int first, int last)
 			       (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
 			       (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
 		printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
-		       width, pa, c0,
+		       pwidth, pa, c0,
 		       (entrylo0 & 4) ? 1 : 0,
 		       (entrylo0 & 2) ? 1 : 0,
 		       (entrylo0 & 1) ? 1 : 0);
 		/* RI/XI are in awkward places, so mask them off separately */
 		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		if (xpa)
+			pa |= (unsigned long long)readx_c0_entrylo1() << 30;
 		pa = (pa << 6) & PAGE_MASK;
 		if (cpu_has_rixi)
 			printk("ri=%d xi=%d ",
 			       (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
 			       (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
 		printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-		       width, pa, c1,
+		       pwidth, pa, c1,
 		       (entrylo1 & 4) ? 1 : 0,
 		       (entrylo1 & 2) ? 1 : 0,
 		       (entrylo1 & 1) ? 1 : 0);
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 8/9] MIPS: dump_tlb: Take XPA into account
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, Steven J. Hill

XPA extends the physical addresses on MIPS32, including the EntryLo
registers. Update dump_tlb() to concatenate the PFNX field from the high
end of the EntryLo registers (as read by mfhc0).

The width of physical and virtual addresses are also separated to show
only 8 nibbles of virtual but 11 nibbles of physical with XPA.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/lib/dump_tlb.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index b918646d6c8d..0be4b8f8a666 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -47,9 +47,13 @@ static void dump_tlb(int first, int last)
 	unsigned long long entrylo0, entrylo1, pa;
 	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
 #ifdef CONFIG_32BIT
-	int width = 8;
+	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
+	int pwidth = xpa ? 11 : 8;
+	int vwidth = 8;
 #else
-	int width = 11;
+	bool xpa = false;
+	int pwidth = 11;
+	int vwidth = 11;
 #endif
 
 	s_pagemask = read_c0_pagemask();
@@ -89,10 +93,12 @@ static void dump_tlb(int first, int last)
 		c1 = (entrylo1 >> 3) & 7;
 
 		printk("va=%0*lx asid=%02lx\n",
-		       width, (entryhi & ~0x1fffUL),
+		       vwidth, (entryhi & ~0x1fffUL),
 		       entryhi & 0xff);
 		/* RI/XI are in awkward places, so mask them off separately */
 		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		if (xpa)
+			pa |= (unsigned long long)readx_c0_entrylo0() << 30;
 		pa = (pa << 6) & PAGE_MASK;
 		printk("\t[");
 		if (cpu_has_rixi)
@@ -100,19 +106,21 @@ static void dump_tlb(int first, int last)
 			       (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
 			       (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
 		printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
-		       width, pa, c0,
+		       pwidth, pa, c0,
 		       (entrylo0 & 4) ? 1 : 0,
 		       (entrylo0 & 2) ? 1 : 0,
 		       (entrylo0 & 1) ? 1 : 0);
 		/* RI/XI are in awkward places, so mask them off separately */
 		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
+		if (xpa)
+			pa |= (unsigned long long)readx_c0_entrylo1() << 30;
 		pa = (pa << 6) & PAGE_MASK;
 		if (cpu_has_rixi)
 			printk("ri=%d xi=%d ",
 			       (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
 			       (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
 		printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
-		       width, pa, c1,
+		       pwidth, pa, c1,
 		       (entrylo1 & 4) ? 1 : 0,
 		       (entrylo1 & 2) ? 1 : 0,
 		       (entrylo1 & 1) ? 1 : 0);
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 9/9] MIPS: tlb-r4k: Fix PG_ELPA comment
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, David Daney

The ELPA bit in PageGrain is all about large *physical* addresses, so
correct the reference to "large virtual address" in the comment above
where it is set for MIPS64.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/mm/tlb-r4k.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index a27a088e6f9f..08318ecb803a 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -495,7 +495,7 @@ static void r4k_tlb_configure(void)
 
 	if (cpu_has_rixi) {
 		/*
-		 * Enable the no read, no exec bits, and enable large virtual
+		 * Enable the no read, no exec bits, and enable large physical
 		 * address.
 		 */
 #ifdef CONFIG_64BIT
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 9/9] MIPS: tlb-r4k: Fix PG_ELPA comment
@ 2015-05-13 10:50   ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-13 10:50 UTC (permalink / raw)
  To: Ralf Baechle, linux-mips; +Cc: James Hogan, David Daney

The ELPA bit in PageGrain is all about large *physical* addresses, so
correct the reference to "large virtual address" in the comment above
where it is set for MIPS64.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/mm/tlb-r4k.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index a27a088e6f9f..08318ecb803a 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -495,7 +495,7 @@ static void r4k_tlb_configure(void)
 
 	if (cpu_has_rixi) {
 		/*
-		 * Enable the no read, no exec bits, and enable large virtual
+		 * Enable the no read, no exec bits, and enable large physical
 		 * address.
 		 */
 #ifdef CONFIG_64BIT
-- 
2.3.6

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* Re: [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read
  2015-05-13 10:50   ` James Hogan
  (?)
@ 2015-05-15 15:08   ` Ralf Baechle
  2015-05-18 13:30       ` James Hogan
  -1 siblings, 1 reply; 33+ messages in thread
From: Ralf Baechle @ 2015-05-15 15:08 UTC (permalink / raw)
  To: James Hogan; +Cc: linux-mips

On Wed, May 13, 2015 at 11:50:48AM +0100, James Hogan wrote:

> Add hazard macros to <asm/hazards.h> for the following hazards around
> tlbr (TLB read) instructions, which are used in TLB dumping code and
> some KVM TLB management code:
> 
> - mtc0_tlbr_hazard
>   Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
>   all cases on the assumption that tlbr always has similar data user
>   timings to tlbw.
> 
> - tlb_read_hazard
>   Between tlbr and mfc0 (various TLB registers). This is copied from
>   tlbw_use_hazard in all cases on the assumption that tlbr has similar
>   data writer characteristics to tlbw, and mfc0 has similar data user
>   characteristics to loads and stores.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
> Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
> and mfc0 had similar data writer timings to loads and stores. Are there
> particular other cores that should be checked too?

The R4600 and R5000 CPUs are important.  The R4600 also covers the
R4700 and the R5000 the R52xx embedded cores.

For most cases the R4000/R4400 due to their long pipeline represent the
worst case but there are exceptions.

  Ralf

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros
  2015-05-13 10:50   ` James Hogan
  (?)
@ 2015-05-15 15:17   ` Ralf Baechle
  2015-05-16  0:32     ` Maciej W. Rozycki
  -1 siblings, 1 reply; 33+ messages in thread
From: Ralf Baechle @ 2015-05-15 15:17 UTC (permalink / raw)
  To: James Hogan; +Cc: linux-mips

On Wed, May 13, 2015 at 11:50:49AM +0100, James Hogan wrote:

> Use the new tlb read hazard macros from <asm/hazards.h> rather than the
> local BARRIER() macro which uses 7 ops regardless of the kernel
> configuration.
> 
> We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
> register and the tlbr, and tlb_read_hazard for the hazard between the
> tlbr and the mfc0 of the TLB registers written by tlbr.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org

Only to repeat for the benefit of the mailing list readers what I already
wrote on IRC recently.  The 7 NOPs sequence will send the uncached
write-back buffer of the R4400 but not R4000 off-chip.  This operation
of course is entirely irrelevant to what the TLB dumper does - but it
just so happens that seven NOPs are also sufficient to deal with TLB
hazards on most CPUs.  If we're lucky - it doesn't use SSNOPs or EHBs.

  Ralf

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
  2015-05-13 10:50   ` James Hogan
  (?)
@ 2015-05-15 15:38   ` Ralf Baechle
  2015-05-18 13:37       ` James Hogan
  -1 siblings, 1 reply; 33+ messages in thread
From: Ralf Baechle @ 2015-05-15 15:38 UTC (permalink / raw)
  To: James Hogan; +Cc: linux-mips

On Wed, May 13, 2015 at 11:50:51AM +0100, James Hogan wrote:

> The TLB only matches the ASID when the global bit isn't set, so
> dump_tlb() shouldn't really be skipping global entries just because the
> ASID doesn't match. Fix the condition to read the TLB entry's global bit
> from EntryLo0. Note that after a TLB read the global bits in both
> EntryLo registers reflect the same global bit in the TLB entry.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
>  arch/mips/lib/dump_tlb.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
> index 17d05caa776d..70e0a6bdb322 100644
> --- a/arch/mips/lib/dump_tlb.c
> +++ b/arch/mips/lib/dump_tlb.c
> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>  		 */
>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>  			continue;
> -		if ((entryhi & 0xff) != asid)
> +		/* ASID takes effect in absense of global bit */
> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>  			continue;

Note the architecture mandates that there only is one global bit per
TLB entry and its written as the logic and of the two global bits in
the entrylo0 and entrylo1 registers.  On TLB read the G bits of both
entrylo registers will return the same value.

In reality some implementations differ in hardware, for example the
SB1 core where the TLB entries both have their separate G bit.  Both
will be written with the logic and of the G bits of the entrylo registers
so the existence of multiple G bits per TLB entry should never become
visible.

Except when writing a duplicate TLB entry where certain revisions will
write the entrylo0 half of the TLB entry, then take the machine check
exception leaving the entrylo1 half of the TLB entry unchanged.  At
this point one may end up with architecturally undefined TLB entries
with one G bit set and one clear.

There may be other CPUs where such invalid TLB entries are possible
therfore think we should check for entries with mismatching global
bits and print those anyway.

  Ralf

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros
  2015-05-15 15:17   ` Ralf Baechle
@ 2015-05-16  0:32     ` Maciej W. Rozycki
  0 siblings, 0 replies; 33+ messages in thread
From: Maciej W. Rozycki @ 2015-05-16  0:32 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: James Hogan, linux-mips

On Fri, 15 May 2015, Ralf Baechle wrote:

> Only to repeat for the benefit of the mailing list readers what I already
> wrote on IRC recently.  The 7 NOPs sequence will send the uncached
> write-back buffer of the R4400 but not R4000 off-chip.

 Well, the R4000 doesn't have such a buffer, so there's simply nothing to 
send. :)  And in any case issuing a SYNC followed by a load operation is 
the proper architectural way to send any outstanding writes off the chip.

  Maciej

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
  2015-05-13 10:50   ` James Hogan
  (?)
  (?)
@ 2015-05-16  0:44   ` Maciej W. Rozycki
  2015-05-16  1:02     ` Maciej W. Rozycki
  2015-05-18 13:50       ` James Hogan
  -1 siblings, 2 replies; 33+ messages in thread
From: Maciej W. Rozycki @ 2015-05-16  0:44 UTC (permalink / raw)
  To: James Hogan; +Cc: Ralf Baechle, linux-mips

On Wed, 13 May 2015, James Hogan wrote:

> The TLB only matches the ASID when the global bit isn't set, so
> dump_tlb() shouldn't really be skipping global entries just because the
> ASID doesn't match. Fix the condition to read the TLB entry's global bit
> from EntryLo0. Note that after a TLB read the global bits in both
> EntryLo registers reflect the same global bit in the TLB entry.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
>  arch/mips/lib/dump_tlb.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
> index 17d05caa776d..70e0a6bdb322 100644
> --- a/arch/mips/lib/dump_tlb.c
> +++ b/arch/mips/lib/dump_tlb.c
> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>  		 */
>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>  			continue;
> -		if ((entryhi & 0xff) != asid)
> +		/* ASID takes effect in absense of global bit */

 Typo here, s/absense/absence/.

> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)

 Hmm, it looks like r3k_dump_tlb.c will need a similar update.  I suggest 
using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.

  Maciej

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
  2015-05-16  0:44   ` Maciej W. Rozycki
@ 2015-05-16  1:02     ` Maciej W. Rozycki
  2015-05-18 13:50       ` James Hogan
  1 sibling, 0 replies; 33+ messages in thread
From: Maciej W. Rozycki @ 2015-05-16  1:02 UTC (permalink / raw)
  To: James Hogan; +Cc: Ralf Baechle, linux-mips

On Sat, 16 May 2015, Maciej W. Rozycki wrote:

> > +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
> 
>  Hmm, it looks like r3k_dump_tlb.c will need a similar update.  I suggest 
> using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.

 Umm, _PAGE_GLOBAL won't work here as the R4k TLB model uses 
`pte_to_entrylo' that shifts PTEs.  So it looks we need another set of 
macros (beyond ASID_MASK) to describe bits in EntryLo registers.

  Maciej

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read
@ 2015-05-18 13:30       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:30 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips

[-- Attachment #1: Type: text/plain, Size: 1869 bytes --]

Hi Ralf,

On 15/05/15 16:08, Ralf Baechle wrote:
> On Wed, May 13, 2015 at 11:50:48AM +0100, James Hogan wrote:
> 
>> Add hazard macros to <asm/hazards.h> for the following hazards around
>> tlbr (TLB read) instructions, which are used in TLB dumping code and
>> some KVM TLB management code:
>>
>> - mtc0_tlbr_hazard
>>   Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
>>   all cases on the assumption that tlbr always has similar data user
>>   timings to tlbw.
>>
>> - tlb_read_hazard
>>   Between tlbr and mfc0 (various TLB registers). This is copied from
>>   tlbw_use_hazard in all cases on the assumption that tlbr has similar
>>   data writer characteristics to tlbw, and mfc0 has similar data user
>>   characteristics to loads and stores.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>> Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
>> and mfc0 had similar data writer timings to loads and stores. Are there
>> particular other cores that should be checked too?
> 
> The R4600 and R5000 CPUs are important.  The R4600 also covers the
> R4700 and the R5000 the R52xx embedded cores.
> 
> For most cases the R4000/R4400 due to their long pipeline represent the
> worst case but there are exceptions.

Okay. For mtc0-tlbw/tlbr on r4000:
mtc0	CPR written stage 7
tlbwi/r	CPR read stage 5-8 (5-7 for tlbr)
delay = 7-5-1 = 1 nop
but linux has 2 nops for __mtc0_tlbw_hazard. Is that one of the exceptions?

(
For r4600, mtc0-tlbw/tlbr = 4-2-1 = 1 nop too

For tlbr-mfc0, r4000:
tlbr	CPR written stage 8
mfc0	CPR read state 4
delay = 8-4-1 = 3 nops (that's what I have)

r4600:
tlbr	CPR written stage 4
mfc0	CPR read stage 2
delay = 4-2-1 = 1 nop
)

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read
@ 2015-05-18 13:30       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:30 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips

[-- Attachment #1: Type: text/plain, Size: 1869 bytes --]

Hi Ralf,

On 15/05/15 16:08, Ralf Baechle wrote:
> On Wed, May 13, 2015 at 11:50:48AM +0100, James Hogan wrote:
> 
>> Add hazard macros to <asm/hazards.h> for the following hazards around
>> tlbr (TLB read) instructions, which are used in TLB dumping code and
>> some KVM TLB management code:
>>
>> - mtc0_tlbr_hazard
>>   Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
>>   all cases on the assumption that tlbr always has similar data user
>>   timings to tlbw.
>>
>> - tlb_read_hazard
>>   Between tlbr and mfc0 (various TLB registers). This is copied from
>>   tlbw_use_hazard in all cases on the assumption that tlbr has similar
>>   data writer characteristics to tlbw, and mfc0 has similar data user
>>   characteristics to loads and stores.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>> Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
>> and mfc0 had similar data writer timings to loads and stores. Are there
>> particular other cores that should be checked too?
> 
> The R4600 and R5000 CPUs are important.  The R4600 also covers the
> R4700 and the R5000 the R52xx embedded cores.
> 
> For most cases the R4000/R4400 due to their long pipeline represent the
> worst case but there are exceptions.

Okay. For mtc0-tlbw/tlbr on r4000:
mtc0	CPR written stage 7
tlbwi/r	CPR read stage 5-8 (5-7 for tlbr)
delay = 7-5-1 = 1 nop
but linux has 2 nops for __mtc0_tlbw_hazard. Is that one of the exceptions?

(
For r4600, mtc0-tlbw/tlbr = 4-2-1 = 1 nop too

For tlbr-mfc0, r4000:
tlbr	CPR written stage 8
mfc0	CPR read state 4
delay = 8-4-1 = 3 nops (that's what I have)

r4600:
tlbr	CPR written stage 4
mfc0	CPR read stage 2
delay = 4-2-1 = 1 nop
)

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-18 13:37       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:37 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips

[-- Attachment #1: Type: text/plain, Size: 2415 bytes --]

On 15/05/15 16:38, Ralf Baechle wrote:
> On Wed, May 13, 2015 at 11:50:51AM +0100, James Hogan wrote:
> 
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>>  arch/mips/lib/dump_tlb.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>>  		 */
>>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>>  			continue;
>> -		if ((entryhi & 0xff) != asid)
>> +		/* ASID takes effect in absense of global bit */
>> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>>  			continue;
> 
> Note the architecture mandates that there only is one global bit per
> TLB entry and its written as the logic and of the two global bits in
> the entrylo0 and entrylo1 registers.  On TLB read the G bits of both
> entrylo registers will return the same value.
> 
> In reality some implementations differ in hardware, for example the
> SB1 core where the TLB entries both have their separate G bit.  Both
> will be written with the logic and of the G bits of the entrylo registers
> so the existence of multiple G bits per TLB entry should never become
> visible.
> 
> Except when writing a duplicate TLB entry where certain revisions will
> write the entrylo0 half of the TLB entry, then take the machine check
> exception leaving the entrylo1 half of the TLB entry unchanged.  At
> this point one may end up with architecturally undefined TLB entries
> with one G bit set and one clear.
> 
> There may be other CPUs where such invalid TLB entries are possible
> therfore think we should check for entries with mismatching global
> bits and print those anyway.

Okay, makes sense. If either global bit is set I'll make it skip the
ASID check.

Thanks for the information.

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-18 13:37       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:37 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips

[-- Attachment #1: Type: text/plain, Size: 2415 bytes --]

On 15/05/15 16:38, Ralf Baechle wrote:
> On Wed, May 13, 2015 at 11:50:51AM +0100, James Hogan wrote:
> 
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>>  arch/mips/lib/dump_tlb.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>>  		 */
>>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>>  			continue;
>> -		if ((entryhi & 0xff) != asid)
>> +		/* ASID takes effect in absense of global bit */
>> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>>  			continue;
> 
> Note the architecture mandates that there only is one global bit per
> TLB entry and its written as the logic and of the two global bits in
> the entrylo0 and entrylo1 registers.  On TLB read the G bits of both
> entrylo registers will return the same value.
> 
> In reality some implementations differ in hardware, for example the
> SB1 core where the TLB entries both have their separate G bit.  Both
> will be written with the logic and of the G bits of the entrylo registers
> so the existence of multiple G bits per TLB entry should never become
> visible.
> 
> Except when writing a duplicate TLB entry where certain revisions will
> write the entrylo0 half of the TLB entry, then take the machine check
> exception leaving the entrylo1 half of the TLB entry unchanged.  At
> this point one may end up with architecturally undefined TLB entries
> with one G bit set and one clear.
> 
> There may be other CPUs where such invalid TLB entries are possible
> therfore think we should check for entries with mismatching global
> bits and print those anyway.

Okay, makes sense. If either global bit is set I'll make it skip the
ASID check.

Thanks for the information.

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-18 13:50       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:50 UTC (permalink / raw)
  To: Maciej W. Rozycki; +Cc: Ralf Baechle, linux-mips

[-- Attachment #1: Type: text/plain, Size: 1783 bytes --]

Hi Maciej,

On 16/05/15 01:44, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, James Hogan wrote:
> 
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>>  arch/mips/lib/dump_tlb.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>>  		 */
>>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>>  			continue;
>> -		if ((entryhi & 0xff) != asid)
>> +		/* ASID takes effect in absense of global bit */
> 
>  Typo here, s/absense/absence/.

Thanks!

> 
>> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
> 
>  Hmm, it looks like r3k_dump_tlb.c will need a similar update.  I suggest 

Yes, quite possibly. Would you be happy to test such a patch (assuming
you have r3000 hardware available)? Patch 1 should allow the code to be
easily triggered.

> using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.

Yeh, as you mentioned these describe the PTE rather than what goes in
EntryLo. Perhaps it makes sense to have a few more TLB dependent
definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits).

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
@ 2015-05-18 13:50       ` James Hogan
  0 siblings, 0 replies; 33+ messages in thread
From: James Hogan @ 2015-05-18 13:50 UTC (permalink / raw)
  To: Maciej W. Rozycki; +Cc: Ralf Baechle, linux-mips

[-- Attachment #1: Type: text/plain, Size: 1783 bytes --]

Hi Maciej,

On 16/05/15 01:44, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, James Hogan wrote:
> 
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>>  arch/mips/lib/dump_tlb.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>>  		 */
>>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>>  			continue;
>> -		if ((entryhi & 0xff) != asid)
>> +		/* ASID takes effect in absense of global bit */
> 
>  Typo here, s/absense/absence/.

Thanks!

> 
>> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
> 
>  Hmm, it looks like r3k_dump_tlb.c will need a similar update.  I suggest 

Yes, quite possibly. Would you be happy to test such a patch (assuming
you have r3000 hardware available)? Patch 1 should allow the code to be
easily triggered.

> using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.

Yeh, as you mentioned these describe the PTE rather than what goes in
EntryLo. Perhaps it makes sense to have a few more TLB dependent
definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits).

Cheers
James


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^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
  2015-05-18 13:50       ` James Hogan
  (?)
@ 2015-05-18 14:19       ` Maciej W. Rozycki
  -1 siblings, 0 replies; 33+ messages in thread
From: Maciej W. Rozycki @ 2015-05-18 14:19 UTC (permalink / raw)
  To: James Hogan; +Cc: Ralf Baechle, linux-mips

On Mon, 18 May 2015, James Hogan wrote:

> >> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
> > 
> >  Hmm, it looks like r3k_dump_tlb.c will need a similar update.  I suggest 
> 
> Yes, quite possibly. Would you be happy to test such a patch (assuming
> you have r3000 hardware available)? Patch 1 should allow the code to be
> easily triggered.

 I'll test the change when you have it, no problem with that.

> > using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.
> 
> Yeh, as you mentioned these describe the PTE rather than what goes in
> EntryLo. Perhaps it makes sense to have a few more TLB dependent
> definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits).

 I think so.  Hardcoded magic values are a pain to track down when you 
need to do so.

 Will you be able to add MIPS_ENTRYLO_G and R3K_ENTRYLO_G, etc. macros 
then please?  I think you can reorder all mipsregs.h changes ahead of the 
series as a single patch.

 Thanks,

  Maciej

^ permalink raw reply	[flat|nested] 33+ messages in thread
end of thread, other threads:[~2015-05-18 14:19 UTC | newest]

Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-13 10:50 [PATCH 0/9] MIPS: dump_tlb improvements James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH RFC 1/9] MIPS: Add SysRq operation to dump TLBs on all CPUs James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-13 10:50 ` [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-15 15:08   ` Ralf Baechle
2015-05-18 13:30     ` James Hogan
2015-05-18 13:30       ` James Hogan
2015-05-13 10:50 ` [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-15 15:17   ` Ralf Baechle
2015-05-16  0:32     ` Maciej W. Rozycki
2015-05-13 10:50 ` [PATCH 4/9] MIPS: dump_tlb: Refactor TLB matching James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-13 10:50 ` [PATCH 5/9] MIPS: dump_tlb: Take global bit into account James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-15 15:38   ` Ralf Baechle
2015-05-18 13:37     ` James Hogan
2015-05-18 13:37       ` James Hogan
2015-05-16  0:44   ` Maciej W. Rozycki
2015-05-16  1:02     ` Maciej W. Rozycki
2015-05-18 13:50     ` James Hogan
2015-05-18 13:50       ` James Hogan
2015-05-18 14:19       ` Maciej W. Rozycki
2015-05-13 10:50 ` [PATCH 6/9] MIPS: dump_tlb: Take EHINV " James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-13 10:50 ` [PATCH 7/9] MIPS: dump_tlb: Take RI/XI bits " James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-13 10:50 ` [PATCH 8/9] MIPS: dump_tlb: Take XPA " James Hogan
2015-05-13 10:50   ` James Hogan
2015-05-13 10:50 ` [PATCH 9/9] MIPS: tlb-r4k: Fix PG_ELPA comment James Hogan
2015-05-13 10:50   ` James Hogan

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