* [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
@ 2015-05-19 12:04 Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
` (3 more replies)
0 siblings, 4 replies; 17+ messages in thread
From: Imre Deak @ 2015-05-19 12:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Also make the WA comment consistent with the rest, where the stepping
info is not shown.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9b96ed7..461b9be 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
- /*
- * FIXME: don't apply the following on BXT for stepping C. On BXT A0
- * the flag reads back as 0.
- */
- /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
- if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+ /* WaDisableMaskBasedCammingInRCC:skl,bxt */
+ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
+ (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] drm/i915/skl: add F0 stepping ID
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
@ 2015-05-19 12:05 ` Imre Deak
2015-05-19 14:42 ` Damien Lespiau
2015-05-19 12:05 ` [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing Imre Deak
` (2 subsequent siblings)
3 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2015-05-19 12:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 840f08f..731b5ce 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
#define SKL_REVID_C0 (0x2)
#define SKL_REVID_D0 (0x3)
#define SKL_REVID_E0 (0x4)
+#define SKL_REVID_F0 (0x5)
#define BXT_REVID_A0 (0x0)
#define BXT_REVID_B0 (0x3)
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
@ 2015-05-19 12:05 ` Imre Deak
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
3 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2015-05-19 12:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 461b9be..2e342db 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -967,6 +967,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
+ /* WaDisableSbeCacheDispatchPortSharing:skl,bxt */
+ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_F0) ||
+ (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0))
+ WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
return 0;
}
@@ -1050,13 +1056,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
- /* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (INTEL_REVID(dev) <= BXT_REVID_B0) {
- WA_SET_BIT_MASKED(
- GEN7_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
- }
-
/* WaForceContextSaveRestoreNonCoherent:bxt */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
2015-05-19 12:05 ` [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing Imre Deak
@ 2015-05-19 12:05 ` Imre Deak
2015-05-19 13:08 ` Mika Kuoppala
` (3 more replies)
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
3 siblings, 4 replies; 17+ messages in thread
From: Imre Deak @ 2015-05-19 12:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2e342db..0d1522f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
return 0;
}
@@ -1056,10 +1060,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
- /* WaForceContextSaveRestoreNonCoherent:bxt */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
return 0;
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
@ 2015-05-19 13:08 ` Mika Kuoppala
2015-05-19 13:28 ` Imre Deak
2015-05-19 14:05 ` [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ Imre Deak
` (2 subsequent siblings)
3 siblings, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2015-05-19 13:08 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Daniel Vetter
Imre Deak <imre.deak@intel.com> writes:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2e342db..0d1522f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>
> + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> + WA_SET_BIT_MASKED(HDC_CHICKEN0,
> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
I think we need to also set bit 15 as it looks to be master switch
for this bit.
-Mika
> return 0;
> }
>
> @@ -1056,10 +1060,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> STALL_DOP_GATING_DISABLE);
>
> - /* WaForceContextSaveRestoreNonCoherent:bxt */
> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
> - HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> -
> return 0;
> }
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 13:08 ` Mika Kuoppala
@ 2015-05-19 13:28 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2015-05-19 13:28 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: Daniel Vetter, intel-gfx
On ti, 2015-05-19 at 16:08 +0300, Mika Kuoppala wrote:
> Imre Deak <imre.deak@intel.com> writes:
>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 2e342db..0d1522f 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
> > GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> >
> > + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> > + WA_SET_BIT_MASKED(HDC_CHICKEN0,
> > + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> > +
>
> I think we need to also set bit 15 as it looks to be master switch
> for this bit.
Yes, thanks for catching it.
--Imre
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 13:08 ` Mika Kuoppala
@ 2015-05-19 14:05 ` Imre Deak
2015-05-19 14:05 ` [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-21 7:45 ` [PATCH " shuang.he
3 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2015-05-19 14:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Mika Kuoppala
On B0 and C0 steppings the workaround enable bit would be overriden by
default, so the overriding must be disabled.
The WA was added in
commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3
Author: Nick Hoath <nicholas.hoath@intel.com>
Date: Fri Apr 10 13:12:26 2015 +0100
drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent
Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84af255..5afff3a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5791,6 +5791,7 @@ enum skl_disp_power_wells {
/* GEN8 chicken */
#define HDC_CHICKEN0 0x7300
+#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2e342db..643fe89 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1049,6 +1049,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t tmp;
gen9_init_workarounds(ring);
@@ -1057,8 +1058,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
STALL_DOP_GATING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:bxt */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+ tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+ if (INTEL_REVID(dev) >= BXT_REVID_B0)
+ tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+ WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
return 0;
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 13:08 ` Mika Kuoppala
2015-05-19 14:05 ` [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ Imre Deak
@ 2015-05-19 14:05 ` Imre Deak
2015-05-21 10:36 ` Mika Kuoppala
2015-05-21 7:45 ` [PATCH " shuang.he
3 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2015-05-19 14:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Mika Kuoppala
v2:
- set the override disable flag too on stepping F0 (mika)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 643fe89..2472415 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t tmp;
/* WaDisablePartialInstShootdown:skl,bxt */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+ tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
+ (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
+ tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+ WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+
return 0;
}
@@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- uint32_t tmp;
gen9_init_workarounds(ring);
@@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
- /* WaForceContextSaveRestoreNonCoherent:bxt */
- tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
- if (INTEL_REVID(dev) >= BXT_REVID_B0)
- tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
- WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
-
return 0;
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
` (2 preceding siblings ...)
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
@ 2015-05-19 14:39 ` Damien Lespiau
2015-05-19 14:46 ` Damien Lespiau
3 siblings, 1 reply; 17+ messages in thread
From: Damien Lespiau @ 2015-05-19 14:39 UTC (permalink / raw)
To: Imre Deak; +Cc: Daniel Vetter, intel-gfx
On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> Also make the WA comment consistent with the rest, where the stepping
> info is not shown.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> [ The patchset is a follow-up to:
> http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9b96ed7..461b9be 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> - /*
> - * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> - * the flag reads back as 0.
> - */
> - /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> - if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> + /* WaDisableMaskBasedCammingInRCC:skl,bxt */
For the record, there seem to be some confusion in the W/A db:
- The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
and indeed there's a bit to do that, but the bug in question talks
about bit 14 of 7308, which is the disabling bit for the RCC unit
- The W/A isn't listed in the W/A db for BXT
In doubt, defaulting to trusting the spec and bug db is probably the
saner option, so:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
> + (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> PIXEL_MASK_CAMMING_DISABLE);
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] drm/i915/skl: add F0 stepping ID
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
@ 2015-05-19 14:42 ` Damien Lespiau
2015-05-20 7:27 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Damien Lespiau @ 2015-05-19 14:42 UTC (permalink / raw)
To: Imre Deak; +Cc: Daniel Vetter, intel-gfx
On Tue, May 19, 2015 at 03:05:00PM +0300, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 840f08f..731b5ce 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
> #define SKL_REVID_C0 (0x2)
> #define SKL_REVID_D0 (0x3)
> #define SKL_REVID_E0 (0x4)
> +#define SKL_REVID_F0 (0x5)
>
> #define BXT_REVID_A0 (0x0)
> #define BXT_REVID_B0 (0x3)
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
@ 2015-05-19 14:46 ` Damien Lespiau
2015-05-19 14:52 ` Imre Deak
0 siblings, 1 reply; 17+ messages in thread
From: Damien Lespiau @ 2015-05-19 14:46 UTC (permalink / raw)
To: Imre Deak; +Cc: Daniel Vetter, intel-gfx
On Tue, May 19, 2015 at 03:39:25PM +0100, Damien Lespiau wrote:
> On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> > Also make the WA comment consistent with the rest, where the stepping
> > info is not shown.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> > 1 file changed, 3 insertions(+), 6 deletions(-)
> >
> > [ The patchset is a follow-up to:
> > http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 9b96ed7..461b9be 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > GEN9_CCS_TLB_PREFETCH_ENABLE);
> >
> > - /*
> > - * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > - * the flag reads back as 0.
> > - */
> > - /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > - if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> > + /* WaDisableMaskBasedCammingInRCC:skl,bxt */
>
> For the record, there seem to be some confusion in the W/A db:
>
> - The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
> and indeed there's a bit to do that, but the bug in question talks
> about bit 14 of 7308, which is the disabling bit for the RCC unit
> - The W/A isn't listed in the W/A db for BXT
>
> In doubt, defaulting to trusting the spec and bug db is probably the
> saner option, so:
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Spoke too soon. This register is in the render context so has to be
written from the ring...
--
Damien
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
2015-05-19 14:46 ` Damien Lespiau
@ 2015-05-19 14:52 ` Imre Deak
2015-05-19 14:56 ` Damien Lespiau
0 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2015-05-19 14:52 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Daniel Vetter, intel-gfx
On ti, 2015-05-19 at 15:46 +0100, Damien Lespiau wrote:
> On Tue, May 19, 2015 at 03:39:25PM +0100, Damien Lespiau wrote:
> > On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> > > Also make the WA comment consistent with the rest, where the stepping
> > > info is not shown.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> > > 1 file changed, 3 insertions(+), 6 deletions(-)
> > >
> > > [ The patchset is a follow-up to:
> > > http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index 9b96ed7..461b9be 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > > GEN9_CCS_TLB_PREFETCH_ENABLE);
> > >
> > > - /*
> > > - * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > > - * the flag reads back as 0.
> > > - */
> > > - /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > > - if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> > > + /* WaDisableMaskBasedCammingInRCC:skl,bxt */
> >
> > For the record, there seem to be some confusion in the W/A db:
> >
> > - The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
> > and indeed there's a bit to do that, but the bug in question talks
> > about bit 14 of 7308, which is the disabling bit for the RCC unit
> > - The W/A isn't listed in the W/A db for BXT
> >
> > In doubt, defaulting to trusting the spec and bug db is probably the
> > saner option, so:
> >
> > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> Spoke too soon. This register is in the render context so has to be
> written from the ring...
Not sure what you mean. I thought all WAs inited here are written from
the ring.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
2015-05-19 14:52 ` Imre Deak
@ 2015-05-19 14:56 ` Damien Lespiau
0 siblings, 0 replies; 17+ messages in thread
From: Damien Lespiau @ 2015-05-19 14:56 UTC (permalink / raw)
To: Imre Deak; +Cc: Daniel Vetter, intel-gfx
On Tue, May 19, 2015 at 05:52:27PM +0300, Imre Deak wrote:
> On ti, 2015-05-19 at 15:46 +0100, Damien Lespiau wrote:
> > On Tue, May 19, 2015 at 03:39:25PM +0100, Damien Lespiau wrote:
> > > On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> > > > Also make the WA comment consistent with the rest, where the stepping
> > > > info is not shown.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> > > > 1 file changed, 3 insertions(+), 6 deletions(-)
> > > >
> > > > [ The patchset is a follow-up to:
> > > > http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > index 9b96ed7..461b9be 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > > @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > > > GEN9_CCS_TLB_PREFETCH_ENABLE);
> > > >
> > > > - /*
> > > > - * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > > > - * the flag reads back as 0.
> > > > - */
> > > > - /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > > > - if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> > > > + /* WaDisableMaskBasedCammingInRCC:skl,bxt */
> > >
> > > For the record, there seem to be some confusion in the W/A db:
> > >
> > > - The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
> > > and indeed there's a bit to do that, but the bug in question talks
> > > about bit 14 of 7308, which is the disabling bit for the RCC unit
> > > - The W/A isn't listed in the W/A db for BXT
> > >
> > > In doubt, defaulting to trusting the spec and bug db is probably the
> > > saner option, so:
> > >
> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> >
> > Spoke too soon. This register is in the render context so has to be
> > written from the ring...
>
> Not sure what you mean. I thought all WAs inited here are written from
> the ring.
Oh, yes, excellent! r-b restored!
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] drm/i915/skl: add F0 stepping ID
2015-05-19 14:42 ` Damien Lespiau
@ 2015-05-20 7:27 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-05-20 7:27 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Daniel Vetter, intel-gfx
On Tue, May 19, 2015 at 03:42:45PM +0100, Damien Lespiau wrote:
> On Tue, May 19, 2015 at 03:05:00PM +0300, Imre Deak wrote:
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Merged the first 2 patches from this series to dinq, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 840f08f..731b5ce 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
> > #define SKL_REVID_C0 (0x2)
> > #define SKL_REVID_D0 (0x3)
> > #define SKL_REVID_E0 (0x4)
> > +#define SKL_REVID_F0 (0x5)
> >
> > #define BXT_REVID_A0 (0x0)
> > #define BXT_REVID_B0 (0x3)
> > --
> > 2.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
` (2 preceding siblings ...)
2015-05-19 14:05 ` [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
@ 2015-05-21 7:45 ` shuang.he
3 siblings, 0 replies; 17+ messages in thread
From: shuang.he @ 2015-05-21 7:45 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, imre.deak
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6433
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 234/234 234/234
ILK 262/262 262/262
SNB -1 282/282 281/282
IVB 300/300 300/300
BYT 254/254 254/254
BDW 275/275 275/275
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(10)PASS(1) DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-19 14:05 ` [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
@ 2015-05-21 10:36 ` Mika Kuoppala
2015-05-21 12:02 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2015-05-21 10:36 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Daniel Vetter
Imre Deak <imre.deak@intel.com> writes:
> v2:
> - set the override disable flag too on stepping F0 (mika)
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
[PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on
steppings B0+
And this patch,
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 643fe89..2472415 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> {
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
>
> /* WaDisablePartialInstShootdown:skl,bxt */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>
> + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
> + (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
> + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> +
> return 0;
> }
>
> @@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> {
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t tmp;
>
> gen9_init_workarounds(ring);
>
> @@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> STALL_DOP_GATING_DISABLE);
>
> - /* WaForceContextSaveRestoreNonCoherent:bxt */
> - tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> - if (INTEL_REVID(dev) >= BXT_REVID_B0)
> - tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> - WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> -
> return 0;
> }
>
> --
> 2.1.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
2015-05-21 10:36 ` Mika Kuoppala
@ 2015-05-21 12:02 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-05-21 12:02 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: Daniel Vetter, intel-gfx
On Thu, May 21, 2015 at 01:36:22PM +0300, Mika Kuoppala wrote:
> Imre Deak <imre.deak@intel.com> writes:
>
> > v2:
> > - set the override disable flag too on stepping F0 (mika)
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on
> steppings B0+
>
> And this patch,
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Both applied, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
> > 1 file changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 643fe89..2472415 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > {
> > struct drm_device *dev = ring->dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > + uint32_t tmp;
> >
> > /* WaDisablePartialInstShootdown:skl,bxt */
> > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> > @@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
> > GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> >
> > + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> > + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> > + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
> > + (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
> > + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> > + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> > +
> > return 0;
> > }
> >
> > @@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> > {
> > struct drm_device *dev = ring->dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > - uint32_t tmp;
> >
> > gen9_init_workarounds(ring);
> >
> > @@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> > STALL_DOP_GATING_DISABLE);
> >
> > - /* WaForceContextSaveRestoreNonCoherent:bxt */
> > - tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> > - if (INTEL_REVID(dev) >= BXT_REVID_B0)
> > - tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> > - WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> > -
> > return 0;
> > }
> >
> > --
> > 2.1.4
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2015-05-21 12:00 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
2015-05-19 14:42 ` Damien Lespiau
2015-05-20 7:27 ` Daniel Vetter
2015-05-19 12:05 ` [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing Imre Deak
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 13:08 ` Mika Kuoppala
2015-05-19 13:28 ` Imre Deak
2015-05-19 14:05 ` [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ Imre Deak
2015-05-19 14:05 ` [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-21 10:36 ` Mika Kuoppala
2015-05-21 12:02 ` Daniel Vetter
2015-05-21 7:45 ` [PATCH " shuang.he
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
2015-05-19 14:46 ` Damien Lespiau
2015-05-19 14:52 ` Imre Deak
2015-05-19 14:56 ` Damien Lespiau
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