* [PATCH v2 00/15] r8a7793 SoC, Gose board support
@ 2015-04-30 14:18 Ulrich Hecht
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (7 more replies)
0 siblings, 8 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: linux-sh
Hi!
Here is a revised set of patches adding R8A7793 (M2-N) support.
The major changes are that I dropped power management for now,
and that the PFC monster patch has been broken down for ease
of review. Also a lot of small errors, most spotted by Geert,
have been fixed.
CU
Uli
Changes since v1:
- pfc: split patch in six
- pfc: fixed typos
- dts: named clock bits correctly
- dts: made more consistent with the very similar r8a7791 dts
- dts: removed adv7511, don't know the address
- pm: dropped for now, needs to be fixed up first
- everywhere: renamed M2N -> M2-N (and M2 to M2-W, while at it)
- everywhere: added Acks
Ulrich Hecht (15):
pinctrl: sh-pfc: Add r8a7793 PFC support part 1: pinmux data
pinctrl: sh-pfc: Add r8a7793 PFC support part 2: pin groups
pinctrl: sh-pfc: Add r8a7793 PFC support part 3: pinmux config
registers
pinctrl: sh-pfc: Add r8a7793 pinmux info
pinctrl: sh-pfc: Enable building of r8a7793 PFC support
pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
ARM: shmobile: Basic r8a7793 SoC support
ARM: shmobile: add r8a7793 SoC device tree
ARM: shmobile: r8a7793: add Gose board device tree
ARM: shmobile: r8a7793: add SMP support
clk: shmobile: r8a7793: document DIV6 clock bindings
mmc: sh_mmcif: Document r8a7793 DT bindings
serial: sh-sci: Add device tree bindings for r8a7793
clk: shmobile: Add r8a7793 SoC to MSTP bindings
PCI: rcar: document r8a7793 DT bindings
.../bindings/clock/renesas,cpg-div6-clocks.txt | 3 +-
.../bindings/clock/renesas,cpg-mstp-clocks.txt | 3 +-
.../devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 +-
.../bindings/serial/renesas,sci-serial.txt | 12 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7793-gose.dts | 534 ++
arch/arm/boot/dts/r8a7793.dtsi | 1376 +++++
arch/arm/mach-shmobile/Kconfig | 4 +
arch/arm/mach-shmobile/Makefile | 2 +
arch/arm/mach-shmobile/r8a7793.h | 6 +
arch/arm/mach-shmobile/setup-r8a7793.c | 35 +
arch/arm/mach-shmobile/smp-r8a7793.c | 67 +
drivers/pinctrl/sh-pfc/Kconfig | 5 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/pfc-r8a7793.c | 6033 ++++++++++++++++++++
include/dt-bindings/clock/r8a7793-clock.h | 158 +
20 files changed, 8245 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7793-gose.dts
create mode 100644 arch/arm/boot/dts/r8a7793.dtsi
create mode 100644 arch/arm/mach-shmobile/r8a7793.h
create mode 100644 arch/arm/mach-shmobile/setup-r8a7793.c
create mode 100644 arch/arm/mach-shmobile/smp-r8a7793.c
create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7793.c
create mode 100644 include/dt-bindings/clock/r8a7793-clock.h
--
2.3.5
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-04-30 14:18 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index bfe72ec..6bcf851 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -16,7 +16,8 @@ Required Properties:
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
+ - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
+ - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
@ 2015-04-30 14:18 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index bfe72ec..6bcf851 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -16,7 +16,8 @@ Required Properties:
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
+ - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
+ - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
--
2.3.5
--
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^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-04-30 14:18 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
Hisashi Nakamura, Kazuya Mizuguchi, Hiroyuki Yokoyama,
Ryo Kataoka, Phil Edworthy, devicetree-u79uwXL29TY76Z2rM5mHXA
r8a7793 device tree including clock descriptions.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[uli: collapsed BSP revisions into a single commit, edited for style]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/r8a7793.dtsi | 1376 +++++++++++++++++++++++++++++
include/dt-bindings/clock/r8a7793-clock.h | 158 ++++
2 files changed, 1534 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7793.dtsi
create mode 100644 include/dt-bindings/clock/r8a7793-clock.h
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
new file mode 100644
index 0000000..52172b0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -0,0 +1,1376 @@
+/*
+ * Device Tree Source for the r8a7793 SoC
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7793-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "renesas,r8a7793";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ voltage-tolerance = <1>; /* 1% */
+ clocks = <&cpg_clocks R8A7793_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
+ };
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
+ 0 320 IRQ_TYPE_LEVEL_HIGH
+ 0 321 IRQ_TYPE_LEVEL_HIGH
+ 0 322 IRQ_TYPE_LEVEL_HIGH
+ 0 323 IRQ_TYPE_LEVEL_HIGH
+ 0 324 IRQ_TYPE_LEVEL_HIGH
+ 0 325 IRQ_TYPE_LEVEL_HIGH
+ 0 326 IRQ_TYPE_LEVEL_HIGH
+ 0 327 IRQ_TYPE_LEVEL_HIGH
+ 0 328 IRQ_TYPE_LEVEL_HIGH
+ 0 329 IRQ_TYPE_LEVEL_HIGH
+ 0 330 IRQ_TYPE_LEVEL_HIGH
+ 0 331 IRQ_TYPE_LEVEL_HIGH
+ 0 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
+ clock-names = "fck";
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
+ 0 333 IRQ_TYPE_LEVEL_HIGH
+ 0 334 IRQ_TYPE_LEVEL_HIGH
+ 0 335 IRQ_TYPE_LEVEL_HIGH
+ 0 336 IRQ_TYPE_LEVEL_HIGH
+ 0 337 IRQ_TYPE_LEVEL_HIGH
+ 0 338 IRQ_TYPE_LEVEL_HIGH
+ 0 339 IRQ_TYPE_LEVEL_HIGH
+ 0 340 IRQ_TYPE_LEVEL_HIGH
+ 0 341 IRQ_TYPE_LEVEL_HIGH
+ 0 342 IRQ_TYPE_LEVEL_HIGH
+ 0 343 IRQ_TYPE_LEVEL_HIGH
+ 0 344 IRQ_TYPE_LEVEL_HIGH
+ 0 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
+ clock-names = "fck";
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audmapp: dma-controller@0xec740000 {
+ compatible = "renesas,rcar-audmapp";
+ #dma-cells = <1>;
+
+ reg = <0 0xec740000 0 0x200>;
+ };
+
+ /* The memory map in the User's Manual maps the cores to bus numbers */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
+ status = "disabled";
+ };
+
+ pfc: pfc@e6060000 {
+ compatible = "renesas,pfc-r8a7793";
+ reg = <0 0xe6060000 0 0x250>;
+ #gpio-range-cells = <3>;
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee100000 0 0x200>;
+ dma-names = "tx", "rx";
+ interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
+ cap-uhs-sdr104;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <195000000>;
+ renesas,mmc-scc-tapnum = <8>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <0>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee140000 0 0x100>;
+ dma-names = "tx", "rx";
+ interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <97500000>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <1>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee160000 0 0x100>;
+ dma-names = "tx", "rx";
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <97500000>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <2>;
+ status = "disabled";
+ };
+
+ mmcif0: mmcif@ee200000 {
+ compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ dma-names = "tx", "rx";
+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
+ reg-io-width = <4>;
+ renesas,clk-rate = <97500000>;
+ status = "disabled";
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6c20000 0 64>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6c30000 0 64>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 64>;
+ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF3>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF4>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF5>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7793";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7793";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_SATA0>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7793";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_SATA1>;
+ status = "disabled";
+ };
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* External root clock */
+ extal_clk: extal_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ clock-output-names = "extal";
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed
+ * frequency clocks by default. Boards that provide audio
+ * clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_a";
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_b";
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_c";
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "pcie_bus";
+ status = "disabled";
+ };
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7793-cpg-clocks",
+ "renesas,rcar-gen2-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1", "pll3",
+ "lb", "qspi", "sdh", "sd0", "z";
+ };
+
+ /* Variable factor clocks */
+ sd2_clk: sd2_clk@e6150078 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150078 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd2";
+ };
+ sd3_clk: sd3_clk@e615026c {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe615026c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd3";
+ };
+ mmc0_clk: mmc0_clk@e6150240 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150240 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc0";
+ };
+ ssp_clk: ssp_clk@e6150248 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150248 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssp";
+ };
+ ssprs_clk: ssprs_clk@e615024c {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe615024c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssprs";
+ };
+
+ /* Fixed factor clocks */
+ pll1_div2_clk: pll1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "pll1_div2";
+ };
+ zg_clk: zg_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <5>;
+ clock-mult = <1>;
+ clock-output-names = "zg";
+ };
+ zx_clk: zx_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ clock-output-names = "zx";
+ };
+ zs_clk: zs_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ clock-output-names = "zs";
+ };
+ hp_clk: hp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "hp";
+ };
+ i_clk: i_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "i";
+ };
+ b_clk: b_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "b";
+ };
+ p_clk: p_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <24>;
+ clock-mult = <1>;
+ clock-output-names = "p";
+ };
+ cl_clk: cl_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <48>;
+ clock-mult = <1>;
+ clock-output-names = "cl";
+ };
+ m2_clk: m2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "m2";
+ };
+ imp_clk: imp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "imp";
+ };
+ rclk_clk: rclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(48 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "rclk";
+ };
+ oscclk_clk: oscclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(12 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "oscclk";
+ };
+ zb3_clk: zb3_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "zb3";
+ };
+ zb3d2_clk: zb3d2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "zb3d2";
+ };
+ ddr_clk: ddr_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "ddr";
+ };
+ mp_clk: mp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <15>;
+ clock-mult = <1>;
+ clock-output-names = "mp";
+ };
+ cp_clk: cp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&extal_clk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "cp";
+ };
+
+ /* Gate clocks */
+ mstp0_clks: mstp0_clks@e6150130 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+ clocks = <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7793_CLK_MSIOF0>;
+ clock-output-names = "msiof0";
+ };
+ mstp1_clks: mstp1_clks@e6150134 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+ <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+ <&zs_clk>, <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
+ R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
+ R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
+ R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
+ R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
+ R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
+ R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
+ R8A7793_CLK_VSP1_S
+ >;
+ clock-output-names + "vcp0", "vpc0", "ssp_dev", "tmu1",
+ "pvrsrvkm", "tddmac", "fdp1", "fdp0",
+ "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+ "vsp1-du0", "vsps";
+ };
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1
+ R8A7793_CLK_SCIFA0 R8A7793_CLK_MSIOF2
+ R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1
+ R8A7793_CLK_MSIOF1 R8A7793_CLK_SCIFB2
+ R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
+ >;
+ clock-output-names + "scifa2", "scifa1", "scifa0", "msiof2",
+ "scifb0", "scifb1", "msiof1", "scifb2",
+ "sys-dmac1", "sys-dmac0";
+ };
+ mstp3_clks: mstp3_clks@e615013c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+ clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
+ <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
+ <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
+ <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
+ R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
+ R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
+ R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
+ R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
+ R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
+ >;
+ clock-output-names + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
+ "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+ "usbdmac0", "usbdmac1";
+ };
+ mstp5_clks: mstp5_clks@e6150144 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&extal_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7793_CLK_AUDIO_DMAC0
+ R8A7793_CLK_AUDIO_DMAC1
+ R8A7793_CLK_THERMAL
+ R8A7793_CLK_PWM>;
+ clock-output-names + "audmac0", "audmac1", "thermal", "pwm";
+ };
+ mstp7_clks: mstp7_clks@e615014c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
+ <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
+ <&zx_clk>, <&zx_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
+ R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
+ R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
+ R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
+ R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
+ R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
+ R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
+ >;
+ clock-output-names + "ehci", "hsusb", "hscif2", "scif5", "scif4",
+ "hscif1", "hscif0", "scif3", "scif2",
+ "scif1", "scif0", "du1", "du0", "lvds0";
+ };
+ mstp8_clks: mstp8_clks@e6150990 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+ clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+ <&p_clk>, <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
+ R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
+ R8A7793_CLK_ETHER R8A7793_CLK_SATA1
+ R8A7793_CLK_SATA0
+ >;
+ clock-output-names + "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
+ "sata1", "sata0";
+ };
+ mstp9_clks: mstp9_clks@e6150994 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&p_clk>, <&p_clk>,
+ <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
+ <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+ <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
+ R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
+ R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
+ R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
+ R8A7793_CLK_RCAN1 R8A7793_CLK_RCAN0
+ R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
+ R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
+ R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
+ R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
+ >;
+ clock-output-names + "gpio7", "gpio6", "gpio5", "gpio4", "gpio3",
+ "gpio2", "gpio1", "gpio0", "rcan1", "rcan0",
+ "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
+ "i2c2", "i2c1", "i2c0";
+ };
+ mstp10_clks: mstp10_clks@e6150998 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+ clocks = <&p_clk>, /* parent of SCU */
+ <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
+
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCU_ALL
+ R8A7793_CLK_SSI_ALL
+
+ R8A7793_CLK_SSI9 R8A7793_CLK_SSI8
+ R8A7793_CLK_SSI7 R8A7793_CLK_SSI6
+ R8A7793_CLK_SSI5
+
+ R8A7793_CLK_SSI4 R8A7793_CLK_SSI3
+ R8A7793_CLK_SSI2 R8A7793_CLK_SSI1
+ R8A7793_CLK_SSI0
+
+ R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
+
+ R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8
+ R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6
+ R8A7793_CLK_SCU_SRC5
+
+ R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3
+ R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1
+ R8A7793_CLK_SCU_SRC0
+ >;
+ clock-output-names + "scu", "ssi",
+ "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+ "dvc1", "dvc0",
+ "src9", "src8", "src7", "src6", "src5",
+ "src4", "src3", "src2", "src1", "src0";
+ };
+ mstp11_clks: mstp11_clks@e615099c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4
+ R8A7793_CLK_SCIFA5
+ >;
+ clock-output-names = "scifa3", "scifa4", "scifa5";
+ };
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7793_CLK_MSIOF0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
+ interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_MSIOF1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
+ interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_MSIOF2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7793";
+ device_type = "pci";
+ clocks = <&mstp7_clks R8A7793_CLK_EHCI>;
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7793";
+ device_type = "pci";
+ clocks = <&mstp7_clks R8A7793_CLK_EHCI>;
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7793";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0 117 IRQ_TYPE_LEVEL_HIGH>,
+ <0 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_PCIEC>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ status = "disabled";
+ };
+
+ rcar_sound: sound@0xec500000 {
+ #sound-dai-cells = <1>;
+ compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x1280>; /* SSI */
+ clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
+ <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
+ <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
+ <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
+ <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
+ <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
+ clock-names = "ssi",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>,
+ <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>,
+ <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>,
+ <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>,
+ <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>,
+ <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>,
+ <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>,
+ <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>,
+ <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>,
+ <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>,
+
+ <&audma0 0x85>, <&audma1 0x9a>, <&audma0 0xbc>,
+ <&audma0 0x87>, <&audma1 0x9c>, <&audma0 0xbe>,
+ <&audma0 0x89>, <&audma1 0x9e>,
+ <&audma0 0x8b>, <&audma1 0xa0>,
+ <&audma0 0x8d>, <&audma1 0xb0>,
+ <&audma0 0x8f>, <&audma1 0xb2>,
+ <&audma0 0x91>, <&audma1 0xb4>,
+ <&audma0 0x93>, <&audma1 0xb6>,
+ <&audma0 0x95>, <&audma1 0xb8>,
+ <&audma0 0x97>, <&audma1 0xba>,
+
+ <&audmapp 0x2d00>, <&audmapp 0x2e00>, <&audmapp 0x2f00>, <&audmapp 0x3000>, <&audmapp 0x3100>,
+ <&audmapp 0x2d04>, <&audmapp 0x2e04>, <&audmapp 0x2f04>, <&audmapp 0x3004>, <&audmapp 0x3104>,
+ <&audmapp 0x2d08>, <&audmapp 0x2e08>, <&audmapp 0x2f08>, <&audmapp 0x3008>, <&audmapp 0x3108>,
+ <&audmapp 0x2d0c>, <&audmapp 0x2e0c>, <&audmapp 0x2f0c>, <&audmapp 0x300c>, <&audmapp 0x310c>,
+ <&audmapp 0x2d0d>, <&audmapp 0x2e0d>, <&audmapp 0x2f0d>, <&audmapp 0x300d>, <&audmapp 0x310d>,
+ <&audmapp 0x2d0e>, <&audmapp 0x2e0e>, <&audmapp 0x2f0e>, <&audmapp 0x300e>, <&audmapp 0x310e>,
+ <&audmapp 0x2d0f>, <&audmapp 0x2e0f>, <&audmapp 0x2f0f>, <&audmapp 0x300f>, <&audmapp 0x310f>,
+ <&audmapp 0x2d10>, <&audmapp 0x2e10>, <&audmapp 0x2f10>, <&audmapp 0x3010>, <&audmapp 0x3110>,
+ <&audmapp 0x2d11>, <&audmapp 0x2e11>, <&audmapp 0x2f11>, <&audmapp 0x3011>, <&audmapp 0x3111>,
+ <&audmapp 0x2d12>, <&audmapp 0x2e12>, <&audmapp 0x2f12>, <&audmapp 0x3012>, <&audmapp 0x3112>,
+
+ <&audmapp 0x3200>, <&audmapp 0x3300>, <&audmapp 0x3400>, <&audmapp 0x3500>, <&audmapp 0x3600>,
+ <&audmapp 0x3204>, <&audmapp 0x3304>, <&audmapp 0x3404>, <&audmapp 0x3504>, <&audmapp 0x3604>,
+ <&audmapp 0x3208>, <&audmapp 0x3308>, <&audmapp 0x3408>, <&audmapp 0x3508>, <&audmapp 0x3608>,
+ <&audmapp 0x320c>, <&audmapp 0x330c>, <&audmapp 0x340c>, <&audmapp 0x350c>, <&audmapp 0x360c>,
+ <&audmapp 0x320d>, <&audmapp 0x330d>, <&audmapp 0x340d>, <&audmapp 0x350d>, <&audmapp 0x360d>,
+ <&audmapp 0x320e>, <&audmapp 0x330e>, <&audmapp 0x340e>, <&audmapp 0x350e>, <&audmapp 0x360e>,
+ <&audmapp 0x320f>, <&audmapp 0x330f>, <&audmapp 0x340f>, <&audmapp 0x350f>, <&audmapp 0x360f>,
+ <&audmapp 0x3210>, <&audmapp 0x3310>, <&audmapp 0x3410>, <&audmapp 0x3510>, <&audmapp 0x3610>,
+ <&audmapp 0x3211>, <&audmapp 0x3311>, <&audmapp 0x3411>, <&audmapp 0x3511>, <&audmapp 0x3611>,
+ <&audmapp 0x3212>, <&audmapp 0x3312>, <&audmapp 0x3412>, <&audmapp 0x3512>, <&audmapp 0x3612>,
+
+ <&audmapp 0x002d>, <&audmapp 0x002e>, <&audmapp 0x002f>, <&audmapp 0x0030>, <&audmapp 0x0031>,
+ <&audmapp 0x042d>, <&audmapp 0x042e>, <&audmapp 0x042f>, <&audmapp 0x0430>, <&audmapp 0x0431>,
+ <&audmapp 0x082d>, <&audmapp 0x082e>, <&audmapp 0x082f>, <&audmapp 0x0830>, <&audmapp 0x0831>,
+ <&audmapp 0x0c2d>, <&audmapp 0x0c2e>, <&audmapp 0x0c2f>, <&audmapp 0x0c30>, <&audmapp 0x0c31>,
+ <&audmapp 0x0d2d>, <&audmapp 0x0d2e>, <&audmapp 0x0d2f>, <&audmapp 0x0d30>, <&audmapp 0x0d31>,
+ <&audmapp 0x0e2d>, <&audmapp 0x0e2e>, <&audmapp 0x0e2f>, <&audmapp 0x0e30>, <&audmapp 0x0e31>,
+ <&audmapp 0x0f2d>, <&audmapp 0x0f2e>, <&audmapp 0x0f2f>, <&audmapp 0x0f30>, <&audmapp 0x0f31>,
+ <&audmapp 0x102d>, <&audmapp 0x102e>, <&audmapp 0x102f>, <&audmapp 0x1030>, <&audmapp 0x1031>,
+ <&audmapp 0x112d>, <&audmapp 0x112e>, <&audmapp 0x112f>, <&audmapp 0x1130>, <&audmapp 0x1131>,
+ <&audmapp 0x122d>, <&audmapp 0x122e>, <&audmapp 0x122f>, <&audmapp 0x1230>, <&audmapp 0x1231>,
+
+ <&audmapp 0x0032>, <&audmapp 0x0033>, <&audmapp 0x0034>, <&audmapp 0x0035>, <&audmapp 0x0036>,
+ <&audmapp 0x0432>, <&audmapp 0x0433>, <&audmapp 0x0434>, <&audmapp 0x0435>, <&audmapp 0x0436>,
+ <&audmapp 0x0832>, <&audmapp 0x0833>, <&audmapp 0x0834>, <&audmapp 0x0835>, <&audmapp 0x0836>,
+ <&audmapp 0x0c32>, <&audmapp 0x0c33>, <&audmapp 0x0c34>, <&audmapp 0x0c35>, <&audmapp 0x0c36>,
+ <&audmapp 0x0d32>, <&audmapp 0x0d33>, <&audmapp 0x0d34>, <&audmapp 0x0d35>, <&audmapp 0x0d36>,
+ <&audmapp 0x0e32>, <&audmapp 0x0e33>, <&audmapp 0x0e34>, <&audmapp 0x0e35>, <&audmapp 0x0e36>,
+ <&audmapp 0x0f32>, <&audmapp 0x0f33>, <&audmapp 0x0f34>, <&audmapp 0x0f35>, <&audmapp 0x0f36>,
+ <&audmapp 0x1032>, <&audmapp 0x1033>, <&audmapp 0x1034>, <&audmapp 0x1035>, <&audmapp 0x1036>,
+ <&audmapp 0x1132>, <&audmapp 0x1133>, <&audmapp 0x1134>, <&audmapp 0x1135>, <&audmapp 0x1136>,
+ <&audmapp 0x1232>, <&audmapp 0x1233>, <&audmapp 0x1234>, <&audmapp 0x1235>, <&audmapp 0x1236>;
+
+ dma-names = "mem_ssi0", "ssi0_mem", "mem_ssiu0", "ssiu0_mem",
+ "mem_ssi1", "ssi1_mem", "mem_ssiu1", "ssiu1_mem",
+ "mem_ssi2", "ssi2_mem", "mem_ssiu2", "ssiu2_mem",
+ "mem_ssi3", "ssi3_mem", "mem_ssiu3", "ssiu3_mem",
+ "mem_ssi4", "ssi4_mem", "mem_ssiu4", "ssiu4_mem",
+ "mem_ssi5", "ssi5_mem", "mem_ssiu5", "ssiu5_mem",
+ "mem_ssi6", "ssi6_mem", "mem_ssiu6", "ssiu6_mem",
+ "mem_ssi7", "ssi7_mem", "mem_ssiu7", "ssiu7_mem",
+ "mem_ssi8", "ssi8_mem", "mem_ssiu8", "ssiu8_mem",
+ "mem_ssi9", "ssi9_mem", "mem_ssiu9", "ssiu9_mem",
+
+ "mem_src0", "src0_mem", "dvc0_mem",
+ "mem_src1", "src1_mem", "dvc1_mem",
+ "mem_src2", "src2_mem",
+ "mem_src3", "src3_mem",
+ "mem_src4", "src4_mem",
+ "mem_src5", "src5_mem",
+ "mem_src6", "src6_mem",
+ "mem_src7", "src7_mem",
+ "mem_src8", "src8_mem",
+ "mem_src9", "src9_mem",
+
+ "src0_ssiu0", "src1_ssiu0", "src2_ssiu0", "src3_ssiu0", "src4_ssiu0",
+ "src0_ssiu1", "src1_ssiu1", "src2_ssiu1", "src3_ssiu1", "src4_ssiu1",
+ "src0_ssiu2", "src1_ssiu2", "src2_ssiu2", "src3_ssiu2", "src4_ssiu2",
+ "src0_ssiu3", "src1_ssiu3", "src2_ssiu3", "src3_ssiu3", "src4_ssiu3",
+ "src0_ssiu4", "src1_ssiu4", "src2_ssiu4", "src3_ssiu4", "src4_ssiu4",
+ "src0_ssiu5", "src1_ssiu5", "src2_ssiu5", "src3_ssiu5", "src4_ssiu5",
+ "src0_ssiu6", "src1_ssiu6", "src2_ssiu6", "src3_ssiu6", "src4_ssiu6",
+ "src0_ssiu7", "src1_ssiu7", "src2_ssiu7", "src3_ssiu7", "src4_ssiu7",
+ "src0_ssiu8", "src1_ssiu8", "src2_ssiu8", "src3_ssiu8", "src4_ssiu8",
+ "src0_ssiu9", "src1_ssiu9", "src2_ssiu9", "src3_ssiu9", "src4_ssiu9",
+
+ "src5_ssiu0", "src6_ssiu0", "src7_ssiu0", "src8_ssiu0", "src9_ssiu0",
+ "src5_ssiu1", "src6_ssiu1", "src7_ssiu1", "src8_ssiu1", "src9_ssiu1",
+ "src5_ssiu2", "src6_ssiu2", "src7_ssiu2", "src8_ssiu2", "src9_ssiu2",
+ "src5_ssiu3", "src6_ssiu3", "src7_ssiu3", "src8_ssiu3", "src9_ssiu3",
+ "src5_ssiu4", "src6_ssiu4", "src7_ssiu4", "src8_ssiu4", "src9_ssiu4",
+ "src5_ssiu5", "src6_ssiu5", "src7_ssiu5", "src8_ssiu5", "src9_ssiu5",
+ "src5_ssiu6", "src6_ssiu6", "src7_ssiu6", "src8_ssiu6", "src9_ssiu6",
+ "src5_ssiu7", "src6_ssiu7", "src7_ssiu7", "src8_ssiu7", "src9_ssiu7",
+ "src5_ssiu8", "src6_ssiu8", "src7_ssiu8", "src8_ssiu8", "src9_ssiu8",
+ "src5_ssiu9", "src6_ssiu9", "src7_ssiu9", "src8_ssiu9", "src9_ssiu9",
+
+ "ssiu0_src0", "ssiu0_src1", "ssiu0_src2", "ssiu0_src3", "ssiu0_src4",
+ "ssiu1_src0", "ssiu1_src1", "ssiu1_src2", "ssiu1_src3", "ssiu1_src4",
+ "ssiu2_src0", "ssiu2_src1", "ssiu2_src2", "ssiu2_src3", "ssiu2_src4",
+ "ssiu3_src0", "ssiu3_src1", "ssiu3_src2", "ssiu3_src3", "ssiu3_src4",
+ "ssiu4_src0", "ssiu4_src1", "ssiu4_src2", "ssiu4_src3", "ssiu4_src4",
+ "ssiu5_src0", "ssiu5_src1", "ssiu5_src2", "ssiu5_src3", "ssiu5_src4",
+ "ssiu6_src0", "ssiu6_src1", "ssiu6_src2", "ssiu6_src3", "ssiu6_src4",
+ "ssiu7_src0", "ssiu7_src1", "ssiu7_src2", "ssiu7_src3", "ssiu7_src4",
+ "ssiu8_src0", "ssiu8_src1", "ssiu8_src2", "ssiu8_src3", "ssiu8_src4",
+ "ssiu9_src0", "ssiu9_src1", "ssiu9_src2", "ssiu9_src3", "ssiu9_src4",
+
+ "ssiu0_src5", "ssiu0_src6", "ssiu0_src7", "ssiu0_src8", "ssiu0_src9",
+ "ssiu1_src5", "ssiu1_src6", "ssiu1_src7", "ssiu1_src8", "ssiu1_src9",
+ "ssiu2_src5", "ssiu2_src6", "ssiu2_src7", "ssiu2_src8", "ssiu2_src9",
+ "ssiu3_src5", "ssiu3_src6", "ssiu3_src7", "ssiu3_src8", "ssiu3_src9",
+ "ssiu4_src5", "ssiu4_src6", "ssiu4_src7", "ssiu4_src8", "ssiu4_src9",
+ "ssiu5_src5", "ssiu5_src6", "ssiu5_src7", "ssiu5_src8", "ssiu5_src9",
+ "ssiu6_src5", "ssiu6_src6", "ssiu6_src7", "ssiu6_src8", "ssiu6_src9",
+ "ssiu7_src5", "ssiu7_src6", "ssiu7_src7", "ssiu7_src8", "ssiu7_src9",
+ "ssiu8_src5", "ssiu8_src6", "ssiu8_src7", "ssiu8_src8", "ssiu8_src9",
+ "ssiu9_src5", "ssiu9_src6", "ssiu9_src7", "ssiu9_src8", "ssiu9_src9";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc@0 { };
+ dvc1: dvc@1 { };
+ };
+
+ rcar_sound,src {
+ src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
+ src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
+ src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
+ src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
+ src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
+ src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
+ src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
+ src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
+ src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
+ src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
new file mode 100644
index 0000000..fab3b21
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -0,0 +1,158 @@
+/*
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN 0
+#define R8A7793_CLK_PLL0 1
+#define R8A7793_CLK_PLL1 2
+#define R8A7793_CLK_PLL3 3
+#define R8A7793_CLK_LB 4
+#define R8A7793_CLK_QSPI 5
+#define R8A7793_CLK_SDH 6
+#define R8A7793_CLK_SD0 7
+#define R8A7793_CLK_Z 8
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0 1
+#define R8A7793_CLK_VPC0 3
+#define R8A7793_CLK_SSP1 9
+#define R8A7793_CLK_TMU1 11
+#define R8A7793_CLK_3DG 12
+#define R8A7793_CLK_2DDMAC 15
+#define R8A7793_CLK_FDP1_1 18
+#define R8A7793_CLK_FDP1_0 19
+#define R8A7793_CLK_TMU3 21
+#define R8A7793_CLK_TMU2 22
+#define R8A7793_CLK_CMT0 24
+#define R8A7793_CLK_TMU0 25
+#define R8A7793_CLK_VSP1_DU1 27
+#define R8A7793_CLK_VSP1_DU0 28
+#define R8A7793_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2 2
+#define R8A7793_CLK_SCIFA1 3
+#define R8A7793_CLK_SCIFA0 4
+#define R8A7793_CLK_MSIOF2 5
+#define R8A7793_CLK_SCIFB0 6
+#define R8A7793_CLK_SCIFB1 7
+#define R8A7793_CLK_MSIOF1 8
+#define R8A7793_CLK_SCIFB2 16
+#define R8A7793_CLK_SYS_DMAC1 18
+#define R8A7793_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0 4
+#define R8A7793_CLK_SDHI2 11
+#define R8A7793_CLK_SDHI1 12
+#define R8A7793_CLK_SDHI0 14
+#define R8A7793_CLK_MMCIF0 15
+#define R8A7793_CLK_IIC0 18
+#define R8A7793_CLK_PCIEC 19
+#define R8A7793_CLK_IIC1 23
+#define R8A7793_CLK_SSUSB 28
+#define R8A7793_CLK_CMT1 29
+#define R8A7793_CLK_USBDMAC0 30
+#define R8A7793_CLK_USBDMAC1 31
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1 1
+#define R8A7793_CLK_AUDIO_DMAC0 2
+#define R8A7793_CLK_THERMAL 22
+#define R8A7793_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI 3
+#define R8A7793_CLK_HSUSB 4
+#define R8A7793_CLK_HSCIF2 13
+#define R8A7793_CLK_SCIF5 14
+#define R8A7793_CLK_SCIF4 15
+#define R8A7793_CLK_HSCIF1 16
+#define R8A7793_CLK_HSCIF0 17
+#define R8A7793_CLK_SCIF3 18
+#define R8A7793_CLK_SCIF2 19
+#define R8A7793_CLK_SCIF1 20
+#define R8A7793_CLK_SCIF0 21
+#define R8A7793_CLK_DU1 23
+#define R8A7793_CLK_DU0 24
+#define R8A7793_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX 0
+#define R8A7793_CLK_VIN2 9
+#define R8A7793_CLK_VIN1 10
+#define R8A7793_CLK_VIN0 11
+#define R8A7793_CLK_ETHER 13
+#define R8A7793_CLK_SATA1 14
+#define R8A7793_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7 4
+#define R8A7793_CLK_GPIO6 5
+#define R8A7793_CLK_GPIO5 7
+#define R8A7793_CLK_GPIO4 8
+#define R8A7793_CLK_GPIO3 9
+#define R8A7793_CLK_GPIO2 10
+#define R8A7793_CLK_GPIO1 11
+#define R8A7793_CLK_GPIO0 12
+#define R8A7793_CLK_RCAN1 15
+#define R8A7793_CLK_RCAN0 16
+#define R8A7793_CLK_QSPI_MOD 17
+#define R8A7793_CLK_I2C5 25
+#define R8A7793_CLK_IICDVFS 26
+#define R8A7793_CLK_I2C4 27
+#define R8A7793_CLK_I2C3 28
+#define R8A7793_CLK_I2C2 29
+#define R8A7793_CLK_I2C1 30
+#define R8A7793_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL 5
+#define R8A7793_CLK_SSI9 6
+#define R8A7793_CLK_SSI8 7
+#define R8A7793_CLK_SSI7 8
+#define R8A7793_CLK_SSI6 9
+#define R8A7793_CLK_SSI5 10
+#define R8A7793_CLK_SSI4 11
+#define R8A7793_CLK_SSI3 12
+#define R8A7793_CLK_SSI2 13
+#define R8A7793_CLK_SSI1 14
+#define R8A7793_CLK_SSI0 15
+#define R8A7793_CLK_SCU_ALL 17
+#define R8A7793_CLK_SCU_DVC1 18
+#define R8A7793_CLK_SCU_DVC0 19
+#define R8A7793_CLK_SCU_SRC9 22
+#define R8A7793_CLK_SCU_SRC8 23
+#define R8A7793_CLK_SCU_SRC7 24
+#define R8A7793_CLK_SCU_SRC6 25
+#define R8A7793_CLK_SCU_SRC5 26
+#define R8A7793_CLK_SCU_SRC4 27
+#define R8A7793_CLK_SCU_SRC3 28
+#define R8A7793_CLK_SCU_SRC2 29
+#define R8A7793_CLK_SCU_SRC1 30
+#define R8A7793_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3 6
+#define R8A7793_CLK_SCIFA4 7
+#define R8A7793_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree
@ 2015-04-30 14:18 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
Hisashi Nakamura, Kazuya Mizuguchi, Hiroyuki Yokoyama,
Ryo Kataoka, Phil Edworthy, devicetree-u79uwXL29TY76Z2rM5mHXA
r8a7793 device tree including clock descriptions.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Phil Edworthy <phil.edworthy-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
[uli: collapsed BSP revisions into a single commit, edited for style]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
arch/arm/boot/dts/r8a7793.dtsi | 1376 +++++++++++++++++++++++++++++
include/dt-bindings/clock/r8a7793-clock.h | 158 ++++
2 files changed, 1534 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7793.dtsi
create mode 100644 include/dt-bindings/clock/r8a7793-clock.h
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
new file mode 100644
index 0000000..52172b0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -0,0 +1,1376 @@
+/*
+ * Device Tree Source for the r8a7793 SoC
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7793-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "renesas,r8a7793";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ spi0 = &qspi;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ voltage-tolerance = <1>; /* 1% */
+ clocks = <&cpg_clocks R8A7793_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
+ };
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
+ 0 320 IRQ_TYPE_LEVEL_HIGH
+ 0 321 IRQ_TYPE_LEVEL_HIGH
+ 0 322 IRQ_TYPE_LEVEL_HIGH
+ 0 323 IRQ_TYPE_LEVEL_HIGH
+ 0 324 IRQ_TYPE_LEVEL_HIGH
+ 0 325 IRQ_TYPE_LEVEL_HIGH
+ 0 326 IRQ_TYPE_LEVEL_HIGH
+ 0 327 IRQ_TYPE_LEVEL_HIGH
+ 0 328 IRQ_TYPE_LEVEL_HIGH
+ 0 329 IRQ_TYPE_LEVEL_HIGH
+ 0 330 IRQ_TYPE_LEVEL_HIGH
+ 0 331 IRQ_TYPE_LEVEL_HIGH
+ 0 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
+ clock-names = "fck";
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
+ 0 333 IRQ_TYPE_LEVEL_HIGH
+ 0 334 IRQ_TYPE_LEVEL_HIGH
+ 0 335 IRQ_TYPE_LEVEL_HIGH
+ 0 336 IRQ_TYPE_LEVEL_HIGH
+ 0 337 IRQ_TYPE_LEVEL_HIGH
+ 0 338 IRQ_TYPE_LEVEL_HIGH
+ 0 339 IRQ_TYPE_LEVEL_HIGH
+ 0 340 IRQ_TYPE_LEVEL_HIGH
+ 0 341 IRQ_TYPE_LEVEL_HIGH
+ 0 342 IRQ_TYPE_LEVEL_HIGH
+ 0 343 IRQ_TYPE_LEVEL_HIGH
+ 0 344 IRQ_TYPE_LEVEL_HIGH
+ 0 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
+ clock-names = "fck";
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audmapp: dma-controller@0xec740000 {
+ compatible = "renesas,rcar-audmapp";
+ #dma-cells = <1>;
+
+ reg = <0 0xec740000 0 0x200>;
+ };
+
+ /* The memory map in the User's Manual maps the cores to bus numbers */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
+ status = "disabled";
+ };
+
+ pfc: pfc@e6060000 {
+ compatible = "renesas,pfc-r8a7793";
+ reg = <0 0xe6060000 0 0x250>;
+ #gpio-range-cells = <3>;
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee100000 0 0x200>;
+ dma-names = "tx", "rx";
+ interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
+ cap-uhs-sdr104;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <195000000>;
+ renesas,mmc-scc-tapnum = <8>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <0>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee140000 0 0x100>;
+ dma-names = "tx", "rx";
+ interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <97500000>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <1>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7793";
+ reg = <0 0xee160000 0 0x100>;
+ dma-names = "tx", "rx";
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
+ cap-uhs-sdr50;
+ dma-xmit-sz = <32>;
+ renesas,clk-rate = <97500000>;
+ renesas,pfcs = <0xe6060000 0x8c>;
+ renesas,id = <2>;
+ status = "disabled";
+ };
+
+ mmcif0: mmcif@ee200000 {
+ compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ dma-names = "tx", "rx";
+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
+ reg-io-width = <4>;
+ renesas,clk-rate = <97500000>;
+ status = "disabled";
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6c20000 0 64>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6c30000 0 64>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 64>;
+ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF3>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF4>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7793", "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_SCIF5>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>;
+ clock-names = "sci_ick";
+ status = "disabled";
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7793";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7793";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_SATA0>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7793";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7793_CLK_SATA1>;
+ status = "disabled";
+ };
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* External root clock */
+ extal_clk: extal_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ clock-output-names = "extal";
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed
+ * frequency clocks by default. Boards that provide audio
+ * clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_a";
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_b";
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "audio_clk_c";
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "pcie_bus";
+ status = "disabled";
+ };
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7793-cpg-clocks",
+ "renesas,rcar-gen2-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "main", "pll0", "pll1", "pll3",
+ "lb", "qspi", "sdh", "sd0", "z";
+ };
+
+ /* Variable factor clocks */
+ sd2_clk: sd2_clk@e6150078 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150078 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd2";
+ };
+ sd3_clk: sd3_clk@e615026c {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe615026c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sd3";
+ };
+ mmc0_clk: mmc0_clk@e6150240 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150240 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "mmc0";
+ };
+ ssp_clk: ssp_clk@e6150248 {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe6150248 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssp";
+ };
+ ssprs_clk: ssprs_clk@e615024c {
+ compatible = "renesas,r8a7793-div6-clock",
+ "renesas,cpg-div6-clock";
+ reg = <0 0xe615024c 0 4>;
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "ssprs";
+ };
+
+ /* Fixed factor clocks */
+ pll1_div2_clk: pll1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "pll1_div2";
+ };
+ zg_clk: zg_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <5>;
+ clock-mult = <1>;
+ clock-output-names = "zg";
+ };
+ zx_clk: zx_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ clock-output-names = "zx";
+ };
+ zs_clk: zs_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <6>;
+ clock-mult = <1>;
+ clock-output-names = "zs";
+ };
+ hp_clk: hp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "hp";
+ };
+ i_clk: i_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "i";
+ };
+ b_clk: b_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ clock-output-names = "b";
+ };
+ p_clk: p_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <24>;
+ clock-mult = <1>;
+ clock-output-names = "p";
+ };
+ cl_clk: cl_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <48>;
+ clock-mult = <1>;
+ clock-output-names = "cl";
+ };
+ m2_clk: m2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "m2";
+ };
+ imp_clk: imp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "imp";
+ };
+ rclk_clk: rclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(48 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "rclk";
+ };
+ oscclk_clk: oscclk_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+ #clock-cells = <0>;
+ clock-div = <(12 * 1024)>;
+ clock-mult = <1>;
+ clock-output-names = "oscclk";
+ };
+ zb3_clk: zb3_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "zb3";
+ };
+ zb3d2_clk: zb3d2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "zb3d2";
+ };
+ ddr_clk: ddr_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7793_CLK_PLL3>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "ddr";
+ };
+ mp_clk: mp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll1_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <15>;
+ clock-mult = <1>;
+ clock-output-names = "mp";
+ };
+ cp_clk: cp_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&extal_clk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "cp";
+ };
+
+ /* Gate clocks */
+ mstp0_clks: mstp0_clks@e6150130 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+ clocks = <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7793_CLK_MSIOF0>;
+ clock-output-names = "msiof0";
+ };
+ mstp1_clks: mstp1_clks@e6150134 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+ <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+ <&zs_clk>, <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
+ R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
+ R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
+ R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
+ R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
+ R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
+ R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
+ R8A7793_CLK_VSP1_S
+ >;
+ clock-output-names =
+ "vcp0", "vpc0", "ssp_dev", "tmu1",
+ "pvrsrvkm", "tddmac", "fdp1", "fdp0",
+ "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+ "vsp1-du0", "vsps";
+ };
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+ <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1
+ R8A7793_CLK_SCIFA0 R8A7793_CLK_MSIOF2
+ R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1
+ R8A7793_CLK_MSIOF1 R8A7793_CLK_SCIFB2
+ R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
+ >;
+ clock-output-names =
+ "scifa2", "scifa1", "scifa0", "msiof2",
+ "scifb0", "scifb1", "msiof1", "scifb2",
+ "sys-dmac1", "sys-dmac0";
+ };
+ mstp3_clks: mstp3_clks@e615013c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+ clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
+ <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
+ <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
+ <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
+ R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
+ R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
+ R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
+ R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
+ R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
+ >;
+ clock-output-names =
+ "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
+ "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+ "usbdmac0", "usbdmac1";
+ };
+ mstp5_clks: mstp5_clks@e6150144 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+ clocks = <&zs_clk>, <&zs_clk>, <&extal_clk>, <&p_clk>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7793_CLK_AUDIO_DMAC0
+ R8A7793_CLK_AUDIO_DMAC1
+ R8A7793_CLK_THERMAL
+ R8A7793_CLK_PWM>;
+ clock-output-names =
+ "audmac0", "audmac1", "thermal", "pwm";
+ };
+ mstp7_clks: mstp7_clks@e615014c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+ clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
+ <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
+ <&zx_clk>, <&zx_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
+ R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
+ R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
+ R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
+ R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
+ R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
+ R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
+ >;
+ clock-output-names =
+ "ehci", "hsusb", "hscif2", "scif5", "scif4",
+ "hscif1", "hscif0", "scif3", "scif2",
+ "scif1", "scif0", "du1", "du0", "lvds0";
+ };
+ mstp8_clks: mstp8_clks@e6150990 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+ clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+ <&p_clk>, <&zs_clk>, <&zs_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
+ R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
+ R8A7793_CLK_ETHER R8A7793_CLK_SATA1
+ R8A7793_CLK_SATA0
+ >;
+ clock-output-names =
+ "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
+ "sata1", "sata0";
+ };
+ mstp9_clks: mstp9_clks@e6150994 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+ <&p_clk>, <&p_clk>,
+ <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
+ <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+ <&hp_clk>, <&hp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
+ R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
+ R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
+ R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
+ R8A7793_CLK_RCAN1 R8A7793_CLK_RCAN0
+ R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
+ R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
+ R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
+ R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
+ >;
+ clock-output-names =
+ "gpio7", "gpio6", "gpio5", "gpio4", "gpio3",
+ "gpio2", "gpio1", "gpio0", "rcan1", "rcan0",
+ "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
+ "i2c2", "i2c1", "i2c0";
+ };
+ mstp10_clks: mstp10_clks@e6150998 {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+ clocks = <&p_clk>, /* parent of SCU */
+ <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
+
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCU_ALL
+ R8A7793_CLK_SSI_ALL
+
+ R8A7793_CLK_SSI9 R8A7793_CLK_SSI8
+ R8A7793_CLK_SSI7 R8A7793_CLK_SSI6
+ R8A7793_CLK_SSI5
+
+ R8A7793_CLK_SSI4 R8A7793_CLK_SSI3
+ R8A7793_CLK_SSI2 R8A7793_CLK_SSI1
+ R8A7793_CLK_SSI0
+
+ R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
+
+ R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8
+ R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6
+ R8A7793_CLK_SCU_SRC5
+
+ R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3
+ R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1
+ R8A7793_CLK_SCU_SRC0
+ >;
+ clock-output-names =
+ "scu", "ssi",
+ "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+ "dvc1", "dvc0",
+ "src9", "src8", "src7", "src6", "src5",
+ "src4", "src3", "src2", "src1", "src0";
+ };
+ mstp11_clks: mstp11_clks@e615099c {
+ compatible = "renesas,r8a7793-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+ clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4
+ R8A7793_CLK_SCIFA5
+ >;
+ clock-output-names = "scifa3", "scifa4", "scifa5";
+ };
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7793_CLK_MSIOF0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
+ interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_MSIOF1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7793";
+ reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
+ interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7793_CLK_MSIOF2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7793";
+ device_type = "pci";
+ clocks = <&mstp7_clks R8A7793_CLK_EHCI>;
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7793";
+ device_type = "pci";
+ clocks = <&mstp7_clks R8A7793_CLK_EHCI>;
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7793";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0 117 IRQ_TYPE_LEVEL_HIGH>,
+ <0 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7793_CLK_PCIEC>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ status = "disabled";
+ };
+
+ rcar_sound: sound@0xec500000 {
+ #sound-dai-cells = <1>;
+ compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x1280>; /* SSI */
+ clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
+ <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
+ <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
+ <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
+ <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
+ <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
+ <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
+ clock-names = "ssi",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6", "src.5",
+ "src.4", "src.3", "src.2", "src.1", "src.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>,
+ <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>,
+ <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>,
+ <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>,
+ <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>,
+ <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>,
+ <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>,
+ <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>,
+ <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>,
+ <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>,
+
+ <&audma0 0x85>, <&audma1 0x9a>, <&audma0 0xbc>,
+ <&audma0 0x87>, <&audma1 0x9c>, <&audma0 0xbe>,
+ <&audma0 0x89>, <&audma1 0x9e>,
+ <&audma0 0x8b>, <&audma1 0xa0>,
+ <&audma0 0x8d>, <&audma1 0xb0>,
+ <&audma0 0x8f>, <&audma1 0xb2>,
+ <&audma0 0x91>, <&audma1 0xb4>,
+ <&audma0 0x93>, <&audma1 0xb6>,
+ <&audma0 0x95>, <&audma1 0xb8>,
+ <&audma0 0x97>, <&audma1 0xba>,
+
+ <&audmapp 0x2d00>, <&audmapp 0x2e00>, <&audmapp 0x2f00>, <&audmapp 0x3000>, <&audmapp 0x3100>,
+ <&audmapp 0x2d04>, <&audmapp 0x2e04>, <&audmapp 0x2f04>, <&audmapp 0x3004>, <&audmapp 0x3104>,
+ <&audmapp 0x2d08>, <&audmapp 0x2e08>, <&audmapp 0x2f08>, <&audmapp 0x3008>, <&audmapp 0x3108>,
+ <&audmapp 0x2d0c>, <&audmapp 0x2e0c>, <&audmapp 0x2f0c>, <&audmapp 0x300c>, <&audmapp 0x310c>,
+ <&audmapp 0x2d0d>, <&audmapp 0x2e0d>, <&audmapp 0x2f0d>, <&audmapp 0x300d>, <&audmapp 0x310d>,
+ <&audmapp 0x2d0e>, <&audmapp 0x2e0e>, <&audmapp 0x2f0e>, <&audmapp 0x300e>, <&audmapp 0x310e>,
+ <&audmapp 0x2d0f>, <&audmapp 0x2e0f>, <&audmapp 0x2f0f>, <&audmapp 0x300f>, <&audmapp 0x310f>,
+ <&audmapp 0x2d10>, <&audmapp 0x2e10>, <&audmapp 0x2f10>, <&audmapp 0x3010>, <&audmapp 0x3110>,
+ <&audmapp 0x2d11>, <&audmapp 0x2e11>, <&audmapp 0x2f11>, <&audmapp 0x3011>, <&audmapp 0x3111>,
+ <&audmapp 0x2d12>, <&audmapp 0x2e12>, <&audmapp 0x2f12>, <&audmapp 0x3012>, <&audmapp 0x3112>,
+
+ <&audmapp 0x3200>, <&audmapp 0x3300>, <&audmapp 0x3400>, <&audmapp 0x3500>, <&audmapp 0x3600>,
+ <&audmapp 0x3204>, <&audmapp 0x3304>, <&audmapp 0x3404>, <&audmapp 0x3504>, <&audmapp 0x3604>,
+ <&audmapp 0x3208>, <&audmapp 0x3308>, <&audmapp 0x3408>, <&audmapp 0x3508>, <&audmapp 0x3608>,
+ <&audmapp 0x320c>, <&audmapp 0x330c>, <&audmapp 0x340c>, <&audmapp 0x350c>, <&audmapp 0x360c>,
+ <&audmapp 0x320d>, <&audmapp 0x330d>, <&audmapp 0x340d>, <&audmapp 0x350d>, <&audmapp 0x360d>,
+ <&audmapp 0x320e>, <&audmapp 0x330e>, <&audmapp 0x340e>, <&audmapp 0x350e>, <&audmapp 0x360e>,
+ <&audmapp 0x320f>, <&audmapp 0x330f>, <&audmapp 0x340f>, <&audmapp 0x350f>, <&audmapp 0x360f>,
+ <&audmapp 0x3210>, <&audmapp 0x3310>, <&audmapp 0x3410>, <&audmapp 0x3510>, <&audmapp 0x3610>,
+ <&audmapp 0x3211>, <&audmapp 0x3311>, <&audmapp 0x3411>, <&audmapp 0x3511>, <&audmapp 0x3611>,
+ <&audmapp 0x3212>, <&audmapp 0x3312>, <&audmapp 0x3412>, <&audmapp 0x3512>, <&audmapp 0x3612>,
+
+ <&audmapp 0x002d>, <&audmapp 0x002e>, <&audmapp 0x002f>, <&audmapp 0x0030>, <&audmapp 0x0031>,
+ <&audmapp 0x042d>, <&audmapp 0x042e>, <&audmapp 0x042f>, <&audmapp 0x0430>, <&audmapp 0x0431>,
+ <&audmapp 0x082d>, <&audmapp 0x082e>, <&audmapp 0x082f>, <&audmapp 0x0830>, <&audmapp 0x0831>,
+ <&audmapp 0x0c2d>, <&audmapp 0x0c2e>, <&audmapp 0x0c2f>, <&audmapp 0x0c30>, <&audmapp 0x0c31>,
+ <&audmapp 0x0d2d>, <&audmapp 0x0d2e>, <&audmapp 0x0d2f>, <&audmapp 0x0d30>, <&audmapp 0x0d31>,
+ <&audmapp 0x0e2d>, <&audmapp 0x0e2e>, <&audmapp 0x0e2f>, <&audmapp 0x0e30>, <&audmapp 0x0e31>,
+ <&audmapp 0x0f2d>, <&audmapp 0x0f2e>, <&audmapp 0x0f2f>, <&audmapp 0x0f30>, <&audmapp 0x0f31>,
+ <&audmapp 0x102d>, <&audmapp 0x102e>, <&audmapp 0x102f>, <&audmapp 0x1030>, <&audmapp 0x1031>,
+ <&audmapp 0x112d>, <&audmapp 0x112e>, <&audmapp 0x112f>, <&audmapp 0x1130>, <&audmapp 0x1131>,
+ <&audmapp 0x122d>, <&audmapp 0x122e>, <&audmapp 0x122f>, <&audmapp 0x1230>, <&audmapp 0x1231>,
+
+ <&audmapp 0x0032>, <&audmapp 0x0033>, <&audmapp 0x0034>, <&audmapp 0x0035>, <&audmapp 0x0036>,
+ <&audmapp 0x0432>, <&audmapp 0x0433>, <&audmapp 0x0434>, <&audmapp 0x0435>, <&audmapp 0x0436>,
+ <&audmapp 0x0832>, <&audmapp 0x0833>, <&audmapp 0x0834>, <&audmapp 0x0835>, <&audmapp 0x0836>,
+ <&audmapp 0x0c32>, <&audmapp 0x0c33>, <&audmapp 0x0c34>, <&audmapp 0x0c35>, <&audmapp 0x0c36>,
+ <&audmapp 0x0d32>, <&audmapp 0x0d33>, <&audmapp 0x0d34>, <&audmapp 0x0d35>, <&audmapp 0x0d36>,
+ <&audmapp 0x0e32>, <&audmapp 0x0e33>, <&audmapp 0x0e34>, <&audmapp 0x0e35>, <&audmapp 0x0e36>,
+ <&audmapp 0x0f32>, <&audmapp 0x0f33>, <&audmapp 0x0f34>, <&audmapp 0x0f35>, <&audmapp 0x0f36>,
+ <&audmapp 0x1032>, <&audmapp 0x1033>, <&audmapp 0x1034>, <&audmapp 0x1035>, <&audmapp 0x1036>,
+ <&audmapp 0x1132>, <&audmapp 0x1133>, <&audmapp 0x1134>, <&audmapp 0x1135>, <&audmapp 0x1136>,
+ <&audmapp 0x1232>, <&audmapp 0x1233>, <&audmapp 0x1234>, <&audmapp 0x1235>, <&audmapp 0x1236>;
+
+ dma-names = "mem_ssi0", "ssi0_mem", "mem_ssiu0", "ssiu0_mem",
+ "mem_ssi1", "ssi1_mem", "mem_ssiu1", "ssiu1_mem",
+ "mem_ssi2", "ssi2_mem", "mem_ssiu2", "ssiu2_mem",
+ "mem_ssi3", "ssi3_mem", "mem_ssiu3", "ssiu3_mem",
+ "mem_ssi4", "ssi4_mem", "mem_ssiu4", "ssiu4_mem",
+ "mem_ssi5", "ssi5_mem", "mem_ssiu5", "ssiu5_mem",
+ "mem_ssi6", "ssi6_mem", "mem_ssiu6", "ssiu6_mem",
+ "mem_ssi7", "ssi7_mem", "mem_ssiu7", "ssiu7_mem",
+ "mem_ssi8", "ssi8_mem", "mem_ssiu8", "ssiu8_mem",
+ "mem_ssi9", "ssi9_mem", "mem_ssiu9", "ssiu9_mem",
+
+ "mem_src0", "src0_mem", "dvc0_mem",
+ "mem_src1", "src1_mem", "dvc1_mem",
+ "mem_src2", "src2_mem",
+ "mem_src3", "src3_mem",
+ "mem_src4", "src4_mem",
+ "mem_src5", "src5_mem",
+ "mem_src6", "src6_mem",
+ "mem_src7", "src7_mem",
+ "mem_src8", "src8_mem",
+ "mem_src9", "src9_mem",
+
+ "src0_ssiu0", "src1_ssiu0", "src2_ssiu0", "src3_ssiu0", "src4_ssiu0",
+ "src0_ssiu1", "src1_ssiu1", "src2_ssiu1", "src3_ssiu1", "src4_ssiu1",
+ "src0_ssiu2", "src1_ssiu2", "src2_ssiu2", "src3_ssiu2", "src4_ssiu2",
+ "src0_ssiu3", "src1_ssiu3", "src2_ssiu3", "src3_ssiu3", "src4_ssiu3",
+ "src0_ssiu4", "src1_ssiu4", "src2_ssiu4", "src3_ssiu4", "src4_ssiu4",
+ "src0_ssiu5", "src1_ssiu5", "src2_ssiu5", "src3_ssiu5", "src4_ssiu5",
+ "src0_ssiu6", "src1_ssiu6", "src2_ssiu6", "src3_ssiu6", "src4_ssiu6",
+ "src0_ssiu7", "src1_ssiu7", "src2_ssiu7", "src3_ssiu7", "src4_ssiu7",
+ "src0_ssiu8", "src1_ssiu8", "src2_ssiu8", "src3_ssiu8", "src4_ssiu8",
+ "src0_ssiu9", "src1_ssiu9", "src2_ssiu9", "src3_ssiu9", "src4_ssiu9",
+
+ "src5_ssiu0", "src6_ssiu0", "src7_ssiu0", "src8_ssiu0", "src9_ssiu0",
+ "src5_ssiu1", "src6_ssiu1", "src7_ssiu1", "src8_ssiu1", "src9_ssiu1",
+ "src5_ssiu2", "src6_ssiu2", "src7_ssiu2", "src8_ssiu2", "src9_ssiu2",
+ "src5_ssiu3", "src6_ssiu3", "src7_ssiu3", "src8_ssiu3", "src9_ssiu3",
+ "src5_ssiu4", "src6_ssiu4", "src7_ssiu4", "src8_ssiu4", "src9_ssiu4",
+ "src5_ssiu5", "src6_ssiu5", "src7_ssiu5", "src8_ssiu5", "src9_ssiu5",
+ "src5_ssiu6", "src6_ssiu6", "src7_ssiu6", "src8_ssiu6", "src9_ssiu6",
+ "src5_ssiu7", "src6_ssiu7", "src7_ssiu7", "src8_ssiu7", "src9_ssiu7",
+ "src5_ssiu8", "src6_ssiu8", "src7_ssiu8", "src8_ssiu8", "src9_ssiu8",
+ "src5_ssiu9", "src6_ssiu9", "src7_ssiu9", "src8_ssiu9", "src9_ssiu9",
+
+ "ssiu0_src0", "ssiu0_src1", "ssiu0_src2", "ssiu0_src3", "ssiu0_src4",
+ "ssiu1_src0", "ssiu1_src1", "ssiu1_src2", "ssiu1_src3", "ssiu1_src4",
+ "ssiu2_src0", "ssiu2_src1", "ssiu2_src2", "ssiu2_src3", "ssiu2_src4",
+ "ssiu3_src0", "ssiu3_src1", "ssiu3_src2", "ssiu3_src3", "ssiu3_src4",
+ "ssiu4_src0", "ssiu4_src1", "ssiu4_src2", "ssiu4_src3", "ssiu4_src4",
+ "ssiu5_src0", "ssiu5_src1", "ssiu5_src2", "ssiu5_src3", "ssiu5_src4",
+ "ssiu6_src0", "ssiu6_src1", "ssiu6_src2", "ssiu6_src3", "ssiu6_src4",
+ "ssiu7_src0", "ssiu7_src1", "ssiu7_src2", "ssiu7_src3", "ssiu7_src4",
+ "ssiu8_src0", "ssiu8_src1", "ssiu8_src2", "ssiu8_src3", "ssiu8_src4",
+ "ssiu9_src0", "ssiu9_src1", "ssiu9_src2", "ssiu9_src3", "ssiu9_src4",
+
+ "ssiu0_src5", "ssiu0_src6", "ssiu0_src7", "ssiu0_src8", "ssiu0_src9",
+ "ssiu1_src5", "ssiu1_src6", "ssiu1_src7", "ssiu1_src8", "ssiu1_src9",
+ "ssiu2_src5", "ssiu2_src6", "ssiu2_src7", "ssiu2_src8", "ssiu2_src9",
+ "ssiu3_src5", "ssiu3_src6", "ssiu3_src7", "ssiu3_src8", "ssiu3_src9",
+ "ssiu4_src5", "ssiu4_src6", "ssiu4_src7", "ssiu4_src8", "ssiu4_src9",
+ "ssiu5_src5", "ssiu5_src6", "ssiu5_src7", "ssiu5_src8", "ssiu5_src9",
+ "ssiu6_src5", "ssiu6_src6", "ssiu6_src7", "ssiu6_src8", "ssiu6_src9",
+ "ssiu7_src5", "ssiu7_src6", "ssiu7_src7", "ssiu7_src8", "ssiu7_src9",
+ "ssiu8_src5", "ssiu8_src6", "ssiu8_src7", "ssiu8_src8", "ssiu8_src9",
+ "ssiu9_src5", "ssiu9_src6", "ssiu9_src7", "ssiu9_src8", "ssiu9_src9";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc@0 { };
+ dvc1: dvc@1 { };
+ };
+
+ rcar_sound,src {
+ src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
+ src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
+ src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
+ src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
+ src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
+ src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
+ src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
+ src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
+ src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
+ src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
+ ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
new file mode 100644
index 0000000..fab3b21
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -0,0 +1,158 @@
+/*
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN 0
+#define R8A7793_CLK_PLL0 1
+#define R8A7793_CLK_PLL1 2
+#define R8A7793_CLK_PLL3 3
+#define R8A7793_CLK_LB 4
+#define R8A7793_CLK_QSPI 5
+#define R8A7793_CLK_SDH 6
+#define R8A7793_CLK_SD0 7
+#define R8A7793_CLK_Z 8
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0 1
+#define R8A7793_CLK_VPC0 3
+#define R8A7793_CLK_SSP1 9
+#define R8A7793_CLK_TMU1 11
+#define R8A7793_CLK_3DG 12
+#define R8A7793_CLK_2DDMAC 15
+#define R8A7793_CLK_FDP1_1 18
+#define R8A7793_CLK_FDP1_0 19
+#define R8A7793_CLK_TMU3 21
+#define R8A7793_CLK_TMU2 22
+#define R8A7793_CLK_CMT0 24
+#define R8A7793_CLK_TMU0 25
+#define R8A7793_CLK_VSP1_DU1 27
+#define R8A7793_CLK_VSP1_DU0 28
+#define R8A7793_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2 2
+#define R8A7793_CLK_SCIFA1 3
+#define R8A7793_CLK_SCIFA0 4
+#define R8A7793_CLK_MSIOF2 5
+#define R8A7793_CLK_SCIFB0 6
+#define R8A7793_CLK_SCIFB1 7
+#define R8A7793_CLK_MSIOF1 8
+#define R8A7793_CLK_SCIFB2 16
+#define R8A7793_CLK_SYS_DMAC1 18
+#define R8A7793_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0 4
+#define R8A7793_CLK_SDHI2 11
+#define R8A7793_CLK_SDHI1 12
+#define R8A7793_CLK_SDHI0 14
+#define R8A7793_CLK_MMCIF0 15
+#define R8A7793_CLK_IIC0 18
+#define R8A7793_CLK_PCIEC 19
+#define R8A7793_CLK_IIC1 23
+#define R8A7793_CLK_SSUSB 28
+#define R8A7793_CLK_CMT1 29
+#define R8A7793_CLK_USBDMAC0 30
+#define R8A7793_CLK_USBDMAC1 31
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1 1
+#define R8A7793_CLK_AUDIO_DMAC0 2
+#define R8A7793_CLK_THERMAL 22
+#define R8A7793_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI 3
+#define R8A7793_CLK_HSUSB 4
+#define R8A7793_CLK_HSCIF2 13
+#define R8A7793_CLK_SCIF5 14
+#define R8A7793_CLK_SCIF4 15
+#define R8A7793_CLK_HSCIF1 16
+#define R8A7793_CLK_HSCIF0 17
+#define R8A7793_CLK_SCIF3 18
+#define R8A7793_CLK_SCIF2 19
+#define R8A7793_CLK_SCIF1 20
+#define R8A7793_CLK_SCIF0 21
+#define R8A7793_CLK_DU1 23
+#define R8A7793_CLK_DU0 24
+#define R8A7793_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX 0
+#define R8A7793_CLK_VIN2 9
+#define R8A7793_CLK_VIN1 10
+#define R8A7793_CLK_VIN0 11
+#define R8A7793_CLK_ETHER 13
+#define R8A7793_CLK_SATA1 14
+#define R8A7793_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7 4
+#define R8A7793_CLK_GPIO6 5
+#define R8A7793_CLK_GPIO5 7
+#define R8A7793_CLK_GPIO4 8
+#define R8A7793_CLK_GPIO3 9
+#define R8A7793_CLK_GPIO2 10
+#define R8A7793_CLK_GPIO1 11
+#define R8A7793_CLK_GPIO0 12
+#define R8A7793_CLK_RCAN1 15
+#define R8A7793_CLK_RCAN0 16
+#define R8A7793_CLK_QSPI_MOD 17
+#define R8A7793_CLK_I2C5 25
+#define R8A7793_CLK_IICDVFS 26
+#define R8A7793_CLK_I2C4 27
+#define R8A7793_CLK_I2C3 28
+#define R8A7793_CLK_I2C2 29
+#define R8A7793_CLK_I2C1 30
+#define R8A7793_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL 5
+#define R8A7793_CLK_SSI9 6
+#define R8A7793_CLK_SSI8 7
+#define R8A7793_CLK_SSI7 8
+#define R8A7793_CLK_SSI6 9
+#define R8A7793_CLK_SSI5 10
+#define R8A7793_CLK_SSI4 11
+#define R8A7793_CLK_SSI3 12
+#define R8A7793_CLK_SSI2 13
+#define R8A7793_CLK_SSI1 14
+#define R8A7793_CLK_SSI0 15
+#define R8A7793_CLK_SCU_ALL 17
+#define R8A7793_CLK_SCU_DVC1 18
+#define R8A7793_CLK_SCU_DVC0 19
+#define R8A7793_CLK_SCU_SRC9 22
+#define R8A7793_CLK_SCU_SRC8 23
+#define R8A7793_CLK_SCU_SRC7 24
+#define R8A7793_CLK_SCU_SRC6 25
+#define R8A7793_CLK_SCU_SRC5 26
+#define R8A7793_CLK_SCU_SRC4 27
+#define R8A7793_CLK_SCU_SRC3 28
+#define R8A7793_CLK_SCU_SRC2 29
+#define R8A7793_CLK_SCU_SRC1 30
+#define R8A7793_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3 6
+#define R8A7793_CLK_SCIFA4 7
+#define R8A7793_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
--
2.3.5
--
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^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 09/15] ARM: shmobile: r8a7793: add Gose board device tree
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
@ 2015-04-30 14:18 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (6 subsequent siblings)
7 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, Hisashi Nakamura, Koji Matsuoka,
Biju Das, Hiroyuki Yokoyama, Kouichi Tomita, devicetree
DT description and Makefile entry for the Gose eval board.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Kouichi Tomita <kouichi.tomita.yn@renesas.com>
[uli: collapsed BSP revisions into a single commit]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7793-gose.dts | 534 +++++++++++++++++++++++++++++++++++++
2 files changed, 535 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7793-gose.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 86217db..03d876f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -492,6 +492,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
+ r8a7793-gose.dtb \
r8a7794-alt.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
new file mode 100644
index 0000000..713ed03
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -0,0 +1,534 @@
+/*
+ * Device Tree Source for the Gose board
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ * 2: CN22
+ * 3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ */
+
+/dts-v1/;
+#include "r8a7793.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Gose";
+ compatible = "renesas,gose", "renesas,r8a7793";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = &scif0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ key-1 {
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW30";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW31";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW32";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-d {
+ gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW33";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-e {
+ gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_E>;
+ label = "SW34";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-f {
+ gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F>;
+ label = "SW35";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-g {
+ gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_G>;
+ label = "SW36";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led6 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ label = "LED6";
+ };
+ led7 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ label = "LED7";
+ };
+ led8 {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ label = "LED8";
+ };
+ };
+
+ vcc_sdhi0: regulator@0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator@1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi1: regulator@2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator@3 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator@4 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator@5 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "i2s";
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&du_pins &usb0_pins &usb1_pins &vin0_pins &vin1_pins>;
+ pinctrl-names = "default";
+
+ i2c2_pins: i2c2 {
+ renesas,groups = "i2c2";
+ renesas,function = "i2c2";
+ };
+
+ du_pins: du {
+ renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
+ renesas,function = "du";
+ };
+
+ scif0_pins: serial0 {
+ renesas,groups = "scif0_data_d";
+ renesas,function = "scif0";
+ };
+
+ scif1_pins: serial1 {
+ renesas,groups = "scif1_data_d";
+ renesas,function = "scif1";
+ };
+
+ ether_pins: ether {
+ renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+ renesas,function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ renesas,groups = "intc_irq0";
+ renesas,function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
+ renesas,function = "sdhi0";
+ };
+
+ sdhi1_pins: sd1 {
+ renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
+ renesas,function = "sdhi1";
+ };
+
+ sdhi2_pins: sd2 {
+ renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+ renesas,function = "sdhi2";
+ };
+
+ qspi_pins: spi0 {
+ renesas,groups = "qspi_ctrl", "qspi_data4";
+ renesas,function = "qspi";
+ };
+
+ msiof0_pins: spi1 {
+ renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+ "msiof0_tx";
+ renesas,function = "msiof0";
+ };
+
+ msiof1_pins: spi2 {
+ renesas,groups = "msiof1_clk_c", "msiof1_sync_c", "msiof1_rx_c",
+ "msiof1_tx_c";
+ renesas,function = "msiof1";
+ };
+
+ usb0_pins: usb0 {
+ renesas,groups = "usb0";
+ renesas,function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ renesas,groups = "usb1";
+ renesas,function = "usb1";
+ };
+
+ vin0_pins: vin0 {
+ renesas,groups = "vin0_data24", "vin0_sync", "vin0_field",
+ "vin0_clkenb", "vin0_clk";
+ renesas,function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ renesas,groups = "vin1_data8", "vin1_clk";
+ renesas,function = "vin1";
+ };
+
+ sound_pins: sound {
+ renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ renesas,function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ renesas,groups = "audio_clk_a";
+ renesas,function = "audio_clk";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl512s";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpha;
+ spi-cpol;
+ m25p,fast-read;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user";
+ reg = <0x00080000 0x00580000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash";
+ reg = <0x00600000 0x03a00000>;
+ };
+ };
+};
+
+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ak4643: sound-codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ eeprom@50 {
+ compatible = "renesas,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie_bus_clk {
+ status = "okay";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_dvfs>;
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 09/15] ARM: shmobile: r8a7793: add Gose board device tree
@ 2015-04-30 14:18 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:18 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, Hisashi Nakamura, Koji Matsuoka,
Biju Das, Hiroyuki Yokoyama, Kouichi Tomita, devicetree
DT description and Makefile entry for the Gose eval board.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Kouichi Tomita <kouichi.tomita.yn@renesas.com>
[uli: collapsed BSP revisions into a single commit]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7793-gose.dts | 534 +++++++++++++++++++++++++++++++++++++
2 files changed, 535 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7793-gose.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 86217db..03d876f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -492,6 +492,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
+ r8a7793-gose.dtb \
r8a7794-alt.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
new file mode 100644
index 0000000..713ed03
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -0,0 +1,534 @@
+/*
+ * Device Tree Source for the Gose board
+ *
+ * Copyright (C) 2014-2015 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ * 2: CN22
+ * 3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "LINEOUT Mixer DACL" on
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ */
+
+/dts-v1/;
+#include "r8a7793.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Gose";
+ compatible = "renesas,gose", "renesas,r8a7793";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = &scif0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ keyboard {
+ compatible = "gpio-keys";
+
+ key-1 {
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW30";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW31";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW32";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-d {
+ gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW33";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-e {
+ gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_E>;
+ label = "SW34";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-f {
+ gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F>;
+ label = "SW35";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ key-g {
+ gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_G>;
+ label = "SW36";
+ gpio-key,wakeup;
+ debounce-interval = <20>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led6 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ label = "LED6";
+ };
+ led7 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ label = "LED7";
+ };
+ led8 {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ label = "LED8";
+ };
+ };
+
+ vcc_sdhi0: regulator@0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator@1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi1: regulator@2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator@3 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi2: regulator@4 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi2: regulator@5 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "i2s";
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4643>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&du_pins &usb0_pins &usb1_pins &vin0_pins &vin1_pins>;
+ pinctrl-names = "default";
+
+ i2c2_pins: i2c2 {
+ renesas,groups = "i2c2";
+ renesas,function = "i2c2";
+ };
+
+ du_pins: du {
+ renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
+ renesas,function = "du";
+ };
+
+ scif0_pins: serial0 {
+ renesas,groups = "scif0_data_d";
+ renesas,function = "scif0";
+ };
+
+ scif1_pins: serial1 {
+ renesas,groups = "scif1_data_d";
+ renesas,function = "scif1";
+ };
+
+ ether_pins: ether {
+ renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+ renesas,function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ renesas,groups = "intc_irq0";
+ renesas,function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
+ renesas,function = "sdhi0";
+ };
+
+ sdhi1_pins: sd1 {
+ renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
+ renesas,function = "sdhi1";
+ };
+
+ sdhi2_pins: sd2 {
+ renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+ renesas,function = "sdhi2";
+ };
+
+ qspi_pins: spi0 {
+ renesas,groups = "qspi_ctrl", "qspi_data4";
+ renesas,function = "qspi";
+ };
+
+ msiof0_pins: spi1 {
+ renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+ "msiof0_tx";
+ renesas,function = "msiof0";
+ };
+
+ msiof1_pins: spi2 {
+ renesas,groups = "msiof1_clk_c", "msiof1_sync_c", "msiof1_rx_c",
+ "msiof1_tx_c";
+ renesas,function = "msiof1";
+ };
+
+ usb0_pins: usb0 {
+ renesas,groups = "usb0";
+ renesas,function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ renesas,groups = "usb1";
+ renesas,function = "usb1";
+ };
+
+ vin0_pins: vin0 {
+ renesas,groups = "vin0_data24", "vin0_sync", "vin0_field",
+ "vin0_clkenb", "vin0_clk";
+ renesas,function = "vin0";
+ };
+
+ vin1_pins: vin1 {
+ renesas,groups = "vin1_data8", "vin1_clk";
+ renesas,function = "vin1";
+ };
+
+ sound_pins: sound {
+ renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+ renesas,function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ renesas,groups = "audio_clk_a";
+ renesas,function = "audio_clk";
+ };
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl512s";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpha;
+ spi-cpol;
+ m25p,fast-read;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "user";
+ reg = <0x00080000 0x00580000>;
+ read-only;
+ };
+ partition@440000 {
+ label = "flash";
+ reg = <0x00600000 0x03a00000>;
+ };
+ };
+};
+
+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ak4643: sound-codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ eeprom@50 {
+ compatible = "renesas,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&pci1 {
+ status = "okay";
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie_bus_clk {
+ status = "okay";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_dvfs>;
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ #sound-dai-cells = <0>;
+
+ status = "okay";
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+};
+
+&ssi1 {
+ shared-pin;
+};
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 11/15] clk: shmobile: r8a7793: document DIV6 clock bindings
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
@ 2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (6 subsequent siblings)
7 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, devicetree
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 054f65f..b0a3a11 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -10,7 +10,8 @@ Required Properties:
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
- - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+ - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
+ - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
- "renesas,cpg-div6-clock" for generic DIV6 clocks
- reg: Base address and length of the memory resource used by the DIV6 clock
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 11/15] clk: shmobile: r8a7793: document DIV6 clock bindings
@ 2015-04-30 14:19 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, devicetree
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 054f65f..b0a3a11 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -10,7 +10,8 @@ Required Properties:
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
- - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+ - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
+ - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
- "renesas,cpg-div6-clock" for generic DIV6 clocks
- reg: Base address and length of the memory resource used by the DIV6 clock
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 12/15] mmc: sh_mmcif: Document r8a7793 DT bindings
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht, Ulf Hansson,
devicetree-u79uwXL29TY76Z2rM5mHXA
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
index 299081f..3b9422b 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
+ - "renesas,mmcif-r8a7793" for the MMCIF found in r8a7793 SoCs
- "renesas,sh-mmcif" for the generic MMCIF
- clocks: reference to the functional clock
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 12/15] mmc: sh_mmcif: Document r8a7793 DT bindings
@ 2015-04-30 14:19 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht, Ulf Hansson,
devicetree-u79uwXL29TY76Z2rM5mHXA
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Acked-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Cc: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
index 299081f..3b9422b 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
+ - "renesas,mmcif-r8a7793" for the MMCIF found in r8a7793 SoCs
- "renesas,sh-mmcif" for the generic MMCIF
- clocks: reference to the functional clock
--
2.3.5
--
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^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: devicetree@vger.kernel.org
---
.../devicetree/bindings/serial/renesas,sci-serial.txt | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index ae73bb0..78419eb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -15,10 +15,14 @@ Required properties:
- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
- "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
- "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
- - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
- - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
- - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
- - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
+ - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
+ - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
+ - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
+ - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
+ - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
+ - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
+ - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
+ - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
- "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
@ 2015-04-30 14:19 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
.../devicetree/bindings/serial/renesas,sci-serial.txt | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index ae73bb0..78419eb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -15,10 +15,14 @@ Required properties:
- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
- "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
- "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
- - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
- - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
- - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
- - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
+ - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
+ - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
+ - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
+ - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
+ - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
+ - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
+ - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
+ - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
- "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
--
2.3.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
@ 2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (6 subsequent siblings)
7 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, Michael Turquette, devicetree
Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 0a80fa7..923ee0f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -15,7 +15,8 @@ Required Properties:
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
+ - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
@ 2015-04-30 14:19 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert, horms, linux-sh
Cc: magnus.damm, laurent.pinchart+renesas, kuninori.morimoto.gx,
linus.walleij, Ulrich Hecht, Michael Turquette, devicetree
Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 0a80fa7..923ee0f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -15,7 +15,8 @@ Required Properties:
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
+ - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 15/15] PCI: rcar: document r8a7793 DT bindings
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
` (3 subsequent siblings)
4 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index d8ef5bf..8b156fe 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -8,6 +8,7 @@ OHCI and EHCI controllers.
Required properties:
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC.
+ "renesas,pci-r8a7793" for the R8A7793 SoC.
- reg: A list of physical regions to access the device: the first is
the operational registers for the OHCI/EHCI controllers and the
second is for the bridge configuration and control registers.
--
2.3.5
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v2 15/15] PCI: rcar: document r8a7793 DT bindings
@ 2015-04-30 14:19 ` Ulrich Hecht
0 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-04-30 14:19 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g, horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, Ulrich Hecht,
devicetree-u79uwXL29TY76Z2rM5mHXA
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Acked-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index d8ef5bf..8b156fe 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -8,6 +8,7 @@ OHCI and EHCI controllers.
Required properties:
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC.
+ "renesas,pci-r8a7793" for the R8A7793 SoC.
- reg: A list of physical regions to access the device: the first is
the operational registers for the OHCI/EHCI controllers and the
second is for the bridge configuration and control registers.
--
2.3.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-01 0:33 ` Simon Horman
-1 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:33 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, Michael Turquette,
devicetree
On Thu, Apr 30, 2015 at 04:19:03PM +0200, Ulrich Hecht wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: Michael Turquette <mturquette@linaro.org>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> index 0a80fa7..923ee0f 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> @@ -15,7 +15,8 @@ Required Properties:
> - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
> - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
> - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
> - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
> + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
> + - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
> - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
> - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
> - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
@ 2015-05-01 0:33 ` Simon Horman
0 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:33 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, Michael Turquette,
devicetree
On Thu, Apr 30, 2015 at 04:19:03PM +0200, Ulrich Hecht wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: Michael Turquette <mturquette@linaro.org>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> index 0a80fa7..923ee0f 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> @@ -15,7 +15,8 @@ Required Properties:
> - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
> - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
> - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
> - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
> + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
> + - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
> - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
> - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
> - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 15/15] PCI: rcar: document r8a7793 DT bindings
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-01 0:36 ` Simon Horman
-1 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:36 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree, Bjorn Helgaas,
linux-pci
[CC Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org ]
On Thu, Apr 30, 2015 at 04:19:04PM +0200, Ulrich Hecht wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: devicetree@vger.kernel.org
> ---
> Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
> 1 file changed, 1 insertion(+)
I suppose this one is for the PCI subsystem and thus Bjorn Helgaas (CCed).
> diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> index d8ef5bf..8b156fe 100644
> --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> @@ -8,6 +8,7 @@ OHCI and EHCI controllers.
> Required properties:
> - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
> "renesas,pci-r8a7791" for the R8A7791 SoC.
> + "renesas,pci-r8a7793" for the R8A7793 SoC.
> - reg: A list of physical regions to access the device: the first is
> the operational registers for the OHCI/EHCI controllers and the
> second is for the bridge configuration and control registers.
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 15/15] PCI: rcar: document r8a7793 DT bindings
@ 2015-05-01 0:36 ` Simon Horman
0 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:36 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree, Bjorn Helgaas,
linux-pci
[CC Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org ]
On Thu, Apr 30, 2015 at 04:19:04PM +0200, Ulrich Hecht wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: devicetree@vger.kernel.org
> ---
> Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
> 1 file changed, 1 insertion(+)
I suppose this one is for the PCI subsystem and thus Bjorn Helgaas (CCed).
> diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> index d8ef5bf..8b156fe 100644
> --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> @@ -8,6 +8,7 @@ OHCI and EHCI controllers.
> Required properties:
> - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
> "renesas,pci-r8a7791" for the R8A7791 SoC.
> + "renesas,pci-r8a7793" for the R8A7793 SoC.
> - reg: A list of physical regions to access the device: the first is
> the operational registers for the OHCI/EHCI controllers and the
> second is for the bridge configuration and control registers.
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-01 0:41 ` Simon Horman
-1 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:41 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree
On Thu, Apr 30, 2015 at 04:19:02PM +0200, Ulrich Hecht wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Most likely this needs to go to the SERIAL DRIVERS maintainers.
> ---
> .../devicetree/bindings/serial/renesas,sci-serial.txt | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> index ae73bb0..78419eb 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -15,10 +15,14 @@ Required properties:
> - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
> - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
> - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
> - - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
> - - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
> - - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
> - - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
> + - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
> + - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
> + - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
> + - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
> + - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
> + - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
> + - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
> + - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
> - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
> - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
> - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
@ 2015-05-01 0:41 ` Simon Horman
0 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:41 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree
On Thu, Apr 30, 2015 at 04:19:02PM +0200, Ulrich Hecht wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Most likely this needs to go to the SERIAL DRIVERS maintainers.
> ---
> .../devicetree/bindings/serial/renesas,sci-serial.txt | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> index ae73bb0..78419eb 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -15,10 +15,14 @@ Required properties:
> - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
> - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
> - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
> - - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
> - - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
> - - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
> - - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
> + - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
> + - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
> + - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
> + - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
> + - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
> + - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
> + - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
> + - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
> - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
> - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
> - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
2015-04-30 14:18 ` Ulrich Hecht
@ 2015-05-01 0:44 ` Simon Horman
-1 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:44 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree
On Thu, Apr 30, 2015 at 04:18:55PM +0200, Ulrich Hecht wrote:
> Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> index bfe72ec..6bcf851 100644
> --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> @@ -16,7 +16,8 @@ Required Properties:
> - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
> - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
> - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
> - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
> + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
> + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
> - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
>
> - reg: Base address and length of each memory resource used by the pin
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
@ 2015-05-01 0:44 ` Simon Horman
0 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:44 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, linux-sh, magnus.damm, laurent.pinchart+renesas,
kuninori.morimoto.gx, linus.walleij, devicetree
On Thu, Apr 30, 2015 at 04:18:55PM +0200, Ulrich Hecht wrote:
> Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> index bfe72ec..6bcf851 100644
> --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
> @@ -16,7 +16,8 @@ Required Properties:
> - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
> - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
> - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
> - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
> + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
> + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
> - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
>
> - reg: Base address and length of each memory resource used by the pin
> --
> 2.3.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/15] r8a7793 SoC, Gose board support
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
` (3 preceding siblings ...)
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-01 0:49 ` Simon Horman
2015-05-12 4:15 ` Simon Horman
` (2 subsequent siblings)
7 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-01 0:49 UTC (permalink / raw)
To: linux-sh
On Thu, Apr 30, 2015 at 04:18:49PM +0200, Ulrich Hecht wrote:
> Hi!
>
> Here is a revised set of patches adding R8A7793 (M2-N) support.
> The major changes are that I dropped power management for now,
> and that the PFC monster patch has been broken down for ease
> of review. Also a lot of small errors, most spotted by Geert,
> have been fixed.
>
> CU
> Uli
>
>
> Changes since v1:
> - pfc: split patch in six
> - pfc: fixed typos
> - dts: named clock bits correctly
> - dts: made more consistent with the very similar r8a7791 dts
> - dts: removed adv7511, don't know the address
> - pm: dropped for now, needs to be fixed up first
> - everywhere: renamed M2N -> M2-N (and M2 to M2-W, while at it)
> - everywhere: added Acks
>
>
> Ulrich Hecht (15):
> pinctrl: sh-pfc: Add r8a7793 PFC support part 1: pinmux data
> pinctrl: sh-pfc: Add r8a7793 PFC support part 2: pin groups
> pinctrl: sh-pfc: Add r8a7793 PFC support part 3: pinmux config
> registers
> pinctrl: sh-pfc: Add r8a7793 pinmux info
> pinctrl: sh-pfc: Enable building of r8a7793 PFC support
> pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
> ARM: shmobile: Basic r8a7793 SoC support
> ARM: shmobile: add r8a7793 SoC device tree
> ARM: shmobile: r8a7793: add Gose board device tree
> ARM: shmobile: r8a7793: add SMP support
It looks like in order to have a functional system the shmobile patches
need at least some of the pinctl patches. Probably the shmobile
and pinctl patches can be merged in parallel. But regardless I am marking
the shmobile patches as deffered until the pinctrl patches are accepted.
FWIW, I think it ought to be possible to supply slimmer DT files that
allow for a working system without any PFC dependencies. This may allow
some Gose support to be merged faster.
> clk: shmobile: r8a7793: document DIV6 clock bindings
> mmc: sh_mmcif: Document r8a7793 DT bindings
> serial: sh-sci: Add device tree bindings for r8a7793
> clk: shmobile: Add r8a7793 SoC to MSTP bindings
> PCI: rcar: document r8a7793 DT bindings
>
> .../bindings/clock/renesas,cpg-div6-clocks.txt | 3 +-
> .../bindings/clock/renesas,cpg-mstp-clocks.txt | 3 +-
> .../devicetree/bindings/mmc/renesas,mmcif.txt | 1 +
> .../devicetree/bindings/pci/pci-rcar-gen2.txt | 1 +
> .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 +-
> .../bindings/serial/renesas,sci-serial.txt | 12 +-
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/r8a7793-gose.dts | 534 ++
> arch/arm/boot/dts/r8a7793.dtsi | 1376 +++++
> arch/arm/mach-shmobile/Kconfig | 4 +
> arch/arm/mach-shmobile/Makefile | 2 +
> arch/arm/mach-shmobile/r8a7793.h | 6 +
> arch/arm/mach-shmobile/setup-r8a7793.c | 35 +
> arch/arm/mach-shmobile/smp-r8a7793.c | 67 +
> drivers/pinctrl/sh-pfc/Kconfig | 5 +
> drivers/pinctrl/sh-pfc/Makefile | 1 +
> drivers/pinctrl/sh-pfc/core.c | 6 +
> drivers/pinctrl/sh-pfc/core.h | 1 +
> drivers/pinctrl/sh-pfc/pfc-r8a7793.c | 6033 ++++++++++++++++++++
> include/dt-bindings/clock/r8a7793-clock.h | 158 +
> 20 files changed, 8245 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/boot/dts/r8a7793-gose.dts
> create mode 100644 arch/arm/boot/dts/r8a7793.dtsi
> create mode 100644 arch/arm/mach-shmobile/r8a7793.h
> create mode 100644 arch/arm/mach-shmobile/setup-r8a7793.c
> create mode 100644 arch/arm/mach-shmobile/smp-r8a7793.c
> create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7793.c
> create mode 100644 include/dt-bindings/clock/r8a7793-clock.h
>
> --
> 2.3.5
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
[not found] ` <1430403544-26742-7-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-05-05 9:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:10 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Thu, Apr 30, 2015 at 4:18 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
@ 2015-05-05 9:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:10 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Thu, Apr 30, 2015 at 4:18 PM, Ulrich Hecht
<ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Acked-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree
[not found] ` <1430403544-26742-9-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-05-05 9:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:27 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, Hisashi Nakamura,
Kazuya Mizuguchi, Hiroyuki Yokoyama, Ryo Kataoka, Phil Edworthy,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Ulrich,
On Thu, Apr 30, 2015 at 4:18 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> r8a7793 device tree including clock descriptions.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> [uli: collapsed BSP revisions into a single commit, edited for style]
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7793.dtsi
> @@ -0,0 +1,1376 @@
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + };
No cmt0, cmt1?
> + irqc0: interrupt-controller@e61c0000 {
> + compatible = "renesas,irqc-r8a7793", "renesas,irqc";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + reg = <0 0xe61c0000 0 0x200>;
> + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 15 IRQ_TYPE_LEVEL_HIGH>,
> + <0 16 IRQ_TYPE_LEVEL_HIGH>,
> + <0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
> + };
> + audmapp: dma-controller@0xec740000 {
> + compatible = "renesas,rcar-audmapp";
> + #dma-cells = <1>;
> +
> + reg = <0 0xec740000 0 0x200>;
> + };
The audmapp node is obsolete.
There's no driver anymore for "renesas,rcar-audmapp".
> + sdhi0: sd@ee100000 {
> + compatible = "renesas,sdhi-r8a7793";
> + reg = <0 0xee100000 0 0x200>;
Length should be 0x328 for sdhi0.
> + dma-names = "tx", "rx";
> + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
> + cap-uhs-sdr104;
> + cap-uhs-sdr50;
> + dma-xmit-sz = <32>;
> + renesas,clk-rate = <195000000>;
> + renesas,mmc-scc-tapnum = <8>;
> + renesas,pfcs = <0xe6060000 0x8c>;
> + renesas,id = <0>;
Undocumented properties not supported in upstream, likewise for sdh[12].
Please look at r8a7791.dtsi.
> + status = "disabled";
> + };
> + clocks {
> + /* Fixed factor clocks */
> + zg_clk: zg_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
> + #clock-cells = <0>;
> + clock-div = <5>;
r8a7791 uses <3>.
But upon closer look, the zg is configurable for 3 or 5 through the
GPUCKCR register on both '91 and '93. so this is wrong on both.
> + clock-mult = <1>;
> + clock-output-names = "zg";
> + };
> + /* Gate clocks */
> + mstp5_clks: mstp5_clks@e6150144 {
> + compatible = "renesas,r8a7793-mstp-clocks",
> + "renesas,cpg-mstp-clocks";
> + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
> + clocks = <&zs_clk>, <&zs_clk>, <&extal_clk>, <&p_clk>;
r8a7791 has hp_clk (High Speed Peripheral Clock) instead of zs_clk (AXI clock)
as the parent clock for the audio DMA controllers.
As audio DMA is connected to the APB, not to the AXI bus, hp_clk looks correct.
> + #clock-cells = <1>;
> + clock-indices = <R8A7793_CLK_AUDIO_DMAC0
> + R8A7793_CLK_AUDIO_DMAC1
> + R8A7793_CLK_THERMAL
> + R8A7793_CLK_PWM>;
> + clock-output-names > + "audmac0", "audmac1", "thermal", "pwm";
> + };
> + msiof0: spi@e6e20000 {
> + compatible = "renesas,msiof-r8a7793";
> + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
Please drop the second register bank, which is obsolete.
Likewise for msiof[12].
> + rcar_sound: sound@0xec500000 {
Bogus "0x" after "@".
> + #sound-dai-cells = <1>;
> + compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
Please drop "renesas,rcar_sound";
Probably more changes to the audio are needed. Please look at r8a7791.dtsi, or
wait for Morimoto-san to comment.
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7793-clock.h
Missing:
/* MSTP4 */
#define R8A7793_CLK_IRQC 7
> +
> +/* MSTP5 */
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree
@ 2015-05-05 9:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:27 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, Hisashi Nakamura,
Kazuya Mizuguchi, Hiroyuki Yokoyama, Ryo Kataoka, Phil Edworthy,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Ulrich,
On Thu, Apr 30, 2015 at 4:18 PM, Ulrich Hecht
<ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> r8a7793 device tree including clock descriptions.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Phil Edworthy <phil.edworthy-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> [uli: collapsed BSP revisions into a single commit, edited for style]
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7793.dtsi
> @@ -0,0 +1,1376 @@
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + };
No cmt0, cmt1?
> + irqc0: interrupt-controller@e61c0000 {
> + compatible = "renesas,irqc-r8a7793", "renesas,irqc";
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + reg = <0 0xe61c0000 0 0x200>;
> + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 15 IRQ_TYPE_LEVEL_HIGH>,
> + <0 16 IRQ_TYPE_LEVEL_HIGH>,
> + <0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
> + };
> + audmapp: dma-controller@0xec740000 {
> + compatible = "renesas,rcar-audmapp";
> + #dma-cells = <1>;
> +
> + reg = <0 0xec740000 0 0x200>;
> + };
The audmapp node is obsolete.
There's no driver anymore for "renesas,rcar-audmapp".
> + sdhi0: sd@ee100000 {
> + compatible = "renesas,sdhi-r8a7793";
> + reg = <0 0xee100000 0 0x200>;
Length should be 0x328 for sdhi0.
> + dma-names = "tx", "rx";
> + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
> + cap-uhs-sdr104;
> + cap-uhs-sdr50;
> + dma-xmit-sz = <32>;
> + renesas,clk-rate = <195000000>;
> + renesas,mmc-scc-tapnum = <8>;
> + renesas,pfcs = <0xe6060000 0x8c>;
> + renesas,id = <0>;
Undocumented properties not supported in upstream, likewise for sdh[12].
Please look at r8a7791.dtsi.
> + status = "disabled";
> + };
> + clocks {
> + /* Fixed factor clocks */
> + zg_clk: zg_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
> + #clock-cells = <0>;
> + clock-div = <5>;
r8a7791 uses <3>.
But upon closer look, the zg is configurable for 3 or 5 through the
GPUCKCR register on both '91 and '93. so this is wrong on both.
> + clock-mult = <1>;
> + clock-output-names = "zg";
> + };
> + /* Gate clocks */
> + mstp5_clks: mstp5_clks@e6150144 {
> + compatible = "renesas,r8a7793-mstp-clocks",
> + "renesas,cpg-mstp-clocks";
> + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
> + clocks = <&zs_clk>, <&zs_clk>, <&extal_clk>, <&p_clk>;
r8a7791 has hp_clk (High Speed Peripheral Clock) instead of zs_clk (AXI clock)
as the parent clock for the audio DMA controllers.
As audio DMA is connected to the APB, not to the AXI bus, hp_clk looks correct.
> + #clock-cells = <1>;
> + clock-indices = <R8A7793_CLK_AUDIO_DMAC0
> + R8A7793_CLK_AUDIO_DMAC1
> + R8A7793_CLK_THERMAL
> + R8A7793_CLK_PWM>;
> + clock-output-names =
> + "audmac0", "audmac1", "thermal", "pwm";
> + };
> + msiof0: spi@e6e20000 {
> + compatible = "renesas,msiof-r8a7793";
> + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
Please drop the second register bank, which is obsolete.
Likewise for msiof[12].
> + rcar_sound: sound@0xec500000 {
Bogus "0x" after "@".
> + #sound-dai-cells = <1>;
> + compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
Please drop "renesas,rcar_sound";
Probably more changes to the audio are needed. Please look at r8a7791.dtsi, or
wait for Morimoto-san to comment.
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7793-clock.h
Missing:
/* MSTP4 */
#define R8A7793_CLK_IRQC 7
> +
> +/* MSTP5 */
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 11/15] clk: shmobile: r8a7793: document DIV6 clock bindings
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-05 9:37 ` Geert Uytterhoeven
-1 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:37 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, devicetree
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 11/15] clk: shmobile: r8a7793: document DIV6 clock bindings
@ 2015-05-05 9:37 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:37 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, devicetree
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
2015-04-30 14:19 ` Ulrich Hecht
@ 2015-05-05 9:37 ` Geert Uytterhoeven
-1 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:37 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, devicetree
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793
@ 2015-05-05 9:37 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:37 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, devicetree
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
[not found] ` <1430403544-26742-15-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-05-05 9:38 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:38 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, Michael Turquette,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas@gmail.com> wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: Michael Turquette <mturquette@linaro.org>
> Cc: devicetree@vger.kernel.org
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings
@ 2015-05-05 9:38 ` Geert Uytterhoeven
0 siblings, 0 replies; 40+ messages in thread
From: Geert Uytterhoeven @ 2015-05-05 9:38 UTC (permalink / raw)
To: Ulrich Hecht
Cc: Simon Horman, Linux-sh list, Magnus Damm, Laurent Pinchart,
Kuninori Morimoto, Linus Walleij, Michael Turquette,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Thu, Apr 30, 2015 at 4:19 PM, Ulrich Hecht
<ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Michael Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Acked-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/15] r8a7793 SoC, Gose board support
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
` (4 preceding siblings ...)
2015-05-01 0:49 ` [PATCH v2 00/15] r8a7793 SoC, Gose board support Simon Horman
@ 2015-05-12 4:15 ` Simon Horman
2015-05-21 10:47 ` Ulrich Hecht
2015-05-22 1:23 ` Simon Horman
7 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-12 4:15 UTC (permalink / raw)
To: linux-sh
Hi Ulrich,
On Fri, May 01, 2015 at 09:49:03AM +0900, Simon Horman wrote:
> On Thu, Apr 30, 2015 at 04:18:49PM +0200, Ulrich Hecht wrote:
> > Hi!
> >
> > Here is a revised set of patches adding R8A7793 (M2-N) support.
> > The major changes are that I dropped power management for now,
> > and that the PFC monster patch has been broken down for ease
> > of review. Also a lot of small errors, most spotted by Geert,
> > have been fixed.
> >
> > CU
> > Uli
> >
> >
> > Changes since v1:
> > - pfc: split patch in six
> > - pfc: fixed typos
> > - dts: named clock bits correctly
> > - dts: made more consistent with the very similar r8a7791 dts
> > - dts: removed adv7511, don't know the address
> > - pm: dropped for now, needs to be fixed up first
> > - everywhere: renamed M2N -> M2-N (and M2 to M2-W, while at it)
> > - everywhere: added Acks
> >
> >
> > Ulrich Hecht (15):
> > pinctrl: sh-pfc: Add r8a7793 PFC support part 1: pinmux data
> > pinctrl: sh-pfc: Add r8a7793 PFC support part 2: pin groups
> > pinctrl: sh-pfc: Add r8a7793 PFC support part 3: pinmux config
> > registers
> > pinctrl: sh-pfc: Add r8a7793 pinmux info
> > pinctrl: sh-pfc: Enable building of r8a7793 PFC support
> > pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
> > ARM: shmobile: Basic r8a7793 SoC support
> > ARM: shmobile: add r8a7793 SoC device tree
> > ARM: shmobile: r8a7793: add Gose board device tree
> > ARM: shmobile: r8a7793: add SMP support
>
> It looks like in order to have a functional system the shmobile patches
> need at least some of the pinctl patches. Probably the shmobile
> and pinctl patches can be merged in parallel. But regardless I am marking
> the shmobile patches as deffered until the pinctrl patches are accepted.
>
> FWIW, I think it ought to be possible to supply slimmer DT files that
> allow for a working system without any PFC dependencies. This may allow
> some Gose support to be merged faster.
>
> > clk: shmobile: r8a7793: document DIV6 clock bindings
> > mmc: sh_mmcif: Document r8a7793 DT bindings
> > serial: sh-sci: Add device tree bindings for r8a7793
> > clk: shmobile: Add r8a7793 SoC to MSTP bindings
> > PCI: rcar: document r8a7793 DT bindings
I see that you have reposted the PFC patches as a separate patch-set.
I am entirely supportive of that. And I would like to offer some
suggestions about how we could move some of the shmobile side forward.
My suggestion is to create a patch set which provides basic support and
does not have any dependency on PFC. By basic support I mean serial port,
timer and maybe network if there is no dependency on PFC.
Once basic support has been merged further support can be added in an
incremental manner as the bindings and other driver support becomes ready
(merged).
I am more than happy to offer assistance, please feel free to contact me
privately or on-list.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree
2015-04-30 14:18 ` Ulrich Hecht
(?)
(?)
@ 2015-05-13 5:57 ` Kuninori Morimoto
-1 siblings, 0 replies; 40+ messages in thread
From: Kuninori Morimoto @ 2015-05-13 5:57 UTC (permalink / raw)
To: Ulrich Hecht
Cc: geert, horms, linux-sh, magnus.damm, laurent.pinchart+renesas,
linus.walleij, Hisashi Nakamura, Kazuya Mizuguchi,
Hiroyuki Yokoyama, Ryo Kataoka, Phil Edworthy, devicetree
Hi Ulrich
> r8a7793 device tree including clock descriptions.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> [uli: collapsed BSP revisions into a single commit, edited for style]
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Cc: devicetree@vger.kernel.org
# Hmm... I have never created patch for r8a7793 BSP before, but it has mine :)
About sound, it is using old style.
Please check upstreamed DTS, like r8a7790.dtsi/r8a7791.dtsi.
I added comment inline
> + rcar_sound: sound@0xec500000 {
> + #sound-dai-cells = <1>;
please don't set #sound-dai-cells on .dtsi
> + compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
> + reg = <0 0xec500000 0 0x1000>, /* SCU */
> + <0 0xec5a0000 0 0x100>, /* ADG */
> + <0 0xec540000 0 0x1000>, /* SSIU */
> + <0 0xec541000 0 0x1280>; /* SSI */
reg needs "Audio DMAC peri peri", and reg-names too.
> + clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
> + <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
> + <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
> + <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
> + <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
> + <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
> + <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
> + <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
> + <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
> + <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
> + <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
> + <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
> + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
> + clock-names = "ssi",
> + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
> + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
> + "src.9", "src.8", "src.7", "src.6", "src.5",
> + "src.4", "src.3", "src.2", "src.1", "src.0",
> + "dvc.0", "dvc.1",
> + "clk_a", "clk_b", "clk_c", "clk_i";
> +
> + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>,
> + <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>,
> + <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>,
> + <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>,
> + <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>,
> + <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>,
> + <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>,
> + <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>,
> + <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>,
> + <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>,
(snip)
> + dma-names = "mem_ssi0", "ssi0_mem", "mem_ssiu0", "ssiu0_mem",
> + "mem_ssi1", "ssi1_mem", "mem_ssiu1", "ssiu1_mem",
> + "mem_ssi2", "ssi2_mem", "mem_ssiu2", "ssiu2_mem",
> + "mem_ssi3", "ssi3_mem", "mem_ssiu3", "ssiu3_mem",
> + "mem_ssi4", "ssi4_mem", "mem_ssiu4", "ssiu4_mem",
> + "mem_ssi5", "ssi5_mem", "mem_ssiu5", "ssiu5_mem",
> + "mem_ssi6", "ssi6_mem", "mem_ssiu6", "ssiu6_mem",
> + "mem_ssi7", "ssi7_mem", "mem_ssiu7", "ssiu7_mem",
> + "mem_ssi8", "ssi8_mem", "mem_ssiu8", "ssiu8_mem",
> + "mem_ssi9", "ssi9_mem", "mem_ssiu9", "ssiu9_mem",
These dmas/dma-names are not supported on upstreamed driver.
> + status = "disabled";
> +
> + rcar_sound,dvc {
> + dvc0: dvc@0 { };
> + dvc1: dvc@1 { };
> + };
> +
> + rcar_sound,src {
> + src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
> + src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
> + src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
> + src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
> + src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
> + src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
> + src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
> + src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
> + src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
> + src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
> + };
> +
> + rcar_sound,ssi {
> + ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
> + ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
> + };
rcar_sound,dvc/src/ssi needs interrupts/dmas/dma-names
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/15] r8a7793 SoC, Gose board support
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
` (5 preceding siblings ...)
2015-05-12 4:15 ` Simon Horman
@ 2015-05-21 10:47 ` Ulrich Hecht
2015-05-22 1:23 ` Simon Horman
7 siblings, 0 replies; 40+ messages in thread
From: Ulrich Hecht @ 2015-05-21 10:47 UTC (permalink / raw)
To: linux-sh
On Tue, May 12, 2015 at 6:15 AM, Simon Horman <horms@verge.net.au> wrote:
> Once basic support has been merged further support can be added in an
> incremental manner as the bindings and other driver support becomes ready
> (merged).
Since a large number of small issues have been identified in this
version, I will post another one in the same arrangement with all that
stuff fixed first.
> I am more than happy to offer assistance, please feel free to contact me
> privately or on-list.
Gladly, thank you.
Now that the PFC patches have been picked up by Linus Walleij, will it
still be necessary to exclude PFC dependencies in the next iteration?
CU
Uli
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v2 00/15] r8a7793 SoC, Gose board support
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
` (6 preceding siblings ...)
2015-05-21 10:47 ` Ulrich Hecht
@ 2015-05-22 1:23 ` Simon Horman
7 siblings, 0 replies; 40+ messages in thread
From: Simon Horman @ 2015-05-22 1:23 UTC (permalink / raw)
To: linux-sh
On Thu, May 21, 2015 at 12:47:50PM +0200, Ulrich Hecht wrote:
> On Tue, May 12, 2015 at 6:15 AM, Simon Horman <horms@verge.net.au> wrote:
> > Once basic support has been merged further support can be added in an
> > incremental manner as the bindings and other driver support becomes ready
> > (merged).
>
> Since a large number of small issues have been identified in this
> version, I will post another one in the same arrangement with all that
> stuff fixed first.
>
> > I am more than happy to offer assistance, please feel free to contact me
> > privately or on-list.
>
> Gladly, thank you.
>
> Now that the PFC patches have been picked up by Linus Walleij, will it
> still be necessary to exclude PFC dependencies in the next iteration?
That is still my preference as I believe it will be easiest in the short
to medium term. We can focus on small steps rather than getting
everything ready all at once.
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2015-05-22 1:23 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-30 14:18 [PATCH v2 00/15] r8a7793 SoC, Gose board support Ulrich Hecht
[not found] ` <1430403544-26742-1-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-04-30 14:18 ` [PATCH v2 06/15] pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
2015-05-01 0:44 ` Simon Horman
2015-05-01 0:44 ` Simon Horman
[not found] ` <1430403544-26742-7-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-05 9:10 ` Geert Uytterhoeven
2015-05-05 9:10 ` Geert Uytterhoeven
2015-04-30 14:18 ` [PATCH v2 08/15] ARM: shmobile: add r8a7793 SoC device tree Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
[not found] ` <1430403544-26742-9-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-05 9:27 ` Geert Uytterhoeven
2015-05-05 9:27 ` Geert Uytterhoeven
2015-05-13 5:57 ` Kuninori Morimoto
2015-04-30 14:19 ` [PATCH v2 12/15] mmc: sh_mmcif: Document r8a7793 DT bindings Ulrich Hecht
2015-04-30 14:19 ` Ulrich Hecht
2015-04-30 14:19 ` [PATCH v2 13/15] serial: sh-sci: Add device tree bindings for r8a7793 Ulrich Hecht
2015-04-30 14:19 ` Ulrich Hecht
2015-05-01 0:41 ` Simon Horman
2015-05-01 0:41 ` Simon Horman
2015-05-05 9:37 ` Geert Uytterhoeven
2015-05-05 9:37 ` Geert Uytterhoeven
2015-04-30 14:19 ` [PATCH v2 15/15] PCI: rcar: document r8a7793 DT bindings Ulrich Hecht
2015-04-30 14:19 ` Ulrich Hecht
2015-05-01 0:36 ` Simon Horman
2015-05-01 0:36 ` Simon Horman
2015-04-30 14:18 ` [PATCH v2 09/15] ARM: shmobile: r8a7793: add Gose board device tree Ulrich Hecht
2015-04-30 14:18 ` Ulrich Hecht
2015-04-30 14:19 ` [PATCH v2 11/15] clk: shmobile: r8a7793: document DIV6 clock bindings Ulrich Hecht
2015-04-30 14:19 ` Ulrich Hecht
2015-05-05 9:37 ` Geert Uytterhoeven
2015-05-05 9:37 ` Geert Uytterhoeven
2015-04-30 14:19 ` [PATCH v2 14/15] clk: shmobile: Add r8a7793 SoC to MSTP bindings Ulrich Hecht
2015-04-30 14:19 ` Ulrich Hecht
2015-05-01 0:33 ` Simon Horman
2015-05-01 0:33 ` Simon Horman
[not found] ` <1430403544-26742-15-git-send-email-ulrich.hecht+renesas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-05-05 9:38 ` Geert Uytterhoeven
2015-05-05 9:38 ` Geert Uytterhoeven
2015-05-01 0:49 ` [PATCH v2 00/15] r8a7793 SoC, Gose board support Simon Horman
2015-05-12 4:15 ` Simon Horman
2015-05-21 10:47 ` Ulrich Hecht
2015-05-22 1:23 ` Simon Horman
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