[U-Boot] [PATCH 0/8] ARM: highbank: fix Calxeda machines

[U-Boot] [PATCH 0/8] ARM: highbank: fix Calxeda machines

[Andre Przywara]

This series aims to upstream fixes that have been in the Calxeda
firmware version of U-Boot for ages.
The first two patches fix reset, both for Highbank and Midway.
Patches 3-5 add support for larger hard disks, so U-Boot can now
access sectors from beyond 2 TB on larger disks.
Patch 6 and 7 teach U-Boot not to touch the FDT memory node. The
primary Calxeda firmware detects the amount of memory (it has a DIMM
socket!) at boot time and populates the memory node accordingly.
U-Boot would overwrite the node with a fixed value, most commonly
getting lost of any memory beyond 4 GB on Midway systems. I have been
told that this fix has been disliked before, so I am open to a
discussion on how to address this problem.
The final patch fixes Highbank's SATA setup, which requires some
special care (cf. the sata_highbank.c driver in Linux).

There are actually more patches [1] in the last official firmware, but
most of the others only make sense with some special management
firmware versions that never made it to the light.
I extracted the most useful and important patches from there and
rebased them on top of the current master. With them I can happily
use upstream U-Boot on a Midway system - I haven't had time to test
it on Highbank, though.

Please review, comment and hopefully apply them!

Cheers,
Andre.

[1] https://git.linaro.org/people/rob.herring/u-boot.git/shortlog/refs/heads/highbank

Mark Langsdorf (5):
  ARM: highbank: add reset support for Calxeda Midway machine
  cmd_scsi: use lbaint_t for LBA values instead of u32
  ahci: support LBA48 data reads for 2+TB drives
  ahci: extend data io wait to 10s
  highbank: add custom ahci_link_up function

Rob Herring (3):
  ARM: highbank: add missing SCU register setup for reset
  ARM: bootm: allow skipping fdt memory node fixup
  ARM: highbank: remove DRAM bank setup

 arch/arm/lib/board.c       |   2 +
 arch/arm/lib/bootm-fdt.c   |   5 +-
 board/highbank/Makefile    |   2 +-
 board/highbank/ahci.c      | 218 +++++++++++++++++++++++++++++++++++++++++++++
 board/highbank/highbank.c  |  37 ++++++--
 common/cmd_scsi.c          |  58 ++++++++++--
 drivers/block/ahci.c       |  32 +++++--
 include/configs/highbank.h |   2 +-
 include/scsi.h             |   1 +
 9 files changed, 331 insertions(+), 26 deletions(-)
 create mode 100644 board/highbank/ahci.c

-- 
1.8.4

[U-Boot] [PATCH 1/8] ARM: highbank: add missing SCU register setup for reset

[Andre Przywara]

From: Rob Herring <robh@kernel.org>

Andre: assign names to the magic values

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 board/highbank/highbank.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index ba1beb5..ba254b6 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -14,6 +14,7 @@
 
 #define HB_AHCI_BASE			0xffe08000
 
+#define HB_SCU_A9_PWR_STATUS		0xfff10008
 #define HB_SREG_A9_PWR_REQ		0xfff3cf00
 #define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
 #define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
@@ -27,6 +28,10 @@
 #define PWRDOM_STAT_PCI			0x40000000
 #define PWRDOM_STAT_EMMC		0x20000000
 
+#define HB_SCU_A9_PWR_NORMAL		0
+#define HB_SCU_A9_PWR_DORMANT		2
+#define HB_SCU_A9_PWR_OFF		3
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -114,6 +119,7 @@ int ft_board_setup(void *fdt, bd_t *bd)
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+	writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
 
 	wfi();
 }
-- 
1.8.4

[U-Boot] [PATCH 2/8] ARM: highbank: add reset support for Calxeda Midway machine

[Andre Przywara]

From: Mark Langsdorf <mark.langsdorf@gmail.com>

The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.

Andre: rework detection of Highbank vs. Midway
Rob: fix Andre's reworked detection

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 board/highbank/highbank.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index ba254b6..e8132b8 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -18,6 +18,7 @@
 #define HB_SREG_A9_PWR_REQ		0xfff3cf00
 #define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
 #define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL		0xfff3c200
 
 #define HB_PWR_SUSPEND			0
 #define HB_PWR_SOFT_RESET		1
@@ -116,10 +117,22 @@ int ft_board_setup(void *fdt, bd_t *bd)
 }
 #endif
 
+static int is_highbank(void)
+{
+	uint32_t midr;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+	return (midr & 0xfff0) == 0xc090;
+}
+
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
-	writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	if (is_highbank())
+		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	else
+		writel(0x1, HB_SREG_A15_PWR_CTRL);
 
 	wfi();
 }
-- 
1.8.4

[U-Boot] [PATCH 3/8] cmd_scsi: use lbaint_t for LBA values instead of u32

[Andre Przywara]

From: Mark Langsdorf <mark.langsdorf@gmail.com>

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 common/cmd_scsi.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index f80f549..fe705b6 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -54,10 +54,10 @@ static block_dev_desc_t scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
  *  forward declerations of some Setup Routines
  */
 void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks);
-void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks);
-static void scsi_setup_write_ext(ccb *pccb, unsigned long start,
-			  unsigned short blocks);
+void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
+void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
+static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
+				unsigned short blocks);
 void scsi_setup_inquiry(ccb * pccb);
 void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
 
@@ -579,7 +579,7 @@ void scsi_setup_test_unit_ready(ccb * pccb)
 	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
 }
 
-void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks)
+void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
 	pccb->cmd[0]=SCSI_READ10;
 	pccb->cmd[1]=pccb->lun<<5;
@@ -599,7 +599,7 @@ void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks)
 		pccb->cmd[7],pccb->cmd[8]);
 }
 
-void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks)
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
 {
 	pccb->cmd[0] = SCSI_WRITE10;
 	pccb->cmd[1] = pccb->lun << 5;
@@ -620,7 +620,7 @@ void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks)
 	      pccb->cmd[7], pccb->cmd[8]);
 }
 
-void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks)
+void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
 	pccb->cmd[0]=SCSI_READ6;
 	pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
-- 
1.8.4

[U-Boot] [PATCH 4/8] ahci: support LBA48 data reads for 2+TB drives

[Andre Przywara]

From: Mark Langsdorf <mark.langsdorf@gmail.com>

Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.

This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI controller.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 common/cmd_scsi.c    | 44 ++++++++++++++++++++++++++++++++++++++++++--
 drivers/block/ahci.c | 30 +++++++++++++++++++++++-------
 include/scsi.h       |  1 +
 3 files changed, 66 insertions(+), 9 deletions(-)

diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index fe705b6..57d6a3f 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -56,6 +56,8 @@ static block_dev_desc_t scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
 void scsi_setup_test_unit_ready(ccb * pccb);
 void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
 void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
+void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks);
+
 static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
 				unsigned short blocks);
 void scsi_setup_inquiry(ccb * pccb);
@@ -357,7 +359,9 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  * scsi_read
  */
 
-#define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ	0xFFFFFFF
 
 static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 		       void *buffer)
@@ -379,7 +383,14 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
 	      device, start, blks, (unsigned long)buffer);
 	do {
 		pccb->pdata=(unsigned char *)buf_addr;
-		if(blks>SCSI_MAX_READ_BLK) {
+		if (start > SCSI_LBA48_READ) {
+			unsigned long blocks;
+			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+			scsi_setup_read16(pccb, start, blocks);
+			start += blocks;
+			blks -= blocks;
+		} else if (blks > SCSI_MAX_READ_BLK) {
 			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
 			smallblks=SCSI_MAX_READ_BLK;
 			scsi_setup_read_ext(pccb,start,smallblks);
@@ -579,6 +590,35 @@ void scsi_setup_test_unit_ready(ccb * pccb)
 	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
 }
 
+void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
+{
+	pccb->cmd[0] = SCSI_READ16;
+	pccb->cmd[1] = pccb->lun<<5;
+	pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
+	pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
+	pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
+	pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
+	pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
+	pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
+	pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
+	pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
+	pccb->cmd[10] = 0;
+	pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
+	pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
+	pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
+	pccb->cmd[14] = (unsigned char) blocks & 0xff;
+	pccb->cmd[15] = 0;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug ("scsi_setup_read16: cmd: %02X %02X "
+	       "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
+	       "blccnt %02X%02X%02X%02X\n",
+		pccb->cmd[0], pccb->cmd[1],
+		pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+		pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+		pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+
 void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
 	pccb->cmd[0]=SCSI_READ10;
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 6508648..28d0b08 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -726,18 +726,25 @@ static int ata_scsiop_inquiry(ccb *pccb)
  */
 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
 {
-	u32 lba = 0;
+	lbaint_t lba = 0;
 	u16 blocks = 0;
 	u8 fis[20];
 	u8 *user_buffer = pccb->pdata;
 	u32 user_buffer_size = pccb->datalen;
 
 	/* Retrieve the base LBA number from the ccb structure. */
-	memcpy(&lba, pccb->cmd + 2, sizeof(lba));
-	lba = be32_to_cpu(lba);
+	if (pccb->cmd[0] == SCSI_READ16) {
+		memcpy(&lba, pccb->cmd + 2, 8);
+		lba = be64_to_cpu(lba);
+	} else {
+		u32 temp;
+		memcpy(&temp, pccb->cmd + 2, 4);
+		lba = be32_to_cpu(temp);
+	}
 
 	/*
-	 * And the number of blocks.
+	 * Retrieve the base LBA number and the block count from
+	 * the ccb structure.
 	 *
 	 * For 10-byte and 16-byte SCSI R/W commands, transfer
 	 * length 0 means transfer 0 block of data.
@@ -746,10 +753,13 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
 	 *
 	 * WARNING: one or two older ATA drives treat 0 as 0...
 	 */
-	blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
+	if (pccb->cmd[0] == SCSI_READ16)
+		blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
+	else
+		blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
 
-	debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
-	      is_write ?  "write" : "read", (unsigned)lba, blocks);
+	debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+	      is_write ?  "write" : "read", blocks, lba);
 
 	/* Preset the FIS */
 	memset(fis, 0, sizeof(fis));
@@ -778,6 +788,11 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
 		fis[6] = (lba >> 16) & 0xff;
 		fis[7] = 1 << 6; /* device reg: set LBA mode */
 		fis[8] = ((lba >> 24) & 0xff);
+		if (pccb->cmd[0] == SCSI_READ16) {
+			fis[9] = ((lba >> 32) & 0xff);
+			fis[10] = ((lba >> 40) & 0xff);
+		}
+
 		fis[3] = 0xe0; /* features */
 
 		/* Block (sector) count */
@@ -883,6 +898,7 @@ int scsi_exec(ccb *pccb)
 	int ret;
 
 	switch (pccb->cmd[0]) {
+	case SCSI_READ16:
 	case SCSI_READ10:
 		ret = ata_scsiop_read_write(pccb, 0);
 		break;
diff --git a/include/scsi.h b/include/scsi.h
index 73de7b7..7e37591 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -132,6 +132,7 @@ typedef struct SCSI_cmd_block{
 #define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
 #define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
 #define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_READ16	0x48
 #define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
 #define SCSI_RD_CAPAC10	SCSI_RD_CAPAC	/* Read Capacity (10) */
 #define SCSI_RD_CAPAC16	0x9e		/* Read Capacity (16) */
-- 
1.8.4

[U-Boot] [PATCH 5/8] ahci: extend data io wait to 10s

[Andre Przywara]

From: Mark Langsdorf <mark.langsdorf@gmail.com>

The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 drivers/block/ahci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 28d0b08..eb22586 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -39,7 +39,7 @@ u16 *ataid[AHCI_MAX_PORTS];
 
 /* Maximum timeouts for each event */
 #define WAIT_MS_SPINUP	20000
-#define WAIT_MS_DATAIO	5000
+#define WAIT_MS_DATAIO	10000
 #define WAIT_MS_FLUSH	5000
 #define WAIT_MS_LINKUP	200
 
-- 
1.8.4

[U-Boot] [PATCH 6/8] ARM: bootm: allow skipping fdt memory node fixup

[Andre Przywara]

From: Rob Herring <robh@kernel.org>

Currently, u-boot will always fixup the DT memory node on ARM. If the dtb
has correct memory information, then we don't want or need u-boot to touch
the memory node. Allow platforms to skip this by not filling in dram bank
information.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 arch/arm/lib/board.c     | 2 ++
 arch/arm/lib/bootm-fdt.c | 5 ++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 37ea6e9..a3c7315 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -191,8 +191,10 @@ typedef int (init_fnc_t) (void);
 
 __weak void dram_init_banksize(void)
 {
+#if CONFIG_NR_DRAM_BANKS
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size =  gd->ram_size;
+#endif
 }
 
 __weak int arch_cpu_init(void)
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 7677358..dbf3d56 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -26,8 +26,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int arch_fixup_fdt(void *blob)
 {
+	int ret = 0;
+#if CONFIG_NR_DRAM_BANKS
 	bd_t *bd = gd->bd;
-	int bank, ret;
+	int bank;
 	u64 start[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -42,6 +44,7 @@ int arch_fixup_fdt(void *blob)
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+#endif
 #ifdef CONFIG_ARMV7_NONSEC
 	if (ret)
 		return ret;
-- 
1.8.4

[U-Boot] [PATCH 7/8] ARM: highbank: remove DRAM bank setup

[Andre Przywara]

From: Rob Herring <robh@kernel.org>

On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in are already correct,
so remove U-Boot's DRAM bank setup so the memory node is not "fixed
up" by u-boot.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 board/highbank/highbank.c  | 6 ------
 include/configs/highbank.h | 2 +-
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index e8132b8..9ebd895 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -93,12 +93,6 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
-}
-
 #if defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *fdt, bd_t *bd)
 {
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index da1c837..b1d618b 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -83,7 +83,7 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		0
 #define PHYS_SDRAM_1_SIZE		(4089 << 20)
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1_SIZE - 0x100000)
-- 
1.8.4

[U-Boot] [PATCH 8/8] highbank: add custom ahci_link_up function

[Andre Przywara]

From: Mark Langsdorf <mark.langsdorf@gmail.com>

The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
so override ahci_link_up with custom function to handle combophy setup.

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Richard Gibbs
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
---
 board/highbank/Makefile   |   2 +-
 board/highbank/ahci.c     | 218 ++++++++++++++++++++++++++++++++++++++++++++++
 board/highbank/highbank.c |  12 +++
 3 files changed, 231 insertions(+), 1 deletion(-)
 create mode 100644 board/highbank/ahci.c

diff --git a/board/highbank/Makefile b/board/highbank/Makefile
index d3eb232..ce7ee68 100644
--- a/board/highbank/Makefile
+++ b/board/highbank/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= highbank.o
+obj-y	:= highbank.o ahci.o
diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c
new file mode 100644
index 0000000..0015323
--- /dev/null
+++ b/board/highbank/ahci.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <asm/io.h>
+
+#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
+#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
+#define CPHY_BASE			0xfff58000
+#define CPHY_WIDTH			0x1000
+#define CPHY_DTE_XS			5
+#define CPHY_MII			31
+#define SERDES_CR_CTL			0x80a0
+#define SERDES_CR_ADDR			0x80a1
+#define SERDES_CR_DATA			0x80a2
+#define CR_BUSY				0x0001
+#define CR_START			0x0001
+#define CR_WR_RDN			0x0002
+#define CPHY_TX_INPUT_STS		0x2001
+#define CPHY_RX_INPUT_STS		0x2002
+#define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
+#define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
+#define CPHY_TX_INPUT_OVERRIDE		0x2004
+#define CPHY_RX_INPUT_OVERRIDE		0x2005
+#define SPHY_LANE			0x100
+#define SPHY_HALF_RATE			0x0001
+#define CPHY_SATA_DPLL_MODE		0x0700
+#define CPHY_SATA_DPLL_SHIFT		8
+#define CPHY_SATA_TX_ATTEN		0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT	10
+
+#define HB_SREG_SATA_ATTEN		0xfff3cf24
+
+#define SATA_PORT_BASE			0xffe08000
+#define SATA_VERSIONR			0xf8
+#define SATA_HB_VERSION			0x3332302a
+
+static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
+{
+	u32 data;
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+	return data;
+}
+
+static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
+{
+	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
+	writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
+}
+
+static u32 combo_phy_read(u8 phy, u32 addr)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
+}
+
+static void combo_phy_write(u8 phy, u32 addr, u32 data)
+{
+	u8 dev = CPHY_DTE_XS;
+	if (phy == 5)
+		dev = CPHY_MII;
+	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
+		udelay(5);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
+	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
+}
+
+static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
+{
+	u32 tmp;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp &= ~CPHY_SATA_DPLL_MODE;
+	tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_tx_attenuation_override(u8 phy, u8 lane)
+{
+	u32 val;
+	u32 tmp;
+	u8  shift;
+
+	shift = ((phy == 5) ? 4 : lane) * 4;
+
+	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
+
+	if (val & 0x8)
+		return;
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_disable_port_overrides(u8 port)
+{
+	u32 tmp;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+
+	tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
+	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
+	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+void cphy_disable_overrides(void)
+{
+	int i;
+	u32 port_map;
+
+	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
+	for (i = 0; i < 5; i++) {
+		if (port_map & (1 << i))
+			cphy_disable_port_overrides(i);
+	}
+}
+
+static void cphy_override_lane(u8 port)
+{
+	u32 tmp, k = 0;
+	u8 lane = 0, phy = 0;
+
+	if (port == 0)
+		phy = 5;
+	else if (port < 5)
+		lane = port - 1;
+	else
+		return;
+
+	do {
+		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
+					lane * SPHY_LANE);
+	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
+	cphy_spread_spectrum_override(phy, lane, 3);
+	cphy_tx_attenuation_override(phy, lane);
+}
+
+#define WAIT_MS_LINKUP	4
+
+int ahci_link_up(struct ahci_probe_ent *probe_ent, int port)
+{
+	u32 tmp;
+	int j = 0;
+	u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+	u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
+				SATA_HB_VERSION ? 1 : 0;
+
+	/* Bring up SATA link.
+	 * SATA link bringup time is usually less than 1 ms; only very
+	 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+	 */
+	while (j < WAIT_MS_LINKUP) {
+		if (is_highbank && (j == 0)) {
+			cphy_disable_port_overrides(port);
+			writel(0x301, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			writel(0x300, port_mmio + PORT_SCR_CTL);
+			udelay(1000);
+			cphy_override_lane(port);
+		}
+
+		tmp = readl(port_mmio + PORT_SCR_STAT);
+		if ((tmp & 0xf) == 0x3)
+			return 0;
+		udelay(1000);
+		j++;
+
+		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
+			j = 0;	/* retry phy reset */
+	}
+	return 1;
+}
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 9ebd895..55999ed 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -35,6 +35,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void cphy_disable_overrides(void);
+
 /*
  * Miscellaneous platform dependent initialisations
  */
@@ -62,6 +64,7 @@ void scsi_init(void)
 {
 	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
 
+	cphy_disable_overrides();
 	if (reg & PWRDOM_STAT_SATA) {
 		ahci_init((void __iomem *)HB_AHCI_BASE);
 		scsi_scan(1);
@@ -130,3 +133,12 @@ void reset_cpu(ulong addr)
 
 	wfi();
 }
+
+/*
+ * turn off the override before transferring control to Linux, since Linux
+ * may not support spread spectrum.
+ */
+void arch_preboot_os(void)
+{
+	cphy_disable_overrides();
+}
-- 
1.8.4

[U-Boot] [PATCH 6/8] ARM: bootm: allow skipping fdt memory node fixup

[Simon Glass]

Hi Andre,

On 4 June 2015 at 17:58, Andre Przywara <osp@andrep.de> wrote:
> From: Rob Herring <robh@kernel.org>
>
> Currently, u-boot will always fixup the DT memory node on ARM. If the dtb
> has correct memory information, then we don't want or need u-boot to touch
> the memory node. Allow platforms to skip this by not filling in dram bank
> information.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> ---
>  arch/arm/lib/board.c     | 2 ++
>  arch/arm/lib/bootm-fdt.c | 5 ++++-
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> index 37ea6e9..a3c7315 100644
> --- a/arch/arm/lib/board.c
> +++ b/arch/arm/lib/board.c

I don't think we should be patching this file now - everything should
be on generic board.

> @@ -191,8 +191,10 @@ typedef int (init_fnc_t) (void);
>
>  __weak void dram_init_banksize(void)
>  {
> +#if CONFIG_NR_DRAM_BANKS
>         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>         gd->bd->bi_dram[0].size =  gd->ram_size;
> +#endif
>  }
>
>  __weak int arch_cpu_init(void)

[snip]

Regards,
Simon

[U-Boot] [PATCH 6/8] ARM: bootm: allow skipping fdt memory node fixup

[Andre Przywara]

On Fri, 5 Jun 2015 08:12:25 -0600
Simon Glass <sjg@chromium.org> wrote:

Hi Simon,

thanks for taking a look.

> On 4 June 2015 at 17:58, Andre Przywara <osp@andrep.de> wrote:
> > From: Rob Herring <robh@kernel.org>
> >
> > Currently, u-boot will always fixup the DT memory node on ARM. If
> > the dtb has correct memory information, then we don't want or need
> > u-boot to touch the memory node. Allow platforms to skip this by
> > not filling in dram bank information.
> >
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Andre Przywara <osp@andrep.de>
> > ---
> >  arch/arm/lib/board.c     | 2 ++
> >  arch/arm/lib/bootm-fdt.c | 5 ++++-
> >  2 files changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> > index 37ea6e9..a3c7315 100644
> > --- a/arch/arm/lib/board.c
> > +++ b/arch/arm/lib/board.c
> 
> I don't think we should be patching this file now - everything should
> be on generic board.

Right, looking closer at this patch much of it is actually not
necessary. Having CONFIG_NR_DRAM_BANKS set to 0 automatically skips a
lot of the code already, so we don't need any extra gating.
Hope that there are no compilers which complain about zero-sized arrays.
The only thing that harms us is the final fdt_setprop(), which will
_clear_ the reg property in the memory node in this case.
So I replaced this patch by just skipping the reg property setting if
the number of banks is 0 in common/fdt_support.c.
From looking at all callers of fdt_fixup_memory_banks() this looks like
a safe approach. Any objections?
I will send the replaced patch with the next revision.

Cheers,
Andre.

> 
> > @@ -191,8 +191,10 @@ typedef int (init_fnc_t) (void);
> >
> >  __weak void dram_init_banksize(void)
> >  {
> > +#if  
> >         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> >         gd->bd->bi_dram[0].size =  gd->ram_size;
> > +#endif
> >  }
> >
> >  __weak int arch_cpu_init(void)
> 
> [snip]
> 
> Regards,
> Simon

[U-Boot] [PATCH 6/8] ARM: bootm: allow skipping fdt memory node fixup

[Simon Glass]

Hi Andre,

On 5 June 2015 at 18:14, Andre Przywara <osp@andrep.de> wrote:
> On Fri, 5 Jun 2015 08:12:25 -0600
> Simon Glass <sjg@chromium.org> wrote:
>
> Hi Simon,
>
> thanks for taking a look.
>
>> On 4 June 2015 at 17:58, Andre Przywara <osp@andrep.de> wrote:
>> > From: Rob Herring <robh@kernel.org>
>> >
>> > Currently, u-boot will always fixup the DT memory node on ARM. If
>> > the dtb has correct memory information, then we don't want or need
>> > u-boot to touch the memory node. Allow platforms to skip this by
>> > not filling in dram bank information.
>> >
>> > Signed-off-by: Rob Herring <robh@kernel.org>
>> > Signed-off-by: Andre Przywara <osp@andrep.de>
>> > ---
>> >  arch/arm/lib/board.c     | 2 ++
>> >  arch/arm/lib/bootm-fdt.c | 5 ++++-
>> >  2 files changed, 6 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
>> > index 37ea6e9..a3c7315 100644
>> > --- a/arch/arm/lib/board.c
>> > +++ b/arch/arm/lib/board.c
>>
>> I don't think we should be patching this file now - everything should
>> be on generic board.
>
> Right, looking closer at this patch much of it is actually not
> necessary. Having CONFIG_NR_DRAM_BANKS set to 0 automatically skips a
> lot of the code already, so we don't need any extra gating.
> Hope that there are no compilers which complain about zero-sized arrays.
> The only thing that harms us is the final fdt_setprop(), which will
> _clear_ the reg property in the memory node in this case.
> So I replaced this patch by just skipping the reg property setting if
> the number of banks is 0 in common/fdt_support.c.
> From looking at all callers of fdt_fixup_memory_banks() this looks like
> a safe approach. Any objections?
> I will send the replaced patch with the next revision.

Should be OK - can you please add docs for that function to the header
file? See fdt_fixup_display() for an example.

>
> Cheers,
> Andre.
>
>>
>> > @@ -191,8 +191,10 @@ typedef int (init_fnc_t) (void);
>> >
>> >  __weak void dram_init_banksize(void)
>> >  {
>> > +#if
>> >         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
>> >         gd->bd->bi_dram[0].size =  gd->ram_size;
>> > +#endif
>> >  }
>> >
>> >  __weak int arch_cpu_init(void)

Regards,
Simon

[U-Boot] [U-Boot, 1/8] ARM: highbank: add missing SCU register setup for reset

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:42AM +0100, Andre Przywara wrote:

> From: Rob Herring <robh@kernel.org>
> 
> Andre: assign names to the magic values
> 
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andre Przywara <osp@andrep.de>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 2/8] ARM: highbank: add reset support for Calxeda Midway machine

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:43AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> The Calxeda Midway part has A15 cores, which do not have the Highbank
> A9's SCU used there for resetting the chip.
> Add code to distinguish between the A9 and the A15 and invoke the
> appropriate register writes to support the newer part.
> 
> Andre: rework detection of Highbank vs. Midway
> Rob: fix Andre's reworked detection
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> Signed-off-by: Rob Herring <robh@kernel.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 3/8] cmd_scsi: use lbaint_t for LBA values instead of u32

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:44AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Andre Przywara <osp@andrep.de>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,5/8] ahci: extend data io wait to 10s

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:46AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> The AHCI driver currently waits 5s before timing out when sending a
> data command to a drive. Some drives take upwards of 8s to respond to
> the initial data command while they're spinning up. Increase the
> data io timeout to 10s so that those drives can be found on initial
> scsi scan.
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Andre Przywara <osp@andrep.de>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,7/8] ARM: highbank: remove DRAM bank setup

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:48AM +0100, Andre Przywara wrote:

> From: Rob Herring <robh@kernel.org>
> 
> On the highbank platform the SoC's management controller firmware
> will probe the DRAM modules and populates the initial device tree with
> the correct values. Therefore the memory sizes in are already correct,
> so remove U-Boot's DRAM bank setup so the memory node is not "fixed
> up" by u-boot.
> 
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andre Przywara <osp@andrep.de>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 8/8] highbank: add custom ahci_link_up function

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:49AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
> so override ahci_link_up with custom function to handle combophy setup.
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Richard Gibbs
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andre Przywara <osp@andrep.de>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 4/8] ahci: support LBA48 data reads for 2+TB drives

[Tom Rini]

On Fri, Jun 05, 2015 at 12:58:45AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> Enable full 48-bit LBA48 data reads by passing the upper word of the
> LBA block pointer in bytes 9 and 10 of the FIS.
> 
> This allows uboot to load data from any arbitrary sector on a drive
> with 2 or more TB of available data connected to an AHCI controller.
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Andre Przywara <osp@andrep.de>

With some changes to make use of CONFIG_SYS_64BIT_LBA in a few areas to
allow the common parts to compile without warning on systems that
don't set this:

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH] fdt: prevent clearing memory node if there are no banks

[Andre Przywara]

Avoid clearing the reg property in the memory DT node if no memory
banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
This allows boards to let U-Boot skip the DT memory tinkering in case
other firmware has already setup the node properly before.
This should be safe as all callers of fdt_fixup_memory_banks that use
a computed <banks> value put at least 1 in there.
Add some documentation comments to the header file.

Signed-off-by: Andre Przywara <osp@andrep.de>
---
Hi,

this replaces my former "6/8: ARM: bootm: allow skipping fdt memory node fixup"
patch, as Simon had some (justified) concerns. If this is too generic now,
let me know and I will rework it.

Cheers,
Andre.

 common/fdt_support.c  | 14 ++++++++------
 include/fdt_support.h | 26 ++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 9e50148..6ad532c 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -429,13 +429,15 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
 		return err;
 	}
 
-	len = fdt_pack_reg(blob, tmp, start, size, banks);
+	if (banks) {
+		len = fdt_pack_reg(blob, tmp, start, size, banks);
 
-	err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
-	if (err < 0) {
-		printf("WARNING: could not set %s %s.\n",
-				"reg", fdt_strerror(err));
-		return err;
+		err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
+		if (err < 0) {
+			printf("WARNING: could not set %s %s.\n",
+					"reg", fdt_strerror(err));
+			return err;
+		}
 	}
 	return 0;
 }
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 5d4f28d..0296ed3 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -40,8 +40,34 @@ void do_fixup_by_compat(void *fdt, const char *compat,
 			const char *prop, const void *val, int len, int create);
 void do_fixup_by_compat_u32(void *fdt, const char *compat,
 			    const char *prop, u32 val, int create);
+/**
+ * Setup the memory node in the DT. Creates one if none was existing before.
+ * Calls fdt_fixup_memory_banks() to populate a single reg pair covering the
+ * whole memory.
+ *
+ * @param blob		FDT blob to update
+ * @param start		Begin of DRAM mapping in physical memory
+ * @param size		Size of the single memory bank
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
 int fdt_fixup_memory(void *blob, u64 start, u64 size);
+
+/**
+ * Fill the DT memory node with multiple memory banks.
+ * Creates the node if none was existing before.
+ * If banks is 0, it will not touch the existing reg property. This allows
+ * boards to not mess with the existing DT setup, which may have been
+ * filled in properly before.
+ *
+ * @param blob		FDT blob to update
+ * @param start		Array of size <banks> to hold the start addresses.
+ * @param size		Array of size <banks> to hold the size of each region.
+ * @param banks		Number of memory banks to create. If 0, the reg
+ *			property will be left untouched.
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
 int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+
 void fdt_fixup_ethernet(void *fdt);
 int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
 			 const void *val, int len, int create);
-- 
1.8.4

[U-Boot] [U-Boot,7/8] ARM: highbank: remove DRAM bank setup

[Andre Przywara]

On Fri, 12 Jun 2015 22:10:07 -0400
Tom Rini <trini@konsulko.com> wrote:

> On Fri, Jun 05, 2015 at 12:58:48AM +0100, Andre Przywara wrote:
> 
> > From: Rob Herring <robh@kernel.org>
> > 
> > On the highbank platform the SoC's management controller firmware
> > will probe the DRAM modules and populates the initial device tree
> > with the correct values. Therefore the memory sizes in are already
> > correct, so remove U-Boot's DRAM bank setup so the memory node is
> > not "fixed up" by u-boot.
> > 
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Andre Przywara <osp@andrep.de>
> 
> Applied to u-boot/master, thanks!

Hi Tom,

thanks for applying the patches!
I sent out a reworked version of patch 6/8, which saw a comment from
Simon. Please consider applying the new one _or_ revert this very patch
here (7/8), as it alone breaks Calxeda machines (which now end up with
an empty memory/reg property instead of an untouched one).
Sorry for the mess!

Cheers,
Andre.

[U-Boot] [U-Boot,7/8] ARM: highbank: remove DRAM bank setup

[Tom Rini]

On Sat, Jun 13, 2015 at 12:01:37PM +0100, Andre Przywara wrote:

> On Fri, 12 Jun 2015 22:10:07 -0400
> Tom Rini <trini@konsulko.com> wrote:
> 
> > On Fri, Jun 05, 2015 at 12:58:48AM +0100, Andre Przywara wrote:
> > 
> > > From: Rob Herring <robh@kernel.org>
> > > 
> > > On the highbank platform the SoC's management controller firmware
> > > will probe the DRAM modules and populates the initial device tree
> > > with the correct values. Therefore the memory sizes in are already
> > > correct, so remove U-Boot's DRAM bank setup so the memory node is
> > > not "fixed up" by u-boot.
> > > 
> > > Signed-off-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Andre Przywara <osp@andrep.de>
> > 
> > Applied to u-boot/master, thanks!
> 
> Hi Tom,
> 
> thanks for applying the patches!
> I sent out a reworked version of patch 6/8, which saw a comment from
> Simon. Please consider applying the new one _or_ revert this very patch
> here (7/8), as it alone breaks Calxeda machines (which now end up with
> an empty memory/reg property instead of an untouched one).
> Sorry for the mess!

"Good" news!  I somehow failed to push things when I said I did, so this
was all still just local.  I've dropped this patch for now as I want
Simon to chime in on your updated patch.

-- 
Tom
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[U-Boot] [PATCH] fdt: prevent clearing memory node if there are no banks

[Rob Herring]

On Sat, Jun 13, 2015 at 5:43 AM, Andre Przywara <osp@andrep.de> wrote:
> Avoid clearing the reg property in the memory DT node if no memory
> banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
> This allows boards to let U-Boot skip the DT memory tinkering in case
> other firmware has already setup the node properly before.
> This should be safe as all callers of fdt_fixup_memory_banks that use
> a computed <banks> value put at least 1 in there.
> Add some documentation comments to the header file.
>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> ---
> Hi,
>
> this replaces my former "6/8: ARM: bootm: allow skipping fdt memory node fixup"
> patch, as Simon had some (justified) concerns. If this is too generic now,
> let me know and I will rework it.
>
> Cheers,
> Andre.
>
>  common/fdt_support.c  | 14 ++++++++------
>  include/fdt_support.h | 26 ++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 6 deletions(-)
>
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index 9e50148..6ad532c 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -429,13 +429,15 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
>                 return err;
>         }
>
> -       len = fdt_pack_reg(blob, tmp, start, size, banks);
> +       if (banks) {
> +               len = fdt_pack_reg(blob, tmp, start, size, banks);

Save some indentation:

if (!banks)
  return 0;

>
> -       err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
> -       if (err < 0) {
> -               printf("WARNING: could not set %s %s.\n",
> -                               "reg", fdt_strerror(err));
> -               return err;
> +               err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
> +               if (err < 0) {
> +                       printf("WARNING: could not set %s %s.\n",
> +                                       "reg", fdt_strerror(err));
> +                       return err;
> +               }
>         }
>         return 0;
>  }

[U-Boot] [PATCH] fdt: prevent clearing memory node if there are no banks

[Simon Glass]

Hi,

On 13 June 2015 at 04:43, Andre Przywara <osp@andrep.de> wrote:
>
> Avoid clearing the reg property in the memory DT node if no memory
> banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
> This allows boards to let U-Boot skip the DT memory tinkering in case
> other firmware has already setup the node properly before.
> This should be safe as all callers of fdt_fixup_memory_banks that use
> a computed <banks> value put at least 1 in there.
> Add some documentation comments to the header file.
>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> ---
> Hi,
>
> this replaces my former "6/8: ARM: bootm: allow skipping fdt memory node fixup"
> patch, as Simon had some (justified) concerns. If this is too generic now,
> let me know and I will rework it.
>
> Cheers,
> Andre.
>
>  common/fdt_support.c  | 14 ++++++++------
>  include/fdt_support.h | 26 ++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 6 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

Tom, you can pick this up if you like?

- Simon

[U-Boot] [U-Boot, 4/8] ahci: support LBA48 data reads for 2+TB drives

[Bin Meng]

Hi Andre,

On Sat, Jun 13, 2015 at 10:10 AM, Tom Rini <trini@konsulko.com> wrote:
> On Fri, Jun 05, 2015 at 12:58:45AM +0100, Andre Przywara wrote:
>
>> From: Mark Langsdorf <mark.langsdorf@gmail.com>
>>
>> Enable full 48-bit LBA48 data reads by passing the upper word of the
>> LBA block pointer in bytes 9 and 10 of the FIS.
>>
>> This allows uboot to load data from any arbitrary sector on a drive
>> with 2 or more TB of available data connected to an AHCI controller.
>>
>> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
>> Signed-off-by: Andre Przywara <osp@andrep.de>
>
> With some changes to make use of CONFIG_SYS_64BIT_LBA in a few areas to
> allow the common parts to compile without warning on systems that
> don't set this:
>
> Applied to u-boot/master, thanks!
>

This commit creates a warning when CONFIG_SYS_64BIT_LBA is defined.
Please check below.

common/cmd_scsi.c: In function ?scsi_read?:
common/cmd_scsi.c:410:3: warning: ?smallblks? may be used
uninitialized in this function [-Wmaybe-uninitialized]

Regards,
Bin