[PATCH 0/9] ARM: mvebu: add suspend to RAM support for Armada 38x

[PATCH 0/9] ARM: mvebu: add suspend to RAM support for Armada 38x

[Thomas Petazzoni]

Hello,

This patch series adds suspend to RAM support for the Armada 38x SoC,
and especially the Armada 388 GP board. It has been tested on Armada
XP GP little and big endian, and on Armada 388 GP little and big
endian.

The first patch is really a fix, that makes Armada XP GP suspend to
RAM work in big endian configurations.

Then patches 2 to 5 are preparation patches, and patches 6 to 9
implement the suspend/resume support for Armada 38x itself, with first
the code changes, and then the Device Tree changes.

This is obviously not intended for 4.2, but for 4.3.

Best regards,

Thomas

Nadav Haklai (1):
  ARM: mvebu: prepare set_cpu_coherent() for future extension

Thomas Petazzoni (8):
  ARM: mvebu: fix suspend to RAM on big-endian configurations
  ARM: mvebu: do not check machine in mvebu_pm_init()
  ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs
  ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x
    support
  ARM: mvebu: add suspend/resume support for Armada 38x
  ARM: mvebu: add suspend/resume related definitions in Armada 38x
    Device Tree
  ARM: mvebu: add suspend/resume DT information for Armada 388 GP
  ARM: mvebu: adjust board name and compatible for Armada 388 GP

 arch/arm/boot/dts/armada-388-gp.dts | 20 +++++++++--
 arch/arm/boot/dts/armada-38x.dtsi   |  7 +++-
 arch/arm/mach-mvebu/board-v7.c      |  1 +
 arch/arm/mach-mvebu/coherency.c     | 33 +++++++++++-------
 arch/arm/mach-mvebu/pm-board.c      | 28 ++++++++-------
 arch/arm/mach-mvebu/pm.c            | 69 +++++++++++++++++++++++++++++++++----
 arch/arm/mach-mvebu/pmsu.h          |  1 +
 arch/arm/mach-mvebu/pmsu_ll.S       | 43 +++++++++++++++++++++++
 8 files changed, 168 insertions(+), 34 deletions(-)

-- 
2.1.0

[PATCH 1/9] ARM: mvebu: fix suspend to RAM on big-endian configurations

[Thomas Petazzoni]

The current Armada XP suspend to RAM implementation, as added in
commit 27432825ae19f ("ARM: mvebu: Armada XP GP specific
suspend/resume code") does not handle big-endian configurations
properly: the small bit of assembly code putting the DRAM in
self-refresh and toggling the GPIOs to turn off power forgets to
convert the values to little-endian.

This commit fixes that by making sure the two values we will write to
the DRAM controller register and GPIO register are already in
little-endian before entering the critical assembly code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.19+
Fixes: 27432825ae19f ("ARM: mvebu: Armada XP GP specific suspend/resume code")
---
 arch/arm/mach-mvebu/pm-board.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 6dfd4ab..301ab38 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
 	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
 		ackcmd |= BIT(pic_raw_gpios[i]);
 
+	srcmd = cpu_to_le32(srcmd);
+	ackcmd = cpu_to_le32(ackcmd);
+
 	/*
 	 * Wait a while, the PIC needs quite a bit of time between the
 	 * two GPIO commands.
-- 
2.1.0

[PATCH 1/9] ARM: mvebu: fix suspend to RAM on big-endian configurations

[Thomas Petazzoni]

The current Armada XP suspend to RAM implementation, as added in
commit 27432825ae19f ("ARM: mvebu: Armada XP GP specific
suspend/resume code") does not handle big-endian configurations
properly: the small bit of assembly code putting the DRAM in
self-refresh and toggling the GPIOs to turn off power forgets to
convert the values to little-endian.

This commit fixes that by making sure the two values we will write to
the DRAM controller register and GPIO register are already in
little-endian before entering the critical assembly code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.19+
Fixes: 27432825ae19f ("ARM: mvebu: Armada XP GP specific suspend/resume code")
---
 arch/arm/mach-mvebu/pm-board.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 6dfd4ab..301ab38 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
 	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
 		ackcmd |= BIT(pic_raw_gpios[i]);
 
+	srcmd = cpu_to_le32(srcmd);
+	ackcmd = cpu_to_le32(ackcmd);
+
 	/*
 	 * Wait a while, the PIC needs quite a bit of time between the
 	 * two GPIO commands.
-- 
2.1.0

[PATCH 2/9] ARM: mvebu: prepare set_cpu_coherent() for future extension

[Thomas Petazzoni]

From: Nadav Haklai <nadavh@marvell.com>

This patch prepares the set_cpu_coherent() function in coherency.c to
be extended to support other SoCs than Armada XP. It will be needed on
Armada 38x to re-enable the coherency after exiting from suspend to
RAM.

This preparation simply moves the function further down in coherency.c
so that it can use coherency_type(), and uses that function to only do
the Armada XP specific work if we are on Armada XP.

Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/coherency.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index e46e9ea..44eedf3 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = {
 int ll_enable_coherency(void);
 void ll_add_cpu_to_smp_group(void);
 
-int set_cpu_coherent(void)
-{
-	if (!coherency_base) {
-		pr_warn("Can't make current CPU cache coherent.\n");
-		pr_warn("Coherency fabric is not initialized\n");
-		return 1;
-	}
-
-	ll_add_cpu_to_smp_group();
-	return ll_enable_coherency();
-}
-
 static int mvebu_hwcc_notifier(struct notifier_block *nb,
 			       unsigned long event, void *__dev)
 {
@@ -206,6 +194,23 @@ static int coherency_type(void)
 	return type;
 }
 
+int set_cpu_coherent(void)
+{
+	int type = coherency_type();
+
+	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
+		if (!coherency_base) {
+			pr_warn("Can't make current CPU cache coherent.\n");
+			pr_warn("Coherency fabric is not initialized\n");
+			return 1;
+		}
+		ll_add_cpu_to_smp_group();
+		return ll_enable_coherency();
+	}
+
+	return 0;
+}
+
 int coherency_available(void)
 {
 	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
-- 
2.1.0

[PATCH 3/9] ARM: mvebu: do not check machine in mvebu_pm_init()

[Thomas Petazzoni]

The mvebu_pm_init() initializes the support for suspend/resume, and
before doing that, it checks if we are on a board on which
suspend/resume is actually supported. However, this check is already
done by mvebu_armada_xp_gp_pm_init(), and there is no need to
duplicate the check: callers of mvebu_pm_init() should now what they
are doing.

This commit is done in preparation to the addition of suspend/resume
support on Armada 38x.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/pm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 6573a8f..eca650b 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -182,9 +182,6 @@ int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
 	struct device_node *np;
 	struct resource res;
 
-	if (!of_machine_is_compatible("marvell,armadaxp"))
-		return -ENODEV;
-
 	np = of_find_compatible_node(NULL, NULL,
 				     "marvell,armada-xp-sdram-controller");
 	if (!np)
-- 
2.1.0

[PATCH 4/9] ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs

[Thomas Petazzoni]

As we are going to introduce support for Armada 38x in pm.c, split out
the Armada XP part of mvebu_pm_store_bootinfo() into
mvebu_pm_store_armadaxp_bootinfo(), and make the former retunr an
error when an unsupported SoC is used.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/pm.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index eca650b..02fdf67 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -105,12 +105,10 @@ static phys_addr_t mvebu_internal_reg_base(void)
 	return of_translate_address(np, in_addr);
 }
 
-static void mvebu_pm_store_bootinfo(void)
+static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
 {
-	u32 *store_addr;
 	phys_addr_t resume_pc;
 
-	store_addr = phys_to_virt(BOOT_INFO_ADDR);
 	resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
 
 	/*
@@ -151,14 +149,33 @@ static void mvebu_pm_store_bootinfo(void)
 	writel(BOOT_MAGIC_LIST_END, store_addr);
 }
 
+static int mvebu_pm_store_bootinfo(void)
+{
+	u32 *store_addr;
+
+	store_addr = phys_to_virt(BOOT_INFO_ADDR);
+
+	if (of_machine_is_compatible("marvell,armadaxp"))
+		mvebu_pm_store_armadaxp_bootinfo(store_addr);
+	else
+		return -ENODEV;
+
+	return 0;
+}
+
 static int mvebu_pm_enter(suspend_state_t state)
 {
+	int ret;
+
 	if (state != PM_SUSPEND_MEM)
 		return -EINVAL;
 
+	ret = mvebu_pm_store_bootinfo();
+	if (ret)
+		return ret;
+
 	cpu_pm_enter();
 
-	mvebu_pm_store_bootinfo();
 	cpu_suspend(0, mvebu_pm_powerdown);
 
 	outer_resume();
-- 
2.1.0

[PATCH 5/9] ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x support

[Thomas Petazzoni]

The pm-board.c code contains the board-specific logic to enter suspend
to RAM. Until now, the code supported only the Armada XP GP board, so
all functions and symbols were named with armada_xp_gp. However, it
turns out that the Armada 388 GP also uses the same 3 GPIOs protocol
to talk to the PIC microcontroller that controls the power supply.

Since we are going to re-use the same code with no change for Armada
38x, this commit renames the functions and symbols to use just
"armada" instead of "armada_xp_gp". Better names can be found if one
day other boards having a different protocol/mechanism are supported
in the kernel.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/pm-board.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 301ab38..b8c26cb 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -1,7 +1,7 @@
 /*
  * Board-level suspend/resume support.
  *
- * Copyright (C) 2014 Marvell
+ * Copyright (C) 2014-2015 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
@@ -20,27 +20,27 @@
 #include <linux/slab.h>
 #include "common.h"
 
-#define ARMADA_XP_GP_PIC_NR_GPIOS 3
+#define ARMADA_PIC_NR_GPIOS 3
 
 static void __iomem *gpio_ctrl;
-static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
-static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
+static int pic_gpios[ARMADA_PIC_NR_GPIOS];
+static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
 
-static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
+static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
 {
 	u32 reg, ackcmd;
 	int i;
 
 	/* Put 001 as value on the GPIOs */
 	reg = readl(gpio_ctrl);
-	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
+	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
 		reg &= ~BIT(pic_raw_gpios[i]);
 	reg |= BIT(pic_raw_gpios[0]);
 	writel(reg, gpio_ctrl);
 
 	/* Prepare writing 111 to the GPIOs */
 	ackcmd = readl(gpio_ctrl);
-	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
+	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
 		ackcmd |= BIT(pic_raw_gpios[i]);
 
 	srcmd = cpu_to_le32(srcmd);
@@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
 		  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
 }
 
-static int mvebu_armada_xp_gp_pm_init(void)
+static int mvebu_armada_pm_init(void)
 {
 	struct device_node *np;
 	struct device_node *gpio_ctrl_np;
@@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void)
 	if (!np)
 		return -ENODEV;
 
-	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) {
+	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
 		char *name;
 		struct of_phandle_args args;
 
@@ -134,11 +134,11 @@ static int mvebu_armada_xp_gp_pm_init(void)
 	if (!gpio_ctrl)
 		return -ENOMEM;
 
-	mvebu_pm_init(mvebu_armada_xp_gp_pm_enter);
+	mvebu_pm_init(mvebu_armada_pm_enter);
 
 out:
 	of_node_put(np);
 	return ret;
 }
 
-late_initcall(mvebu_armada_xp_gp_pm_init);
+late_initcall(mvebu_armada_pm_init);
-- 
2.1.0

[PATCH 6/9] ARM: mvebu: add suspend/resume support for Armada 38x

[Thomas Petazzoni]

This commit adds support for suspend/resume on Armada 38x, and
specifically for the Armada 388 GP board (since on Marvell EBU
systems, suspend/resume requires board-level specific details). In
details, the needed changes are:

 - Register mvebu_memblock_reserve() as the ->reserve() callback in
   DT_MACHINE_START. This is needed to make sure that the small
   portions of RAM used by the bootloader to do the DDR3 training are
   not used by the kernel, since this training is done again when
   existing from suspend to RAM.

 - Add support for Armada 38x in set_cpu_coherent() by enabling the
   SCU. This will make sure the SCU gets re-enabled after existing
   from suspend to RAM.

 - Add marvell,a388-gp to the list of supported boards in the
   board-specific code pm-board.c. No other changes are needed since
   the Armada 388 GP uses a 3 GPIOs protocol with the PIC
   micro-controller, like the one used on Armada XP GP.

 - Add mvebu_pm_store_armada38x_bootinfo() in pm.c to prepare the
   entry to suspend to RAM by creating the boot information structure
   expected by the bootloader.

 - Add the assembly code in pmsu_ll.S used when returning from suspend
   to RAM.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/board-v7.c  |  1 +
 arch/arm/mach-mvebu/coherency.c |  4 ++++
 arch/arm/mach-mvebu/pm-board.c  |  3 ++-
 arch/arm/mach-mvebu/pm.c        | 41 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/pmsu.h      |  1 +
 arch/arm/mach-mvebu/pmsu_ll.S   | 43 +++++++++++++++++++++++++++++++++++++++++
 6 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index afee908..e5911de 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -230,6 +230,7 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
 	.l2c_aux_mask	= ~0,
 	.init_irq       = mvebu_init_irq,
 	.restart	= mvebu_restart,
+	.reserve        = mvebu_memblock_reserve,
 	.dt_compat	= armada_38x_dt_compat,
 MACHINE_END
 
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 44eedf3..caf4769 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -31,9 +31,11 @@
 #include <linux/mbus.h>
 #include <linux/pci.h>
 #include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
 #include <asm/dma-mapping.h>
+#include "common.h"
 #include "coherency.h"
 #include "mvebu-soc-id.h"
 
@@ -206,6 +208,8 @@ int set_cpu_coherent(void)
 		}
 		ll_add_cpu_to_smp_group();
 		return ll_enable_coherency();
+	} else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380) {
+		scu_enable(mvebu_get_scu_base());
 	}
 
 	return 0;
diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index b8c26cb..0f471fa 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -82,7 +82,8 @@ static int mvebu_armada_pm_init(void)
 	struct device_node *gpio_ctrl_np;
 	int ret = 0, i;
 
-	if (!of_machine_is_compatible("marvell,axp-gp"))
+	if (!of_machine_is_compatible("marvell,axp-gp") &&
+	    !of_machine_is_compatible("marvell,a388-gp"))
 		return -ENODEV;
 
 	np = of_find_node_by_name(NULL, "pm_pic");
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index 02fdf67..90d85ef 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -149,6 +149,45 @@ static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
 	writel(BOOT_MAGIC_LIST_END, store_addr);
 }
 
+static void mvebu_pm_store_armada38x_bootinfo(u32 *store_addr)
+{
+	phys_addr_t resume_pc;
+	extern unsigned char armada_38x_mem_resume_data;
+	void *armada_38x_mem_resume_datap =
+		&armada_38x_mem_resume_data;
+
+	/*
+	 * Provide the internal register address to the resume code in
+	 * assembly. The value must be given in the native endianness
+	 * of the system, hence the usage of the raw variant.
+	 */
+	__raw_writel(mvebu_internal_reg_base(),
+		     armada_38x_mem_resume_datap);
+
+	resume_pc = virt_to_phys(armada_38x_mem_resume);
+
+	/*
+	 * The bootloader expects the first two words to be a magic
+	 * value (BOOT_MAGIC_WORD), followed by the address of the
+	 * resume code to jump to. Then, it expects a sequence of
+	 * (address, value) pairs, which can be used to restore the
+	 * value of certain registers. This sequence must end with the
+	 * BOOT_MAGIC_LIST_END magic value.
+	 */
+
+	writel(BOOT_MAGIC_WORD, store_addr++);
+	writel(resume_pc, store_addr++);
+
+	/*
+	 * We don't restore much registers here compared to Armada XP,
+	 * because we're getting out of the bootloader with MMU
+	 * enabled, so we have to disable it first in
+	 * armada_38x_mem_resume before being able to restore things.
+	 */
+
+	writel(BOOT_MAGIC_LIST_END, store_addr);
+}
+
 static int mvebu_pm_store_bootinfo(void)
 {
 	u32 *store_addr;
@@ -157,6 +196,8 @@ static int mvebu_pm_store_bootinfo(void)
 
 	if (of_machine_is_compatible("marvell,armadaxp"))
 		mvebu_pm_store_armadaxp_bootinfo(store_addr);
+	else if (of_machine_is_compatible("marvell,armada380"))
+		mvebu_pm_store_armada38x_bootinfo(store_addr);
 	else
 		return -ENODEV;
 
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index ea79269..9166e94 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -18,6 +18,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
 
 void mvebu_v7_pmsu_idle_exit(void);
 void armada_370_xp_cpu_resume(void);
+void armada_38x_mem_resume(void);
 
 int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
 int armada_38x_do_cpu_suspend(unsigned long deepidle);
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 8865122..6305d80 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -51,6 +51,49 @@ ARM_BE8(setend	be )			@ go BE8 if entered LE
 	b	cpu_resume
 ENDPROC(armada_38x_cpu_resume)
 
+.global armada_38x_mem_resume_data
+
+#define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
+
+ENTRY(armada_38x_mem_resume)
+ARM_BE8(setend	be )			@ go BE8 if entered LE
+	/* MMU disable, left enabled by the bootloader */
+	mrc	p15, 0, r1, c1, c0, 0
+	bic	r1, #1
+	mcr	p15, 0, r1, c1, c0, 0
+
+	bl      v7_invalidate_l1
+
+	/*
+	 * Load the internal register base address, we keep the value
+	 * unmodified in r1 throughout this function.
+	 */
+	adr	r1, armada_38x_mem_resume_data
+	ldr	r1, [r1]
+
+	/* Restore internal register address */
+	mov	r2, r1
+ARM_BE8(rev	r2, r2)
+	ldr	r3, =MBUS_INTERNAL_REG_ADDRESS
+	str	r2, [r3]
+
+	/* Update SCU offset CP15 register */
+	add	r2, r1, #0xC000
+	mcr  	p15, 4, r2, c15, c0, 0
+
+	/*
+	 * Disable L2 cache, left enabled by the bootloader,
+	 * it will be re-enabled later by the resume logic
+	 */
+	add	r2, r1, #0x8100
+	ldr  	r3, =0x0
+	str  	r3, [r2]
+
+	b 	cpu_resume
+armada_38x_mem_resume_data:
+	.long	.
+ENDPROC(armada_38x_mem_resume)
+
 .global mvebu_boot_wa_start
 .global mvebu_boot_wa_end
 
-- 
2.1.0

[PATCH 7/9] ARM: mvebu: add suspend/resume related definitions in Armada 38x Device Tree

[Thomas Petazzoni]

In order to support suspend/resume, the SoC-level Armada 38x Device
Tree file must be improved with the following additions:

 - Description of the SDRAM controller registers, which are needed in
   order to allow the suspend/resume code to put the RAM in
   self-refresh. This is similar to what was done in commit
   6e6db2bea3ea ("ARM: mvebu: add SDRAM controller description for
   Armada XP") for Armada XP.

 - Description of additional registers for the MBus controller, which
   need to be saved/restored accross a suspend/resume cycle. This is
   similar to what was done in commit 8b7dc9d37a44e ("ARM: mvebu:
   adjust mbus controller description on Armada 370/XP") for Armada
   XP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 218a2ac..ffaf351 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -138,6 +138,11 @@
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 
+			sdramc at 1400 {
+				compatible = "marvell,armada-xp-sdram-controller";
+				reg = <0x1400 0x500>;
+			};
+
 			L2: cache-controller at 8000 {
 				compatible = "arm,pl310-cache";
 				reg = <0x8000 0x1000>;
@@ -369,7 +374,7 @@
 
 			mbusc: mbus-controller at 20000 {
 				compatible = "marvell,mbus-controller";
-				reg = <0x20000 0x100>, <0x20180 0x20>;
+				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
 			};
 
 			mpic: interrupt-controller at 20a00 {
-- 
2.1.0

[PATCH 8/9] ARM: mvebu: add suspend/resume DT information for Armada 388 GP

[Thomas Petazzoni]

This commit improves the Armada 388 GP Device Tree description to
describe the 3 GPIOs that are used to connect the SoC to the PIC
micro-controller that we talk to shutdown the SoC when entering
suspend to RAM.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-388-gp.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 78514ab..5f53a96 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -56,6 +56,14 @@
 		reg = <0x00000000 0x80000000>; /* 2 GB */
 	};
 
+	cpus {
+		pm_pic {
+			ctrl-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>,
+				     <&gpio1 2 GPIO_ACTIVE_LOW>,
+				     <&gpio1 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
@@ -406,8 +414,16 @@
 };
 
 &pinctrl {
+	pinctrl-0 = <&pic_pins>;
+	pinctrl-names = "default";
+
 	pca0_pins: pca0_pins {
 		marvell,pins = "mpp18";
 		marvell,function = "gpio";
 	};
+
+	pic_pins: pic-pins-0 {
+		marvell,pins = "mpp33", "mpp34", "mpp35";
+		marvell,function = "gpio";
+	};
 };
-- 
2.1.0

[PATCH 9/9] ARM: mvebu: adjust board name and compatible for Armada 388 GP

[Thomas Petazzoni]

As the name of the Device Tree file name suggests, the Armada 388 GP
really contains an Armada 388 SoC, so this commit updates the board
name and compatible string in the Device Tree file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-388-gp.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 5f53a96..605f924 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -44,8 +44,8 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-	model = "Marvell Armada 385 GP";
-	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+	model = "Marvell Armada 388 GP";
+	compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-- 
2.1.0

Re: [PATCH 1/9] ARM: mvebu: fix suspend to RAM on big-endian configurations

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:12, Thomas Petazzoni wrote:
> The current Armada XP suspend to RAM implementation, as added in
> commit 27432825ae19f ("ARM: mvebu: Armada XP GP specific
> suspend/resume code") does not handle big-endian configurations
> properly: the small bit of assembly code putting the DRAM in
> self-refresh and toggling the GPIOs to turn off power forgets to
> convert the values to little-endian.
> 
> This commit fixes that by making sure the two values we will write to
> the DRAM controller register and GPIO register are already in
> little-endian before entering the critical assembly code.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: <stable@vger.kernel.org> # v3.19+
> Fixes: 27432825ae19f ("ARM: mvebu: Armada XP GP specific suspend/resume code")


Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

applied on mvebu/fixes

Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/pm-board.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
> index 6dfd4ab..301ab38 100644
> --- a/arch/arm/mach-mvebu/pm-board.c
> +++ b/arch/arm/mach-mvebu/pm-board.c
> @@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
>  	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
>  		ackcmd |= BIT(pic_raw_gpios[i]);
>  
> +	srcmd = cpu_to_le32(srcmd);
> +	ackcmd = cpu_to_le32(ackcmd);
> +
>  	/*
>  	 * Wait a while, the PIC needs quite a bit of time between the
>  	 * two GPIO commands.
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 1/9] ARM: mvebu: fix suspend to RAM on big-endian configurations

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:12, Thomas Petazzoni wrote:
> The current Armada XP suspend to RAM implementation, as added in
> commit 27432825ae19f ("ARM: mvebu: Armada XP GP specific
> suspend/resume code") does not handle big-endian configurations
> properly: the small bit of assembly code putting the DRAM in
> self-refresh and toggling the GPIOs to turn off power forgets to
> convert the values to little-endian.
> 
> This commit fixes that by making sure the two values we will write to
> the DRAM controller register and GPIO register are already in
> little-endian before entering the critical assembly code.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: <stable@vger.kernel.org> # v3.19+
> Fixes: 27432825ae19f ("ARM: mvebu: Armada XP GP specific suspend/resume code")


Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

applied on mvebu/fixes

Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/pm-board.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
> index 6dfd4ab..301ab38 100644
> --- a/arch/arm/mach-mvebu/pm-board.c
> +++ b/arch/arm/mach-mvebu/pm-board.c
> @@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
>  	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
>  		ackcmd |= BIT(pic_raw_gpios[i]);
>  
> +	srcmd = cpu_to_le32(srcmd);
> +	ackcmd = cpu_to_le32(ackcmd);
> +
>  	/*
>  	 * Wait a while, the PIC needs quite a bit of time between the
>  	 * two GPIO commands.
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 2/9] ARM: mvebu: prepare set_cpu_coherent() for future extension

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:12, Thomas Petazzoni wrote:
> From: Nadav Haklai <nadavh@marvell.com>
> 
> This patch prepares the set_cpu_coherent() function in coherency.c to
> be extended to support other SoCs than Armada XP. It will be needed on
> Armada 38x to re-enable the coherency after exiting from suspend to
> RAM.
> 
> This preparation simply moves the function further down in coherency.c
> so that it can use coherency_type(), and uses that function to only do
> the Armada XP specific work if we are on Armada XP.
> 
> Signed-off-by: Nadav Haklai <nadavh@marvell.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/coherency.c | 29 +++++++++++++++++------------
>  1 file changed, 17 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
> index e46e9ea..44eedf3 100644
> --- a/arch/arm/mach-mvebu/coherency.c
> +++ b/arch/arm/mach-mvebu/coherency.c
> @@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = {
>  int ll_enable_coherency(void);
>  void ll_add_cpu_to_smp_group(void);
>  
> -int set_cpu_coherent(void)
> -{
> -	if (!coherency_base) {
> -		pr_warn("Can't make current CPU cache coherent.\n");
> -		pr_warn("Coherency fabric is not initialized\n");
> -		return 1;
> -	}
> -
> -	ll_add_cpu_to_smp_group();
> -	return ll_enable_coherency();
> -}
> -
>  static int mvebu_hwcc_notifier(struct notifier_block *nb,
>  			       unsigned long event, void *__dev)
>  {
> @@ -206,6 +194,23 @@ static int coherency_type(void)
>  	return type;
>  }
>  
> +int set_cpu_coherent(void)
> +{
> +	int type = coherency_type();
> +
> +	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
> +		if (!coherency_base) {
> +			pr_warn("Can't make current CPU cache coherent.\n");
> +			pr_warn("Coherency fabric is not initialized\n");
> +			return 1;
> +		}
> +		ll_add_cpu_to_smp_group();
> +		return ll_enable_coherency();
> +	}
> +
> +	return 0;
> +}
> +
>  int coherency_available(void)
>  {
>  	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 3/9] ARM: mvebu: do not check machine in mvebu_pm_init()

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:12, Thomas Petazzoni wrote:
> The mvebu_pm_init() initializes the support for suspend/resume, and
> before doing that, it checks if we are on a board on which
> suspend/resume is actually supported. However, this check is already
> done by mvebu_armada_xp_gp_pm_init(), and there is no need to
> duplicate the check: callers of mvebu_pm_init() should now what they
> are doing.
> 
> This commit is done in preparation to the addition of suspend/resume
> support on Armada 38x.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/pm.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
> index 6573a8f..eca650b 100644
> --- a/arch/arm/mach-mvebu/pm.c
> +++ b/arch/arm/mach-mvebu/pm.c
> @@ -182,9 +182,6 @@ int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
>  	struct device_node *np;
>  	struct resource res;
>  
> -	if (!of_machine_is_compatible("marvell,armadaxp"))
> -		return -ENODEV;
> -
>  	np = of_find_compatible_node(NULL, NULL,
>  				     "marvell,armada-xp-sdram-controller");
>  	if (!np)
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 4/9] ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:13, Thomas Petazzoni wrote:
> As we are going to introduce support for Armada 38x in pm.c, split out
> the Armada XP part of mvebu_pm_store_bootinfo() into
> mvebu_pm_store_armadaxp_bootinfo(), and make the former retunr an
> error when an unsupported SoC is used.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/pm.c | 25 +++++++++++++++++++++----
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
> index eca650b..02fdf67 100644
> --- a/arch/arm/mach-mvebu/pm.c
> +++ b/arch/arm/mach-mvebu/pm.c
> @@ -105,12 +105,10 @@ static phys_addr_t mvebu_internal_reg_base(void)
>  	return of_translate_address(np, in_addr);
>  }
>  
> -static void mvebu_pm_store_bootinfo(void)
> +static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
>  {
> -	u32 *store_addr;
>  	phys_addr_t resume_pc;
>  
> -	store_addr = phys_to_virt(BOOT_INFO_ADDR);
>  	resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
>  
>  	/*
> @@ -151,14 +149,33 @@ static void mvebu_pm_store_bootinfo(void)
>  	writel(BOOT_MAGIC_LIST_END, store_addr);
>  }
>  
> +static int mvebu_pm_store_bootinfo(void)
> +{
> +	u32 *store_addr;
> +
> +	store_addr = phys_to_virt(BOOT_INFO_ADDR);
> +
> +	if (of_machine_is_compatible("marvell,armadaxp"))
> +		mvebu_pm_store_armadaxp_bootinfo(store_addr);
> +	else
> +		return -ENODEV;
> +
> +	return 0;
> +}
> +
>  static int mvebu_pm_enter(suspend_state_t state)
>  {
> +	int ret;
> +
>  	if (state != PM_SUSPEND_MEM)
>  		return -EINVAL;
>  
> +	ret = mvebu_pm_store_bootinfo();
> +	if (ret)
> +		return ret;
> +
>  	cpu_pm_enter();
>  
> -	mvebu_pm_store_bootinfo();
>  	cpu_suspend(0, mvebu_pm_powerdown);
>  
>  	outer_resume();
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 5/9] ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x support

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:13, Thomas Petazzoni wrote:
> The pm-board.c code contains the board-specific logic to enter suspend
> to RAM. Until now, the code supported only the Armada XP GP board, so
> all functions and symbols were named with armada_xp_gp. However, it
> turns out that the Armada 388 GP also uses the same 3 GPIOs protocol
> to talk to the PIC microcontroller that controls the power supply.
> 
> Since we are going to re-use the same code with no change for Armada
> 38x, this commit renames the functions and symbols to use just
> "armada" instead of "armada_xp_gp". Better names can be found if one
> day other boards having a different protocol/mechanism are supported
> in the kernel.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/pm-board.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
> index 301ab38..b8c26cb 100644
> --- a/arch/arm/mach-mvebu/pm-board.c
> +++ b/arch/arm/mach-mvebu/pm-board.c
> @@ -1,7 +1,7 @@
>  /*
>   * Board-level suspend/resume support.
>   *
> - * Copyright (C) 2014 Marvell
> + * Copyright (C) 2014-2015 Marvell
>   *
>   * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>   *
> @@ -20,27 +20,27 @@
>  #include <linux/slab.h>
>  #include "common.h"
>  
> -#define ARMADA_XP_GP_PIC_NR_GPIOS 3
> +#define ARMADA_PIC_NR_GPIOS 3
>  
>  static void __iomem *gpio_ctrl;
> -static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
> -static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
> +static int pic_gpios[ARMADA_PIC_NR_GPIOS];
> +static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
>  
> -static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
> +static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
>  {
>  	u32 reg, ackcmd;
>  	int i;
>  
>  	/* Put 001 as value on the GPIOs */
>  	reg = readl(gpio_ctrl);
> -	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
> +	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
>  		reg &= ~BIT(pic_raw_gpios[i]);
>  	reg |= BIT(pic_raw_gpios[0]);
>  	writel(reg, gpio_ctrl);
>  
>  	/* Prepare writing 111 to the GPIOs */
>  	ackcmd = readl(gpio_ctrl);
> -	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
> +	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
>  		ackcmd |= BIT(pic_raw_gpios[i]);
>  
>  	srcmd = cpu_to_le32(srcmd);
> @@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
>  		  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
>  }
>  
> -static int mvebu_armada_xp_gp_pm_init(void)
> +static int mvebu_armada_pm_init(void)
>  {
>  	struct device_node *np;
>  	struct device_node *gpio_ctrl_np;
> @@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void)
>  	if (!np)
>  		return -ENODEV;
>  
> -	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) {
> +	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
>  		char *name;
>  		struct of_phandle_args args;
>  
> @@ -134,11 +134,11 @@ static int mvebu_armada_xp_gp_pm_init(void)
>  	if (!gpio_ctrl)
>  		return -ENOMEM;
>  
> -	mvebu_pm_init(mvebu_armada_xp_gp_pm_enter);
> +	mvebu_pm_init(mvebu_armada_pm_enter);
>  
>  out:
>  	of_node_put(np);
>  	return ret;
>  }
>  
> -late_initcall(mvebu_armada_xp_gp_pm_init);
> +late_initcall(mvebu_armada_pm_init);
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 9/9] ARM: mvebu: adjust board name and compatible for Armada 388 GP

[Gregory CLEMENT]

Hi Thomas,

On 16/06/2015 14:13, Thomas Petazzoni wrote:
> As the name of the Device Tree file name suggests, the Armada 388 GP
> really contains an Armada 388 SoC, so this commit updates the board
> name and compatible string in the Device Tree file.

Actually the name of the board (the one written on the box) is DB-88F6820-GP.
And 88F6820 is the code name of Armada 385. But indeed the SoC is an Armada 388
on our boards.

Gregory

> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-388-gp.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
> index 5f53a96..605f924 100644
> --- a/arch/arm/boot/dts/armada-388-gp.dts
> +++ b/arch/arm/boot/dts/armada-388-gp.dts
> @@ -44,8 +44,8 @@
>  #include <dt-bindings/gpio/gpio.h>
>  
>  / {
> -	model = "Marvell Armada 385 GP";
> -	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
> +	model = "Marvell Armada 388 GP";
> +	compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
>  
>  	chosen {
>  		stdout-path = "serial0:115200n8";
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 9/9] ARM: mvebu: adjust board name and compatible for Armada 388 GP

[Thomas Petazzoni]

Dear Gregory CLEMENT,

On Wed, 17 Jun 2015 18:31:09 +0200, Gregory CLEMENT wrote:

> On 16/06/2015 14:13, Thomas Petazzoni wrote:
> > As the name of the Device Tree file name suggests, the Armada 388 GP
> > really contains an Armada 388 SoC, so this commit updates the board
> > name and compatible string in the Device Tree file.
> 
> Actually the name of the board (the one written on the box) is DB-88F6820-GP.
> And 88F6820 is the code name of Armada 385. But indeed the SoC is an Armada 388
> on our boards.

So what do you suggest exactly for the model and compatible strings?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com