[U-Boot] [PATCH v3 0/8] dm: x86: PCI/SPI fixes for minnowboard MAX

[U-Boot] [PATCH v3 0/8] dm: x86: PCI/SPI fixes for minnowboard MAX

[Simon Glass]

The SPI flash starts off protected on baytrail. The code which is supposed to
fix this is broken. This series fixes that, enables the SPI environment and
adds documentation.

Also when driver model is enabled for PCI some bugs appear. This series fixes
those and enables driver model for PCI on minnowboard MAX.

Changes in v3:
- Correct parameter order with ich_writeb()
- Drop the asm/pci.h header file also
- Drop the patch to board_f.c as it is not needed, and interferes with the fix
- Add a comment about why gd->pci_ram_top is being set

Changes in v2:
- Continue to use writew for ICH7
- Use ich_read/write() for BIOS protection update
- Fix typos in README.x86
- Rename the ops and ids arrays for consistency
- Drop the coreboot PCI driver which is no-longer needed
- Only limit the PCI system memory region on x86 machines
- Use md5sum -b
- Rebase on x86/master

Simon Glass (8):
  dm: spi: Correct status register access width
  dm: spi: Correct BIOS protection logic for ICH9
  dm: spi: Enable environment for minnowmax
  x86: Add ROM image description for minnowmax
  x86: pci: Tidy up the generic x86 PCI driver
  dm: x86: minnowmax: Move PCI to use driver model
  dm: x86: baytrail: Correct PCI region 3 when driver model is used
  x86: Add binary blob checksums for Minnowboard MAX

 arch/x86/cpu/baytrail/Makefile    |  1 -
 arch/x86/cpu/baytrail/pci.c       | 46 ---------------------------------------
 arch/x86/cpu/coreboot/pci.c       | 22 -------------------
 arch/x86/cpu/cpu.c                |  2 ++
 arch/x86/dts/minnowmax.dts        | 10 +++++++++
 configs/minnowmax_defconfig       |  1 +
 doc/README.x86                    | 25 +++++++++++++++++++++
 drivers/pci/pci-uclass.c          |  8 +++++--
 drivers/pci/pci_x86.c             | 13 ++++++-----
 drivers/spi/ich.c                 | 15 ++++++++-----
 include/asm-generic/global_data.h |  1 +
 include/configs/minnowmax.h       |  6 ++---
 12 files changed, 65 insertions(+), 85 deletions(-)
 delete mode 100644 arch/x86/cpu/baytrail/pci.c

-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 1/8] dm: spi: Correct status register access width

[Simon Glass]

The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
---

Changes in v3: None
Changes in v2:
- Continue to use writew for ICH7

 drivers/spi/ich.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 6b6cfbf..66a5cba 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -411,6 +411,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			const void *dout, void *din, unsigned long flags)
 {
 	struct udevice *bus = dev_get_parent(dev);
+	struct ich_spi_platdata *plat = dev_get_platdata(bus);
 	struct ich_spi_priv *ctlr = dev_get_priv(bus);
 	uint16_t control;
 	int16_t opcode_index;
@@ -477,7 +478,10 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (ret < 0)
 		return ret;
 
-	ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+	if (plat->ich_version == 7)
+		ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+	else
+		ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 
 	spi_setup_type(trans, using_cmd ? bytes : 0);
 	opcode_index = spi_setup_opcode(ctlr, trans);
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 2/8] dm: spi: Correct BIOS protection logic for ICH9

[Simon Glass]

The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Correct parameter order with ich_writeb()

Changes in v2:
- Use ich_read/write() for BIOS protection update

 drivers/spi/ich.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 66a5cba..2e388e7 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -40,6 +40,7 @@ struct ich_spi_priv {
 	int status;
 	int control;
 	int bbar;
+	int bcr;
 	uint32_t *pr;		/* only for ich9 */
 	int speed;		/* pointer to speed control */
 	ulong max_speed;	/* Maximum bus speed in MHz */
@@ -239,6 +240,7 @@ static int ich_init_controller(struct ich_spi_platdata *plat,
 		ctlr->speed = ctlr->control + 2;
 		ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
 		ctlr->preop = offsetof(struct ich9_spi_regs, preop);
+		ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
 		ctlr->pr = &ich9_spi->pr[0];
 		ctlr->base = ich9_spi;
 	} else {
@@ -688,13 +690,10 @@ static int ich_spi_probe(struct udevice *bus)
 	 * v9, deassert SMM BIOS Write Protect Disable.
 	 */
 	if (plat->use_sbase) {
-		struct ich9_spi_regs *ich9_spi;
-
-		ich9_spi = priv->base;
-		bios_cntl = ich_readb(priv, ich9_spi->bcr);
+		bios_cntl = ich_readb(priv, priv->bcr);
 		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
-		ich_writeb(priv, bios_cntl, ich9_spi->bcr);
+		ich_writeb(priv, bios_cntl, priv->bcr);
 	} else {
 		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
 		if (plat->ich_version == 9)
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 3/8] dm: spi: Enable environment for minnowmax

[Simon Glass]

Enable a SPI environment and store it in a suitable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
---

Changes in v3: None
Changes in v2: None

 include/configs/minnowmax.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 547765d..d4d28a7 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -65,8 +65,7 @@
 /* Avoid a warning in the Realtek Ethernet driver */
 #define CONFIG_SYS_CACHELINE_SIZE 16
 
-/* Environment in SPI flash is unsupported for now */
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x007fe000
 
 #endif	/* __CONFIG_H */
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 4/8] x86: Add ROM image description for minnowmax

[Simon Glass]

The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Fix typos in README.x86

 doc/README.x86 | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86
index 49d6e83..e58ca19 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -160,6 +160,23 @@ Now you can build U-Boot and obtain u-boot.rom
 $ make minnowmax_defconfig
 $ make all
 
+The ROM image is broken up into these parts:
+
+Offset   Description         Controlling config
+------------------------------------------------------------
+000000   descriptor.bin      Hard-coded to 0 in ifdtool
+001000   me.bin              Set by the descriptor
+500000   <spare>
+700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
+790000   vga.bin             CONFIG_X86_OPTION_ROM_ADDR
+7c0000   fsp.bin             CONFIG_FSP_ADDR
+7f8000   <spare>             (depends on size of fsp.bin)
+7fe000   Environment         CONFIG_ENV_OFFSET
+7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
+
+Overall ROM image size is controlled by CONFIG_ROM_SIZE.
+
+
 Intel Galileo instructions:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 5/8] x86: pci: Tidy up the generic x86 PCI driver

[Simon Glass]

This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop the asm/pci.h header file also

Changes in v2:
- Rename the ops and ids arrays for consistency
- Drop the coreboot PCI driver which is no-longer needed

 arch/x86/cpu/coreboot/pci.c | 22 ----------------------
 drivers/pci/pci_x86.c       | 13 ++++++++-----
 2 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 67eb14c..41e29a6 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -11,29 +11,7 @@
 
 #include <common.h>
 #include <dm.h>
-#include <errno.h>
 #include <pci.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct dm_pci_ops pci_x86_ops = {
-	.read_config	= pci_x86_read_config,
-	.write_config	= pci_x86_write_config,
-};
-
-static const struct udevice_id pci_x86_ids[] = {
-	{ .compatible = "pci-x86" },
-	{ }
-};
-
-U_BOOT_DRIVER(pci_x86_drv) = {
-	.name		= "pci_x86",
-	.id		= UCLASS_PCI,
-	.of_match	= pci_x86_ids,
-	.ops		= &pci_x86_ops,
-};
 
 static const struct udevice_id generic_pch_ids[] = {
 	{ .compatible = "intel,pch" },
diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
index 901bdca..89e8c11 100644
--- a/drivers/pci/pci_x86.c
+++ b/drivers/pci/pci_x86.c
@@ -7,18 +7,21 @@
 #include <common.h>
 #include <dm.h>
 #include <pci.h>
+#include <asm/pci.h>
 
-static const struct dm_pci_ops x86_pci_ops = {
+static const struct dm_pci_ops pci_x86_ops = {
+	.read_config	= pci_x86_read_config,
+	.write_config	= pci_x86_write_config,
 };
 
-static const struct udevice_id x86_pci_ids[] = {
-	{ .compatible = "x86,pci" },
+static const struct udevice_id pci_x86_ids[] = {
+	{ .compatible = "pci-x86" },
 	{ }
 };
 
 U_BOOT_DRIVER(pci_x86) = {
 	.name	= "pci_x86",
 	.id	= UCLASS_PCI,
-	.of_match = x86_pci_ids,
-	.ops	= &x86_pci_ops,
+	.of_match = pci_x86_ids,
+	.ops	= &pci_x86_ops,
 };
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 6/8] dm: x86: minnowmax: Move PCI to use driver model

[Simon Glass]

Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/baytrail/Makefile |  1 -
 arch/x86/cpu/baytrail/pci.c    | 46 ------------------------------------------
 arch/x86/dts/minnowmax.dts     | 10 +++++++++
 configs/minnowmax_defconfig    |  1 +
 include/configs/minnowmax.h    |  1 +
 5 files changed, 12 insertions(+), 47 deletions(-)
 delete mode 100644 arch/x86/cpu/baytrail/pci.c

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index c78b644..5be5491 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -7,5 +7,4 @@
 obj-y += cpu.o
 obj-y += early_uart.o
 obj-y += fsp_configs.o
-obj-y += pci.o
 obj-y += valleyview.o
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
deleted file mode 100644
index 48409de..0000000
--- a/arch/x86/cpu/baytrail/pci.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/fsp/fsp_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_PREF_BUS,
-		       CONFIG_PCI_PREF_PHYS,
-		       CONFIG_PCI_PREF_SIZE,
-		       PCI_REGION_PREFETCH);
-
-	pci_set_region(hose->regions + 3,
-		       0,
-		       0,
-		       gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 4;
-}
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index bd21bfb..0e59b18 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -111,6 +111,16 @@
 
 	};
 
+	pci {
+		compatible = "intel,pci-baytrail", "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+	};
+
 	spi {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 744aca3..ff2bfda 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -12,3 +12,4 @@ CONFIG_CMD_CPU=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
+CONFIG_DM_PCI=y
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index d4d28a7..41653ba 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -32,6 +32,7 @@
 #define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE		0xe000
 
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 #define CONFIG_RTL8169
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 7/8] dm: x86: baytrail: Correct PCI region 3 when driver model is used

[Simon Glass]

Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop the patch to board_f.c as it is not needed, and interferes with the fix
- Add a comment about why gd->pci_ram_top is being set

Changes in v2:
- Only limit the PCI system memory region on x86 machines

 arch/x86/cpu/cpu.c                | 2 ++
 drivers/pci/pci-uclass.c          | 8 ++++++--
 include/asm-generic/global_data.h | 1 +
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index d108ee5..2b6ed11 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -351,6 +351,8 @@ int x86_cpu_init_f(void)
 
 		gd->arch.has_mtrr = has_mtrr();
 	}
+	/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+	gd->pci_ram_top = 0x80000000U;
 
 	return 0;
 }
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index edec93f..5b91fe3 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
 {
 	int pci_addr_cells, addr_cells, size_cells;
 	int cells_per_record;
+	phys_addr_t addr;
 	const u32 *prop;
 	int len;
 	int i;
@@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
 	}
 
 	/* Add a region for our local memory */
-	pci_set_region(hose->regions + hose->region_count++, 0, 0,
-		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+	addr = gd->ram_size;
+	if (gd->pci_ram_top && gd->pci_ram_top < addr)
+		addr = gd->pci_ram_top;
+	pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	return 0;
 }
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 6747619..db0550b 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -93,6 +93,7 @@ typedef struct global_data {
 #endif
 #ifdef CONFIG_PCI
 	struct pci_controller *hose;	/* PCI hose for early use */
+	phys_addr_t pci_ram_top;	/* top of region accessible to PCI */
 #endif
 #ifdef CONFIG_PCI_BOOTDELAY
 	int pcidelay_done;
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 8/8] x86: Add binary blob checksums for Minnowboard MAX

[Simon Glass]

To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- Use md5sum -b
- Rebase on x86/master

 doc/README.x86 | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86
index e58ca19..022898d 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -160,6 +160,14 @@ Now you can build U-Boot and obtain u-boot.rom
 $ make minnowmax_defconfig
 $ make all
 
+Checksums are as follows (but note that newer versions will invalidate this):
+
+$ md5sum -b board/intel/minnowmax/*.bin
+ffda9a3b94df5b74323afb328d51e6b4  board/intel/minnowmax/descriptor.bin
+69f65b9a580246291d20d08cbef9d7c5  board/intel/minnowmax/fsp.bin
+894a97d371544ec21de9c3e8e1716c4b  board/intel/minnowmax/me.bin
+a2588537da387da592a27219d56e9962  board/intel/minnowmax/vga.bin
+
 The ROM image is broken up into these parts:
 
 Offset   Description         Controlling config
-- 
2.4.3.573.g4eafbef

[U-Boot] [PATCH v3 2/8] dm: spi: Correct BIOS protection logic for ICH9

[Bin Meng]

On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
> The logic is incorrect and currently has no effect. Fix it so that we can
> write to SPI flash, since by default it is write-protected.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Correct parameter order with ich_writeb()
>
> Changes in v2:
> - Use ich_read/write() for BIOS protection update
>
>  drivers/spi/ich.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index 66a5cba..2e388e7 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -40,6 +40,7 @@ struct ich_spi_priv {
>         int status;
>         int control;
>         int bbar;
> +       int bcr;
>         uint32_t *pr;           /* only for ich9 */
>         int speed;              /* pointer to speed control */
>         ulong max_speed;        /* Maximum bus speed in MHz */
> @@ -239,6 +240,7 @@ static int ich_init_controller(struct ich_spi_platdata *plat,
>                 ctlr->speed = ctlr->control + 2;
>                 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
>                 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
> +               ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
>                 ctlr->pr = &ich9_spi->pr[0];
>                 ctlr->base = ich9_spi;
>         } else {
> @@ -688,13 +690,10 @@ static int ich_spi_probe(struct udevice *bus)
>          * v9, deassert SMM BIOS Write Protect Disable.
>          */
>         if (plat->use_sbase) {
> -               struct ich9_spi_regs *ich9_spi;
> -
> -               ich9_spi = priv->base;
> -               bios_cntl = ich_readb(priv, ich9_spi->bcr);
> +               bios_cntl = ich_readb(priv, priv->bcr);
>                 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
>                 bios_cntl |= 1;         /* Write Protect Disable (WPD) */
> -               ich_writeb(priv, bios_cntl, ich9_spi->bcr);
> +               ich_writeb(priv, bios_cntl, priv->bcr);
>         } else {
>                 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
>                 if (plat->ich_version == 9)
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 5/8] x86: pci: Tidy up the generic x86 PCI driver

[Bin Meng]

On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
> This driver should use the x86 PCI configuration functions. Also adjust its
> compatible string to something generic (i.e. without a vendor name).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop the asm/pci.h header file also
>
> Changes in v2:
> - Rename the ops and ids arrays for consistency
> - Drop the coreboot PCI driver which is no-longer needed
>
>  arch/x86/cpu/coreboot/pci.c | 22 ----------------------
>  drivers/pci/pci_x86.c       | 13 ++++++++-----
>  2 files changed, 8 insertions(+), 27 deletions(-)
>
> diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
> index 67eb14c..41e29a6 100644
> --- a/arch/x86/cpu/coreboot/pci.c
> +++ b/arch/x86/cpu/coreboot/pci.c
> @@ -11,29 +11,7 @@
>
>  #include <common.h>
>  #include <dm.h>
> -#include <errno.h>
>  #include <pci.h>
> -#include <asm/io.h>
> -#include <asm/pci.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static const struct dm_pci_ops pci_x86_ops = {
> -       .read_config    = pci_x86_read_config,
> -       .write_config   = pci_x86_write_config,
> -};
> -
> -static const struct udevice_id pci_x86_ids[] = {
> -       { .compatible = "pci-x86" },
> -       { }
> -};
> -
> -U_BOOT_DRIVER(pci_x86_drv) = {
> -       .name           = "pci_x86",
> -       .id             = UCLASS_PCI,
> -       .of_match       = pci_x86_ids,
> -       .ops            = &pci_x86_ops,
> -};
>
>  static const struct udevice_id generic_pch_ids[] = {
>         { .compatible = "intel,pch" },
> diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
> index 901bdca..89e8c11 100644
> --- a/drivers/pci/pci_x86.c
> +++ b/drivers/pci/pci_x86.c
> @@ -7,18 +7,21 @@
>  #include <common.h>
>  #include <dm.h>
>  #include <pci.h>
> +#include <asm/pci.h>
>
> -static const struct dm_pci_ops x86_pci_ops = {
> +static const struct dm_pci_ops pci_x86_ops = {
> +       .read_config    = pci_x86_read_config,
> +       .write_config   = pci_x86_write_config,
>  };
>
> -static const struct udevice_id x86_pci_ids[] = {
> -       { .compatible = "x86,pci" },
> +static const struct udevice_id pci_x86_ids[] = {
> +       { .compatible = "pci-x86" },
>         { }
>  };
>
>  U_BOOT_DRIVER(pci_x86) = {
>         .name   = "pci_x86",
>         .id     = UCLASS_PCI,
> -       .of_match = x86_pci_ids,
> -       .ops    = &x86_pci_ops,
> +       .of_match = pci_x86_ids,
> +       .ops    = &pci_x86_ops,
>  };
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 7/8] dm: x86: baytrail: Correct PCI region 3 when driver model is used

[Bin Meng]

On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
> Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
> model code handles this also.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop the patch to board_f.c as it is not needed, and interferes with the fix
> - Add a comment about why gd->pci_ram_top is being set
>
> Changes in v2:
> - Only limit the PCI system memory region on x86 machines
>
>  arch/x86/cpu/cpu.c                | 2 ++
>  drivers/pci/pci-uclass.c          | 8 ++++++--
>  include/asm-generic/global_data.h | 1 +
>  3 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index d108ee5..2b6ed11 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -351,6 +351,8 @@ int x86_cpu_init_f(void)
>
>                 gd->arch.has_mtrr = has_mtrr();
>         }
> +       /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
> +       gd->pci_ram_top = 0x80000000U;
>
>         return 0;
>  }
> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> index edec93f..5b91fe3 100644
> --- a/drivers/pci/pci-uclass.c
> +++ b/drivers/pci/pci-uclass.c
> @@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
>  {
>         int pci_addr_cells, addr_cells, size_cells;
>         int cells_per_record;
> +       phys_addr_t addr;
>         const u32 *prop;
>         int len;
>         int i;
> @@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
>         }
>
>         /* Add a region for our local memory */
> -       pci_set_region(hose->regions + hose->region_count++, 0, 0,
> -                      gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
> +       addr = gd->ram_size;
> +       if (gd->pci_ram_top && gd->pci_ram_top < addr)
> +               addr = gd->pci_ram_top;
> +       pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
> +                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>
>         return 0;
>  }
> diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
> index 6747619..db0550b 100644
> --- a/include/asm-generic/global_data.h
> +++ b/include/asm-generic/global_data.h
> @@ -93,6 +93,7 @@ typedef struct global_data {
>  #endif
>  #ifdef CONFIG_PCI
>         struct pci_controller *hose;    /* PCI hose for early use */
> +       phys_addr_t pci_ram_top;        /* top of region accessible to PCI */
>  #endif
>  #ifdef CONFIG_PCI_BOOTDELAY
>         int pcidelay_done;
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 8/8] x86: Add binary blob checksums for Minnowboard MAX

[Bin Meng]

On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
> To try to reduce the pain of confusion of binary blobs, add MD5 checksums
> for the current versions. This may worsen the situation as new versions
> appear, but it should still be possible to obtain these versions, and thus
> get a working setup.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Use md5sum -b
> - Rebase on x86/master
>
>  doc/README.x86 | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/doc/README.x86 b/doc/README.x86
> index e58ca19..022898d 100644
> --- a/doc/README.x86
> +++ b/doc/README.x86
> @@ -160,6 +160,14 @@ Now you can build U-Boot and obtain u-boot.rom
>  $ make minnowmax_defconfig
>  $ make all
>
> +Checksums are as follows (but note that newer versions will invalidate this):
> +
> +$ md5sum -b board/intel/minnowmax/*.bin
> +ffda9a3b94df5b74323afb328d51e6b4  board/intel/minnowmax/descriptor.bin
> +69f65b9a580246291d20d08cbef9d7c5  board/intel/minnowmax/fsp.bin
> +894a97d371544ec21de9c3e8e1716c4b  board/intel/minnowmax/me.bin
> +a2588537da387da592a27219d56e9962  board/intel/minnowmax/vga.bin
> +
>  The ROM image is broken up into these parts:
>
>  Offset   Description         Controlling config
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 2/8] dm: spi: Correct BIOS protection logic for ICH9

[Andrew Bradford]

On 07/03 18:28, Simon Glass wrote:
> The logic is incorrect and currently has no effect. Fix it so that we can
> write to SPI flash, since by default it is write-protected.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v3:
> - Correct parameter order with ich_writeb()
> 
> Changes in v2:
> - Use ich_read/write() for BIOS protection update
> 
>  drivers/spi/ich.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)

Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>

Thanks! :)
-Andrew

[U-Boot] [PATCH v3 1/8] dm: spi: Correct status register access width

[Simon Glass]

On 3 July 2015 at 18:28, Simon Glass <sjg@chromium.org> wrote:
> The status register on ICH9 is a single byte, so use byte access when
> writing to it, to avoid updating the control register also.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Continue to use writew for ICH7
>
>  drivers/spi/ich.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)

Applied to u-boot-x86.

[U-Boot] [PATCH v3 2/8] dm: spi: Correct BIOS protection logic for ICH9

[Simon Glass]

On 6 July 2015 at 10:45, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> On 07/03 18:28, Simon Glass wrote:
>> The logic is incorrect and currently has no effect. Fix it so that we can
>> write to SPI flash, since by default it is write-protected.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Correct parameter order with ich_writeb()
>>
>> Changes in v2:
>> - Use ich_read/write() for BIOS protection update
>>
>>  drivers/spi/ich.c | 9 ++++-----
>>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>
> Thanks! :)
> -Andrew

Applied to u-boot-x86.

[U-Boot] [PATCH v3 3/8] dm: spi: Enable environment for minnowmax

[Simon Glass]

On 3 July 2015 at 18:28, Simon Glass <sjg@chromium.org> wrote:
> Enable a SPI environment and store it in a suitable place.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  include/configs/minnowmax.h | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)

Applied to u-boot-x86.

[U-Boot] [PATCH v3 4/8] x86: Add ROM image description for minnowmax

[Simon Glass]

On 3 July 2015 at 18:28, Simon Glass <sjg@chromium.org> wrote:
> The layout of the ROM is a bit hard to discover by reading the code. Add
> a table to make it easier.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Fix typos in README.x86
>
>  doc/README.x86 | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)

Applied to u-boot-x86.

[U-Boot] [PATCH v3 5/8] x86: pci: Tidy up the generic x86 PCI driver

[Simon Glass]

On 5 July 2015 at 21:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
>> This driver should use the x86 PCI configuration functions. Also adjust its
>> compatible string to something generic (i.e. without a vendor name).
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Drop the asm/pci.h header file also
>>
>> Changes in v2:
>> - Rename the ops and ids arrays for consistency
>> - Drop the coreboot PCI driver which is no-longer needed
>>
>>  arch/x86/cpu/coreboot/pci.c | 22 ----------------------
>>  drivers/pci/pci_x86.c       | 13 ++++++++-----
>>  2 files changed, 8 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
>> index 67eb14c..41e29a6 100644
>> --- a/arch/x86/cpu/coreboot/pci.c
>> +++ b/arch/x86/cpu/coreboot/pci.c
>> @@ -11,29 +11,7 @@
>>
>>  #include <common.h>
>>  #include <dm.h>
>> -#include <errno.h>
>>  #include <pci.h>
>> -#include <asm/io.h>
>> -#include <asm/pci.h>
>> -
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> -static const struct dm_pci_ops pci_x86_ops = {
>> -       .read_config    = pci_x86_read_config,
>> -       .write_config   = pci_x86_write_config,
>> -};
>> -
>> -static const struct udevice_id pci_x86_ids[] = {
>> -       { .compatible = "pci-x86" },
>> -       { }
>> -};
>> -
>> -U_BOOT_DRIVER(pci_x86_drv) = {
>> -       .name           = "pci_x86",
>> -       .id             = UCLASS_PCI,
>> -       .of_match       = pci_x86_ids,
>> -       .ops            = &pci_x86_ops,
>> -};
>>
>>  static const struct udevice_id generic_pch_ids[] = {
>>         { .compatible = "intel,pch" },
>> diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
>> index 901bdca..89e8c11 100644
>> --- a/drivers/pci/pci_x86.c
>> +++ b/drivers/pci/pci_x86.c
>> @@ -7,18 +7,21 @@
>>  #include <common.h>
>>  #include <dm.h>
>>  #include <pci.h>
>> +#include <asm/pci.h>
>>
>> -static const struct dm_pci_ops x86_pci_ops = {
>> +static const struct dm_pci_ops pci_x86_ops = {
>> +       .read_config    = pci_x86_read_config,
>> +       .write_config   = pci_x86_write_config,
>>  };
>>
>> -static const struct udevice_id x86_pci_ids[] = {
>> -       { .compatible = "x86,pci" },
>> +static const struct udevice_id pci_x86_ids[] = {
>> +       { .compatible = "pci-x86" },
>>         { }
>>  };
>>
>>  U_BOOT_DRIVER(pci_x86) = {
>>         .name   = "pci_x86",
>>         .id     = UCLASS_PCI,
>> -       .of_match = x86_pci_ids,
>> -       .ops    = &x86_pci_ops,
>> +       .of_match = pci_x86_ids,
>> +       .ops    = &pci_x86_ops,
>>  };
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Applied to u-boot-x86.

[U-Boot] [PATCH v3 6/8] dm: x86: minnowmax: Move PCI to use driver model

[Simon Glass]

On 3 July 2015 at 18:28, Simon Glass <sjg@chromium.org> wrote:
> Adjust minnowmax to use driver model for PCI. This requires adding a device
> tree node to specify the ranges, removing the board-specific PCI code and
> ensuring that the host bridge is configured.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/baytrail/Makefile |  1 -
>  arch/x86/cpu/baytrail/pci.c    | 46 ------------------------------------------
>  arch/x86/dts/minnowmax.dts     | 10 +++++++++
>  configs/minnowmax_defconfig    |  1 +
>  include/configs/minnowmax.h    |  1 +
>  5 files changed, 12 insertions(+), 47 deletions(-)
>  delete mode 100644 arch/x86/cpu/baytrail/pci.c

Applied to u-boot-x86.

[U-Boot] [PATCH v3 7/8] dm: x86: baytrail: Correct PCI region 3 when driver model is used

[Simon Glass]

On 5 July 2015 at 21:22, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
>> Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
>> model code handles this also.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Drop the patch to board_f.c as it is not needed, and interferes with the fix
>> - Add a comment about why gd->pci_ram_top is being set
>>
>> Changes in v2:
>> - Only limit the PCI system memory region on x86 machines
>>
>>  arch/x86/cpu/cpu.c                | 2 ++
>>  drivers/pci/pci-uclass.c          | 8 ++++++--
>>  include/asm-generic/global_data.h | 1 +
>>  3 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>> index d108ee5..2b6ed11 100644
>> --- a/arch/x86/cpu/cpu.c
>> +++ b/arch/x86/cpu/cpu.c
>> @@ -351,6 +351,8 @@ int x86_cpu_init_f(void)
>>
>>                 gd->arch.has_mtrr = has_mtrr();
>>         }
>> +       /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
>> +       gd->pci_ram_top = 0x80000000U;
>>
>>         return 0;
>>  }
>> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
>> index edec93f..5b91fe3 100644
>> --- a/drivers/pci/pci-uclass.c
>> +++ b/drivers/pci/pci-uclass.c
>> @@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
>>  {
>>         int pci_addr_cells, addr_cells, size_cells;
>>         int cells_per_record;
>> +       phys_addr_t addr;
>>         const u32 *prop;
>>         int len;
>>         int i;
>> @@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
>>         }
>>
>>         /* Add a region for our local memory */
>> -       pci_set_region(hose->regions + hose->region_count++, 0, 0,
>> -                      gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>> +       addr = gd->ram_size;
>> +       if (gd->pci_ram_top && gd->pci_ram_top < addr)
>> +               addr = gd->pci_ram_top;
>> +       pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
>> +                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>>
>>         return 0;
>>  }
>> diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
>> index 6747619..db0550b 100644
>> --- a/include/asm-generic/global_data.h
>> +++ b/include/asm-generic/global_data.h
>> @@ -93,6 +93,7 @@ typedef struct global_data {
>>  #endif
>>  #ifdef CONFIG_PCI
>>         struct pci_controller *hose;    /* PCI hose for early use */
>> +       phys_addr_t pci_ram_top;        /* top of region accessible to PCI */
>>  #endif
>>  #ifdef CONFIG_PCI_BOOTDELAY
>>         int pcidelay_done;
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Applied to u-boot-x86.

[U-Boot] [PATCH v3 8/8] x86: Add binary blob checksums for Minnowboard MAX

[Simon Glass]

On 5 July 2015 at 21:23, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Jul 4, 2015 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
>> To try to reduce the pain of confusion of binary blobs, add MD5 checksums
>> for the current versions. This may worsen the situation as new versions
>> appear, but it should still be possible to obtain these versions, and thus
>> get a working setup.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3: None
>> Changes in v2:
>> - Use md5sum -b
>> - Rebase on x86/master
>>
>>  doc/README.x86 | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/doc/README.x86 b/doc/README.x86
>> index e58ca19..022898d 100644
>> --- a/doc/README.x86
>> +++ b/doc/README.x86
>> @@ -160,6 +160,14 @@ Now you can build U-Boot and obtain u-boot.rom
>>  $ make minnowmax_defconfig
>>  $ make all
>>
>> +Checksums are as follows (but note that newer versions will invalidate this):
>> +
>> +$ md5sum -b board/intel/minnowmax/*.bin
>> +ffda9a3b94df5b74323afb328d51e6b4  board/intel/minnowmax/descriptor.bin
>> +69f65b9a580246291d20d08cbef9d7c5  board/intel/minnowmax/fsp.bin
>> +894a97d371544ec21de9c3e8e1716c4b  board/intel/minnowmax/me.bin
>> +a2588537da387da592a27219d56e9962  board/intel/minnowmax/vga.bin
>> +
>>  The ROM image is broken up into these parts:
>>
>>  Offset   Description         Controlling config
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Applied to u-boot-x86.