* [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support
@ 2015-07-20 11:28 Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
` (14 more replies)
0 siblings, 15 replies; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Add i.MX 6UltraLite support and include mx6ul_14x14_evk basic board support.
i.MX 6UltraLite is a high performance, ultra-efficient processor family
featuring an advanced implementation of a single Cortex-A7 core.
This patch set is based on i.MX6QP patch v5 set:
https://patchwork.ozlabs.org/patch/493961/
https://patchwork.ozlabs.org/patch/493962/
https://patchwork.ozlabs.org/patch/493963/
https://patchwork.ozlabs.org/patch/493964/
https://patchwork.ozlabs.org/patch/493965/
https://patchwork.ozlabs.org/patch/493966/
Changes v3:
1. fix WDOG3_BASE_ADDR according Marek's suggestion for patch 3/15
2. Add uboot boot log for patch 15/15
Changes v2:
1. refine commit msg
2. split CONFIG_SYS_CACHELINE_SIZE part into a single patch
3. discard system counter, default use GPT now.
4. SPL support
Peng Fan (15):
imx: mx6ul: Add i.MX6UL CPU type
imx: mx6ul: Add pins IOMUX head file
imx: mx6ul: Update imx registers head file
imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
imx-common: timer: add i.MX6UL support
imx: mx6ul remove errata for i.MX6UL
imx:mx6ul add clock support
imx: mx6ul select SYS_L2CACHE_OFF
imx: mx6ul update soc related settings
imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
mxc: gpio add i.MX6UL support
mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
imx:mx6ul add dram spl configuration and header file
imx: imx6_spl add mx6ul support
imx: mx6ul_14x14_evk add basic board support
arch/arm/Kconfig | 8 +
arch/arm/cpu/armv7/mx6/Kconfig | 4 +
arch/arm/cpu/armv7/mx6/clock.c | 151 +--
arch/arm/cpu/armv7/mx6/ddr.c | 61 +-
arch/arm/cpu/armv7/mx6/soc.c | 9 +-
arch/arm/imx-common/cpu.c | 2 +
arch/arm/imx-common/timer.c | 8 +-
arch/arm/include/asm/arch-imx/cpu.h | 3 +-
arch/arm/include/asm/arch-mx6/crm_regs.h | 98 +-
arch/arm/include/asm/arch-mx6/imx-regs.h | 64 +-
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 45 +
arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 +
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 45 +
arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1065 +++++++++++++++++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 4 +
board/freescale/mx6ul_14x14_evk/Kconfig | 15 +
board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 +
board/freescale/mx6ul_14x14_evk/Makefile | 6 +
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++
configs/mx6ul_14x14_evk_defconfig | 4 +
drivers/gpio/mxc_gpio.c | 4 +
include/configs/imx6_spl.h | 2 +-
include/configs/mx6_common.h | 6 +-
include/configs/mx6ul_14x14_evk.h | 227 +++++
24 files changed, 2338 insertions(+), 137 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul_pins.h
create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig
create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS
create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile
create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
create mode 100644 configs/mx6ul_14x14_evk_defconfig
create mode 100644 include/configs/mx6ul_14x14_evk.h
--
1.8.4
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:05 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file Peng Fan
` (13 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes v3:
None
Changes v2:
Refine commit msg.
arch/arm/imx-common/cpu.c | 2 ++
arch/arm/include/asm/arch-imx/cpu.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 096d22e..e27546c 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -138,6 +138,8 @@ const char *get_imx_type(u32 imxtype)
return "6SL"; /* Solo-Lite version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
+ case MXC_CPU_MX6UL:
+ return "6UL"; /* Ultra-Lite version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 99e0e32..c7f9fff 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -10,8 +10,9 @@
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SX 0x62
#define MXC_CPU_MX6Q 0x63
-#define MXC_CPU_MX6D 0x64
+#define MXC_CPU_MX6UL 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
+#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:06 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
` (12 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes v3:
none
Changes v2:
none
arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 +
arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1065 ++++++++++++++++++++++++++++
2 files changed, 1067 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul_pins.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 534f780..4b6bb18 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -37,6 +37,8 @@ enum {
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
#include "mx6sx_pins.h"
+#elif defined(CONFIG_MX6UL)
+#include "mx6ul_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6Q */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
new file mode 100644
index 0000000..c92b4f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
@@ -0,0 +1,1065 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX6UL_PINS_H__
+#define __ASM_ARCH_IMX6UL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+
+ MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0),
+ /*
+ * The TAMPER Pin can be used for GPIO, which depends on
+ * fusemap TAMPER_PIN_DISABLE[1:0] settings.
+ */
+ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
+ MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
+ MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
+
+ MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
+ MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
+ MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
+ MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
+ MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0),
+ MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0),
+ MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
+ MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
+ MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0),
+ MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0),
+ MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0),
+ MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0),
+ MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0),
+ MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0),
+ MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0),
+ MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0),
+ MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0),
+ MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0),
+
+ MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
+ MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
+ MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
+ MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0),
+ MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
+ MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0),
+
+ MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0),
+ MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0),
+ MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0),
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0),
+ MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0),
+ MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0),
+ MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0),
+ MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0),
+
+ MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0),
+ MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0),
+ MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0),
+ MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0),
+ MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0),
+ MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0),
+ MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0),
+ MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0),
+ MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0),
+
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0),
+ MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0),
+ MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0),
+ MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0),
+
+ MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0),
+ MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0),
+ MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0),
+ MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0),
+
+ MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0),
+ MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0),
+ MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0),
+ MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0),
+
+ MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0),
+
+ MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0),
+ MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0),
+ MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0),
+
+ MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0),
+ MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0),
+ MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0),
+ MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0),
+ MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0),
+
+ MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0),
+
+ MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0),
+ MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0),
+ MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0),
+ MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0),
+
+ MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0),
+ MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0),
+ MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0),
+
+ MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0),
+
+ MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0),
+ MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0),
+ MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0),
+
+ MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0),
+ MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0),
+ MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0),
+ MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0),
+
+ MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0),
+
+ MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0),
+ MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0),
+ MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0),
+ MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0),
+ MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0),
+
+ MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0),
+ MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0),
+ MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0),
+ MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0),
+ MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0),
+ MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0),
+
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0),
+
+ MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0),
+ MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0),
+ MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0),
+ MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0),
+ MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0),
+
+ MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0),
+ MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
+ MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
+ MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
+ MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0),
+
+ MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0),
+
+ MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0),
+ MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0),
+ MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0),
+
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0),
+ MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0),
+ MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
+ MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
+ MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0),
+ MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
+ MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
+ MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0),
+ MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0),
+ MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0),
+ MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0),
+ MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0),
+ MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0),
+ MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0),
+
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0),
+ MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0),
+ MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0),
+
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
+ MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0),
+ MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0),
+ MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0),
+ MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
+ MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0),
+ MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
+ MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0),
+ MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+
+ MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0),
+ MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
+ MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0),
+ MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0),
+ MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0),
+ MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0),
+ MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0),
+ MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
+ MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0),
+ MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0),
+ MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
+ MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0),
+ MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0),
+ MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
+ MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+
+ MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
+ MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+
+ MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
+ MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+
+ MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
+ MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+
+ MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
+ MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
+ MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
+ MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
+ MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
+ MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
+ MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
+ MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
+ MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
+ MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0),
+
+ MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
+ MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
+ MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0),
+
+ MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
+ MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
+ MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
+ MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
+ MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
+ MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
+ MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+
+ MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
+ MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+
+ MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
+ MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
+ MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+
+ MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
+ MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
+ MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+
+ MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0),
+ MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0),
+ MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0),
+
+ MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0),
+ MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0),
+
+ MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0),
+ MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0),
+ MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0),
+
+ MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0),
+ MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0),
+ MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0),
+ MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+
+ MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0),
+ MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0),
+ MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0),
+
+ MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0),
+ MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0),
+ MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0),
+
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0),
+ MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0),
+ MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0),
+ MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0),
+ MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0),
+ MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0),
+ MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0),
+ MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0),
+ MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0),
+ MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0),
+ MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0),
+ MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0),
+ MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0),
+ MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0),
+ MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0),
+
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0),
+ MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0),
+ MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0),
+ MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0),
+ MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0),
+ MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0),
+
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0),
+ MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0),
+ MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0),
+ MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0),
+ MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0),
+
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0),
+ MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0),
+ MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0),
+ MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0),
+
+ MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0),
+ MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0),
+ MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0),
+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0),
+ MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0),
+
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0),
+ MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0),
+ MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0),
+ MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0),
+
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0),
+ MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0),
+
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0),
+ MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0),
+ MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0),
+ MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0),
+ MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0),
+ MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0),
+
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0),
+ MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0),
+ MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0),
+
+ MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0),
+ MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0),
+ MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0),
+
+ MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0),
+ MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0),
+ MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0),
+ MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0),
+ MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0),
+ MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0),
+ MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0),
+ MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0),
+ MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0),
+ MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0),
+ MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0),
+ MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0),
+
+ MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0),
+ MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0),
+ MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0),
+ MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0),
+
+ MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0),
+ MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0),
+ MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0),
+ MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0),
+ MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0),
+ MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0),
+ MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0),
+ MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0),
+ MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0),
+ MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),
+ MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0),
+ MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0),
+ MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0),
+
+ MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0),
+ MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0),
+ MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0),
+ MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0),
+ MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0),
+
+ MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0),
+ MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0),
+ MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0),
+ MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0),
+ MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0),
+
+ MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0),
+ MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0),
+ MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0),
+ MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0),
+ MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0),
+ MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0),
+ MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0),
+ MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX6UL_PINS_H__ */
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers head file
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-07-20 18:39 ` Marek Vasut
2015-08-02 9:15 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Peng Fan
` (11 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
"AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
because we can use runtime check
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
Taking Marek's suggestion, fix the WDOG3_BASE_ADDRESS for assembler usage.
Changes v2:
split CONFIG_SYS_CACHELINE_SIZE part into another patch
arch/arm/include/asm/arch-mx6/imx-regs.h | 60 +++++++++++++++++++-------------
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 35a324c..d8b5d6f 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -19,7 +19,7 @@
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
-#elif CONFIG_MX6SX
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
@@ -28,10 +28,6 @@
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
-#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
-#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
-#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
-
#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
@@ -52,13 +48,13 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
@@ -87,15 +83,21 @@
#define AIPS1_ARB_END_ADDR 0x020FFFFF
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
-#ifdef CONFIG_MX6SX
+/* AIPS3 only on i.MX6SX */
#define AIPS3_ARB_BASE_ADDR 0x02200000
#define AIPS3_ARB_END_ADDR 0x022FFFFF
+#ifdef CONFIG_MX6SX
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
+#elif defined(CONFIG_MX6UL)
+#define WEIM_ARB_BASE_ADDR 0x50000000
+#define WEIM_ARB_END_ADDR 0x57FFFFFF
+#define QSPI0_AMBA_BASE 0x60000000
+#define QSPI0_AMBA_END 0x6FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
@@ -111,7 +113,7 @@
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
@@ -238,13 +240,16 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
-#ifdef CONFIG_MX6SL
+/* i.MX6SL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
-#elif CONFIG_MX6SX
-#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#ifdef CONFIG_MX6UL
+#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
-#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+/* i.MX6SX */
+#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
+/* i.MX6DQ/SDL */
+#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
@@ -257,22 +262,21 @@
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_MX6UL
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#elif defined(CONFIG_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
-#else
-#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
-#endif
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
+#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#endif
+#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
@@ -296,7 +300,6 @@
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
@@ -308,12 +311,17 @@
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
+#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
+
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
-#ifndef CONFIG_MX6SX
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
@@ -451,7 +459,7 @@ struct src {
struct iomuxc {
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
@@ -577,7 +585,7 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
@@ -661,7 +669,7 @@ struct fuse_bank1_regs {
u32 rsvd7[3];
};
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
@@ -674,7 +682,9 @@ struct fuse_bank4_regs {
u32 mac_addr2;
u32 rsvd4[7];
u32 gp1;
- u32 rsvd5[7];
+ u32 rsvd5[3];
+ u32 gp2;
+ u32 rsvd6[3];
};
#else
struct fuse_bank4_regs {
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (2 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:15 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support Peng Fan
` (10 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
new patch, splitted from patch 03/15.
arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index d8b5d6f..4d84a9b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,11 @@
#define ARCH_MXC
+#ifdef CONFIG_MX6UL
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#else
#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (3 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL Peng Fan
` (9 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Add i.MX6UL GPT timer support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
system counter patch is removed. Now, defaut use gpt.
arch/arm/imx-common/timer.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index c12556a..1a88ce6 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -45,7 +45,8 @@ static inline int gpt_has_clk_source_osc(void)
#if defined(CONFIG_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
(soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+ is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
+ is_cpu_type(MXC_CPU_MX6UL))
return 1;
return 0;
@@ -103,10 +104,11 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
- /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
+ /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) ||
- is_cpu_type(MXC_CPU_MX6SX)) {
+ is_cpu_type(MXC_CPU_MX6SX) ||
+ is_cpu_type(MXC_CPU_MX6UL)) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (4 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support Peng Fan
` (8 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
remove the system counter define, since default use GPT now.
include/configs/mx6_common.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 54ab890..ce43bd7 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -17,11 +17,11 @@
#ifndef __MX6_COMMON_H
#define __MX6_COMMON_H
+#ifndef CONFIG_MX6UL
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#define CONFIG_ARM_ERRATA_761320
-#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
@@ -29,6 +29,8 @@
#endif
#define CONFIG_MP
+#endif
+#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SYS_NO_FLASH
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (5 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF Peng Fan
` (7 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
fix possible assembler usage for MXC_CCM_CS2CDR_ENFC_CLKxx
Changes v2:
none
arch/arm/cpu/armv7/mx6/clock.c | 151 +++++++++++++++++++------------
arch/arm/include/asm/arch-mx6/crm_regs.h | 98 +++++++++++++-------
2 files changed, 159 insertions(+), 90 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 3e94472..9cf4eec 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -81,19 +81,32 @@ void enable_usboh3_clk(unsigned char enable)
#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
- u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+ u32 mask, *addr;
+
+ if (is_cpu_type(MXC_CPU_MX6UL)) {
+ mask = MXC_CCM_CCGR3_ENET_MASK;
+ addr = &imx_ccm->CCGR3;
+ } else {
+ mask = MXC_CCM_CCGR1_ENET_MASK;
+ addr = &imx_ccm->CCGR1;
+ }
if (enable)
- setbits_le32(&imx_ccm->CCGR1, mask);
+ setbits_le32(addr, mask);
else
- clrbits_le32(&imx_ccm->CCGR1, mask);
+ clrbits_le32(addr, mask);
}
#endif
#ifdef CONFIG_MXC_UART
void enable_uart_clk(unsigned char enable)
{
- u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+ u32 mask;
+
+ if (is_cpu_type(MXC_CPU_MX6UL))
+ mask = MXC_CCM_CCGR5_UART_MASK;
+ else
+ mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR5, mask);
@@ -141,7 +154,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
- if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
@@ -214,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
switch (pll) {
case PLL_BUS:
- if (pfd_num == 3) {
- /* No PFD3 on PPL2 */
- return 0;
+ if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (pfd_num == 3) {
+ /* No PFD3 on PPL2 */
+ return 0;
+ }
}
div = __raw_readl(&imx_ccm->analog_pfd_528);
freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
@@ -248,10 +263,12 @@ static u32 get_mcu_main_clk(void)
u32 get_periph_clk(void)
{
- u32 reg, freq = 0;
+ u32 reg, div = 0, freq = 0;
reg = __raw_readl(&imx_ccm->cbcdr);
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
reg = __raw_readl(&imx_ccm->cbcmr);
reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -291,7 +308,7 @@ u32 get_periph_clk(void)
}
}
- return freq;
+ return freq / (div + 1);
}
static u32 get_ipg_clk(void)
@@ -311,7 +328,7 @@ static u32 get_ipg_per_clk(void)
reg = __raw_readl(&imx_ccm->cscmr1);
if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp()) {
+ is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
@@ -328,7 +345,7 @@ static u32 get_uart_clk(void)
reg = __raw_readl(&imx_ccm->cscdr1);
if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp()) {
+ is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -347,7 +364,8 @@ static u32 get_cspi_clk(void)
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- if (is_mx6dqp()) {
+ if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+ is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -402,47 +420,60 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 freq, podf;
- podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
- >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
-
- switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ u32 freq, podf, per2_clk2_podf;
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6SL)) {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+ if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+ per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = MXC_HCLK;
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ } else {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ }
+ } else {
+ per2_clk2_podf = 0;
+ switch ((cbcmr &
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ break;
+ case 2:
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ break;
+ case 3:
+ /* static / 2 divider */
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ break;
+ }
+ }
+ return freq / (podf + 1) / (per2_clk2_podf + 1);
+ } else {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+ return get_periph_clk() / (podf + 1);
}
-
- return freq / (podf + 1);
-
}
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
- return get_periph_clk() / (mmdc_ch0_podf + 1);
-}
-#endif
-
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_FSL_QSPI
/* qspi_num can be from 0 - 1 */
void enable_qspi_clk(int qspi_num)
{
@@ -603,6 +634,7 @@ u32 imx_get_fecclk(void)
return mxc_get_clock(MXC_IPG_CLK);
}
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
static int enable_enet_pll(uint32_t en)
{
struct mxc_ccm_reg *const imx_ccm
@@ -627,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
writel(reg, &imx_ccm->analog_pll_enet);
return 0;
}
+#endif
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
@@ -637,18 +670,7 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
-#endif
-
-static void ungate_pcie_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* Enable PCIe clock. */
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
-
-#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
ungate_sata_clock();
@@ -664,6 +686,16 @@ void disable_sata_clock(void)
}
#endif
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Enable PCIe clock. */
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
int enable_pcie_clock(void)
{
struct anatop_regs *anatop_regs =
@@ -703,7 +735,7 @@ int enable_pcie_clock(void)
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
ungate_sata_clock();
#endif
ungate_pcie_clock();
@@ -711,6 +743,7 @@ int enable_pcie_clock(void)
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
BM_ANADIG_PLL_ENET_ENABLE_PCIE);
}
+#endif
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 7d9fe73..fe75da4 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -110,6 +110,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCR_RBC_EN (1 << 27)
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
+/* CCR_WB does not exist on i.MX6SX/UL */
#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
@@ -150,12 +151,11 @@ struct mxc_ccm_reg {
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
-#ifndef CONFIG_MX6SX
+/* MMDC_CH0 not exists on i.MX6SX */
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
-#endif
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
@@ -178,7 +178,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
#ifndef CONFIG_MX6SX
@@ -203,18 +203,19 @@ struct mxc_ccm_reg {
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
-#ifdef CONFIG_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
-#else
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
-#endif
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
+/* CSCMR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
+#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
@@ -225,10 +226,9 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
-#ifdef CONFIG_MX6SX
+/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
-#endif
/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
@@ -256,6 +256,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
#endif
+/* CSCDR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
+#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
+
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
@@ -290,7 +296,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
-#ifdef CONFIG_MX6SX
+/* QSPI2 on i.MX6SX */
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
@@ -300,7 +306,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
-#else
+
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
@@ -308,14 +314,26 @@ struct mxc_ccm_reg {
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
- (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
- (is_mx6dqp() ? 15 : 16)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
- (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
+ ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
-#endif
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
@@ -543,10 +561,9 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#ifndef CONFIG_MX6SX
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
-#endif
+/* CCGR1_ENET does not exist on i.MX6SX/UL */
+#define MXC_CCM_CCGR1_ENET_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
@@ -617,21 +634,21 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#endif
-#ifdef CONFIG_MX6SX
+/* Exist on i.MX6SX */
#define MXC_CCM_CCGR3_M4_OFFSET 2
#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
#define MXC_CCM_CCGR3_ENET_OFFSET 4
#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
-#else
+
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
-#endif
+
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
@@ -640,15 +657,22 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#ifdef CONFIG_MX6SX
+
+/* QSPI1 exists on i.MX6SX/UL */
#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
-#else
+
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
-#endif
+
+/* A7_CLKDIV/WDOG1 on i.MX6UL */
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
+
#define MXC_CCM_CCGR3_MLB_OFFSET 18
#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
@@ -661,8 +685,16 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+/* AXI on i.MX6UL */
+#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
+#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+
+/* GPIO4 on i.MX6UL */
+#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
+#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
+
#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
@@ -670,13 +702,11 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
-#ifdef CONFIG_MX6SX
+/* QSPI2 on i.MX6SX */
#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
-#else
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
-#endif
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
@@ -736,6 +766,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+/* GPMI/BCH on i.MX6UL */
+#define MXC_CCM_CCGR6_BCH_OFFSET 6
+#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
+#define MXC_CCM_CCGR6_GPMI_OFFSET 8
+#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
+
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (6 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings Peng Fan
` (6 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
refine commit msg.
arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 10908c4..fceba27 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -25,6 +25,10 @@ config MX6SL
config MX6SX
bool
+config MX6UL
+ select SYS_L2CACHE_OFF
+ bool
+
choice
prompt "MX6 board select"
optional
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (7 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL Peng Fan
` (5 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
---
Changes v3:
none
Changes v2:
runtime check for wdog part.
arch/arm/cpu/armv7/mx6/soc.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e80c09c..033f9de 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -316,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
-
-#ifdef CONFIG_MX6SX
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
- writew(enable, &wdog3->wmcr);
-#endif
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+ writew(enable, &wdog3->wmcr);
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
@@ -530,7 +529,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (8 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support Peng Fan
` (4 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
none
arch/arm/include/asm/imx-common/iomux-v3.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 5cde90f..42098a3 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -98,7 +98,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_ODE (1 << 11)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#define PAD_CTL_SPEED_LOW (0 << 6)
+#else
#define PAD_CTL_SPEED_LOW (1 << 6)
+#endif
#define PAD_CTL_SPEED_MED (2 << 6)
#define PAD_CTL_SPEED_HIGH (3 << 6)
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (9 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL Peng Fan
` (3 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
none
drivers/gpio/mxc_gpio.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 2012f99..57a650f 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -45,11 +45,15 @@ static unsigned long gpio_ports[] = {
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
[4] = GPIO5_BASE_ADDR,
+#ifndef CONFIG_MX6UL
[5] = GPIO6_BASE_ADDR,
#endif
+#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#ifndef CONFIG_MX6UL
[6] = GPIO7_BASE_ADDR,
#endif
+#endif
};
static int mxc_gpio_direction(unsigned int gpio,
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (10 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file Peng Fan
` (2 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
refine commit msg.
include/configs/mx6_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index ce43bd7..ef4cb68 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -54,7 +54,7 @@
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (11 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
new patch
arch/arm/cpu/armv7/mx6/ddr.c | 61 ++++++++++++++++++++++++++-----
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 45 +++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 45 +++++++++++++++++++++++
3 files changed, 141 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 86c8354..b808627 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
}
#endif
+#ifdef CONFIG_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+ const struct mx6ul_iomux_ddr_regs *ddr,
+ const struct mx6ul_iomux_grp_regs *grp)
+{
+ struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#ifdef CONFIG_MX6SX
-#define MMDC1(entry, value) do {} while (0)
-#else
-#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
-#endif
+#define MMDC1(entry, value) do { \
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
+ mmdc1->entry = value; \
+ } while (0)
+
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
-#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
-#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-#ifndef CONFIG_MX6SX
- mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-#endif
+ if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+ mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index c49aa62..7bfbdc3 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -16,7 +16,11 @@
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
+#ifdef CONFIG_MX6UL
+#include "mx6ul-ddr.h"
+#else
#error "Please select cpu"
+#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
@@ -62,6 +66,44 @@ struct mmdc_p_regs {
u32 mpmur0;
};
+#define MX6UL_IOM_DDR_BASE 0x020e0200
+struct mx6ul_iomux_ddr_regs {
+ u32 res1[17];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_ras;
+ u32 dram_cas;
+ u32 dram_cs0;
+ u32 dram_cs1;
+ u32 dram_sdwe_b;
+ u32 dram_odt0;
+ u32 dram_odt1;
+ u32 dram_sdba0;
+ u32 dram_sdba1;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_reset;
+};
+
+#define MX6UL_IOM_GRP_BASE 0x020e0400
+struct mx6ul_iomux_grp_regs {
+ u32 res1[36];
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_b0ds;
+ u32 grp_ddrpk;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddrhys;
+ u32 grp_ddrpke;
+ u32 grp_ddrmode;
+ u32 grp_ddr_type;
+};
+
#define MX6SX_IOM_DDR_BASE 0x020e0200
struct mx6sx_iomux_ddr_regs {
u32 res1[59];
@@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
void mx6sx_dram_iocfg(unsigned width,
const struct mx6sx_iomux_ddr_regs *,
const struct mx6sx_iomux_grp_regs *);
+void mx6ul_dram_iocfg(unsigned width,
+ const struct mx6ul_iomux_ddr_regs *,
+ const struct mx6ul_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
new file mode 100644
index 0000000..ed11c4b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6UL_DDR_H__
+#define __ASM_ARCH_MX6UL_DDR_H__
+
+#ifndef CONFIG_MX6UL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0 0x020e0244
+#define MX6_IOM_DRAM_DQM1 0x020e0248
+
+#define MX6_IOM_DRAM_RAS 0x020e024c
+#define MX6_IOM_DRAM_CAS 0x020e0250
+#define MX6_IOM_DRAM_CS0 0x020e0254
+#define MX6_IOM_DRAM_CS1 0x020e0258
+#define MX6_IOM_DRAM_SDWE_B 0x020e025c
+#define MX6_IOM_DRAM_SDODT0 0x020e0260
+#define MX6_IOM_DRAM_SDODT1 0x020e0264
+#define MX6_IOM_DRAM_SDBA0 0x020e0268
+#define MX6_IOM_DRAM_SDBA1 0x020e026c
+#define MX6_IOM_DRAM_SDBA2 0x020e0270
+#define MX6_IOM_DRAM_SDCKE0 0x020e0274
+#define MX6_IOM_DRAM_SDCKE1 0x020e0278
+#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
+#define MX6_IOM_DRAM_SDQS0 0x020e0280
+#define MX6_IOM_DRAM_SDQS1 0x020e0284
+#define MX6_IOM_DRAM_RESET 0x020e0288
+
+#define MX6_IOM_GRP_ADDDS 0x020e0490
+#define MX6_IOM_DDRMODE_CTL 0x020e0494
+#define MX6_IOM_GRP_B0DS 0x020e0498
+#define MX6_IOM_GRP_DDRPK 0x020e049c
+#define MX6_IOM_GRP_CTLDS 0x020e04a0
+#define MX6_IOM_GRP_B1DS 0x020e04a4
+#define MX6_IOM_GRP_DDRHYS 0x020e04a8
+#define MX6_IOM_GRP_DDRPKE 0x020e04ac
+#define MX6_IOM_GRP_DDRMODE 0x020e04b0
+#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
+
+#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (12 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
14 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
None
Changes v2:
new patch
include/configs/imx6_spl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 21c5dce..0a585b7 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -61,7 +61,7 @@
#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
` (13 preceding siblings ...)
2015-07-20 11:28 ` [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support Peng Fan
@ 2015-07-20 11:28 ` Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-08-10 16:22 ` Fabio Estevam
14 siblings, 2 replies; 36+ messages in thread
From: Peng Fan @ 2015-07-20 11:28 UTC (permalink / raw)
To: u-boot
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
supports sd for usdhc2, but can do hardware rework to make usdhc2 support
emmc.
Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
Changes v3:
none
Changes v2:
Add SPL support
More commit msg for CONFIG_MX6UL_14X14_EVK_EMMC_REWORK.
arch/arm/Kconfig | 8 +
board/freescale/mx6ul_14x14_evk/Kconfig | 15 +
board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 +
board/freescale/mx6ul_14x14_evk/Makefile | 6 +
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++++++++++++
configs/mx6ul_14x14_evk_defconfig | 4 +
include/configs/mx6ul_14x14_evk.h | 227 ++++++++
7 files changed, 902 insertions(+)
create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig
create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS
create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile
create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
create mode 100644 configs/mx6ul_14x14_evk_defconfig
create mode 100644 include/configs/mx6ul_14x14_evk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9908b43..14a622e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -575,6 +575,13 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
+config TARGET_MX6UL_14X14_EVK
+ bool "Support mx6ul_14x14_evk"
+ select CPU_V7
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_GW_VENTANA
bool "Support gw_ventana"
select CPU_V7
@@ -920,6 +927,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
new file mode 100644
index 0000000..393aca6
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6UL_14X14_EVK
+
+config SYS_BOARD
+ default "mx6ul_14x14_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6ul_14x14_evk"
+
+endif
diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
new file mode 100644
index 0000000..611feca
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6ULEVK BOARD
+M: Peng Fan <Peng.Fan@freescale.com>
+S: Maintained
+F: board/freescale/mx6ul_14x14_evk/
+F: include/configs/mx6ul_14x14_evk.h
+F: configs/mx6ul_14x14_evk_defconfig
diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile
new file mode 100644
index 0000000..61f6778
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6ul_14x14_evk.o
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
new file mode 100644
index 0000000..8f712cb
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -0,0 +1,636 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define IOX_SDI IMX_GPIO_NR(5, 10)
+#define IOX_STCP IMX_GPIO_NR(5, 7)
+#define IOX_SHCP IMX_GPIO_NR(5, 11)
+#define IOX_OE IMX_GPIO_NR(5, 18)
+
+static iomux_v3_cfg_t const iox_pads[] = {
+ /* IOX_SDI */
+ MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_SHCP */
+ MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_STCP */
+ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_nOE */
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * HDMI_nRST --> Q0
+ * ENET1_nRST --> Q1
+ * ENET2_nRST --> Q2
+ * CAN1_2_STBY --> Q3
+ * BT_nPWD --> Q4
+ * CSI_RST --> Q5
+ * CSI_PWDN --> Q6
+ * LCD_nPWREN --> Q7
+ */
+enum qn {
+ HDMI_NRST,
+ ENET1_NRST,
+ ENET2_NRST,
+ CAN1_2_STBY,
+ BT_NPWD,
+ CSI_RST,
+ CSI_PWDN,
+ LCD_NPWREN,
+};
+
+enum qn_func {
+ qn_reset,
+ qn_enable,
+ qn_disable,
+};
+
+enum qn_level {
+ qn_low = 0,
+ qn_high = 1,
+};
+
+static enum qn_level seq[3][2] = {
+ {0, 1}, {1, 1}, {0, 0}
+};
+
+static enum qn_func qn_output[8] = {
+ qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
+ qn_disable, qn_enable
+};
+
+static void iox74lv_init(void)
+{
+ int i;
+
+ gpio_direction_output(IOX_OE, 0);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ gpio_direction_output(IOX_OE, 1);
+};
+
+void iox74lv_set(int index)
+{
+ int i;
+
+ gpio_direction_output(IOX_OE, 0);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+
+ if (i == index)
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ else
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ gpio_direction_output(IOX_OE, 1);
+};
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
+ .gp = IMX_GPIO_NR(1, 28),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
+ .gp = IMX_GPIO_NR(1, 29),
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* VSELECT */
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_B */
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * mx6ul_14x14_evk board default supports sd card. If want to use
+ * EMMC, need to do board rework for sd2.
+ * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
+ * emmc, need to define this macro.
+ */
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*
+ * RST_B
+ */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
+ /*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+ MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
+ MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+ /* Set the clock */
+ enable_qspi_clk(0);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ {USDHC2_BASE_ADDR, 0, 8},
+#else
+ {USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ ret = 1;
+#else
+ imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
+ ARRAY_SIZE(usdhc2_cd_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+
+ /*
+ * Since it is the DAT3 pin, this pin is pulled to
+ * low voltage if no card
+ */
+ ret = gpio_get_value(USDHC2_CD_GPIO);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
+ ARRAY_SIZE(usdhc2_dat3_pads));
+#endif
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
+ ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+#else
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* At default the 3v3 enables the MIC2026 for VBUS power */
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
+
+ iox74lv_init();
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6UL 14x14 EVK\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00070007,
+ .p0_mpdgctrl0 = 0x41490145,
+ .p0_mprddlctl = 0x40404546,
+ .p0_mpwrdlctl = 0x4040524D,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
new file mode 100644
index 0000000..b6eefaf
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SPL=y
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
new file mode 100644
index 0000000..436b022
--- /dev/null
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MX6UL_14X14_EVK_CONFIG_H
+#define __MX6UL_14X14_EVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+/* SPL options */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_MX6
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#endif
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6ul-14x14-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT "=> "
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_BMODE
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM 1
+#define FSL_QSPI_FLASH_SIZE SZ_32M
+#endif
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX6_THERMAL
+
+#endif
--
1.8.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers head file
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
@ 2015-07-20 18:39 ` Marek Vasut
2015-08-02 9:07 ` Stefano Babic
2015-08-02 9:15 ` Stefano Babic
1 sibling, 1 reply; 36+ messages in thread
From: Marek Vasut @ 2015-07-20 18:39 UTC (permalink / raw)
To: u-boot
On Monday, July 20, 2015 at 01:28:23 PM, Peng Fan wrote:
> 1. Update imx register base address for i.MX6UL.
> 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
> 3. Remove #ifdef for register addresses that equal to
> "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
> 4. According fuse map, complete fuse_bank4_regs.
> 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef
> CONFIG_MX6SX, because we can use runtime check
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
[...]
> @@ -296,7 +300,6 @@
> #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
> #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
> #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
> -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
> #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
> #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
> @@ -308,12 +311,17 @@
> #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
> #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
> #endif
> +#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> +
> +/* only for i.MX6SX/UL */
> +#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
> + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
Nitpick -- this should probably be protected by #ifndef __ASSELMBLY__ .
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
@ 2015-08-02 9:05 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:05 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
> DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
> is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
> was not occupied.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
>
> Changes v3:
> None
>
> Changes v2:
> Refine commit msg.
>
> arch/arm/imx-common/cpu.c | 2 ++
> arch/arm/include/asm/arch-imx/cpu.h | 3 ++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 096d22e..e27546c 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -138,6 +138,8 @@ const char *get_imx_type(u32 imxtype)
> return "6SL"; /* Solo-Lite version of the mx6 */
> case MXC_CPU_MX6SX:
> return "6SX"; /* SoloX version of the mx6 */
> + case MXC_CPU_MX6UL:
> + return "6UL"; /* Ultra-Lite version of the mx6 */
> case MXC_CPU_MX51:
> return "51";
> case MXC_CPU_MX53:
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
> index 99e0e32..c7f9fff 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -10,8 +10,9 @@
> #define MXC_CPU_MX6DL 0x61
> #define MXC_CPU_MX6SX 0x62
> #define MXC_CPU_MX6Q 0x63
> -#define MXC_CPU_MX6D 0x64
> +#define MXC_CPU_MX6UL 0x64
> #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
> +#define MXC_CPU_MX6D 0x67
> #define MXC_CPU_MX6DP 0x68
> #define MXC_CPU_MX6QP 0x69
>
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file
2015-07-20 11:28 ` [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file Peng Fan
@ 2015-08-02 9:06 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:06 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers head file
2015-07-20 18:39 ` Marek Vasut
@ 2015-08-02 9:07 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:07 UTC (permalink / raw)
To: u-boot
On 20/07/2015 20:39, Marek Vasut wrote:
> On Monday, July 20, 2015 at 01:28:23 PM, Peng Fan wrote:
>> 1. Update imx register base address for i.MX6UL.
>> 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
>> 3. Remove #ifdef for register addresses that equal to
>> "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
>> 4. According fuse map, complete fuse_bank4_regs.
>> 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef
>> CONFIG_MX6SX, because we can use runtime check
>>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>
> [...]
>
>> @@ -296,7 +300,6 @@
>> #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
>> #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
>> #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
>> -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
>> #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
>> #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
>> #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
>> @@ -308,12 +311,17 @@
>> #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
>> #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
>> #endif
>> +#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
>> +
>> +/* only for i.MX6SX/UL */
>> +#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
>> + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
>
> Nitpick -- this should probably be protected by #ifndef __ASSELMBLY__ .
>
Anyway, I decided to apply it - it could be easy fixed with a follow up
patch if this case arises.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers head file
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
2015-07-20 18:39 ` Marek Vasut
@ 2015-08-02 9:15 ` Stefano Babic
1 sibling, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:15 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> 1. Update imx register base address for i.MX6UL.
> 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
> 3. Remove #ifdef for register addresses that equal to
> "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
> 4. According fuse map, complete fuse_bank4_regs.
> 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
> because we can use runtime check
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> Taking Marek's suggestion, fix the WDOG3_BASE_ADDRESS for assembler usage.
>
> Changes v2:
> split CONFIG_SYS_CACHELINE_SIZE part into another patch
>
> arch/arm/include/asm/arch-mx6/imx-regs.h | 60 +++++++++++++++++++-------------
> 1 file changed, 35 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 35a324c..d8b5d6f 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -19,7 +19,7 @@
> #define GPU_2D_ARB_END_ADDR 0x02203FFF
> #define OPENVG_ARB_BASE_ADDR 0x02204000
> #define OPENVG_ARB_END_ADDR 0x02207FFF
> -#elif CONFIG_MX6SX
> +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define CAAM_ARB_BASE_ADDR 0x00100000
> #define CAAM_ARB_END_ADDR 0x00107FFF
> #define GPU_ARB_BASE_ADDR 0x01800000
> @@ -28,10 +28,6 @@
> #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
> #define M4_BOOTROM_BASE_ADDR 0x007F8000
>
> -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
> -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
> -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
> -
> #else
> #define CAAM_ARB_BASE_ADDR 0x00100000
> #define CAAM_ARB_END_ADDR 0x00103FFF
> @@ -52,13 +48,13 @@
> #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
>
> /* GPV - PL301 configuration ports */
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define GPV2_BASE_ADDR 0x00D00000
> #else
> #define GPV2_BASE_ADDR 0x00200000
> #endif
>
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define GPV3_BASE_ADDR 0x00E00000
> #define GPV4_BASE_ADDR 0x00F00000
> #define GPV5_BASE_ADDR 0x01000000
> @@ -87,15 +83,21 @@
> #define AIPS1_ARB_END_ADDR 0x020FFFFF
> #define AIPS2_ARB_BASE_ADDR 0x02100000
> #define AIPS2_ARB_END_ADDR 0x021FFFFF
> -#ifdef CONFIG_MX6SX
> +/* AIPS3 only on i.MX6SX */
> #define AIPS3_ARB_BASE_ADDR 0x02200000
> #define AIPS3_ARB_END_ADDR 0x022FFFFF
> +#ifdef CONFIG_MX6SX
> #define WEIM_ARB_BASE_ADDR 0x50000000
> #define WEIM_ARB_END_ADDR 0x57FFFFFF
> #define QSPI0_AMBA_BASE 0x60000000
> #define QSPI0_AMBA_END 0x6FFFFFFF
> #define QSPI1_AMBA_BASE 0x70000000
> #define QSPI1_AMBA_END 0x7FFFFFFF
> +#elif defined(CONFIG_MX6UL)
> +#define WEIM_ARB_BASE_ADDR 0x50000000
> +#define WEIM_ARB_END_ADDR 0x57FFFFFF
> +#define QSPI0_AMBA_BASE 0x60000000
> +#define QSPI0_AMBA_END 0x6FFFFFFF
> #else
> #define SATA_ARB_BASE_ADDR 0x02200000
> #define SATA_ARB_END_ADDR 0x02203FFF
> @@ -111,7 +113,7 @@
> #define WEIM_ARB_END_ADDR 0x0FFFFFFF
> #endif
>
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define MMDC0_ARB_BASE_ADDR 0x80000000
> #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
> #define MMDC1_ARB_BASE_ADDR 0xC0000000
> @@ -238,13 +240,16 @@
> #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
> #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
> #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
> -#ifdef CONFIG_MX6SL
> +/* i.MX6SL */
> #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> -#elif CONFIG_MX6SX
> -#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> +#ifdef CONFIG_MX6UL
> +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
> #else
> -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> +/* i.MX6SX */
> +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> #endif
> +/* i.MX6DQ/SDL */
> +#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
>
> #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
> #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
> @@ -257,22 +262,21 @@
> #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
> #endif
> #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
> -#ifdef CONFIG_MX6SX
> +#ifdef CONFIG_MX6UL
> +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> +#elif defined(CONFIG_MX6SX)
> #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> -#else
> -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> -#endif
> #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> -#ifdef CONFIG_MX6SX
> #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #else
> +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #endif
> +#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
> #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
> #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
> @@ -296,7 +300,6 @@
> #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
> #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
> #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
> -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
> #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
> #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
> @@ -308,12 +311,17 @@
> #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
> #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
> #endif
> +#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> +
> +/* only for i.MX6SX/UL */
> +#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
> + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
>
> #define CHIP_REV_1_0 0x10
> #define CHIP_REV_1_2 0x12
> #define CHIP_REV_1_5 0x15
> #define CHIP_REV_2_0 0x20
> -#ifndef CONFIG_MX6SX
> +#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define IRAM_SIZE 0x00040000
> #else
> #define IRAM_SIZE 0x00020000
> @@ -451,7 +459,7 @@ struct src {
>
>
> struct iomuxc {
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> u8 reserved[0x4000];
> #endif
> u32 gpr[14];
> @@ -577,7 +585,7 @@ struct cspi_regs {
> #define MXC_CSPICON_POL 4 /* SCLK polarity */
> #define MXC_CSPICON_SSPOL 12 /* SS polarity */
> #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
> -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
> +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
> #define MXC_SPI_BASE_ADDRESSES \
> ECSPI1_BASE_ADDR, \
> ECSPI2_BASE_ADDR, \
> @@ -661,7 +669,7 @@ struct fuse_bank1_regs {
> u32 rsvd7[3];
> };
>
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
> @@ -674,7 +682,9 @@ struct fuse_bank4_regs {
> u32 mac_addr2;
> u32 rsvd4[7];
> u32 gp1;
> - u32 rsvd5[7];
> + u32 rsvd5[3];
> + u32 gp2;
> + u32 rsvd6[3];
> };
> #else
> struct fuse_bank4_regs {
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
2015-07-20 11:28 ` [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Peng Fan
@ 2015-08-02 9:15 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:15 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> Since i.MX6UL's cache line size is 64bytes, need to
> define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
> Changes v2:
> new patch, splitted from patch 03/15.
>
> arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index d8b5d6f..4d84a9b 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,11 @@
>
> #define ARCH_MXC
>
> +#ifdef CONFIG_MX6UL
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +#else
> #define CONFIG_SYS_CACHELINE_SIZE 32
> +#endif
>
> #define ROMCP_ARB_BASE_ADDR 0x00000000
> #define ROMCP_ARB_END_ADDR 0x000FFFFF
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support Peng Fan
@ 2015-08-02 9:16 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:16 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> Add i.MX6UL GPT timer support.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> system counter patch is removed. Now, defaut use gpt.
>
> arch/arm/imx-common/timer.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
> index c12556a..1a88ce6 100644
> --- a/arch/arm/imx-common/timer.c
> +++ b/arch/arm/imx-common/timer.c
> @@ -45,7 +45,8 @@ static inline int gpt_has_clk_source_osc(void)
> #if defined(CONFIG_MX6)
> if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
> (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
> - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
> + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
> + is_cpu_type(MXC_CPU_MX6UL))
> return 1;
>
> return 0;
> @@ -103,10 +104,11 @@ int timer_init(void)
> if (gpt_has_clk_source_osc()) {
> i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
>
> - /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
> + /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
> if (is_cpu_type(MXC_CPU_MX6DL) ||
> is_cpu_type(MXC_CPU_MX6SOLO) ||
> - is_cpu_type(MXC_CPU_MX6SX)) {
> + is_cpu_type(MXC_CPU_MX6SX) ||
> + is_cpu_type(MXC_CPU_MX6UL)) {
> i |= GPTCR_24MEN;
>
> /* Produce 3Mhz clock */
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL
2015-07-20 11:28 ` [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL Peng Fan
@ 2015-08-02 9:16 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:16 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> Since i.MX6UL use A7 core, but not A9 core, we do not need
> the erratas for i.MX6UL.
>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> remove the system counter define, since default use GPT now.
>
> include/configs/mx6_common.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
> index 54ab890..ce43bd7 100644
> --- a/include/configs/mx6_common.h
> +++ b/include/configs/mx6_common.h
> @@ -17,11 +17,11 @@
> #ifndef __MX6_COMMON_H
> #define __MX6_COMMON_H
>
> +#ifndef CONFIG_MX6UL
> #define CONFIG_ARM_ERRATA_743622
> #define CONFIG_ARM_ERRATA_751472
> #define CONFIG_ARM_ERRATA_794072
> #define CONFIG_ARM_ERRATA_761320
> -#define CONFIG_BOARD_POSTCLK_INIT
>
> #ifndef CONFIG_SYS_L2CACHE_OFF
> #define CONFIG_SYS_L2_PL310
> @@ -29,6 +29,8 @@
> #endif
>
> #define CONFIG_MP
> +#endif
> +#define CONFIG_BOARD_POSTCLK_INIT
> #define CONFIG_MXC_GPT_HCLK
>
> #define CONFIG_SYS_NO_FLASH
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> 1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
> 2. Correct get_periph_clk, it should account for
> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
> 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
> but not use 'ifdef'.
> 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
> 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
> sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
> || defined....", only need one CONFIG_PCIE_IMX in header file.
>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> fix possible assembler usage for MXC_CCM_CS2CDR_ENFC_CLKxx
>
> Changes v2:
> none
>
> arch/arm/cpu/armv7/mx6/clock.c | 151 +++++++++++++++++++------------
> arch/arm/include/asm/arch-mx6/crm_regs.h | 98 +++++++++++++-------
> 2 files changed, 159 insertions(+), 90 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index 3e94472..9cf4eec 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -81,19 +81,32 @@ void enable_usboh3_clk(unsigned char enable)
> #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
> void enable_enet_clk(unsigned char enable)
> {
> - u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
> + u32 mask, *addr;
> +
> + if (is_cpu_type(MXC_CPU_MX6UL)) {
> + mask = MXC_CCM_CCGR3_ENET_MASK;
> + addr = &imx_ccm->CCGR3;
> + } else {
> + mask = MXC_CCM_CCGR1_ENET_MASK;
> + addr = &imx_ccm->CCGR1;
> + }
>
> if (enable)
> - setbits_le32(&imx_ccm->CCGR1, mask);
> + setbits_le32(addr, mask);
> else
> - clrbits_le32(&imx_ccm->CCGR1, mask);
> + clrbits_le32(addr, mask);
> }
> #endif
>
> #ifdef CONFIG_MXC_UART
> void enable_uart_clk(unsigned char enable)
> {
> - u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
> + u32 mask;
> +
> + if (is_cpu_type(MXC_CPU_MX6UL))
> + mask = MXC_CCM_CCGR5_UART_MASK;
> + else
> + mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
>
> if (enable)
> setbits_le32(&imx_ccm->CCGR5, mask);
> @@ -141,7 +154,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
> reg &= ~mask;
> __raw_writel(reg, &imx_ccm->CCGR2);
> } else {
> - if (is_cpu_type(MXC_CPU_MX6SX)) {
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
> mask = MXC_CCM_CCGR6_I2C4_MASK;
> addr = &imx_ccm->CCGR6;
> } else {
> @@ -214,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
>
> switch (pll) {
> case PLL_BUS:
> - if (pfd_num == 3) {
> - /* No PFD3 on PPL2 */
> - return 0;
> + if (!is_cpu_type(MXC_CPU_MX6UL)) {
> + if (pfd_num == 3) {
> + /* No PFD3 on PPL2 */
> + return 0;
> + }
> }
> div = __raw_readl(&imx_ccm->analog_pfd_528);
> freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
> @@ -248,10 +263,12 @@ static u32 get_mcu_main_clk(void)
>
> u32 get_periph_clk(void)
> {
> - u32 reg, freq = 0;
> + u32 reg, div = 0, freq = 0;
>
> reg = __raw_readl(&imx_ccm->cbcdr);
> if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> + div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
> + MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
> reg = __raw_readl(&imx_ccm->cbcmr);
> reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
> reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
> @@ -291,7 +308,7 @@ u32 get_periph_clk(void)
> }
> }
>
> - return freq;
> + return freq / (div + 1);
> }
>
> static u32 get_ipg_clk(void)
> @@ -311,7 +328,7 @@ static u32 get_ipg_per_clk(void)
>
> reg = __raw_readl(&imx_ccm->cscmr1);
> if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
> - is_mx6dqp()) {
> + is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
> if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
> return MXC_HCLK; /* OSC 24Mhz */
> }
> @@ -328,7 +345,7 @@ static u32 get_uart_clk(void)
> reg = __raw_readl(&imx_ccm->cscdr1);
>
> if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
> - is_mx6dqp()) {
> + is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
> if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
> freq = MXC_HCLK;
> }
> @@ -347,7 +364,8 @@ static u32 get_cspi_clk(void)
> cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
>
> - if (is_mx6dqp()) {
> + if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
> + is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
> if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
> return MXC_HCLK / (cspi_podf + 1);
> }
> @@ -402,47 +420,60 @@ static u32 get_emi_slow_clk(void)
> return root_freq / (emi_slow_podf + 1);
> }
>
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> static u32 get_mmdc_ch0_clk(void)
> {
> u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
> u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
> - u32 freq, podf;
>
> - podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
> - >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
> -
> - switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
> - MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
> - case 0:
> - freq = decode_pll(PLL_BUS, MXC_HCLK);
> - break;
> - case 1:
> - freq = mxc_get_pll_pfd(PLL_BUS, 2);
> - break;
> - case 2:
> - freq = mxc_get_pll_pfd(PLL_BUS, 0);
> - break;
> - case 3:
> - /* static / 2 divider */
> - freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
> + u32 freq, podf, per2_clk2_podf;
> +
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
> + is_cpu_type(MXC_CPU_MX6SL)) {
> + podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
> + MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
> + if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
> + per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
> + MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
> + if (is_cpu_type(MXC_CPU_MX6SL)) {
> + if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
> + freq = MXC_HCLK;
> + else
> + freq = decode_pll(PLL_USBOTG, MXC_HCLK);
> + } else {
> + if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
> + freq = decode_pll(PLL_BUS, MXC_HCLK);
> + else
> + freq = decode_pll(PLL_USBOTG, MXC_HCLK);
> + }
> + } else {
> + per2_clk2_podf = 0;
> + switch ((cbcmr &
> + MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
> + MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
> + case 0:
> + freq = decode_pll(PLL_BUS, MXC_HCLK);
> + break;
> + case 1:
> + freq = mxc_get_pll_pfd(PLL_BUS, 2);
> + break;
> + case 2:
> + freq = mxc_get_pll_pfd(PLL_BUS, 0);
> + break;
> + case 3:
> + /* static / 2 divider */
> + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
> + break;
> + }
> + }
> + return freq / (podf + 1) / (per2_clk2_podf + 1);
> + } else {
> + podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
> + MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
> + return get_periph_clk() / (podf + 1);
> }
> -
> - return freq / (podf + 1);
> -
> }
> -#else
> -static u32 get_mmdc_ch0_clk(void)
> -{
> - u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
> - u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
> - MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
>
> - return get_periph_clk() / (mmdc_ch0_podf + 1);
> -}
> -#endif
> -
> -#ifdef CONFIG_MX6SX
> +#ifdef CONFIG_FSL_QSPI
> /* qspi_num can be from 0 - 1 */
> void enable_qspi_clk(int qspi_num)
> {
> @@ -603,6 +634,7 @@ u32 imx_get_fecclk(void)
> return mxc_get_clock(MXC_IPG_CLK);
> }
>
> +#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
> static int enable_enet_pll(uint32_t en)
> {
> struct mxc_ccm_reg *const imx_ccm
> @@ -627,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
> writel(reg, &imx_ccm->analog_pll_enet);
> return 0;
> }
> +#endif
>
> -#ifndef CONFIG_MX6SX
> +#ifdef CONFIG_CMD_SATA
> static void ungate_sata_clock(void)
> {
> struct mxc_ccm_reg *const imx_ccm =
> @@ -637,18 +670,7 @@ static void ungate_sata_clock(void)
> /* Enable SATA clock. */
> setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
> }
> -#endif
> -
> -static void ungate_pcie_clock(void)
> -{
> - struct mxc_ccm_reg *const imx_ccm =
> - (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>
> - /* Enable PCIe clock. */
> - setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
> -}
> -
> -#ifndef CONFIG_MX6SX
> int enable_sata_clock(void)
> {
> ungate_sata_clock();
> @@ -664,6 +686,16 @@ void disable_sata_clock(void)
> }
> #endif
>
> +#ifdef CONFIG_PCIE_IMX
> +static void ungate_pcie_clock(void)
> +{
> + struct mxc_ccm_reg *const imx_ccm =
> + (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + /* Enable PCIe clock. */
> + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
> +}
> +
> int enable_pcie_clock(void)
> {
> struct anatop_regs *anatop_regs =
> @@ -703,7 +735,7 @@ int enable_pcie_clock(void)
> clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
>
> /* Party time! Ungate the clock to the PCIe. */
> -#ifndef CONFIG_MX6SX
> +#ifdef CONFIG_CMD_SATA
> ungate_sata_clock();
> #endif
> ungate_pcie_clock();
> @@ -711,6 +743,7 @@ int enable_pcie_clock(void)
> return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
> BM_ANADIG_PLL_ENET_ENABLE_PCIE);
> }
> +#endif
>
> #ifdef CONFIG_SECURE_BOOT
> void hab_caam_clock_enable(unsigned char enable)
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 7d9fe73..fe75da4 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -110,6 +110,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCR_RBC_EN (1 << 27)
> #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
> #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
> +/* CCR_WB does not exist on i.MX6SX/UL */
> #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
> #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
> #define MXC_CCM_CCR_COSC_EN (1 << 12)
> @@ -150,12 +151,11 @@ struct mxc_ccm_reg {
> /* Define the bits in register CBCDR */
> #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
> #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
> -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
> +#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
> #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
> -#ifndef CONFIG_MX6SX
> +/* MMDC_CH0 not exists on i.MX6SX */
> #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
> #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
> -#endif
> #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
> #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
> #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
> @@ -178,7 +178,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
> #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
> #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
> -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
> +#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
> #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
> #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
> #ifndef CONFIG_MX6SX
> @@ -203,18 +203,19 @@ struct mxc_ccm_reg {
> /* Define the bits in register CSCMR1 */
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
> -#ifdef CONFIG_MX6SX
> +/* QSPI1 exist on i.MX6SX/UL */
> #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
> #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
> -#else
> #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
> #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
> -#endif
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
> /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
> #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
> #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
> +/* CSCMR1_GPMI/BCH exist on i.MX6UL */
> +#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
> +#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
> #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
> #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
> #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
> @@ -225,10 +226,9 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
> #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
> #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
> -#ifdef CONFIG_MX6SX
> +/* QSPI1 exist on i.MX6SX/UL */
> #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
> #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
> -#endif
> /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
> #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
> #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
> @@ -256,6 +256,12 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
> #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
> #endif
> +/* CSCDR1_GPMI/BCH exist on i.MX6UL */
> +#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
> +#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
> +#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
> +#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
> +
> #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
> #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
> #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
> @@ -290,7 +296,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
>
> /* Define the bits in register CS2CDR */
> -#ifdef CONFIG_MX6SX
> +/* QSPI2 on i.MX6SX */
> #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
> #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
> #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
> @@ -300,7 +306,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
> #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
> #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
> -#else
> +
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
> @@ -308,14 +314,26 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
>
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
> - (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
> - (is_mx6dqp() ? 15 : 16)
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
> - (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
> +
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
> + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
> + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
> + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
>
> -#endif
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
> #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
> @@ -543,10 +561,9 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
> #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
> #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
> -#ifndef CONFIG_MX6SX
> -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
> -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
> -#endif
> +/* CCGR1_ENET does not exist on i.MX6SX/UL */
> +#define MXC_CCM_CCGR1_ENET_OFFSET 10
> +#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
> #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
> #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
> #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
> @@ -617,21 +634,21 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
> #endif
>
> -#ifdef CONFIG_MX6SX
> +/* Exist on i.MX6SX */
> #define MXC_CCM_CCGR3_M4_OFFSET 2
> #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
> #define MXC_CCM_CCGR3_ENET_OFFSET 4
> #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
> #define MXC_CCM_CCGR3_QSPI_OFFSET 14
> #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
> -#else
> +
> #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
> #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
> #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
> #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
> #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
> #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
> -#endif
> +
> #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
> #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
> #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
> @@ -640,15 +657,22 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
> #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
> #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
> -#ifdef CONFIG_MX6SX
> +
> +/* QSPI1 exists on i.MX6SX/UL */
> #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
> #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
> -#else
> +
> #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
> #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
> #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
> #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
> -#endif
> +
> +/* A7_CLKDIV/WDOG1 on i.MX6UL */
> +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
> +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
> +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
> +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
> +
> #define MXC_CCM_CCGR3_MLB_OFFSET 18
> #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
> #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
> @@ -661,8 +685,16 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
> +/* AXI on i.MX6UL */
> +#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
> +#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
> #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
> #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
> +
> +/* GPIO4 on i.MX6UL */
> +#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
> +#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
> +
> #ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
> #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
> @@ -670,13 +702,11 @@ struct mxc_ccm_reg {
>
> #define MXC_CCM_CCGR4_PCIE_OFFSET 0
> #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
> -#ifdef CONFIG_MX6SX
> +/* QSPI2 on i.MX6SX */
> #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
> #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
> -#else
> #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
> #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
> -#endif
> #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
> #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
> #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
> @@ -736,6 +766,12 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
> #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
> #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
> +/* GPMI/BCH on i.MX6UL */
> +#define MXC_CCM_CCGR6_BCH_OFFSET 6
> +#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
> +#define MXC_CCM_CCGR6_GPMI_OFFSET 8
> +#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
> +
> #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
> #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
> #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF
2015-07-20 11:28 ` [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
> chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
> There is on specific switch for on/off L2 Cache, so default select
> SYS_L2CACHE_OFF.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> refine commit msg.
>
> arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
> index 10908c4..fceba27 100644
> --- a/arch/arm/cpu/armv7/mx6/Kconfig
> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> @@ -25,6 +25,10 @@ config MX6SL
> config MX6SX
> bool
>
> +config MX6UL
> + select SYS_L2CACHE_OFF
> + bool
> +
> choice
> prompt "MX6 board select"
> optional
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings
2015-07-20 11:28 ` [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> 1.Update WDOG settings.
> 2.No need to gate/ungate all PFDs for i.MX6UL.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> runtime check for wdog part.
>
> arch/arm/cpu/armv7/mx6/soc.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index e80c09c..033f9de 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -316,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable)
> {
> struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
> struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
> -
> -#ifdef CONFIG_MX6SX
> struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
> - writew(enable, &wdog3->wmcr);
> -#endif
> +
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
> + writew(enable, &wdog3->wmcr);
>
> /* Write to the PDE (Power Down Enable) bit */
> writew(enable, &wdog1->wmcr);
> @@ -530,7 +529,7 @@ void s_init(void)
> u32 mask528;
> u32 reg, periph1, periph2;
>
> - if (is_cpu_type(MXC_CPU_MX6SX))
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
> return;
>
> /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
2015-07-20 11:28 ` [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)
>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> none
>
> arch/arm/include/asm/imx-common/iomux-v3.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
> index 5cde90f..42098a3 100644
> --- a/arch/arm/include/asm/imx-common/iomux-v3.h
> +++ b/arch/arm/include/asm/imx-common/iomux-v3.h
> @@ -98,7 +98,11 @@ typedef u64 iomux_v3_cfg_t;
>
> #define PAD_CTL_ODE (1 << 11)
>
> +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
> +#define PAD_CTL_SPEED_LOW (0 << 6)
> +#else
> #define PAD_CTL_SPEED_LOW (1 << 6)
> +#endif
> #define PAD_CTL_SPEED_MED (2 << 6)
> #define PAD_CTL_SPEED_HIGH (3 << 6)
>
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> none
>
> drivers/gpio/mxc_gpio.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
> index 2012f99..57a650f 100644
> --- a/drivers/gpio/mxc_gpio.c
> +++ b/drivers/gpio/mxc_gpio.c
> @@ -45,11 +45,15 @@ static unsigned long gpio_ports[] = {
> #endif
> #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
> [4] = GPIO5_BASE_ADDR,
> +#ifndef CONFIG_MX6UL
> [5] = GPIO6_BASE_ADDR,
> #endif
> +#endif
> #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
> +#ifndef CONFIG_MX6UL
> [6] = GPIO7_BASE_ADDR,
> #endif
> +#endif
> };
>
> static int mxc_gpio_direction(unsigned int gpio,
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
2015-07-20 11:28 ` [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL Peng Fan
@ 2015-08-02 9:17 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:17 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> DRAM space starts from 0x80000000 for i.MX6UL, so need to
> fix LOADADDR, SYS_TEXT_BASE.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> refine commit msg.
>
> include/configs/mx6_common.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
> index ce43bd7..ef4cb68 100644
> --- a/include/configs/mx6_common.h
> +++ b/include/configs/mx6_common.h
> @@ -54,7 +54,7 @@
> #define CONFIG_REVISION_TAG
>
> /* Boot options */
> -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL))
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
> #define CONFIG_LOADADDR 0x82000000
> #ifndef CONFIG_SYS_TEXT_BASE
> #define CONFIG_SYS_TEXT_BASE 0x87800000
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file
2015-07-20 11:28 ` [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file Peng Fan
@ 2015-08-02 9:18 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:18 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
> 2. Add a new function mx6ul_dram_iocfg to configure dram io.
> 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
> only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
> runtime check, but not hardcoding #ifdef macros.
> 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
> IO configuration.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> new patch
>
> arch/arm/cpu/armv7/mx6/ddr.c | 61 ++++++++++++++++++++++++++-----
> arch/arm/include/asm/arch-mx6/mx6-ddr.h | 45 +++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 45 +++++++++++++++++++++++
> 3 files changed, 141 insertions(+), 10 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
>
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index 86c8354..b808627 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
> }
> #endif
>
> +#ifdef CONFIG_MX6UL
> +void mx6ul_dram_iocfg(unsigned width,
> + const struct mx6ul_iomux_ddr_regs *ddr,
> + const struct mx6ul_iomux_grp_regs *grp)
> +{
> + struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
> + struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
> +
> + mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
> + mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
> +
> + /* DDR IO TYPE */
> + writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
> + writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
> +
> + /* CLOCK */
> + writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
> +
> + /* ADDRESS */
> + writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
> + writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
> + writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
> +
> + /* Control */
> + writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
> + writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
> + writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
> + writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
> + writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
> +
> + /* Data Strobes */
> + writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
> + writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
> + writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
> +
> + /* Data */
> + writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
> + writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
> + writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
> + writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
> + writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
> +}
> +#endif
> +
> #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
> /* Configure MX6DQ mmdc iomux */
> void mx6dq_dram_iocfg(unsigned width,
> @@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
> */
> #define MR(val, ba, cmd, cs1) \
> ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
> -#ifdef CONFIG_MX6SX
> -#define MMDC1(entry, value) do {} while (0)
> -#else
> -#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
> -#endif
> +#define MMDC1(entry, value) do { \
> + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
> + mmdc1->entry = value; \
> + } while (0)
> +
> void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
> const struct mx6_mmdc_calibration *calib,
> const struct mx6_ddr3_cfg *ddr3_cfg)
> {
> volatile struct mmdc_p_regs *mmdc0;
> -#ifndef CONFIG_MX6SX
> volatile struct mmdc_p_regs *mmdc1;
> -#endif
> u32 val;
> u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
> u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
> @@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
> u16 mem_speed = ddr3_cfg->mem_speed;
>
> mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> -#ifndef CONFIG_MX6SX
> - mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
> -#endif
> + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
> + mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
>
> /* Limit mem_speed for MX6D/MX6Q */
> if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> index c49aa62..7bfbdc3 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -16,7 +16,11 @@
> #ifdef CONFIG_MX6SX
> #include "mx6sx-ddr.h"
> #else
> +#ifdef CONFIG_MX6UL
> +#include "mx6ul-ddr.h"
> +#else
> #error "Please select cpu"
> +#endif /* CONFIG_MX6UL */
> #endif /* CONFIG_MX6SX */
> #endif /* CONFIG_MX6DL or CONFIG_MX6S */
> #endif /* CONFIG_MX6Q */
> @@ -62,6 +66,44 @@ struct mmdc_p_regs {
> u32 mpmur0;
> };
>
> +#define MX6UL_IOM_DDR_BASE 0x020e0200
> +struct mx6ul_iomux_ddr_regs {
> + u32 res1[17];
> + u32 dram_dqm0;
> + u32 dram_dqm1;
> + u32 dram_ras;
> + u32 dram_cas;
> + u32 dram_cs0;
> + u32 dram_cs1;
> + u32 dram_sdwe_b;
> + u32 dram_odt0;
> + u32 dram_odt1;
> + u32 dram_sdba0;
> + u32 dram_sdba1;
> + u32 dram_sdba2;
> + u32 dram_sdcke0;
> + u32 dram_sdcke1;
> + u32 dram_sdclk_0;
> + u32 dram_sdqs0;
> + u32 dram_sdqs1;
> + u32 dram_reset;
> +};
> +
> +#define MX6UL_IOM_GRP_BASE 0x020e0400
> +struct mx6ul_iomux_grp_regs {
> + u32 res1[36];
> + u32 grp_addds;
> + u32 grp_ddrmode_ctl;
> + u32 grp_b0ds;
> + u32 grp_ddrpk;
> + u32 grp_ctlds;
> + u32 grp_b1ds;
> + u32 grp_ddrhys;
> + u32 grp_ddrpke;
> + u32 grp_ddrmode;
> + u32 grp_ddr_type;
> +};
> +
> #define MX6SX_IOM_DDR_BASE 0x020e0200
> struct mx6sx_iomux_ddr_regs {
> u32 res1[59];
> @@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
> void mx6sx_dram_iocfg(unsigned width,
> const struct mx6sx_iomux_ddr_regs *,
> const struct mx6sx_iomux_grp_regs *);
> +void mx6ul_dram_iocfg(unsigned width,
> + const struct mx6ul_iomux_ddr_regs *,
> + const struct mx6ul_iomux_grp_regs *);
>
> /* configure mx6 mmdc registers */
> void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
> diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
> new file mode 100644
> index 0000000..ed11c4b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_MX6UL_DDR_H__
> +#define __ASM_ARCH_MX6UL_DDR_H__
> +
> +#ifndef CONFIG_MX6UL
> +#error "wrong CPU"
> +#endif
> +
> +#define MX6_IOM_DRAM_DQM0 0x020e0244
> +#define MX6_IOM_DRAM_DQM1 0x020e0248
> +
> +#define MX6_IOM_DRAM_RAS 0x020e024c
> +#define MX6_IOM_DRAM_CAS 0x020e0250
> +#define MX6_IOM_DRAM_CS0 0x020e0254
> +#define MX6_IOM_DRAM_CS1 0x020e0258
> +#define MX6_IOM_DRAM_SDWE_B 0x020e025c
> +#define MX6_IOM_DRAM_SDODT0 0x020e0260
> +#define MX6_IOM_DRAM_SDODT1 0x020e0264
> +#define MX6_IOM_DRAM_SDBA0 0x020e0268
> +#define MX6_IOM_DRAM_SDBA1 0x020e026c
> +#define MX6_IOM_DRAM_SDBA2 0x020e0270
> +#define MX6_IOM_DRAM_SDCKE0 0x020e0274
> +#define MX6_IOM_DRAM_SDCKE1 0x020e0278
> +#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
> +#define MX6_IOM_DRAM_SDQS0 0x020e0280
> +#define MX6_IOM_DRAM_SDQS1 0x020e0284
> +#define MX6_IOM_DRAM_RESET 0x020e0288
> +
> +#define MX6_IOM_GRP_ADDDS 0x020e0490
> +#define MX6_IOM_DDRMODE_CTL 0x020e0494
> +#define MX6_IOM_GRP_B0DS 0x020e0498
> +#define MX6_IOM_GRP_DDRPK 0x020e049c
> +#define MX6_IOM_GRP_CTLDS 0x020e04a0
> +#define MX6_IOM_GRP_B1DS 0x020e04a4
> +#define MX6_IOM_GRP_DDRHYS 0x020e04a8
> +#define MX6_IOM_GRP_DDRPKE 0x020e04ac
> +#define MX6_IOM_GRP_DDRMODE 0x020e04b0
> +#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
> +
> +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support Peng Fan
@ 2015-08-02 9:18 ` Stefano Babic
0 siblings, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:18 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
> same address with i.MX6SX.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> None
>
> Changes v2:
> new patch
>
> include/configs/imx6_spl.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
> index 21c5dce..0a585b7 100644
> --- a/include/configs/imx6_spl.h
> +++ b/include/configs/imx6_spl.h
> @@ -61,7 +61,7 @@
> #define CONFIG_SPL_LIBDISK_SUPPORT
> #endif
>
> -#if defined(CONFIG_MX6SX)
> +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
> #define CONFIG_SPL_BSS_START_ADDR 0x88200000
> #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
> #define CONFIG_SYS_SPL_MALLOC_START 0x88300000
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
@ 2015-08-02 9:18 ` Stefano Babic
2015-08-10 16:22 ` Fabio Estevam
1 sibling, 0 replies; 36+ messages in thread
From: Stefano Babic @ 2015-08-02 9:18 UTC (permalink / raw)
To: u-boot
On 20/07/2015 13:28, Peng Fan wrote:
> 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
> 2. Support SPL
> 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
> supports sd for usdhc2, but can do hardware rework to make usdhc2 support
> emmc.
>
> Boot Log:
> U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
> reading u-boot.img
> reading u-boot.img
>
> U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
>
> CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
> CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
> - invalid sensor device
> Reset cause: POR
> Board: MX6UL 14x14 EVK
> I2C: ready
> DRAM: 512 MiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: CPU Net Initialization Failed
> No ethernet found.
> Hit any key to stop autoboot: 0
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> none
>
> Changes v2:
> Add SPL support
> More commit msg for CONFIG_MX6UL_14X14_EVK_EMMC_REWORK.
>
> arch/arm/Kconfig | 8 +
> board/freescale/mx6ul_14x14_evk/Kconfig | 15 +
> board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 +
> board/freescale/mx6ul_14x14_evk/Makefile | 6 +
> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++++++++++++
> configs/mx6ul_14x14_evk_defconfig | 4 +
> include/configs/mx6ul_14x14_evk.h | 227 ++++++++
> 7 files changed, 902 insertions(+)
> create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig
> create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS
> create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile
> create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> create mode 100644 configs/mx6ul_14x14_evk_defconfig
> create mode 100644 include/configs/mx6ul_14x14_evk.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 9908b43..14a622e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -575,6 +575,13 @@ config TARGET_MX6SXSABRESD
> select DM
> select DM_THERMAL
>
> +config TARGET_MX6UL_14X14_EVK
> + bool "Support mx6ul_14x14_evk"
> + select CPU_V7
> + select DM
> + select DM_THERMAL
> + select SUPPORT_SPL
> +
> config TARGET_GW_VENTANA
> bool "Support gw_ventana"
> select CPU_V7
> @@ -920,6 +927,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
> source "board/freescale/mx6sabresd/Kconfig"
> source "board/freescale/mx6slevk/Kconfig"
> source "board/freescale/mx6sxsabresd/Kconfig"
> +source "board/freescale/mx6ul_14x14_evk/Kconfig"
> source "board/freescale/vf610twr/Kconfig"
> source "board/gateworks/gw_ventana/Kconfig"
> source "board/genesi/mx51_efikamx/Kconfig"
> diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
> new file mode 100644
> index 0000000..393aca6
> --- /dev/null
> +++ b/board/freescale/mx6ul_14x14_evk/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_MX6UL_14X14_EVK
> +
> +config SYS_BOARD
> + default "mx6ul_14x14_evk"
> +
> +config SYS_VENDOR
> + default "freescale"
> +
> +config SYS_SOC
> + default "mx6"
> +
> +config SYS_CONFIG_NAME
> + default "mx6ul_14x14_evk"
> +
> +endif
> diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
> new file mode 100644
> index 0000000..611feca
> --- /dev/null
> +++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX6ULEVK BOARD
> +M: Peng Fan <Peng.Fan@freescale.com>
> +S: Maintained
> +F: board/freescale/mx6ul_14x14_evk/
> +F: include/configs/mx6ul_14x14_evk.h
> +F: configs/mx6ul_14x14_evk_defconfig
> diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile
> new file mode 100644
> index 0000000..61f6778
> --- /dev/null
> +++ b/board/freescale/mx6ul_14x14_evk/Makefile
> @@ -0,0 +1,6 @@
> +# (C) Copyright 2015 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := mx6ul_14x14_evk.o
> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> new file mode 100644
> index 0000000..8f712cb
> --- /dev/null
> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> @@ -0,0 +1,636 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/mx6ul_pins.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/io.h>
> +#include <common.h>
> +#include <fsl_esdhc.h>
> +#include <i2c.h>
> +#include <linux/sizes.h>
> +#include <mmc.h>
> +#include <usb.h>
> +#include <usb/ehci-fsl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE)
> +
> +#define IOX_SDI IMX_GPIO_NR(5, 10)
> +#define IOX_STCP IMX_GPIO_NR(5, 7)
> +#define IOX_SHCP IMX_GPIO_NR(5, 11)
> +#define IOX_OE IMX_GPIO_NR(5, 18)
> +
> +static iomux_v3_cfg_t const iox_pads[] = {
> + /* IOX_SDI */
> + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* IOX_SHCP */
> + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* IOX_STCP */
> + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* IOX_nOE */
> + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +/*
> + * HDMI_nRST --> Q0
> + * ENET1_nRST --> Q1
> + * ENET2_nRST --> Q2
> + * CAN1_2_STBY --> Q3
> + * BT_nPWD --> Q4
> + * CSI_RST --> Q5
> + * CSI_PWDN --> Q6
> + * LCD_nPWREN --> Q7
> + */
> +enum qn {
> + HDMI_NRST,
> + ENET1_NRST,
> + ENET2_NRST,
> + CAN1_2_STBY,
> + BT_NPWD,
> + CSI_RST,
> + CSI_PWDN,
> + LCD_NPWREN,
> +};
> +
> +enum qn_func {
> + qn_reset,
> + qn_enable,
> + qn_disable,
> +};
> +
> +enum qn_level {
> + qn_low = 0,
> + qn_high = 1,
> +};
> +
> +static enum qn_level seq[3][2] = {
> + {0, 1}, {1, 1}, {0, 0}
> +};
> +
> +static enum qn_func qn_output[8] = {
> + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
> + qn_disable, qn_enable
> +};
> +
> +static void iox74lv_init(void)
> +{
> + int i;
> +
> + gpio_direction_output(IOX_OE, 0);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + gpio_direction_output(IOX_OE, 1);
> +};
> +
> +void iox74lv_set(int index)
> +{
> + int i;
> +
> + gpio_direction_output(IOX_OE, 0);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> +
> + if (i == index)
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
> + else
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + gpio_direction_output(IOX_OE, 1);
> +};
> +
> +#ifdef CONFIG_SYS_I2C_MXC
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +/* I2C1 for PMIC and EEPROM */
> +struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
> + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
> + .gp = IMX_GPIO_NR(1, 28),
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
> + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
> + .gp = IMX_GPIO_NR(1, 29),
> + },
> +};
> +#endif
> +
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +static iomux_v3_cfg_t const uart1_pads[] = {
> + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +
> + /* VSELECT */
> + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + /* CD */
> + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* RST_B */
> + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +/*
> + * mx6ul_14x14_evk board default supports sd card. If want to use
> + * EMMC, need to do board rework for sd2.
> + * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
> + * emmc, need to define this macro.
> + */
> +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
> +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
> + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +
> + /*
> + * RST_B
> + */
> + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +#else
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
> + /*
> + * The evk board uses DAT3 to detect CD card plugin,
> + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
> + */
> + MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
> + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
> + MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
> +};
> +#endif
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> +}
> +
> +#ifdef CONFIG_FSL_QSPI
> +
> +#define QSPI_PAD_CTRL1 \
> + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
> + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
> +
> +static iomux_v3_cfg_t const quadspi_pads[] = {
> + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
> +};
> +
> +int board_qspi_init(void)
> +{
> + /* Set the iomux */
> + imx_iomux_v3_setup_multiple_pads(quadspi_pads,
> + ARRAY_SIZE(quadspi_pads));
> + /* Set the clock */
> + enable_qspi_clk(0);
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC1_BASE_ADDR, 0, 4},
> +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
> + {USDHC2_BASE_ADDR, 0, 8},
> +#else
> + {USDHC2_BASE_ADDR, 0, 4},
> +#endif
> +};
> +
> +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
> +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC1_BASE_ADDR:
> + ret = !gpio_get_value(USDHC1_CD_GPIO);
> + break;
> + case USDHC2_BASE_ADDR:
> +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
> + ret = 1;
> +#else
> + imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
> + ARRAY_SIZE(usdhc2_cd_pads));
> + gpio_direction_input(USDHC2_CD_GPIO);
> +
> + /*
> + * Since it is the DAT3 pin, this pin is pulled to
> + * low voltage if no card
> + */
> + ret = gpio_get_value(USDHC2_CD_GPIO);
> +
> + imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
> + ARRAY_SIZE(usdhc2_dat3_pads));
> +#endif
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +#ifdef CONFIG_SPL_BUILD
> +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
> + imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
> + ARRAY_SIZE(usdhc2_emmc_pads));
> +#else
> + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> +#endif
> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
> +#else
> + int i, ret;
> +
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-boot device node) (Physical Port)
> + * mmc0 USDHC1
> + * mmc1 USDHC2
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + gpio_direction_input(USDHC1_CD_GPIO);
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +
> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
> + break;
> + case 1:
> +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
> +#else
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> +#endif
> + gpio_direction_output(USDHC2_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC2_PWR_GPIO, 1);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + break;
> + default:
> + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret) {
> + printf("Warning: failed to initialize mmc dev %d\n", i);
> + return ret;
> + }
> + }
> +#endif
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> +#define USB_OTHERREGS_OFFSET 0x800
> +#define UCTRL_PWR_POL (1 << 9)
> +
> +static iomux_v3_cfg_t const usb_otg_pads[] = {
> + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +/* At default the 3v3 enables the MIC2026 for VBUS power */
> +static void setup_usb(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
> + ARRAY_SIZE(usb_otg_pads));
> +}
> +
> +int board_usb_phy_mode(int port)
> +{
> + if (port == 1)
> + return USB_INIT_HOST;
> + else
> + return usb_phy_mode(port);
> +}
> +
> +int board_ehci_hcd_init(int port)
> +{
> + u32 *usbnc_usb_ctrl;
> +
> + if (port > 1)
> + return -EINVAL;
> +
> + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
> + port * 4);
> +
> + /* Set Power polarity */
> + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
> +
> + return 0;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* Address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
> +
> + iox74lv_init();
> +
> +#ifdef CONFIG_SYS_I2C_MXC
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +#endif
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> + setup_usb();
> +#endif
> +
> +#ifdef CONFIG_FSL_QSPI
> + board_qspi_init();
> +#endif
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
> + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> +
> + return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + return get_cpu_rev();
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: MX6UL 14x14 EVK\n");
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +#include <libfdt.h>
> +#include <spl.h>
> +#include <asm/arch/mx6-ddr.h>
> +
> +const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
> + .dram_dqm0 = 0x00000030,
> + .dram_dqm1 = 0x00000030,
> + .dram_ras = 0x00000030,
> + .dram_cas = 0x00000030,
> + .dram_odt0 = 0x00000030,
> + .dram_odt1 = 0x00000030,
> + .dram_sdba2 = 0x00000000,
> + .dram_sdclk_0 = 0x00000008,
> + .dram_sdqs0 = 0x00000038,
> + .dram_sdqs1 = 0x00000030,
> + .dram_reset = 0x00000030,
> +};
> +
> +const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
> + .grp_addds = 0x00000030,
> + .grp_ddrmode_ctl = 0x00020000,
> + .grp_b0ds = 0x00000030,
> + .grp_ctlds = 0x00000030,
> + .grp_b1ds = 0x00000030,
> + .grp_ddrpke = 0x00000000,
> + .grp_ddrmode = 0x00020000,
> + .grp_ddr_type = 0x000c0000,
> +};
> +
> +const struct mx6_mmdc_calibration mx6_mmcd_calib = {
> + .p0_mpwldectrl0 = 0x00070007,
> + .p0_mpdgctrl0 = 0x41490145,
> + .p0_mprddlctl = 0x40404546,
> + .p0_mpwrdlctl = 0x4040524D,
> +};
> +
> +static struct mx6_ddr3_cfg mem_ddr = {
> + .mem_speed = 800,
> + .density = 4,
> + .width = 16,
> + .banks = 8,
> + .rowaddr = 15,
> + .coladdr = 10,
> + .pagesz = 2,
> + .trcd = 1375,
> + .trcmin = 4875,
> + .trasmin = 3500,
> +};
> +
> +static void ccgr_init(void)
> +{
> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + writel(0xFFFFFFFF, &ccm->CCGR0);
> + writel(0xFFFFFFFF, &ccm->CCGR1);
> + writel(0xFFFFFFFF, &ccm->CCGR2);
> + writel(0xFFFFFFFF, &ccm->CCGR3);
> + writel(0xFFFFFFFF, &ccm->CCGR4);
> + writel(0xFFFFFFFF, &ccm->CCGR5);
> + writel(0xFFFFFFFF, &ccm->CCGR6);
> + writel(0xFFFFFFFF, &ccm->CCGR7);
> +}
> +
> +static void spl_dram_init(void)
> +{
> + struct mx6_ddr_sysinfo sysinfo = {
> + .dsize = 0,
> + .cs_density = 20,
> + .ncs = 1,
> + .cs1_mirror = 0,
> + .rtt_wr = 2,
> + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
> + .walat = 1, /* Write additional latency */
> + .ralat = 5, /* Read additional latency */
> + .mif3_mode = 3, /* Command prediction working mode */
> + .bi_on = 1, /* Bank interleaving enabled */
> + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> + };
> +
> + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + /* setup AIPS and disable watchdog */
> + arch_cpu_init();
> +
> + ccgr_init();
> +
> + /* iomux and setup of i2c */
> + board_early_init_f();
> +
> + /* setup GP timer */
> + timer_init();
> +
> + /* UART clocks enabled and gd valid - init serial console */
> + preloader_console_init();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + /* load/boot image from boot device */
> + board_init_r(NULL, 0);
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +}
> +#endif
> diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
> new file mode 100644
> index 0000000..b6eefaf
> --- /dev/null
> +++ b/configs/mx6ul_14x14_evk_defconfig
> @@ -0,0 +1,4 @@
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
> +CONFIG_ARM=y
> +CONFIG_TARGET_MX6UL_14X14_EVK=y
> +CONFIG_SPL=y
> diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
> new file mode 100644
> index 0000000..436b022
> --- /dev/null
> +++ b/include/configs/mx6ul_14x14_evk.h
> @@ -0,0 +1,227 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef __MX6UL_14X14_EVK_CONFIG_H
> +#define __MX6UL_14X14_EVK_CONFIG_H
> +
> +
> +#include <asm/arch/imx-regs.h>
> +#include <linux/sizes.h>
> +#include "mx6_common.h"
> +#include <asm/imx-common/gpio.h>
> +
> +/* SPL options */
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#include "imx6_spl.h"
> +
> +#define CONFIG_MX6
> +#define CONFIG_ROM_UNIFIED_SECTIONS
> +#define CONFIG_SYS_GENERIC_BOARD
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +
> +#define CONFIG_CMD_FUSE
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
> +
> +/* MMC Configs */
> +#ifdef CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
> +
> +/* NAND pin conflicts with usdhc2 */
> +#ifdef CONFIG_NAND_MXS
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +#else
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#endif
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> +#endif
> +
> +#undef CONFIG_BOOTM_NETBSD
> +#undef CONFIG_BOOTM_PLAN9
> +#undef CONFIG_BOOTM_RTEMS
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +
> +/* I2C configs */
> +#define CONFIG_CMD_I2C
> +#ifdef CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#endif
> +
> +#define PHYS_SDRAM_SIZE SZ_512M
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=zImage\0" \
> + "console=ttymxc0\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "fdt_file=imx6ul-14x14-evk.dtb\0" \
> + "fdt_addr=0x83000000\0" \
> + "boot_fdt=try\0" \
> + "ip_dyn=yes\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcautodetect=yes\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot}\0" \
> + "loadbootscript=" \
> + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev};" \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else run netboot; fi"
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_PROMPT "=> "
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +#define CONFIG_CMD_MEMTEST
> +#define CONFIG_SYS_MEMTEST_START 0x80000000
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_STACKSIZE SZ_128K
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE SZ_8K
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_ENV_OFFSET (8 * SZ_64K)
> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
> +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_BMODE
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +#define CONFIG_FSL_QSPI
> +#ifdef CONFIG_FSL_QSPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_SPI_FLASH_BAR
> +#define CONFIG_SF_DEFAULT_BUS 0
> +#define CONFIG_SF_DEFAULT_CS 0
> +#define CONFIG_SF_DEFAULT_SPEED 40000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +#define FSL_QSPI_FLASH_NUM 1
> +#define FSL_QSPI_FLASH_SIZE SZ_32M
> +#endif
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> +#endif
> +
> +#define CONFIG_IMX6_THERMAL
> +
> +#endif
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
2015-08-02 9:18 ` Stefano Babic
@ 2015-08-10 16:22 ` Fabio Estevam
2015-08-11 0:13 ` Peng Fan
1 sibling, 1 reply; 36+ messages in thread
From: Fabio Estevam @ 2015-08-10 16:22 UTC (permalink / raw)
To: u-boot
Hi Peng,
On Mon, Jul 20, 2015 at 8:28 AM, Peng Fan <Peng.Fan@freescale.com> wrote:
> 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
> 2. Support SPL
> 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
> supports sd for usdhc2, but can do hardware rework to make usdhc2 support
> emmc.
>
> Boot Log:
> U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
> reading u-boot.img
> reading u-boot.img
>
> U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
>
> CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
> CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
> - invalid sensor device
> Reset cause: POR
> Board: MX6UL 14x14 EVK
> I2C: ready
> DRAM: 512 MiB
> MMC: FSL_SDHC: 0, FSL_SDHC: 1
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: CPU Net Initialization Failed
> No ethernet found.
> Hit any key to stop autoboot: 0
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
I am running u-boot-imx tree that has this patch applied, but I am not
able to boot from SD card:
U-Boot SPL 2015.07-22910-g1c23c1e (Aug 10 2015 - 16:17:50)
MMC: no card present
spl: mmc init failed with error: -16
### ERROR ### Please RESET the board ###
Any ideas?
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support
2015-08-10 16:22 ` Fabio Estevam
@ 2015-08-11 0:13 ` Peng Fan
2015-08-11 10:31 ` Fabio Estevam
0 siblings, 1 reply; 36+ messages in thread
From: Peng Fan @ 2015-08-11 0:13 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On Mon, Aug 10, 2015 at 01:22:49PM -0300, Fabio Estevam wrote:
>Hi Peng,
>
>On Mon, Jul 20, 2015 at 8:28 AM, Peng Fan <Peng.Fan@freescale.com> wrote:
>> 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
>> 2. Support SPL
>> 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
>> supports sd for usdhc2, but can do hardware rework to make usdhc2 support
>> emmc.
>>
>> Boot Log:
>> U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
>> reading u-boot.img
>> reading u-boot.img
>>
>> U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
>>
>> CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
>> CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
>> - invalid sensor device
>> Reset cause: POR
>> Board: MX6UL 14x14 EVK
>> I2C: ready
>> DRAM: 512 MiB
>> MMC: FSL_SDHC: 0, FSL_SDHC: 1
>> *** Warning - bad CRC, using default environment
>>
>> In: serial
>> Out: serial
>> Err: serial
>> Net: CPU Net Initialization Failed
>> No ethernet found.
>> Hit any key to stop autoboot: 0
>>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>
>I am running u-boot-imx tree that has this patch applied, but I am not
>able to boot from SD card:
>
>U-Boot SPL 2015.07-22910-g1c23c1e (Aug 10 2015 - 16:17:50)
>MMC: no card present
>spl: mmc init failed with error: -16
>### ERROR ### Please RESET the board ###
>
>Any ideas?
Are you using the micro sd slot for boot? Please do not use SD1, the big sd
card slot. We only support sd2, the micro sd slot for boot.
You can refer to the boot select switch. we have no chance to choose sd1
for boot.
Regards,
Peng.
>
>Regards,
>
>Fabio Estevam
--
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support
2015-08-11 0:13 ` Peng Fan
@ 2015-08-11 10:31 ` Fabio Estevam
0 siblings, 0 replies; 36+ messages in thread
From: Fabio Estevam @ 2015-08-11 10:31 UTC (permalink / raw)
To: u-boot
Hi Peng,
On Mon, Aug 10, 2015 at 9:13 PM, Peng Fan <b51431@freescale.com> wrote:
> Are you using the micro sd slot for boot? Please do not use SD1, the big sd
> card slot. We only support sd2, the micro sd slot for boot.
>
> You can refer to the boot select switch. we have no chance to choose sd1
> for boot.
I was using the big SD slot and was not aware of this limitation.
Will try to boot from the micro SD slot instead.
Thanks,
Fabio Estevam
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2015-08-11 10:31 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
2015-08-02 9:05 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file Peng Fan
2015-08-02 9:06 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
2015-07-20 18:39 ` Marek Vasut
2015-08-02 9:07 ` Stefano Babic
2015-08-02 9:15 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Peng Fan
2015-08-02 9:15 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-08-10 16:22 ` Fabio Estevam
2015-08-11 0:13 ` Peng Fan
2015-08-11 10:31 ` Fabio Estevam
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.