From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: "Jon Hunter" <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, "Stephen Warren" <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>, "Alexandre Courbot" <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, "Philipp Zabel" <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>, "Prashant Gaikwad" <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, "Terje Bergström" <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, "Hans de Goede" <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, "Tejun Heo" <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, "Vince Hsu" <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, "Rafael J. Wysocki" <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>, "Kevin Hilman" <khilman-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, "Ulf Hansson" <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: Re: [PATCH V3 02/19] memory: tegra: Add MC flush support Date: Tue, 21 Jul 2015 13:57:51 +0300 [thread overview] Message-ID: <20150721105751.GK6287@tbergstrom-lnx.Nvidia.com> (raw) In-Reply-To: <20150720131410.GA1098@ulmo> On Mon, Jul 20, 2015 at 03:14:25PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Jul 20, 2015 at 12:59:41PM +0300, Peter De Schrijver wrote: > > On Fri, Jul 17, 2015 at 01:31:24PM +0200, Thierry Reding wrote: > > > > Old Signed by an unknown key > > > > > > On Fri, Jul 17, 2015 at 01:20:49PM +0300, Peter De Schrijver wrote: > > > > On Fri, Jul 17, 2015 at 11:57:55AM +0200, Thierry Reding wrote: > > > > > > Old Signed by an unknown key > > > > > > > > > > On Mon, Jul 13, 2015 at 01:39:40PM +0100, Jon Hunter wrote: > > > > > > The Tegra memory controller implements a flush feature to flush pending > > > > > > accesses and prevent further accesses from occurring. This feature is > > > > > > used when powering down IP blocks to ensure the IP block is in a good > > > > > > state. The flushes are organised by software groups and IP blocks are > > > > > > assigned in hardware to the different software groups. Add helper > > > > > > functions for requesting a handle to an MC flush for a given > > > > > > software group and enabling/disabling the MC flush itself. > > > > > > > > > > > > This is based upon a change by Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>. > > > > > > > > > > > > Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > > > > > --- > > > > > > drivers/memory/tegra/mc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > drivers/memory/tegra/mc.h | 2 + > > > > > > include/soc/tegra/mc.h | 34 ++++++++++++++ > > > > > > 3 files changed, 146 insertions(+) > > > > > > > > > > Do we know if this is actually necessary? I remember having a discussion > > > > > with Arnd Bergmann a while ago, and the Linux driver model kind of > > > > > assumes that by the time a device is disabled all outstanding accesses > > > > > will have stopped. > > > > > > > > > > Do we have a way to determine that this even makes a difference? Can we > > > > > trigger a case where not doing this would cause breakage and see that > > > > > adding this fixes that particular issue? > > > > > > > > > > > > > Most likely it is. The memory controller can still be processing requests > > > > when the peripheral domain is powergated. This would mean the response cannot > > > > be delivered in that case. So we need to be sure there are no outstanding > > > > requests before shutting down the domain. > > > > > > My point is that that's the driver's responsibility anyway, hence making > > > the explicit flush unnecessary. > > > > > > > The peripheral driver doesn't know how long a request is queued in the memory > > controller. So it can't be responsible for ensuring this. > > Surely whenever the peripheral reports that the operation is done (be > that via some DMA controller interrupt or syncpoint increment) the > operation would have flushed from the memory controller. Drivers are > already supposed to make sure this is the case when they are removed or > suspended, so this would mean that we'd be adding all this code for no > real gain. > That highly depends on how the peripheral is implemented. I'm not sure we can assume things work this way. > It would also explain why we're currently not seeing any such problems. > I don't think we are doing agressive enough powergating today to see any problems. That might also mean we're just lucky. Cheers, Peter.
WARNING: multiple messages have this Message-ID (diff)
From: pdeschrijver@nvidia.com (Peter De Schrijver) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V3 02/19] memory: tegra: Add MC flush support Date: Tue, 21 Jul 2015 13:57:51 +0300 [thread overview] Message-ID: <20150721105751.GK6287@tbergstrom-lnx.Nvidia.com> (raw) In-Reply-To: <20150720131410.GA1098@ulmo> On Mon, Jul 20, 2015 at 03:14:25PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Jul 20, 2015 at 12:59:41PM +0300, Peter De Schrijver wrote: > > On Fri, Jul 17, 2015 at 01:31:24PM +0200, Thierry Reding wrote: > > > > Old Signed by an unknown key > > > > > > On Fri, Jul 17, 2015 at 01:20:49PM +0300, Peter De Schrijver wrote: > > > > On Fri, Jul 17, 2015 at 11:57:55AM +0200, Thierry Reding wrote: > > > > > > Old Signed by an unknown key > > > > > > > > > > On Mon, Jul 13, 2015 at 01:39:40PM +0100, Jon Hunter wrote: > > > > > > The Tegra memory controller implements a flush feature to flush pending > > > > > > accesses and prevent further accesses from occurring. This feature is > > > > > > used when powering down IP blocks to ensure the IP block is in a good > > > > > > state. The flushes are organised by software groups and IP blocks are > > > > > > assigned in hardware to the different software groups. Add helper > > > > > > functions for requesting a handle to an MC flush for a given > > > > > > software group and enabling/disabling the MC flush itself. > > > > > > > > > > > > This is based upon a change by Vince Hsu <vinceh@nvidia.com>. > > > > > > > > > > > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > > > > > > --- > > > > > > drivers/memory/tegra/mc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++ > > > > > > drivers/memory/tegra/mc.h | 2 + > > > > > > include/soc/tegra/mc.h | 34 ++++++++++++++ > > > > > > 3 files changed, 146 insertions(+) > > > > > > > > > > Do we know if this is actually necessary? I remember having a discussion > > > > > with Arnd Bergmann a while ago, and the Linux driver model kind of > > > > > assumes that by the time a device is disabled all outstanding accesses > > > > > will have stopped. > > > > > > > > > > Do we have a way to determine that this even makes a difference? Can we > > > > > trigger a case where not doing this would cause breakage and see that > > > > > adding this fixes that particular issue? > > > > > > > > > > > > > Most likely it is. The memory controller can still be processing requests > > > > when the peripheral domain is powergated. This would mean the response cannot > > > > be delivered in that case. So we need to be sure there are no outstanding > > > > requests before shutting down the domain. > > > > > > My point is that that's the driver's responsibility anyway, hence making > > > the explicit flush unnecessary. > > > > > > > The peripheral driver doesn't know how long a request is queued in the memory > > controller. So it can't be responsible for ensuring this. > > Surely whenever the peripheral reports that the operation is done (be > that via some DMA controller interrupt or syncpoint increment) the > operation would have flushed from the memory controller. Drivers are > already supposed to make sure this is the case when they are removed or > suspended, so this would mean that we'd be adding all this code for no > real gain. > That highly depends on how the peripheral is implemented. I'm not sure we can assume things work this way. > It would also explain why we're currently not seeing any such problems. > I don't think we are doing agressive enough powergating today to see any problems. That might also mean we're just lucky. Cheers, Peter.
next prev parent reply other threads:[~2015-07-21 10:57 UTC|newest] Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-07-13 12:39 [PATCH V3 00/19] Add generic PM domain support for Tegra SoCs Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 06/19] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-13 13:41 ` Peter De Schrijver 2015-07-13 13:41 ` Peter De Schrijver 2015-07-13 14:02 ` Jon Hunter 2015-07-13 14:02 ` Jon Hunter [not found] ` <55A3C50E.7060706-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-14 11:59 ` Jon Hunter 2015-07-14 11:59 ` Jon Hunter 2015-07-14 11:59 ` Jon Hunter [not found] ` <55A4F985.7010503-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-15 8:16 ` Peter De Schrijver 2015-07-15 8:16 ` Peter De Schrijver [not found] ` <1436791197-32358-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-13 12:39 ` [PATCH V3 01/19] reset: add of_reset_control_get_by_index() Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-2-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 12:08 ` Philipp Zabel 2015-07-17 12:08 ` Philipp Zabel 2015-07-13 12:39 ` [PATCH V3 02/19] memory: tegra: Add MC flush support Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-17 9:57 ` Thierry Reding 2015-07-17 9:57 ` Thierry Reding 2015-07-17 10:20 ` Peter De Schrijver 2015-07-17 10:20 ` Peter De Schrijver [not found] ` <20150717102049.GQ6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2015-07-17 11:31 ` Thierry Reding 2015-07-17 11:31 ` Thierry Reding 2015-07-20 8:46 ` Jon Hunter 2015-07-20 8:46 ` Jon Hunter 2015-07-20 9:17 ` Thierry Reding 2015-07-20 9:17 ` Thierry Reding 2015-07-20 9:59 ` Peter De Schrijver 2015-07-20 9:59 ` Peter De Schrijver [not found] ` <20150720095941.GZ6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2015-07-20 13:14 ` Thierry Reding 2015-07-20 13:14 ` Thierry Reding 2015-07-21 10:57 ` Peter De Schrijver [this message] 2015-07-21 10:57 ` Peter De Schrijver 2015-07-13 12:39 ` [PATCH V3 03/19] memory: tegra: add flush operation for Tegra30 memory clients Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 10:03 ` Thierry Reding 2015-07-17 10:03 ` Thierry Reding 2015-07-21 8:54 ` Jon Hunter 2015-07-21 8:54 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 04/19] memory: tegra: add flush operation for Tegra114 " Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 10:05 ` Thierry Reding 2015-07-17 10:05 ` Thierry Reding 2015-07-13 12:39 ` [PATCH V3 05/19] memory: tegra: add flush operation for Tegra124 " Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-17 10:05 ` Thierry Reding 2015-07-17 10:05 ` Thierry Reding 2015-07-13 12:39 ` [PATCH V3 07/19] soc: tegra: pmc: Wait for powergate state to change Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-8-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 10:17 ` Thierry Reding 2015-07-17 10:17 ` Thierry Reding 2015-07-21 9:34 ` Jon Hunter 2015-07-21 9:34 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 08/19] soc: tegra: pmc: Clean-up PMC helper functions Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-17 10:25 ` Thierry Reding 2015-07-17 10:25 ` Thierry Reding 2015-07-21 9:38 ` Jon Hunter 2015-07-21 9:38 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 14/19] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-15-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 9:38 ` Thierry Reding 2015-07-17 9:38 ` Thierry Reding 2015-07-13 12:39 ` [PATCH V3 15/19] soc: tegra: pmc: Add generic PM domain support Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-16-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 11:29 ` Thierry Reding 2015-07-17 11:29 ` Thierry Reding 2015-07-13 12:39 ` [PATCH V3 16/19] soc: tegra: pmc: Remove the deprecated powergate APIs Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 18/19] ARM: tegra: add GPU power supply to Jetson TK1 DT Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-19-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 9:28 ` Thierry Reding 2015-07-17 9:28 ` Thierry Reding 2015-07-13 12:39 ` [PATCH V3 19/19] ARM: tegra: select PM_GENERIC_DOMAINS Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 13:50 ` Peter De Schrijver 2015-07-13 13:50 ` Peter De Schrijver [not found] ` <20150713135047.GR6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org> 2015-07-13 14:03 ` Jon Hunter 2015-07-13 14:03 ` Jon Hunter 2015-07-14 11:59 ` Jon Hunter 2015-07-14 11:59 ` Jon Hunter 2015-07-14 11:59 ` Jon Hunter [not found] ` <55A4F9B6.1070904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-15 8:17 ` Peter De Schrijver 2015-07-15 8:17 ` Peter De Schrijver 2015-07-13 12:39 ` [PATCH V3 09/19] soc: tegra: pmc: Prepare for migrating to generic PM domains Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 10/19] drm/tegra: dc: Prepare for " Jon Hunter 2015-07-13 12:39 ` Jon Hunter [not found] ` <1436791197-32358-11-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-17 10:41 ` Thierry Reding 2015-07-17 10:41 ` Thierry Reding 2015-07-28 8:30 ` Jon Hunter 2015-07-28 8:30 ` Jon Hunter [not found] ` <55B73D8C.103-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-07-28 11:20 ` Thierry Reding 2015-07-28 11:20 ` Thierry Reding [not found] ` <20150728112030.GA10949-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org> 2015-07-28 15:30 ` Jon Hunter 2015-07-28 15:30 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 11/19] PCI: tegra: Add support " Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-17 10:45 ` Thierry Reding 2015-07-17 10:45 ` Thierry Reding 2015-07-28 8:35 ` Jon Hunter 2015-07-28 8:35 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 12/19] ata: ahci_tegra: " Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 13/19] drm/tegra: gr3d: " Jon Hunter 2015-07-13 12:39 ` Jon Hunter 2015-07-13 12:39 ` [PATCH V3 17/19] ARM: tegra: Add PM domain device nodes to Tegra124 DT Jon Hunter 2015-07-13 12:39 ` Jon Hunter
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