[Qemu-devel] [Bug 1480562] [NEW] register values in sp804 timer

[Qemu-devel] [Bug 1480562] [NEW] register values in sp804 timer

[T-T Yu]

Public bug reported:

In the arm_timer.c, when first reading the load register,  I got 0.

...
case 0: /* TimerLoad */
...

According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, 
"The minimum valid value for TimerXLoad is 1".  Is the initial value supposed to be 0xffffffff?


When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. 

Thanks.

** Affects: qemu
     Importance: Undecided
         Status: New

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Title:
  register values in sp804 timer

Status in QEMU:
  New

Bug description:
  In the arm_timer.c, when first reading the load register,  I got 0.

  ...
  case 0: /* TimerLoad */
  ...

  According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, 
  "The minimum valid value for TimerXLoad is 1".  Is the initial value supposed to be 0xffffffff?

  
  When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. 

  Thanks.

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Re: [Qemu-devel] [Bug 1480562] [NEW] register values in sp804 timer

[Peter Maydell]

On 1 August 2015 at 15:46, T-T Yu <tingting703@gmail.com> wrote:
> Public bug reported:
>
> In the arm_timer.c, when first reading the load register,  I got 0.
>
> ...
> case 0: /* TimerLoad */
> ...
>
> According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html,
> "The minimum valid value for TimerXLoad is 1".  Is the initial value
> supposed to be 0xffffffff?

No. See the "summary of registers" table 3.1 in section 3.1,
which lists this register's reset value as zero (and also
section 2.2.6 which agrees that on reset the load register
value is zero).

The text you quote is attempting to describe the minimum
value which it is sensible to write to the register -- it
makes no sense for an OS to write 0 to this register because
it would always just interrupt immediately with no actual
timer function, so the shortest possible timeout is
obtained by writing a 1.

> When the 5th and 7th bit in Control Register are set, RIS and MIS
> remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both
> interrupt and timer module are set.

RIS and MIS will only become 1 when the timer generates an
interrupt. They don't get set merely because the OS has
enabled interrupts.

thanks
-- PMM

[Qemu-devel] [Bug 1480562] Re: register values in sp804 timer

[Peter Maydell]

** Changed in: qemu
       Status: New => Invalid

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1480562

Title:
  register values in sp804 timer

Status in QEMU:
  Invalid

Bug description:
  In the arm_timer.c, when first reading the load register,  I got 0.

  ...
  case 0: /* TimerLoad */
  ...

  According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, 
  "The minimum valid value for TimerXLoad is 1".  Is the initial value supposed to be 0xffffffff?

  
  When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. 

  Thanks.

To manage notifications about this bug go to:
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