[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Alison Wang]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a.dtsi    | 82 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..6c41b10 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,85 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d10000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d50000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d90000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
2.1.0.27.g96db324

[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Alison Wang]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a.dtsi    | 82 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..6c41b10 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,85 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d10000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d50000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d90000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
2.1.0.27.g96db324

[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Alison Wang]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++
 arch/arm/boot/dts/ls1021a.dtsi    | 82 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..6c41b10 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,85 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet at 2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d10000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet1: ethernet at 2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d50000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		enet2: ethernet at 2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d90000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb at 8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
2.1.0.27.g96db324

Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> @@ -391,6 +394,85 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet@2d10000 {

Most of the vendor specific properties below are undocumented bindings.

Shawn

> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,magic-packet;
> +			fsl,wake-on-filer;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d10000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +		};
> +
> +		enet1: ethernet@2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d50000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +		};
> +
> +		enet2: ethernet@2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d90000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb@8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 2.1.0.27.g96db324
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 

[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> @@ -391,6 +394,85 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet at 2d10000 {

Most of the vendor specific properties below are undocumented bindings.

Shawn

> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,magic-packet;
> +			fsl,wake-on-filer;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d10000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +		};
> +
> +		enet1: ethernet at 2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d50000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +		};
> +
> +		enet2: ethernet at 2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d90000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb at 8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 2.1.0.27.g96db324
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 

RE: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Sunday, July 12, 2015 9:51 AM
> To: Wang Huan-B18965
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; shawn.guo@linaro.org; Manoil Claudiu-B08782;
> Wang Huan-B18965
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > @@ -391,6 +394,85 @@
> >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> >  		};
> >
> > +		enet0: ethernet@2d10000 {
> 
> Most of the vendor specific properties below are undocumented bindings.
> 
> Shawn
> 

Hi Shawn,

Please note that these properties (with only one exception) were accepted long time ago
and are in use for the upstream powerpc platforms, eg:
$ git grep fsl,num_rx_queues
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",

So, I think the bindings documentation could be added in a separate, follow-up, patch.

Thanks,
Claudiu

RE: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Sunday, July 12, 2015 9:51 AM
> To: Wang Huan-B18965
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Manoil Claudiu-B08782;
> Wang Huan-B18965
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > @@ -391,6 +394,85 @@
> >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> >  		};
> >
> > +		enet0: ethernet@2d10000 {
> 
> Most of the vendor specific properties below are undocumented bindings.
> 
> Shawn
> 

Hi Shawn,

Please note that these properties (with only one exception) were accepted long time ago
and are in use for the upstream powerpc platforms, eg:
$ git grep fsl,num_rx_queues
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",

So, I think the bindings documentation could be added in a separate, follow-up, patch.

Thanks,
Claudiu
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Sunday, July 12, 2015 9:51 AM
> To: Wang Huan-B18965
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; shawn.guo at linaro.org; Manoil Claudiu-B08782;
> Wang Huan-B18965
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > @@ -391,6 +394,85 @@
> >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> >  		};
> >
> > +		enet0: ethernet at 2d10000 {
> 
> Most of the vendor specific properties below are undocumented bindings.
> 
> Shawn
> 

Hi Shawn,

Please note that these properties (with only one exception) were accepted long time ago
and are in use for the upstream powerpc platforms, eg:
$ git grep fsl,num_rx_queues
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",

So, I think the bindings documentation could be added in a separate, follow-up, patch.

Thanks,
Claudiu

Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Mon, Jul 13, 2015 at 10:47:49AM +0000, Manoil Claudiu wrote:
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > Sent: Sunday, July 12, 2015 9:51 AM
> > To: Wang Huan-B18965
> > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; shawn.guo@linaro.org; Manoil Claudiu-B08782;
> > Wang Huan-B18965
> > Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> > eTSEC2
> > 
> > On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > > @@ -391,6 +394,85 @@
> > >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> > >  		};
> > >
> > > +		enet0: ethernet@2d10000 {
> > 
> > Most of the vendor specific properties below are undocumented bindings.
> > 
> > Shawn
> > 
> 
> Hi Shawn,
> 
> Please note that these properties (with only one exception) were accepted long time ago
> and are in use for the upstream powerpc platforms, eg:
> $ git grep fsl,num_rx_queues
> arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
> drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",
> 
> So, I think the bindings documentation could be added in a separate, follow-up, patch.

I would like to see patch for bindings documentation before I apply this
one.

Shawn

Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Mon, Jul 13, 2015 at 10:47:49AM +0000, Manoil Claudiu wrote:
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> > Sent: Sunday, July 12, 2015 9:51 AM
> > To: Wang Huan-B18965
> > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-
> > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Manoil Claudiu-B08782;
> > Wang Huan-B18965
> > Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> > eTSEC2
> > 
> > On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > > @@ -391,6 +394,85 @@
> > >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> > >  		};
> > >
> > > +		enet0: ethernet@2d10000 {
> > 
> > Most of the vendor specific properties below are undocumented bindings.
> > 
> > Shawn
> > 
> 
> Hi Shawn,
> 
> Please note that these properties (with only one exception) were accepted long time ago
> and are in use for the upstream powerpc platforms, eg:
> $ git grep fsl,num_rx_queues
> arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
> drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",
> 
> So, I think the bindings documentation could be added in a separate, follow-up, patch.

I would like to see patch for bindings documentation before I apply this
one.

Shawn
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Mon, Jul 13, 2015 at 10:47:49AM +0000, Manoil Claudiu wrote:
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > Sent: Sunday, July 12, 2015 9:51 AM
> > To: Wang Huan-B18965
> > Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> > kernel at vger.kernel.org; shawn.guo at linaro.org; Manoil Claudiu-B08782;
> > Wang Huan-B18965
> > Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> > eTSEC2
> > 
> > On Thu, Jun 25, 2015 at 02:24:58PM +0800, Alison Wang wrote:
> > > @@ -391,6 +394,85 @@
> > >  			reg = <0x0 0x2d24000 0x0 0x4000>;
> > >  		};
> > >
> > > +		enet0: ethernet at 2d10000 {
> > 
> > Most of the vendor specific properties below are undocumented bindings.
> > 
> > Shawn
> > 
> 
> Hi Shawn,
> 
> Please note that these properties (with only one exception) were accepted long time ago
> and are in use for the upstream powerpc platforms, eg:
> $ git grep fsl,num_rx_queues
> arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi:    fsl,num_rx_queues = <0x8>;
> arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi:    fsl,num_rx_queues = <0x8>;
> drivers/net/ethernet/freescale/gianfar.c:                       ret = of_property_read_u32(np, "fsl,num_rx_queues",
> 
> So, I think the bindings documentation could be added in a separate, follow-up, patch.

I would like to see patch for bindings documentation before I apply this
one.

Shawn

RE: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, July 13, 2015 4:32 PM
> To: Manoil Claudiu-B08782
> Cc: Wang Huan-B18965; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> shawn.guo@linaro.org
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> I would like to see patch for bindings documentation before I apply this
> one.

Agreed.  I just noticed that this is an old version of the patch (using an
obsoleted property), so please expect a v2 of this patch as well,  besides
the device tree binding document which I think will be named:
./Documentation/devicetree/bindings/net/fsl-etsec2.txt.

Thanks.
Claudiu

RE: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, July 13, 2015 4:32 PM
> To: Manoil Claudiu-B08782
> Cc: Wang Huan-B18965; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> shawn.guo@linaro.org
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> I would like to see patch for bindings documentation before I apply this
> one.

Agreed.  I just noticed that this is an old version of the patch (using an
obsoleted property), so please expect a v2 of this patch as well,  besides
the device tree binding document which I think will be named:
./Documentation/devicetree/bindings/net/fsl-etsec2.txt.

Thanks.
Claudiu

[PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Monday, July 13, 2015 4:32 PM
> To: Manoil Claudiu-B08782
> Cc: Wang Huan-B18965; devicetree at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> shawn.guo at linaro.org
> Subject: Re: [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> I would like to see patch for bindings documentation before I apply this
> one.

Agreed.  I just noticed that this is an old version of the patch (using an
obsoleted property), so please expect a v2 of this patch as well,  besides
the device tree binding document which I think will be named:
./Documentation/devicetree/bindings/net/fsl-etsec2.txt.

Thanks.
Claudiu

[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Claudiu Manoil]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.  DT binding documentation updates.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2:
 - register block size is 0x1000 (4kB memory page), not 0x8000;
 - reg property has 2 "address" and resp. 2 "size" cells;
 - remove optional/ obsoleted properties;
 - use register block address as queue-group id for consistency;
 - binding documentation updates for missing vendor properties;


 .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
 arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++
 4 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl-etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@ Properties:
     "rgmii-id", as all other connection types are detected by hardware.
   - fsl,magic-packet : If present, indicates that the hardware supports
     waking up via magic packet.
+  - fsl,wake-on-filer: Indicates that the device can wake up the system
+    by generating a filer interrupt. Depending on the wake-on-lan mode
+    set for this device, the filer interrupt can be triggered by certain
+    user-defined ethernet packets (usually ARP or L2 unicast packets).
   - bd-stash : If present, indicates that the hardware supports stashing
     buffer descriptors in the L2.
   - rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,95 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Claudiu Manoil]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.  DT binding documentation updates.

Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
v2:
 - register block size is 0x1000 (4kB memory page), not 0x8000;
 - reg property has 2 "address" and resp. 2 "size" cells;
 - remove optional/ obsoleted properties;
 - use register block address as queue-group id for consistency;
 - binding documentation updates for missing vendor properties;


 .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
 arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++
 4 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl-etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@ Properties:
     "rgmii-id", as all other connection types are detected by hardware.
   - fsl,magic-packet : If present, indicates that the hardware supports
     waking up via magic packet.
+  - fsl,wake-on-filer: Indicates that the device can wake up the system
+    by generating a filer interrupt. Depending on the wake-on-lan mode
+    set for this device, the filer interrupt can be triggered by certain
+    user-defined ethernet packets (usually ARP or L2 unicast packets).
   - bd-stash : If present, indicates that the hardware supports stashing
     buffer descriptors in the L2.
   - rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,95 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

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[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Claudiu Manoil]

This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.  DT binding documentation updates.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2:
 - register block size is 0x1000 (4kB memory page), not 0x8000;
 - reg property has 2 "address" and resp. 2 "size" cells;
 - remove optional/ obsoleted properties;
 - use register block address as queue-group id for consistency;
 - binding documentation updates for missing vendor properties;


 .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
 arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++
 4 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl-etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@ Properties:
     "rgmii-id", as all other connection types are detected by hardware.
   - fsl,magic-packet : If present, indicates that the hardware supports
     waking up via magic packet.
+  - fsl,wake-on-filer: Indicates that the device can wake up the system
+    by generating a filer interrupt. Depending on the wake-on-lan mode
+    set for this device, the filer interrupt can be triggered by certain
+    user-defined ethernet packets (usually ARP or L2 unicast packets).
   - bd-stash : If present, indicates that the hardware supports stashing
     buffer descriptors in the L2.
   - rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,95 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet at 2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet at 2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet at 2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group at 2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb at 8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil@freescale.com> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

It seems you missed to put Alison in the From field.

You should also put his Signed-off-by tag just before yours.

Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

It seems you missed to put Alison in the From field.

You should also put his Signed-off-by tag just before yours.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil@freescale.com> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

It seems you missed to put Alison in the From field.

You should also put his Signed-off-by tag just before yours.

RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1301 bytes --]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node.  DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
> 
> It seems you missed to put Alison in the From field.
> 
> You should also put his Signed-off-by tag just before yours.

Is this a rule invented by you?  Last time I checked this was a
valid patch format.  Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.

ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node.  DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
> 
> It seems you missed to put Alison in the From field.
> 
> You should also put his Signed-off-by tag just before yours.

Is this a rule invented by you?  Last time I checked this was a
valid patch format.  Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.

[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node.  DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
> 
> It seems you missed to put Alison in the From field.
> 
> You should also put his Signed-off-by tag just before yours.

Is this a rule invented by you?  Last time I checked this was a
valid patch format.  Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.

Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil@freescale.com> wrote:

>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you?  Last time I checked this was a

No, just usual practice.

Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:

>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you?  Last time I checked this was a

No, just usual practice.
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Fabio Estevam]

On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil@freescale.com> wrote:

>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you?  Last time I checked this was a

No, just usual practice.

Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Tue, Jul 14, 2015 at 06:46:17PM +0300, Claudiu Manoil wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>

SoBs should be put together.

> 
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

Please use "ARM: dts: ls1021a: ..." as subject prefix.

> ---
> v2:
>  - register block size is 0x1000 (4kB memory page), not 0x8000;
>  - reg property has 2 "address" and resp. 2 "size" cells;
>  - remove optional/ obsoleted properties;
>  - use register block address as queue-group id for consistency;
>  - binding documentation updates for missing vendor properties;
> 
> 
>  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-

Bindings doc should be a separate patch reviewed by device tree
maintainers.

>  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++

Please separate soc level dts changes from board level changes.

>  4 files changed, 137 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 1e97532..b3291c7 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> @@ -45,7 +45,7 @@ Properties:
>  
>    - device_type : Should be "network"
>    - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
> -  - compatible : Should be "gianfar"
> +  - compatible : "gianfar", "fsl-etsec2"

You meant "fsl,etsec2", which is what I see from dts changes?

>    - reg : Offset and length of the register set for the device
>    - interrupts : For FEC devices, the first interrupt is the device's
>      interrupt.  For TSEC and eTSEC devices, the first interrupt is
> @@ -57,6 +57,10 @@ Properties:
>      "rgmii-id", as all other connection types are detected by hardware.
>    - fsl,magic-packet : If present, indicates that the hardware supports
>      waking up via magic packet.
> +  - fsl,wake-on-filer: Indicates that the device can wake up the system
> +    by generating a filer interrupt. Depending on the wake-on-lan mode
> +    set for this device, the filer interrupt can be triggered by certain
> +    user-defined ethernet packets (usually ARP or L2 unicast packets).
>    - bd-stash : If present, indicates that the hardware supports stashing
>      buffer descriptors in the L2.
>    - rx-stash-len : Denotes the number of bytes of a received buffer to stash
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..f16a061 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -75,6 +75,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi0>;

tbi-handle is undocumented.

> +	phy-handle = <&sgmii_phy1c>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi0>;
> +	phy-handle = <&sgmii_phy1d>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy3>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..4b61766 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -73,6 +73,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy2>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy0>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy1>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..cc48d56 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;
>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,95 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet@2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			fsl,wake-on-filer;
> +			local-mac-address = [ 00 00 00 00 00 00 ];

What is this all zero local-mac-address used for?

Shawn

> +			ranges;
> +
> +			queue-group@2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet@2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet@2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb@8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Shawn Guo]

On Tue, Jul 14, 2015 at 06:46:17PM +0300, Claudiu Manoil wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>

SoBs should be put together.

> 
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

Please use "ARM: dts: ls1021a: ..." as subject prefix.

> ---
> v2:
>  - register block size is 0x1000 (4kB memory page), not 0x8000;
>  - reg property has 2 "address" and resp. 2 "size" cells;
>  - remove optional/ obsoleted properties;
>  - use register block address as queue-group id for consistency;
>  - binding documentation updates for missing vendor properties;
> 
> 
>  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-

Bindings doc should be a separate patch reviewed by device tree
maintainers.

>  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++

Please separate soc level dts changes from board level changes.

>  4 files changed, 137 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 1e97532..b3291c7 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> @@ -45,7 +45,7 @@ Properties:
>  
>    - device_type : Should be "network"
>    - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
> -  - compatible : Should be "gianfar"
> +  - compatible : "gianfar", "fsl-etsec2"

You meant "fsl,etsec2", which is what I see from dts changes?

>    - reg : Offset and length of the register set for the device
>    - interrupts : For FEC devices, the first interrupt is the device's
>      interrupt.  For TSEC and eTSEC devices, the first interrupt is
> @@ -57,6 +57,10 @@ Properties:
>      "rgmii-id", as all other connection types are detected by hardware.
>    - fsl,magic-packet : If present, indicates that the hardware supports
>      waking up via magic packet.
> +  - fsl,wake-on-filer: Indicates that the device can wake up the system
> +    by generating a filer interrupt. Depending on the wake-on-lan mode
> +    set for this device, the filer interrupt can be triggered by certain
> +    user-defined ethernet packets (usually ARP or L2 unicast packets).
>    - bd-stash : If present, indicates that the hardware supports stashing
>      buffer descriptors in the L2.
>    - rx-stash-len : Denotes the number of bytes of a received buffer to stash
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..f16a061 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -75,6 +75,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi0>;

tbi-handle is undocumented.

> +	phy-handle = <&sgmii_phy1c>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi0>;
> +	phy-handle = <&sgmii_phy1d>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy3>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..4b61766 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -73,6 +73,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy2>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy0>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy1>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..cc48d56 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;
>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,95 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet at 2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			fsl,wake-on-filer;
> +			local-mac-address = [ 00 00 00 00 00 00 ];

What is this all zero local-mac-address used for?

Shawn

> +			ranges;
> +
> +			queue-group at 2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet at 2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group at 2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet at 2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group at 2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb at 8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; shawn.guo@linaro.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
[...]
> >
> >  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
> 
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
> 
> >  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                     | 92
> ++++++++++++++++++++++
> 
> Please separate soc level dts changes from board level changes.
> 

Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed.  Thanks.

RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
[...]
> >
> >  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
> 
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
> 
> >  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                     | 92
> ++++++++++++++++++++++
> 
> Please separate soc level dts changes from board level changes.
> 

Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed.  Thanks.
--
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[PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

[Manoil Claudiu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; shawn.guo at linaro.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
[...]
> >
> >  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
> 
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
> 
> >  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                     | 92
> ++++++++++++++++++++++
> 
> Please separate soc level dts changes from board level changes.
> 

Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed.  Thanks.

[PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc

[Claudiu Manoil]

Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
   - fixed typo ("fsl,etsec2" is the correct string);

 Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl,etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
     transmit, the second is receive, and the third is error.
   - phy-handle : See ethernet.txt file in the same directory.
+  - tbi-handle : Handle to a tbi-phy node containing information about
+    the TBIPA register needed to initialize the TBI PHY.  See
+    "TBI Internal MDIO bus", this document.
   - fixed-link : See fixed-link.txt in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory.
     This property is only really needed if the connection is of type
-- 
1.7.11.7

[PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc

[Claudiu Manoil]

Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
   - fixed typo ("fsl,etsec2" is the correct string);

 Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl,etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
     transmit, the second is receive, and the third is error.
   - phy-handle : See ethernet.txt file in the same directory.
+  - tbi-handle : Handle to a tbi-phy node containing information about
+    the TBIPA register needed to initialize the TBI PHY.  See
+    "TBI Internal MDIO bus", this document.
   - fixed-link : See fixed-link.txt in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory.
     This property is only really needed if the connection is of type
-- 
1.7.11.7

[PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc

[Claudiu Manoil]

Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
   - fixed typo ("fsl,etsec2" is the correct string);

 Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl,etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
     transmit, the second is receive, and the third is error.
   - phy-handle : See ethernet.txt file in the same directory.
+  - tbi-handle : Handle to a tbi-phy node containing information about
+    the TBIPA register needed to initialize the TBI PHY.  See
+    "TBI Internal MDIO bus", this document.
   - fixed-link : See fixed-link.txt in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory.
     This property is only really needed if the connection is of type
-- 
1.7.11.7

[PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Claudiu Manoil]

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
    - initial patch split in soc, boards and bindings patches;
    - removed redundant all zero local-mac-address;
    - subject prefix;

 arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,91 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			ranges;
+
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

[PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Claudiu Manoil]

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
    - initial patch split in soc, boards and bindings patches;
    - removed redundant all zero local-mac-address;
    - subject prefix;

 arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,91 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			ranges;
+
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

[PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Claudiu Manoil]

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
    - initial patch split in soc, boards and bindings patches;
    - removed redundant all zero local-mac-address;
    - subject prefix;

 arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,91 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet at 2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			ranges;
+
+			queue-group at 2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet at 2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group at 2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet at 2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			ranges;
+
+			queue-group at 2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group at 2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb at 8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.11.7

[PATCH,v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR

[Claudiu Manoil]

This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;

 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
-- 
1.7.11.7

[PATCH,v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR

[Claudiu Manoil]

This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;

 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
-- 
1.7.11.7

[PATCH, v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR

[Claudiu Manoil]

This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;

 arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
-- 
1.7.11.7

Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Shawn Guo]

On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC.  Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

Applied both with a minor change below.

> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
>     - initial patch split in soc, boards and bindings patches;
>     - removed redundant all zero local-mac-address;
>     - subject prefix;
> 
>  arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 88 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;

I moved these above serial to keep them sort alphabetically.

Shawn

>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,91 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet@2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			ranges;
> +
> +			queue-group@2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet@2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group@2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet@2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group@2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb@8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Shawn Guo]

On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC.  Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
> 
> Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>

Applied both with a minor change below.

> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
>     - initial patch split in soc, boards and bindings patches;
>     - removed redundant all zero local-mac-address;
>     - subject prefix;
> 
>  arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 88 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;

I moved these above serial to keep them sort alphabetically.

Shawn

>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,91 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet@2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			ranges;
> +
> +			queue-group@2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet@2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group@2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet@2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group@2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb@8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
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> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
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[PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes

[Shawn Guo]

On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC.  Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

Applied both with a minor change below.

> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
>     - initial patch split in soc, boards and bindings patches;
>     - removed redundant all zero local-mac-address;
>     - subject prefix;
> 
>  arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 88 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;

I moved these above serial to keep them sort alphabetically.

Shawn

>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,91 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet at 2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			ranges;
> +
> +			queue-group at 2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet at 2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group at 2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet at 2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			ranges;
> +
> +			queue-group at 2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group at 2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb at 8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>