* [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
@ 2015-08-19 5:49 ` Masahiro Yamada
0 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2015-08-19 5:49 UTC (permalink / raw)
To: arm
Cc: Masahiro Yamada, Russell King, devicetree, Kumar Gala,
linux-kernel, Ian Campbell, Rob Herring, Pawel Moll,
Mark Rutland, linux-arm-kernel
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v2:
- Fix git-description
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <1 11 0xf04>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <1 13 0xf04>;
clocks = <&arm_timer_clk>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
@ 2015-08-19 5:49 ` Masahiro Yamada
0 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2015-08-19 5:49 UTC (permalink / raw)
To: arm
Cc: Mark Rutland, devicetree, Russell King, Pawel Moll, Ian Campbell,
linux-kernel, Masahiro Yamada, Rob Herring, Kumar Gala,
linux-arm-kernel
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v2:
- Fix git-description
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <1 11 0xf04>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <1 13 0xf04>;
clocks = <&arm_timer_clk>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
@ 2015-08-19 5:49 ` Masahiro Yamada
0 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2015-08-19 5:49 UTC (permalink / raw)
To: linux-arm-kernel
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v2:
- Fix git-description
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer at 60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <1 11 0xf04>;
clocks = <&arm_timer_clk>;
};
timer at 60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <1 13 0xf04>;
clocks = <&arm_timer_clk>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
2015-08-19 5:49 ` Masahiro Yamada
@ 2015-08-21 1:28 ` Olof Johansson
-1 siblings, 0 replies; 5+ messages in thread
From: Olof Johansson @ 2015-08-21 1:28 UTC (permalink / raw)
To: Masahiro Yamada
Cc: arm, Russell King, devicetree, Kumar Gala, linux-kernel,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
On Wed, Aug 19, 2015 at 02:49:26PM +0900, Masahiro Yamada wrote:
> This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
> document says that the bits[15:8] of the 3rd cell of the interrupts
> property represents PPI interrupt CPU mask. Because the timer
> interrupts are wired to all of the 4 cores, bits[15:8] should be set
> to 0xf.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> Changes in v2:
> - Fix git-description
Thanks, applied.
-Olof
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
@ 2015-08-21 1:28 ` Olof Johansson
0 siblings, 0 replies; 5+ messages in thread
From: Olof Johansson @ 2015-08-21 1:28 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 19, 2015 at 02:49:26PM +0900, Masahiro Yamada wrote:
> This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
> document says that the bits[15:8] of the 3rd cell of the interrupts
> property represents PPI interrupt CPU mask. Because the timer
> interrupts are wired to all of the 4 cores, bits[15:8] should be set
> to 0xf.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> Changes in v2:
> - Fix git-description
Thanks, applied.
-Olof
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-08-21 2:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2015-08-19 5:49 [PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes Masahiro Yamada
2015-08-19 5:49 ` Masahiro Yamada
2015-08-19 5:49 ` Masahiro Yamada
2015-08-21 1:28 ` Olof Johansson
2015-08-21 1:28 ` Olof Johansson
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