[PATCH v5 0/4] Check pixel clock when setting mode

[PATCH v5 0/4] Check pixel clock when setting mode

[Mika Kahola]

From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview

'cvt 2560 1600 60' gives

# 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync

where pixel clock 348.50 MHz is higher than the supported 304 MHz.

The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
CRT, TV, and DP-MST.

V2:
- The maximum DOT clock frequency is added to debugfs i915_frequency_info.
- max dotclock cached in dev_priv structure
- moved computation of max dotclock to 'intel_display.c'

V3:
- intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
- for GEN9 and above the max dotclock frequency is equal to CD clock
  frequency
- for older generations the dot clock frequency is limited to 90% of the
  CD clock frequency
- For Cherryview the dot clock is limited to 95% of CD clock frequency
- for GEN2/3 the maximum dot clock frequency is limited to 90% of the
  2X CD clock frequency as we have on option to use double wide mode
- cleanup

V4:
- renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
  caused changes to all patches in my series even though some of them has
  been r-b'd by Ville
- for consistency the max_pixclk variable is renamed as max_dotclk throughout
  the whole series

V5:
- remaining tweaks for dotclock max frequency computation (HSW and BDW)
  and LVDS, DSI, and DVO fixes based on Ville's comments

Thanks Ville for reviewing the rest of the series!

Mika Kahola (4):
  drm/i915: Store max dotclock
  drm/i915: LVDS pixel clock check
  drm/i915: DSI pixel clock check
  drm/i915: DVO pixel clock check

 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.c     |  3 +++
 drivers/gpu/drm/i915/intel_dvo.c     |  7 +++++++
 drivers/gpu/drm/i915/intel_lvds.c    |  3 +++
 5 files changed, 34 insertions(+)

-- 
1.9.1

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[PATCH v5 1/4] drm/i915: Store max dotclock

[Mika Kahola]

Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.

V2:
- limit the max dot clock frequency to max CD clock frequency
  for the gen9 and above
- limit the max dot clock frequency to 90% of the max CD clock
  frequency for the older gens
- for Cherryview the max dot clock frequency is limited to 95%
  of the max CD clock frequency
- for gen2 and gen3 the max dot clock limit is set to 90% of the
  2X max CD clock frequency

V3:
- max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
- in intel_compute_max_dotclk() the rounding method changed from
  round up to round down when computing max dotclock

V4:
- Haswell and Broadwell supports now dot clocks up to max CD clock
  frequency

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0f3f05..4696685 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1792,6 +1792,7 @@ struct drm_i915_private {
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_boot_cdclk;
 	unsigned int cdclk_freq, max_cdclk_freq;
+	unsigned int max_dotclk_freq;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f604ce1..a0f790d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5271,6 +5271,21 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 			modeset_put_power_domains(dev_priv, put_domains[i]);
 }
 
+static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
+{
+	int max_cdclk_freq = dev_priv->max_cdclk_freq;
+
+	if (INTEL_INFO(dev_priv)->gen >= 9 ||
+	    IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		return max_cdclk_freq;
+	else if (IS_CHERRYVIEW(dev_priv))
+		return max_cdclk_freq*95/100;
+	else if (INTEL_INFO(dev_priv)->gen < 4)
+		return 2*max_cdclk_freq*90/100;
+	else
+		return max_cdclk_freq*90/100;
+}
+
 static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5310,8 +5325,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
 	}
 
+	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
+
 	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
 			 dev_priv->max_cdclk_freq);
+
+	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
+			 dev_priv->max_dotclk_freq);
 }
 
 static void intel_update_cdclk(struct drm_device *dev)
-- 
1.9.1

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[PATCH v5 2/4] drm/i915: LVDS pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to LVDS.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- moved supported dotclock check from mode_valid() to intel_lvds_init()

V5:
- dotclock check moved back to mode_valid() function
- dotclock check for fixed mode

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 881b5d1..0794dc8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -289,11 +289,14 @@ intel_lvds_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->hdisplay > fixed_mode->hdisplay)
 		return MODE_PANEL;
 	if (mode->vdisplay > fixed_mode->vdisplay)
 		return MODE_PANEL;
+	if (fixed_mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
 }
-- 
1.9.1

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[PATCH v5 3/4] drm/i915: DSI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DSI.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk
- moved dot clock checking inside 'if (fixed_mode)'

V5:
- dot clock checked against fixed_mode clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4a601cf..781c267 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -667,6 +668,8 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 		if (mode->vdisplay > fixed_mode->vdisplay)
 			return MODE_PANEL;
+		if (fixed_mode->clock > max_dotclk)
+			return MODE_CLOCK_HIGH;
 	}
 
 	return MODE_OK;
-- 
1.9.1

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[PATCH v5 4/4] drm/i915: DVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- clock check against max dotclock moved inside 'if (fixed_mode)'

V5:
- dot clock check against fixed_mode clock when available

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index dc532bb..c80fe1f 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -201,6 +201,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+	int target_clock = mode->clock;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -212,8 +214,13 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
 			return MODE_PANEL;
+
+		target_clock = intel_dvo->panel_fixed_mode->clock;
 	}
 
+	if (target_clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
 }
 
-- 
1.9.1

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Re: [PATCH v5 1/4] drm/i915: Store max dotclock

[Ville Syrjälä]

On Tue, Aug 18, 2015 at 02:36:59PM +0300, Mika Kahola wrote:
> Store max dotclock into dev_priv structure so we are able
> to filter out the modes that are not supported by our
> platforms.
> 
> V2:
> - limit the max dot clock frequency to max CD clock frequency
>   for the gen9 and above
> - limit the max dot clock frequency to 90% of the max CD clock
>   frequency for the older gens
> - for Cherryview the max dot clock frequency is limited to 95%
>   of the max CD clock frequency
> - for gen2 and gen3 the max dot clock limit is set to 90% of the
>   2X max CD clock frequency
> 
> V3:
> - max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
> - in intel_compute_max_dotclk() the rounding method changed from
>   round up to round down when computing max dotclock
> 
> V4:
> - Haswell and Broadwell supports now dot clocks up to max CD clock
>   frequency
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e0f3f05..4696685 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1792,6 +1792,7 @@ struct drm_i915_private {
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
>  	unsigned int skl_boot_cdclk;
>  	unsigned int cdclk_freq, max_cdclk_freq;
> +	unsigned int max_dotclk_freq;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f604ce1..a0f790d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5271,6 +5271,21 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  			modeset_put_power_domains(dev_priv, put_domains[i]);
>  }
>  
> +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> +{
> +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> +
> +	if (INTEL_INFO(dev_priv)->gen >= 9 ||
> +	    IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +		return max_cdclk_freq;
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		return max_cdclk_freq*95/100;
> +	else if (INTEL_INFO(dev_priv)->gen < 4)
> +		return 2*max_cdclk_freq*90/100;
> +	else
> +		return max_cdclk_freq*90/100;
> +}
> +
>  static void intel_update_max_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5310,8 +5325,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
>  	}
>  
> +	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
> +
>  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
>  			 dev_priv->max_cdclk_freq);
> +
> +	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
> +			 dev_priv->max_dotclk_freq);
>  }
>  
>  static void intel_update_cdclk(struct drm_device *dev)
> -- 
> 1.9.1
> 
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v5 2/4] drm/i915: LVDS pixel clock check

[Ville Syrjälä]

On Tue, Aug 18, 2015 at 02:37:00PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to LVDS.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - moved supported dotclock check from mode_valid() to intel_lvds_init()
> 
> V5:
> - dotclock check moved back to mode_valid() function
> - dotclock check for fixed mode
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_lvds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 881b5d1..0794dc8 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -289,11 +289,14 @@ intel_lvds_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
>  
>  	if (mode->hdisplay > fixed_mode->hdisplay)
>  		return MODE_PANEL;
>  	if (mode->vdisplay > fixed_mode->vdisplay)
>  		return MODE_PANEL;
> +	if (fixed_mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
>  
>  	return MODE_OK;
>  }
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v5 3/4] drm/i915: DSI pixel clock check

[Ville Syrjälä]

On Tue, Aug 18, 2015 at 02:37:01PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DSI.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - max_pixclk variable renamed as max_dotclk
> - moved dot clock checking inside 'if (fixed_mode)'
> 
> V5:
> - dot clock checked against fixed_mode clock
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4a601cf..781c267 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> @@ -667,6 +668,8 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  		if (mode->vdisplay > fixed_mode->vdisplay)
>  			return MODE_PANEL;
> +		if (fixed_mode->clock > max_dotclk)
> +			return MODE_CLOCK_HIGH;
>  	}
>  
>  	return MODE_OK;
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v5 4/4] drm/i915: DVO pixel clock check

[Ville Syrjälä]

On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DVO.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - clock check against max dotclock moved inside 'if (fixed_mode)'
> 
> V5:
> - dot clock check against fixed_mode clock when available
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dvo.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index dc532bb..c80fe1f 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -201,6 +201,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
>  {
>  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> +	int target_clock = mode->clock;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -212,8 +214,13 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
>  			return MODE_PANEL;
> +
> +		target_clock = intel_dvo->panel_fixed_mode->clock;
>  	}
>  
> +	if (target_clock > max_dotclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
>  }
>  
> -- 
> 1.9.1
> 
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Re: [PATCH v5 4/4] drm/i915: DVO pixel clock check

[Mika Kahola]

On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote:
> On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to DVO.
> > 
> > V2:
> > - removed computation for max pixel clock
> > 
> > V3:
> > - cleanup by removing unnecessary lines
> > 
> > V4:
> > - clock check against max dotclock moved inside 'if (fixed_mode)'
> > 
> > V5:
> > - dot clock check against fixed_mode clock when available
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
Thanks Ville for the reviews!

-Mika-

> > ---
> >  drivers/gpu/drm/i915/intel_dvo.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> > index dc532bb..c80fe1f 100644
> > --- a/drivers/gpu/drm/i915/intel_dvo.c
> > +++ b/drivers/gpu/drm/i915/intel_dvo.c
> > @@ -201,6 +201,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
> >  		     struct drm_display_mode *mode)
> >  {
> >  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> > +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > +	int target_clock = mode->clock;
> >  
> >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> >  		return MODE_NO_DBLESCAN;
> > @@ -212,8 +214,13 @@ intel_dvo_mode_valid(struct drm_connector *connector,
> >  			return MODE_PANEL;
> >  		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
> >  			return MODE_PANEL;
> > +
> > +		target_clock = intel_dvo->panel_fixed_mode->clock;
> >  	}
> >  
> > +	if (target_clock > max_dotclk)
> > +		return MODE_CLOCK_HIGH;
> > +
> >  	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH v5 4/4] drm/i915: DVO pixel clock check

[Daniel Vetter]

On Fri, Aug 21, 2015 at 02:52:54PM +0300, Mika Kahola wrote:
> On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> > > It is possible the we request to have a mode that has
> > > higher pixel clock than our HW can support. This patch
> > > checks if requested pixel clock is lower than the one
> > > supported by the HW. The requested mode is discarded
> > > if we cannot support the requested pixel clock.
> > > 
> > > This patch applies to DVO.
> > > 
> > > V2:
> > > - removed computation for max pixel clock
> > > 
> > > V3:
> > > - cleanup by removing unnecessary lines
> > > 
> > > V4:
> > > - clock check against max dotclock moved inside 'if (fixed_mode)'
> > > 
> > > V5:
> > > - dot clock check against fixed_mode clock when available
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> Thanks Ville for the reviews!

Merged entire series, thanks.
-Daniel

> 
> -Mika-
> 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dvo.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> > > index dc532bb..c80fe1f 100644
> > > --- a/drivers/gpu/drm/i915/intel_dvo.c
> > > +++ b/drivers/gpu/drm/i915/intel_dvo.c
> > > @@ -201,6 +201,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
> > >  		     struct drm_display_mode *mode)
> > >  {
> > >  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> > > +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > > +	int target_clock = mode->clock;
> > >  
> > >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > >  		return MODE_NO_DBLESCAN;
> > > @@ -212,8 +214,13 @@ intel_dvo_mode_valid(struct drm_connector *connector,
> > >  			return MODE_PANEL;
> > >  		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
> > >  			return MODE_PANEL;
> > > +
> > > +		target_clock = intel_dvo->panel_fixed_mode->clock;
> > >  	}
> > >  
> > > +	if (target_clock > max_dotclk)
> > > +		return MODE_CLOCK_HIGH;
> > > +
> > >  	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
> > >  }
> > >  
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v5 4/4] drm/i915: DVO pixel clock check

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 7228
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                 -1              302/302              301/302
SNB                                  315/315              315/315
IVB                                  336/336              336/336
BYT                                  283/283              283/283
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt@kms_flip@wf_vblank-vs-modeset-interruptible      PASS(1)      DMESG_WARN(1)
Note: You need to pay more attention to line start with '*'
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