* [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init
@ 2015-08-31 1:18 Simon Glass
2015-08-31 1:18 ` [U-Boot] [PATCH 01/45] arm: Remove balloon3 board Simon Glass
` (45 more replies)
0 siblings, 46 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
The follow boards have still not been moved to use CONFIG_SYS_GENERIC_BOARD.
This series removes these boards in preparation for dropping the old board
init file arch/arm/lib/board.c:
https://patchwork.ozlabs.org/patch/508559/
balloon3, cpu9260, cpu9260_128M, cpu9260_nand, cpu9260_nand_128M, cpu9G20,
cpu9G20_128M, cpu9G20_nand, cpu9G20_nand_128M, cpuat91, cpuat91_ram, d2net_v2,
da830evm, davinci_dm355evm, davinci_dm355leopard, davinci_dm365evm,
davinci_dm6467evm, davinci_dm6467Tevm, davinci_dvevm, davinci_schmoogie,
davinci_sffsdr, davinci_sonata, dig297, ea20, eb_cpux9k2, eb_cpux9k2_ram,
edb9315a, enbw_cmc, ima3-mx53, imx27lite, imx31_litekit, inetspace_v2, jornada,
lp8x4x, magnesium, meesc, meesc_dataflash, mv88f6281gtw_ge, mx51_efikamx,
mx51_efikasb, net2big_v2, netspace_lite_v2, netspace_max_v2, netspace_mini_v2,
netspace_v2, nhk8815, nhk8815_onenand, omap3_evm, omap3_evm_quick_mmc,
omap3_evm_quick_nand, omap3_logic, omap3_mvblx, omap3_sdp3430, openrd_base,
openrd_client, openrd_ultimate, otc570, otc570_dataflash, palmld, palmtc,
palmtreo680, polaris, portuxg20, pxa255_idp, qong, rd6281a, scb9328, snowball,
stamp9g20, ti814x_evm, ti816x_evm, tk71, trizepsiv, tt01, tx25, u8500_href,
versatileab, versatilepb, versatileqemu, vision2, vl_ma2sc, vl_ma2sc_ram,
vpac270_nor_128, vpac270_nor_256, vpac270_ond_256, wireless_space, xaeniax,
zipitz2
Simon Glass (45):
arm: Remove balloon3 board
arm: Remove eukrea boards
arm: Remove most LaCie boards
arm: Remove snowball and u8500_href boards
arm: Remove unmaintained davinci boards
arm: Remove d2net_v2 defconfig file
arm: Remove dig297 board
arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards
arm: Remove edb9315a board
arm: Remove enbw_cmc board
arm: Remove ima3-mx53 board
arm: Remove imx27lite, imx27_litekit and magnesium boards
arm: Remove mx31_litekit board
arm: Remove inetspace_v2_cmc board
arm: Remove jornada board
arm: Remove lp8x4x board
arm: Remove meesc and meesc_dataflash boards
arm: Remove mv88f6281gtw_ge board
arm: Remove mx51_efikamx, mx51_efikasb boards
arm: Remove nhk8815 boards and nomadik arch
arm: Remove omap3_logic board
arm: Remove omap3_mvblx board
arm: Remove omap3_sdp3430 board
arm: Remove openrd boards
arm: Remove otc570 board
arm: Remove palmld board
arm: Remove palmtc board
arm: Remove polaris and trizepsiv boards
arm: Remove portuxg20, stamp9g20 boards
arm: Remove pxa255_idp, zipitz2 boards
arm: Remove qong board
arm: Remove rd6281a board
arm: Remove scb9328 board
arm: Remove tk71 board
arm: Remove tt01 board
arm: Remove versatileab board
arm: Remove vision2 board
arm: Remove vl_ma2sc board
arm: Remove vpac270_nor_128 board
arm: Remove xaeniax board
arm: Remove omap3_evm board
arm: Remove palmtreo680 board
arm: Remove ti814x_evm board
arm: Remove ti816x_evm board
arm: Remove tx25 board
arch/arm/Kconfig | 148 +---
arch/arm/Makefile | 1 -
arch/arm/cpu/armv7/omap3/Kconfig | 29 -
arch/arm/include/asm/mach-types.h | 76 --
arch/arm/mach-at91/Kconfig | 35 -
arch/arm/mach-davinci/Kconfig | 40 --
arch/arm/mach-kirkwood/Kconfig | 28 -
arch/arm/mach-nomadik/Kconfig | 17 -
arch/arm/mach-nomadik/Makefile | 9 -
arch/arm/mach-nomadik/gpio.c | 83 ---
arch/arm/mach-nomadik/include/mach/gpio.h | 26 -
arch/arm/mach-nomadik/include/mach/mtu.h | 50 --
arch/arm/mach-nomadik/reset.S | 14 -
arch/arm/mach-nomadik/timer.c | 71 --
arch/arm/mach-versatile/Kconfig | 15 -
board/BuS/eb_cpux9k2/Kconfig | 12 -
board/BuS/eb_cpux9k2/MAINTAINERS | 7 -
board/BuS/eb_cpux9k2/Makefile | 8 -
board/BuS/eb_cpux9k2/cpux9k2.c | 373 ----------
board/BuS/vl_ma2sc/Kconfig | 12 -
board/BuS/vl_ma2sc/MAINTAINERS | 7 -
board/BuS/vl_ma2sc/Makefile | 12 -
board/BuS/vl_ma2sc/vl_ma2sc.c | 519 --------------
board/LaCie/net2big_v2/Kconfig | 12 -
board/LaCie/net2big_v2/MAINTAINERS | 11 -
board/LaCie/net2big_v2/Makefile | 15 -
board/LaCie/net2big_v2/kwbimage.cfg | 151 ----
board/LaCie/net2big_v2/net2big_v2.c | 253 -------
board/LaCie/net2big_v2/net2big_v2.h | 29 -
board/LaCie/netspace_v2/Kconfig | 12 -
board/LaCie/netspace_v2/MAINTAINERS | 14 -
board/LaCie/netspace_v2/Makefile | 12 -
board/LaCie/netspace_v2/kwbimage-is2.cfg | 151 ----
board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 151 ----
board/LaCie/netspace_v2/kwbimage.cfg | 151 ----
board/LaCie/netspace_v2/netspace_v2.c | 117 ----
board/LaCie/netspace_v2/netspace_v2.h | 23 -
board/LaCie/wireless_space/Kconfig | 12 -
board/LaCie/wireless_space/MAINTAINERS | 6 -
board/LaCie/wireless_space/Makefile | 12 -
board/LaCie/wireless_space/kwbimage.cfg | 71 --
board/LaCie/wireless_space/wireless_space.c | 165 -----
board/Marvell/mv88f6281gtw_ge/Kconfig | 12 -
board/Marvell/mv88f6281gtw_ge/MAINTAINERS | 6 -
board/Marvell/mv88f6281gtw_ge/Makefile | 9 -
board/Marvell/mv88f6281gtw_ge/kwbimage.cfg | 149 ----
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 119 ----
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h | 20 -
board/Marvell/openrd/Kconfig | 12 -
board/Marvell/openrd/MAINTAINERS | 12 -
board/Marvell/openrd/Makefile | 14 -
board/Marvell/openrd/kwbimage.cfg | 152 ----
board/Marvell/openrd/openrd.c | 161 -----
board/Marvell/openrd/openrd.h | 30 -
board/Marvell/rd6281a/Kconfig | 12 -
board/Marvell/rd6281a/MAINTAINERS | 6 -
board/Marvell/rd6281a/Makefile | 9 -
board/Marvell/rd6281a/kwbimage.cfg | 151 ----
board/Marvell/rd6281a/rd6281a.c | 157 -----
board/Marvell/rd6281a/rd6281a.h | 25 -
board/armltd/versatile/MAINTAINERS | 8 -
board/armltd/versatile/Makefile | 9 -
board/armltd/versatile/lowlevel_init.S | 17 -
board/armltd/versatile/versatile.c | 99 ---
board/balloon3/Kconfig | 9 -
board/balloon3/MAINTAINERS | 6 -
board/balloon3/Makefile | 9 -
board/balloon3/balloon3.c | 221 ------
board/cirrus/edb93xx/Kconfig | 15 -
board/cirrus/edb93xx/MAINTAINERS | 6 -
board/cirrus/edb93xx/Makefile | 11 -
board/cirrus/edb93xx/edb93xx.c | 382 ----------
board/cirrus/edb93xx/u-boot.lds | 116 ---
board/comelit/dig297/Kconfig | 12 -
board/comelit/dig297/MAINTAINERS | 6 -
board/comelit/dig297/Makefile | 8 -
board/comelit/dig297/dig297.c | 182 -----
board/comelit/dig297/dig297.h | 367 ----------
board/davedenx/qong/Kconfig | 15 -
board/davedenx/qong/MAINTAINERS | 6 -
board/davedenx/qong/Makefile | 11 -
board/davedenx/qong/fpga.c | 77 --
board/davedenx/qong/lowlevel_init.S | 223 ------
board/davedenx/qong/qong.c | 259 -------
board/davedenx/qong/qong_fpga.h | 23 -
board/davinci/dm355evm/Kconfig | 12 -
board/davinci/dm355evm/MAINTAINERS | 6 -
board/davinci/dm355evm/Makefile | 10 -
board/davinci/dm355evm/config.mk | 11 -
board/davinci/dm355evm/dm355evm.c | 144 ----
board/davinci/dm355leopard/Kconfig | 12 -
board/davinci/dm355leopard/MAINTAINERS | 6 -
board/davinci/dm355leopard/Makefile | 10 -
board/davinci/dm355leopard/config.mk | 6 -
board/davinci/dm355leopard/dm355leopard.c | 86 ---
board/davinci/dm365evm/Kconfig | 12 -
board/davinci/dm365evm/MAINTAINERS | 6 -
board/davinci/dm365evm/Makefile | 10 -
board/davinci/dm365evm/config.mk | 11 -
board/davinci/dm365evm/dm365evm.c | 139 ----
board/davinci/dm6467evm/Kconfig | 12 -
board/davinci/dm6467evm/MAINTAINERS | 7 -
board/davinci/dm6467evm/Makefile | 10 -
board/davinci/dm6467evm/config.mk | 2 -
board/davinci/dm6467evm/dm6467evm.c | 76 --
board/davinci/dvevm/Kconfig | 12 -
board/davinci/dvevm/MAINTAINERS | 6 -
board/davinci/dvevm/Makefile | 11 -
board/davinci/dvevm/board_init.S | 16 -
board/davinci/dvevm/config.mk | 39 --
board/davinci/dvevm/dvevm.c | 91 ---
board/davinci/ea20/Kconfig | 12 -
board/davinci/ea20/MAINTAINERS | 6 -
board/davinci/ea20/Makefile | 10 -
board/davinci/ea20/ea20.c | 339 ---------
board/davinci/schmoogie/Kconfig | 12 -
board/davinci/schmoogie/MAINTAINERS | 6 -
board/davinci/schmoogie/Makefile | 11 -
board/davinci/schmoogie/board_init.S | 16 -
board/davinci/schmoogie/config.mk | 39 --
board/davinci/schmoogie/schmoogie.c | 119 ----
board/davinci/sffsdr/Kconfig | 12 -
board/davinci/sffsdr/MAINTAINERS | 6 -
board/davinci/sffsdr/Makefile | 11 -
board/davinci/sffsdr/board_init.S | 16 -
board/davinci/sffsdr/config.mk | 23 -
board/davinci/sffsdr/sffsdr.c | 132 ----
board/davinci/sonata/Kconfig | 12 -
board/davinci/sonata/MAINTAINERS | 6 -
board/davinci/sonata/Makefile | 11 -
board/davinci/sonata/board_init.S | 87 ---
board/davinci/sonata/config.mk | 39 --
board/davinci/sonata/sonata.c | 87 ---
board/enbw/enbw_cmc/Kconfig | 12 -
board/enbw/enbw_cmc/MAINTAINERS | 6 -
board/enbw/enbw_cmc/Makefile | 10 -
board/enbw/enbw_cmc/enbw_cmc.c | 893 ------------------------
board/esd/meesc/Kconfig | 12 -
board/esd/meesc/MAINTAINERS | 7 -
board/esd/meesc/Makefile | 13 -
board/esd/meesc/meesc.c | 271 -------
board/esd/meesc/partition.c | 23 -
board/esd/otc570/Kconfig | 12 -
board/esd/otc570/MAINTAINERS | 7 -
board/esd/otc570/Makefile | 13 -
board/esd/otc570/otc570.c | 372 ----------
board/esd/otc570/partition.c | 23 -
board/esg/ima3-mx53/Kconfig | 15 -
board/esg/ima3-mx53/MAINTAINERS | 6 -
board/esg/ima3-mx53/Makefile | 9 -
board/esg/ima3-mx53/ima3-mx53.c | 206 ------
board/esg/ima3-mx53/imximage.cfg | 104 ---
board/eukrea/cpu9260/Kconfig | 12 -
board/eukrea/cpu9260/MAINTAINERS | 13 -
board/eukrea/cpu9260/Makefile | 17 -
board/eukrea/cpu9260/cpu9260.c | 158 -----
board/eukrea/cpu9260/led.c | 139 ----
board/eukrea/cpuat91/Kconfig | 12 -
board/eukrea/cpuat91/MAINTAINERS | 7 -
board/eukrea/cpuat91/Makefile | 8 -
board/eukrea/cpuat91/cpuat91.c | 75 --
board/genesi/mx51_efikamx/Kconfig | 15 -
board/genesi/mx51_efikamx/MAINTAINERS | 7 -
board/genesi/mx51_efikamx/Makefile | 13 -
board/genesi/mx51_efikamx/efikamx-usb.c | 230 ------
board/genesi/mx51_efikamx/efikamx.c | 509 --------------
board/genesi/mx51_efikamx/imximage_mx.cfg | 118 ----
board/genesi/mx51_efikamx/imximage_sb.cfg | 101 ---
board/hale/tt01/Kconfig | 15 -
board/hale/tt01/MAINTAINERS | 6 -
board/hale/tt01/Makefile | 10 -
board/hale/tt01/lowlevel_init.S | 16 -
board/hale/tt01/tt01.c | 243 -------
board/icpdas/lp8x4x/Kconfig | 12 -
board/icpdas/lp8x4x/MAINTAINERS | 6 -
board/icpdas/lp8x4x/Makefile | 9 -
board/icpdas/lp8x4x/lp8x4x.c | 128 ----
board/jornada/Kconfig | 9 -
board/jornada/MAINTAINERS | 6 -
board/jornada/Makefile | 11 -
board/jornada/jornada.c | 44 --
board/jornada/setup.S | 194 -----
board/karo/tk71/Kconfig | 12 -
board/karo/tk71/MAINTAINERS | 6 -
board/karo/tk71/Makefile | 9 -
board/karo/tk71/kwbimage.cfg | 158 -----
board/karo/tk71/tk71.c | 150 ----
board/karo/tx25/Kconfig | 15 -
board/karo/tx25/MAINTAINERS | 6 -
board/karo/tx25/Makefile | 11 -
board/karo/tx25/lowlevel_init.S | 98 ---
board/karo/tx25/tx25.c | 210 ------
board/logicpd/imx27lite/Kconfig | 31 -
board/logicpd/imx27lite/MAINTAINERS | 12 -
board/logicpd/imx27lite/Makefile | 9 -
board/logicpd/imx27lite/imx27lite.c | 77 --
board/logicpd/imx27lite/lowlevel_init.S | 156 -----
board/logicpd/imx31_litekit/Kconfig | 15 -
board/logicpd/imx31_litekit/MAINTAINERS | 6 -
board/logicpd/imx31_litekit/Makefile | 9 -
board/logicpd/imx31_litekit/imx31_litekit.c | 91 ---
board/logicpd/imx31_litekit/lowlevel_init.S | 87 ---
board/logicpd/omap3som/Kconfig | 12 -
board/logicpd/omap3som/MAINTAINERS | 6 -
board/logicpd/omap3som/Makefile | 8 -
board/logicpd/omap3som/omap3logic.c | 242 -------
board/logicpd/omap3som/omap3logic.h | 31 -
board/matrix_vision/mvblx/Kconfig | 12 -
board/matrix_vision/mvblx/MAINTAINERS | 6 -
board/matrix_vision/mvblx/Makefile | 11 -
board/matrix_vision/mvblx/config.mk | 17 -
board/matrix_vision/mvblx/fpga.c | 214 ------
board/matrix_vision/mvblx/fpga.h | 15 -
board/matrix_vision/mvblx/mvblx.c | 159 -----
board/matrix_vision/mvblx/mvblx.h | 346 ---------
board/matrix_vision/mvblx/sys_eeprom.c | 403 -----------
board/palmld/Kconfig | 9 -
board/palmld/MAINTAINERS | 6 -
board/palmld/Makefile | 9 -
board/palmld/palmld.c | 61 --
board/palmtc/Kconfig | 9 -
board/palmtc/MAINTAINERS | 6 -
board/palmtc/Makefile | 9 -
board/palmtc/palmtc.c | 61 --
board/palmtreo680/Kconfig | 9 -
board/palmtreo680/MAINTAINERS | 6 -
board/palmtreo680/Makefile | 9 -
board/palmtreo680/README | 563 ---------------
board/palmtreo680/palmtreo680.c | 148 ----
board/pxa255_idp/Kconfig | 9 -
board/pxa255_idp/MAINTAINERS | 6 -
board/pxa255_idp/Makefile | 8 -
board/pxa255_idp/README | 11 -
board/pxa255_idp/idp_notes.txt | 46 --
board/pxa255_idp/pxa_idp.c | 140 ----
board/pxa255_idp/pxa_reg_calcs.out | 119 ----
board/pxa255_idp/pxa_reg_calcs.py | 298 --------
board/quipos/cairo/cairo.c | 12 -
board/scb9328/Kconfig | 12 -
board/scb9328/MAINTAINERS | 6 -
board/scb9328/Makefile | 9 -
board/scb9328/flash.c | 310 --------
board/scb9328/intel.h | 78 ---
board/scb9328/lowlevel_init.S | 188 -----
board/scb9328/scb9328.c | 54 --
board/st-ericsson/snowball/Kconfig | 15 -
board/st-ericsson/snowball/MAINTAINERS | 6 -
board/st-ericsson/snowball/Makefile | 9 -
board/st-ericsson/snowball/db8500_pins.h | 745 --------------------
board/st-ericsson/snowball/snowball.c | 340 ---------
board/st-ericsson/u8500/Kconfig | 15 -
board/st-ericsson/u8500/MAINTAINERS | 6 -
board/st-ericsson/u8500/Makefile | 9 -
board/st-ericsson/u8500/gpio.c | 331 ---------
board/st-ericsson/u8500/u8500_href.c | 477 -------------
board/st/nhk8815/Kconfig | 12 -
board/st/nhk8815/MAINTAINERS | 8 -
board/st/nhk8815/Makefile | 12 -
board/st/nhk8815/README.nhk8815 | 32 -
board/st/nhk8815/nhk8815.c | 92 ---
board/taskit/stamp9g20/Kconfig | 12 -
board/taskit/stamp9g20/MAINTAINERS | 7 -
board/taskit/stamp9g20/Makefile | 17 -
board/taskit/stamp9g20/led.c | 122 ----
board/taskit/stamp9g20/stamp9g20.c | 159 -----
board/ti/evm/Kconfig | 38 -
board/ti/evm/MAINTAINERS | 10 -
board/ti/evm/Makefile | 8 -
board/ti/evm/evm.c | 274 --------
board/ti/evm/evm.h | 394 -----------
board/ti/sdp3430/Kconfig | 12 -
board/ti/sdp3430/MAINTAINERS | 6 -
board/ti/sdp3430/Makefile | 8 -
board/ti/sdp3430/config.mk | 17 -
board/ti/sdp3430/sdp.c | 203 ------
board/ti/sdp3430/sdp.h | 401 -----------
board/ti/ti814x/Kconfig | 15 -
board/ti/ti814x/MAINTAINERS | 6 -
board/ti/ti814x/Makefile | 13 -
board/ti/ti814x/evm.c | 188 -----
board/ti/ti814x/evm.h | 8 -
board/ti/ti814x/mux.c | 86 ---
board/ti/ti816x/Kconfig | 15 -
board/ti/ti816x/MAINTAINERS | 6 -
board/ti/ti816x/Makefile | 12 -
board/ti/ti816x/evm.c | 216 ------
board/trizepsiv/Kconfig | 9 -
board/trizepsiv/MAINTAINERS | 7 -
board/trizepsiv/Makefile | 8 -
board/trizepsiv/conxs.c | 148 ----
board/trizepsiv/eeprom.c | 62 --
board/ttcontrol/vision2/Kconfig | 15 -
board/ttcontrol/vision2/MAINTAINERS | 6 -
board/ttcontrol/vision2/Makefile | 9 -
board/ttcontrol/vision2/imximage_hynix.cfg | 212 ------
board/ttcontrol/vision2/vision2.c | 572 ---------------
board/vpac270/Kconfig | 9 -
board/vpac270/MAINTAINERS | 8 -
board/vpac270/Makefile | 13 -
board/vpac270/onenand.c | 46 --
board/vpac270/u-boot-spl.lds | 81 ---
board/vpac270/vpac270.c | 126 ----
board/xaeniax/Kconfig | 9 -
board/xaeniax/MAINTAINERS | 6 -
board/xaeniax/Makefile | 8 -
board/xaeniax/flash.c | 412 -----------
board/xaeniax/xaeniax.c | 69 --
board/zipitz2/Kconfig | 9 -
board/zipitz2/MAINTAINERS | 6 -
board/zipitz2/Makefile | 10 -
board/zipitz2/zipitz2.c | 202 ------
configs/balloon3_defconfig | 6 -
configs/cpu9260_128M_defconfig | 11 -
configs/cpu9260_defconfig | 11 -
configs/cpu9260_nand_128M_defconfig | 11 -
configs/cpu9260_nand_defconfig | 11 -
configs/cpu9G20_128M_defconfig | 11 -
configs/cpu9G20_defconfig | 11 -
configs/cpu9G20_nand_128M_defconfig | 11 -
configs/cpu9G20_nand_defconfig | 11 -
configs/cpuat91_defconfig | 13 -
configs/cpuat91_ram_defconfig | 13 -
configs/d2net_v2_defconfig | 8 -
configs/davinci_dm355evm_defconfig | 9 -
configs/davinci_dm355leopard_defconfig | 9 -
configs/davinci_dm365evm_defconfig | 9 -
configs/davinci_dm6467Tevm_defconfig | 9 -
configs/davinci_dm6467evm_defconfig | 10 -
configs/davinci_dvevm_defconfig | 9 -
configs/davinci_schmoogie_defconfig | 9 -
configs/davinci_sffsdr_defconfig | 9 -
configs/davinci_sonata_defconfig | 7 -
configs/dig297_defconfig | 10 -
configs/ea20_defconfig | 8 -
configs/eb_cpux9k2_defconfig | 5 -
configs/eb_cpux9k2_ram_defconfig | 5 -
configs/edb9315a_defconfig | 6 -
configs/enbw_cmc_defconfig | 5 -
configs/ima3-mx53_defconfig | 6 -
configs/imx27lite_defconfig | 3 -
configs/imx31_litekit_defconfig | 4 -
configs/inetspace_v2_defconfig | 8 -
configs/jornada_defconfig | 9 -
configs/lp8x4x_defconfig | 4 -
configs/magnesium_defconfig | 3 -
configs/meesc_dataflash_defconfig | 9 -
configs/meesc_defconfig | 9 -
configs/mv88f6281gtw_ge_defconfig | 7 -
configs/mx51_efikamx_defconfig | 7 -
configs/mx51_efikasb_defconfig | 6 -
configs/net2big_v2_defconfig | 8 -
configs/netspace_lite_v2_defconfig | 8 -
configs/netspace_max_v2_defconfig | 8 -
configs/netspace_mini_v2_defconfig | 8 -
configs/netspace_v2_defconfig | 8 -
configs/nhk8815_defconfig | 7 -
configs/nhk8815_onenand_defconfig | 7 -
configs/omap3_evm_defconfig | 10 -
configs/omap3_evm_quick_mmc_defconfig | 26 -
configs/omap3_evm_quick_nand_defconfig | 26 -
configs/omap3_logic_defconfig | 8 -
configs/omap3_mvblx_defconfig | 9 -
configs/omap3_sdp3430_defconfig | 7 -
configs/openrd_base_defconfig | 7 -
configs/openrd_client_defconfig | 7 -
configs/openrd_ultimate_defconfig | 7 -
configs/otc570_dataflash_defconfig | 8 -
configs/otc570_defconfig | 8 -
configs/palmld_defconfig | 7 -
configs/palmtc_defconfig | 6 -
configs/palmtreo680_defconfig | 12 -
configs/polaris_defconfig | 4 -
configs/portuxg20_defconfig | 10 -
configs/pxa255_idp_defconfig | 3 -
configs/qong_defconfig | 2 -
configs/rd6281a_defconfig | 6 -
configs/scb9328_defconfig | 7 -
configs/snowball_defconfig | 13 -
configs/stamp9g20_defconfig | 11 -
configs/ti814x_evm_defconfig | 7 -
configs/ti816x_evm_defconfig | 7 -
configs/tk71_defconfig | 6 -
configs/trizepsiv_defconfig | 3 -
configs/tt01_defconfig | 4 -
configs/tx25_defconfig | 6 -
configs/u8500_href_defconfig | 13 -
configs/versatileab_defconfig | 18 -
configs/versatilepb_defconfig | 18 -
configs/versatileqemu_defconfig | 18 -
configs/vision2_defconfig | 7 -
configs/vl_ma2sc_defconfig | 9 -
configs/vl_ma2sc_ram_defconfig | 9 -
configs/vpac270_nor_128_defconfig | 6 -
configs/vpac270_nor_256_defconfig | 6 -
configs/vpac270_ond_256_defconfig | 8 -
configs/wireless_space_defconfig | 7 -
configs/xaeniax_defconfig | 3 -
configs/zipitz2_defconfig | 7 -
doc/README.omap3 | 9 -
doc/README.switch_config | 25 -
doc/README.watchdog | 1 +
drivers/mtd/nand/Makefile | 1 -
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drivers/net/smc91111.c | 51 +-
drivers/net/smc91111.h | 22 -
drivers/usb/musb/omap3.c | 4 -
drivers/usb/musb/omap3.h | 4 -
include/configs/balloon3.h | 242 -------
include/configs/cpu9260.h | 485 -------------
include/configs/cpuat91.h | 222 ------
include/configs/davinci_dm355evm.h | 195 ------
include/configs/davinci_dm355leopard.h | 140 ----
include/configs/davinci_dm365evm.h | 220 ------
include/configs/davinci_dm6467evm.h | 138 ----
include/configs/davinci_dvevm.h | 216 ------
include/configs/davinci_schmoogie.h | 136 ----
include/configs/davinci_sffsdr.h | 129 ----
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include/configs/eb_cpux9k2.h | 400 -----------
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include/configs/enbw_cmc.h | 440 ------------
include/configs/ima3-mx53.h | 238 -------
include/configs/imx27lite.h | 49 --
include/configs/imx31_litekit.h | 171 -----
include/configs/jornada.h | 123 ----
include/configs/lacie_kw.h | 214 ------
include/configs/lp8x4x.h | 238 -------
include/configs/magnesium.h | 58 --
include/configs/meesc.h | 199 ------
include/configs/mv88f6281gtw_ge.h | 88 ---
include/configs/mx51_efikamx.h | 242 -------
include/configs/nhk8815.h | 170 -----
include/configs/omap3_evm.h | 154 ----
include/configs/omap3_evm_common.h | 289 --------
include/configs/omap3_evm_quick_mmc.h | 92 ---
include/configs/omap3_evm_quick_nand.h | 92 ---
include/configs/omap3_logic.h | 322 ---------
include/configs/omap3_mvblx.h | 277 --------
include/configs/omap3_sdp3430.h | 318 ---------
include/configs/openrd.h | 137 ----
include/configs/otc570.h | 252 -------
include/configs/palmld.h | 245 -------
include/configs/palmtc.h | 219 ------
include/configs/palmtreo680.h | 270 -------
include/configs/pxa255_idp.h | 335 ---------
include/configs/qong.h | 283 --------
include/configs/rd6281a.h | 96 ---
include/configs/scb9328.h | 312 ---------
include/configs/snowball.h | 232 ------
include/configs/stamp9g20.h | 244 -------
include/configs/ti814x_evm.h | 230 ------
include/configs/ti816x_evm.h | 172 -----
include/configs/tk71.h | 112 ---
include/configs/trizepsiv.h | 309 --------
include/configs/tt01.h | 266 -------
include/configs/tx25.h | 172 -----
include/configs/u8500_href.h | 198 ------
include/configs/versatile.h | 214 ------
include/configs/vision2.h | 199 ------
include/configs/vl_ma2sc.h | 429 ------------
include/configs/vpac270.h | 325 ---------
include/configs/wireless_space.h | 179 -----
include/configs/xaeniax.h | 539 --------------
include/configs/zipitz2.h | 238 -------
include/nomadik.h | 40 --
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delete mode 100644 configs/openrd_base_defconfig
delete mode 100644 configs/openrd_client_defconfig
delete mode 100644 configs/openrd_ultimate_defconfig
delete mode 100644 configs/otc570_dataflash_defconfig
delete mode 100644 configs/otc570_defconfig
delete mode 100644 configs/palmld_defconfig
delete mode 100644 configs/palmtc_defconfig
delete mode 100644 configs/palmtreo680_defconfig
delete mode 100644 configs/polaris_defconfig
delete mode 100644 configs/portuxg20_defconfig
delete mode 100644 configs/pxa255_idp_defconfig
delete mode 100644 configs/qong_defconfig
delete mode 100644 configs/rd6281a_defconfig
delete mode 100644 configs/scb9328_defconfig
delete mode 100644 configs/snowball_defconfig
delete mode 100644 configs/stamp9g20_defconfig
delete mode 100644 configs/ti814x_evm_defconfig
delete mode 100644 configs/ti816x_evm_defconfig
delete mode 100644 configs/tk71_defconfig
delete mode 100644 configs/trizepsiv_defconfig
delete mode 100644 configs/tt01_defconfig
delete mode 100644 configs/tx25_defconfig
delete mode 100644 configs/u8500_href_defconfig
delete mode 100644 configs/versatileab_defconfig
delete mode 100644 configs/versatilepb_defconfig
delete mode 100644 configs/versatileqemu_defconfig
delete mode 100644 configs/vision2_defconfig
delete mode 100644 configs/vl_ma2sc_defconfig
delete mode 100644 configs/vl_ma2sc_ram_defconfig
delete mode 100644 configs/vpac270_nor_128_defconfig
delete mode 100644 configs/vpac270_nor_256_defconfig
delete mode 100644 configs/vpac270_ond_256_defconfig
delete mode 100644 configs/wireless_space_defconfig
delete mode 100644 configs/xaeniax_defconfig
delete mode 100644 configs/zipitz2_defconfig
delete mode 100644 doc/README.switch_config
delete mode 100644 drivers/mtd/nand/nomadik.c
delete mode 100644 include/configs/balloon3.h
delete mode 100644 include/configs/cpu9260.h
delete mode 100644 include/configs/cpuat91.h
delete mode 100644 include/configs/davinci_dm355evm.h
delete mode 100644 include/configs/davinci_dm355leopard.h
delete mode 100644 include/configs/davinci_dm365evm.h
delete mode 100644 include/configs/davinci_dm6467evm.h
delete mode 100644 include/configs/davinci_dvevm.h
delete mode 100644 include/configs/davinci_schmoogie.h
delete mode 100644 include/configs/davinci_sffsdr.h
delete mode 100644 include/configs/davinci_sonata.h
delete mode 100644 include/configs/dig297.h
delete mode 100644 include/configs/ea20.h
delete mode 100644 include/configs/eb_cpux9k2.h
delete mode 100644 include/configs/edb93xx.h
delete mode 100644 include/configs/enbw_cmc.h
delete mode 100644 include/configs/ima3-mx53.h
delete mode 100644 include/configs/imx27lite.h
delete mode 100644 include/configs/imx31_litekit.h
delete mode 100644 include/configs/jornada.h
delete mode 100644 include/configs/lacie_kw.h
delete mode 100644 include/configs/lp8x4x.h
delete mode 100644 include/configs/magnesium.h
delete mode 100644 include/configs/meesc.h
delete mode 100644 include/configs/mv88f6281gtw_ge.h
delete mode 100644 include/configs/mx51_efikamx.h
delete mode 100644 include/configs/nhk8815.h
delete mode 100644 include/configs/omap3_evm.h
delete mode 100644 include/configs/omap3_evm_common.h
delete mode 100644 include/configs/omap3_evm_quick_mmc.h
delete mode 100644 include/configs/omap3_evm_quick_nand.h
delete mode 100644 include/configs/omap3_logic.h
delete mode 100644 include/configs/omap3_mvblx.h
delete mode 100644 include/configs/omap3_sdp3430.h
delete mode 100644 include/configs/openrd.h
delete mode 100644 include/configs/otc570.h
delete mode 100644 include/configs/palmld.h
delete mode 100644 include/configs/palmtc.h
delete mode 100644 include/configs/palmtreo680.h
delete mode 100644 include/configs/pxa255_idp.h
delete mode 100644 include/configs/qong.h
delete mode 100644 include/configs/rd6281a.h
delete mode 100644 include/configs/scb9328.h
delete mode 100644 include/configs/snowball.h
delete mode 100644 include/configs/stamp9g20.h
delete mode 100644 include/configs/ti814x_evm.h
delete mode 100644 include/configs/ti816x_evm.h
delete mode 100644 include/configs/tk71.h
delete mode 100644 include/configs/trizepsiv.h
delete mode 100644 include/configs/tt01.h
delete mode 100644 include/configs/tx25.h
delete mode 100644 include/configs/u8500_href.h
delete mode 100644 include/configs/versatile.h
delete mode 100644 include/configs/vision2.h
delete mode 100644 include/configs/vl_ma2sc.h
delete mode 100644 include/configs/vpac270.h
delete mode 100644 include/configs/wireless_space.h
delete mode 100644 include/configs/xaeniax.h
delete mode 100644 include/configs/zipitz2.h
delete mode 100644 include/nomadik.h
--
2.5.0.457.gab17608
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 01/45] arm: Remove balloon3 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
@ 2015-08-31 1:18 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,01/45] " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 02/45] arm: Remove eukrea boards Simon Glass
` (44 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
arch/arm/include/asm/mach-types.h | 13 --
board/balloon3/Kconfig | 9 --
board/balloon3/MAINTAINERS | 6 -
board/balloon3/Makefile | 9 --
board/balloon3/balloon3.c | 221 ----------------------------------
configs/balloon3_defconfig | 6 -
include/configs/balloon3.h | 242 --------------------------------------
8 files changed, 511 deletions(-)
delete mode 100644 board/balloon3/Kconfig
delete mode 100644 board/balloon3/MAINTAINERS
delete mode 100644 board/balloon3/Makefile
delete mode 100644 board/balloon3/balloon3.c
delete mode 100644 configs/balloon3_defconfig
delete mode 100644 include/configs/balloon3.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a99ae28..0ef52bd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -756,10 +756,6 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
-config TARGET_BALLOON3
- bool "Support balloon3"
- select CPU_PXA
-
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -894,7 +890,6 @@ source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/bachmann/ot1200/Kconfig"
-source "board/balloon3/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index e72184b..b1caa16 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -197,7 +197,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_SMDK2412 1009
#define MACH_TYPE_SMDK2413 1022
#define MACH_TYPE_AML_M5900 1024
-#define MACH_TYPE_BALLOON3 1029
#define MACH_TYPE_ECBAT91 1072
#define MACH_TYPE_ONEARM 1075
#define MACH_TYPE_SMDK2443 1084
@@ -3332,18 +3331,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_aml_m5900() (0)
#endif
-#ifdef CONFIG_MACH_BALLOON3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BALLOON3
-# endif
-# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3)
-#else
-# define machine_is_balloon3() (0)
-#endif
-
#ifdef CONFIG_MACH_ECBAT91
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig
deleted file mode 100644
index 53b7a9a..0000000
--- a/board/balloon3/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BALLOON3
-
-config SYS_BOARD
- default "balloon3"
-
-config SYS_CONFIG_NAME
- default "balloon3"
-
-endif
diff --git a/board/balloon3/MAINTAINERS b/board/balloon3/MAINTAINERS
deleted file mode 100644
index df9a5bb..0000000
--- a/board/balloon3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BALLOON3 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/balloon3/
-F: include/configs/balloon3.h
-F: configs/balloon3_defconfig
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
deleted file mode 100644
index d7fb5e0..0000000
--- a/board/balloon3/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Balloon3 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := balloon3.o
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
deleted file mode 100644
index 458d90c..0000000
--- a/board/balloon3/balloon3.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Balloon3 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <spartan3.h>
-#include <command.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void balloon3_init_fpga(void);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of balloon3 */
- gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Init the FPGA */
- balloon3_init_fpga();
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-}
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-#endif
-
-#if defined(CONFIG_FPGA)
-/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
-int fpga_pgm_fn(int nassert, int nflush, int cookie)
-{
- if (nassert)
- writel(0x80, GPCR3);
- else
- writel(0x80, GPSR3);
- if (nflush)
- writel(0x100, GPCR3);
- else
- writel(0x100, GPSR3);
- return nassert;
-}
-
-/* Check GPIO83 -- INITB */
-int fpga_init_fn(int cookie)
-{
- return !(readl(GPLR2) & 0x80000);
-}
-
-/* Check GPIO84 -- BUSY */
-int fpga_busy_fn(int cookie)
-{
- return !(readl(GPLR2) & 0x100000);
-}
-
-/* Check GPIO111 -- DONE */
-int fpga_done_fn(int cookie)
-{
- return readl(GPLR3) & 0x8000;
-}
-
-/* Configure GPIO104 as GPIO and deassert it */
-int fpga_pre_config_fn(int cookie)
-{
- writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
- writel(0x100, GPCR3);
- return 0;
-}
-
-/* Configure GPIO104 as nSKTSEL */
-int fpga_post_config_fn(int cookie)
-{
- writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
- return 0;
-}
-
-/* Toggle RDnWR */
-int fpga_wr_fn(int nassert_write, int flush, int cookie)
-{
- udelay(1000);
-
- if (nassert_write)
- writel(0x100, GPCR3);
- else
- writel(0x100, GPSR3);
-
- return nassert_write;
-}
-
-/* Write program to the FPGA */
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
- writeb(data, 0x10f00000);
- return 0;
-}
-
-/* Toggle Clock pin -- NO-OP */
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- return assert_clk;
-}
-
-/* Toggle ChipSelect pin -- NO-OP */
-int fpga_cs_fn(int assert_clk, int flush, int cookie)
-{
- return assert_clk;
-}
-
-xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- NULL, /* err */
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- NULL, /* rdata */
- fpga_wdata_fn,
- fpga_busy_fn,
- NULL, /* abort */
- fpga_post_config_fn,
-};
-
-xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
- (void *)&balloon3_fpga_fns, 0);
-
-/* Initialize the FPGA */
-void balloon3_init_fpga(void)
-{
- fpga_init();
- fpga_add(fpga_xilinx, &fpga);
-}
-#else
-void balloon3_init_fpga(void) {}
-#endif /* CONFIG_FPGA */
diff --git a/configs/balloon3_defconfig b/configs/balloon3_defconfig
deleted file mode 100644
index bf524ce..0000000
--- a/configs/balloon3_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_BALLOON3=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
deleted file mode 100644
index 124a766..0000000
--- a/include/configs/balloon3.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Balloon3 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_BALLOON3 1 /* Balloon3 board */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "fpga load 0x0 0x50000 0x62638; " \
- "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "bootm 0xd0000;"
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_STUART 1
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#undef CONFIG_CMD_ENV
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FPGA_LOADMK
-#undef CONFIG_LCD
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_IS_IN_FLASH
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0x000000
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
-#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
-#define CONFIG_SYS_GPSR2_VAL 0x7131c000
-#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
-
-#define CONFIG_SYS_GPCR0_VAL 0x0
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
-#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
-#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
-#define CONFIG_SYS_GPDR3_VAL 0x000201fe
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
-#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
-#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0xffffffff
-#define CONFIG_SYS_CCCR 0x00000290
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
-#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
-#define CONFIG_SYS_MSC2_VAL 0x74a42491
-#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
-#define CONFIG_SYS_MDREFR_VAL 0x001d8018
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_BALLOON3LCD
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * FPGA
- */
-#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_WAIT 1000
-#define CONFIG_MAX_FPGA_DEVICES 1
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 02/45] arm: Remove eukrea boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
2015-08-31 1:18 ` [U-Boot] [PATCH 01/45] arm: Remove balloon3 board Simon Glass
@ 2015-08-31 1:18 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,02/45] " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards Simon Glass
` (43 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove all cpu9260 and cpuat91 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/include/asm/mach-types.h | 37 ---
arch/arm/mach-at91/Kconfig | 10 -
board/eukrea/cpu9260/Kconfig | 12 -
board/eukrea/cpu9260/MAINTAINERS | 13 -
board/eukrea/cpu9260/Makefile | 17 --
board/eukrea/cpu9260/cpu9260.c | 158 ------------
board/eukrea/cpu9260/led.c | 139 -----------
board/eukrea/cpuat91/Kconfig | 12 -
board/eukrea/cpuat91/MAINTAINERS | 7 -
board/eukrea/cpuat91/Makefile | 8 -
board/eukrea/cpuat91/cpuat91.c | 75 ------
configs/cpu9260_128M_defconfig | 11 -
configs/cpu9260_defconfig | 11 -
configs/cpu9260_nand_128M_defconfig | 11 -
configs/cpu9260_nand_defconfig | 11 -
configs/cpu9G20_128M_defconfig | 11 -
configs/cpu9G20_defconfig | 11 -
configs/cpu9G20_nand_128M_defconfig | 11 -
configs/cpu9G20_nand_defconfig | 11 -
configs/cpuat91_defconfig | 13 -
configs/cpuat91_ram_defconfig | 13 -
include/configs/cpu9260.h | 485 ------------------------------------
include/configs/cpuat91.h | 222 -----------------
23 files changed, 1309 deletions(-)
delete mode 100644 board/eukrea/cpu9260/Kconfig
delete mode 100644 board/eukrea/cpu9260/MAINTAINERS
delete mode 100644 board/eukrea/cpu9260/Makefile
delete mode 100644 board/eukrea/cpu9260/cpu9260.c
delete mode 100644 board/eukrea/cpu9260/led.c
delete mode 100644 board/eukrea/cpuat91/Kconfig
delete mode 100644 board/eukrea/cpuat91/MAINTAINERS
delete mode 100644 board/eukrea/cpuat91/Makefile
delete mode 100644 board/eukrea/cpuat91/cpuat91.c
delete mode 100644 configs/cpu9260_128M_defconfig
delete mode 100644 configs/cpu9260_defconfig
delete mode 100644 configs/cpu9260_nand_128M_defconfig
delete mode 100644 configs/cpu9260_nand_defconfig
delete mode 100644 configs/cpu9G20_128M_defconfig
delete mode 100644 configs/cpu9G20_defconfig
delete mode 100644 configs/cpu9G20_nand_128M_defconfig
delete mode 100644 configs/cpu9G20_nand_defconfig
delete mode 100644 configs/cpuat91_defconfig
delete mode 100644 configs/cpuat91_ram_defconfig
delete mode 100644 include/configs/cpu9260.h
delete mode 100644 include/configs/cpuat91.h
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index b1caa16..55a543a 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -150,7 +150,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
#define MACH_TYPE_PNX4008 782
-#define MACH_TYPE_CPUAT91 787
#define MACH_TYPE_IQ81340SC 799
#define MACH_TYPE_IQ81340MC 801
#define MACH_TYPE_MICRO9 811
@@ -2767,18 +2766,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_pnx4008() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT91
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT91
-# endif
-# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91)
-#else
-# define machine_is_cpuat91() (0)
-#endif
-
#ifdef CONFIG_MACH_IQ81340SC
# ifdef machine_arch_type
# undef machine_arch_type
@@ -5035,30 +5022,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_omap_zoom2() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT9260
-# endif
-# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260)
-#else
-# define machine_is_cpuat9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX27
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27
-# endif
-# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27)
-#else
-# define machine_is_eukrea_cpuimx27() (0)
-#endif
-
#ifdef CONFIG_MACH_ACS5K
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index f9f148d..01a8d45 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,10 +12,6 @@ config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
select CPU_ARM920T
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
-
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select CPU_ARM926EJS
@@ -115,10 +111,6 @@ config TARGET_OTC570
bool "Support otc570"
select CPU_ARM926EJS
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
@@ -152,14 +144,12 @@ source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig
deleted file mode 100644
index 90d2124..0000000
--- a/board/eukrea/cpu9260/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPU9260
-
-config SYS_BOARD
- default "cpu9260"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpu9260"
-
-endif
diff --git a/board/eukrea/cpu9260/MAINTAINERS b/board/eukrea/cpu9260/MAINTAINERS
deleted file mode 100644
index fb5aee8..0000000
--- a/board/eukrea/cpu9260/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-CPU9260 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpu9260/
-F: include/configs/cpu9260.h
-F: configs/cpu9260_defconfig
-F: configs/cpu9260_128M_defconfig
-F: configs/cpu9260_nand_defconfig
-F: configs/cpu9260_nand_128M_defconfig
-F: configs/cpu9G20_defconfig
-F: configs/cpu9G20_128M_defconfig
-F: configs/cpu9G20_nand_defconfig
-F: configs/cpu9G20_nand_128M_defconfig
diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile
deleted file mode 100644
index e34792a..0000000
--- a/board/eukrea/cpu9260/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net
-# Lead Tech Design <www.leadtechdesign.com>
-# Ilko Iliev <www.ronetix.at>
-#
-# (C) Copyright 2009
-# Eric Benard <eric@eukrea.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu9260.o
-obj-y += led.o
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
deleted file mode 100644
index 01ecccb..0000000
--- a/board/eukrea/cpu9260/cpu9260.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009-2011
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-#ifdef CONFIG_CMD_NAND
-static void cpu9260_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
-#if defined(CONFIG_CPU9G20)
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-#elif defined(CONFIG_CPU9260)
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-#endif
-
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void cpu9260_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- writel((1 << ATMEL_ID_PIOA) |
- (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-
-
-int board_init(void)
-{
- /* arch number of the board */
-#if defined(CONFIG_CPU9G20)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
-#elif defined(CONFIG_CPU9260)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- cpu9260_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- cpu9260_macb_hw_init();
-#endif
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
-#endif
- return rc;
-}
diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c
deleted file mode 100644
index 0cfe0a6..0000000
--- a/board/eukrea/cpu9260/led.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
- STATUS_LED_OFF, STATUS_LED_OFF};
-
-void coloured_LED_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- at91_set_pio_output(CONFIG_RED_LED, 1);
- at91_set_pio_output(CONFIG_GREEN_LED, 1);
- at91_set_pio_output(CONFIG_YELLOW_LED, 1);
- at91_set_pio_output(CONFIG_BLUE_LED, 1);
-
- at91_set_pio_value(CONFIG_RED_LED, 1);
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
-}
-
-void red_led_off(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 1);
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void green_led_off(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
-}
-
-void yellow_led_off(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
-}
-
-void blue_led_off(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 0);
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void green_led_on(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 0);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
-}
-
-void yellow_led_on(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 0);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
-}
-
-void blue_led_on(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 0);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
- blue_led_off();
- else
- blue_led_on();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
- green_led_off();
- else
- green_led_on();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
- yellow_led_off();
- else
- yellow_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == state)
- blue_led_on();
- else
- blue_led_off();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
- green_led_on();
- else
- green_led_off();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == state)
- yellow_led_on();
- else
- yellow_led_off();
- }
-}
diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig
deleted file mode 100644
index 27b005c..0000000
--- a/board/eukrea/cpuat91/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPUAT91
-
-config SYS_BOARD
- default "cpuat91"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpuat91"
-
-endif
diff --git a/board/eukrea/cpuat91/MAINTAINERS b/board/eukrea/cpuat91/MAINTAINERS
deleted file mode 100644
index 1f6bc79..0000000
--- a/board/eukrea/cpuat91/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CPUAT91 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpuat91/
-F: include/configs/cpuat91.h
-F: configs/cpuat91_defconfig
-F: configs/cpuat91_ram_defconfig
diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile
deleted file mode 100644
index 59b80c2..0000000
--- a/board/eukrea/cpuat91/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cpuat91.o
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
deleted file mode 100644
index ec0ce0b..0000000
--- a/board/eukrea/cpuat91/cpuat91.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
- * Eric Benard <eric@eukrea.com>
- * based on at91rm9200dk.c which is :
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* arch number of CPUAT91-Board */
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- return 0;
-}
-
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(bd_t *bis)
-{
- return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
- u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << AT91_ID_PIOA, &pmc->pcer);
- pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-}
-#endif
diff --git a/configs/cpu9260_128M_defconfig b/configs/cpu9260_128M_defconfig
deleted file mode 100644
index 187fced..0000000
--- a/configs/cpu9260_128M_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_defconfig b/configs/cpu9260_defconfig
deleted file mode 100644
index 4b50505..0000000
--- a/configs/cpu9260_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_nand_128M_defconfig b/configs/cpu9260_nand_128M_defconfig
deleted file mode 100644
index 797fb85..0000000
--- a/configs/cpu9260_nand_128M_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9260_nand_defconfig b/configs/cpu9260_nand_defconfig
deleted file mode 100644
index 8d155d0..0000000
--- a/configs/cpu9260_nand_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
diff --git a/configs/cpu9G20_128M_defconfig b/configs/cpu9G20_128M_defconfig
deleted file mode 100644
index 650c934..0000000
--- a/configs/cpu9G20_128M_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_defconfig b/configs/cpu9G20_defconfig
deleted file mode 100644
index 997eec5..0000000
--- a/configs/cpu9G20_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_nand_128M_defconfig b/configs/cpu9G20_nand_128M_defconfig
deleted file mode 100644
index 6d62732..0000000
--- a/configs/cpu9G20_nand_128M_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpu9G20_nand_defconfig b/configs/cpu9G20_nand_defconfig
deleted file mode 100644
index 52f916f..0000000
--- a/configs/cpu9G20_nand_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
diff --git a/configs/cpuat91_defconfig b/configs/cpuat91_defconfig
deleted file mode 100644
index 10b8ad2..0000000
--- a/configs/cpuat91_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="CPUAT91=> "
diff --git a/configs/cpuat91_ram_defconfig b/configs/cpuat91_ram_defconfig
deleted file mode 100644
index 188c2b9..0000000
--- a/configs/cpuat91_ram_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
deleted file mode 100644
index 82f4fe7..0000000
--- a/include/configs/cpu9260.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * Configuration settings for the Eukrea CPU9260 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* to be removed once maemory-map.h is fixed */
-#define AT91_BASE_SYS 0xffffe800
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260
-#else
-#error "Unknown board"
-#endif
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#endif
-
-/* clocks */
-#if defined(CONFIG_CPU9G20)
-#define MASTER_PLL_DIV 0x01
-#define MASTER_PLL_MUL 0x2B
-#elif defined(CONFIG_CPU9260)
-#define MASTER_PLL_DIV 0x09
-#define MASTER_PLL_MUL 0x61
-#endif
-
-/* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_6 | \
- AT91_PMC_PDIV_2)
-#define CONFIG_SYS_MCKR2_VAL \
- CONFIG_SYS_MCKR1_VAL
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#endif
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
- AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
-
-/* SDRAM */
-/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x287
-/* SDRAMC_CR - Configuration register*/
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-#endif
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
- AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(3))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
- AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(2))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_CR_PROCRST | \
- AT91_RSTC_MR_ERSTL(1) | \
- AT91_RSTC_MR_ERSTL(2))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
- AT91_WDT_MR_WDV(0xfff) | \
- AT91_WDT_MR_WDDIS | \
- AT91_WDT_MR_WDD(0xfff))
-
-/*
- * Hardware drivers
- */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
-#else
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
-#endif
-
-/* NAND flash */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-
-/* NOR flash */
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_NO_FLASH
-#else
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_2 0x12000000
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1, PHYS_FLASH_2 }
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-/* LEDS */
-/* Status LED */
-#define CONFIG_STATUS_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_RED 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_YELLOW 2
-#define STATUS_LED_BLUE 3
-/* Red */
-#define STATUS_LED_BIT STATUS_LED_RED
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-/* Green */
-#define STATUS_LED_BIT1 STATUS_LED_GREEN
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-/* Yellow */
-#define STATUS_LED_BIT2 STATUS_LED_YELLOW
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
-/* Blue */
-#define STATUS_LED_BIT3 STATUS_LED_BLUE
-#define STATUS_LED_STATE3 STATUS_LED_ON
-#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
-/* Optional value */
-#define STATUS_LED_BOOT STATUS_LED_BIT
-
-#define CONFIG_RED_LED AT91_PIO_PORTC, 11
-#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
-#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
-#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#endif
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_USE_NANDFLASH
-#undef CONFIG_SYS_USE_FLASH
-#else
-#define CONFIG_SYS_USE_FLASH
-#undef CONFIG_SYS_USE_NANDFLASH
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR "cpu9260"
-#endif
-
-#if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "1792k(kernel)," \
- "-(rootfs);" \
- "atmel_nand:-(nand)"
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,0\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs;bootm 0x10060000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
- "off 0x10000000 0x1003ffff;erase 0x10000000 " \
- "0x1003ffff;cp.b 0x24000000 0x10000000 " \
- "$(filesize)\0" \
- "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
- " 0x10060000 0x1021ffff;erase 0x10060000 " \
- "0x1021ffff;cp.b 0x24000000 0x10060000 " \
- "$(filesize)\0" \
- "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
- "protect off 0x10220000 0x13ffffff;erase " \
- "0x10220000 0x13ffffff;cp.b 0x24000000 " \
- "0x10220000 $(filesize)\0" \
- ""
-#elif defined(CONFIG_NANDBOOT)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=atmel_nand:" \
- "128k(bootstrap)ro," \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "128k(u-boot-env2)ro," \
- "2M(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
- "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,5\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
- "0x200000; bootm 0x22000000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "u-boot=u-boot-eukrea-cpu9260.bin\0" \
- "kernel=uImage-eukrea-cpu9260.bin\0" \
- "rootfs=image-eukrea-cpu9260.ubi\0" \
- "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
- "nand erase 20000 40000; " \
- "nand write ${loadaddr} 20000 40000\0" \
- "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
- "nand erase a0000 200000; " \
- "nand write ${loadaddr} a0000 200000\0" \
- "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
- "nand erase 2a0000 fd60000; " \
- "nand write ${loadaddr} 2a0000 ${filesize}\0"
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_NETCONSOLE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
deleted file mode 100644
index 29cd842..0000000
--- a/include/configs/cpuat91.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
- * eric@eukrea.com
- *
- * Configuration settings for the CPUAT91 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_CPUAT91_H
-#define _CONFIG_CPUAT91_H
-
-#include <linux/sizes.h>
-
-#ifdef CONFIG_RAMBOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x21F00000
-#else
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_SYS_TEXT_BASE 0
-#endif
-
-#define AT91C_XTAL_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
-#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
-#define CONFIG_AT91RM9200
-#define CONFIG_CPUAT91
-#define USE_920T_MMU
-
-#include <asm/hardware.h> /* needed for port definitions */
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR
-/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
-#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
-#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
-#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
-
-/* sdram */
-#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
-#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
-#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
-#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID 0/* ignored in arm */
-
-#undef CONFIG_HARD_I2C
-#define AT91_PIN_SDA (1<<25)
-#define AT91_PIN_SCL (1<<26)
-
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
-#define I2C_SDA(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
-#define I2C_SCL(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
-
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CACHE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_DHCP
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#endif
-
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#define CONFIG_DRIVER_AT91EMAC
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RMII
-#define CONFIG_MII
-#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_KS8721_PHY
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION
-#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1 }
-
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_AT91C_PQFP_UHPBU
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#endif
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_DEVICE_NULLDEV
-#define CONFIG_SILENT_CONSOLE
-
-#define CONFIG_VERSION_VARIABLE
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "128k(u-boot)ro," \
- "128k(u-boot-env)," \
- "1792k(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdid=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
- "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
- "10000000 ${filesize}\0" \
- "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
- "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \
- "10040000 ${filesize}\0" \
- "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
- "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \
- "21000000 10200000 ${filesize}\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "flashboot=run ramargs;bootm 10040000\0" \
- "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
- "bootm 21000000\0"
-#endif /* _CONFIG_CPUAT91_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
2015-08-31 1:18 ` [U-Boot] [PATCH 01/45] arm: Remove balloon3 board Simon Glass
2015-08-31 1:18 ` [U-Boot] [PATCH 02/45] arm: Remove eukrea boards Simon Glass
@ 2015-08-31 1:18 ` Simon Glass
2015-08-31 7:51 ` Simon Guinot
2015-08-31 1:18 ` [U-Boot] [PATCH 04/45] arm: Remove snowball and u8500_href boards Simon Glass
` (42 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove all except edmini_v2 (which has been converted).
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 12 --
board/LaCie/net2big_v2/Kconfig | 12 --
board/LaCie/net2big_v2/MAINTAINERS | 11 --
board/LaCie/net2big_v2/Makefile | 15 --
board/LaCie/net2big_v2/kwbimage.cfg | 151 -----------------
board/LaCie/net2big_v2/net2big_v2.c | 253 ----------------------------
board/LaCie/net2big_v2/net2big_v2.h | 29 ----
board/LaCie/netspace_v2/Kconfig | 12 --
board/LaCie/netspace_v2/MAINTAINERS | 14 --
board/LaCie/netspace_v2/Makefile | 12 --
board/LaCie/netspace_v2/kwbimage-is2.cfg | 151 -----------------
board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 151 -----------------
board/LaCie/netspace_v2/kwbimage.cfg | 151 -----------------
board/LaCie/netspace_v2/netspace_v2.c | 117 -------------
board/LaCie/netspace_v2/netspace_v2.h | 23 ---
board/LaCie/wireless_space/Kconfig | 12 --
board/LaCie/wireless_space/MAINTAINERS | 6 -
board/LaCie/wireless_space/Makefile | 12 --
board/LaCie/wireless_space/kwbimage.cfg | 71 --------
board/LaCie/wireless_space/wireless_space.c | 165 ------------------
configs/net2big_v2_defconfig | 8 -
configs/netspace_lite_v2_defconfig | 8 -
configs/netspace_max_v2_defconfig | 8 -
configs/netspace_mini_v2_defconfig | 8 -
configs/netspace_v2_defconfig | 8 -
configs/wireless_space_defconfig | 7 -
include/configs/lacie_kw.h | 214 -----------------------
include/configs/wireless_space.h | 179 --------------------
28 files changed, 1820 deletions(-)
delete mode 100644 board/LaCie/net2big_v2/Kconfig
delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS
delete mode 100644 board/LaCie/net2big_v2/Makefile
delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg
delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c
delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h
delete mode 100644 board/LaCie/netspace_v2/Kconfig
delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS
delete mode 100644 board/LaCie/netspace_v2/Makefile
delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg
delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg
delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg
delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c
delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h
delete mode 100644 board/LaCie/wireless_space/Kconfig
delete mode 100644 board/LaCie/wireless_space/MAINTAINERS
delete mode 100644 board/LaCie/wireless_space/Makefile
delete mode 100644 board/LaCie/wireless_space/kwbimage.cfg
delete mode 100644 board/LaCie/wireless_space/wireless_space.c
delete mode 100644 configs/net2big_v2_defconfig
delete mode 100644 configs/netspace_lite_v2_defconfig
delete mode 100644 configs/netspace_max_v2_defconfig
delete mode 100644 configs/netspace_mini_v2_defconfig
delete mode 100644 configs/netspace_v2_defconfig
delete mode 100644 configs/wireless_space_defconfig
delete mode 100644 include/configs/lacie_kw.h
delete mode 100644 include/configs/wireless_space.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 1261885..1ac99b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -40,15 +40,6 @@ config TARGET_TK71
config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board"
-config TARGET_NET2BIG_V2
- bool "LaCie 2Big Network v2 NAS Board"
-
-config TARGET_NETSPACE_V2
- bool "LaCie netspace_v2 Board"
-
-config TARGET_WIRELESS_SPACE
- bool "LaCie Wireless_space Board"
-
config TARGET_IB62X0
bool "ib62x0 Board"
@@ -78,9 +69,6 @@ source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig"
-source "board/LaCie/net2big_v2/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig
deleted file mode 100644
index ba460db..0000000
--- a/board/LaCie/net2big_v2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_NET2BIG_V2
-
-config SYS_BOARD
- default "net2big_v2"
-
-config SYS_VENDOR
- default "LaCie"
-
-config SYS_CONFIG_NAME
- default "lacie_kw"
-
-endif
diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
deleted file mode 100644
index 205c75e..0000000
--- a/board/LaCie/net2big_v2/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-NET2BIG_V2 BOARD
-#M: -
-S: Maintained
-F: board/LaCie/net2big_v2/
-F: include/configs/lacie_kw.h
-F: configs/d2net_v2_defconfig
-
-NET2BIG_V2 BOARD
-M: Simon Guinot <simon.guinot@sequanux.org>
-S: Maintained
-F: configs/net2big_v2_defconfig
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
deleted file mode 100644
index f3074af..0000000
--- a/board/LaCie/net2big_v2/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := net2big_v2.o ../common/common.o
-ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
-obj-y += ../common/cpld-gpio-bus.o
-endif
diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
deleted file mode 100644
index 453fcb2..0000000
--- a/board/LaCie/net2big_v2/kwbimage.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000C30 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000CCCC # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000662 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000044 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
deleted file mode 100644
index 263bb54..0000000
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "net2big_v2.h"
-#include "../common/common.h"
-#include "../common/cpld-gpio-bus.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* GPIO configuration */
- mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
- NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Request power-off */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP13_GPIO, /* Rear power switch (on|auto) */
- MPP14_GPIO, /* USB fuse alarm */
- MPP15_GPIO, /* Rear power switch (auto|off) */
- MPP16_GPIO, /* SATA HDD1 power */
- MPP17_GPIO, /* SATA HDD2 power */
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP24_GPIO, /* USB mode select */
- MPP26_GPIO, /* USB device vbus */
- MPP28_GPIO, /* USB enable host vbus */
- MPP29_GPIO, /* CPLD GPIO bus ALE */
- MPP34_GPIO, /* Rear Push button 0=on 1=off */
- MPP35_GPIO, /* Inhibit switch power-off */
- MPP36_GPIO, /* SATA HDD1 presence */
- MPP37_GPIO, /* SATA HDD2 presence */
- MPP40_GPIO, /* eSATA presence */
- MPP44_GPIO, /* CPLD GPIO bus (data 0) */
- MPP45_GPIO, /* CPLD GPIO bus (data 1) */
- MPP46_GPIO, /* CPLD GPIO bus (data 2) */
- MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
- MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
- MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
- 0
- };
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Machine number */
- gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
-
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
-/*
- * Start I2C fan (GMT G762 controller)
- */
-static void init_fan(void)
-{
- u8 data;
-
- i2c_set_bus_num(0);
-
- /* Enable open-loop and PWM modes */
- data = 0x20;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
- G762_REG_FAN_CMD1, 1, &data, 1) != 0)
- goto err;
- data = 0;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
- G762_REG_SET_CNT, 1, &data, 1) != 0)
- goto err;
- /*
- * RPM to PWM (set_out register) fan speed conversion array:
- * 0 0x00
- * 1500 0x04
- * 2800 0x08
- * 3400 0x0C
- * 3700 0x10
- * 4400 0x20
- * 4700 0x30
- * 4800 0x50
- * 5200 0x80
- * 5400 0xC0
- * 5500 0xFF
- *
- * Start fan at low speed (2800 RPM):
- */
- data = 0x08;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
- G762_REG_SET_OUT, 1, &data, 1) != 0)
- goto err;
-
- return;
-err:
- printf("Error: failed to start I2C fan @%02x\n",
- CONFIG_SYS_I2C_G762_ADDR);
-}
-#else
-static void init_fan(void) {}
-#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
-
-#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
-/*
- * CPLD GPIO bus:
- *
- * - address register : bit [0-2] -> GPIO [47-49]
- * - data register : bit [0-2] -> GPIO [44-46]
- * - enable register : GPIO 29
- */
-static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
-static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
-
-static struct cpld_gpio_bus cpld_gpio_bus = {
- .addr = cpld_gpio_bus_addr,
- .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
- .data = cpld_gpio_bus_data,
- .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
- .enable = 29,
-};
-
-/*
- * LEDs configuration:
- *
- * The LEDs are controlled by a CPLD and can be configured through
- * the CPLD GPIO bus.
- *
- * Address register selection:
- *
- * addr | register
- * ----------------------------
- * 0 | front LED
- * 1 | front LED brightness
- * 2 | SATA LED brightness
- * 3 | SATA0 LED
- * 4 | SATA1 LED
- * 5 | SATA2 LED
- * 6 | SATA3 LED
- * 7 | SATA4 LED
- *
- * Data register configuration:
- *
- * data | LED brightness
- * -------------------------------------------------
- * 0 | min (off)
- * - | -
- * 7 | max
- *
- * data | front LED mode
- * -------------------------------------------------
- * 0 | fix off
- * 1 | fix blue on
- * 2 | fix red on
- * 3 | blink blue on=1 sec and blue off=1 sec
- * 4 | blink red on=1 sec and red off=1 sec
- * 5 | blink blue on=2.5 sec and red on=0.5 sec
- * 6 | blink blue on=1 sec and red on=1 sec
- * 7 | blink blue on=0.5 sec and blue off=2.5 sec
- *
- * data | SATA LED mode
- * -------------------------------------------------
- * 0 | fix off
- * 1 | SATA activity blink
- * 2 | fix red on
- * 3 | blink blue on=1 sec and blue off=1 sec
- * 4 | blink red on=1 sec and red off=1 sec
- * 5 | blink blue on=2.5 sec and red on=0.5 sec
- * 6 | blink blue on=1 sec and red on=1 sec
- * 7 | fix blue on
- */
-static void init_leds(void)
-{
- /* Enable the front blue LED */
- cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
- cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
-
- /* Configure SATA LEDs to blink in relation with the SATA activity */
- cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
- cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
- cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
-}
-#else
-static void init_leds(void) {}
-#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
-
-int misc_init_r(void)
-{
- init_fan();
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
- if (!getenv("ethaddr")) {
- uchar mac[6];
- if (lacie_read_mac_address(mac) == 0)
- eth_setenv_enetaddr("ethaddr", mac);
- }
-#endif
- init_leds();
-
- return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- mv_phy_88e1116_init("egiga0", 8);
-}
-#endif
-
-#if defined(CONFIG_KIRKWOOD_GPIO)
-/* Return GPIO push button status */
-static int
-do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
-}
-
-U_BOOT_CMD(button, 1, 1, do_read_push_button,
- "Return GPIO push button status 0=off 1=on", "");
-#endif
diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
deleted file mode 100644
index 8dead89..0000000
--- a/board/LaCie/net2big_v2/net2big_v2.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef NET2BIG_V2_H
-#define NET2BIG_V2_H
-
-/* GPIO configuration */
-#define NET2BIG_V2_OE_LOW 0x0600E000
-#define NET2BIG_V2_OE_HIGH 0x00000134
-#define NET2BIG_V2_OE_VAL_LOW 0x10030000
-#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
-
-/* Buttons */
-#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
-
-/* GMT G762 registers (I2C fan controller) */
-#define G762_REG_SET_CNT 0x00
-#define G762_REG_SET_OUT 0x03
-#define G762_REG_FAN_CMD1 0x04
-
-#endif /* NET2BIG_V2_H */
diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
deleted file mode 100644
index 930b822..0000000
--- a/board/LaCie/netspace_v2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_NETSPACE_V2
-
-config SYS_BOARD
- default "netspace_v2"
-
-config SYS_VENDOR
- default "LaCie"
-
-config SYS_CONFIG_NAME
- default "lacie_kw"
-
-endif
diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
deleted file mode 100644
index 55fd50d..0000000
--- a/board/LaCie/netspace_v2/MAINTAINERS
+++ /dev/null
@@ -1,14 +0,0 @@
-NETSPACE_V2 BOARD
-M: Simon Guinot <simon.guinot@sequanux.org>
-S: Maintained
-F: board/LaCie/netspace_v2/
-F: include/configs/lacie_kw.h
-F: configs/inetspace_v2_defconfig
-F: configs/netspace_max_v2_defconfig
-F: configs/netspace_v2_defconfig
-
-NETSPACE_LITE_V2 BOARD
-#M: -
-S: Maintained
-F: configs/netspace_lite_v2_defconfig
-F: configs/netspace_mini_v2_defconfig
diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
deleted file mode 100644
index 47778d8..0000000
--- a/board/LaCie/netspace_v2/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := netspace_v2.o ../common/common.o
diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
deleted file mode 100644
index 98713ea..0000000
--- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000008 # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
deleted file mode 100644
index 6b32193..0000000
--- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000DDDD # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
deleted file mode 100644
index 1515f81..0000000
--- a/board/LaCie/netspace_v2/kwbimage.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000000C # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
deleted file mode 100644
index 17e6296..0000000
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "netspace_v2.h"
-#include "../common/common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
- NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Fan speed (bit 1) */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO, /* Red led */
- MPP14_GPIO, /* USB fuse */
- MPP16_GPIO, /* SATA 0 power */
- MPP17_GPIO, /* SATA 1 power */
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP22_GPIO, /* Fan speed (bit 0) */
- MPP23_GPIO, /* Fan power */
- MPP24_GPIO, /* USB mode select */
- MPP25_GPIO, /* Fan rotation fail */
- MPP26_GPIO, /* USB vbus-in detection */
- MPP28_GPIO, /* USB enable vbus-out */
- MPP29_GPIO, /* Blue led (slow register) */
- MPP30_GPIO, /* Blue led (command register) */
- MPP31_GPIO, /* Board power off */
- MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
- MPP33_GPIO, /* Fan speed (bit 2) */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Machine number */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
- if (!getenv("ethaddr")) {
- uchar mac[6];
- if (lacie_read_mac_address(mac) == 0)
- eth_setenv_enetaddr("ethaddr", mac);
- }
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
- mv_phy_88e1318_init("egiga0", 0);
-#else
- mv_phy_88e1116_init("egiga0", 8);
-#endif
-}
-#endif
-
-#if defined(CONFIG_KIRKWOOD_GPIO)
-/* Return GPIO button status */
-static int
-do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
-}
-
-U_BOOT_CMD(button, 1, 1, do_read_button,
- "Return GPIO button status 0=off 1=on", "");
-#endif
diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h
deleted file mode 100644
index cdf5238..0000000
--- a/board/LaCie/netspace_v2/netspace_v2.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef NETSPACE_V2_H
-#define NETSPACE_V2_H
-
-/* GPIO configuration */
-#define NETSPACE_V2_OE_LOW 0x06004000
-#define NETSPACE_V2_OE_HIGH 0x00000031
-#define NETSPACE_V2_OE_VAL_LOW 0x10030000
-#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
-
-#define NETSPACE_V2_GPIO_BUTTON 32
-
-#endif /* NETSPACE_V2_H */
diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig
deleted file mode 100644
index 75a2fc5..0000000
--- a/board/LaCie/wireless_space/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_WIRELESS_SPACE
-
-config SYS_BOARD
- default "wireless_space"
-
-config SYS_VENDOR
- default "LaCie"
-
-config SYS_CONFIG_NAME
- default "wireless_space"
-
-endif
diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
deleted file mode 100644
index c32ecb8..0000000
--- a/board/LaCie/wireless_space/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WIRELESS_SPACE BOARD
-M: Albert ARIBAUD <albert.u.boot@aribaud.net>
-S: Maintained
-F: board/LaCie/wireless_space/
-F: include/configs/wireless_space.h
-F: configs/wireless_space_defconfig
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
deleted file mode 100644
index 90a84f4..0000000
--- a/board/LaCie/wireless_space/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := wireless_space.o ../common/common.o
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
deleted file mode 100644
index 037248b..0000000
--- a/board/LaCie/wireless_space/kwbimage.cfg
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# Based on netspace_v2 kwbimage.cfg:
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand # Boot from NAND flash
-NAND_PAGE_SIZE 800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Values taken from image original LaCie U-Boot header dump!
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-
-DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-
-DATA 0xFFD01410 0x0000CCCC # DDR Address Control
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-
-DATA 0xFFD0141C 0x00000662 # DDR Mode
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-
-DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
-
-DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-DATA 0xFFD20134 0x66666666
-DATA 0xFFD20138 0x66666666
-DATA 0xFFD10000 0x01112222
-DATA 0xFFD1000C 0x00000000
-DATA 0xFFD10104 0x00000000
-DATA 0xFFD10100 0x40000000
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
deleted file mode 100644
index 8620e4b..0000000
--- a/board/LaCie/wireless_space/wireless_space.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "../common/common.h"
-#include "netdev.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO configuration: start FAN at low speed, USB and HDD */
-
-#define WIRELESS_SPACE_OE_LOW 0xFF006808
-#define WIRELESS_SPACE_OE_HIGH 0x0000F989
-#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
-#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
-
-#define WIRELESS_SPACE_REAR_BUTTON 13
-#define WIRELESS_SPACE_FRONT_BUTTON 43
-
-const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Fan speed (bit 1) */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP13_GPIO, /* Red led */
- MPP14_GPIO, /* USB fuse */
- MPP15_SATA0_ACTn,
- MPP16_GPIO, /* SATA 0 power */
- MPP17_GPIO, /* SATA 1 power */
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0, /* Gigabit Ethernet 1 */
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GE1_8,
- MPP29_GE1_9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GE1_15,
- MPP36_GPIO, /* Fan speed (bit 2) */
- MPP37_GPIO, /* Fan speed (bit 0) */
- MPP38_GPIO, /* Fan power */
- MPP39_GPIO, /* Fan rotation fail */
- MPP40_GPIO, /* Ethernet switch link */
- MPP41_GPIO, /* USB enable host vbus */
- MPP42_GPIO, /* LED clock control */
- MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
- MPP44_GPIO, /* Red LED on/off */
- MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
- MPP46_GPIO, /* Green LED on/off */
- MPP47_GPIO, /* LED (blue, green) SATA activity blink */
- MPP48_GPIO, /* Blue LED on/off */
- 0
-};
-
-struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .mdip = MV88E61XX_MDIP_NOCHANGE,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = 0x20,
- .ports_enabled = 0x3F,
-};
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
- WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Machine number */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
- if (!getenv("ethaddr")) {
- uchar mac[6];
- if (lacie_read_mac_address(mac) == 0)
- eth_setenv_enetaddr("ethaddr", mac);
- }
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- /* configure switch on egiga0 */
- mv88e61xx_switch_initialize(&swcfg);
-}
-#endif
-
-#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
-/* Return GPIO button status */
-static int
-do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (strcmp(argv[1], "button") == 0) {
- if (strcmp(argv[2], "rear") == 0)
- /* invert GPIO result for intuitive while/until use */
- return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
- else if (strcmp(argv[2], "front") == 0)
- return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
- else
- return -1;
- } else {
- return -1;
- }
-}
-
-U_BOOT_CMD(ws, 3, 0, do_ws,
- "Return GPIO button status 0=off 1=on",
- "- ws button rear|front: test buttons' states\n"
-);
-#endif
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
deleted file mode 100644
index 09df520..0000000
--- a/configs/net2big_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NET2BIG_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
deleted file mode 100644
index 862a9ae..0000000
--- a/configs/netspace_lite_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
deleted file mode 100644
index 1829995..0000000
--- a/configs/netspace_max_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
deleted file mode 100644
index 35cb154..0000000
--- a/configs/netspace_mini_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
deleted file mode 100644
index a13452b..0000000
--- a/configs/netspace_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig
deleted file mode 100644
index 63013f6..0000000
--- a/configs/wireless_space_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_WIRELESS_SPACE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-ONFIG_SYS_PROMPT="ws> "
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
deleted file mode 100644
index 30810d3..0000000
--- a/include/configs/lacie_kw.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_LACIE_KW_H
-#define _CONFIG_LACIE_KW_H
-
-/*
- * Machine number definition
- */
-#if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
-#define CONFIG_IDENT_STRING " IS v2"
-#elif defined(CONFIG_NETSPACE_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
-#define CONFIG_IDENT_STRING " NS v2"
-#elif defined(CONFIG_NETSPACE_LITE_V2)
-#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
-#define CONFIG_IDENT_STRING " NS v2 Lite"
-#elif defined(CONFIG_NETSPACE_MINI_V2)
-#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
-#define CONFIG_IDENT_STRING " NS v2 Mini"
-#elif defined(CONFIG_NETSPACE_MAX_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
-#define CONFIG_IDENT_STRING " NS Max v2"
-#elif defined(CONFIG_D2NET_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
-#define CONFIG_IDENT_STRING " D2 v2"
-#elif defined(CONFIG_NET2BIG_V2)
-#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
-#define CONFIG_IDENT_STRING " 2Big v2"
-#else
-#error "Unknown board"
-#endif
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-/* SoC name */
-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_KW88F6192
-#else
-#define CONFIG_KW88F6281
-#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
-#define CONFIG_CMD_USB
-#endif
-
-/*
- * Core clock definition
- */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
-
-/*
- * SDRAM configuration
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * Different SDRAM configuration and size for some of the boards derived
- * from the Network Space v2
- */
-#if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
-#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
-#endif
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_RBTREE
-#undef CONFIG_ENV_SPI_MAX_HZ
-#undef CONFIG_SYS_IDE_MAXBUS
-#undef CONFIG_SYS_IDE_MAXDEVICE
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#if defined(CONFIG_D2NET_V2)
-#define CONFIG_SYS_PROMPT "d2v2> "
-#elif defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_PROMPT "2big2> "
-#else
-#define CONFIG_SYS_PROMPT "ns2> "
-#endif
-
-/*
- * Enable platform initialisation via misc_init_r() function
- */
-#define CONFIG_MISC_INIT_R
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_NETCONSOLE
-#endif
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
- defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif
-#endif /* CONFIG_MVSATA_IDE */
-
-/*
- * Enable GPI0 support
- */
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Enable I2C support
- */
-#ifdef CONFIG_CMD_I2C
-/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
-#if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_I2C_G762_ADDR 0x3e
-#endif
-#endif /* CONFIG_CMD_I2C */
-
-/*
- * Partition support
- */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/*
- * File systems support
- */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-/*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
-#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
-#define CONFIG_ENV_ADDR 0x70000
-#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND \
- "dhcp && run netconsole; " \
- "if run usbload || run diskload; then bootm; fi"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "bootfile=uImage\0" \
- "loadaddr=0x800000\0" \
- "autoload=no\0" \
- "netconsole=" \
- "set stdin $stdin,nc; " \
- "set stdout $stdout,nc; " \
- "set stderr $stderr,nc;\0" \
- "diskload=ide reset && " \
- "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
- "usbload=usb start && " \
- "fatload usb 0:1 $loadaddr /boot/$bootfile\0"
-
-#endif /* _CONFIG_LACIE_KW_H */
diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h
deleted file mode 100644
index 191ac1b..0000000
--- a/include/configs/wireless_space.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on the netspace_v2 code which is
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_WIRELESS_SPACE_H
-#define _CONFIG_WIRELESS_SPACE_H
-
-/*
- * Machine number definition
- */
-#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */
-#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE
-#define CONFIG_IDENT_STRING " Wireless Space"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-/* SoC name */
-#define CONFIG_KW88F6281
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_USB
-
-/*
- * Core clock definition
- */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
-
-/*
- * SDRAM configuration
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * Different SDRAM configuration and size for some of the boards derived
- * from the Network Space v2
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_RBTREE
-#undef CONFIG_SYS_IDE_MAXBUS
-#undef CONFIG_SYS_IDE_MAXDEVICE
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */
-#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
-#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */
-#define CONFIG_MII
-#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_NETCONSOLE
-#define CONFIG_MV88E61XX_SWITCH
-#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-#define CONFIG_MV88E61XX_CMD
-#define CONFIG_CMD_TFTPPUT
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /* CONFIG_MVSATA_IDE */
-
-/*
- * Enable GPI0 support
- */
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Enable I2C support
- */
-#ifdef CONFIG_CMD_I2C
-/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
-#endif /* CONFIG_CMD_I2C */
-
-/*
- * Partition support
- */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/*
- * File systems support
- */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-/*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Environment variables configurations
- */
-
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
-
-/*
- * Board-specific command to make using buttons etc easier
- */
-
-#define CONFIG_WIRELESS_SPACE_CMD
-
-/*
- * Default environment variables
- */
-#define CONFIG_PREBOOT
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND \
- "if run usbload || run diskload; then bootm; fi"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "bootfile=uImage\0" \
- "loadaddr=0x800000\0" \
- "autoload=no\0" \
- "netconsole=" \
- "set stdin $stdin,nc; " \
- "set stdout $stdout,nc; " \
- "set stderr $stderr,nc;\0" \
- "diskload=ide reset && " \
- "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
- "usbload=usb start && " \
- "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
- "preboot=" \
- "dhcp && run netconsole\0"
-
-#endif /* _CONFIG_WIRELESS_SPACE_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 04/45] arm: Remove snowball and u8500_href boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (2 preceding siblings ...)
2015-08-31 1:18 ` [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards Simon Glass
@ 2015-08-31 1:18 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards Simon Glass
` (41 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 10 -
arch/arm/include/asm/mach-types.h | 26 --
board/st-ericsson/snowball/Kconfig | 15 -
board/st-ericsson/snowball/MAINTAINERS | 6 -
board/st-ericsson/snowball/Makefile | 9 -
board/st-ericsson/snowball/db8500_pins.h | 745 -------------------------------
board/st-ericsson/snowball/snowball.c | 340 --------------
board/st-ericsson/u8500/Kconfig | 15 -
board/st-ericsson/u8500/MAINTAINERS | 6 -
board/st-ericsson/u8500/Makefile | 9 -
board/st-ericsson/u8500/gpio.c | 331 --------------
board/st-ericsson/u8500/u8500_href.c | 477 --------------------
configs/snowball_defconfig | 13 -
configs/u8500_href_defconfig | 13 -
include/configs/snowball.h | 232 ----------
include/configs/u8500_href.h | 198 --------
16 files changed, 2445 deletions(-)
delete mode 100644 board/st-ericsson/snowball/Kconfig
delete mode 100644 board/st-ericsson/snowball/MAINTAINERS
delete mode 100644 board/st-ericsson/snowball/Makefile
delete mode 100644 board/st-ericsson/snowball/db8500_pins.h
delete mode 100644 board/st-ericsson/snowball/snowball.c
delete mode 100644 board/st-ericsson/u8500/Kconfig
delete mode 100644 board/st-ericsson/u8500/MAINTAINERS
delete mode 100644 board/st-ericsson/u8500/Makefile
delete mode 100644 board/st-ericsson/u8500/gpio.c
delete mode 100644 board/st-ericsson/u8500/u8500_href.c
delete mode 100644 configs/snowball_defconfig
delete mode 100644 configs/u8500_href_defconfig
delete mode 100644 include/configs/snowball.h
delete mode 100644 include/configs/u8500_href.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ef52bd..5429dc8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -662,14 +662,6 @@ config ARCH_SUNXI
select USB_STORAGE
select USB_KEYBOARD
-config TARGET_SNOWBALL
- bool "Support snowball"
- select CPU_V7
-
-config TARGET_U8500_HREF
- bool "Support u8500_href"
- select CPU_V7
-
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
@@ -967,8 +959,6 @@ source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
-source "board/st-ericsson/snowball/Kconfig"
-source "board/st-ericsson/u8500/Kconfig"
source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 55a543a..d51be0b 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -402,7 +402,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_IGEP0020 2344
#define MACH_TYPE_NUC932EVB 2356
#define MACH_TYPE_OPENRD_CLIENT 2361
-#define MACH_TYPE_U8500 2368
#define MACH_TYPE_MX51_EFIKASB 2370
#define MACH_TYPE_MARVELL_JASPER 2382
#define MACH_TYPE_FLINT 2383
@@ -974,7 +973,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_RHINO 3360
#define MACH_TYPE_ARMLEX4210 3361
#define MACH_TYPE_SWARCOEXTMODEM 3362
-#define MACH_TYPE_SNOWBALL 3363
#define MACH_TYPE_PCM049 3364
#define MACH_TYPE_VIGOR 3365
#define MACH_TYPE_OSLO_AMUNDSEN 3366
@@ -5754,18 +5752,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_openrd_client() (0)
#endif
-#ifdef CONFIG_MACH_U8500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_U8500
-# endif
-# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500)
-#else
-# define machine_is_u8500() (0)
-#endif
-
#ifdef CONFIG_MACH_MX51_EFIKASB
# ifdef machine_arch_type
# undef machine_arch_type
@@ -12618,18 +12604,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_swarcoextmodem() (0)
#endif
-#ifdef CONFIG_MACH_SNOWBALL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SNOWBALL
-# endif
-# define machine_is_snowball() (machine_arch_type == MACH_TYPE_SNOWBALL)
-#else
-# define machine_is_snowball() (0)
-#endif
-
#ifdef CONFIG_MACH_PCM049
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/board/st-ericsson/snowball/Kconfig b/board/st-ericsson/snowball/Kconfig
deleted file mode 100644
index 0b3a0cc..0000000
--- a/board/st-ericsson/snowball/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SNOWBALL
-
-config SYS_BOARD
- default "snowball"
-
-config SYS_VENDOR
- default "st-ericsson"
-
-config SYS_SOC
- default "u8500"
-
-config SYS_CONFIG_NAME
- default "snowball"
-
-endif
diff --git a/board/st-ericsson/snowball/MAINTAINERS b/board/st-ericsson/snowball/MAINTAINERS
deleted file mode 100644
index 132fc52..0000000
--- a/board/st-ericsson/snowball/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SNOWBALL BOARD
-M: Mathieu Poirier <mathieu.poirier@linaro.org>
-S: Maintained
-F: board/st-ericsson/snowball/
-F: include/configs/snowball.h
-F: configs/snowball_defconfig
diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile
deleted file mode 100644
index f0605e2..0000000
--- a/board/st-ericsson/snowball/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) ST-Ericsson SA 2009
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ccflags-y += -D__RELEASE -D__STN_8500
-
-obj-y := snowball.o
diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h
deleted file mode 100644
index e339cb8..0000000
--- a/board/st-ericsson/snowball/db8500_pins.h
+++ /dev/null
@@ -1,745 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot.
- *
- * Ported to U-boot by:
- * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
- **
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- */
-
-#ifndef __DB8500_PINS_H
-#define __DB8500_PINS_H
-
-#include <asm/arch/db8500_pincfg.h>
-
-#define GPIO0_GPIO PIN_CFG(0, GPIO)
-#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
-#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
-#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
-
-#define GPIO1_GPIO PIN_CFG(1, GPIO)
-#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
-#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
-#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
-
-#define GPIO2_GPIO PIN_CFG(2, GPIO)
-#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
-#define GPIO2_NONE PIN_CFG(2, ALT_B)
-#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
-
-#define GPIO3_GPIO PIN_CFG(3, GPIO)
-#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
-#define GPIO3_NONE PIN_CFG(3, ALT_B)
-#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
-
-#define GPIO4_GPIO PIN_CFG(4, GPIO)
-#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP)
-#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
-
-#define GPIO5_GPIO PIN_CFG(5, GPIO)
-#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP)
-#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
-
-#define GPIO6_GPIO PIN_CFG(6, GPIO)
-#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP)
-#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
-
-#define GPIO7_GPIO PIN_CFG(7, GPIO)
-#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP)
-#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
-
-#define GPIO8_GPIO PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP)
-#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP)
-
-#define GPIO9_GPIO PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP)
-#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP)
-
-#define GPIO10_GPIO PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP)
-#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP)
-#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
-
-#define GPIO11_GPIO PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP)
-#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP)
-#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
-
-#define GPIO12_GPIO PIN_CFG(12, GPIO)
-#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
-#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
-
-#define GPIO13_GPIO PIN_CFG(13, GPIO)
-#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
-
-#define GPIO14_GPIO PIN_CFG(14, GPIO)
-#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
-
-#define GPIO15_GPIO PIN_CFG(15, GPIO)
-#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
-#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
-
-#define GPIO16_GPIO PIN_CFG(16, GPIO)
-#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP)
-#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
-
-#define GPIO17_GPIO PIN_CFG(17, GPIO)
-#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP)
-#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
-
-#define GPIO18_GPIO PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A)
-#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
-#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
-
-#define GPIO19_GPIO PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A)
-#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
-#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
-
-#define GPIO20_GPIO PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A)
-#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
-#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
-
-#define GPIO21_GPIO PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A)
-#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
-#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
-
-#define GPIO22_GPIO PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A)
-#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
-#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
-
-#define GPIO23_GPIO PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A)
-#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
-#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
-
-#define GPIO24_GPIO PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A)
-#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
-#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
-
-#define GPIO25_GPIO PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A)
-#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
-#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
-
-#define GPIO26_GPIO PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A)
-#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
-#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
-
-#define GPIO27_GPIO PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A)
-#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
-#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
-
-#define GPIO28_GPIO PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A)
-#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
-#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
-
-#define GPIO29_GPIO PIN_CFG(29, GPIO)
-#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
-#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
-#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
-
-#define GPIO30_GPIO PIN_CFG(30, GPIO)
-#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
-#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
-#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
-
-#define GPIO31_GPIO PIN_CFG(31, GPIO)
-#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
-#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
-#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
-
-#define GPIO32_GPIO PIN_CFG(32, GPIO)
-#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
-#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
-#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
-
-#define GPIO33_GPIO PIN_CFG(33, GPIO)
-#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
-#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
-#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
-
-#define GPIO34_GPIO PIN_CFG(34, GPIO)
-#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
-#define GPIO34_NONE PIN_CFG(34, ALT_B)
-#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
-
-#define GPIO35_GPIO PIN_CFG(35, GPIO)
-#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
-#define GPIO35_NONE PIN_CFG(35, ALT_B)
-#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
-
-#define GPIO36_GPIO PIN_CFG(36, GPIO)
-#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
-#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
-#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
-
-#define GPIO64_GPIO PIN_CFG(64, GPIO)
-#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
-#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
-#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
-
-#define GPIO65_GPIO PIN_CFG(65, GPIO)
-#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
-#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
-#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
-
-#define GPIO66_GPIO PIN_CFG(66, GPIO)
-#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
-#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
-#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
-
-#define GPIO67_GPIO PIN_CFG(67, GPIO)
-#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
-#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
-#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
-
-#define GPIO68_GPIO PIN_CFG(68, GPIO)
-#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
-#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
-#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
-
-#define GPIO69_GPIO PIN_CFG(69, GPIO)
-#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
-#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
-#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
-
-#define GPIO70_GPIO PIN_CFG(70, GPIO)
-#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
-#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
-#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
-
-#define GPIO71_GPIO PIN_CFG(71, GPIO)
-#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
-#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
-#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
-
-#define GPIO72_GPIO PIN_CFG(72, GPIO)
-#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
-#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
-#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
-
-#define GPIO73_GPIO PIN_CFG(73, GPIO)
-#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
-#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
-#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
-
-#define GPIO74_GPIO PIN_CFG(74, GPIO)
-#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
-#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
-#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
-
-#define GPIO75_GPIO PIN_CFG(75, GPIO)
-#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
-#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
-#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
-
-#define GPIO76_GPIO PIN_CFG(76, GPIO)
-#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
-#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
-#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
-
-#define GPIO77_GPIO PIN_CFG(77, GPIO)
-#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
-#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
-#define GPIO77_NONE PIN_CFG(77, ALT_C)
-
-#define GPIO78_GPIO PIN_CFG(78, GPIO)
-#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
-#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
-#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
-
-#define GPIO79_GPIO PIN_CFG(79, GPIO)
-#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
-#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
-#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
-
-#define GPIO80_GPIO PIN_CFG(80, GPIO)
-#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
-#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
-#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
-
-#define GPIO81_GPIO PIN_CFG(81, GPIO)
-#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
-#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
-#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
-
-#define GPIO82_GPIO PIN_CFG(82, GPIO)
-#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
-#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
-
-#define GPIO83_GPIO PIN_CFG(83, GPIO)
-#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
-#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
-
-#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP)
-#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
-#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
-
-#define GPIO85_GPIO PIN_CFG(85, GPIO)
-#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
-#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
-
-#define GPIO86_GPIO PIN_CFG(86, GPIO)
-#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
-#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
-#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
-
-#define GPIO87_GPIO PIN_CFG(87, GPIO)
-#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
-#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
-#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
-
-#define GPIO88_GPIO PIN_CFG(88, GPIO)
-#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
-#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
-#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
-
-#define GPIO89_GPIO PIN_CFG(89, GPIO)
-#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
-#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
-#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
-
-#define GPIO90_GPIO PIN_CFG(90, GPIO)
-#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
-#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
-#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
-
-#define GPIO91_GPIO PIN_CFG(91, GPIO)
-#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
-#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
-#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
-
-#define GPIO92_GPIO PIN_CFG(92, GPIO)
-#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
-#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
-#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
-
-#define GPIO93_GPIO PIN_CFG(93, GPIO)
-#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
-#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
-#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
-
-#define GPIO94_GPIO PIN_CFG(94, GPIO)
-#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
-#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
-#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
-
-#define GPIO95_GPIO PIN_CFG(95, GPIO)
-#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
-#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
-#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
-
-#define GPIO96_GPIO PIN_CFG(96, GPIO)
-#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
-#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
-#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
-
-#define GPIO97_GPIO PIN_CFG(97, GPIO)
-#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
-#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
-#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
-
-#define GPIO128_GPIO PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A)
-#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
-
-#define GPIO129_GPIO PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A)
-#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
-
-#define GPIO130_GPIO PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A)
-#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
-#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
-
-#define GPIO131_GPIO PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A)
-#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
-
-#define GPIO132_GPIO PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A)
-#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
-
-#define GPIO133_GPIO PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A)
-#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
-
-#define GPIO134_GPIO PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A)
-#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
-
-#define GPIO135_GPIO PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A)
-#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
-
-#define GPIO136_GPIO PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A)
-#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
-
-#define GPIO137_GPIO PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A)
-#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
-
-#define GPIO138_GPIO PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A)
-#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
-
-#define GPIO139_GPIO PIN_CFG(139, GPIO)
-#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
-#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
-#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
-
-#define GPIO140_GPIO PIN_CFG(140, GPIO)
-#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
-#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
-#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
-
-#define GPIO141_GPIO PIN_CFG(141, GPIO)
-#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
-#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
-#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
-
-#define GPIO142_GPIO PIN_CFG(142, GPIO)
-#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
-#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
-#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
-
-#define GPIO143_GPIO PIN_CFG(143, GPIO)
-#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
-
-#define GPIO144_GPIO PIN_CFG(144, GPIO)
-#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
-
-#define GPIO145_GPIO PIN_CFG(145, GPIO)
-#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
-
-#define GPIO146_GPIO PIN_CFG(146, GPIO)
-#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
-
-#define GPIO147_GPIO PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP)
-
-#define GPIO148_GPIO PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP)
-
-#define GPIO149_GPIO PIN_CFG(149, GPIO)
-#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
-#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
-#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
-
-#define GPIO150_GPIO PIN_CFG(150, GPIO)
-#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
-#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
-
-#define GPIO151_GPIO PIN_CFG(151, GPIO)
-#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
-#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
-#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
-
-#define GPIO152_GPIO PIN_CFG(152, GPIO)
-#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
-#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
-#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
-
-#define GPIO153_GPIO PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN)
-#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
-#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
-
-#define GPIO154_GPIO PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN)
-#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
-#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
-
-#define GPIO155_GPIO PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN)
-#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
-#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
-
-#define GPIO156_GPIO PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN)
-#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
-#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
-
-#define GPIO157_GPIO PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP)
-#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
-#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
-
-#define GPIO158_GPIO PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP)
-#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
-#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
-
-#define GPIO159_GPIO PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP)
-#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
-#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
-
-#define GPIO160_GPIO PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP)
-#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
-#define GPIO160_NONE PIN_CFG(160, ALT_C)
-
-#define GPIO161_GPIO PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN)
-#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
-#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
-
-#define GPIO162_GPIO PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN)
-#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
-#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
-
-#define GPIO163_GPIO PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN)
-#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
-#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
-
-#define GPIO164_GPIO PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP)
-#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
-#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
-
-#define GPIO165_GPIO PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP)
-#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
-#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
-
-#define GPIO166_GPIO PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP)
-#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
-#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
-
-#define GPIO167_GPIO PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP)
-#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
-#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
-
-#define GPIO168_GPIO PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP)
-#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
-#define GPIO168_NONE PIN_CFG(168, ALT_C)
-
-#define GPIO169_GPIO PIN_CFG(169, GPIO)
-#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
-#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
-#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
-
-#define GPIO170_GPIO PIN_CFG(170, GPIO)
-#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
-#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
-#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
-
-#define GPIO171_GPIO PIN_CFG(171, GPIO)
-#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
-#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
-#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
-
-#define GPIO192_GPIO PIN_CFG(192, GPIO)
-#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
-
-#define GPIO193_GPIO PIN_CFG(193, GPIO)
-#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
-
-#define GPIO194_GPIO PIN_CFG(194, GPIO)
-#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
-
-#define GPIO195_GPIO PIN_CFG(195, GPIO)
-#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
-
-#define GPIO196_GPIO PIN_CFG(196, GPIO)
-#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
-
-#define GPIO197_GPIO PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A)
-
-#define GPIO198_GPIO PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A)
-
-#define GPIO199_GPIO PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A)
-
-#define GPIO200_GPIO PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A)
-
-#define GPIO201_GPIO PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A)
-
-#define GPIO202_GPIO PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A)
-#define GPIO202_PWL PIN_CFG(202, ALT_B)
-#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
-
-#define GPIO203_GPIO PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A)
-
-#define GPIO204_GPIO PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A)
-
-#define GPIO205_GPIO PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A)
-
-#define GPIO206_GPIO PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A)
-
-#define GPIO207_GPIO PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A)
-
-#define GPIO208_GPIO PIN_CFG(208, GPIO)
-#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
-
-#define GPIO209_GPIO PIN_CFG(209, GPIO)
-#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
-#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
-
-#define GPIO210_GPIO PIN_CFG(210, GPIO)
-#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
-
-#define GPIO211_GPIO PIN_CFG(211, GPIO)
-#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
-
-#define GPIO212_GPIO PIN_CFG(212, GPIO)
-#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
-#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
-
-#define GPIO213_GPIO PIN_CFG(213, GPIO)
-#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
-#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
-
-#define GPIO214_GPIO PIN_CFG(214, GPIO)
-#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
-#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
-
-#define GPIO215_GPIO PIN_CFG(215, GPIO)
-#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
-#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
-#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
-
-#define GPIO216_GPIO PIN_CFG(216, GPIO)
-#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
-#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP)
-
-#define GPIO217_GPIO PIN_CFG(217, GPIO)
-#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
-#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
-#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
-
-#define GPIO218_GPIO PIN_CFG(218, GPIO)
-#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
-#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP)
-
-#define GPIO219_GPIO PIN_CFG(219, GPIO)
-#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
-#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
-
-#define GPIO220_GPIO PIN_CFG(220, GPIO)
-#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
-#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
-#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
-
-#define GPIO221_GPIO PIN_CFG(221, GPIO)
-#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
-#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
-
-#define GPIO222_GPIO PIN_CFG(222, GPIO)
-#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
-#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
-
-#define GPIO223_GPIO PIN_CFG(223, GPIO)
-#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
-#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
-#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
-
-#define GPIO224_GPIO PIN_CFG(224, GPIO)
-#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
-#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
-#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
-
-#define GPIO225_GPIO PIN_CFG(225, GPIO)
-#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
-#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
-#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
-
-#define GPIO226_GPIO PIN_CFG(226, GPIO)
-#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
-#define GPIO226_PWL PIN_CFG(226, ALT_B)
-#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
-
-#define GPIO227_GPIO PIN_CFG(227, GPIO)
-#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
-
-#define GPIO228_GPIO PIN_CFG(228, GPIO)
-#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
-
-#define GPIO229_GPIO PIN_CFG(229, GPIO)
-#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
-#define GPIO229_PWL PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP)
-
-#define GPIO230_GPIO PIN_CFG(230, GPIO)
-#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
-#define GPIO230_PWL PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP)
-
-#define GPIO256_GPIO PIN_CFG(256, GPIO)
-#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
-
-#define GPIO257_GPIO PIN_CFG(257, GPIO)
-#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
-
-#define GPIO258_GPIO PIN_CFG(258, GPIO)
-#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
-#define GPIO258_NONE PIN_CFG(258, ALT_B)
-#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
-
-#define GPIO259_GPIO PIN_CFG(259, GPIO)
-#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
-
-#define GPIO260_GPIO PIN_CFG(260, GPIO)
-#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
-
-#define GPIO261_GPIO PIN_CFG(261, GPIO)
-#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
-
-#define GPIO262_GPIO PIN_CFG(262, GPIO)
-#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
-
-#define GPIO263_GPIO PIN_CFG(263, GPIO)
-#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
-
-#define GPIO264_GPIO PIN_CFG(264, GPIO)
-#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
-
-#define GPIO265_GPIO PIN_CFG(265, GPIO)
-#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
-
-#define GPIO266_GPIO PIN_CFG(266, GPIO)
-#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
-
-#define GPIO267_GPIO PIN_CFG(267, GPIO)
-#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
-
-#endif
diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c
deleted file mode 100644
index c3061e2..0000000
--- a/board/st-ericsson/snowball/snowball.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/db8500_pincfg.h>
-#include <asm/arch/prcmu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-
-#ifdef CONFIG_MMC
-#include "../../../drivers/mmc/arm_pl180_mmci.h"
-#endif
-#include "db8500_pins.h"
-
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Memory controller register
- */
-#define DMC_BASE_ADDR 0x80156000
-#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
-
-/*
- * GPIO pin config common for MOP500/HREF boards
- */
-unsigned long gpio_cfg_common[] = {
- /* I2C */
- GPIO147_I2C0_SCL,
- GPIO148_I2C0_SDA,
- GPIO16_I2C1_SCL,
- GPIO17_I2C1_SDA,
- GPIO10_I2C2_SDA,
- GPIO11_I2C2_SCL,
- GPIO229_I2C3_SDA,
- GPIO230_I2C3_SCL,
-
- /* SSP0, to AB8500 */
- GPIO143_SSP0_CLK,
- GPIO144_SSP0_FRM,
- GPIO145_SSP0_RXD | PIN_PULL_DOWN,
- GPIO146_SSP0_TXD,
-
- /* MMC0 (MicroSD card) */
- GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
- GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
- GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
- GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
- GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
- GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
- GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
- GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
- GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
- GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
- GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
-
- /* MMC4 (On-board eMMC) */
- GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
- GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
- GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
- GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
- GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
- GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
- GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
- GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
- GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
- GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
- GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
-
- /* UART2, console */
- GPIO29_U2_RXD | PIN_INPUT_PULLUP,
- GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
- GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
- GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
-
- /*
- * USB, pin 256-267 USB, Is probably already setup correctly from
- * BootROM/boot stages, but we don't trust that and set it up anyway
- */
- GPIO256_USB_NXT,
- GPIO257_USB_STP,
- GPIO258_USB_XCLK,
- GPIO259_USB_DIR,
- GPIO260_USB_DAT7,
- GPIO261_USB_DAT6,
- GPIO262_USB_DAT5,
- GPIO263_USB_DAT4,
- GPIO264_USB_DAT3,
- GPIO265_USB_DAT2,
- GPIO266_USB_DAT1,
- GPIO267_USB_DAT0,
-};
-
-unsigned long gpio_cfg_snowball[] = {
- /* MMC0 (MicroSD card) */
- GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
- GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
- GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
-
- /* eMMC */
- GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
-
- /* LAN */
- GPIO131_SM_ADQ8,
- GPIO132_SM_ADQ9,
- GPIO133_SM_ADQ10,
- GPIO134_SM_ADQ11,
- GPIO135_SM_ADQ12,
- GPIO136_SM_ADQ13,
- GPIO137_SM_ADQ14,
- GPIO138_SM_ADQ15,
-
- /* RSTn_LAN */
- GPIO141_GPIO | PIN_OUTPUT_HIGH,
-};
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /*
- * Setup board (bd) and board-info (bi).
- * bi_arch_number: Unique id for this board. It will passed in r1 to
- * Linux startup code and is the machine_id.
- * bi_boot_params: Where this board expects params.
- */
- gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
- gd->bd->bi_boot_params = 0x00000100;
-
- /* Configure GPIO pins needed by U-boot */
- db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
-
- db8500_gpio_config_pins(gpio_cfg_snowball,
- ARRAY_SIZE(gpio_cfg_snowball));
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->ram_size = gd->bd->bi_dram[0].size =
- get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- return 0;
-}
-
-static int raise_ab8500_gpio16(void)
-{
- int ret;
-
- /* selection */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
- if (ret < 0)
- goto out;
-
- /* direction */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
- if (ret < 0)
- goto out;
-
- /* out */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
-
-out:
- return ret;
-}
-
-static int raise_ab8500_gpio26(void)
-{
- int ret;
-
- /* selection */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x2;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
- if (ret < 0)
- goto out;
-
- /* out */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x2;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
-
-out:
- return ret;
-}
-
-int board_late_init(void)
-{
- /* enable 3V3 for LAN controller */
- if (raise_ab8500_gpio26() >= 0) {
- /* Turn on FSMC device */
- writel(0x1, 0x8000f000);
- writel(0x1, 0x8000f008);
-
- /* setup FSMC for LAN controler */
- writel(0x305b, 0x80000000);
-
- /* run at the highest possible speed */
- writel(0x01010210, 0x80000004);
- } else
- printf("error: can't raise GPIO26\n");
-
- /* enable 3v6 for GBF chip */
- if ((raise_ab8500_gpio16() < 0))
- printf("error: cant' raise GPIO16\n");
-
- /* empty UART RX FIFO */
- while (tstc())
- (void) getc();
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-/*
- * emmc_host_init - initialize the emmc controller.
- * Configure GPIO settings, set initial clock and power for emmc slot.
- * Initialize mmc struct and register with mmc framework.
- */
-static int emmc_host_init(void)
-{
- struct pl180_mmc_host *host;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- host->base = (struct sdi_registers *)CFG_EMMC_BASE;
- host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
- SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
- strcpy(host->name, "EMMC");
- host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
- host->voltages = VOLTAGE_WINDOW_MMC;
- host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
- host->clock_max = ARM_MCLK / 2;
- host->clock_in = ARM_MCLK;
- host->version2 = 1;
-
- return arm_pl180_mmci_init(host);
-}
-
-/*
- * mmc_host_init - initialize the external mmc controller.
- * Configure GPIO settings, set initial clock and power for mmc slot.
- * Initialize mmc struct and register with mmc framework.
- */
-static int mmc_host_init(void)
-{
- struct pl180_mmc_host *host;
- u32 sdi_u32;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- host->base = (struct sdi_registers *)CFG_MMC_BASE;
- sdi_u32 = 0xBF;
- writel(sdi_u32, &host->base->power);
- host->pwr_init = 0xBF;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
- SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
- strcpy(host->name, "MMC");
- host->caps = MMC_MODE_8BIT;
- host->b_max = 0;
- host->voltages = VOLTAGE_WINDOW_SD;
- host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
- host->clock_max = ARM_MCLK / 2;
- host->clock_in = ARM_MCLK;
- host->version2 = 1;
-
- return arm_pl180_mmci_init(host);
-}
-
-/*
- * board_mmc_init - initialize all the mmc/sd host controllers.
- * Called by generic mmc framework.
- */
-int board_mmc_init(bd_t *bis)
-{
- int error;
-
- (void) bis;
-
- error = emmc_host_init();
- if (error) {
- printf("emmc_host_init() %d\n", error);
- return -1;
- }
-
- u8500_mmc_power_init();
-
- error = mmc_host_init();
- if (error) {
- printf("mmc_host_init() %d\n", error);
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_MMC */
diff --git a/board/st-ericsson/u8500/Kconfig b/board/st-ericsson/u8500/Kconfig
deleted file mode 100644
index 909f30d..0000000
--- a/board/st-ericsson/u8500/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_U8500_HREF
-
-config SYS_BOARD
- default "u8500"
-
-config SYS_VENDOR
- default "st-ericsson"
-
-config SYS_SOC
- default "u8500"
-
-config SYS_CONFIG_NAME
- default "u8500_href"
-
-endif
diff --git a/board/st-ericsson/u8500/MAINTAINERS b/board/st-ericsson/u8500/MAINTAINERS
deleted file mode 100644
index e2581eb..0000000
--- a/board/st-ericsson/u8500/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-U8500 BOARD
-#M: -
-S: Maintained
-F: board/st-ericsson/u8500/
-F: include/configs/u8500_href.h
-F: configs/u8500_href_defconfig
diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile
deleted file mode 100644
index d6c4280..0000000
--- a/board/st-ericsson/u8500/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) ST-Ericsson SA 2009
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ccflags-y += -D__RELEASE -D__STN_8500
-
-obj-y := u8500_href.o gpio.o
diff --git a/board/st-ericsson/u8500/gpio.c b/board/st-ericsson/u8500/gpio.c
deleted file mode 100644
index 2ddc7af..0000000
--- a/board/st-ericsson/u8500/gpio.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/gpio.h>
-
-static struct gpio_register *addr_gpio_register[] = {
- (void *)U8500_GPIO_0_BASE,
- (void *)U8500_GPIO_1_BASE,
- (void *)U8500_GPIO_2_BASE,
- (void *)U8500_GPIO_3_BASE,
- (void *)U8500_GPIO_4_BASE,
- (void *)U8500_GPIO_5_BASE,
- (void *)U8500_GPIO_6_BASE,
- (void *)U8500_GPIO_7_BASE,
- (void *)U8500_GPIO_8_BASE,
-};
-
-struct gpio_altfun_data altfun_table[] = {
- {
- .altfun = GPIO_ALT_I2C_0,
- .start = 147,
- .end = 148,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_I2C_1,
- .start = 16,
- .end = 17,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_I2C_2,
- .start = 10,
- .end = 11,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_I2C_3,
- .start = 229,
- .end = 230,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_UART_0_MODEM,
- .start = 0,
- .end = 3,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_UART_0_MODEM,
- .start = 33,
- .end = 36,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_UART_1,
- .start = 4,
- .end = 7,
- .cont = 0,
- .type =
- GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_UART_2,
- .start = 18,
- .end = 19,
- .cont = 1,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_UART_2,
- .start = 29,
- .end = 32,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_MSP_0,
- .start = 12,
- .end = 17,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MSP_0,
- .start = 21,
- .end = 21,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_MSP_1,
- .start = 33,
- .end = 36,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MSP_2,
- .start = 192,
- .end = 196,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_LCD_PANEL,
- .start = 64,
- .end = 93,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_LCD_PANEL,
- .start = 150,
- .end = 171,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_SD_CARD0,
- .start = 18,
- .end = 28,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MM_CARD0,
- .start = 18,
- .end = 32,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_USB_OTG,
- .start = 256,
- .end = 267,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_EMMC,
- .start = 197,
- .end = 207,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_POP_EMMC,
- .start = 128,
- .end = 138,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
-};
-
-/*
- * Static Function declarations
- */
-enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
- enum gpio_error error = GPIO_OK;
- u32 temp_reg;
-
- switch (config->mode) {
- case GPIO_ALTF_A:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_ALTF_B:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_ALTF_C:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_MODE_SOFTWARE:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
-
- switch (config->direction) {
- case GPIO_DIR_INPUT:
- writel(mask, &p_gpio_register->gpio_dirc);
- break;
- case GPIO_DIR_OUTPUT:
- writel(mask, &p_gpio_register->gpio_dirs);
- break;
- case GPIO_DIR_LEAVE_UNCHANGED:
- break;
- default:
- return GPIO_INVALID_PARAMETER;
- }
-
- break;
- case GPIO_MODE_LEAVE_UNCHANGED:
- break;
- default:
- return GPIO_INVALID_PARAMETER;
- }
- return error;
-}
-
-enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
- enum gpio_error error = GPIO_OK;
- u32 temp_reg;
-
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- writel(mask, &p_gpio_register->gpio_dirc);
-
- return error;
-}
-
-struct gpio_config altfun_pinconfig;
-enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func,
- int which_altfunc, char *dev_name)
-{
- int i, j, start, end;
- enum gpio_error error = -1;
-
- for (i = 0; i < ARRAY_SIZE(altfun_table); i++) {
- if (altfun_table[i].altfun != alt_func)
- continue;
-
- start = altfun_table[i].start;
- end = altfun_table[i].end;
- for (j = start; j <= end; j++) {
- if (which_altfunc == GPIO_ALTF_FIND)
- altfun_pinconfig.mode = altfun_table[i].type;
- else
- altfun_pinconfig.mode = which_altfunc;
- altfun_pinconfig.direction = GPIO_DIR_OUTPUT;
- altfun_pinconfig.dev_name = dev_name;
-
- if (which_altfunc != GPIO_ALTF_DISABLE)
- error = gpio_setpinconfig(j, &altfun_pinconfig);
- else
- error = gpio_resetgpiopin(j, dev_name);
- if (!error)
- continue;
- printf("GPIO %d configuration failure (nmdk_error:%d)",
- j, error);
- error = GPIO_INVALID_PARAMETER;
- return error;
- }
-
- if (!altfun_table[i].cont)
- break;
- }
- return error;
-}
-
-int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
-
- switch (value) {
- case GPIO_DATA_HIGH:
- writel(mask, &p_gpio_register->gpio_dats);
- break;
- case GPIO_DATA_LOW:
- writel(mask, &p_gpio_register->gpio_datc);
- break;
- default:
- printf("Invalid value passed in %s", __FUNCTION__);
- return GPIO_INVALID_PARAMETER;
- }
- return GPIO_OK;
-}
-
-int gpio_readpin(int pin_id, enum gpio_data *rv)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
-
- if ((readl(&p_gpio_register->gpio_dat) & mask) != 0)
- *rv = GPIO_DATA_HIGH;
- else
- *rv = GPIO_DATA_LOW;
- return GPIO_OK;
-}
-
-int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name)
-{
- return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name);
-}
-
-int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name)
-{
- return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name);
-}
diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c
deleted file mode 100644
index 9df499b..0000000
--- a/board/st-ericsson/u8500/u8500_href.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/prcmu.h>
-#ifdef CONFIG_MMC
-#include "../../../drivers/mmc/arm_pl180_mmci.h"
-#endif
-
-#define NOMADIK_PER4_BASE (0x80150000)
-#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
-#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
-
-/* Power, Reset, Clock Management Unit */
-/*
- * SVA: Smart Video Accelerator
- * SIA: Smart Imaging Accelerator
- * SGA: Smart Graphic accelerator
- * B2R2: Graphic blitter
- */
-#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
-#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
-#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
-#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
-#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
-#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
-#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
-#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
-#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
-#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
-#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
-#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
-#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
-#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
-#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
-#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
-#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
-#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
-#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
-
-#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
-#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
-#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
-#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
-#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
-
-#define PRCM_TCR (PRCMU_BASE + 0x1C8)
-
-/*
- * Memory controller register
- */
-#define DMC_BASE_ADDR 0x80156000
-#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
-
-int board_id; /* set in board_late_init() */
-
-/* PLLs for clock management registers */
-enum {
- GATED = 0,
- PLLSOC0, /* pllsw = 001, ffs() = 1 */
- PLLSOC1, /* pllsw = 010, ffs() = 2 */
- PLLDDR, /* pllsw = 100, ffs() = 3 */
- PLLARM,
-};
-
-static struct pll_freq_regs {
- int idx; /* index fror pll_name and pll_khz arrays */
- uint32_t addr;
-} pll_freq_regs[] = {
- {PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
- {PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
- {PLLDDR, PRCM_PLLDDR_FREQ_REG},
- {PLLARM, PRCM_PLLARM_FREQ_REG},
- {0, 0},
-};
-
-static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
-static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
-
-static struct clk_mgt_regs {
- uint32_t addr;
- uint32_t val;
- const char *descr;
-} clk_mgt_regs[] = {
- /* register content taken from bootrom settings */
- {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
- {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
- {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
- {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
- {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
- {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
- {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
- {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
- {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
- {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
- {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
- {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
- {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
- {0, 0, NULL},
-};
-
-static void init_regs(void);
-
-DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- init_regs();
- return 0;
-}
-
-int board_init(void)
-{
- uint32_t unused_cols_rows;
- unsigned int nrows;
- unsigned int ncols;
-
- gd->bd->bi_arch_number = 0x1A4;
- gd->bd->bi_boot_params = 0x00000100;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-
- /*
- * Assumption: 2 CS active, both CS have same layout.
- * 15 rows max, 11 cols max (controller spec).
- * memory chip has 8 banks, I/O width 32 bit.
- * The correct way would be to read MR#8: I/O width and density,
- * but this requires locking against the PRCMU firmware.
- * Simplified approach:
- * Read number of unused rows and columns from mem controller.
- * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
- */
- unused_cols_rows = readl(DMC_CTL_97);
- nrows = 15 - (unused_cols_rows & 0x07);
- ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
- gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
-
- icache_enable();
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_SIZE_1;
-
- return 0;
-}
-
-unsigned int addr_vall_arr[] = {
- 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
- 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
- 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
- 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
- 0x80157020, 0x00000150, /* I2C 48MHz clock */
- 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
- 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
- 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
- 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
- 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
- 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
- 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
- 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
- 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
- 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
- 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
- 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
- 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
- PRCM_APE_RESETN_SET_REG */
- 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
- 0xA03FF000, 0x00000003, /* USB */
- 0xA03FF008, 0x00000001, /* USB */
- 0xA03FE00C, 0x00000000, /* USB */
- 0xA03FE020, 0x00000FFF, /* USB */
- 0xA03FE024, 0x00000000 /* USB */
-};
-
-#ifdef CONFIG_BOARD_LATE_INIT
-/*
- * called after all initialisation were done, but before the generic
- * mmc_initialize().
- */
-int board_late_init(void)
-{
- uchar byte;
-
- /*
- * Determine and set board_id environment variable
- * 0: mop500, 1: href500
- * Above boards have different GPIO expander chips which we can
- * distinguish by the chip id.
- *
- * The board_id environment variable is needed for the Linux bootargs.
- */
- (void) i2c_set_bus_num(0);
- (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
- if (byte == 0x01) {
- board_id = 0;
- setenv("board_id", "0");
- } else {
- board_id = 1;
- setenv("board_id", "1");
- }
-#ifdef CONFIG_MMC
- u8500_mmc_power_init();
-
- /*
- * config extended GPIO pins for level shifter and
- * SDMMC_ENABLE
- */
- if (board_id == 0) {
- /* MOP500 */
- byte = 0x0c;
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
- } else {
- /* HREF */
- /* set the direction of GPIO KPY9 and KPY10 */
- byte = 0x06;
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
- /* must be a multibyte access */
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
- (uchar []) {0x06, 0x06}, 2);
- }
-#endif /* CONFIG_MMC */
- /*
- * Create a memargs variable which points uses either the memargs256 or
- * memargs512 environment variable, depending on the memory size.
- * memargs is used to build the bootargs, memargs256 and memargs512 are
- * stored in the environment.
- */
- if (gd->bd->bi_dram[0].size == 0x10000000) {
- setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
- setenv("mem", "256M");
- } else {
- setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
- setenv("mem", "512M");
- }
-
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
-{
- writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
- writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
-}
-
-static void init_regs(void)
-{
- /* FIXME Remove magic register array settings for ED also */
- struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
-
- /* Enable timers */
- writel(1 << 17, &prcmu->tcr);
-
- u8500_prcmu_enable(&prcmu->per1clk_mgt);
- u8500_prcmu_enable(&prcmu->per2clk_mgt);
- u8500_prcmu_enable(&prcmu->per3clk_mgt);
- u8500_prcmu_enable(&prcmu->per5clk_mgt);
- u8500_prcmu_enable(&prcmu->per6clk_mgt);
- u8500_prcmu_enable(&prcmu->per7clk_mgt);
-
- u8500_prcmu_enable(&prcmu->uartclk_mgt);
- u8500_prcmu_enable(&prcmu->i2cclk_mgt);
-
- u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
-
- u8500_clock_enable(1, 9, -1); /* GPIO0 */
-
- u8500_clock_enable(2, 11, -1); /* GPIO1 */
-
- u8500_clock_enable(3, 8, -1); /* GPIO2 */
- u8500_clock_enable(5, 1, -1); /* GPIO3 */
-
- u8500_clock_enable(3, 6, 6); /* UART2 */
-
- gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
- u8500_clock_enable(3, 3, 3); /* I2C0 */
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
- gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
- gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
- gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
-
- u8500_clock_enable(1, 5, 5); /* SDI0 */
- u8500_clock_enable(2, 4, 2); /* SDI4 */
-
- u8500_clock_enable(6, 7, -1); /* MTU0 */
- u8500_clock_enable(3, 4, 4); /* SDI2 */
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
- gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
-
- /*
- * Enabling clocks for all devices which are AMBA devices in the
- * kernel. Otherwise they will not get probe()'d because the
- * peripheral ID register will not be powered.
- */
-
- /* XXX: some of these differ between ED/V1 */
-
- u8500_clock_enable(1, 1, 1); /* UART1 */
- u8500_clock_enable(1, 0, 0); /* UART0 */
-
- u8500_clock_enable(3, 2, 2); /* SSP1 */
- u8500_clock_enable(3, 1, 1); /* SSP0 */
-
- u8500_clock_enable(2, 8, -1); /* SPI0 */
- u8500_clock_enable(2, 5, 3); /* MSP2 */
-}
-
-#ifdef CONFIG_MMC
-static int u8500_mmci_board_init(void)
-{
- enum gpio_error error;
- struct gpio_register *gpio_base_address;
-
- gpio_base_address = (void *)(U8500_GPIO_0_BASE);
- gpio_base_address->gpio_dats |= 0xFFC0000;
- gpio_base_address->gpio_pdis &= ~0xFFC0000;
-
- /* save the GPIO0 AFSELA register */
- error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
- if (error != GPIO_OK) {
- printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
- return -ENODEV;
- }
- return 0;
-}
-
-int board_mmc_init(bd_t *bd)
-{
- struct pl180_mmc_host *host;
-
- if (u8500_mmci_board_init())
- return -ENODEV;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- strcpy(host->name, "MMC");
- host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
- host->pwr_init = INIT_PWR;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
- host->voltages = VOLTAGE_WINDOW_MMC;
- host->caps = 0;
- host->clock_in = ARM_MCLK;
- host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
- host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
-
- return arm_pl180_mmci_init(host);
-}
-#endif
-
-
-/*
- * get_pll_freq_khz - return PLL frequency in kHz
- */
-static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
-{
- uint32_t idf, ldf, odf, seldiv, phi;
-
- /*
- * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
- * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
- * where:
- * IDF=R(2:0) (when R=000, IDF=1d)
- * LDF = 2*D(7:0) (D must be greater than or equal to 6)
- * ODF = N(5:0) (when N=000000, 0DF=1d)
- */
-
- idf = (freq_reg & 0x70000) >> 16;
- ldf = (freq_reg & 0xff) * 2;
- odf = (freq_reg & 0x3f00) >> 8;
- seldiv = (freq_reg & 0x01000000) >> 24;
- phi = (inclk_khz * ldf) / (2 * odf * idf);
- if (seldiv)
- phi = phi/2;
-
- return phi;
-}
-
-int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uint32_t inclk_khz;
- uint32_t reg, phi;
- uint32_t clk_khz;
- unsigned int clk_sel;
- struct clk_mgt_regs *clks = clk_mgt_regs;
- struct pll_freq_regs *plls = pll_freq_regs;
-
- /*
- * Go through list of PLLs.
- * Initialise pll out frequency array (pll_khz) and print frequency.
- */
- inclk_khz = 38400; /* 38.4 MHz */
- while (plls->addr) {
- reg = readl(plls->addr);
- phi = get_pll_freq_khz(inclk_khz, reg);
- pll_khz[plls->idx] = phi;
- printf("%s PLL out frequency: %d.%d Mhz\n",
- pll_name[plls->idx], phi/1000, phi % 1000);
- plls++;
- }
-
- /* check ARM clock source */
- reg = readl(PRCM_ARM_CHGCLKREQ_REG);
- printf("A9 running on %s\n",
- (reg & 1) ? "external clock" : "ARM PLL");
-
- /* go through list of clk_mgt_reg */
- printf("\n%19s %9s %7s %9s enabled\n",
- "name(addr)", "value", "PLL", "CLK[MHz]");
- while (clks->addr) {
- reg = readl(clks->addr);
-
- /* convert bit position into array index */
- clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
-
- if (reg & 0x200)
- clk_khz = 38400; /* CLK38 is set */
- else if ((reg & 0x1f) == 0)
- /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
- clk_khz = 0;
- else
- clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
-
- printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
- clks->descr, clks->addr, reg, pll_name[clk_sel],
- clk_khz / 1000, clk_khz % 1000,
- (reg & 0x100) ? "ena" : "dis");
- clks++;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- clkinfo, 1, 1, do_clkinfo,
- "print clock info",
- ""
-);
diff --git a/configs/snowball_defconfig b/configs/snowball_defconfig
deleted file mode 100644
index e73bc48..0000000
--- a/configs/snowball_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_SNOWBALL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U8500 $ "
diff --git a/configs/u8500_href_defconfig b/configs/u8500_href_defconfig
deleted file mode 100644
index 0aebc78..0000000
--- a/configs/u8500_href_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_U8500_HREF=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U8500 $ "
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
deleted file mode 100644
index de03e76..0000000
--- a/include/configs/snowball.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * #define DEBUG 1
- */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SNOWBALL
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_U8500
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-
-/*-----------------------------------------------------------------------
- * Size of environment and malloc() pool
- */
-/*
- * If you use U-Boot as crash kernel, make sure that it does not overwrite
- * information saved by kexec during panic. Kexec expects the start
- * address of the executable 32K above "crashkernel" address.
- */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (8*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_OFFSET 0x0118000
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
-
-/*
- * PL011 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_SERIAL_RLCR
-#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
-/*
- * U8500 UART registers base for 3 serial devices
- */
-#define CFG_UART0_BASE 0x80120000
-#define CFG_UART1_BASE 0x80121000
-#define CFG_UART2_BASE 0x80007000
-#define CFG_SERIAL0 CFG_UART0_BASE
-#define CFG_SERIAL1 CFG_UART1_BASE
-#define CFG_SERIAL2 CFG_UART2_BASE
-#define CONFIG_PL011_CLOCK 38400000
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
- (void *)CFG_SERIAL2 }
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Devices and file systems
- */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/*
- * Commands
- */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY 1
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-"mmc dev 1; " \
- "if run loadbootscript; " \
- "then run bootscript; " \
- "else " \
- "if run mmcload; " \
- "then run mmcboot; " \
- "else " \
- "mmc dev 0; " \
- "if run emmcloadbootscript; " \
- "then run bootscript; " \
- "else " \
- "if run emmcload; " \
- "then run emmcboot; " \
- "else " \
- "echo No media to boot from; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "fi; "
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr=0x00100000\0" \
- "console=ttyAMA2,115200n8\0" \
- "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
- "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript " \
- "from mmc ...; source ${loadaddr}\0" \
- "memargs256=mem=96M at 0 mem_modem=32M at 96M mem=32M at 128M " \
- "hwmem=22M at 160M pmem_hwb=42M at 182M mem_mali=32 at 224M\0" \
- "memargs512=mem=96M at 0 mem_modem=32M at 96M hwmem=32M at 128M " \
- "mem=64M at 160M mem_mali=32M at 224M " \
- "pmem_hwb=128M at 256M mem=128M at 384M\0" \
- "memargs1024=mem=128M at 0 mali.mali_mem=32M at 128M " \
- "hwmem=168M at M160M mem=48M at 328M " \
- "mem_issw=1M at 383M mem=640M at 384M\0" \
- "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
- "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
- "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
- "commonargs=setenv bootargs console=${console} " \
- "vmalloc=300M\0" \
- "emmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p3 " \
- "rootwait\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console}\0" \
- "emmcboot=echo Booting from eMMC ...; " \
- "run commonargs emmcargs memargs; " \
- "bootm ${loadaddr}\0" \
- "mmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk1p2 " \
- "rootwait earlyprintk\0" \
- "mmcboot=echo Booting from external MMC ...; " \
- "run commonargs mmcargs memargs; " \
- "bootm ${loadaddr}\0" \
- "fdt_high=0x2BC00000\0" \
- "stdout=serial,usbtty\0" \
- "stdin=serial,usbtty\0" \
- "stderr=serial,usbtty\0"
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SETUP_MEMORY_TAGS 2
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-
-/*
- * additions for new relocation code
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/* landing address before relocation */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x0
-#endif
-
-/*
- * MMC related configs
- */
-#define CONFIG_ARM_PL180_MMCI
-#define MMC_BLOCK_SIZE 512
-#define CFG_EMMC_BASE 0x80114000
-#define CFG_MMC_BASE 0x80126000
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */
-
-
-/*
- * U8500 GPIO register base for 9 banks
- */
-#define CONFIG_DB8500_GPIO
-#define CFG_GPIO_0_BASE 0x8012E000
-#define CFG_GPIO_1_BASE 0x8012E080
-#define CFG_GPIO_2_BASE 0x8000E000
-#define CFG_GPIO_3_BASE 0x8000E080
-#define CFG_GPIO_4_BASE 0x8000E100
-#define CFG_GPIO_5_BASE 0x8000E180
-#define CFG_GPIO_6_BASE 0x8011E000
-#define CFG_GPIO_7_BASE 0x8011E080
-#define CFG_GPIO_8_BASE 0xA03FE000
-
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
deleted file mode 100644
index a8cc030..0000000
--- a/include/configs/u8500_href.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_U8500
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Size of malloc() pool
- */
-#ifdef CONFIG_BOOT_SRAM
-#define CONFIG_ENV_SIZE (32*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024)
-#else
-#define CONFIG_ENV_SIZE (128*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#endif
-
-/*
- * PL011 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_SERIAL_RLCR
-#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
-/*
- * U8500 UART registers base for 3 serial devices
- */
-#define CFG_UART0_BASE 0x80120000
-#define CFG_UART1_BASE 0x80121000
-#define CFG_UART2_BASE 0x80007000
-#define CFG_SERIAL0 CFG_UART0_BASE
-#define CFG_SERIAL1 CFG_UART1_BASE
-#define CFG_SERIAL2 CFG_UART2_BASE
-#define CONFIG_PL011_CLOCK 38400000
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
- (void *)CFG_SERIAL2 }
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Devices and file systems
- */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/*
- * Commands
- */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
-
-#ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY 1
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "run emmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr=0x00100000\0" \
- "console=ttyAMA2,115200n8\0" \
- "memargs256=mem=96M at 0 mem_modem=32M at 96M mem=30M at 128M " \
- "pmem=22M at 158M pmem_hwb=44M at 180M mem_mali=32 at 224M\0" \
- "memargs512=mem=96M at 0 mem_modem=32M at 96M mem=44M at 128M " \
- "pmem=22M at 172M mem=30M at 194M mem_mali=32M at 224M " \
- "pmem_hwb=54M at 256M mem=202M at 310M\0" \
- "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \
- "init=init " \
- "board_id=${board_id} " \
- "logo.${logo} " \
- "startup_graphics=${startup_graphics}\0" \
- "emmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p2 " \
- "rootdelay=1\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console}\0" \
- "emmcboot=echo Booting from eMMC ...; " \
- "run commonargs emmcargs addcons memargs;" \
- "mmc read 0 ${loadaddr} 0xA0000 0x4000;" \
- "bootm ${loadaddr}\0" \
- "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \
- "source ${loadaddr}\0" \
- "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \
- "usbtty=cdc_acm\0" \
- "stdout=serial,usbtty\0" \
- "stdin=serial,usbtty\0" \
- "stderr=serial,usbtty\0"
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SETUP_MEMORY_TAGS 2
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-
-/*
- * I2C
- */
-#define CONFIG_U8500_I2C
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */
-#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000
-#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000
-#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000
-#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000
-#define CONFIG_SYS_U8500_I2C_BUS_MAX 4
-
-#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */
-#define CONFIG_TC35892_GPIO
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */
-
-/*
- * additions for new relocation code
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/* landing address before relocation */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x0
-#endif
-
-/*
- * MMC related configs
- * NB Only externa SD slot is currently supported
- */
-#define MMC_BLOCK_SIZE 512
-#define CONFIG_ARM_PL180_MMCI
-#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */
-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
-#define CONFIG_MMC_DEV_NUM 1
-
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET 0x13F80000
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
- management unit */
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (3 preceding siblings ...)
2015-08-31 1:18 ` [U-Boot] [PATCH 04/45] arm: Remove snowball and u8500_href boards Simon Glass
@ 2015-08-31 1:18 ` Simon Glass
2015-09-01 14:44 ` Stefano Babic
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 06/45] arm: Remove d2net_v2 defconfig file Simon Glass
` (40 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:18 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
sffsdr, sonata.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-davinci/Kconfig | 36 ----
board/davinci/dm355evm/Kconfig | 12 --
board/davinci/dm355evm/MAINTAINERS | 6 -
board/davinci/dm355evm/Makefile | 10 -
board/davinci/dm355evm/config.mk | 11 -
board/davinci/dm355evm/dm355evm.c | 144 -------------
board/davinci/dm355leopard/Kconfig | 12 --
board/davinci/dm355leopard/MAINTAINERS | 6 -
board/davinci/dm355leopard/Makefile | 10 -
board/davinci/dm355leopard/config.mk | 6 -
board/davinci/dm355leopard/dm355leopard.c | 86 --------
board/davinci/dm365evm/Kconfig | 12 --
board/davinci/dm365evm/MAINTAINERS | 6 -
board/davinci/dm365evm/Makefile | 10 -
board/davinci/dm365evm/config.mk | 11 -
board/davinci/dm365evm/dm365evm.c | 139 ------------
board/davinci/dm6467evm/Kconfig | 12 --
board/davinci/dm6467evm/MAINTAINERS | 7 -
board/davinci/dm6467evm/Makefile | 10 -
board/davinci/dm6467evm/config.mk | 2 -
board/davinci/dm6467evm/dm6467evm.c | 76 -------
board/davinci/dvevm/Kconfig | 12 --
board/davinci/dvevm/MAINTAINERS | 6 -
board/davinci/dvevm/Makefile | 11 -
board/davinci/dvevm/board_init.S | 16 --
board/davinci/dvevm/config.mk | 39 ----
board/davinci/dvevm/dvevm.c | 91 --------
board/davinci/ea20/Kconfig | 12 --
board/davinci/ea20/MAINTAINERS | 6 -
board/davinci/ea20/Makefile | 10 -
board/davinci/ea20/ea20.c | 339 ------------------------------
board/davinci/schmoogie/Kconfig | 12 --
board/davinci/schmoogie/MAINTAINERS | 6 -
board/davinci/schmoogie/Makefile | 11 -
board/davinci/schmoogie/board_init.S | 16 --
board/davinci/schmoogie/config.mk | 39 ----
board/davinci/schmoogie/schmoogie.c | 119 -----------
board/davinci/sffsdr/Kconfig | 12 --
board/davinci/sffsdr/MAINTAINERS | 6 -
board/davinci/sffsdr/Makefile | 11 -
board/davinci/sffsdr/board_init.S | 16 --
board/davinci/sffsdr/config.mk | 23 --
board/davinci/sffsdr/sffsdr.c | 132 ------------
board/davinci/sonata/Kconfig | 12 --
board/davinci/sonata/MAINTAINERS | 6 -
board/davinci/sonata/Makefile | 11 -
board/davinci/sonata/board_init.S | 87 --------
board/davinci/sonata/config.mk | 39 ----
board/davinci/sonata/sonata.c | 87 --------
configs/davinci_dm355evm_defconfig | 9 -
configs/davinci_dm355leopard_defconfig | 9 -
configs/davinci_dm365evm_defconfig | 9 -
configs/davinci_dm6467Tevm_defconfig | 9 -
configs/davinci_dm6467evm_defconfig | 10 -
configs/davinci_dvevm_defconfig | 9 -
configs/davinci_schmoogie_defconfig | 9 -
configs/davinci_sffsdr_defconfig | 9 -
configs/davinci_sonata_defconfig | 7 -
configs/ea20_defconfig | 8 -
include/configs/davinci_dm355evm.h | 195 -----------------
include/configs/davinci_dm355leopard.h | 140 ------------
include/configs/davinci_dm365evm.h | 220 -------------------
include/configs/davinci_dm6467evm.h | 138 ------------
include/configs/davinci_dvevm.h | 216 -------------------
include/configs/davinci_schmoogie.h | 136 ------------
include/configs/davinci_sffsdr.h | 129 ------------
include/configs/davinci_sonata.h | 187 ----------------
include/configs/ea20.h | 308 ---------------------------
68 files changed, 3568 deletions(-)
delete mode 100644 board/davinci/dm355evm/Kconfig
delete mode 100644 board/davinci/dm355evm/MAINTAINERS
delete mode 100644 board/davinci/dm355evm/Makefile
delete mode 100644 board/davinci/dm355evm/config.mk
delete mode 100644 board/davinci/dm355evm/dm355evm.c
delete mode 100644 board/davinci/dm355leopard/Kconfig
delete mode 100644 board/davinci/dm355leopard/MAINTAINERS
delete mode 100644 board/davinci/dm355leopard/Makefile
delete mode 100644 board/davinci/dm355leopard/config.mk
delete mode 100644 board/davinci/dm355leopard/dm355leopard.c
delete mode 100644 board/davinci/dm365evm/Kconfig
delete mode 100644 board/davinci/dm365evm/MAINTAINERS
delete mode 100644 board/davinci/dm365evm/Makefile
delete mode 100644 board/davinci/dm365evm/config.mk
delete mode 100644 board/davinci/dm365evm/dm365evm.c
delete mode 100644 board/davinci/dm6467evm/Kconfig
delete mode 100644 board/davinci/dm6467evm/MAINTAINERS
delete mode 100644 board/davinci/dm6467evm/Makefile
delete mode 100644 board/davinci/dm6467evm/config.mk
delete mode 100644 board/davinci/dm6467evm/dm6467evm.c
delete mode 100644 board/davinci/dvevm/Kconfig
delete mode 100644 board/davinci/dvevm/MAINTAINERS
delete mode 100644 board/davinci/dvevm/Makefile
delete mode 100644 board/davinci/dvevm/board_init.S
delete mode 100644 board/davinci/dvevm/config.mk
delete mode 100644 board/davinci/dvevm/dvevm.c
delete mode 100644 board/davinci/ea20/Kconfig
delete mode 100644 board/davinci/ea20/MAINTAINERS
delete mode 100644 board/davinci/ea20/Makefile
delete mode 100644 board/davinci/ea20/ea20.c
delete mode 100644 board/davinci/schmoogie/Kconfig
delete mode 100644 board/davinci/schmoogie/MAINTAINERS
delete mode 100644 board/davinci/schmoogie/Makefile
delete mode 100644 board/davinci/schmoogie/board_init.S
delete mode 100644 board/davinci/schmoogie/config.mk
delete mode 100644 board/davinci/schmoogie/schmoogie.c
delete mode 100644 board/davinci/sffsdr/Kconfig
delete mode 100644 board/davinci/sffsdr/MAINTAINERS
delete mode 100644 board/davinci/sffsdr/Makefile
delete mode 100644 board/davinci/sffsdr/board_init.S
delete mode 100644 board/davinci/sffsdr/config.mk
delete mode 100644 board/davinci/sffsdr/sffsdr.c
delete mode 100644 board/davinci/sonata/Kconfig
delete mode 100644 board/davinci/sonata/MAINTAINERS
delete mode 100644 board/davinci/sonata/Makefile
delete mode 100644 board/davinci/sonata/board_init.S
delete mode 100644 board/davinci/sonata/config.mk
delete mode 100644 board/davinci/sonata/sonata.c
delete mode 100644 configs/davinci_dm355evm_defconfig
delete mode 100644 configs/davinci_dm355leopard_defconfig
delete mode 100644 configs/davinci_dm365evm_defconfig
delete mode 100644 configs/davinci_dm6467Tevm_defconfig
delete mode 100644 configs/davinci_dm6467evm_defconfig
delete mode 100644 configs/davinci_dvevm_defconfig
delete mode 100644 configs/davinci_schmoogie_defconfig
delete mode 100644 configs/davinci_sffsdr_defconfig
delete mode 100644 configs/davinci_sonata_defconfig
delete mode 100644 configs/ea20_defconfig
delete mode 100644 include/configs/davinci_dm355evm.h
delete mode 100644 include/configs/davinci_dm355leopard.h
delete mode 100644 include/configs/davinci_dm365evm.h
delete mode 100644 include/configs/davinci_dm6467evm.h
delete mode 100644 include/configs/davinci_dvevm.h
delete mode 100644 include/configs/davinci_schmoogie.h
delete mode 100644 include/configs/davinci_sffsdr.h
delete mode 100644 include/configs/davinci_sonata.h
delete mode 100644 include/configs/ea20.h
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 681270d..790d177 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -22,33 +22,6 @@ config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
-config TARGET_DAVINCI_DM355EVM
- bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
- bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
- bool "DVEVM board"
-
-config TARGET_EA20
- bool "EA20 board"
-
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
- bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
- bool "Sonata board"
-
config TARGET_CALIMAIN
bool "Calimain board"
@@ -60,15 +33,6 @@ config SYS_SOC
source "board/enbw/enbw_cmc/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
source "board/omicron/calimain/Kconfig"
endif
diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig
deleted file mode 100644
index ec2c276..0000000
--- a/board/davinci/dm355evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM355EVM
-
-config SYS_BOARD
- default "dm355evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm355evm"
-
-endif
diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS
deleted file mode 100644
index c017e09..0000000
--- a/board/davinci/dm355evm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM355EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm355evm/
-F: include/configs/davinci_dm355evm.h
-F: configs/davinci_dm355evm_defconfig
diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile
deleted file mode 100644
index bcb7e6f..0000000
--- a/board/davinci/dm355evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm355evm.o
diff --git a/board/davinci/dm355evm/config.mk b/board/davinci/dm355evm/config.mk
deleted file mode 100644
index 9a06300..0000000
--- a/board/davinci/dm355evm/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Spectrum Digital DM355 EVM board
-# dm355evm board has 1 bank of 128 MB DDR RAM
-# Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
deleted file mode 100644
index e5a958f..0000000
--- a/board/davinci/dm355evm/dm355evm.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * With the DM355 EVM, u-boot is *always* a third stage loader,
- * unless a JTAG debugger handles the first two stages:
- *
- * - 1st stage is ROM Boot Loader (RBL), which searches for a
- * second stage loader in one of three places based on SW7:
- * NAND (with MMC/SD fallback), MMC/SD, or UART.
- *
- * - 2nd stage is User Boot Loader (UBL), using at most 30KB
- * of on-chip SRAM, responsible for lowlevel init, and for
- * loading the third stage loader into DRAM.
- *
- * - 3rd stage, that's us!
- */
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* We expect the UBL to have handled "lowlevel init", which
- * involves setting up at least:
- * - clocks
- * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
- * + clock divisors for those PLLs
- * + LPSC_DDR module enabled
- * + LPSC_TIMER0 module (still) enabled
- * - EMIF
- * + DDR init and timings
- * + AEMIF timings (for NAND and DM9000)
- * - pinmux
- *
- * Some of that is repeated here, mostly as a precaution.
- */
-
- /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
- * could be too if we used A12 as a GPIO during NAND chipselect
- * (and Linux did too), letting us control the LED on A7/GPIO61.
- */
- REG(PINMUX2) = 0x0c08;
-
- /* UART0 may still be in SyncReset if we didn't boot from UART */
- davinci_enable_uart0();
-
- /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
- lpsc_on(DAVINCI_LPSC_TPCC);
- lpsc_on(DAVINCI_LPSC_TPTC0);
- lpsc_on(DAVINCI_LPSC_TPTC1);
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-
-static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long wbase = (unsigned long) this->IO_ADDR_W;
- unsigned long rbase = (unsigned long) this->IO_ADDR_R;
-
- if (chip == 1) {
- __set_bit(14, &wbase);
- __set_bit(14, &rbase);
- } else {
- __clear_bit(14, &wbase);
- __clear_bit(14, &rbase);
- }
- this->IO_ADDR_W = (void *)wbase;
- this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_dm355evm_select_chip;
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .input_clk = 108000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_1,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 108000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_1,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- /* Add slot-0 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd0);
- if (err)
- return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
- /* Add slot-1 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
- return err;
-}
-#endif
diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig
deleted file mode 100644
index ab4230a..0000000
--- a/board/davinci/dm355leopard/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM355LEOPARD
-
-config SYS_BOARD
- default "dm355leopard"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm355leopard"
-
-endif
diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS
deleted file mode 100644
index ed04d43..0000000
--- a/board/davinci/dm355leopard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM355LEOPARD BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm355leopard/
-F: include/configs/davinci_dm355leopard.h
-F: configs/davinci_dm355leopard_defconfig
diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile
deleted file mode 100644
index 7035429..0000000
--- a/board/davinci/dm355leopard/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm355leopard.o
diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk
deleted file mode 100644
index 28ff3f3..0000000
--- a/board/davinci/dm355leopard/config.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c
deleted file mode 100644
index 53902f9..0000000
--- a/board/davinci/dm355leopard/dm355leopard.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- struct davinci_gpio *gpio01_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
- struct davinci_gpio *gpio23_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
- struct davinci_gpio *gpio67_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
-
- gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* GIO 9 & 10 are used for IO */
- writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
-
- /* Interrupt set GIO 9 */
- writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
-
- /* set GIO 9 input */
- writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
-
- /* Both edge trigger GIO 9 */
- writel((readl(&gpio01_base->set_rising) | (1 << 9)),
- &gpio01_base->set_rising);
- writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
-
- /* output low */
- writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
- &gpio01_base->set_data);
-
- /* set GIO 10 output */
- writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
-
- /* output high */
- writel((readl(&gpio01_base->set_data) | (1 << 10)),
- &gpio01_base->set_data);
-
- /* set GIO 32 output */
- writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
-
- /* output High */
- writel((readl(&gpio23_base->set_data) | (1 << 0)),
- &gpio23_base->set_data);
-
- /* Enable UART1 MUX Lines */
- writel((readl(PINMUX0) & ~3), PINMUX0);
- writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
- writel((readl(&gpio67_base->set_data) | (1 << 6)),
- &gpio67_base->set_data);
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig
deleted file mode 100644
index 724c7b6..0000000
--- a/board/davinci/dm365evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM365EVM
-
-config SYS_BOARD
- default "dm365evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm365evm"
-
-endif
diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS
deleted file mode 100644
index 97c3ed3..0000000
--- a/board/davinci/dm365evm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM365EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm365evm/
-F: include/configs/davinci_dm365evm.h
-F: configs/davinci_dm365evm_defconfig
diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile
deleted file mode 100644
index d35d81c..0000000
--- a/board/davinci/dm365evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm365evm.o
diff --git a/board/davinci/dm365evm/config.mk b/board/davinci/dm365evm/config.mk
deleted file mode 100644
index 7b1e900..0000000
--- a/board/davinci/dm365evm/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Spectrum Digital DM365 EVM board
-# DM365 EVM board has 1 bank of 128 MB DDR RAM
-# Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
deleted file mode 100644
index 24bec56..0000000
--- a/board/davinci/dm365evm/dm365evm.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/gpio.h>
-#include <netdev.h>
-#include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-int board_eth_init(bd_t *bis)
-{
- uint8_t eeprom_enetaddr[6];
- int i;
- struct davinci_gpio *gpio1_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
-
- /* Configure PINMUX 3 to enable EMAC pins */
- writel((readl(PINMUX3) | 0x1affff), PINMUX3);
-
- /* Configure GPIO20 as output */
- writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
-
- /* Toggle GPIO 20 */
- for (i = 0; i < 20; i++) {
- /* GPIO 20 low */
- writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
- &gpio1_base->out_data);
-
- udelay(1000);
-
- /* GPIO 20 high */
- writel((readl(&gpio1_base->out_data) | (1 << 20)),
- &gpio1_base->out_data);
- }
-
- /* Configure I2C pins so that EEPROM can be read */
- writel((readl(PINMUX3) | 0x01400000), PINMUX3);
-
- /* Read Ethernet MAC address from EEPROM */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- davinci_emac_initialize();
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long wbase = (unsigned long) this->IO_ADDR_W;
- unsigned long rbase = (unsigned long) this->IO_ADDR_R;
-
- if (chip == 1) {
- __set_bit(14, &wbase);
- __set_bit(14, &rbase);
- } else {
- __clear_bit(14, &wbase);
- __clear_bit(14, &rbase);
- }
- this->IO_ADDR_W = (void *)wbase;
- this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_dm365evm_select_chip;
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .input_clk = 121500000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 121500000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- /* Add slot-0 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd0);
- if (err)
- return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-#define PUPDCTL1 0x01c4007c
- /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
- writel((readl(PINMUX4) | 0x55400000), PINMUX4);
- writel((readl(PINMUX0) | 0x00010000), PINMUX0);
-
- /* Configure MMC/SD pins as pullup */
- writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
-
- /* Add slot-1 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
- return err;
-}
-#endif
diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig
deleted file mode 100644
index 56d2ab4..0000000
--- a/board/davinci/dm6467evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM6467EVM
-
-config SYS_BOARD
- default "dm6467evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm6467evm"
-
-endif
diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS
deleted file mode 100644
index 8ca53c4..0000000
--- a/board/davinci/dm6467evm/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-DM6467EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm6467evm/
-F: include/configs/davinci_dm6467evm.h
-F: configs/davinci_dm6467evm_defconfig
-F: configs/davinci_dm6467Tevm_defconfig
diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile
deleted file mode 100644
index acbbdd5..0000000
--- a/board/davinci/dm6467evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm6467evm.o
diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk
deleted file mode 100644
index 3751043..0000000
--- a/board/davinci/dm6467evm/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
deleted file mode 100644
index e51cc9e..0000000
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define REV_DM6467EVM 0
-#define REV_DM6467TEVM 1
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3] System clock frequency
- * 0000b - 27 MHz
- * 0001b - 33 MHz
- */
-u32 get_board_rev(void)
-{
-
-#ifdef CONFIG_DAVINCI_DM6467TEVM
- return REV_DM6467TEVM;
-#else
- return REV_DM6467EVM;
-#endif
-
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
- lpsc_on(DAVINCI_DM646X_LPSC_UART0);
- lpsc_on(DAVINCI_DM646X_LPSC_I2C);
- lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-
- /* Enable GIO3.3V cells used for EMAC */
- REG(VDD3P3V_PWDN) = 0x80000c0;
-
- /* Select UART function on UART0 */
- REG(PINMUX0) &= ~(0x0000003f << 18);
- REG(PINMUX1) &= ~(0x00000003);
-
- return 0;
-}
-
-#if defined(CONFIG_DRIVER_TI_EMAC)
-
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig
deleted file mode 100644
index 3f0ef82..0000000
--- a/board/davinci/dvevm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DVEVM
-
-config SYS_BOARD
- default "dvevm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dvevm"
-
-endif
diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS
deleted file mode 100644
index a718b90..0000000
--- a/board/davinci/dvevm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DVEVM BOARD
-#M: -
-S: Maintained
-F: board/davinci/dvevm/
-F: include/configs/davinci_dvevm.h
-F: configs/davinci_dvevm_defconfig
diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile
deleted file mode 100644
index 7ade325..0000000
--- a/board/davinci/dvevm/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dvevm.o
-obj-y += board_init.o
diff --git a/board/davinci/dvevm/board_init.S b/board/davinci/dvevm/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/dvevm/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
diff --git a/board/davinci/dvevm/config.mk b/board/davinci/dvevm/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/dvevm/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
deleted file mode 100644
index c34bde4..0000000
--- a/board/davinci/dvevm/dvevm.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
- lpsc_on(DAVINCI_LPSC_USB);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- uint8_t video_mode;
- uint8_t eeprom_enetaddr[6];
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- i2c_read(0x39, 0x00, 1, &video_mode, 1);
-
- setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
-
- return(0);
-}
-
-#ifdef CONFIG_USB_DAVINCI
-
-/* IO Expander I2C address and USB VBUS enable mask */
-#define IOEXP_I2C_ADDR 0x3A
-#define IOEXP_VBUSEN_MASK 1
-
-/*
- * This function enables USB VBUS by writting to IO expander using I2C.
- * Note that the I2C is already initialized at this stage. This
- * function is used by davinci specific USB wrapper code.
- */
-void enable_vbus(void)
-{
- uchar data; /* IO Expander data to enable VBUS */
-
- /* Write to IO expander to enable VBUS */
- i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
- data &= ~IOEXP_VBUSEN_MASK;
- i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
-}
-#endif
diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig
deleted file mode 100644
index ae5b16e..0000000
--- a/board/davinci/ea20/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_EA20
-
-config SYS_BOARD
- default "ea20"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "ea20"
-
-endif
diff --git a/board/davinci/ea20/MAINTAINERS b/board/davinci/ea20/MAINTAINERS
deleted file mode 100644
index 5c300a3..0000000
--- a/board/davinci/ea20/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EA20 BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/davinci/ea20/
-F: include/configs/ea20.h
-F: configs/ea20_defconfig
diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile
deleted file mode 100644
index a5311c4..0000000
--- a/board/davinci/ea20/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ea20.o
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
deleted file mode 100644
index 66804d7..0000000
--- a/board/davinci/ea20/ea20.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic at denx.de
- *
- * Based on da850evm.c, original Copyrights follow:
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/gpio.h>
-#include "../../../drivers/video/da8xx-fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct da8xx_panel lcd_panel = {
- /* Casio COM57H531x */
- .name = "Casio_COM57H531x",
- .width = 640,
- .height = 480,
- .hfp = 12,
- .hbp = 144,
- .hsw = 30,
- .vfp = 10,
- .vbp = 35,
- .vsw = 3,
- .pxl_clk = 25000000,
- .invert_pxl_clk = 0,
-};
-
-static const struct display_panel disp_panel = {
- QVGA,
- 16,
- 16,
- COLOR_ACTIVE,
-};
-
-static const struct lcd_ctrl_config lcd_cfg = {
- &disp_panel,
- .ac_bias = 255,
- .ac_bias_intrpt = 0,
- .dma_burst_sz = 16,
- .bpp = 16,
- .fdd = 255,
- .tft_alt_mode = 0,
- .stn_565_mode = 0,
- .mono_8bit_mode = 0,
- .invert_line_clock = 1,
- .invert_frm_clock = 1,
- .sync_edge = 0,
- .sync_ctrl = 1,
- .raster_order = 0,
-};
-
-/* SPI0 pin muxer settings */
-static const struct pinmux_config spi1_pins[] = {
- { pinmux(5), 1, 1 },
- { pinmux(5), 1, 2 },
- { pinmux(5), 1, 4 },
- { pinmux(5), 1, 5 }
-};
-
-/* I2C pin muxer settings */
-static const struct pinmux_config i2c_pins[] = {
- { pinmux(4), 2, 2 },
- { pinmux(4), 2, 3 }
-};
-
-/* UART0 pin muxer settings */
-static const struct pinmux_config uart_pins[] = {
- { pinmux(3), 2, 7 },
- { pinmux(3), 2, 6 },
- { pinmux(3), 2, 4 },
- { pinmux(3), 2, 5 }
-};
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define HAS_RMII 1
-static const struct pinmux_config emac_pins[] = {
- { pinmux(14), 8, 2 },
- { pinmux(14), 8, 3 },
- { pinmux(14), 8, 4 },
- { pinmux(14), 8, 5 },
- { pinmux(14), 8, 6 },
- { pinmux(14), 8, 7 },
- { pinmux(15), 8, 1 },
- { pinmux(4), 8, 0 },
- { pinmux(4), 8, 1 }
-};
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-const struct pinmux_config nand_pins[] = {
- { pinmux(7), 1, 0}, /* CS2 */
- { pinmux(7), 0, 1}, /* CS3 in three state*/
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
- { pinmux(6), 1, 0 } /* EMA_CLK */
-};
-#endif
-
-const struct pinmux_config gpio_pins[] = {
- { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
- { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
- { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
- { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
- { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
-};
-
-const struct pinmux_config lcd_pins[] = {
- { pinmux(17), 2, 1 }, /* LCD_D_0 */
- { pinmux(17), 2, 0 }, /* LCD_D_1 */
- { pinmux(16), 2, 7 }, /* LCD_D_2 */
- { pinmux(16), 2, 6 }, /* LCD_D_3 */
- { pinmux(16), 2, 5 }, /* LCD_D_4 */
- { pinmux(16), 2, 4 }, /* LCD_D_5 */
- { pinmux(16), 2, 3 }, /* LCD_D_6 */
- { pinmux(16), 2, 2 }, /* LCD_D_7 */
- { pinmux(18), 2, 1 }, /* LCD_D_8 */
- { pinmux(18), 2, 0 }, /* LCD_D_9 */
- { pinmux(17), 2, 7 }, /* LCD_D_10 */
- { pinmux(17), 2, 6 }, /* LCD_D_11 */
- { pinmux(17), 2, 5 }, /* LCD_D_12 */
- { pinmux(17), 2, 4 }, /* LCD_D_13 */
- { pinmux(17), 2, 3 }, /* LCD_D_14 */
- { pinmux(17), 2, 2 }, /* LCD_D_15 */
- { pinmux(18), 2, 6 }, /* LCD_PCLK */
- { pinmux(19), 2, 0 }, /* LCD_HSYNC */
- { pinmux(19), 2, 1 }, /* LCD_VSYNC */
- { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
-};
-
-const struct pinmux_config halten_pin[] = {
- { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
-};
-
-static const struct pinmux_resource pinmuxes[] = {
-#ifdef CONFIG_SPI_FLASH
- PINMUX_ITEM(spi1_pins),
-#endif
- PINMUX_ITEM(uart_pins),
- PINMUX_ITEM(i2c_pins),
-#ifdef CONFIG_NAND_DAVINCI
- PINMUX_ITEM(nand_pins),
-#endif
-#ifdef CONFIG_VIDEO
- PINMUX_ITEM(lcd_pins),
-#endif
-};
-
-static const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART0 }, /* console */
- { DAVINCI_LPSC_GPIO },
- { DAVINCI_LPSC_LCDC }, /* LCD */
-};
-
-int board_early_init_f(void)
-{
- /* PinMux for GPIO */
- if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
- return 1;
-
- /* Set DISP_ON high to enable LCD output*/
- gpio_direction_output(97, 1);
-
- /* Set the RESETOUTn low */
- gpio_direction_output(111, 0);
-
- /* Set U0_SW0 low for UART0 as console*/
- gpio_direction_output(106, 0);
-
- /* Set U0_SW1 low for UART0 as console*/
- gpio_direction_output(108, 0);
-
- /* Set LCD_B_PWR low to power down LCD Backlight*/
- gpio_direction_output(102, 0);
-
-#ifndef CONFIG_USE_IRQ
- irq_init();
-#endif
-
- /*
- * NAND CS setup - cycle counts based on da850evm NAND timings in the
- * Linux kernel @ 25MHz EMIFA
- */
-#ifdef CONFIG_NAND_DAVINCI
- writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(1) |
- DAVINCI_ABCR_WHOLD(0) |
- DAVINCI_ABCR_RSETUP(0) |
- DAVINCI_ABCR_RSTROBE(1) |
- DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(0) |
- DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->ab1cr); /* CS2 */
-#endif
-
- /*
- * Power on required peripherals
- * ARM does not have access by default to PSC0 and PSC1
- * assuming here that the DSP bootloader has set the IOPU
- * such that PSC access is available to ARM
- */
- if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
- return 1;
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- writel(readl(&davinci_syscfg_regs->suspsrc) &
- ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART0),
- &davinci_syscfg_regs->suspsrc);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
- return 1;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
- if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
- return 1;
-
- davinci_emac_mii_mode_sel(HAS_RMII);
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
- /* enable the console UART */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart0_ctrl_regs->pwremu_mgmt);
-
- /*
- * Reconfigure the LCDC priority to the highest to ensure that
- * the throughput/latency requirements for the LCDC are met.
- */
- writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
- &davinci_syscfg_regs->mstpri[2]);
-
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-
-int board_late_init(void)
-{
- unsigned char buf[2];
- int ret;
-
- /* PinMux for HALTEN */
- if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
- return 1;
-
- /* Set HALTEN to high */
- gpio_direction_output(134, 1);
-
- /* Set fixed contrast settings for LCD via I2C potentiometer */
- buf[0] = 0x00;
- buf[1] = 0xd7;
- ret = i2c_write(0x2e, 6, 1, buf, 2);
- if (ret)
- puts("\nContrast Settings FAILED\n");
-
- /* Set LCD_B_PWR high to power up LCD Backlight*/
- gpio_set_value(102, 1);
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- /*
- * This board has a RMII PHY. However, the MDC line on the SOM
- * must not be disabled (there is no MII PHY on the
- * baseboard) via the GPIO2[6], because this pin
- * disables at the same time the SPI flash.
- */
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig
deleted file mode 100644
index 3581075..0000000
--- a/board/davinci/schmoogie/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SCHMOOGIE
-
-config SYS_BOARD
- default "schmoogie"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_schmoogie"
-
-endif
diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS
deleted file mode 100644
index 808e7fc..0000000
--- a/board/davinci/schmoogie/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SCHMOOGIE BOARD
-#M: -
-S: Maintained
-F: board/davinci/schmoogie/
-F: include/configs/davinci_schmoogie.h
-F: configs/davinci_schmoogie_defconfig
diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile
deleted file mode 100644
index e170d55..0000000
--- a/board/davinci/schmoogie/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := schmoogie.o
-obj-y += board_init.o
diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/schmoogie/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/schmoogie/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
deleted file mode 100644
index 741afc4..0000000
--- a/board/davinci/schmoogie/schmoogie.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- u_int8_t tmp[20], buf[10];
- int i = 0;
-
- /* Set serial number from UID chip */
- const u_int8_t crc_tbl[256] = {
- 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
- 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
- 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
- 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
- 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
- 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
- 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
- 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
- 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
- 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
- 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
- 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
- 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
- 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
- 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
- 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
- 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
- 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
- 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
- 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
- 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
- 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
- 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
- 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
- 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
- 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
- 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
- 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
- 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
- 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
- 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
- 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
- };
-
- /* Set serial number from UID chip */
- if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
- printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- } else {
- if (buf[0] != 0x70) {
- /* Device Family Code */
- printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- }
- }
- /* Now check CRC */
- tmp[0] = 0;
- for (i = 0; i < 8; i++)
- tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
-
- if (tmp[0] != 0) {
- printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- } else {
- /* CRC OK, set "serial" env variable */
- sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
- buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
- setenv("serial#", (char *)&tmp[0]);
- }
-
- return(0);
-}
diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig
deleted file mode 100644
index dc48f31..0000000
--- a/board/davinci/sffsdr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SFFSDR
-
-config SYS_BOARD
- default "sffsdr"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_sffsdr"
-
-endif
diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS
deleted file mode 100644
index 5c7e132..0000000
--- a/board/davinci/sffsdr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SFFSDR BOARD
-#M: -
-S: Maintained
-F: board/davinci/sffsdr/
-F: include/configs/davinci_sffsdr.h
-F: configs/davinci_sffsdr_defconfig
diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile
deleted file mode 100644
index 4ab30a4..0000000
--- a/board/davinci/sffsdr/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sffsdr.o
-obj-y += board_init.o
diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/sffsdr/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk
deleted file mode 100644
index 4fe9007..0000000
--- a/board/davinci/sffsdr/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
-# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
-#
-# Lyrtech SFF SDR board (ARM926EJS) cpu
-#
-# SFF SDR board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 87FF'FFFF
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
-# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
-#
-# we load ourself to 8400'0000 to provide at least 32MB spacing
-# between us and the Integrity kernel image
-CONFIG_SYS_TEXT_BASE = 0x84000000
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
deleted file mode 100644
index f6ab91e..0000000
--- a/board/davinci/sffsdr/sffsdr.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
-#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
-
-#define INTEGRITY_SYSCFG_OFFSET 0x7E8
-#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
-#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-/* Read ethernet MAC address from Integrity data structure inside EEPROM.
- * Returns 1 if found, 0 otherwise.
- */
-static int sffsdr_read_mac_address(uint8_t *buf)
-{
- u_int32_t value, mac[2], address;
-
- /* Read Integrity data structure checkword. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- if (value != INTEGRITY_CHECKWORD_VALUE)
- return 0;
-
- /* Read SYSCFG structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + (int) value; /* Address of SYSCFG structure. */
-
- /* Read NET CONFIG structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
- address += 12; /* Address of NET INTERFACE CONFIG structure. */
-
- /* Read NET INTERFACE CONFIG 2 structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
- * CONFIG 2 structure. */
-
- /* Read MAC address. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
- goto err;
-
- buf[0] = mac[0] >> 24;
- buf[1] = mac[0] >> 16;
- buf[2] = mac[0] >> 8;
- buf[3] = mac[0];
- buf[4] = mac[1] >> 24;
- buf[5] = mac[1] >> 16;
-
- return 1; /* Found */
-
-err:
- printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
- return 0;
-}
-
-/* Platform dependent initialisation. */
-int misc_init_r(void)
-{
- uint8_t i2cbuf;
- uint8_t eeprom_enetaddr[6];
-
- /* EMIF-A CS3 configuration for FPGA. */
- REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
-
- /* Configure I2C switch (PCA9543) to enable channel 0. */
- i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
- if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
- CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
- printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
- return 1;
- }
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (sffsdr_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- return(0);
-}
diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig
deleted file mode 100644
index 4440d95..0000000
--- a/board/davinci/sonata/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SONATA
-
-config SYS_BOARD
- default "sonata"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_sonata"
-
-endif
diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS
deleted file mode 100644
index 40659e5..0000000
--- a/board/davinci/sonata/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SONATA BOARD
-#M: -
-S: Maintained
-F: board/davinci/sonata/
-F: include/configs/davinci_sonata.h
-F: configs/davinci_sonata_defconfig
diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile
deleted file mode 100644
index 92e1a18..0000000
--- a/board/davinci/sonata/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sonata.o
-obj-y += board_init.o
diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S
deleted file mode 100644
index 0a47ad5..0000000
--- a/board/davinci/sonata/board_init.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
- * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
- * Visioneering if they reinvented the wheel once again to make sure :)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-#ifdef SONATA_BOARD_GPIOWP
- /* Set PINMUX0 to enable GPIO4 */
- ldr r0, _PINMUX0
- ldr r1, GPIO4_EN_MASK
- ldr r2, [r0]
- and r2, r2, r1
- str r2, [r0]
-
- /* Enable GPIO LPSC module */
- ldr r0, PTSTAT
-
-gpio_ptstat_loop1:
- ldr r2, [r0]
- tst r2, $0x00000001
- bne gpio_ptstat_loop1
-
- ldr r1, MDCTL_GPIO
- ldr r2, [r1]
- and r2, r2, $0xfffffff8
- orr r2, r2, $0x00000003
- str r2, [r1]
-
- orr r2, r2, $0x00000200
- str r2, [r1]
-
- ldr r1, PTCMD
- mov r2, $0x00000001
- str r2, [r1]
-
-gpio_ptstat_loop2:
- ldr r2, [r0]
- tst r2, $0x00000001
- bne gpio_ptstat_loop2
-
- ldr r0, MDSTAT_GPIO
-gpio_mdstat_loop:
- ldr r2, [r0]
- and r2, r2, $0x0000001f
- teq r2, $0x00000003
- bne gpio_mdstat_loop
-
- /* GPIO4 -> output */
- ldr r0, GPIO_DIR01
- mov r1, $0x10
- ldr r2, [r0]
- bic r2, r2, r0
- str r2, [r0]
-
- /* Set it to 0 (Write Protect) */
- ldr r0, GPIO_CLR_DATA01
- str r1, [r0]
-#endif
-
- mov pc, lr
-
-#ifdef SONATA_BOARD_GPIOWP
-.ltorg
-
-GPIO4_EN_MASK:
- .word 0xf77fffff
-MDCTL_GPIO:
- .word 0x01c41a68
-MDSTAT_GPIO:
- .word 0x01c41868
-GPIO_DIR01:
- .word 0x01c67010
-GPIO_CLR_DATA01:
- .word 0x01c6701c
-#endif
diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/sonata/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
deleted file mode 100644
index f5c3258..0000000
--- a/board/davinci/sonata/sonata.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- uint8_t eeprom_enetaddr[6];
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- return(0);
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-
-/* Set WP on deselect, write enable on select */
-static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
-{
-#define GPIO_SET_DATA01 0x01c67018
-#define GPIO_CLR_DATA01 0x01c6701c
-#define GPIO_NAND_WP (1 << 4)
-#ifdef SONATA_BOARD_GPIOWP
- if (chip < 0) {
- REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
- } else {
- REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
- }
-#endif
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_sonata_select_chip;
- return 0;
-}
-
-#endif /* CONFIG_NAND_DAVINCI */
diff --git a/configs/davinci_dm355evm_defconfig b/configs/davinci_dm355evm_defconfig
deleted file mode 100644
index 4513ce4..0000000
--- a/configs/davinci_dm355evm_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355EVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM355 EVM # "
diff --git a/configs/davinci_dm355leopard_defconfig b/configs/davinci_dm355leopard_defconfig
deleted file mode 100644
index 7945605..0000000
--- a/configs/davinci_dm355leopard_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM355 LEOPARD # "
diff --git a/configs/davinci_dm365evm_defconfig b/configs/davinci_dm365evm_defconfig
deleted file mode 100644
index 3550e75..0000000
--- a/configs/davinci_dm365evm_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM365EVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM36x EVM # "
diff --git a/configs/davinci_dm6467Tevm_defconfig b/configs/davinci_dm6467Tevm_defconfig
deleted file mode 100644
index 3749b81..0000000
--- a/configs/davinci_dm6467Tevm_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig
deleted file mode 100644
index b2021af..0000000
--- a/configs/davinci_dm6467evm_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM6467 EVM > "
diff --git a/configs/davinci_dvevm_defconfig b/configs/davinci_dvevm_defconfig
deleted file mode 100644
index 7c6f03e..0000000
--- a/configs/davinci_dvevm_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DVEVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_schmoogie_defconfig b/configs/davinci_schmoogie_defconfig
deleted file mode 100644
index 2fb4d9f..0000000
--- a/configs/davinci_schmoogie_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_sffsdr_defconfig b/configs/davinci_sffsdr_defconfig
deleted file mode 100644
index 633b4a8..0000000
--- a/configs/davinci_sffsdr_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SFFSDR=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/davinci_sonata_defconfig b/configs/davinci_sonata_defconfig
deleted file mode 100644
index 697ce06..0000000
--- a/configs/davinci_sonata_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SONATA=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
deleted file mode 100644
index 1d7494f..0000000
--- a/configs/ea20_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_EA20=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="ea20 > "
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
deleted file mode 100644
index 72296a0..0000000
--- a/include/configs/davinci_dm355evm.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM355 EVM board */
-#define DAVINCI_DM355EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM355
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Ethernet: external DM9000 */
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x04014000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-/* USB: OTG connector */
-/* NYET -- #define CONFIG_USB_DAVINCI */
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#else
-#undef CONFIG_USB_MUSB_HCD
-#undef CONFIG_CMD_USB
-#undef CONFIG_USB_STORAGE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTCOMMAND \
- "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-
-/* NAND configuration ... socketed with two chipselects. It normally comes
- * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
- * pretty much demands the 4-bit ECC support.) You can of course swap in
- * other parts, including small page ones.
- *
- * This presents a single read-only partition for all bootloader stuff.
- * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
- * some extra space to help cope with bad blocks in that data. Linux
- * shouldn't care about its detailed layout, and will probably want to use
- * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
- * override this default partitioning using MTDPARTS and cmdlinepart.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/* Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
deleted file mode 100644
index e3ff943..0000000
--- a/include/configs/davinci_dm355leopard.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DAVINCI_DM355LEOPARD
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM355 /* DM355 based board */
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Ethernet: external DM9000 */
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x04000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 16)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
-
-/* NAND */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
deleted file mode 100644
index bbc801b..0000000
--- a/include/configs/davinci_dm365evm.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM365 EVM board */
-#define DAVINCI_DM365EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM365
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* EEPROM definitions for EEPROM on DM365 EVM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
-#define PINMUX4_USBDRVBUS_BITSET 0x2000
-
-/* USB Configuration */
-#define CONFIG_USB_DAVINCI
-#define CONFIG_USB_MUSB_HCD
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB /* include support for usb */
-#define CONFIG_CMD_STORAGE /* include support for usb */
-#define CONFIG_CMD_FAT /* include support for FAT/storage*/
-#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
-#endif
-
-#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */
-#define CONFIG_CMD_USB /* include support for usb cmd */
-#define CONFIG_USB_STORAGE /* MSC class support */
-#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
-#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
-#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
-
-#ifdef CONFIG_USB_KEYBOARD /* HID class support */
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-#endif /* CONFIG_USB_MUSB_HCD */
-
-#ifdef CONFIG_USB_MUSB_UDC
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "DM365VM"
-#endif /* CONFIG_USB_MUSB_UDC */
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND \
- "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-
-/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
- * It normally comes with a 2GByte SLC part with 2KB pages
- * (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
- * pretty much demands the 4-bit ECC support.) You can of course swap in
- * other parts, including small page ones.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/* Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
deleted file mode 100644
index 6346422..0000000
--- a/include/configs/davinci_dm6467evm.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM6467 EVM board */
-#define DAVINCI_DM6467EVM
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NAND_SMALLPAGE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* SoC Configuration */
-
-/* Clock rates detection */
-#ifndef __ASSEMBLY__
-extern unsigned int davinci_arm_clk_get(void);
-#endif
-
-/* Arm Clock frequency */
-#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
-/* Timer Input clock freq */
-#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SOC_DM646X
-
-/* EEPROM definitions for EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-#define CONFIG_REVISION_TAG
-
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK 24000000
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
-
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* Flash & Environment */
-#define CONFIG_SYS_NO_FLASH
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_MASK_CLE 0x80000
-#define CONFIG_SYS_NAND_MASK_ALE 0x40000
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_ENV_OFFSET 0
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
-#endif
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
-#define CONFIG_BOOTARGS \
- "mem=120M console=ttyS0,115200n8 " \
- "root=/dev/hda1 rw noinitrd ip=dhcp"
-
-/* U-Boot commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
deleted file mode 100644
index 15d8150..0000000
--- a/include/configs/davinci_dvevm.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define DV_EVM
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NAND
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
-
-#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#ifdef CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT \
- "nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
-#else
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_DAVINCI
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-/*==========================*/
-/* USB MSC support (if any) */
-/*==========================*/
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB
-#ifdef CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
deleted file mode 100644
index bc5e1ca..0000000
--- a/include/configs/davinci_schmoogie.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SCHMOOGIE
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define MACH_TYPE_SCHMOOGIE 1255
-#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
-
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-/*=====================*/
-/* Board related stuff */
-/*=====================*/
-#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
-#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
-#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
deleted file mode 100644
index e719388..0000000
--- a/include/configs/davinci_sffsdr.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board */
-#define SFFSDR
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/* Flash & Environment */
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-/* I2C switch definitions for PCA9543 chip */
-#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
-#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
-#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
-/* U-Boot general configuration */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
- * load address. */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
- * may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/* Linux Information */
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS \
- "mem=56M " \
- "console=ttyS0,115200n8 " \
- "root=/dev/nfs rw noinitrd ip=dhcp " \
- "nfsroot=${serverip}:/nfsroot/sffsdr " \
- "eth0=${ethaddr}"
-#define CONFIG_BOOTCOMMAND \
- "nand read 87A00000 100000 300000;" \
- "bootelf 87A00000"
-/* U-Boot commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
deleted file mode 100644
index b85c988..0000000
--- a/include/configs/davinci_sonata.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SONATA_BOARD
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NOR
-#define MACH_TYPE_SONATA 1254
-#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
-#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
deleted file mode 100644
index 9a70aae..0000000
--- a/include/configs/ea20.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_USE_SPIFLASH
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_VIDEO
-#define CONFIG_PREBOOT
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
-#define CONFIG_DA8XX_GPIO
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-
-/*
- * I2C Configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 0
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_OFFSET 0x80000
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
-#define CONFIG_SYS_NO_FLASH
-#endif
-
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_VIDEO_DA8XX
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#endif
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY 3
-
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_GPIO
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-/* NAND Setup */
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_NO_SUBPAGE
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#endif
-
-/* SPI Flash */
-#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#endif
-
-#if !defined(CONFIG_SYS_USE_NAND) && \
- !defined(CONFIG_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
-#endif
-
-/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME ea20
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "as=3\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "rfsbargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rfsbpath}\0" \
- "testrfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${testrfspath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw initrd=" \
- "0x${ramdisk_addr_r},4M\0" \
- "mtdids=nand0=davinci_nand.0\0" \
- "serverip=192.168.5.249\0" \
- "ipaddr=192.168.5.248\0" \
- "rootpath=/opt/eldk/arm\0" \
- "splashpos=230,180\0" \
- "testrfspath=/opt/eldk/test_arm\0" \
- "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
- "ubi.mtd=${as} root=ubi0:rootfs\0" \
- "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \
- "ubi.mtd=${as} root=ubi0:rootfs\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${consoledev},${baudrate}n8\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
- "consoledev=ttyS0\0" \
- "loadaddr=c0000014\0" \
- "memory=32M\0" \
- "kernel_addr_r=c0700000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/image.ext2\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr_r}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr_r}\0" \
- "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
- "run rfsbargs addip addtty addmtd addmisc addmem; " \
- "bootm ${kernel_addr_r}\0" \
- "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run testrfsargs addip addtty addmtd addmisc addmem; " \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "ubifsload ${kernel_addr_r} /boot/uImage;" \
- "ubifsumount; run nandargs addip addtty " \
- "addmtd addmisc addmem;clrlogo;" \
- "bootm ${kernel_addr_r}\0" \
- "nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "ubifsload ${kernel_addr_r} /boot/uImage;" \
- "ubifsumount; run nandrwargs addip addtty " \
- "addmtd addmisc addmem;clrlogo;" \
- "bootm ${kernel_addr_r}\0" \
- "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
- " addip addtty addmtd addmisc addmem;" \
- "clrlogo;bootm ${kernel_addr_r}\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "load_magic=if sf probe 0;then sf " \
- "read c0000000 0x10000 0x60000;fi\0" \
- "load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "if ubifsload c0000014 /boot/u-boot.bin;" \
- "then mw c0000008 ${filesize};else echo Error reading" \
- " u-boot from nand!;fi\0" \
- "load_net=if sf probe 0;then sf read c0000000 0x10000 " \
- "0x60000;tftp c0000014 ${u-boot};" \
- "mw c0000008 ${filesize};fi\0" \
- "upd=if sf probe 0;then sf erase 10000 60000;" \
- "sf write c0000000 10000 60000;fi\0" \
- "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \
- "sf erase 0 10000;" \
- "sf write 0xc0700000 0 ${filesize};fi\0" \
- "ubootupd_net=if run load_net;then echo Updating u-boot;" \
- "if run upd; then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
- "bootcmd=run net_testrfs\0"
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 06/45] arm: Remove d2net_v2 defconfig file
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (4 preceding siblings ...)
2015-08-31 1:18 ` [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,06/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 07/45] arm: Remove dig297 board Simon Glass
` (39 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This file appears to be an orphan with no board files. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/d2net_v2_defconfig | 8 --------
1 file changed, 8 deletions(-)
delete mode 100644 configs/d2net_v2_defconfig
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
deleted file mode 100644
index d5f783f..0000000
--- a/configs/d2net_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NET2BIG_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 07/45] arm: Remove dig297 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (5 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 06/45] arm: Remove d2net_v2 defconfig file Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,07/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards Simon Glass
` (38 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/armv7/omap3/Kconfig | 4 -
board/comelit/dig297/Kconfig | 12 --
board/comelit/dig297/MAINTAINERS | 6 -
board/comelit/dig297/Makefile | 8 -
board/comelit/dig297/dig297.c | 182 -------------------
board/comelit/dig297/dig297.h | 367 ---------------------------------------
configs/dig297_defconfig | 10 --
include/configs/dig297.h | 268 ----------------------------
8 files changed, 857 deletions(-)
delete mode 100644 board/comelit/dig297/Kconfig
delete mode 100644 board/comelit/dig297/MAINTAINERS
delete mode 100644 board/comelit/dig297/Makefile
delete mode 100644 board/comelit/dig297/dig297.c
delete mode 100644 board/comelit/dig297/dig297.h
delete mode 100644 configs/dig297_defconfig
delete mode 100644 include/configs/dig297.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index f4fb6cb..336da53 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -79,9 +79,6 @@ config TARGET_ECO5PK
bool "ECO5PK"
select SUPPORT_SPL
-config TARGET_DIG297
- bool "DIG297"
-
config TARGET_TRICORDER
bool "Tricorder"
select SUPPORT_SPL
@@ -140,7 +137,6 @@ source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
-source "board/comelit/dig297/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig
deleted file mode 100644
index 6dccaff..0000000
--- a/board/comelit/dig297/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DIG297
-
-config SYS_BOARD
- default "dig297"
-
-config SYS_VENDOR
- default "comelit"
-
-config SYS_CONFIG_NAME
- default "dig297"
-
-endif
diff --git a/board/comelit/dig297/MAINTAINERS b/board/comelit/dig297/MAINTAINERS
deleted file mode 100644
index 318374e..0000000
--- a/board/comelit/dig297/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DIG297 BOARD
-M: Luca Ceresoli <luca.ceresoli@comelit.it>
-S: Maintained
-F: board/comelit/dig297/
-F: include/configs/dig297.h
-F: configs/dig297_defconfig
diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile
deleted file mode 100644
index 1c85b63..0000000
--- a/board/comelit/dig297/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dig297.o
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
deleted file mode 100644
index 9d4c41b..0000000
--- a/board/comelit/dig297/dig297.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.c:
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/omap3-regs.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "dig297.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NET
-static void setup_net_chip(void);
-
-#define NET_LAN9221_RESET_GPIO 12
-
-/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
-#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT)
-#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \
- CSRDOFFTIME(7) | \
- ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \
- ADVRDOFFTIME(2) | \
- ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \
- WEONTIME(1) | \
- OEOFFTIME(7)| \
- OEONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \
- RDACCESSTIME(6) | \
- WRCYCLETIME(0x1D) | \
- RDCYCLETIME(0x1D))
-#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \
- WRACCESSTIME(0x1D) | \
- WRDATAONADMUXBUS(3))
-
-static const u32 gpmc_lan_config[] = {
- NET_LAN9220_GPMC_CONFIG1,
- NET_LAN9220_GPMC_CONFIG2,
- NET_LAN9220_GPMC_CONFIG3,
- NET_LAN9220_GPMC_CONFIG4,
- NET_LAN9220_GPMC_CONFIG5,
- NET_LAN9220_GPMC_CONFIG6,
- /* CONFIG7: computed by enable_gpmc_cs_config() */
-};
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-
- twl4030_power_init();
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-
- /*
- * GPIO list
- * - 159 OUT (GPIO5+31): reset for remote camera interface connector.
- * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
- * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
- */
-
- /* Configure GPIOs to output */
- writel(~(GPIO19 | GPIO20), &gpio1_base->oe);
- writel(~(GPIO31), &gpio5_base->oe);
-
- /* Set GPIO values */
- writel((GPIO19 | GPIO20), &gpio1_base->setdataout);
- writel(0, &gpio5_base->setdataout);
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DIG297();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-
- /* Make GPIO 12 as output pin and send a magic pulse through it */
- if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) {
- gpio_direction_output(NET_LAN9221_RESET_GPIO, 0);
- gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
- udelay(1);
- gpio_set_value(NET_LAN9221_RESET_GPIO, 0);
- udelay(31000); /* Should be >= 30ms according to datasheet */
- gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
- }
-}
-#endif /* CONFIG_CMD_NET */
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- return rc;
-}
diff --git a/board/comelit/dig297/dig297.h b/board/comelit/dig297/dig297.h
deleted file mode 100644
index 8edfc09..0000000
--- a/board/comelit/dig297/dig297.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.h:
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DIG297_H_
-#define _DIG297_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 DIG297 board",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DIG297() \
-/*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
-/*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\
- /* GPMC_nCS1/2: not available on CUS package*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
- MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
- /* GPMC_WAIT2: not available on CUS package*/\
- MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
- /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- /* GPMC_WAIT1: not available on CUS package*/\
-/*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-/*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
-/*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-/*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
-/*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
-/*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
-/*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
-/*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
-/* USB EHCI (port 2) */\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
-/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
- /*
- * McSPI1_CLK.
- * IEN needed fot the McSPI to "receive" the clock and be able to
- * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
- * omap_applications_processors/f/42/p/29444/102394.aspx#102394
- */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\
- MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\
-/* MCSPI2: to HIMAX TFT controller.*/\
- MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\
- /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
- MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
-/* GPIO */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\
- MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\
- MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\
- MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\
- MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\
-/*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */
-
-#endif
diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig
deleted file mode 100644
index 4c2c982..0000000
--- a/configs/dig297_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_DIG297=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="DIG297# "
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
deleted file mode 100644
index 98205ad..0000000
--- a/include/configs/dig297.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the Comelit DIG297 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_OMAP3_CPS
-#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
-#else
-#define MACH_TYPE_OMAP3_CPS 2751
-#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SYS_TEXT_BASE 0x80008000
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration: UART3 (ttyO2)
- */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION
-
-/* library portions to compile in */
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-
-/* commands to include */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_UBI /* UBI Support */
-#define CONFIG_CMD_UBIFS /* UBIFS Support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
- "128k(uboot-env),3m(kernel),252m(ubi)"
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER
-#define CONFIG_TWL4030_LED
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
-
-#if defined(CONFIG_CMD_NET)
-/*
- * SMSC9220 Ethernet
- */
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/* Environment information */
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,3\0"\
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "nandroot=ubi0:rootfs ro\0" \
- "nandrootfstype=ubifs\0" \
- "nfspath=/srv/nfs\0" \
- "tftpfilename=uImage\0" \
- "gatewayip=0.0.0.0\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "ubi.mtd=3 " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "netargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "root=/dev/nfs rw " \
- "nfsroot=${serverip}:${nfspath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 100000 300000; " \
- "bootm ${loadaddr}\0" \
- "netboot=echo Booting from network ...; " \
- "run netargs; " \
- "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
- "bootm ${loadaddr}\0" \
- "resetenv=nand erase e0000 20000\0"\
-
-#define CONFIG_BOOTCOMMAND \
- "run nandboot"
-
-#define CONFIG_AUTO_COMPLETE
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
- /* works on */
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
- /* load address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
-
-/* Monitor@start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_NAND
-#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (6 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 07/45] arm: Remove dig297 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 09/45] arm: Remove edb9315a board Simon Glass
` (37 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These board have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 5 -
board/BuS/eb_cpux9k2/Kconfig | 12 --
board/BuS/eb_cpux9k2/MAINTAINERS | 7 -
board/BuS/eb_cpux9k2/Makefile | 8 -
board/BuS/eb_cpux9k2/cpux9k2.c | 373 ------------------------------------
configs/eb_cpux9k2_defconfig | 5 -
configs/eb_cpux9k2_ram_defconfig | 5 -
include/configs/eb_cpux9k2.h | 400 ---------------------------------------
8 files changed, 815 deletions(-)
delete mode 100644 board/BuS/eb_cpux9k2/Kconfig
delete mode 100644 board/BuS/eb_cpux9k2/MAINTAINERS
delete mode 100644 board/BuS/eb_cpux9k2/Makefile
delete mode 100644 board/BuS/eb_cpux9k2/cpux9k2.c
delete mode 100644 configs/eb_cpux9k2_defconfig
delete mode 100644 configs/eb_cpux9k2_ram_defconfig
delete mode 100644 include/configs/eb_cpux9k2.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 01a8d45..de06416 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -8,10 +8,6 @@ config TARGET_AT91RM9200EK
bool "Atmel AT91RM9200 evaluation kit"
select CPU_ARM920T
-config TARGET_EB_CPUX9K2
- bool "Support eb_cpux9k2"
- select CPU_ARM920T
-
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select CPU_ARM926EJS
@@ -143,7 +139,6 @@ source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
-source "board/BuS/eb_cpux9k2/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig
deleted file mode 100644
index e2a787a..0000000
--- a/board/BuS/eb_cpux9k2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_EB_CPUX9K2
-
-config SYS_BOARD
- default "eb_cpux9k2"
-
-config SYS_VENDOR
- default "BuS"
-
-config SYS_CONFIG_NAME
- default "eb_cpux9k2"
-
-endif
diff --git a/board/BuS/eb_cpux9k2/MAINTAINERS b/board/BuS/eb_cpux9k2/MAINTAINERS
deleted file mode 100644
index 81c4349..0000000
--- a/board/BuS/eb_cpux9k2/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-EB_CPUX9K2 BOARD
-M: Jens Scharsig <esw@bus-elektronik.de>
-S: Maintained
-F: board/BuS/eb_cpux9k2/
-F: include/configs/eb_cpux9k2.h
-F: configs/eb_cpux9k2_defconfig
-F: configs/eb_cpux9k2_ram_defconfig
diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile
deleted file mode 100644
index b2ec389..0000000
--- a/board/BuS/eb_cpux9k2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cpux9k2.o
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
deleted file mode 100644
index 3880a06..0000000
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
- * Jens Scharsig <esw@bus-elektronik.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <exports.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_common.h>
-
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-
-#ifdef CONFIG_VIDEO
-#include <bus_vcxk.h>
-
-extern unsigned long display_width;
-extern unsigned long display_height;
-#endif
-
-#ifdef CONFIG_CMD_NAND
-void cpux9k2_nand_hw_init(void);
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- /* Correct IRDA resistor problem / Set PA23_TXD in Output */
- writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
-
- gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_STATUS_LED
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
-#ifdef CONFIG_CMD_NAND
- cpux9k2_nand_hw_init();
-#endif
- return 0;
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-
-int misc_init_r(void)
-{
- uchar mac[8];
- uchar tm;
- uchar midx;
- uchar macn6, macn7;
-
- if (getenv("ethaddr") == NULL) {
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- (uchar *) &mac, sizeof(mac)) != 0) {
- puts("Error reading MAC from EEPROM\n");
- } else {
- tm = 0;
- macn6 = 0;
- macn7 = 0xFF;
- for (midx = 0; midx < 6; midx++) {
- if ((mac[midx] != 0) && (mac[midx] != 0xFF))
- tm++;
- macn6 += mac[midx];
- macn7 ^= mac[midx];
- }
- if ((macn6 != mac[6]) || (macn7 != mac[7]))
- tm = 0;
- if (tm)
- eth_setenv_enetaddr("ethaddr", mac);
- else
- puts("Error: invalid MAC@EEPROM\n");
- }
- }
- gd->jt->do_reset = do_reset;
-
-#ifdef CONFIG_STATUS_LED
- status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
- udelay(10000);
- eth_init();
-}
-#endif
-
-/*
- * DRAM initialisations
- */
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-/*
- * Ethernet initialisations
- */
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
- return rc;
-}
-#endif
-
-/*
- * Disk On Chip (NAND) Millenium initialization.
- * The NAND lives in the CS2* space
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define MASK_ALE (1 << 22) /* our ALE is AD22 */
-#define MASK_CLE (1 << 21) /* our CLE is AD21 */
-
-void cpux9k2_nand_hw_init(void)
-{
- unsigned long csr;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
-
- /* Setup Smart Media, fitst enable the address range of CS3 */
- writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
-
- /* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
- csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
- AT91_SMC_CSR_NWS(3) |
- AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
- AT91_SMC_CSR_WSEN;
- writel(csr, &mc->smc.csr[3]);
-
- writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
- writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
- &pio->pioc.pdr);
-
- /* Configure PC2 as input (signal Nand READY ) */
- writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
- writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
- writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
-
- /* PIOC clock enabling */
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-}
-
-static void board_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- if ((ctrl & NAND_NCE))
- writel(1, &pio->pioc.codr);
- else
- writel(1, &pio->pioc.sodr);
-
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int board_nand_dev_ready(struct mtd_info *mtd)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- cpux9k2_nand_hw_init();
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->cmd_ctrl = board_nand_hwcontrol;
- nand->dev_ready = board_nand_dev_ready;
- nand->chip_delay = 20;
- return 0;
-}
-
-#endif
-
-#if defined(CONFIG_VIDEO)
-/*
- * drv_video_init
- * FUNCTION: initialize VCxK device
- */
-
-int drv_video_init(void)
-{
-#ifdef CONFIG_SPLASH_SCREEN
- unsigned long splash;
-#endif
- char *s;
- unsigned long csr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
-
- printf("Init Video as ");
- s = getenv("displaywidth");
- if (s != NULL)
- display_width = simple_strtoul(s, NULL, 10);
- else
- display_width = 256;
- s = getenv("displayheight");
- if (s != NULL)
- display_height = simple_strtoul(s, NULL, 10);
- else
- display_height = 256;
- printf("%ld x %ld pixel matrix\n", display_width, display_height);
-
- /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */
- csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
- AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
- AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
- AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
- writel(csr, &mc->smc.csr[2]);
- writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
-
- vcxk_init(display_width, display_height);
-#ifdef CONFIG_SPLASH_SCREEN
- s = getenv("splashimage");
- if (s != NULL) {
- splash = simple_strtoul(s, NULL, 16);
- printf("use splashimage: %lx\n", splash);
- video_display_bitmap(splash, 0, 0);
- }
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-
-void i2c_init_board(void)
-{
- u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
- pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_STATUS_LED
-
-void __led_toggle(led_id_t mask)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- if (readl(&pio->piod.odsr) & mask)
- writel(mask, &pio->piod.codr);
- else
- writel(mask, &pio->piod.codr);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
- /* Disable peripherals on LEDs */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
- /* Enable pins as outputs */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
- /* Turn all LEDs OFF */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
-
- __led_set(mask, state);
-}
-
-void __led_set(led_id_t mask, int state)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- if (state == STATUS_LED_ON)
- writel(mask, &pio->piod.codr);
- else
- writel(mask, &pio->piod.sodr);
-}
-
-#endif
-
-/*---------------------------------------------------------------------------*/
-
-int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 0;
- ulong side;
- ulong bright;
-
- switch (argc) {
- case 3:
- side = simple_strtoul(argv[1], NULL, 10);
- bright = simple_strtoul(argv[2], NULL, 10);
- if ((side >= 0) && (side <= 3) &&
- (bright >= 0) && (bright <= 1000)) {
- vcxk_setbrightness(side, bright);
- rcode = 0;
- } else {
- printf("parameters out of range\n");
- printf("Usage:\n%s\n", cmdtp->usage);
- rcode = 1;
- }
- break;
- default:
- printf("Usage:\n%s\n", cmdtp->usage);
- rcode = 1;
- break;
- }
- return rcode;
-}
-
-/*---------------------------------------------------------------------------*/
-
-U_BOOT_CMD(
- bright, 3, 0, do_brightness,
- "bright - sets the display brightness\n",
- " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
-);
-
-/* EOF cpu9k2.c */
diff --git a/configs/eb_cpux9k2_defconfig b/configs/eb_cpux9k2_defconfig
deleted file mode 100644
index 6a6f3cd..0000000
--- a/configs/eb_cpux9k2_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_EB_CPUX9K2=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/eb_cpux9k2_ram_defconfig b/configs/eb_cpux9k2_ram_defconfig
deleted file mode 100644
index 47c2178..0000000
--- a/configs/eb_cpux9k2_ram_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_EB_CPUX9K2=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
deleted file mode 100644
index d27f7e0..0000000
--- a/include/configs/eb_cpux9k2.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
- * Jens Scharsig <esw@bus-elektronik.de>
- *
- * Configuation settings for the EB+CPUx9K2 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_EB_CPUx9K2_H_
-#define _CONFIG_EB_CPUx9K2_H_
-
-/*--------------------------------------------------------------------------*/
-
-#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
-#define USE_920T_MMU
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
-
-#include <asm/hardware.h> /* needed for port definitions */
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define MACH_TYPE_EB_CPUX9K2 1977
-#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SYS_DCACHE_OFF
-
-/*--------------------------------------------------------------------------*/
-#ifndef CONFIG_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x21800000
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
-
-#define CONFIG_BOOT_RETRY_TIME 30
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-
-/*
- * ARM asynchronous clock
- */
-
-#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
-#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
-
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
-/* flash */
-#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
-#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
-#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
-#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/*
- * sdram
- */
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
- CONFIG_SYS_MALLOC_LEN)
-
-#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
-#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
-#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
-#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-/*
- * Command line configuration
- */
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_SYS_LONGHELP
-
-/*
- * MTD defines
- */
-
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
-#define MTDPARTS_DEFAULT "mtdparts=" \
- "physmap-flash.0:" \
- "512k(U-Boot)," \
- "128k(Env)," \
- "128k(Splash)," \
- "4M(Kernel)," \
- "384k(MiniFS)," \
- "-(FS)" \
- ";" \
- "atmel_nand:" \
- "1M(emergency)," \
- "-(data)"
-/*
- * Hardware drivers
- */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_AT91C_PQFP_UHPBUG
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_EFI_PARTITION
-
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-
-/*
- * UART/CONSOLE
- */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID 0/* ignored in arm */
-
-/*
- * network
- */
-
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_RESET_PHY_R 1
-
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_DRIVER_AT91EMAC_QUIET 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#define CONFIG_MII 1
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * I2C-Bus
- */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-
-/* Software I2C driver configuration */
-
-#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
-#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
-
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
-#define I2C_SDA(bit) \
- if (bit) \
- writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
- else \
- writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
-#define I2C_SCL(bit) \
- if (bit) \
- writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
- else \
- writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
-
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
-
-/* I2C-RTC */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/* EEPROM */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
-/* FLASH organization */
-
-/* NOR-FLASH */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
-
-/* NAND */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-
-/* Status LED's */
-
-#define CONFIG_STATUS_LED 1
-#define CONFIG_BOARD_SPECIFIC_LED 1
-
-#define STATUS_LED_BOOT 1
-#define STATUS_LED_ACTIVE 0
-
-#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
-#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
-#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
-
-#define CONFIG_VIDEO 1
-
-/* Options */
-
-#ifdef CONFIG_VIDEO
-
-#define CONFIG_VIDEO_VCXK 1
-
-#define CONFIG_SPLASH_SCREEN 1
-
-#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
-#define CONFIG_SYS_VCXK_BASE 0x30000000
-
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
-
-#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
-#define CONFIG_SYS_VCXK_ENABLE_PORT piob
-#define CONFIG_SYS_VCXK_ENABLE_DDR oer
-
-#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
-#define CONFIG_SYS_VCXK_REQUEST_PORT piob
-#define CONFIG_SYS_VCXK_REQUEST_DDR oer
-
-#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
-#define CONFIG_SYS_VCXK_INVERT_PORT piob
-#define CONFIG_SYS_VCXK_INVERT_DDR oer
-
-#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
-#define CONFIG_SYS_VCXK_RESET_PORT piob
-#define CONFIG_SYS_VCXK_RESET_DDR oer
-
-#endif /* CONFIG_VIDEO */
-
-/* Environment */
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
-#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOMMAND "run nfsboot"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "run bootargsdefaults;" \
- "set bootargs $(bootargs) boot=nfs " \
- ";echo $(bootargs)" \
- ";bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "displaywidth=256\0" \
- "displayheight=512\0" \
- "displaybsteps=1023\0" \
- "ubootaddr=10000000\0" \
- "splashimage=100A0000\0" \
- "kerneladdr=100C0000\0" \
- "kernelsize=00400000\0" \
- "rootfsaddr=10520000\0" \
- "copy_addr=21200000\0" \
- "rootfssize=00AE0000\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "bootargsdefaults=set bootargs " \
- "console=ttyS0,115200 " \
- "video=vcxk_fb:xres:${displaywidth}," \
- "yres:${displayheight}," \
- "bres:${displaybsteps} " \
- "mem=62M " \
- "panic=10 " \
- "uboot=\\\"${ver}\\\" " \
- "\0" \
- "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "erase $(kerneladdr) +$(kernelsize);" \
- "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
- "protect on $(kerneladdr) +$(kernelsize)" \
- "\0" \
- "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
- "dhcp $(copy_addr) rfs;" \
- "erase $(rootfsaddr) +$(rootfssize);" \
- "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
- "\0" \
- "update_uboot=protect off 10000000 1007FFFF;" \
- "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
- "erase 10000000 1007FFFF;" \
- "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
- "protect on 10000000 1007FFFF;reset\0" \
- "update_splash=protect off $(splashimage) +20000;" \
- "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
- "erase $(splashimage) +20000;" \
- "cp.b $(fileaddr) $(splashimage) $(filesize);" \
- "protect on $(splashimage) +20000;reset\0" \
- "emergency=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(kerneladdr)\0" \
- "netemergency=run bootargsdefaults;" \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(copy_addr)\0" \
- "norboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=local " \
- ";bootm $(kerneladdr)\0" \
- "nandboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=nand " \
- ";bootm $(kerneladdr)\0" \
- " "
-
-/*--------------------------------------------------------------------------*/
-
-#endif
-
-/* EOF */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 09/45] arm: Remove edb9315a board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (7 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 7:38 ` sergey kostanbaev
2015-08-31 1:19 ` [U-Boot] [PATCH 10/45] arm: Remove enbw_cmc board Simon Glass
` (36 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/cirrus/edb93xx/Kconfig | 15 --
board/cirrus/edb93xx/MAINTAINERS | 6 -
board/cirrus/edb93xx/Makefile | 11 --
board/cirrus/edb93xx/edb93xx.c | 382 ---------------------------------------
board/cirrus/edb93xx/u-boot.lds | 116 ------------
configs/edb9315a_defconfig | 6 -
include/configs/edb93xx.h | 284 -----------------------------
8 files changed, 825 deletions(-)
delete mode 100644 board/cirrus/edb93xx/Kconfig
delete mode 100644 board/cirrus/edb93xx/MAINTAINERS
delete mode 100644 board/cirrus/edb93xx/Makefile
delete mode 100644 board/cirrus/edb93xx/edb93xx.c
delete mode 100644 board/cirrus/edb93xx/u-boot.lds
delete mode 100644 configs/edb9315a_defconfig
delete mode 100644 include/configs/edb93xx.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5429dc8..fa52901 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -69,10 +69,6 @@ choice
config ARCH_AT91
bool "Atmel AT91"
-config TARGET_EDB93XX
- bool "Support edb93xx"
- select CPU_ARM920T
-
config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
@@ -889,7 +885,6 @@ source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
-source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
deleted file mode 100644
index c5f4897..0000000
--- a/board/cirrus/edb93xx/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_EDB93XX
-
-config SYS_BOARD
- default "edb93xx"
-
-config SYS_VENDOR
- default "cirrus"
-
-config SYS_SOC
- default "ep93xx"
-
-config SYS_CONFIG_NAME
- default "edb93xx"
-
-endif
diff --git a/board/cirrus/edb93xx/MAINTAINERS b/board/cirrus/edb93xx/MAINTAINERS
deleted file mode 100644
index 3bb2843..0000000
--- a/board/cirrus/edb93xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EDB93XX BOARD
-M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
-S: Maintained
-F: board/cirrus/edb93xx/
-F: include/configs/edb93xx.h
-F: configs/edb9315a_defconfig
diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
deleted file mode 100644
index d03c498..0000000
--- a/board/cirrus/edb93xx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2013
-# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
-#
-# * SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := edb93xx.o
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
deleted file mode 100644
index 8963d3a..0000000
--- a/board/cirrus/edb93xx/edb93xx.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * Board initialization for EP93xx
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias <at> kaehlcke.net>
- *
- * (C) Copyright 2002 2003
- * Network Audio Technologies, Inc. <www.netaudiotech.com>
- * Adam Bezanson <bezanson <at> netaudiotech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/ep93xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * usb_div: 4, nbyp2: 1, pll2_en: 1
- * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
- * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
- */
-#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
- 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
- 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
- 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
- SYSCON_CLKSET2_PLL2_EN | \
- SYSCON_CLKSET2_NBYP2 | \
- 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
-
-#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
- SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
- 1 << SMC_BCR_MW_SHIFT)
-
-/* delay execution before timers are initialized */
-static inline void early_udelay(uint32_t usecs)
-{
- /* loop takes 4 cycles at 5.0ns (fastest case, running@200MHz) */
- register uint32_t loops = (usecs * 1000) / 20;
-
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-#ifndef CONFIG_EP93XX_NO_FLASH_CFG
-static void flash_cfg(void)
-{
- struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
-
- writel(SMC_BCR6_VALUE, &smc->bcr6);
-}
-#else
-#define flash_cfg()
-#endif
-
-int board_init(void)
-{
- /*
- * Setup PLL2, PPL1 has been set during lowlevel init
- */
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- writel(CLKSET2_VAL, &syscon->clkset2);
-
- /*
- * the user's guide recommends to wait at least 1 ms for PLL2 to
- * stabilize
- */
- early_udelay(1000);
-
- /* Go to Async mode */
- __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
- __asm__ volatile ("orr r0, r0, #0xc0000000");
- __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
-
- icache_enable();
-
-#ifdef USE_920T_MMU
- dcache_enable();
-#endif
-
- /* Machine number, as defined in linux/arch/arm/tools/mach-types */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* We have a console */
- gd->have_console = 1;
-
- enable_interrupts();
-
- flash_cfg();
-
- green_led_on();
- red_led_off();
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /*
- * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
- * 14.7456/2 MHz
- */
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
- return 0;
-}
-
-int board_eth_init(bd_t *bd)
-{
- return ep93xx_eth_initialize(0, MAC_BASE);
-}
-
-static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
- unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
-{
- if (dram_bank_cnt == 1) {
- dram_bank_base[0] = PHYS_SDRAM_1;
- } else {
- /* Table lookup for holes in address space. Maximum memory
- * for the single SDCS may be up to 256Mb. We start scanning
- * banks from 1Mb, so it could be up to 128 banks theoretically.
- * We need at maximum 7 bits for the loockup, 8 slots is
- * enough for the worst case.
- */
- unsigned tbl[8];
- unsigned i = dram_bank_cnt / 2;
- unsigned j = 0x00100000; /* 1 Mb */
- unsigned *ptbl = tbl;
- do {
- while (!(dram_addr_mask & j)) {
- j <<= 1;
- }
- *ptbl++ = j;
- j <<= 1;
- i >>= 1;
- } while (i != 0);
-
- for (i = dram_bank_cnt, j = 0;
- (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
- unsigned addr = PHYS_SDRAM_1;
- unsigned k;
- unsigned bit;
-
- for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
- if (bit & j)
- addr |= tbl[k];
- }
-
- dram_bank_base[j] = addr;
- }
- }
-}
-
-/* called in board_init_f (before relocation) */
-static unsigned dram_init_banksize_int(int print)
-{
- /*
- * Collect information of banks that has been filled during lowlevel
- * initialization
- */
- unsigned i;
- unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
- unsigned dram_total = 0;
- unsigned dram_bank_size = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
- unsigned dram_addr_mask = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
- unsigned dram_bank_cnt = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
-
- dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
-
- for (i = 0; i < dram_bank_cnt; i++) {
- gd->bd->bi_dram[i].start = dram_bank_base[i];
- gd->bd->bi_dram[i].size = dram_bank_size;
- dram_total += dram_bank_size;
- }
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
-
- if (print) {
- printf("DRAM mask: %08x\n", dram_addr_mask);
- printf("DRAM total %u banks:\n", dram_bank_cnt);
- printf("bank base-address size\n");
-
- if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
- printf("WARNING! UBoot was configured for %u banks,\n"
- "but %u has been found. "
- "Supressing extra memory banks\n",
- CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
- dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
- }
-
- for (i = 0; i < dram_bank_cnt; i++) {
- printf(" %u %08x %08x\n",
- i, dram_bank_base[i], dram_bank_size);
- }
- printf(" ------------------------------------------\n"
- "Total %9d\n\n",
- dram_total);
- }
-
- return dram_total;
-}
-
-void dram_init_banksize(void)
-{
- dram_init_banksize_int(0);
-}
-
-/* called in board_init_f (before relocation) */
-int dram_init(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned sec_id = readl(SECURITY_EXTENSIONID);
- unsigned chip_id = readl(&syscon->chipid);
-
- printf("CPU: Cirrus Logic ");
- switch (sec_id & 0x000001FE) {
- case 0x00000008:
- printf("EP9301");
- break;
- case 0x00000004:
- printf("EP9307");
- break;
- case 0x00000002:
- printf("EP931x");
- break;
- case 0x00000000:
- printf("EP9315");
- break;
- default:
- printf("<unknown>");
- break;
- }
-
- printf(" - Rev. ");
- switch (chip_id & 0xF0000000) {
- case 0x00000000:
- printf("A");
- break;
- case 0x10000000:
- printf("B");
- break;
- case 0x20000000:
- printf("C");
- break;
- case 0x30000000:
- printf("D0");
- break;
- case 0x40000000:
- printf("D1");
- break;
- case 0x50000000:
- printf("E0");
- break;
- case 0x60000000:
- printf("E1");
- break;
- case 0x70000000:
- printf("E2");
- break;
- default:
- printf("?");
- break;
- }
- printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
-
- gd->ram_size = dram_init_banksize_int(1);
- return 0;
-}
-
-
-#ifdef CONFIG_EP93XX_SPI
-#include <spi.h>
-
-/*
- * EGIO0-EGIPO7 -> port A
- * EGIO8-EGIP15 -> port B
- */
-
-static void ep93xx_set_epgio(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->padr) | (1<<num), ®s->padr);
- else
- writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
-}
-
-static void ep93xx_clear_epgio(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
- else
- writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
-}
-
-static void ep93xx_dir_epgio_out(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->paddr) | (1<<num), ®s->paddr);
- else
- writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (bus == 0 && cs < 16)
- return 1;
-
- return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- ep93xx_clear_epgio(slave->cs);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- ep93xx_set_epgio(slave->cs);
-}
-
-#ifdef CONFIG_MMC_SPI
-#include <mmc.h>
-
-#ifndef CONFIG_MMC_SPI_CS_EPGIO
-# define CONFIG_MMC_SPI_CS_EPGIO 4
-#endif
-
-#ifndef CONFIG_MMC_SPI_SPEED
-# define CONFIG_MMC_SPI_SPEED 25000000
-#endif
-
-#ifndef CONFIG_MMC_SPI_MODE
-# define CONFIG_MMC_SPI_MODE SPI_MODE_0
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-
- ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
-
-#ifdef CONFIG_MMC_SPI_POWER_EGPIO
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
- ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
-#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
- ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
-#endif
- struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
- CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
-
- if (!mmc) {
- printf("Failed to create MMC Device\n");
- return 1;
- }
- mmc_init(mmc);
- return 0;
-}
-
-
-#endif /* CONFIG_MMC_SPI */
-#endif /* CONFIG_EP93XX_SPI */
diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds
deleted file mode 100644
index 4aa7891..0000000
--- a/board/cirrus/edb93xx/u-boot.lds
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text : {
- *(.__image_copy_start)
- *(.vectors)
- arch/arm/cpu/arm920t/start.o (.text*)
- . = 0x1000;
-
- LONG(0x53555243)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu.hash : { *(.gnu.hash) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
- .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
-}
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
deleted file mode 100644
index 452bf0d..0000000
--- a/configs/edb9315a_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_EDB93XX=y
-CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
deleted file mode 100644
index efe2a9d..0000000
--- a/include/configs/edb93xx.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * U-boot - Configuration file for Cirrus Logic EDB93xx boards
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_MK_edb9301
-#define CONFIG_EDB9301
-#elif defined(CONFIG_MK_edb9302)
-#define CONFIG_EDB9302
-#elif defined(CONFIG_MK_edb9302a)
-#define CONFIG_EDB9302A
-#elif defined(CONFIG_MK_edb9307)
-#define CONFIG_EDB9307
-#elif defined(CONFIG_MK_edb9307a)
-#define CONFIG_EDB9307A
-#elif defined(CONFIG_MK_edb9312)
-#define CONFIG_EDB9312
-#elif defined(CONFIG_MK_edb9315)
-#define CONFIG_EDB9315
-#elif defined(CONFIG_MK_edb9315a)
-#define CONFIG_EDB9315A
-#else
-#error "no board defined"
-#endif
-
-/* Initial environment and monitor configuration options. */
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
-#define CONFIG_BOOTFILE "edb93xx.img"
-
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-
-#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
-
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_EDB9301
-#define CONFIG_EP9301
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
-#define CONFIG_SYS_PROMPT "EDB9301> "
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#elif defined(CONFIG_EDB9302)
-#define CONFIG_EP9302
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
-#define CONFIG_SYS_PROMPT "EDB9302> "
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#elif defined(CONFIG_EDB9302A)
-#define CONFIG_EP9302
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
-#define CONFIG_SYS_PROMPT "EDB9302A> "
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#elif defined(CONFIG_EDB9307)
-#define CONFIG_EP9307
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
-#define CONFIG_SYS_PROMPT "EDB9307> "
-#define CONFIG_ENV_SECT_SIZE 0x00040000
-#elif defined(CONFIG_EDB9307A)
-#define CONFIG_EP9307
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
-#define CONFIG_SYS_PROMPT "EDB9307A> "
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#elif defined(CONFIG_EDB9312)
-#define CONFIG_EP9312
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
-#define CONFIG_SYS_PROMPT "EDB9312> "
-#define CONFIG_ENV_SECT_SIZE 0x00040000
-#elif defined(CONFIG_EDB9315)
-#define CONFIG_EP9315
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
-#define CONFIG_SYS_PROMPT "EDB9315> "
-#define CONFIG_ENV_SECT_SIZE 0x00040000
-#elif defined(CONFIG_EDB9315A)
-#define CONFIG_EP9315
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
-#define CONFIG_SYS_PROMPT "EDB9315A> "
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#else
-#error "no board defined"
-#endif
-
-/* High-level configuration options */
-#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
-
-#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
-#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
-
-/* Monitor configuration */
-#undef CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-/* Print buffer size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* Boot argument buffer size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-
-/* Serial port hardware configuration */
-#define CONFIG_PL010_SERIAL
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
- 115200, 230400}
-#define CONFIG_SYS_SERIAL0 0x808C0000
-#define CONFIG_SYS_SERIAL1 0x808D0000
-/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1} */
-
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
-
-/* Status LED */
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED 1
-#define STATUS_LED_GREEN 0
-#define STATUS_LED_RED 1
-/* Green */
-#define STATUS_LED_BIT STATUS_LED_GREEN
-#define STATUS_LED_STATE STATUS_LED_ON
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-/* Red */
-#define STATUS_LED_BIT1 STATUS_LED_RED
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-/* Optional value */
-#define STATUS_LED_BOOT STATUS_LED_BIT
-
-/* Network hardware configuration */
-#define CONFIG_DRIVER_EP93XX_MAC
-#define CONFIG_MII_SUPPRESS_PREAMBLE
-#define CONFIG_MII
-#define CONFIG_PHY_ADDR 1
-#undef CONFIG_NETCONSOLE
-
-/* SDRAM configuration */
-#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
- defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
- defined(CONFIG_EDB9315)
-/*
- * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
- * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
- * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
- *
- * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
- * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
- * 64 MB of SDRAM.
- */
-
-#define CONFIG_EDB93XX_SDCS3
-
-#elif defined(CONFIG_EDB9302A) || \
- defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
-/*
- * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
- * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
- * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
- *
- * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
- * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
- */
-#define CONFIG_EDB93XX_SDCS0
-
-#else
-#error "no SDCS configuration for this board"
-#endif
-
-
-#if defined(CONFIG_EDB93XX_SDCS3)
-#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
-#define PHYS_SDRAM_1 0x00000000
-#elif defined(CONFIG_EDB93XX_SDCS0)
-#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
-#define PHYS_SDRAM_1 0xc0000000
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_NR_DRAM_BANKS 8
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
-
-
-/* Must match kernel config */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-
-/* Run-time memory allocatons */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_STACKSIZE (128 * 1024)
-
-#if defined(CONFIG_USE_IRQ)
-#define CONFIG_STACKSIZE_IRQ (4 * 1024)
-#define CONFIG_STACKSIZE_FIQ (4 * 1024)
-#endif
-
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/* -----------------------------------------------------------------------------
- * FLASH and environment organization
- *
- * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
- * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
- * data bus, for a total of 16 MB of CFI-compatible flash.
- *
- * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
- * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
- * data bus, for a total of 32 MB of CFI-compatible flash.
- *
- *
- * EDB9301/02(a)7a/15a EDB9307/12/15
- * 0x60000000 - 0x0003FFFF u-boot u-boot
- * 0x60040000 - 0x0005FFFF environment #1 environment #1
- * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
- * 0x60080000 - 0x0009FFFF unused environment #2
- * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
- * 0x600C0000 - 0x00FFFFFF unused unused
- * 0x61000000 - 0x01FFFFFF not present unused
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
-
-#define CONFIG_SYS_TEXT_BASE 0x60000000
-#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-
-#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_ADDR 0x60040000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/* Define to enable MMC on SPI support */
-/* #define CONFIG_EP93XX_SPI_MMC */
-
-#ifdef CONFIG_EP93XX_SPI_MMC
-#define CONFIG_EP93XX_SPI
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SPI
-#define CONFIG_CMD_MMC
-#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
-#endif
-
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_EP93XX
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_CMD_BOOTZ
-
-/* Define to disable flash configuration*/
-/* #define CONFIG_EP93XX_NO_FLASH_CFG */
-
-/* Define this for indusrial rated chips */
-/* #define CONFIG_EDB93XX_INDUSTRIAL */
-
-#endif /* !defined (__CONFIG_H) */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 10/45] arm: Remove enbw_cmc board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (8 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 09/45] arm: Remove edb9315a board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,10/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 11/45] arm: Remove ima3-mx53 board Simon Glass
` (35 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-davinci/Kconfig | 4 -
board/enbw/enbw_cmc/Kconfig | 12 -
board/enbw/enbw_cmc/MAINTAINERS | 6 -
board/enbw/enbw_cmc/Makefile | 10 -
board/enbw/enbw_cmc/enbw_cmc.c | 893 ----------------------------------------
configs/enbw_cmc_defconfig | 5 -
doc/README.switch_config | 25 --
include/configs/enbw_cmc.h | 440 --------------------
8 files changed, 1395 deletions(-)
delete mode 100644 board/enbw/enbw_cmc/Kconfig
delete mode 100644 board/enbw/enbw_cmc/MAINTAINERS
delete mode 100644 board/enbw/enbw_cmc/Makefile
delete mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
delete mode 100644 configs/enbw_cmc_defconfig
delete mode 100644 doc/README.switch_config
delete mode 100644 include/configs/enbw_cmc.h
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 790d177..cac0867 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,9 +4,6 @@ choice
prompt "DaVinci board select"
optional
-config TARGET_ENBW_CMC
- bool "EnBW CMC board"
-
config TARGET_IPAM390
bool "IPAM390 board"
select SUPPORT_SPL
@@ -30,7 +27,6 @@ endchoice
config SYS_SOC
default "davinci"
-source "board/enbw/enbw_cmc/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/omicron/calimain/Kconfig"
diff --git a/board/enbw/enbw_cmc/Kconfig b/board/enbw/enbw_cmc/Kconfig
deleted file mode 100644
index 796736d..0000000
--- a/board/enbw/enbw_cmc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ENBW_CMC
-
-config SYS_BOARD
- default "enbw_cmc"
-
-config SYS_VENDOR
- default "enbw"
-
-config SYS_CONFIG_NAME
- default "enbw_cmc"
-
-endif
diff --git a/board/enbw/enbw_cmc/MAINTAINERS b/board/enbw/enbw_cmc/MAINTAINERS
deleted file mode 100644
index f7c9920..0000000
--- a/board/enbw/enbw_cmc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ENBW_CMC BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/enbw/enbw_cmc/
-F: include/configs/enbw_cmc.h
-F: configs/enbw_cmc_defconfig
diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile
deleted file mode 100644
index 054d6e7..0000000
--- a/board/enbw/enbw_cmc/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := enbw_cmc.o
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
deleted file mode 100644
index 53b8362..0000000
--- a/board/enbw/enbw_cmc/enbw_cmc.c
+++ /dev/null
@@ -1,893 +0,0 @@
-/*
- * (C) Copyright 2011
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * Based on:
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <linux/ctype.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sdmmc_defs.h>
-#include <asm/arch/timer_defs.h>
-#include <asm/davinci_rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF },
- { DAVINCI_LPSC_SPI1 },
- { DAVINCI_LPSC_ARM_RAM_ROM },
- { DAVINCI_LPSC_UART0 },
- { DAVINCI_LPSC_EMAC },
- { DAVINCI_LPSC_UART0 },
- { DAVINCI_LPSC_GPIO },
- { DAVINCI_LPSC_DDR_EMIF },
- { DAVINCI_LPSC_UART1 },
- { DAVINCI_LPSC_UART2 },
- { DAVINCI_LPSC_MMC_SD1 },
- { DAVINCI_LPSC_USB20 },
- { DAVINCI_LPSC_USB11 },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-static const struct pinmux_config enbw_pins[] = {
- { pinmux(0), 8, 0 },
- { pinmux(0), 8, 1 },
- { pinmux(0), 8, 2 },
- { pinmux(0), 8, 3 },
- { pinmux(0), 8, 4 },
- { pinmux(0), 8, 5 },
- { pinmux(1), 4, 0 },
- { pinmux(1), 8, 1 },
- { pinmux(1), 8, 2 },
- { pinmux(1), 8, 3 },
- { pinmux(1), 8, 4 },
- { pinmux(1), 8, 5 },
- { pinmux(1), 8, 6 },
- { pinmux(1), 4, 7 },
- { pinmux(2), 8, 0 },
- { pinmux(5), 1, 0 },
- { pinmux(5), 1, 3 },
- { pinmux(5), 1, 7 },
- { pinmux(5), 1, 5 },
- { pinmux(5), 1, 4 },
- { pinmux(5), 1, 3 },
- { pinmux(5), 1, 2 },
- { pinmux(5), 1, 1 },
- { pinmux(5), 1, 0 },
- { pinmux(6), 8, 0 },
- { pinmux(6), 8, 1 },
- { pinmux(6), 8, 2 },
- { pinmux(6), 8, 3 },
- { pinmux(6), 8, 4 },
- { pinmux(6), 8, 5 },
- { pinmux(6), 1, 7 },
- { pinmux(7), 8, 2 },
- { pinmux(7), 1, 3 },
- { pinmux(7), 8, 6 },
- { pinmux(7), 1, 7 },
- { pinmux(13), 8, 2 },
- { pinmux(13), 8, 3 },
- { pinmux(13), 8, 4 },
- { pinmux(13), 8, 5 },
- { pinmux(13), 8, 6 },
- { pinmux(13), 8, 7 },
- { pinmux(14), 8, 0 },
- { pinmux(14), 8, 1 },
- { pinmux(16), 8, 1 },
- { pinmux(16), 8, 2 },
- { pinmux(16), 8, 3 },
- { pinmux(16), 8, 4 },
- { pinmux(16), 8, 5 },
- { pinmux(16), 8, 6 },
- { pinmux(16), 8, 7 },
- { pinmux(17), 1, 0 },
- { pinmux(17), 1, 1 },
- { pinmux(17), 1, 2 },
- { pinmux(17), 8, 3 },
- { pinmux(17), 8, 4 },
- { pinmux(17), 8, 5 },
- { pinmux(17), 8, 6 },
- { pinmux(17), 8, 7 },
- { pinmux(18), 8, 0 },
- { pinmux(18), 8, 1 },
- { pinmux(18), 2, 2 },
- { pinmux(18), 2, 3 },
- { pinmux(18), 2, 4 },
- { pinmux(18), 8, 6 },
- { pinmux(18), 8, 7 },
- { pinmux(19), 8, 0 },
- { pinmux(19), 2, 1 },
- { pinmux(19), 2, 2 },
- { pinmux(19), 2, 3 },
- { pinmux(19), 2, 4 },
- { pinmux(19), 8, 5 },
- { pinmux(19), 8, 6 },
-};
-
-const struct pinmux_resource pinmuxes[] = {
- PINMUX_ITEM(emac_pins_mii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(i2c0_pins),
- PINMUX_ITEM(emifa_pins_cs2),
- PINMUX_ITEM(emifa_pins_cs3),
- PINMUX_ITEM(emifa_pins_cs4),
- PINMUX_ITEM(emifa_pins_nand),
- PINMUX_ITEM(emifa_pins_nor),
- PINMUX_ITEM(spi1_pins_base),
- PINMUX_ITEM(spi1_pins_scs0),
- PINMUX_ITEM(uart1_pins_txrx),
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(uart2_pins_rtscts),
- PINMUX_ITEM(enbw_pins),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-struct gpio_config {
- char name[GPIO_NAME_SIZE];
- unsigned char bank;
- unsigned char gpio;
- unsigned char out;
- unsigned char value;
-};
-
-static const struct gpio_config enbw_gpio_config_hut[] = {
- { "RS485 enable", 8, 11, 1, 0 },
- { "RS485 iso", 8, 10, 1, 1 },
- { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
- { "W2HUT RS485 iso", 8, 8, 1, 1 },
-};
-
-static const struct gpio_config enbw_gpio_config_w[] = {
- { "RS485 enable", 8, 11, 1, 0 },
- { "RS485 iso", 8, 10, 1, 0 },
- { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
- { "W2HUT RS485 iso", 8, 8, 1, 0 },
-};
-
-static const struct gpio_config enbw_gpio_config[] = {
- { "LAN reset", 7, 15, 1, 1 },
- { "ena 11V PLC", 7, 14, 1, 0 },
- { "ena 1.5V PLC", 7, 13, 1, 0 },
- { "disable VBUS", 7, 12, 1, 1 },
- { "PLC reset", 6, 13, 1, 0 },
- { "LCM RS", 6, 12, 1, 0 },
- { "LCM R/W", 6, 11, 1, 0 },
- { "PLC pairing", 6, 10, 1, 1 },
- { "PLC MDIO CLK", 6, 9, 1, 0 },
- { "HK218", 6, 8, 1, 0 },
- { "HK218 Rx", 6, 1, 1, 1 },
- { "TPM reset", 6, 0, 1, 0 },
- { "Board-Type", 3, 9, 0, 0 },
- { "HW-ID0", 2, 7, 0, 0 },
- { "HW-ID1", 2, 6, 0, 0 },
- { "HW-ID2", 2, 3, 0, 0 },
- { "PV-IF RxD ena", 0, 15, 1, 1 },
- { "LED1", 1, 15, 1, 1 },
- { "LED2", 0, 1, 1, 1 },
- { "LED3", 0, 2, 1, 1 },
- { "LED4", 0, 3, 1, 1 },
- { "LED5", 0, 4, 1, 1 },
- { "LED6", 0, 5, 1, 0 },
- { "LED7", 0, 6, 1, 0 },
- { "LED8", 0, 14, 1, 0 },
- { "USER1", 0, 12, 0, 0 },
- { "USER2", 0, 13, 0, 0 },
-};
-
-#define PHY_POWER 0x0800
-
-static void enbw_cmc_switch(int port, int on)
-{
- const char *devname;
- unsigned char phyaddr = 3;
- unsigned char reg = 0;
- unsigned short data;
-
- if (port == 1)
- phyaddr = 2;
-
- devname = miiphy_get_current_dev();
- if (!devname) {
- printf("Error: no mii device\n");
- return;
- }
- if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
- printf("Error reading from the PHY addr=%02x reg=%02x\n",
- phyaddr, reg);
- return;
- }
-
- if (on)
- data &= ~PHY_POWER;
- else
- data |= PHY_POWER;
-
- if (miiphy_write(devname, phyaddr, reg, data) != 0) {
- printf("Error writing to the PHY addr=%02x reg=%02x\n",
- phyaddr, reg);
- return;
- }
-}
-
-static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz)
-{
- int i, ret;
-
- for (i = 0; i < sz; i++) {
- int gpio = conf[i].bank * 16 +
- conf[i].gpio;
-
- ret = gpio_request(gpio, conf[i].name);
- if (ret) {
- printf("%s: Could not get %s gpio\n", __func__,
- conf[i].name);
- return ret;
- }
-
- if (conf[i].out)
- gpio_direction_output(gpio,
- conf[i].value);
- else
- gpio_direction_input(gpio);
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- int board_type, hw_id;
-
-#ifndef CONFIG_USE_IRQ
- irq_init();
-#endif
- /* address of boot parameters, not used as booting with DTT */
- gd->bd->bi_boot_params = 0;
-
- enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config));
-
- /* detect HW version */
- board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE);
- hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) +
- (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) +
- (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2);
- printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"),
- hw_id);
- if (board_type)
- enbw_cmc_init_gpio(enbw_gpio_config_w,
- ARRAY_SIZE(enbw_gpio_config_w));
- else
- enbw_cmc_init_gpio(enbw_gpio_config_hut,
- ARRAY_SIZE(enbw_gpio_config_hut));
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- clrbits_le32(&davinci_syscfg_regs->suspsrc,
- (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART2));
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#define KSZ_CMD_READ 0x03
-#define KSZ_CMD_WRITE 0x02
-#define KSZ_ID 0x95
-
-static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
- int cmd_len;
- u8 cmd[2];
-
- cmd[0] = KSZ_CMD_READ;
- cmd[1] = reg;
- cmd_len = 2;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
- flags |= SPI_XFER_END;
- *val = 0;
- cmd_len = 1;
- ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags);
- if (ret) {
- debug("Failed to read (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int enbw_cmc_switch_read_ident(struct spi_slave *spi)
-{
- int ret;
- u8 val;
-
- ret = enbw_cmc_switch_read(spi, 0, &val);
- if (ret) {
- debug("Failed to read\n");
- return -EINVAL;
- }
-
- if (val != KSZ_ID)
- return -EINVAL;
-
- return 0;
-}
-
-static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg,
- unsigned long val)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
- int cmd_len;
- u8 cmd[3];
-
- cmd[0] = KSZ_CMD_WRITE;
- cmd[1] = reg;
- cmd[2] = val;
- cmd_len = 3;
- flags |= SPI_XFER_END;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
-
- udelay(1000);
- ret = enbw_cmc_switch_read(spi, reg, &cmd[0]);
- if (ret) {
- debug("Failed to read\n");
- return -EINVAL;
- }
- if (val != cmd[0])
- debug("warning: reg: %lx va: %x soll: %lx\n",
- reg, cmd[0], val);
-
- return 0;
-}
-
-static int enbw_cmc_eof(unsigned char *ptr)
-{
- if (*ptr == 0xff)
- return 1;
-
- return 0;
-}
-
-static char *enbw_cmc_getnewline(char *ptr)
-{
- while (*ptr != 0x0a) {
- ptr++;
- if (enbw_cmc_eof((unsigned char *)ptr))
- return NULL;
- }
-
- ptr++;
- return ptr;
-}
-
-static char *enbw_cmc_getvalue(char *ptr, int *value)
-{
- int end = 0;
-
- *value = -EINVAL;
-
- if (!isxdigit(*ptr))
- end = 1;
-
- while (end) {
- if ((*ptr == '#') || (*ptr == ';')) {
- ptr = enbw_cmc_getnewline(ptr);
- return ptr;
- }
- if (ptr != NULL) {
- if (isxdigit(*ptr)) {
- end = 0;
- } else if (*ptr == 0x0a) {
- ptr++;
- return ptr;
- } else {
- ptr++;
- if (enbw_cmc_eof((unsigned char *)ptr))
- return NULL;
- }
- } else {
- return NULL;
- }
- }
- *value = (int)simple_strtoul((const char *)ptr, &ptr, 16);
- ptr++;
- return ptr;
-}
-
-static struct spi_slave *enbw_cmc_init_spi(void)
-{
- struct spi_slave *spi;
- int ret;
-
- spi = spi_setup_slave(0, 0, 1000000, 0);
- if (!spi) {
- printf("Failed to set up slave\n");
- return NULL;
- }
-
- ret = spi_claim_bus(spi);
- if (ret) {
- debug("Failed to claim SPI bus: %d\n", ret);
- goto err_claim_bus;
- }
-
- ret = enbw_cmc_switch_read_ident(spi);
- if (ret)
- goto err_read;
-
- return spi;
-err_read:
- spi_release_bus(spi);
-err_claim_bus:
- spi_free_slave(spi);
- return NULL;
-}
-
-static int enbw_cmc_config_switch(unsigned long addr)
-{
- struct spi_slave *spi;
- char *ptr = (char *)addr;
- int value, reg;
- int ret = 0;
-
- debug("configure switch with file on addr: 0x%lx\n", addr);
-
- spi = enbw_cmc_init_spi();
- if (!spi)
- return -EINVAL;
-
- while (ptr != NULL) {
- ptr = enbw_cmc_getvalue(ptr, ®);
- if (ptr != NULL) {
- ptr = enbw_cmc_getvalue(ptr, &value);
- if ((ptr != NULL) && (value >= 0))
- if (enbw_cmc_switch_write(spi, reg, value)) {
- /* error writing to switch */
- ptr = NULL;
- ret = -EINVAL;
- }
- }
- }
-
- spi_release_bus(spi);
- spi_free_slave(spi);
- return ret;
-}
-
-static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned long addr;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- addr = simple_strtoul(argv[1], NULL, 16);
- enbw_cmc_config_switch(addr);
-
- return 0;
-}
-
-U_BOOT_CMD(switch, 3, 1, do_switch,
- "switch addr",
- "[addr]"
-);
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- struct spi_slave *spi;
- const char *s;
- size_t len = 0;
- int config = 1;
-
- davinci_emac_mii_mode_sel(0);
-
- /* send a config file to the switch */
- s = hwconfig_subarg("switch", "config", &len);
- if (len) {
- unsigned long addr = simple_strtoul(s, NULL, 16);
-
- config = enbw_cmc_config_switch(addr);
- }
-
- if (config) {
- /*
- * no valid config file -> do we have some args in
- * hwconfig ?
- */
- if ((hwconfig_subarg("switch", "lan", &len)) ||
- (hwconfig_subarg("switch", "lmn", &len))) {
- /* If so start switch */
- spi = enbw_cmc_init_spi();
- if (spi) {
- if (enbw_cmc_switch_write(spi, 1, 0))
- config = 0;
- udelay(10000);
- if (enbw_cmc_switch_write(spi, 1, 1))
- config = 0;
- spi_release_bus(spi);
- spi_free_slave(spi);
- }
- } else {
- config = 0;
- }
- }
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- if (config) {
- if (hwconfig_subarg_cmp("switch", "lan", "on"))
- /* Switch port lan on */
- enbw_cmc_switch(1, 1);
- else
- enbw_cmc_switch(1, 0);
-
- if (hwconfig_subarg_cmp("switch", "lmn", "on"))
- /* Switch port pwl on */
- enbw_cmc_switch(2, 1);
- else
- enbw_cmc_switch(2, 0);
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_PREBOOT
-static uchar kbd_magic_prefix[] = "key_magic_";
-static uchar kbd_command_prefix[] = "key_cmd_";
-
-struct kbd_data_t {
- char s1;
-};
-
-struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
-{
- /* read SW1 + SW2 */
- kbd_data->s1 = gpio_get_value(12) +
- (gpio_get_value(13) << 1);
- return kbd_data;
-}
-
-static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s1)
- return -1;
-
- return 0;
-}
-
-static char *key_match(const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof(kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- kbd_magic_keys = getenv("magic_keys");
- if (kbd_magic_keys == NULL)
- kbd_magic_keys = "";
-
- /*
- * loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof(kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv(cmd_name);
-
- return cmd;
- }
- }
-
- return NULL;
-}
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r(void)
-{
- char *s, buf[32];
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup(key_match(get_keys(&kbd_data)));
- /* Set or delete definition */
- setenv("preboot", str);
- free(str);
-#endif /* CONFIG_PREBOOT */
-
- /* count all restarts, and save this in an environment var */
- s = getenv("restartcount");
-
- if (s)
- sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1);
- else
- strcpy(buf, "1");
-
- setenv("restartcount", buf);
- saveenv();
-
-#ifdef CONFIG_HW_WATCHDOG
- davinci_hw_watchdog_enable();
-#endif
-
- return 0;
-}
-
-struct cmc_led {
- char name[20];
- unsigned char bank;
- unsigned char gpio;
-};
-
-struct cmc_led led_table[] = {
- {"led1", 1, 15},
- {"led2", 0, 1},
- {"led3", 0, 2},
- {"led4", 0, 3},
- {"led5", 0, 4},
- {"led6", 0, 5},
- {"led7", 0, 6},
- {"led8", 0, 14},
-};
-
-static int cmc_get_led_state(struct cmc_led *led)
-{
- int value;
- int gpio = led->bank * 16 + led->gpio;
-
- value = gpio_get_value(gpio);
-
- return value;
-}
-
-static int cmc_set_led_state(struct cmc_led *led, int state)
-{
- int gpio = led->bank * 16 + led->gpio;
-
- gpio_set_value(gpio, state);
- return 0;
-}
-
-static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmc_led *led;
- int found = 0;
- int i = 0;
- int only_print = 0;
- int len = ARRAY_SIZE(led_table);
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if (argc < 3)
- only_print = 1;
-
- led = led_table;
- while ((!found) && (i < len)) {
- if (strcmp(argv[1], led->name) == 0) {
- found = 1;
- } else {
- led++;
- i++;
- }
- }
- if (!found)
- return cmd_usage(cmdtp);
-
- if (only_print) {
- if (cmc_get_led_state(led))
- printf("on\n");
- else
- printf("off\n");
-
- return 0;
- }
- if (strcmp(argv[2], "on") == 0)
- cmc_set_led_state(led, 1);
- else
- cmc_set_led_state(led, 0);
-
- return 0;
-}
-
-U_BOOT_CMD(led, 3, 1, do_led,
- "switch on/off board led",
- "[name] [on/off]"
-);
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
- davinci_hw_watchdog_reset();
-}
-#endif
-
-#if defined(CONFIG_POST)
-void arch_memory_failure_handle(void)
-{
- struct davinci_gpio *gpio = davinci_gpio_bank01;
- int state = 1;
-
- /*
- * if memor< failure blink with the LED 1,2 and 3
- * as we running from flash, we cannot use the gpio
- * api here, so access the gpio pin direct through
- * the gpio register.
- */
- while (1) {
- if (state) {
- clrbits_le32(&gpio->out_data, 0x80000006);
- state = 0;
- } else {
- setbits_le32(&gpio->out_data, 0x80000006);
- state = 1;
- }
- udelay(500);
- }
-}
-#endif
-
-ulong post_word_load(void)
-{
- struct davinci_rtc *reg =
- (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
-
- return in_be32(®->scratch2);
-}
-
-void post_word_store(ulong value)
-{
- struct davinci_rtc *reg =
- (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
-
- /*
- * write RTC kick register to enable write
- * for RTC Scratch registers. Cratch0 and 1 are
- * used for bootcount values.
- */
- writel(RTC_KICK0R_WE, ®->kick0r);
- writel(RTC_KICK1R_WE, ®->kick1r);
- out_be32(®->scratch2, value);
-}
-
-void board_gpio_init(void)
-{
- struct davinci_gpio *gpio = davinci_gpio_bank01;
-
- /*
- * set LED (gpio Interface not usable here)
- * set LED pins to output and state 0
- */
- clrbits_le32(&gpio->dir, 0x8000407e);
- clrbits_le32(&gpio->out_data, 0x8000407e);
- /* set LED 1 - 5 to state on */
- setbits_le32(&gpio->out_data, 0x8000001e);
-
- /*
- * set some gpio pins to low, this is needed early,
- * so we have no gpio Interface here
- * gpios:
- * 8[8] Mode PV select low
- * 8[9] Debug Rx Enable low
- * 8[10] Mode Select PV low
- * 8[11] Counter Interface RS485 Rx-Enable low
- */
- gpio = davinci_gpio_bank8;
- clrbits_le32(&gpio->dir, 0x00000f00);
- clrbits_le32(&gpio->out_data, 0x0f00);
-}
-
-int board_late_init(void)
-{
- cmc_set_led_state(&led_table[4], 0);
-
- return 0;
-}
-
-void show_boot_progress(int val)
-{
- switch (val) {
- case 1:
- cmc_set_led_state(&led_table[4], 1);
- break;
- case 4:
- cmc_set_led_state(&led_table[4], 0);
- break;
- case 15:
- cmc_set_led_state(&led_table[4], 1);
- break;
- }
-}
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 228000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID);
- /* Add slot-0 to mmc subsystem */
- return davinci_mmc_init(bis, &mmc_sd1);
-}
-#endif
diff --git a/configs/enbw_cmc_defconfig b/configs/enbw_cmc_defconfig
deleted file mode 100644
index 90249f3..0000000
--- a/configs/enbw_cmc_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_ENBW_CMC=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.switch_config b/doc/README.switch_config
deleted file mode 100644
index f890373..0000000
--- a/doc/README.switch_config
+++ /dev/null
@@ -1,25 +0,0 @@
-On the enbw_cmc board is a KSZ8864RMN switch which needs
-configured through spi before working. This is done on
-startup from u-boot through a config file stored at an
-address specified in the "hwconfig" environment variable,
-subcommand "config".
-
-For example on the enbw_cmc board:
-
-hwconfig=switch:lan=on,pwl=off,config=0x60160000
-
-The file has the following structure:
-
-- a comment starts with a '#' or a ';' and ends with a newline
-- The switch needs for its config a reg/value pair, so we
- have two columns in the file:
- reg : contains the register address
- value: contains a 8 bit register value
- This 2 columns are seperated through space or tab.
-
-example (minimal configuration on the enbw_cmc board):
-
-;reg value comment
-;-----------------------------------------
-0x01 0x00
-0x01 0x01 ; Start Switch with this configuration
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
deleted file mode 100644
index 141489d..0000000
--- a/include/configs/enbw_cmc.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * (C) Copyright 2011
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * Based on:
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
-#define CONFIG_USE_NAND
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_DA850_LOWLEVEL
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
-#define CONFIG_DA8XX_GPIO
-#define CONFIG_HOSTNAME enbw_cmc
-
-#define MACH_TYPE_ENBW_CMC 3585
-#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-/*
- * I2C Configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
-#define CONFIG_CMD_I2C
-
-#define CONFIG_CMD_DTT
-#define CONFIG_DTT_LM75
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-/*
- * SPI Configuration
- */
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-#define CONFIG_CMD_SPI
-
-/*
- * Flash & Environment
- */
-#ifdef CONFIG_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "512k(U-Boot)," \
- "64k(env1)," \
- "64k(env2)," \
- "-(rest);" \
- "davinci_nand.1:" \
- "128k(dtb)," \
- "3m(kernel)," \
- "4m(rootfs)," \
- "-(userfs)"
-
-
-#define CONFIG_CMD_MTDPARTS
-
-#endif
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
- CONFIG_ENV_SECT_SIZE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "u-boot_addr_r=c0000000\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize};" \
- "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
- "netdev=eth0\0" \
- "rootpath=/opt/eldk-arm/arm\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "kernel_addr_r=c0700000\0" \
- "fdt_addr_r=c0600000\0" \
- "ramdisk_addr_r=c0b00000\0" \
- "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
- __stringify(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
- "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
- "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
- "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
- "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
- "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
- "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
- "addcon=setenv bootargs ${bootargs} console=ttyS2," \
- "${baudrate}n8\0" \
- "net_nfs=run load_fdt load_kernel; " \
- "run nfsargs addip addcon addmtd addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
- "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "bootcmd=run net_nfs\0" \
- "machid=e01\0" \
- "key_cmd_0=echo key: 0\0" \
- "key_cmd_1=echo key: 1\0" \
- "key_cmd_2=echo key: 2\0" \
- "key_cmd_3=echo key: 3\0" \
- "key_magic_0=0\0" \
- "key_magic_1=1\0" \
- "key_magic_2=2\0" \
- "key_magic_3=3\0" \
- "magic_keys=0123\0" \
- "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "logversion=2\0" \
- "\0"
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_HWCONFIG
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_CACHE
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-#ifdef CONFIG_USE_NAND
-#define CONFIG_CMD_NAND
-
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#endif
-
-#if !defined(CONFIG_USE_NAND) && \
- !defined(CONFIG_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
-#endif
-
-#define CONFIG_SYS_TEXT_BASE 0x60000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMC_RESET_PIN 0x04000000
-#define CONFIG_CMC_RESET_TIMEOUT 3
-
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
-#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
-#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
-
-#define CONFIG_CMD_DATE
-#define CONFIG_RTC_DAVINCI
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_MMC_MBLOCK
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-
-/* GPIO */
-#define CONFIG_ENBW_CMC_BOARD_TYPE 57
-#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
-#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
-#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
-
-/* FDT support */
-#define CONFIG_OF_LIBFDT
-
-/* LowLevel Init */
-/* PLL */
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
-
-#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
-#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
-
-/* DDR RAM */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
- DV_DDR_PHY_EXT_STRBEN | \
- (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
- (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
- (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
- (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
- (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
- (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
- (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
- (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
-
-/*
- * freq = 150MHz -> t = 7ns
- */
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
- (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
- (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
- (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
- (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
- (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
- ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
-
-/*
- * freq = 150MHz -> t=7ns
- */
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
- (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
- (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
- (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
- (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
- (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
- (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
- (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
- (2 << DV_DDR_SDTMR2_CKE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2 | \
- DAVINCI_SYSCFG_SUSPSRC_EMAC |\
- DAVINCI_SYSCFG_SUSPSRC_I2C)
-
-#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
- DAVINCI_ABCR_WSTROBE(6) | \
- DAVINCI_ABCR_WHOLD(1) | \
- DAVINCI_ABCR_RSETUP(2) | \
- DAVINCI_ABCR_RSTROBE(6) | \
- DAVINCI_ABCR_RHOLD(1) | \
- DAVINCI_ABCR_ASIZE_16BIT)
-
-#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
- DAVINCI_ABCR_WSTROBE(2) | \
- DAVINCI_ABCR_WHOLD(1) | \
- DAVINCI_ABCR_RSETUP(1) | \
- DAVINCI_ABCR_RSTROBE(6) | \
- DAVINCI_ABCR_RHOLD(1) | \
- DAVINCI_ABCR_ASIZE_8BIT)
-
-/*
- * NOR Bootconfiguration word:
- * Method: Direc boot
- * EMIFA access mode: 16 Bit
- */
-#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
-
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS
-#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 11/45] arm: Remove ima3-mx53 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (9 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 10/45] arm: Remove enbw_cmc board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,11/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards Simon Glass
` (34 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/esg/ima3-mx53/Kconfig | 15 ---
board/esg/ima3-mx53/MAINTAINERS | 6 -
board/esg/ima3-mx53/Makefile | 9 --
board/esg/ima3-mx53/ima3-mx53.c | 206 ---------------------------------
board/esg/ima3-mx53/imximage.cfg | 104 -----------------
configs/ima3-mx53_defconfig | 6 -
include/configs/ima3-mx53.h | 238 ---------------------------------------
8 files changed, 589 deletions(-)
delete mode 100644 board/esg/ima3-mx53/Kconfig
delete mode 100644 board/esg/ima3-mx53/MAINTAINERS
delete mode 100644 board/esg/ima3-mx53/Makefile
delete mode 100644 board/esg/ima3-mx53/ima3-mx53.c
delete mode 100644 board/esg/ima3-mx53/imximage.cfg
delete mode 100644 configs/ima3-mx53_defconfig
delete mode 100644 include/configs/ima3-mx53.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fa52901..0b63698 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -475,10 +475,6 @@ config TARGET_M53EVK
select CPU_V7
select SUPPORT_SPL
-config TARGET_IMA3_MX53
- bool "Support ima3-mx53"
- select CPU_V7
-
config TARGET_MX51EVK
bool "Support mx51evk"
select CPU_V7
@@ -894,7 +890,6 @@ source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
diff --git a/board/esg/ima3-mx53/Kconfig b/board/esg/ima3-mx53/Kconfig
deleted file mode 100644
index d73238f..0000000
--- a/board/esg/ima3-mx53/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_IMA3_MX53
-
-config SYS_BOARD
- default "ima3-mx53"
-
-config SYS_VENDOR
- default "esg"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "ima3-mx53"
-
-endif
diff --git a/board/esg/ima3-mx53/MAINTAINERS b/board/esg/ima3-mx53/MAINTAINERS
deleted file mode 100644
index 96de081..0000000
--- a/board/esg/ima3-mx53/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IMA3-MX53 BOARD
-#M: -
-S: Maintained
-F: board/esg/ima3-mx53/
-F: include/configs/ima3-mx53.h
-F: configs/ima3-mx53_defconfig
diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
deleted file mode 100644
index afb8925..0000000
--- a/board/esg/ima3-mx53/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
-#
-# Based on ti/evm/Makefile
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ima3-mx53.o
diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
deleted file mode 100644
index df758ee..0000000
--- a/board/esg/ima3-mx53/ima3-mx53.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/gpio.h>
-
-/* NOR flash configuration */
-#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
-#define IMA3_MX53_CS0GCR2 0
-#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
-#define IMA3_MX53_CS0RCR2 0
-#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
-#define IMA3_MX53_CS0WCR2 0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void weim_nor_settings(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
- writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
- writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
- writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
- writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
- writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
- writel(0x0, &weim_regs->wcr);
-
- set_chipselect_size(CS0_128);
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
- NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- int ret;
-
- ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
-
- return ret;
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
-
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
- gpio_direction_input(IMX_GPIO_NR(1, 1));
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-#endif
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
- /* SSEL 0 */
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
- gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
-}
-
-int board_early_init_f(void)
-{
- /* configure I/O pads */
- setup_iomux_uart();
- setup_iomux_fec();
-
- weim_nor_settings();
-
- /* configure spi */
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- mxc_set_sata_internal_clock();
-
- return 0;
-}
-
-#if defined(CONFIG_RESET_PHY_R)
-#include <miiphy.h>
-
-void reset_phy(void)
-{
- unsigned short reg;
-
- /* reset the phy */
- miiphy_reset("FEC", CONFIG_PHY_ADDR);
-
- /* set hard link to 100Mbit, full-duplex */
- miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
- reg &= ~BMCR_ANENABLE;
- reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
- miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
-
- miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
- reg |= (1 << 5);
- miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
-}
-#endif
-
-int checkboard(void)
-{
- puts("Board: IMA3_MX53\n");
-
- return 0;
-}
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
deleted file mode 100644
index 324a90e..0000000
--- a/board/esg/ima3-mx53/imximage.cfg
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2012
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM nor
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/* IOMUX for RAM only */
-DATA 4 0x53fa8554 0x300020
-DATA 4 0x53fa8560 0x300020
-DATA 4 0x53fa8594 0x300020
-DATA 4 0x53fa8584 0x300020
-DATA 4 0x53fa8558 0x300040
-DATA 4 0x53fa8568 0x300040
-DATA 4 0x53fa8590 0x300040
-DATA 4 0x53fa857c 0x300040
-DATA 4 0x53fa8564 0x300040
-DATA 4 0x53fa8580 0x300040
-DATA 4 0x53fa8570 0x300220
-DATA 4 0x53fa8578 0x300220
-DATA 4 0x53fa872c 0x300000
-DATA 4 0x53fa8728 0x300000
-DATA 4 0x53fa871c 0x300000
-DATA 4 0x53fa8718 0x300000
-DATA 4 0x53fa8574 0x300020
-DATA 4 0x53fa8588 0x300020
-DATA 4 0x53fa855c 0x0
-DATA 4 0x53fa858c 0x0
-DATA 4 0x53fa856c 0x300040
-DATA 4 0x53fa86f0 0x300000
-DATA 4 0x53fa8720 0x300000
-DATA 4 0x53fa86fc 0x0
-DATA 4 0x53fa86f4 0x0
-DATA 4 0x53fa8714 0x0
-DATA 4 0x53fa8724 0x4000000
-
-/* DDR RAM */
-DATA 4 0x63fd9088 0x40404040
-DATA 4 0x63fd9090 0x40404040
-DATA 4 0x63fd907C 0x01420143
-DATA 4 0x63fd9080 0x01450146
-DATA 4 0x63fd9018 0x00111740
-DATA 4 0x63fd9000 0x84190000
-
-/* esdcfgX */
-DATA 4 0x63fd900C 0x9f5152e3
-DATA 4 0x63fd9010 0xb68e8a63
-DATA 4 0x63fd9014 0x01ff00db
-
-/* Read/Write command delay */
-DATA 4 0x63fd902c 0x000026d2
-
-/* Out of reset delays */
-DATA 4 0x63fd9030 0x00ff0e21
-
-/* ESDCTL ODT timing control */
-DATA 4 0x63fd9008 0x12273030
-
-/* ESDCTL power down control */
-DATA 4 0x63fd9004 0x0002002d
-
-/* Set registers in DDR memory chips */
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x052080b0
-DATA 4 0x63fd901c 0x04008040
-
-/* ESDCTL refresh control */
-DATA 4 0x63fd9020 0x00005800
-
-/* PHY ZQ HW control */
-DATA 4 0x63fd9040 0x05380003
-
-/* PHY ODT control */
-DATA 4 0x63fd9058 0x00022222
-
-/* start DDR3 */
-DATA 4 0x63fd901c 0x00000000
diff --git a/configs/ima3-mx53_defconfig b/configs/ima3-mx53_defconfig
deleted file mode 100644
index 1f5e3a6..0000000
--- a/configs/ima3-mx53_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_IMA3_MX53=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="IMA3 MX53 U-Boot > "
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
deleted file mode 100644
index 2fa6c3d..0000000
--- a/include/configs/ima3-mx53.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53-EVK Freescale board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SOC type must be included before imx-regs.h */
-#define CONFIG_MX53
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_OF_LIBFDT
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* Enable GPIOs */
-#define CONFIG_MXC_GPIO
-
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
-
-/* MMC */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/* Ethernet on FEC */
-#define CONFIG_MII
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x01
-#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR
-#define CONFIG_RESET_PHY_R
-#define CONFIG_FEC_MXC_NO_ANEG
-#define CONFIG_ETHPRIME "FEC0"
-
-/* SPI */
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
-
-/* SPI FLASH - not used for environment */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_GPIO
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
-#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x70000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nor0=f0000000.flash"
-
-/* FLASH and environment organization */
-
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
-#define CONFIG_FLASH_CFI_MTD /* with MTD support */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define HOSTNAME ima3-mx53
-
-#define CONFIG_HOSTNAME ima3-mx53
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram0 rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${console},${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "console=ttymxc3\0" \
- "loadaddr=70800000\0" \
- "kernel_addr_r=70800000\0" \
- "ramdisk_addr_r=71000000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
- "mmcargs=setenv bootargs root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs addip addtty addmtd addmisc mmcload;" \
- "bootm\0" \
- "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \
- "${loadaddr} ${uimage}\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \
- "tftp ${kernel_addr_r} ${bootfile}\0" \
- "net_self=if run net_self_load;then " \
- "run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
- "else echo Images not loades;fi\0" \
- "satargs=setenv bootargs root=/dev/sda1\0" \
- "satafile=boot/uImage\0" \
- "ssdboot=echo Booting from ssd ...; " \
- "run satargs addip addtty addmtd addmisc;" \
- "sata init;ext2load sata 0:1 ${kernel_addr_r} " \
- "${satafile};bootm\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \
- "uimage=uImage\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=0xf0001000\0" \
- "update=protect off 0xf0000000 +60000;" \
- "erase ${uboot_addr} +60000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-
-#define CONFIG_CMD_SATA
-#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
- #define CONFIG_SYS_SATA_MAX_DEVICE 1
- #define CONFIG_DWC_AHSATA_PORT_ID 0
- #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
- #define CONFIG_LBA48
- #define CONFIG_LIBATA
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (10 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 11/45] arm: Remove ima3-mx53 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 13/45] arm: Remove mx31_litekit board Simon Glass
` (33 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 9 --
board/logicpd/imx27lite/Kconfig | 31 -------
board/logicpd/imx27lite/MAINTAINERS | 12 ---
board/logicpd/imx27lite/Makefile | 9 --
board/logicpd/imx27lite/imx27lite.c | 77 ----------------
board/logicpd/imx27lite/lowlevel_init.S | 156 --------------------------------
configs/imx27lite_defconfig | 3 -
configs/magnesium_defconfig | 3 -
include/configs/imx27lite.h | 49 ----------
include/configs/magnesium.h | 58 ------------
10 files changed, 407 deletions(-)
delete mode 100644 board/logicpd/imx27lite/Kconfig
delete mode 100644 board/logicpd/imx27lite/MAINTAINERS
delete mode 100644 board/logicpd/imx27lite/Makefile
delete mode 100644 board/logicpd/imx27lite/imx27lite.c
delete mode 100644 board/logicpd/imx27lite/lowlevel_init.S
delete mode 100644 configs/imx27lite_defconfig
delete mode 100644 configs/magnesium_defconfig
delete mode 100644 include/configs/imx27lite.h
delete mode 100644 include/configs/magnesium.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0b63698..36ec100 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -142,14 +142,6 @@ config TARGET_APF27
select CPU_ARM926EJS
select SUPPORT_SPL
-config TARGET_IMX27LITE
- bool "Support imx27lite"
- select CPU_ARM926EJS
-
-config TARGET_MAGNESIUM
- bool "Support magnesium"
- select CPU_ARM926EJS
-
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
select CPU_ARM926EJS
@@ -924,7 +916,6 @@ source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/kosagi/novena/Kconfig"
-source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig
deleted file mode 100644
index c7de2e3..0000000
--- a/board/logicpd/imx27lite/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if TARGET_IMX27LITE
-
-config SYS_BOARD
- default "imx27lite"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx27"
-
-config SYS_CONFIG_NAME
- default "imx27lite"
-
-endif
-
-if TARGET_MAGNESIUM
-
-config SYS_BOARD
- default "imx27lite"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx27"
-
-config SYS_CONFIG_NAME
- default "magnesium"
-
-endif
diff --git a/board/logicpd/imx27lite/MAINTAINERS b/board/logicpd/imx27lite/MAINTAINERS
deleted file mode 100644
index a7b22ac..0000000
--- a/board/logicpd/imx27lite/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-IMX27LITE BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/logicpd/imx27lite/
-F: include/configs/imx27lite.h
-F: configs/imx27lite_defconfig
-
-MAGNESIUM BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: include/configs/magnesium.h
-F: configs/magnesium_defconfig
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
deleted file mode 100644
index 50a3da6..0000000
--- a/board/logicpd/imx27lite/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx27lite.o
-obj-y += lowlevel_init.o
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
deleted file mode 100644
index 07b07a0..0000000
--- a/board/logicpd/imx27lite/imx27lite.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-#ifdef CONFIG_MXC_UART
- mx27_uart1_init_pins();
-#endif
-#ifdef CONFIG_FEC_MXC
- mx27_fec_init_pins();
- imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
- gpio_set_value(GPIO_PORTC | 31, 1);
-#endif
-#ifdef CONFIG_MXC_MMC
-#if defined(CONFIG_MAGNESIUM)
- mx27_sd1_init_pins();
-#else
- mx27_sd2_init_pins();
-#endif
-#endif
-
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
- /*
- * set in FMCR NF_FMS Bit(5) to 1
- * (NAND Flash with 2 Kbyte page size)
- */
- writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
-#endif
-}
-
-int checkboard(void)
-{
- puts("Board: ");
- puts(CONFIG_BOARDNAME);
- return 0;
-}
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
deleted file mode 100644
index 9cb702f..0000000
--- a/board/logicpd/imx27lite/lowlevel_init.S
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-#include <asm/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
-SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
-SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
-SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
-SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
-
-.macro init_aipi
- /*
- * setup AIPI1 and AIPI2
- */
- write32 AIPI1_PSR0, AIPI1_PSR0_VAL
- write32 AIPI1_PSR1, AIPI1_PSR1_VAL
- write32 AIPI2_PSR0, AIPI2_PSR0_VAL
- write32 AIPI2_PSR1, AIPI2_PSR1_VAL
-
-.endm /* init_aipi */
-
-.macro init_clock
- ldr r0, =CSCR
- /* disable MPLL/SPLL first */
- ldr r1, [r0]
- bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
- str r1, [r0]
-
- write32 MPCTL0, MPCTL0_VAL
- write32 SPCTL0, SPCTL0_VAL
-
- write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
-
- /*
- * add some delay here
- */
- wait_timer 0x1000
-
- /* peripheral clock divider */
- write32 PCDR0, PCDR0_VAL
- write32 PCDR1, PCDR1_VAL
-
- /* Configure PCCR0 and PCCR1 */
- write32 PCCR0, PCCR0_VAL
- write32 PCCR1, PCCR1_VAL
-
-.endm /* init_clock */
-
-.macro sdram_init
- ldr r0, SOC_ESDCTL_BASE_W
- mov r2, #PHYS_SDRAM_1
-
- /* Do initial reset */
- mov r1, #ESDMISC_MDDR_DL_RST
- str r1, [r0, #ESDMISC_ROF]
-
- /* Hold for more than 200ns */
- wait_timer 0x10000
-
- /* Activate LPDDR iface */
- mov r1, #ESDMISC_MDDREN
- str r1, [r0, #ESDMISC_ROF]
-
- /* Check The chip version TO1 or TO2 */
- ldr r1, SOC_SI_ID_REG_W
- ldr r1, [r1]
- ands r1, r1, #0xF0000000
- /* add Latency on CAS only for TO2 */
- ldreq r1, SDRAM_ESDCFG_T2_W
- ldrne r1, SDRAM_ESDCFG_T1_W
- str r1, [r0, #ESDCFG0_ROF]
-
- /* Run initialization sequence */
- ldr r1, SDRAM_PRECHARGE_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_AUTOREF_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_LOADMODE_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
- add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
- ldrb r1, [r3]
-
- ldr r1, SDRAM_NORMAL_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
-
-#if (CONFIG_NR_DRAM_BANKS > 1)
- /* 2nd sdram */
- mov r2, #PHYS_SDRAM_2
-
- /* Check The chip version TO1 or TO2 */
- ldr r1, SOC_SI_ID_REG_W
- ldr r1, [r1]
- ands r1, r1, #0xF0000000
- /* add Latency on CAS only for TO2 */
- ldreq r1, SDRAM_ESDCFG_T2_W
- ldrne r1, SDRAM_ESDCFG_T1_W
- str r1, [r0, #ESDCFG1_ROF]
-
- /* Run initialization sequence */
- ldr r1, SDRAM_PRECHARGE_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_AUTOREF_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_LOADMODE_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
- add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
- ldrb r1, [r3]
-
- ldr r1, SDRAM_NORMAL_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
-#endif /* CONFIG_NR_DRAM_BANKS > 1 */
-
-.endm /* sdram_init */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- init_aipi
-
- init_clock
-
- sdram_init
-
- mov pc,r10
diff --git a/configs/imx27lite_defconfig b/configs/imx27lite_defconfig
deleted file mode 100644
index b02955d..0000000
--- a/configs/imx27lite_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_IMX27LITE=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/magnesium_defconfig b/configs/magnesium_defconfig
deleted file mode 100644
index 2fa6589..0000000
--- a/configs/magnesium_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MAGNESIUM=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
deleted file mode 100644
index c18c35e..0000000
--- a/include/configs/imx27lite.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* include common defines/options for all imx27lite related boards */
-#include "imx27lite-common.h"
-/*
- * SoC Configuration
- */
-#define CONFIG_IMX27LITE
-#define CONFIG_HOSTNAME imx27
-#define CONFIG_BOARDNAME "LogicPD imx27lite\n"
-
-/*
- * Flash & Environment
- */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
-#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
-#define PHYS_FLASH_SIZE 0x200000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
-
-/*
- * SD/MMC
- */
-#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
-
-/*
- * MTD partitions
- */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "256k(U-Boot)," \
- "1664k(user)," \
- "64k(env1)," \
- "64k(env2);" \
- "mxc_nand.0:" \
- "128k(IPL-SPL)," \
- "4m(kernel)," \
- "22m(rootfs)," \
- "-(userfs)"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h
deleted file mode 100644
index 3364bde..0000000
--- a/include/configs/magnesium.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
- *
- * based on:
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* include common defines/options for all imx27lite related boards */
-#include "imx27lite-common.h"
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MAGNESIUM
-#define CONFIG_HOSTNAME magnesium
-#define CONFIG_BOARDNAME "Projectiondesign magnesium\n"
-
-/*
- * Flash & Environment
- */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */
-#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000)
-#define PHYS_FLASH_SIZE 0x800000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */
-
-/*
- * NAND
- */
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/*
- * SD/MMC
- */
-#define CONFIG_MXC_MCI_REGS_BASE 0x10013000
-
-/*
- * MTD partitions
- */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "256k(U-Boot)," \
- "7680k(user)," \
- "128k(env1)," \
- "128k(env2);" \
- "mxc_nand.0:" \
- "128k(IPL-SPL)," \
- "4m(kernel)," \
- "22m(rootfs)," \
- "-(userfs)"
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 13/45] arm: Remove mx31_litekit board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (11 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,13/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 14/45] arm: Remove inetspace_v2_cmc board Simon Glass
` (32 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/logicpd/imx31_litekit/Kconfig | 15 ---
board/logicpd/imx31_litekit/MAINTAINERS | 6 -
board/logicpd/imx31_litekit/Makefile | 9 --
board/logicpd/imx31_litekit/imx31_litekit.c | 91 ---------------
board/logicpd/imx31_litekit/lowlevel_init.S | 87 --------------
configs/imx31_litekit_defconfig | 4 -
include/configs/imx31_litekit.h | 171 ----------------------------
8 files changed, 388 deletions(-)
delete mode 100644 board/logicpd/imx31_litekit/Kconfig
delete mode 100644 board/logicpd/imx31_litekit/MAINTAINERS
delete mode 100644 board/logicpd/imx31_litekit/Makefile
delete mode 100644 board/logicpd/imx31_litekit/imx31_litekit.c
delete mode 100644 board/logicpd/imx31_litekit/lowlevel_init.S
delete mode 100644 configs/imx31_litekit_defconfig
delete mode 100644 include/configs/imx31_litekit.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36ec100..9016bfd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -250,10 +250,6 @@ config TARGET_TT01
bool "Support tt01"
select CPU_ARM1136
-config TARGET_IMX31_LITEKIT
- bool "Support imx31_litekit"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
@@ -916,7 +912,6 @@ source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/kosagi/novena/Kconfig"
-source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
diff --git a/board/logicpd/imx31_litekit/Kconfig b/board/logicpd/imx31_litekit/Kconfig
deleted file mode 100644
index d90f854..0000000
--- a/board/logicpd/imx31_litekit/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_IMX31_LITEKIT
-
-config SYS_BOARD
- default "imx31_litekit"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "imx31_litekit"
-
-endif
diff --git a/board/logicpd/imx31_litekit/MAINTAINERS b/board/logicpd/imx31_litekit/MAINTAINERS
deleted file mode 100644
index 8e3608e..0000000
--- a/board/logicpd/imx31_litekit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IMX31_LITEKIT BOARD
-#M: -
-S: Maintained
-F: board/logicpd/imx31_litekit/
-F: include/configs/imx31_litekit.h
-F: configs/imx31_litekit_defconfig
diff --git a/board/logicpd/imx31_litekit/Makefile b/board/logicpd/imx31_litekit/Makefile
deleted file mode 100644
index 3fd71c8..0000000
--- a/board/logicpd/imx31_litekit/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx31_litekit.o
-obj-y += lowlevel_init.o
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
deleted file mode 100644
index 386e106..0000000
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS0: Nor Flash */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- /* CS4: Network Controller */
- static const struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
- mxc_setup_weimcs(4, &cs4);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* SPI2 */
- mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
- /* start SPI2 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: i.MX31 Litekit\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S
deleted file mode 100644
index 7c456bc..0000000
--- a/board/logicpd/imx31_litekit/lowlevel_init.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG IPU_CONF, IPU_CONF_DI_EN
- REG CCM_CCMR, 0x074B0BF5
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
-
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
- REG 0x43FAC26C, 0 /* SDCLK */
- REG 0x43FAC270, 0 /* CAS */
- REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
- REG 0x43FAC284, 0 /* DQM3 */
- REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- REG 0x43FAC28C, 0
- REG 0x43FAC290, 0
- REG 0x43FAC294, 0
- REG 0x43FAC298, 0
- REG 0x43FAC29C, 0
- REG 0x43FAC2A0, 0
- REG 0x43FAC2A4, 0
- REG 0x43FAC2A8, 0
- REG 0x43FAC2AC, 0
- REG 0x43FAC2B0, 0
- REG 0x43FAC2B4, 0
- REG 0x43FAC2B8, 0
- REG 0x43FAC2BC, 0
- REG 0x43FAC2C0, 0
- REG 0x43FAC2C4, 0
- REG 0x43FAC2C8, 0
- REG 0x43FAC2CC, 0
- REG 0x43FAC2D0, 0
- REG 0x43FAC2D4, 0
- REG 0x43FAC2D8, 0
- REG 0x43FAC2DC, 0
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
diff --git a/configs/imx31_litekit_defconfig b/configs/imx31_litekit_defconfig
deleted file mode 100644
index f10759b..0000000
--- a/configs/imx31_litekit_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_LITEKIT=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="uboot> "
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
deleted file mode 100644
index 23e3a6c..0000000
--- a/include/configs/imx31_litekit.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the LogicPD i.MX31 Litekit board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX31 1 /* This is a mx31 */
-#define CONFIG_MX31_CLK32 32000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
-
-/* Temporarily disabled */
-#if 0
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-#endif
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MXC_SPI 1
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 1
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.23.168
-#define CONFIG_SERVERIP 192.168.23.2
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
- "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
- "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
-
-
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
-#define CONFIG_SMC911X_32_BIT 1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
-
-#define CONFIG_CMDLINE_EDITING 1
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE (64 * 1024)
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/*
- * JFFS2 partitions
- */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-
-/*
- * NAND flash
- */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 14/45] arm: Remove inetspace_v2_cmc board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (12 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 13/45] arm: Remove mx31_litekit board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,14/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 15/45] arm: Remove jornada board Simon Glass
` (31 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/inetspace_v2_defconfig | 8 --------
1 file changed, 8 deletions(-)
delete mode 100644 configs/inetspace_v2_defconfig
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
deleted file mode 100644
index f314059..0000000
--- a/configs/inetspace_v2_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 15/45] arm: Remove jornada board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (13 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 14/45] arm: Remove inetspace_v2_cmc board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,15/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 16/45] arm: Remove lp8x4x board Simon Glass
` (30 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 --
board/jornada/Kconfig | 9 ---
board/jornada/MAINTAINERS | 6 --
board/jornada/Makefile | 11 ---
board/jornada/jornada.c | 44 -----------
board/jornada/setup.S | 194 ----------------------------------------------
configs/jornada_defconfig | 9 ---
include/configs/jornada.h | 123 -----------------------------
8 files changed, 401 deletions(-)
delete mode 100644 board/jornada/Kconfig
delete mode 100644 board/jornada/MAINTAINERS
delete mode 100644 board/jornada/Makefile
delete mode 100644 board/jornada/jornada.c
delete mode 100644 board/jornada/setup.S
delete mode 100644 configs/jornada_defconfig
delete mode 100644 include/configs/jornada.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9016bfd..c8b07a1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -774,10 +774,6 @@ config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
-config TARGET_JORNADA
- bool "Support jornada"
- select CPU_SA1100
-
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CPU_V7
@@ -909,7 +905,6 @@ source "board/hale/tt01/Kconfig"
source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/maxbcm/Kconfig"
diff --git a/board/jornada/Kconfig b/board/jornada/Kconfig
deleted file mode 100644
index 195bc26..0000000
--- a/board/jornada/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_JORNADA
-
-config SYS_BOARD
- default "jornada"
-
-config SYS_CONFIG_NAME
- default "jornada"
-
-endif
diff --git a/board/jornada/MAINTAINERS b/board/jornada/MAINTAINERS
deleted file mode 100644
index c77d745..0000000
--- a/board/jornada/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JORNADA BOARD
-M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
-S: Maintained
-F: board/jornada/
-F: include/configs/jornada.h
-F: configs/jornada_defconfig
diff --git a/board/jornada/Makefile b/board/jornada/Makefile
deleted file mode 100644
index 6a6fbf3..0000000
--- a/board/jornada/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# 2004 (c) MontaVista Software, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := jornada.o
-obj-y += setup.o
diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c
deleted file mode 100644
index ff6dbf0..0000000
--- a/board/jornada/jornada.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * 2004 (c) MontaVista Software, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <SA-1100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
- gd->bd->bi_boot_params = 0xc0000100;
-
-
- /*
- * Turn on flashing.
- * Would be nice to have some protection but
- * that would have to be implemented in the
- * flash init function, which isnt possible yet.
- */
- PPSR |= (1 << 7);
- PPDR |= (1 << 7);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return (0);
-}
diff --git a/board/jornada/setup.S b/board/jornada/setup.S
deleted file mode 100644
index da9f006..0000000
--- a/board/jornada/setup.S
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
- * 2004 (c) MontaVista Software, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*-----------------------------------------------------------------------
- * Board defines:
- */
-
-#define MDCNFG 0x00
-#define MDCAS00 0x04
-#define MDCAS01 0x08
-#define MDCAS02 0x0C
-#define MSC0 0x10
-#define MSC1 0x14
-#define MECR 0x18
-#define MDREFR 0x1C
-#define MDCAS20 0x20
-#define MDCAS21 0x24
-#define MDCAS22 0x28
-#define MSC2 0x2C
-#define SMCNFG 0x30
-
-#define GPDR 0x04
-#define GPSR 0x08
-#define GPCR 0x0C
-#define GAFR 0x1C
-
-#define PPDR 0x00
-#define PPSR 0x04
-#define PPAR 0x08
-
-#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
-#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
-#define MDREFR_K0DB2 (1 << 18)
-#define MDREFR_K1DB2 (1 << 22)
-#define MDREFR_K2DB2 (1 << 26)
-
-#define MDREFR_K0RUN (1 << 17)
-#define MDREFR_K1RUN (1 << 21)
-#define MDREFR_K2RUN (1 << 25)
-
-#define MDREFR_SLFRSH (1 << 31)
-#define MDREFR_E1PIN (1 << 20)
-
-#define PSSR 0x04
-#define PSSR_DH 0x00000008
-#define POSR 0x08
-#define RCSR 0x04
-
-/*-----------------------------------------------------------------------
- * Setup parameters for the board:
- */
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-PWR_BASE: .word 0x90020000
-RST_BASE: .long 0x90030000
-PPC_BASE: .long 0x90060000
-GPIO_BASE: .long 0x90040000
-IC_BASE: .word 0x90050000
-
-cpuspeed: .word 0xa0
-/* calculated from old blob bootloader */
-mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
-mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
-mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
-mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
-msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
-msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
-mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
-mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
-mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
-mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
-mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
-msc2: .long 0x201d2959 /* msc2 0x201d2959 */
-smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
-
-pin_set_out: .long 0x37ff70
-pin_set_dir: .long 0x11480
-
-gpdr_set: .long 0x0B3A0900
-gpsr_set: .long 0x02100800
-gpcr_set: .long 0x092A0100
-gafr_set: .long 0x08600000
-
-.globl lowlevel_init
-lowlevel_init:
-
-
- /* this is required for flashing */
- ldr r0, PPC_BASE
- ldr r1, pin_set_out
- str r1, [r0, #PPSR]
- ldr r1, pin_set_dir
- str r1, [r0, #PPDR]
-
- /* Setting up the memory and stuff */
- /***********************************/
-
- ldr r0, MEM_BASE
-
- ldr r1, mdcnfg
- str r1, [r0, #MDCNFG]
- ldr r1, mdcas00
- str r1, [r0, #MDCAS00]
- ldr r1, mdcas01
- str r1, [r0, #MDCAS01]
- ldr r1, mdcas02
- str r1, [r0, #MDCAS02]
- ldr r1, mdcas20
- str r1, [r0, #MDCAS20]
- ldr r1, mdcas21
- str r1, [r0, #MDCAS21]
- ldr r1, mdcas22
- str r1, [r0, #MDCAS22]
-
- /* clear kxDB2 */
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_K0DB2
- bic r2, r2, #MDREFR_K1DB2
- bic r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_TRASR(7)
-
- mov r4, #0x2000
- spin: subs r4, r4, #1
- bne spin
-
- ldr r1, PWR_BASE
- mov r2, #PSSR_DH
- str r2, [r1, #PSSR]
-
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_K0DB2
- bic r2, r2, #MDREFR_K1DB2
- bic r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_TRASR(7)
- orr r2, r2, #MDREFR_DRI(12)
- orr r2, r2, #MDREFR_K0DB2
- orr r2, r2, #MDREFR_K1DB2
- orr r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_K0RUN
- orr r2, r2, #MDREFR_K1RUN
- orr r2, r2, #MDREFR_K2RUN
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_SLFRSH
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_E1PIN
- str r2, [r0, #MDREFR]
-
- ldr r2, MEM_START
-.rept 8
- ldr r3, [r2]
-.endr
-
- ldr r2, [r0, #MDCNFG]
- orr r2, r2, #0x00000003
- orr r2, r2, #0x00030000
- str r2, [r0, #MDCNFG]
-
- ldr r1, msc0
- str r1, [r0, #MSC0]
- ldr r1, msc1
- str r1, [r0, #MSC1]
- ldr r1, msc2
- str r1, [r0, #MSC2]
- ldr r1, smcnfg
- str r1, [r0, #SMCNFG]
- ldr r1, mecr
- str r1, [r0, #MECR]
-
- mov pc, lr
diff --git a/configs/jornada_defconfig b/configs/jornada_defconfig
deleted file mode 100644
index 65cbc2a..0000000
--- a/configs/jornada_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_JORNADA=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="HP Jornada# "
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
deleted file mode 100644
index 3090476..0000000
--- a/include/configs/jornada.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2010 (C)
- * Kristoffer Ericson <kristoffer.ericson@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1110 1 /* This is an SA110 CPU */
-#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_SYS_TEXT_BASE 0xC1F00000
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Console setting */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SA1100_SERIAL 1
-#define CONFIG_SERIAL3 1 /* we use serial 3 */
-#define CONFIG_BAUDRATE 19200
-#define CONFIG_LOADS_ECHO 1
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
-#define CONFIG_BOOTCOMMAND "run boot_kernel"
-#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
-#define CONFIG_SYS_LOAD_ADDR 0xc0000000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
-#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
-#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
-#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_ERASE_TOUT (4096)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (4096)
-#define CONFIG_SYS_FLASH_INCREMENT 0x02000000
-#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */
-#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 260
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_FLASH_SHOW_PROGRESS 1
-
-/* Environment */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x00040000
-#define CONFIG_ENV_OFFSET 0x00040000
-#define CONFIG_ENV_SIZE 0x00040000
-#define CONFIG_ENV_SECT_SIZE 0x00040000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- Monitor - 0x00000000 - 0x00040000 (256kb)
- Environment - 0x00040000 - 0x00080000 (256kb)
- Kernel - 0x00080000 - 0x00380000 (3mb)
- Rootfs - 0x00380000 - 0x........ (rest)
-*/
-
-#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_INIT_SP_ADDR 0x0
-#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=jornada7xx-0"
-#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
- "3m(kernel),-(user);"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "flash_kernel=protect off all; " \
- "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \
- "flash_uboot=protect off all; " \
- "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \
- "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 16/45] arm: Remove lp8x4x board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (14 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 15/45] arm: Remove jornada board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,16/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards Simon Glass
` (29 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/icpdas/lp8x4x/Kconfig | 12 --
board/icpdas/lp8x4x/MAINTAINERS | 6 -
board/icpdas/lp8x4x/Makefile | 9 --
board/icpdas/lp8x4x/lp8x4x.c | 128 ---------------------
configs/lp8x4x_defconfig | 4 -
include/configs/lp8x4x.h | 238 ----------------------------------------
7 files changed, 402 deletions(-)
delete mode 100644 board/icpdas/lp8x4x/Kconfig
delete mode 100644 board/icpdas/lp8x4x/MAINTAINERS
delete mode 100644 board/icpdas/lp8x4x/Makefile
delete mode 100644 board/icpdas/lp8x4x/lp8x4x.c
delete mode 100644 configs/lp8x4x_defconfig
delete mode 100644 include/configs/lp8x4x.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c8b07a1..62b28d9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -766,10 +766,6 @@ config TARGET_ZIPITZ2
bool "Support zipitz2"
select CPU_PXA
-config TARGET_LP8X4X
- bool "Support lp8x4x"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@@ -902,7 +898,6 @@ source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
-source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/karo/tx25/Kconfig"
diff --git a/board/icpdas/lp8x4x/Kconfig b/board/icpdas/lp8x4x/Kconfig
deleted file mode 100644
index 3e87c40..0000000
--- a/board/icpdas/lp8x4x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LP8X4X
-
-config SYS_BOARD
- default "lp8x4x"
-
-config SYS_VENDOR
- default "icpdas"
-
-config SYS_CONFIG_NAME
- default "lp8x4x"
-
-endif
diff --git a/board/icpdas/lp8x4x/MAINTAINERS b/board/icpdas/lp8x4x/MAINTAINERS
deleted file mode 100644
index 90a82e3..0000000
--- a/board/icpdas/lp8x4x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LP8X4X BOARD
-M: Sergey Yanovich <ynvich@gmail.com>
-S: Maintained
-F: board/icpdas/lp8x4x/
-F: include/configs/lp8x4x.h
-F: configs/lp8x4x_defconfig
diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile
deleted file mode 100644
index 88e0606..0000000
--- a/board/icpdas/lp8x4x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# ICPDAS LP-8x4x Support
-#
-# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := lp8x4x.o
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
deleted file mode 100644
index a136dc4..0000000
--- a/board/icpdas/lp8x4x/lp8x4x.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * ICP DAS LP-8x4x Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * adapted from Voipac PXA270 Support by
- * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
-#include <asm/arch/pxa.h>
-#include <netdev.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- if (index !=0 || init != USB_INIT_HOST)
- return -1;
-
- writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
-
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- continue; /* required by checkpath.pl */
-
- writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
- writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
- writel(readl(UHCRHDA) | 0x800, UHCRHDA);
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- return 0;
-}
-
-int usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- if (index !=0 || init != USB_INIT_HOST)
- return -1;
-
- return usb_board_stop();
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
diff --git a/configs/lp8x4x_defconfig b/configs/lp8x4x_defconfig
deleted file mode 100644
index 63bbcca..0000000
--- a/configs/lp8x4x_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LP8X4X=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h
deleted file mode 100644
index 10a7b05..0000000
--- a/include/configs/lp8x4x.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * ICP DAS LP-8x4x configuration file
- *
- * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
-#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
-#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "bootm 80000 - 240000;"
-
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
- "init=/sbin/init rootfstype=ext4 rootwait"
-
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_LZMA /* LZMA compression support */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
-#undef CONFIG_LCD
-#undef CONFIG_CMD_IDE
-
-/*
- * Networking Configuration
- * chip on the ICPDAS LINPAC board
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x0C000000
-#define DM9000_IO 0x0C000000
-#define DM9000_DATA 0x0C004000
-#define DM9000_IO_2 0x0D000000
-#define DM9000_DATA_2 0x0D004000
-#define CONFIG_NET_RETRY_COUNT 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa0008000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-/* Use first 64kb bank of the internal SRAM */
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
-
-/*
- * NOR FLASH
- */
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x0808c014
-#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
-#define CONFIG_SYS_GPSR2_VAL 0x0221c000
-#define CONFIG_SYS_GPSR3_VAL 0x00020000
-
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
-#define CONFIG_SYS_GPCR2_VAL 0x00100000
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
-#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
-#define CONFIG_SYS_GPDR3_VAL 0x00021b81
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
-#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402
-#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
-
-#define CONFIG_SYS_PSSR_VAL 0x32
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x005002c0
-#define CONFIG_SYS_CCCR 0x02000290
-#define CONFIG_SYS_CLKCFG 0x0000000b
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
-#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
-#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
-#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
-#define CONFIG_SYS_MDREFR_VAL 0x2093e018
-#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
-#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
-#define CONFIG_SYS_MCATT0_VAL 0x0000c497
-#define CONFIG_SYS_MCATT1_VAL 0x0000c497
-#define CONFIG_SYS_MCIO0_VAL 0x00008407
-#define CONFIG_SYS_MCIO1_VAL 0x00008407
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
-#define CONFIG_USB_STORAGE
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (15 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 16/45] arm: Remove lp8x4x board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 5:30 ` Daniel Gorsulowski
2015-08-31 5:32 ` [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board Daniel Gorsulowski
2015-08-31 1:19 ` [U-Boot] [PATCH 18/45] arm: Remove mv88f6281gtw_ge board Simon Glass
` (28 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 5 -
board/esd/meesc/Kconfig | 12 --
board/esd/meesc/MAINTAINERS | 7 -
board/esd/meesc/Makefile | 13 --
board/esd/meesc/meesc.c | 271 --------------------------------------
board/esd/meesc/partition.c | 23 ----
configs/meesc_dataflash_defconfig | 9 --
configs/meesc_defconfig | 9 --
include/configs/meesc.h | 199 ----------------------------
9 files changed, 548 deletions(-)
delete mode 100644 board/esd/meesc/Kconfig
delete mode 100644 board/esd/meesc/MAINTAINERS
delete mode 100644 board/esd/meesc/Makefile
delete mode 100644 board/esd/meesc/meesc.c
delete mode 100644 board/esd/meesc/partition.c
delete mode 100644 configs/meesc_dataflash_defconfig
delete mode 100644 configs/meesc_defconfig
delete mode 100644 include/configs/meesc.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index de06416..d2d60f3 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -99,10 +99,6 @@ config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
select CPU_ARM926EJS
-config TARGET_MEESC
- bool "Support meesc"
- select CPU_ARM926EJS
-
config TARGET_OTC570
bool "Support otc570"
select CPU_ARM926EJS
@@ -143,7 +139,6 @@ source "board/bluewater/snapper9260/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
-source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig
deleted file mode 100644
index 150348a..0000000
--- a/board/esd/meesc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MEESC
-
-config SYS_BOARD
- default "meesc"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "meesc"
-
-endif
diff --git a/board/esd/meesc/MAINTAINERS b/board/esd/meesc/MAINTAINERS
deleted file mode 100644
index 9403699..0000000
--- a/board/esd/meesc/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MEESC BOARD
-M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-S: Maintained
-F: board/esd/meesc/
-F: include/configs/meesc.h
-F: configs/meesc_defconfig
-F: configs/meesc_dataflash_defconfig
diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile
deleted file mode 100644
index 5d16738..0000000
--- a/board/esd/meesc/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += meesc.o
-obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
deleted file mode 100644
index c5994e0..0000000
--- a/board/esd/meesc/meesc.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-static int hw_rev = -1; /* hardware revision */
-
-int get_hw_rev(void)
-{
- if (hw_rev >= 0)
- return hw_rev;
-
- hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
-
- if (hw_rev == 15)
- hw_rev = 0;
-
- return hw_rev;
-}
-
-#ifdef CONFIG_CMD_NAND
-static void meesc_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa[0]);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
- &smc->cs[3].setup);
-
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
-
- writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(12),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif /* CONFIG_CMD_NAND */
-
-#ifdef CONFIG_MACB
-static void meesc_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
- at91_macb_hw_init();
-}
-#endif
-
-/*
- * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
- * controller debugging
- * The ET1100 is located at physical address 0x70000000
- * Its process memory is located at physical address 0x70001000
- */
-static void meesc_ethercat_hw_init(void)
-{
- at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
-
- /* Configure SMC EBI1_CS0 for EtherCAT */
- writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
- &smc1->cs[0].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
- AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
- &smc1->cs[0].pulse);
- writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
- &smc1->cs[0].cycle);
- /*
- * Configure behavior at external wait signal, byte-select mode, 16 bit
- * data bus width, none data float wait states and TDF optimization
- */
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
- AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
- AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
-
- /* Configure RDY/BSY */
- at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
- return rc;
-}
-
-int checkboard(void)
-{
- char str[32];
- u_char hw_type; /* hardware type */
-
- /* read the "Type" register of the ET1100 controller */
- hw_type = readb(CONFIG_ET1100_BASE);
-
- switch (hw_type) {
- case 0x11:
- case 0x3F:
- /* ET1100 present, arch number of MEESC-Board */
- gd->bd->bi_arch_number = MACH_TYPE_MEESC;
- puts("Board: CAN-EtherCAT Gateway");
- break;
- case 0xFF:
- /* no ET1100 present, arch number of EtherCAN/2-Board */
- gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
- puts("Board: EtherCAN/2 Gateway");
- /* switch on LED1D */
- at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
- break;
- default:
- /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
- gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
- printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
- puts("Board: EtherCAN/2 Gateway");
- break;
- }
- if (getenv_f("serial#", str, sizeof(str)) > 0) {
- puts(", serial# ");
- puts(str);
- }
- printf("\nHardware-revision: 1.%d\n", get_hw_rev());
- printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *str;
-
- char *serial = getenv("serial#");
- if (serial) {
- str = strchr(serial, '_');
- if (str && (strlen(str) >= 4)) {
- serialnr->high = (*(str + 1) << 8) | *(str + 2);
- serialnr->low = simple_strtoul(str + 3, NULL, 16);
- }
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
- return hw_rev | 0x100;
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- char *str;
- char buf[32];
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /*
- * Normally the processor clock has a divisor of 2.
- * In some cases this this needs to be set to 4.
- * Check the user has set environment mdiv to 4 to change the divisor.
- */
- if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
- writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
- AT91SAM9_PMC_MDIV_4, &pmc->mckr);
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
- serial_setbrg();
- /* Notify the user that the clock is not default */
- printf("Setting master clock to %s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
- }
-
- return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* enable all clocks */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* initialize ET1100 Controller */
- meesc_ethercat_hw_init();
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- meesc_nand_hw_init();
-#endif
-#ifdef CONFIG_HAS_DATAFLASH
- at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
- meesc_macb_hw_init();
-#endif
-#ifdef CONFIG_AT91_CAN
- at91_can_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
- at91_uhp_hw_init();
-#endif
- return 0;
-}
diff --git a/board/esd/meesc/partition.c b/board/esd/meesc/partition.c
deleted file mode 100644
index b6afafc..0000000
--- a/board/esd/meesc/partition.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
-};
-
-/* define the area offsets */
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
-};
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
deleted file mode 100644
index e4f7cce..0000000
--- a/configs/meesc_dataflash_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_MEESC=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
deleted file mode 100644
index 7d1fe7b..0000000
--- a/configs/meesc_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_MEESC=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
deleted file mode 100644
index e5bb873..0000000
--- a/include/configs/meesc.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * Configuation settings for the esd MEESC board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- * Since the linker has to swallow that define, we must use a pure
- * hex number here!
- */
-#define CONFIG_SYS_TEXT_BASE 0x20002000
-
-/*
- * since a number of boards are not being listed in linux
- * arch/arm/tools/mach-types any more, the mach-types have to be
- * defined here
- */
-#define MACH_TYPE_MEESC 2165
-#define MACH_TYPE_ETHERCAN2 2407
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
-
-/* Misc CPU related */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-
-#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-/*
- * Hardware drivers
- */
-
-/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-/* general purpose I/O */
-#define CONFIG_AT91_GPIO
-
-/* Console output */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-
-/* LED */
-#define CONFIG_AT91_LED
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000
-
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-
-/*
- * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-/* DataFlash */
-#ifdef CONFIG_SYS_USE_DATAFLASH
-# define CONFIG_ATMEL_DATAFLASH_SPI
-# define CONFIG_HAS_DATAFLASH
-# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
-# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
-# define AT91_SPI_CLK 15000000
-# define DATAFLASH_TCSS (0x1a << 16)
-# define DATAFLASH_TCHS (0x1 << 24)
-#endif
-
-/* NOR flash is not populated, disable it */
-#define CONFIG_SYS_NO_FLASH
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-# define CONFIG_NAND_ATMEL
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */
-# define CONFIG_SYS_NAND_DBW_8
-# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_FIT
-#define CONFIG_NET_RETRY_COUNT 20
-#undef CONFIG_RESET_PHY_R
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
-/* CAN */
-#define CONFIG_AT91_CAN
-
-/* hw-controller addresses */
-#define CONFIG_ET1100_BASE 0x70000000
-
-#ifdef CONFIG_SYS_USE_DATAFLASH
-
-/* bootstrap + u-boot + env in dataflash on CS0 */
-# define CONFIG_ENV_IS_IN_DATAFLASH
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- 0x8400)
-# define CONFIG_ENV_OFFSET 0x4200
-# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- CONFIG_ENV_OFFSET)
-# define CONFIG_ENV_SIZE 0x4200
-
-#elif CONFIG_SYS_USE_NANDFLASH
-
-/* bootstrap + u-boot + env + linux in nandflash */
-# define CONFIG_ENV_IS_IN_NAND 1
-# define CONFIG_ENV_OFFSET 0xC0000
-# define CONFIG_ENV_SIZE 0x20000
-
-#endif
-
-#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- 128*1024, 0x1000)
-
-#endif
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 18/45] arm: Remove mv88f6281gtw_ge board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (16 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,18/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards Simon Glass
` (27 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 4 -
board/Marvell/mv88f6281gtw_ge/Kconfig | 12 --
board/Marvell/mv88f6281gtw_ge/MAINTAINERS | 6 -
board/Marvell/mv88f6281gtw_ge/Makefile | 9 --
board/Marvell/mv88f6281gtw_ge/kwbimage.cfg | 149 ------------------------
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 119 -------------------
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h | 20 ----
configs/mv88f6281gtw_ge_defconfig | 7 --
include/configs/mv88f6281gtw_ge.h | 88 --------------
9 files changed, 414 deletions(-)
delete mode 100644 board/Marvell/mv88f6281gtw_ge/Kconfig
delete mode 100644 board/Marvell/mv88f6281gtw_ge/MAINTAINERS
delete mode 100644 board/Marvell/mv88f6281gtw_ge/Makefile
delete mode 100644 board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
delete mode 100644 board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
delete mode 100644 configs/mv88f6281gtw_ge_defconfig
delete mode 100644 include/configs/mv88f6281gtw_ge.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 1ac99b8..ae29a11 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -7,9 +7,6 @@ choice
config TARGET_OPENRD
bool "Marvell OpenRD Board"
-config TARGET_MV88F6281GTW_GE
- bool "MV88f6281GTW_GE Board"
-
config TARGET_RD6281A
bool "RD6281A Board"
@@ -58,7 +55,6 @@ config SYS_SOC
default "kirkwood"
source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig
deleted file mode 100644
index 00d7d1c..0000000
--- a/board/Marvell/mv88f6281gtw_ge/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MV88F6281GTW_GE
-
-config SYS_BOARD
- default "mv88f6281gtw_ge"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "mv88f6281gtw_ge"
-
-endif
diff --git a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS
deleted file mode 100644
index 9c26ca7..0000000
--- a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MV88F6281GTW_GE BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/mv88f6281gtw_ge/
-F: include/configs/mv88f6281gtw_ge.h
-F: configs/mv88f6281gtw_ge_defconfig
diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile
deleted file mode 100644
index e83bbf7..0000000
--- a/board/Marvell/mv88f6281gtw_ge/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mv88f6281gtw_ge.o
diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
deleted file mode 100644
index 9fa87ac..0000000
--- a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
+++ /dev/null
@@ -1,149 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000a00 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000000D # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000046 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
deleted file mode 100644
index ef08ad8..0000000
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "mv88f6281gtw_ge.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
- MV88F6281GTW_GE_OE_VAL_HIGH,
- MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_GPIO,
- MPP5_GPO,
- MPP6_SYSRST_OUTn,
- MPP7_SPI_SCn,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO,
- MPP13_GPIO,
- MPP14_GPIO,
- MPP15_GPIO,
- MPP16_GPIO,
- MPP17_GPIO,
- MPP18_GPO,
- MPP19_GPO,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_MV88E61XX_SWITCH
-void reset_phy(void)
-{
- /* configure and initialize switch */
- struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .mdip = MV88E61XX_MDIP_REVERSE,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = (1 << 5),
- .ports_enabled = 0x3f
- };
-
- mv88e61xx_switch_initialize(&swcfg);
-}
-#endif /* CONFIG_MV88E61XX_SWITCH */
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
deleted file mode 100644
index 447e227..0000000
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MV88F6281GTW_GE_H
-#define __MV88F6281GTW_GE_H
-
-#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \
- |(1 << 20) | (1 << 21))) /*enable GLED,RLED */
-#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \
- |(1 << 13)|(1 << 16)|(1 << 17)))
-#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */
-#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17))
-
-
-#endif /* __MV88F6281GTW_GE_H */
diff --git a/configs/mv88f6281gtw_ge_defconfig b/configs/mv88f6281gtw_ge_defconfig
deleted file mode 100644
index 8988734..0000000
--- a/configs/mv88f6281gtw_ge_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_MV88F6281GTW_GE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
deleted file mode 100644
index 45a4a75..0000000
--- a/include/configs/mv88f6281gtw_ge.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_MV88F6281GTW_GE_H
-#define _CONFIG_MV88F6281GTW_GE_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_USB
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Unwanted stuffs from mv-common.h */
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_UBI
-#undef CONFIG_CMD_UBIFS
-#undef CONFIG_RBTREE
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-#define CONFIG_ENV_SIZE 0x1000 /* 4k */
-#define CONFIG_ENV_ADDR 0x30000
-#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \
- "512k at 512k(psm),2m at 1m(kernel),13m at 3m(rootfs)\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
- "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
-#endif /* CONFIG_CMD_NET */
-
-#endif /* _CONFIG_MV88F6281GTW_GE_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (17 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 18/45] arm: Remove mv88f6281gtw_ge board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 20/45] arm: Remove nhk8815 boards and nomadik arch Simon Glass
` (26 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/genesi/mx51_efikamx/Kconfig | 15 -
board/genesi/mx51_efikamx/MAINTAINERS | 7 -
board/genesi/mx51_efikamx/Makefile | 13 -
board/genesi/mx51_efikamx/efikamx-usb.c | 230 --------------
board/genesi/mx51_efikamx/efikamx.c | 509 ------------------------------
board/genesi/mx51_efikamx/imximage_mx.cfg | 118 -------
board/genesi/mx51_efikamx/imximage_sb.cfg | 101 ------
configs/mx51_efikamx_defconfig | 7 -
configs/mx51_efikasb_defconfig | 6 -
include/configs/mx51_efikamx.h | 242 --------------
11 files changed, 1253 deletions(-)
delete mode 100644 board/genesi/mx51_efikamx/Kconfig
delete mode 100644 board/genesi/mx51_efikamx/MAINTAINERS
delete mode 100644 board/genesi/mx51_efikamx/Makefile
delete mode 100644 board/genesi/mx51_efikamx/efikamx-usb.c
delete mode 100644 board/genesi/mx51_efikamx/efikamx.c
delete mode 100644 board/genesi/mx51_efikamx/imximage_mx.cfg
delete mode 100644 board/genesi/mx51_efikamx/imximage_sb.cfg
delete mode 100644 configs/mx51_efikamx_defconfig
delete mode 100644 configs/mx51_efikasb_defconfig
delete mode 100644 include/configs/mx51_efikamx.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 62b28d9..9b367d2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -483,10 +483,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
-config TARGET_MX51_EFIKAMX
- bool "Support mx51_efikamx"
- select CPU_V7
-
config TARGET_VISION2
bool "Support vision2"
select CPU_V7
@@ -894,7 +890,6 @@ source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
-source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
diff --git a/board/genesi/mx51_efikamx/Kconfig b/board/genesi/mx51_efikamx/Kconfig
deleted file mode 100644
index 355702a..0000000
--- a/board/genesi/mx51_efikamx/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX51_EFIKAMX
-
-config SYS_BOARD
- default "mx51_efikamx"
-
-config SYS_VENDOR
- default "genesi"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "mx51_efikamx"
-
-endif
diff --git a/board/genesi/mx51_efikamx/MAINTAINERS b/board/genesi/mx51_efikamx/MAINTAINERS
deleted file mode 100644
index f1398c4..0000000
--- a/board/genesi/mx51_efikamx/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MX51_EFIKAMX BOARD
-#M: -
-S: Maintained
-F: board/genesi/mx51_efikamx/
-F: include/configs/mx51_efikamx.h
-F: configs/mx51_efikamx_defconfig
-F: configs/mx51_efikasb_defconfig
diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile
deleted file mode 100644
index 87f5f9e..0000000
--- a/board/genesi/mx51_efikamx/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
-#
-# BASED ON: imx51evk
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := efikamx.o efikamx-usb.o
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
deleted file mode 100644
index 9dfd249..0000000
--- a/board/genesi/mx51_efikamx/efikamx-usb.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <usb/ehci-fsl.h>
-#include <usb/ulpi.h>
-#include <errno.h>
-
-#include "../../../drivers/usb/host/ehci.h"
-
-/*
- * Configure the USB H1 and USB H2 IOMUX
- */
-void setup_iomux_usb(void)
-{
- static const iomux_v3_cfg_t usb_h1_pads[] = {
- MX51_PAD_USBH1_CLK__USBH1_CLK,
- MX51_PAD_USBH1_DIR__USBH1_DIR,
- MX51_PAD_USBH1_STP__USBH1_STP,
- MX51_PAD_USBH1_NXT__USBH1_NXT,
- MX51_PAD_USBH1_DATA0__USBH1_DATA0,
- MX51_PAD_USBH1_DATA1__USBH1_DATA1,
- MX51_PAD_USBH1_DATA2__USBH1_DATA2,
- MX51_PAD_USBH1_DATA3__USBH1_DATA3,
- MX51_PAD_USBH1_DATA4__USBH1_DATA4,
- MX51_PAD_USBH1_DATA5__USBH1_DATA5,
- MX51_PAD_USBH1_DATA6__USBH1_DATA6,
- MX51_PAD_USBH1_DATA7__USBH1_DATA7,
- };
-
- static const iomux_v3_cfg_t usb_pads[] = {
- MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
- MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
- NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
- NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
- NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
- };
-
- imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
-
- if (machine_is_efikasb()) {
- static const iomux_v3_cfg_t usb_h2_pads[] = {
- MX51_PAD_EIM_A24__USBH2_CLK,
- MX51_PAD_EIM_A25__USBH2_DIR,
- MX51_PAD_EIM_A26__USBH2_STP,
- MX51_PAD_EIM_A27__USBH2_NXT,
- MX51_PAD_EIM_D16__USBH2_DATA0,
- MX51_PAD_EIM_D17__USBH2_DATA1,
- MX51_PAD_EIM_D18__USBH2_DATA2,
- MX51_PAD_EIM_D19__USBH2_DATA3,
- MX51_PAD_EIM_D20__USBH2_DATA4,
- MX51_PAD_EIM_D21__USBH2_DATA5,
- MX51_PAD_EIM_D22__USBH2_DATA6,
- MX51_PAD_EIM_D23__USBH2_DATA7,
- };
-
- imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
- ARRAY_SIZE(usb_h2_pads));
- }
-
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-}
-
-/*
- * Enable devices connected to USB BUSes
- */
-static void efika_usb_enable_devices(void)
-{
- /* Enable Bluetooth */
- gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(2, 11), 1);
-
- /* Enable WiFi */
- gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
- udelay(10000);
-
- /* Reset the WiFi chip */
- gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(2, 10), 1);
-}
-
-/*
- * Reset USB HUB (or HUBs on EfikaSB)
- */
-static void efika_usb_hub_reset(void)
-{
- /* HUB reset */
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(1, 5), 0);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(1, 5), 1);
-}
-
-/*
- * Reset USB PHY (or PHYs on EfikaSB)
- */
-static void efika_usb_phy_reset(void)
-{
- /* SMSC 3317 PHY reset */
- gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(2, 9), 1);
-}
-
-static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
- iomux_v3_cfg_t stp_pad_gpio,
- iomux_v3_cfg_t stp_pad_usb)
-{
- int ret;
- struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
- struct ulpi_viewport ulpi_vp;
-
- imx_iomux_v3_setup_pad(stp_pad_gpio);
- gpio_direction_output(stp_gpio, 0);
- udelay(1000);
- gpio_set_value(stp_gpio, 1);
- udelay(1000);
-
- imx_iomux_v3_setup_pad(stp_pad_usb);
- udelay(10000);
-
- ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
- ulpi_vp.port_num = 0;
-
- ret = ulpi_init(&ulpi_vp);
- if (ret) {
- printf("Efika USB ULPI initialization failed\n");
- return;
- }
-
- /* ULPI set flags */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
- ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
- ULPI_OTG_EXTVBUSIND);
- ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
- ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
- ULPI_FC_SUSPENDM);
- ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
-
- /* Set VBus */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- /*
- * Set VBusChrg
- *
- * NOTE: This violates USB specification, but otherwise, USB on Efika
- * doesn't work.
- */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
-}
-
-int board_ehci_hcd_init(int port)
-{
- /* Init iMX51 EHCI */
- efika_usb_phy_reset();
- efika_usb_hub_reset();
- efika_usb_enable_devices();
-
- return 0;
-}
-
-/* This overrides a weak function */
-void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
- uint32_t *reg)
-{
- uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT);
- struct usb_ehci *ehci = (struct usb_ehci *)port;
- struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
- struct ulpi_viewport ulpi_vp;
-
- ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
- ulpi_vp.port_num = 0;
-
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
-
- mdelay(50);
-
- /* terminate the reset */
- *reg = ehci_readl(status_reg);
- *reg |= EHCI_PS_PE;
-}
-
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
-{
- uint32_t tmp;
-
- if (port == 0) {
- /* Adjust UTMI PHY frequency to 24MHz */
- tmp = readl(OTG_BASE_ADDR + 0x80c);
- tmp = (tmp & ~0x3) | 0x01;
- writel(tmp, OTG_BASE_ADDR + 0x80c);
- } else if (port == 1) {
- efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
- MX51_PAD_USBH1_STP__GPIO1_27,
- MX51_PAD_USBH1_STP__USBH1_STP);
- } else if ((port == 2) && machine_is_efikasb()) {
- efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
- MX51_PAD_EIM_A26__GPIO2_20,
- MX51_PAD_EIM_A26__USBH2_STP);
- }
-
- if (port)
- mdelay(10);
-}
-
-/*
- * Ethernet on the Smarttop is on the USB bus. Rather than give an error about
- * "CPU Net Initialization Failed", just pass this test since no other settings
- * are required. Smartbook doesn't have built-in Ethernet but we will let it
- * pass anyway considering someone may have plugged in a USB stick and all
- * they need to do is run "usb start".
- */
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
deleted file mode 100644
index 6ba55cd..0000000
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <asm/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/imx-common/spi.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Compile-time error checking
- */
-#ifndef CONFIG_MXC_SPI
-#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
-#endif
-
-/*
- * Board revisions
- *
- * Note that we get these revisions here for convenience, but we only set
- * up for the production model Smarttop (1.3) and Smartbook (2.0).
- *
- */
-#define EFIKAMX_BOARD_REV_11 0x1
-#define EFIKAMX_BOARD_REV_12 0x2
-#define EFIKAMX_BOARD_REV_13 0x3
-#define EFIKAMX_BOARD_REV_14 0x4
-
-#define EFIKASB_BOARD_REV_13 0x1
-#define EFIKASB_BOARD_REV_20 0x2
-
-/*
- * Board identification
- */
-static u32 get_mx_rev(void)
-{
- u32 rev = 0;
- /*
- * Retrieve board ID:
- *
- * gpio: 16 17 11
- * ==============
- * r1.1: 1+ 1 1
- * r1.2: 1 1 0
- * r1.3: 1 0 1
- * r1.4: 1 0 0
- *
- * + note: r1.1 does not strap this pin properly so it needs to
- * be hacked or ignored.
- */
-
- /* set to 1 in order to get correct value on board rev 1.1 */
- gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
- gpio_direction_input(IMX_GPIO_NR(3, 11));
- gpio_direction_input(IMX_GPIO_NR(3, 16));
- gpio_direction_input(IMX_GPIO_NR(3, 17));
-
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
-
- return (~rev & 0x7) + 1;
-}
-
-static iomux_v3_cfg_t const efikasb_revision_pads[] = {
- MX51_PAD_EIM_CS3__GPIO2_28,
- MX51_PAD_EIM_CS4__GPIO2_29,
-};
-
-static inline u32 get_sb_rev(void)
-{
- u32 rev = 0;
-
- imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
- ARRAY_SIZE(efikasb_revision_pads));
- gpio_direction_input(IMX_GPIO_NR(2, 28));
- gpio_direction_input(IMX_GPIO_NR(2, 29));
-
- rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
-
- return rev;
-}
-
-inline uint32_t get_efikamx_rev(void)
-{
- if (machine_is_efikamx())
- return get_mx_rev();
- else if (machine_is_efikasb())
- return get_sb_rev();
-}
-
-u32 get_board_rev(void)
-{
- return get_cpu_rev() | (get_efikamx_rev() << 8);
-}
-
-/*
- * DRAM initialization
- */
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-/*
- * UART configuration
- */
-static iomux_v3_cfg_t const efikamx_uart_pads[] = {
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- MX51_PAD_UART1_RTS__UART1_RTS,
- MX51_PAD_UART1_CTS__UART1_CTS,
-};
-
-/*
- * SPI configuration
- */
-static iomux_v3_cfg_t const efikamx_spi_pads[] = {
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_SS0__GPIO4_24,
- MX51_PAD_CSPI1_SS1__GPIO4_25,
- MX51_PAD_GPIO1_6__GPIO1_6,
-};
-
-#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
-#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
-
-/*
- * PMIC configuration
- */
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 1) ? 121 : -1;
-}
-
-static void power_init(void)
-{
- unsigned int val;
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(CONFIG_FSL_PMIC_BUS);
- if (ret)
- return;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return;
-
- /* Write needed to Power Gate 2 register */
- pmic_reg_read(p, REG_POWER_MISC, &val);
- val &= ~PWGT2SPIEN;
- pmic_reg_write(p, REG_POWER_MISC, val);
-
- /* Externally powered */
- pmic_reg_read(p, REG_CHARGE, &val);
- val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
- pmic_reg_write(p, REG_CHARGE, val);
-
- /* power up the system first */
- pmic_reg_write(p, REG_POWER_MISC, PWUP);
-
- /* Set core voltage to 1.1V */
- pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
- pmic_reg_write(p, REG_SW_0, val);
-
- /* Setup VCC (SW2) to 1.25 */
- pmic_reg_read(p, REG_SW_1, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_1, val);
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- pmic_reg_read(p, REG_SW_2, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_2, val);
- udelay(50);
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, &mxc_ccm->cacrr);
-
- /* Set switchers in Auto in NORMAL mode & STANDBY mode */
- /* Setup the switcher mode for SW1 & SW2*/
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
- (SWMODE_MASK << SWMODE4_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
- /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
- val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- pmic_reg_read(p, REG_SETTING_1, &val);
- val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
- val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
- pmic_reg_write(p, REG_SETTING_1, val);
-
- /* Enable VGEN1, VGEN2, VDIG, VPLL */
- pmic_reg_read(p, REG_MODE_0, &val);
- val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
- pmic_reg_write(p, REG_MODE_0, val);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(p, REG_MODE_1, val);
- udelay(200);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
- VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- pmic_reg_read(p, REG_POWER_CTL2, &val);
- val |= WDIRESET;
- pmic_reg_write(p, REG_POWER_CTL2, val);
-
- udelay(2500);
-}
-#else
-static inline void power_init(void) { }
-#endif
-
-/*
- * MMC configuration
- */
-#ifdef CONFIG_FSL_ESDHC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC2_BASE_ADDR},
-};
-
-static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- MX51_PAD_GPIO1_1__SD1_WP,
-};
-
-#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
-
-static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
- MX51_PAD_GPIO1_0__SD1_CD,
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
-};
-
-#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
-#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
-
-static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
- MX51_PAD_SD2_CMD__SD2_CMD,
- MX51_PAD_SD2_CLK__SD2_CLK,
- MX51_PAD_SD2_DATA0__SD2_DATA0,
- MX51_PAD_SD2_DATA1__SD2_DATA1,
- MX51_PAD_SD2_DATA2__SD2_DATA2,
- MX51_PAD_SD2_DATA3__SD2_DATA3,
- MX51_PAD_GPIO1_7__SD2_WP,
- MX51_PAD_GPIO1_8__SD2_CD,
-};
-
-#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
-#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
-
-static inline uint32_t efikamx_mmc_getcd(u32 base)
-{
- if (base == MMC_SDHC1_BASE_ADDR)
- if (machine_is_efikamx())
- return EFIKAMX_SDHC1_CD;
- else
- return EFIKASB_SDHC1_CD;
- else
- return EFIKASB_SDHC2_CD;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
- int ret = !gpio_get_value(cd);
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /*
- * All Efika MX boards use eSDHC1 with a common write-protect GPIO
- */
- imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
- ARRAY_SIZE(efikamx_sdhc1_pads));
- gpio_direction_input(EFIKAMX_SDHC1_WP);
-
- /*
- * Smartbook and Smarttop differ on the location of eSDHC1
- * carrier-detect GPIO
- */
- if (machine_is_efikamx()) {
- imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
- gpio_direction_input(EFIKAMX_SDHC1_CD);
- } else if (machine_is_efikasb()) {
- imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
- gpio_direction_input(EFIKASB_SDHC1_CD);
- }
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-
- if (machine_is_efikasb()) {
-
- imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
- ARRAY_SIZE(efikasb_sdhc2_pads));
- gpio_direction_input(EFIKASB_SDHC2_CD);
- gpio_direction_input(EFIKASB_SDHC2_WP);
- if (!ret)
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
- }
-
- return ret;
-}
-#endif
-
-/*
- * PATA
- */
-static iomux_v3_cfg_t const efikamx_pata_pads[] = {
- MX51_PAD_NANDF_WE_B__PATA_DIOW,
- MX51_PAD_NANDF_RE_B__PATA_DIOR,
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
- MX51_PAD_NANDF_CLE__PATA_RESET_B,
- MX51_PAD_NANDF_WP_B__PATA_DMACK,
- MX51_PAD_NANDF_RB0__PATA_DMARQ,
- MX51_PAD_NANDF_RB1__PATA_IORDY,
- MX51_PAD_GPIO_NAND__PATA_INTRQ,
- MX51_PAD_NANDF_CS2__PATA_CS_0,
- MX51_PAD_NANDF_CS3__PATA_CS_1,
- MX51_PAD_NANDF_CS4__PATA_DA_0,
- MX51_PAD_NANDF_CS5__PATA_DA_1,
- MX51_PAD_NANDF_CS6__PATA_DA_2,
- MX51_PAD_NANDF_D15__PATA_DATA15,
- MX51_PAD_NANDF_D14__PATA_DATA14,
- MX51_PAD_NANDF_D13__PATA_DATA13,
- MX51_PAD_NANDF_D12__PATA_DATA12,
- MX51_PAD_NANDF_D11__PATA_DATA11,
- MX51_PAD_NANDF_D10__PATA_DATA10,
- MX51_PAD_NANDF_D9__PATA_DATA9,
- MX51_PAD_NANDF_D8__PATA_DATA8,
- MX51_PAD_NANDF_D7__PATA_DATA7,
- MX51_PAD_NANDF_D6__PATA_DATA6,
- MX51_PAD_NANDF_D5__PATA_DATA5,
- MX51_PAD_NANDF_D4__PATA_DATA4,
- MX51_PAD_NANDF_D3__PATA_DATA3,
- MX51_PAD_NANDF_D2__PATA_DATA2,
- MX51_PAD_NANDF_D1__PATA_DATA1,
- MX51_PAD_NANDF_D0__PATA_DATA0,
-};
-
-/*
- * EHCI USB
- */
-#ifdef CONFIG_CMD_USB
-extern void setup_iomux_usb(void);
-#else
-static inline void setup_iomux_usb(void) { }
-#endif
-
-/*
- * LED configuration
- *
- * Smarttop LED pad config is done in the DCD
- *
- */
-#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
-#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
-#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
-
-static iomux_v3_cfg_t const efikasb_led_pads[] = {
- MX51_PAD_GPIO1_3__GPIO1_3,
- MX51_PAD_EIM_CS0__GPIO2_25,
-};
-
-#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
-#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
-
-/*
- * Board initialization
- */
-int board_early_init_f(void)
-{
- if (machine_is_efikasb()) {
- imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
- ARRAY_SIZE(efikasb_led_pads));
- gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
- gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
- } else if (machine_is_efikamx()) {
- /*
- * Set up GPIO directions for LEDs.
- * IOMUX has been done in the DCD already.
- * Turn the red LED on for pre-relocation code.
- */
- gpio_direction_output(EFIKAMX_LED_BLUE, 0);
- gpio_direction_output(EFIKAMX_LED_GREEN, 0);
- gpio_direction_output(EFIKAMX_LED_RED, 1);
- }
-
- /*
- * Both these pad configurations for UART and SPI are kind of redundant
- * since they are the Power-On Defaults for the i.MX51. But, it seems we
- * should make absolutely sure that they are set up correctly.
- */
- imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
- ARRAY_SIZE(efikamx_uart_pads));
- imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
- ARRAY_SIZE(efikamx_spi_pads));
-
- /* not technically required for U-Boot operation but do it anyway. */
- gpio_direction_input(EFIKAMX_PMIC_IRQ);
- /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
- gpio_direction_output(EFIKAMX_SPI_SS0, 0);
- gpio_direction_output(EFIKAMX_SPI_SS1, 1);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- if (machine_is_efikamx()) {
- /*
- * Set up Blue LED for "In U-Boot" status.
- * We're all relocated and ready to U-Boot!
- */
- gpio_set_value(EFIKAMX_LED_RED, 0);
- gpio_set_value(EFIKAMX_LED_GREEN, 0);
- gpio_set_value(EFIKAMX_LED_BLUE, 1);
- }
-
- power_init();
-
- imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
- ARRAY_SIZE(efikamx_pata_pads));
- setup_iomux_usb();
-
- return 0;
-}
-
-int checkboard(void)
-{
- u32 rev = get_efikamx_rev();
-
- printf("Board: Genesi Efika MX ");
- if (machine_is_efikamx())
- printf("Smarttop (1.%i)\n", rev & 0xf);
- else if (machine_is_efikasb())
- printf("Smartbook\n");
-
- return 0;
-}
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
deleted file mode 100644
index e2911eb..0000000
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2009 Pegatron Corporation
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * BASED ON: imx51evk
- *
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/*
- * Essential GPIO settings to be done as early as possible
- * PCBIDn pad settings are all the defaults except #2 which needs HVE off
- */
-DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
-DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
-DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
-DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
-DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
-DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
-DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-
-/* DDR bus IOMUX PAD settings */
-DATA 4 0x73fa850c 0x20c5 # SDODT1
-DATA 4 0x73fa8510 0x20c5 # SDODT0
-DATA 4 0x73fa84ac 0xc5 # SDWE
-DATA 4 0x73fa84b0 0xc5 # SDCKE0
-DATA 4 0x73fa84b4 0xc5 # SDCKE1
-DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
-DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
-DATA 4 0x73fa882c 0x2 # DRAM_B4
-DATA 4 0x73fa88a4 0x2 # DRAM_B0
-DATA 4 0x73fa88ac 0x2 # DRAM_B1
-DATA 4 0x73fa88b8 0x2 # DRAM_B2
-DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
-DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
-DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
-DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-
-/*
- * Setting DDR for micron
- * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
- * CAS=3 BL=4
- */
-/* ESDCTL_ESDCTL0 */
-DATA 4 0x83fd9000 0x82a20000
-/* ESDCTL_ESDCTL1 */
-DATA 4 0x83fd9008 0x82a20000
-/* ESDCTL_ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCFG0 */
-DATA 4 0x83fd9004 0x3f3574aa
-/* ESDCTL_ESDCFG1 */
-DATA 4 0x83fd900c 0x3f3574aa
-
-/* Init DRAM on CS0 */
-/* ESDCTL_ESDSCR */
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x0000801a
-DATA 4 0x83fd9014 0x0000801b
-DATA 4 0x83fd9014 0x00448019
-DATA 4 0x83fd9014 0x07328018
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x06328018
-DATA 4 0x83fd9014 0x03808019
-DATA 4 0x83fd9014 0x00408019
-DATA 4 0x83fd9014 0x00008000
-
-/* Init DRAM on CS1 */
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x0000801e
-DATA 4 0x83fd9014 0x0000801f
-DATA 4 0x83fd9014 0x0000801d
-DATA 4 0x83fd9014 0x0732801c
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x0632801c
-DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0040801d
-DATA 4 0x83fd9014 0x00008004
-
-/* Write to CTL0 */
-DATA 4 0x83fd9000 0xb2a20000
-/* Write to CTL1 */
-DATA 4 0x83fd9008 0xb2a20000
-/* ESDMISC */
-DATA 4 0x83fd9010 0x000ad6d0
-/* ESDCTL_ESDCDLYGD */
-DATA 4 0x83fd9034 0x90000000
-DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
deleted file mode 100644
index a67d41b..0000000
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2009 Pegatron Corporation
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * BASED ON: imx51evk
- *
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
-*/
-/* DDR bus IOMUX PAD settings */
-DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
-DATA 4 0x73fa850c 0x20c5 # SDODT1
-DATA 4 0x73fa8510 0x20c5 # SDODT0
-DATA 4 0x73fa8848 0x4 # DDR_A1
-DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
-DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
-DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
-DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
-DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
-DATA 4 0x73fa8820 0x0 # DDRPKS
-DATA 4 0x73fa84ac 0xe5 # SDWE
-DATA 4 0x73fa84b0 0xe5 # SDCKE0
-DATA 4 0x73fa84b4 0xe5 # SDCKE1
-DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
-DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
-
-/*
- * Setting DDR for micron
- * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
- * CAS=3 BL=4
- */
-/* ESDCTL_ESDCTL0 */
-DATA 4 0x83fd9000 0x82a20000
-/* ESDCTL_ESDCTL1 */
-DATA 4 0x83fd9008 0x82a20000
-/* ESDCTL_ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCFG0 */
-DATA 4 0x83fd9004 0x333574aa
-/* ESDCTL_ESDCFG1 */
-DATA 4 0x83fd900c 0x333574aa
-
-/* Init DRAM on CS0 */
-/* ESDCTL_ESDSCR */
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x0000801a
-DATA 4 0x83fd9014 0x0000801b
-DATA 4 0x83fd9014 0x00448019
-DATA 4 0x83fd9014 0x07328018
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x06328018
-DATA 4 0x83fd9014 0x03808019
-DATA 4 0x83fd9014 0x00408019
-DATA 4 0x83fd9014 0x00008000
-
-/* Init DRAM on CS1 */
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x0000801e
-DATA 4 0x83fd9014 0x0000801f
-DATA 4 0x83fd9014 0x0000801d
-DATA 4 0x83fd9014 0x0732801c
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x0632801c
-DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0042801d
-DATA 4 0x83fd9014 0x00008004
-
-/* Write to CTL0 */
-DATA 4 0x83fd9000 0xb2a20000
-/* Write to CTL1 */
-DATA 4 0x83fd9008 0xb2a20000
-/* ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCDLYGD */
-DATA 4 0x83fd9034 0x90000000
-DATA 4 0x83fd9014 0x00000000
diff --git a/configs/mx51_efikamx_defconfig b/configs/mx51_efikamx_defconfig
deleted file mode 100644
index a88c223..0000000
--- a/configs/mx51_efikamx_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MX51_EFIKAMX=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="Efika> "
diff --git a/configs/mx51_efikasb_defconfig b/configs/mx51_efikasb_defconfig
deleted file mode 100644
index 1bc7c00..0000000
--- a/configs/mx51_efikasb_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MX51_EFIKAMX=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
deleted file mode 100644
index 373cfcb..0000000
--- a/include/configs/mx51_efikamx.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX51EVK Board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-/* An i.MX51 CPU */
-#define CONFIG_MX51
-
-#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX)
-#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB)
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0x97800000
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DATE
-
-/*
- * Environmental settings
- */
-
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
-#define CONFIG_ENV_SIZE (4 * 1024)
-
-/*
- * ATAG setup
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_MXC_GPIO
-
-/*
- * SPI Interface
- */
-#ifdef CONFIG_CMD_SPI
-
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-
-/* SPI FLASH */
-#ifdef CONFIG_CMD_SF
-
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS 1
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
-#define CONFIG_FSL_ENV_IN_SF
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SYS_NO_FLASH
-
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-/* SPI PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 0
-#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
-#define CONFIG_FSL_PMIC_CLK 25000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-#endif
-
-/*
- * MMC Configs
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#endif
-
-/*
- * ATA/IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define CONFIG_MX51_PATA
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0
-#define CONFIG_SYS_ATA_REG_OFFSET 0xa0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8
-
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MXC_ATA_PIO_MODE 4
-#endif
-
-/*
- * USB
- */
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MX5
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_MXC_USB_PORT 1
-#if (CONFIG_MXC_USB_PORT == 0)
-#define CONFIG_MXC_USB_PORTSC (1 << 28)
-#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY
-#else
-#define CONFIG_MXC_USB_PORTSC (2 << 30)
-#define CONFIG_MXC_USB_FLAGS 0
-#endif
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
-#define CONFIG_PREBOOT
-/* USB NET */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#endif
-#endif /* CONFIG_CMD_USB */
-
-/*
- * Filesystems
- */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_LOADADDR 0x90800000
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x90010000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
-#define CONFIG_SYS_MAIN_PWR_ON
-
-#endif
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 20/45] arm: Remove nhk8815 boards and nomadik arch
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (18 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board Simon Glass
` (25 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 -
arch/arm/mach-nomadik/Kconfig | 17 ---
arch/arm/mach-nomadik/Makefile | 9 --
arch/arm/mach-nomadik/gpio.c | 83 ------------
arch/arm/mach-nomadik/include/mach/gpio.h | 26 ----
arch/arm/mach-nomadik/include/mach/mtu.h | 50 --------
arch/arm/mach-nomadik/reset.S | 14 --
arch/arm/mach-nomadik/timer.c | 71 ----------
board/st/nhk8815/Kconfig | 12 --
board/st/nhk8815/MAINTAINERS | 8 --
board/st/nhk8815/Makefile | 12 --
board/st/nhk8815/README.nhk8815 | 32 -----
board/st/nhk8815/nhk8815.c | 92 -------------
configs/nhk8815_defconfig | 7 -
configs/nhk8815_onenand_defconfig | 7 -
drivers/mtd/nand/Makefile | 1 -
drivers/mtd/nand/nomadik.c | 206 ------------------------------
include/configs/nhk8815.h | 170 ------------------------
include/nomadik.h | 40 ------
19 files changed, 863 deletions(-)
delete mode 100644 arch/arm/mach-nomadik/Kconfig
delete mode 100644 arch/arm/mach-nomadik/Makefile
delete mode 100644 arch/arm/mach-nomadik/gpio.c
delete mode 100644 arch/arm/mach-nomadik/include/mach/gpio.h
delete mode 100644 arch/arm/mach-nomadik/include/mach/mtu.h
delete mode 100644 arch/arm/mach-nomadik/reset.S
delete mode 100644 arch/arm/mach-nomadik/timer.c
delete mode 100644 board/st/nhk8815/Kconfig
delete mode 100644 board/st/nhk8815/MAINTAINERS
delete mode 100644 board/st/nhk8815/Makefile
delete mode 100644 board/st/nhk8815/README.nhk8815
delete mode 100644 board/st/nhk8815/nhk8815.c
delete mode 100644 configs/nhk8815_defconfig
delete mode 100644 configs/nhk8815_onenand_defconfig
delete mode 100644 drivers/mtd/nand/nomadik.c
delete mode 100644 include/configs/nhk8815.h
delete mode 100644 include/nomadik.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9b367d2..6d1da69 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -187,10 +187,6 @@ config TARGET_SC_SPS_1
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_NOMADIK
- bool "ST-Ericsson Nomadik"
- select CPU_ARM926EJS
-
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
@@ -805,8 +801,6 @@ source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/mach-nomadik/Kconfig"
-
source "arch/arm/cpu/armv7/omap3/Kconfig"
source "arch/arm/cpu/armv7/omap4/Kconfig"
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
deleted file mode 100644
index ba72a41..0000000
--- a/arch/arm/mach-nomadik/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if ARCH_NOMADIK
-
-choice
- prompt "Nomadik board select"
- optional
-
-config NOMADIK_NHK8815
- bool "ST 8815 Nomadik Hardware Kit"
-
-endchoice
-
-config SYS_SOC
- default "nomadik"
-
-source "board/st/nhk8815/Kconfig"
-
-endif
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
deleted file mode 100644
index cdf1345..0000000
--- a/arch/arm/mach-nomadik/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o gpio.o
-obj-y += reset.o
diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c
deleted file mode 100644
index eff5b2b..0000000
--- a/arch/arm/mach-nomadik/gpio.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
- NOMADIK_GPIO0_BASE,
- NOMADIK_GPIO1_BASE,
- NOMADIK_GPIO2_BASE,
- NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
- GPIO_DAT = 0x00, /* data register */
- GPIO_DATS = 0x04, /* data set */
- GPIO_DATC = 0x08, /* data clear */
- GPIO_PDIS = 0x0c, /* pull disable */
- GPIO_DIR = 0x10, /* direction */
- GPIO_DIRS = 0x14, /* direction set */
- GPIO_DIRC = 0x18, /* direction clear */
- GPIO_AFSLA = 0x20, /* alternate function select A */
- GPIO_AFSLB = 0x24, /* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
- return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
- return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
- u32 afunc, bfunc;
-
- /* alternate function is 0..3, with one bit per register */
- afunc = readl(base + GPIO_AFSLA) & ~bit;
- bfunc = readl(base + GPIO_AFSLB) & ~bit;
- if (alternate_function & 1) afunc |= bit;
- if (alternate_function & 2) bfunc |= bit;
- writel(afunc, base + GPIO_AFSLA);
- writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (dir)
- writel(bit, base + GPIO_DIRS);
- else
- writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (val)
- writel(bit, base + GPIO_DATS);
- else
- writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- return readl(base + GPIO_DAT) & bit;
-}
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
deleted file mode 100644
index 311758a..0000000
--- a/arch/arm/mach-nomadik/include/mach/gpio.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __NMK_GPIO_H__
-#define __NMK_GPIO_H__
-
-/*
- * These functions are called from the soft-i2c driver, but
- * are also used by board files to set output bits.
- */
-
-enum nmk_af { /* alternate function settings */
- GPIO_GPIO = 0,
- GPIO_ALT_A,
- GPIO_ALT_B,
- GPIO_ALT_C
-};
-
-extern void nmk_gpio_af(int gpio, int alternate_function);
-extern void nmk_gpio_dir(int gpio, int dir);
-extern void nmk_gpio_set(int gpio, int val);
-extern int nmk_gpio_get(int gpio);
-
-#endif /* __NMK_GPIO_H__ */
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
deleted file mode 100644
index f89f242..0000000
--- a/arch/arm/mach-nomadik/include/mach/mtu.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/mach-nomadik/reset.S b/arch/arm/mach-nomadik/reset.S
deleted file mode 100644
index ec95472..0000000
--- a/arch/arm/mach-nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
- ldr r1, =0x1
- str r1, [r0, #0x18]
-
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
deleted file mode 100644
index 775d0b7..0000000
--- a/arch/arm/mach-nomadik/timer.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK (24 * 100 * 1000)
-#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
-#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
- ulong val;
-
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
-
- /* Reset the timer */
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
- /*
- * The load-register isn't really immediate: it changes on clock
- * edges, so we must wait for our newly-written value to appear.
- * Since we might miss reading 0, wait for any change in value.
- */
- val = READ_TIMER();
- while (READ_TIMER() == val)
- ;
-
- return 0;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
- return TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
- ulong ini, end;
-
- ini = READ_TIMER();
- end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
- ;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/board/st/nhk8815/Kconfig b/board/st/nhk8815/Kconfig
deleted file mode 100644
index 94547dc..0000000
--- a/board/st/nhk8815/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if NOMADIK_NHK8815
-
-config SYS_BOARD
- default "nhk8815"
-
-config SYS_VENDOR
- default "st"
-
-config SYS_CONFIG_NAME
- default "nhk8815"
-
-endif
diff --git a/board/st/nhk8815/MAINTAINERS b/board/st/nhk8815/MAINTAINERS
deleted file mode 100644
index 72c3a8d..0000000
--- a/board/st/nhk8815/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-NHK8815 BOARD
-M: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
-M: Alessandro Rubini <rubini@unipv.it>
-S: Maintained
-F: board/st/nhk8815/
-F: include/configs/nhk8815.h
-F: configs/nhk8815_defconfig
-F: configs/nhk8815_onenand_defconfig
diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile
deleted file mode 100644
index dd56944..0000000
--- a/board/st/nhk8815/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2004
-# ARM Ltd.
-# Philippe Robin, <philippe.robin@arm.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := nhk8815.o
diff --git a/board/st/nhk8815/README.nhk8815 b/board/st/nhk8815/README.nhk8815
deleted file mode 100644
index 9008e39..0000000
--- a/board/st/nhk8815/README.nhk8815
+++ /dev/null
@@ -1,32 +0,0 @@
-
-The Nomadik 8815 CPU has a "secure" boot mode where no external access
-(not even JTAG) is allowed. The "remap" bits in the evaluation board
-are configured in order to boot from the internal ROM memory (in
-secure mode).
-
-The boot process as defined by the manufacturer executes external code
-(loaded from NAND or OneNAND) that that disables such "security" in
-order to run u-boot and later the kernel without constraints. Such
-code is a proprietary initial boot loader, called "X-Loader" (in case
-anyone wonders, it has no relations with other loaders with the same
-name and there is no GPL code inside the ST X-Loader).
-
-SDRAM configuration, PLL setup and initial loading from NAND is
-implemented in the X-Loader, so U-Boot is already running in SDRAM
-when control is handed over to it.
-
-The Makefile offers two different configurations to be used if you
-boot from Nand or OneNand.
-
- make nhk8815_config
- make nhk8815_onenand_config
-
-Both support OneNand and Nand. Since U-Boot, running in RAM, can't know
-where it was loaded from, the configurations differ in where the filesystem
-is looked for by default.
-
-
-On www.st.com/nomadik and on www.stnwireless.com there are documents,
-summary data and white papers on Nomadik. The full datasheet for
-STn8815 is not currently available on line but under specific request
-to the local ST sales offices.
diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c
deleted file mode 100644
index 94d0f76..0000000
--- a/board/st/nhk8815/nhk8815.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2005
- * STMicrolelctronics, <www.st.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress(int progress)
-{
- printf("%i\n", progress);
-}
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
- gd->bd->bi_boot_params = 0x00000100;
- writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
- writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
- writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
- writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
-
- /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
- writel(0x0000305b, REG_FSMC_BCR1);
- writel(0x00033f33, REG_FSMC_BTR1);
-
- /* Set up SMCS0 for OneNand: sram-like once again */
- writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
- writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
-
- icache_enable();
- return 0;
-}
-
-int board_late_init(void)
-{
- /* Set the two I2C gpio lines to be gpio high */
- nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
- nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
- nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
-
- /* Reset the I2C port expander, on GPIO77 */
- nmk_gpio_af(77, GPIO_GPIO);
- nmk_gpio_dir(77, 1);
- nmk_gpio_set(77, 0);
- udelay(10);
- nmk_gpio_set(77, 1);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/configs/nhk8815_defconfig b/configs/nhk8815_defconfig
deleted file mode 100644
index 218d92a..0000000
--- a/configs/nhk8815_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_NOMADIK=y
-CONFIG_NOMADIK_NHK8815=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="Nomadik> "
diff --git a/configs/nhk8815_onenand_defconfig b/configs/nhk8815_onenand_defconfig
deleted file mode 100644
index c01559d..0000000
--- a/configs/nhk8815_onenand_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_NOMADIK=y
-CONFIG_NOMADIK_NHK8815=y
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 64d1675..16a051b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_NDFC) += ndfc.o
-obj-$(CONFIG_NAND_NOMADIK) += nomadik.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c
deleted file mode 100644
index a7cee51..0000000
--- a/drivers/mtd/nand/nomadik.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * (C) Copyright 2007 STMicroelectronics, <www.st.com>
- * (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-
-static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */
-{
- __asm__ __volatile__(
- "eor %0, %0, %0, lsr #4\n\t"
- "eor %0, %0, %0, lsr #2\n\t"
- "eor %0, %0, %0, lsr #1\n\t"
- "ands %0, %0, #1\n\t"
- "subne %0, %0, #2\t"
- : "=r" (b) : "0" (b));
- return b;
-}
-
-/*
- * This is the ECC routine used in hardware, according to the manual.
- * HW claims to make the calculation but not the correction; so we must
- * recalculate the bytes for a comparison.
- */
-static int ecc512(const unsigned char *data, unsigned char *ecc)
-{
- int gpar = 0;
- int i, val, par;
- int pbits = 0; /* P8, P16, ... P2048 */
- int pprime = 0; /* P8', P16', ... P2048' */
- int lowbits; /* P1, P2, P4 and primes */
-
- for (i = 0; i < 512; i++) {
- par = parity((val = data[i]));
- gpar ^= val;
- pbits ^= (i & par);
- }
- /*
- * Ok, now gpar is global parity (xor of all bytes)
- * pbits are all the parity bits (non-prime ones)
- */
- par = parity(gpar);
- pprime = pbits ^ par;
- /* Put low bits in the right position for ecc[2] (bits 7..2) */
- lowbits = 0
- | (parity(gpar & 0xf0) & 0x80) /* P4 */
- | (parity(gpar & 0x0f) & 0x40) /* P4' */
- | (parity(gpar & 0xcc) & 0x20) /* P2 */
- | (parity(gpar & 0x33) & 0x10) /* P2' */
- | (parity(gpar & 0xaa) & 0x08) /* P1 */
- | (parity(gpar & 0x55) & 0x04); /* P1' */
-
- ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8));
- /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */
- ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1)
- | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2)
- | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3)
- | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4));
-
- ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3)
- | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2)
- | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1)
- | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0));
- return 0;
-}
-
-/* This is the method in the chip->ecc field */
-static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc_code)
-{
- return ecc512(dat, ecc_code);
-}
-
-static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
- uint8_t *r_ecc, uint8_t *c_ecc)
-{
- struct nand_chip *chip = mtd->priv;
- uint32_t r, c, d, diff; /*read, calculated, xor of them */
-
- if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes))
- return 0;
-
- /* Reorder the bytes into ascending-order 24 bits -- see manual */
- r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2;
- c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2;
- diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */
-
- /* If 12 bits are different, one per pair, it's correctable */
- if (((diff | (diff>>1)) & 0x555555) == 0x555555) {
- int bit = ((diff & 2) >> 1)
- | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3);
- int byte;
-
- d = diff >> 6; /* remove bit-order info */
- byte = ((d & 2) >> 1)
- | ((d & 0x8) >> 2) | ((d & 0x20) >> 3)
- | ((d & 0x80) >> 4) | ((d & 0x200) >> 5)
- | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7)
- | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9);
- /* correct the single bit */
- dat[byte] ^= 1<<bit;
- return 0;
- }
- /* If 1 bit only differs, it's one bit error in ECC, ignore */
- if ((diff ^ (1 << (ffs(diff) - 1))) == 0)
- return 0;
- /* Otherwise, uncorrectable */
- return -1;
-}
-
-static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode)
-{ /* mandatory in the structure but not used here */ }
-
-
-/* This is the layout used by older installations, we keep compatible */
-struct nand_ecclayout nomadik_ecc_layout = {
- .eccbytes = 3 * 4,
- .eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
- 0x02, 0x03, 0x04,
- 0x12, 0x13, 0x14,
- 0x22, 0x23, 0x24,
- 0x32, 0x33, 0x34},
- .oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
-};
-
-#define MASK_ALE (1 << 24) /* our ALE is AD21 */
-#define MASK_CLE (1 << 23) /* our CLE is AD22 */
-
-/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */
-static void nomadik_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- u32 pcr0 = readl(REG_FSMC_PCR0);
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- if (ctrl & NAND_NCE)
- writel(pcr0 | 0x4, REG_FSMC_PCR0);
- else
- writel(pcr0 & ~0x4, REG_FSMC_PCR0);
-
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- this->IO_ADDR_R = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */
-static int nomadik_nand_ready(struct mtd_info *mtd)
-{
- return 1; /* The ready bit is handled in hardware */
-}
-
-/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */
-static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
- u32 *p = (u32 *) buf;
-
- len >>= 2;
- writel(0, REG_FSMC_ECCR0);
- for (i = 0; i < len; i++)
- p[i] = readl(chip->IO_ADDR_R);
-}
-
-int board_nand_init(struct nand_chip *chip)
-{
- /* Set up the FSMC_PCR0 for nand access*/
- writel(0x0000004a, REG_FSMC_PCR0);
- /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */
- writel(0x00020401, REG_FSMC_PMEM0);
- writel(0x00020404, REG_FSMC_PATT0);
-
- chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
- chip->cmd_ctrl = nomadik_nand_hwcontrol;
- chip->dev_ready = nomadik_nand_ready;
- /* The chip allows 32bit reads, so avoid the default 8bit copy */
- chip->read_buf = nomadik_nand_read_buf;
-
- /* ECC: follow the hardware-defined rulse, but do it in sw */
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.bytes = 3;
- chip->ecc.size = 512;
- chip->ecc.strength = 1;
- chip->ecc.layout = &nomadik_ecc_layout;
- chip->ecc.calculate = nomadik_ecc_calculate;
- chip->ecc.hwctl = nomadik_ecc_hwctl;
- chip->ecc.correct = nomadik_ecc_correct;
-
- return 0;
-}
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
deleted file mode 100644
index dd70adc..0000000
--- a/include/configs/nhk8815.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2005
- * STMicroelectronics.
- * Configuration settings for the "Nomadik Hardware Kit" NHK-8815,
- * the evaluation board for the Nomadik 8815 System on Chip.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <nomadik.h>
-
-#define CONFIG_NOMADIK_8815 /* cpu variant */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
-
-/* commands */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_SYS_NO_FLASH
-/* There is NAND storage */
-#define CONFIG_NAND_NOMADIK
-#define CONFIG_CMD_JFFS2
-
-/* user interface */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* boot config */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
-#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \
- " fsload 0x800000 initrd.gz.uimg;" \
- " bootm 0x100000 0x800000"
-
-/* memory-related information */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
-
-#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */
-
-/* timing informazion */
-#define CONFIG_SYS_TIMERBASE 0x101E2000
-
-/* serial port (PL011) configuration */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CFG_SERIAL0 0x101FD000
-#define CFG_SERIAL1 0x101FB000
-
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
-#define CONFIG_PL011_CLOCK 48000000
-
-/* i2c, for the port extenders (uses gpio.c in board directory) */
-#ifndef __ASSEMBLY__
-#include <asm/arch/gpio.h>
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */
-#define I2C_SOFT_DEFS
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define __SDA 63
-#define __SCL 62
-#define I2C_SDA(x) nmk_gpio_set(__SDA, x)
-#define I2C_SCL(x) nmk_gpio_set(__SCL, x)
-#define I2C_READ (nmk_gpio_get(__SDA)!=0)
-#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1)
-#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0)
-#define I2C_DELAY (udelay(2))
-#endif /* __ASSEMBLY__ */
-
-/* Ethernet */
-#define PCI_MEMORY_VADDR 0xe8000000
-#define PCI_IO_VADDR 0xee000000
-#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
-#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
-
-#define CONFIG_SMC91111 /* Using SMC91c111*/
-#define CONFIG_SMC91111_BASE 0x34000300
-#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */
-#define CONFIG_TFTP_BLOCKSIZE 4096
-#define CONFIG_NFS_READ_SIZE 4096
-
-/* Storage information: onenand and nand */
-#define CONFIG_CMD_ONENAND
-#define CONFIG_MTD_ONENAND_VERIFY_WRITE
-#define CONFIG_SYS_ONENAND_BASE 0x30000000
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */
-
-/*
- * Filesystem information
- *
- * Since U-Boot has been loaded to RAM by vendor code, we could use
- * either or both OneNand and Nand. However, we need to know where the
- * filesystem lives. Comments below report vendor-selected partitions
- */
-#ifdef CONFIG_BOOT_ONENAND
- /* Partition Size Start
- * XloaderTOC + X-Loader 256KB 0x00000000
- * Memory init function 256KB 0x00040000
- * U-Boot + env 2MB 0x00080000
- * Sysimage (kernel + ramdisk) 4MB 0x00280000
- * JFFS2 Root filesystem 22MB 0x00680000
- * JFFS2 User Data 227.5MB 0x01C80000
- */
-# define CONFIG_JFFS2_DEV "onenand0"
-# define CONFIG_JFFS2_PART_SIZE 0x01600000
-# define CONFIG_JFFS2_PART_OFFSET 0x00680000
-# define CONFIG_ENV_IS_IN_ONENAND
-# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
-# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE)
-
-#else /* BOOT_NAND */
- /* Partition Size Start
- * XloaderTOC + X-Loader 256KB 0x00000000
- * Memory init function 256KB 0x00040000
- * U-Boot + env 2MB 0x00080000
- * Kernel Image 3MB 0x00280000
- * JFFS2 Root filesystem 22MB 0x00580000
- * JFFS2 User Data 100.5MB 0x01b80000
- */
-# define CONFIG_JFFS2_DEV "nand0"
-# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/
-# define CONFIG_JFFS2_PART_SIZE 0x01600000
-# define CONFIG_JFFS2_PART_OFFSET 0x00580000
-# define CONFIG_ENV_IS_IN_NAND
-# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
-# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE)
-
-#endif /* CONFIG_BOOT_ONENAND */
-
-/* this is needed to make hello_world.c and other stuff happy */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#endif /* __CONFIG_H */
diff --git a/include/nomadik.h b/include/nomadik.h
deleted file mode 100644
index ea65b2d..0000000
--- a/include/nomadik.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Collection of constants used to access Nomadik registers */
-
-#ifndef __NOMADIK_H__
-#define __NOMADIK_H__
-
-/* Base addresses of our peripherals */
-#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
-#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */
-#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
-#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */
-#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */
-#define NOMADIK_1NAND_BASE 0x30000000
-#define NOMADIK_GPIO0_BASE 0x101E4000
-#define NOMADIK_GPIO1_BASE 0x101E5000
-#define NOMADIK_GPIO2_BASE 0x101E6000
-#define NOMADIK_GPIO3_BASE 0x101E7000
-#define NOMADIK_CPLD_BASE 0x36000000
-#define NOMADIK_UART0_BASE 0x101FD000
-#define NOMADIK_UART1_BASE 0x101FB000
-#define NOMADIK_UART2_BASE 0x101F2000
-
-#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
-#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
-
-#define NOMADIK_RTC_BASE 0x101E8000
-#define NOMADIK_ETH0_BASE 0x36800300
-#define NOMADIK_CPLD_UART_BASE 0x36480000
-
-/* Chip select registers ("Flexible Static Memory Controller") */
-
-#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00)
-#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04)
-#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08)
-#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c)
-#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40)
-#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48)
-#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c)
-#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54)
-
-#endif /* __NOMADIK_H__ */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (19 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 20/45] arm: Remove nhk8815 boards and nomadik arch Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 13:47 ` Adam Ford
2015-08-31 1:19 ` [U-Boot] [PATCH 22/45] arm: Remove omap3_mvblx board Simon Glass
` (24 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/armv7/omap3/Kconfig | 4 -
board/logicpd/omap3som/Kconfig | 12 --
board/logicpd/omap3som/MAINTAINERS | 6 -
board/logicpd/omap3som/Makefile | 8 -
board/logicpd/omap3som/omap3logic.c | 242 ---------------------------
board/logicpd/omap3som/omap3logic.h | 31 ----
configs/omap3_logic_defconfig | 8 -
include/configs/omap3_logic.h | 322 ------------------------------------
8 files changed, 633 deletions(-)
delete mode 100644 board/logicpd/omap3som/Kconfig
delete mode 100644 board/logicpd/omap3som/MAINTAINERS
delete mode 100644 board/logicpd/omap3som/Makefile
delete mode 100644 board/logicpd/omap3som/omap3logic.c
delete mode 100644 board/logicpd/omap3som/omap3logic.h
delete mode 100644 configs/omap3_logic_defconfig
delete mode 100644 include/configs/omap3_logic.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 336da53..9665c95 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -87,9 +87,6 @@ config TARGET_MCX
bool "MCX"
select SUPPORT_SPL
-config TARGET_OMAP3_LOGIC
- bool "OMAP3 Logic"
-
config TARGET_OMAP3_MVBLX
bool "OMAP3 MVBLX"
@@ -139,7 +136,6 @@ source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
deleted file mode 100644
index 03d272a..0000000
--- a/board/logicpd/omap3som/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_LOGIC
-
-config SYS_BOARD
- default "omap3som"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_CONFIG_NAME
- default "omap3_logic"
-
-endif
diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS
deleted file mode 100644
index ffe2201..0000000
--- a/board/logicpd/omap3som/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OMAP3SOM BOARD
-M: Peter Barada <peter.barada@logicpd.com>
-S: Maintained
-F: board/logicpd/omap3som/
-F: include/configs/omap3_logic.h
-F: configs/omap3_logic_defconfig
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
deleted file mode 100644
index 87b86ad..0000000
--- a/board/logicpd/omap3som/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := omap3logic.o
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
deleted file mode 100644
index 609edf1..0000000
--- a/board/logicpd/omap3som/omap3logic.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author :
- * Peter Barada <peter.barada@logicpd.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <flash.h>
-#include <nand.h>
-#include <i2c.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "omap3logic.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * two dimensional array of strucures containining board name and Linux
- * machine IDs; row it selected based on CPU column is slected based
- * on hsusb0_data5 pin having a pulldown resistor
- */
-static struct board_id {
- char *name;
- int machine_id;
-} boards[2][2] = {
- {
- {
- .name = "OMAP35xx SOM LV",
- .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
- },
- {
- .name = "OMAP35xx Torpedo",
- .machine_id = MACH_TYPE_OMAP3_TORPEDO,
- },
- },
- {
- {
- .name = "DM37xx SOM LV",
- .machine_id = MACH_TYPE_DM3730_SOM_LV,
- },
- {
- .name = "DM37xx Torpedo",
- .machine_id = MACH_TYPE_DM3730_TORPEDO,
- },
- },
-};
-
-/*
- * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
- */
-#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- struct board_id *board;
- unsigned int val;
-
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- /*
- * To identify between a SOM LV and Torpedo module,
- * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
- * Drive the pin (and let it soak), then read it back.
- * If the pin is still high its a Torpedo. If low its a SOM LV
- */
-
- /* Mux hsusb0_data5 as a GPIO */
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
-
- if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
-
- /*
- * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
- * will drain the voltage.
- */
- gpio_direction_output(BOARD_ID_GPIO, 0);
- gpio_set_value(BOARD_ID_GPIO, 1);
-
- /* Let it soak for a bit */
- sdelay(0x100);
-
- /*
- * Read state of BOARD_ID_GPIO as an input and if its set.
- * If so the board is a Torpedo
- */
- gpio_direction_input(BOARD_ID_GPIO);
- val = gpio_get_value(BOARD_ID_GPIO);
- gpio_free(BOARD_ID_GPIO);
-
- board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
- printf("Board: %s\n", board->name);
-
- /* Set the machine_id passed to Linux */
- gd->bd->bi_arch_number = board->machine_id;
- }
-
- /* restore hsusb0_data5 pin as hsusb0_data5 */
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-
- return 0;
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_SMC911X
-/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
-static const u32 gpmc_lan92xx_config[] = {
- NET_LAN92XX_GPMC_CONFIG1,
- NET_LAN92XX_GPMC_CONFIG2,
- NET_LAN92XX_GPMC_CONFIG3,
- NET_LAN92XX_GPMC_CONFIG4,
- NET_LAN92XX_GPMC_CONFIG5,
- NET_LAN92XX_GPMC_CONFIG6,
-};
-
-int board_eth_init(bd_t *bis)
-{
- enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- /*GPMC*/
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
-
- /*Expansion card */
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
-
- /* Serial Console */
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
-
- /* I2C */
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
-
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
-
- /*Control and debug */
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
-}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
deleted file mode 100644
index 3a3ef6e..0000000
--- a/board/logicpd/omap3som/omap3logic.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author:
- * Peter Barada <peter.barada@logicpd.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _OMAP3LOGIC_H_
-#define _OMAP3LOGIC_H_
-
-/*
- * OMAP3 GPMC register settings for CS1 LAN922x
- */
-#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
-#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
-#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
-#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
-#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
-#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
-
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "Logic DM37x/OMAP35x reference board",
- "NAND",
-};
-
-
-#endif
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
deleted file mode 100644
index 5d0ac9e..0000000
--- a/configs/omap3_logic_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_LOGIC=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-CONFIG_SYS_PROMPT="OMAP Logic # "
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
deleted file mode 100644
index e09e617..0000000
--- a/include/configs/omap3_logic.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
- * Peter Barada <peter.barada@logicpd.com>
- *
- * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
- * reference boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SYS_TEXT_BASE 0x80400000
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
-
-/* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
- "1920k(u-boot),128k(u-boot-env),"\
- "4m(kernel),-(fs)"
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_QUIET_TEST
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand@*/
- /* CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
-
-/* Environment information */
-#define CONFIG_BOOTDELAY 2
-
-/*
- * PREBOOT assumes the 4.3" display is attached. User can interrupt
- * and modify display variable to suit their needs.
- */
-#define CONFIG_PREBOOT \
- "echo ======================NOTICE============================;"\
- "echo \"The u-boot environment is not set.\";" \
- "echo \"If using a display a valid display varible for your panel\";" \
- "echo \"needs to be set.\";" \
- "echo \"Valid display options are:\";" \
- "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
- "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
- "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
- "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
- "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
- "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
- "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
- "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
- "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
- "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
- "setenv display 15;" \
- "setenv preboot;" \
- "saveenv;"
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x81000000\0" \
- "bootfile=uImage\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "mmcdev=0\0" \
- "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "run defaultboot;" \
- "fi; " \
- "else run defaultboot; fi\0" \
- "defaultboot=run mmcramboot\0" \
- "consoledevice=ttyO0\0" \
- "display=15\0" \
- "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
- "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
- "rotation=0\0" \
- "vrfb_arg=if itest ${rotation} -ne 0; then " \
- "setenv bootargs ${bootargs} omapfb.vrfb=y " \
- "omapfb.rotate=${rotation}; " \
- "fi\0" \
- "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
- "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
- "${otherbootargs};" \
- "run addmtdparts; " \
- "run vrfb_arg\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo 'Running bootscript from mmc ...'; " \
- "source ${loadaddr}\0" \
- "loaduimage=mmc rescan ${mmcdev}; " \
- "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
- "ramdisksize=64000\0" \
- "ramdiskaddr=0x82000000\0" \
- "ramdiskimage=rootfs.ext2.gz.uboot\0" \
- "ramargs=run setconsole; setenv bootargs console=${console} " \
- "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
- "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
- "run ramargs; " \
- "run common_bootargs; " \
- "run dump_bootargs; " \
- "run loaduimage; " \
- "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
- "bootm ${loadaddr} ${ramdiskaddr}\0" \
- "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
- "run ramargs; " \
- "run common_bootargs; " \
- "run dump_bootargs; " \
- "tftpboot ${loadaddr} ${bootfile}; "\
- "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
- "bootm ${loadaddr} ${ramdiskaddr}\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run autoboot"
-
-#define CONFIG_AUTO_COMPLETE
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
-#endif
-
-/* Monitor@start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#endif
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * SMSC922x Ethernet
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_SMC911X_BASE 0x08000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * BOOTP fields
- */
-
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 22/45] arm: Remove omap3_mvblx board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (20 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,22/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 23/45] arm: Remove omap3_sdp3430 board Simon Glass
` (23 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/armv7/omap3/Kconfig | 4 -
board/matrix_vision/mvblx/Kconfig | 12 -
board/matrix_vision/mvblx/MAINTAINERS | 6 -
board/matrix_vision/mvblx/Makefile | 11 -
board/matrix_vision/mvblx/config.mk | 17 --
board/matrix_vision/mvblx/fpga.c | 214 -----------------
board/matrix_vision/mvblx/fpga.h | 15 --
board/matrix_vision/mvblx/mvblx.c | 159 -------------
board/matrix_vision/mvblx/mvblx.h | 346 ----------------------------
board/matrix_vision/mvblx/sys_eeprom.c | 403 ---------------------------------
configs/omap3_mvblx_defconfig | 9 -
doc/README.omap3 | 4 -
include/configs/omap3_mvblx.h | 277 ----------------------
13 files changed, 1477 deletions(-)
delete mode 100644 board/matrix_vision/mvblx/Kconfig
delete mode 100644 board/matrix_vision/mvblx/MAINTAINERS
delete mode 100644 board/matrix_vision/mvblx/Makefile
delete mode 100644 board/matrix_vision/mvblx/config.mk
delete mode 100644 board/matrix_vision/mvblx/fpga.c
delete mode 100644 board/matrix_vision/mvblx/fpga.h
delete mode 100644 board/matrix_vision/mvblx/mvblx.c
delete mode 100644 board/matrix_vision/mvblx/mvblx.h
delete mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
delete mode 100644 configs/omap3_mvblx_defconfig
delete mode 100644 include/configs/omap3_mvblx.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 9665c95..967c0a5 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -87,9 +87,6 @@ config TARGET_MCX
bool "MCX"
select SUPPORT_SPL
-config TARGET_OMAP3_MVBLX
- bool "OMAP3 MVBLX"
-
config TARGET_NOKIA_RX51
bool "Nokia RX51"
@@ -136,7 +133,6 @@ source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig
deleted file mode 100644
index adbc20a..0000000
--- a/board/matrix_vision/mvblx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_MVBLX
-
-config SYS_BOARD
- default "mvblx"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "omap3_mvblx"
-
-endif
diff --git a/board/matrix_vision/mvblx/MAINTAINERS b/board/matrix_vision/mvblx/MAINTAINERS
deleted file mode 100644
index 2f9a153..0000000
--- a/board/matrix_vision/mvblx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MVBLX BOARD
-M: Michael Jones <michael.jones@matrix-vision.de>
-S: Maintained
-F: board/matrix_vision/mvblx/
-F: include/configs/omap3_mvblx.h
-F: configs/omap3_mvblx_defconfig
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
deleted file mode 100644
index c056eba..0000000
--- a/board/matrix_vision/mvblx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mvblx.o fpga.o
-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-
-ccflags-y += -Werror
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
deleted file mode 100644
index de13072..0000000
--- a/board/matrix_vision/mvblx/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
deleted file mode 100644
index 7f9b245..0000000
--- a/board/matrix_vision/mvblx/fpga.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
- * Keith Outwater, keith_outwater at mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
- * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <linux/byteorder/generic.h>
-#include "fpga.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
- fpga_null_fn, /* Altera_pre_fn */
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_null_fn,
- fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
- Altera_CYC2,
- fast_passive_parallel,
- Altera_EP3C5_SIZE,
- (void *) &altera_fns,
- NULL,
- 0
-};
-
-#define GPIO_RESET 43
-#define GPIO_DCLK 65
-#define GPIO_nSTATUS 157
-#define GPIO_CONF_DONE 158
-#define GPIO_nCONFIG 159
-#define GPIO_DATA0 54
-#define GPIO_DATA1 55
-#define GPIO_DATA2 56
-#define GPIO_DATA3 57
-#define GPIO_DATA4 58
-#define GPIO_DATA5 60
-#define GPIO_DATA6 61
-#define GPIO_DATA7 62
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* return FPGA_SUCCESS on success, else FPGA_FAIL
- */
-int mvblx_init_fpga(void)
-{
- fpga_debug("Initializing FPGA interface\n");
- fpga_init();
- fpga_add(fpga_altera, &cyclone2);
-
- if (gpio_request(GPIO_DCLK, "dclk") ||
- gpio_request(GPIO_nSTATUS, "nStatus") ||
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- gpio_request(GPIO_CONF_DONE, "conf_done") ||
-#endif
- gpio_request(GPIO_nCONFIG, "nConfig") ||
- gpio_request(GPIO_DATA0, "data0") ||
- gpio_request(GPIO_DATA1, "data1") ||
- gpio_request(GPIO_DATA2, "data2") ||
- gpio_request(GPIO_DATA3, "data3") ||
- gpio_request(GPIO_DATA4, "data4") ||
- gpio_request(GPIO_DATA5, "data5") ||
- gpio_request(GPIO_DATA6, "data6") ||
- gpio_request(GPIO_DATA7, "data7")) {
- printf("%s: error requesting GPIOs.", __func__);
- return FPGA_FAIL;
- }
-
- /* set up outputs */
- gpio_direction_output(GPIO_DCLK, 0);
- gpio_direction_output(GPIO_nCONFIG, 0);
- gpio_direction_output(GPIO_DATA0, 0);
- gpio_direction_output(GPIO_DATA1, 0);
- gpio_direction_output(GPIO_DATA2, 0);
- gpio_direction_output(GPIO_DATA3, 0);
- gpio_direction_output(GPIO_DATA4, 0);
- gpio_direction_output(GPIO_DATA5, 0);
- gpio_direction_output(GPIO_DATA6, 0);
- gpio_direction_output(GPIO_DATA7, 0);
-
- /* NB omap_free_gpio() resets to an input, so we can't
- * free ie. nCONFIG, or else the FPGA would reset
- * Q: presumably gpio_free() has the same effect?
- */
-
- /* set up inputs */
- gpio_direction_input(GPIO_nSTATUS);
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- gpio_direction_input(GPIO_CONF_DONE);
-#endif
-
- fpga_config_fn(0, 1, 0);
- udelay(60);
-
- return FPGA_SUCCESS;
-}
-
-int fpga_null_fn(int cookie)
-{
- return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
- fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
- if (flush) {
- gpio_set_value(GPIO_nCONFIG, !assert);
- udelay(1);
- gpio_set_value(GPIO_nCONFIG, assert);
- }
-
- return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
- int result = 0;
-
- /* since revA of BLX, we will not get this signal. */
- udelay(10);
-#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- fpga_debug("not waiting for CONF_DONE.");
- result = 1;
-#else
- fpga_debug("CONF_DONE check ... ");
- if (gpio_get_value(GPIO_CONF_DONE)) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
- gpio_free(GPIO_CONF_DONE);
-#endif
-
- return result;
-}
-
-int fpga_status_fn(int cookie)
-{
- int result = 0;
- fpga_debug("STATUS check ... ");
-
- result = gpio_get_value(GPIO_nSTATUS);
-
- if (result < 0)
- fpga_debug("error\n");
- else if (result > 0)
- fpga_debug("high\n");
- else
- fpga_debug("low\n");
-
- return result;
-}
-
-static inline int _write_fpga(u8 byte)
-{
- gpio_set_value(GPIO_DATA0, byte & 0x01);
- gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
- gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
- gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
- gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
- gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
- gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
- gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
-
- /* clock */
- gpio_set_value(GPIO_DCLK, 1);
- udelay(1);
- gpio_set_value(GPIO_DCLK, 0);
- udelay(1);
-
- return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
- unsigned char *data = (unsigned char *) buf;
- int i;
- int headerlen = len - cyclone2.size;
-
- if (headerlen < 0)
- return FPGA_FAIL;
- else if (headerlen == sizeof(uint32_t)) {
- const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
- char fpgavers_str[fpgavers_len];
- snprintf(fpgavers_str, fpgavers_len, "0x%08x",
- be32_to_cpup((uint32_t*)data));
- setenv("fpgavers", fpgavers_str);
- }
-
- fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = headerlen; i < len; i++)
- _write_fpga(data[i]);
- fpga_debug("-%s\n", __func__);
-
- return FPGA_SUCCESS;
-}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
deleted file mode 100644
index 411b039..0000000
--- a/board/matrix_vision/mvblx/fpga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mvblx_init_fpga(void);
-
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
deleted file mode 100644
index c9d615b..0000000
--- a/board/matrix_vision/mvblx/mvblx.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from Beagle and Overo
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-types.h>
-#include "mvblx.h"
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- printf("mvBlueLYNX-X\n");
- if (get_cpu_family() == CPU_OMAP36XX)
- setenv("mpurate", "1000");
- else
- setenv("mpurate", "600");
-
- twl4030_power_init();
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif /* CONFIG_CMD_NET */
-
- mvblx_init_fpga();
-
- mac_read_from_eeprom();
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_MVBLX();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
- twl4030_power_mmc_init(1);
-}
-#endif
-
-#if defined(CONFIG_CMD_NET)
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-
- /* Make GPIO 139 as output pin */
- writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
-
- /* Now send a pulse on the GPIO pin */
- writel(GPIO11, &gpio5_base->setdataout);
- udelay(1);
- writel(GPIO11, &gpio5_base->cleardataout);
- udelay(1);
- writel(GPIO11, &gpio5_base->setdataout);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-int overwrite_console(void)
-{
- /* return true if console should be overwritten */
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
deleted file mode 100644
index 6c1c752..0000000
--- a/board/matrix_vision/mvblx/mvblx.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _MVBLX_H_
-#define _MVBLX_H_
-
-#include <asm/arch/sys_proto.h>
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 mvBlueLYNX-X camera",
- "no NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MVBLX() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card 1*/\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
- /*Expansion card 2 */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
- MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
- /* USB EHCI (port 2) not used */\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
- MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
- MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
- MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
- /* USB EHCI (port 1) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
deleted file mode 100644
index db42987..0000000
--- a/board/matrix_vision/mvblx/sys_eeprom.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- * York Sun (yorksun at freescale.com)
- * Haiying Wang (haiying.wang at freescale.com)
- * Timur Tabi (timur at freescale.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-/* #define DEBUG */
-
-/*
- * static eeprom: EEPROM layout
- */
-static struct __attribute__ ((__packed__)) eeprom {
- u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
- u8 sn[10]; /* 0x10 - 0x19 Serial Number */
- u8 date[6]; /* 0x1A - 0x1F Build Date */
- u8 mac[6]; /* 0x20 - 0x25 MAC address */
- u8 reserved[10];/* 0x26 - 0x2f reserved */
- u32 crc; /* x+1 CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-static void show_eeprom(void)
-{
- unsigned int crc;
- char safe_string[16];
-
-#ifdef DEBUG
- int i;
-#endif
- u8 *p;
-
- /* ID */
- strncpy(safe_string, (char *)e.id, sizeof(e.id));
- safe_string[sizeof(e.id)-1] = 0;
- printf("ID: mvBlueLYNX-X%s\n", safe_string);
-
- /* Serial number */
- strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
- safe_string[sizeof(e.sn)-1] = 0;
- printf("SN: %s\n", safe_string);
-
- /* Build date, BCD date values, as YYMMDDhhmmss */
- printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
- e.date[0], e.date[1], e.date[2],
- e.date[3] & 0x7F, e.date[4], e.date[5],
- e.date[3] & 0x80 ? "PM" : "");
-
- /* Show MAC address */
- p = e.mac;
- printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
- p[0], p[1], p[2], p[3], p[4], p[5]);
-
- crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
- if (crc == be32_to_cpu(e.crc))
- printf("CRC: %08x\n", be32_to_cpu(e.crc));
- else
- printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
- printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
- for (i = 0; i < sizeof(e); i++) {
- if ((i % 16) == 0)
- printf("%02X: ", i);
- printf("%02X ", ((u8 *)&e)[i]);
- if (((i % 16) == 15) || (i == sizeof(e) - 1))
- printf("\n");
- }
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-static int read_eeprom(void)
-{
- int ret;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
-
- if (has_been_read)
- return 0;
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
- ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e, sizeof(e));
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
-
-#ifdef DEBUG
- show_eeprom();
-#endif
-
- has_been_read = (ret == 0) ? 1 : 0;
-
- return ret;
-}
-
-/**
- * update_crc - update the CRC
- *
- * This function should be called after each update to the EEPROM structure,
- * to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
- u32 crc;
-
- crc = crc32(0, (void *)&e, sizeof(e) - 4);
- e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
- int ret = 0;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
-
- update_crc();
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
- ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e, sizeof(e));
-
- if (!ret) {
- /* Verify the write by reading back the EEPROM and comparing */
- struct eeprom e2;
-#ifdef DEBUG
- printf("%s verifying...\n", __func__);
-#endif
- ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e2, sizeof(e2));
-
- if (!ret && memcmp(&e, &e2, sizeof(e)))
- ret = -1;
- }
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
-
- if (ret) {
- printf("Programming failed.\n");
- has_been_read = 0;
- return -1;
- }
-
- printf("Programming passed.\n");
- return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
- if ((p >= '0') && (p <= '9'))
- return p - '0';
-
- if ((p >= 'A') && (p <= 'F'))
- return (p - 'A') + 10;
-
- if ((p >= 'a') && (p <= 'f'))
- return (p - 'a') + 10;
-
- return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
- unsigned int i;
-
- if (strlen(string) != 12) {
- printf("Usage: mac date YYMMDDhhmmss\n");
- return;
- }
-
- for (i = 0; i < 6; i++)
- e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
- update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in the MAC address field in the EEPROM local copy.
- */
-static void set_mac_address(const char *string)
-{
- char *p = (char *) string;
- unsigned int i;
-
- for (i = 0; *p && (i < 6); i++) {
- e.mac[i] = simple_strtoul(p, &p, 16);
- if (*p == ':')
- p++;
- }
-
- update_crc();
-}
-
-int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
-
- if (argc == 1) {
- show_eeprom();
- return 0;
- }
-
- cmd = argv[1][0];
-
- if (cmd == 'r') {
-#ifdef DEBUG
- printf("%s read\n", __func__);
-#endif
- read_eeprom();
- return 0;
- }
-
- if (argc == 2) {
- switch (cmd) {
- case 's': /* save */
-#ifdef DEBUG
- printf("%s save\n", __func__);
-#endif
- prog_eeprom();
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
- }
-
- /* We know we have@least one parameter */
-
- switch (cmd) {
- case 'n': /* serial number */
-#ifdef DEBUG
- printf("%s serial number\n", __func__);
-#endif
- memset(e.sn, 0, sizeof(e.sn));
- strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
- update_crc();
- break;
- case 'd': /* date BCD format YYMMDDhhmmss */
- set_date(argv[2]);
- break;
- case 'e': /* errata */
- printf("mac errata not implemented\n");
- break;
- case 'i': /* id */
- memset(e.id, 0, sizeof(e.id));
- strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
- update_crc();
- break;
- case 'p': /* ports */
- printf("mac ports not implemented (always 1 port)\n");
- break;
- case '0' ... '9':
- /* we only have "mac 0" but any digit can be used here */
- set_mac_address(argv[2]);
- break;
- case 'h': /* help */
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-static inline int is_portrait(void)
-{
- int i;
- unsigned int orient_index = 0; /* idx of char which determines orientation */
-
- for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
- if (e.id[i] == '-') {
- orient_index = i+1;
- break;
- }
- }
-
- return (orient_index &&
- (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
-}
-
-int mac_read_from_eeprom(void)
-{
- u32 crc, crc_offset = offsetof(struct eeprom, crc);
- u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
-#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
-
- if (read_eeprom()) {
- printf("EEPROM Read failed.\n");
- return -1;
- }
-
- crc = crc32(0, (void *)&e, crc_offset);
- crcp = (void *)&e + crc_offset;
- if (crc != be32_to_cpu(*crcp)) {
- printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
- be32_to_cpu(e.crc));
- return -1;
- }
-
- if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
- memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
- char ethaddr[18];
-
- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- e.mac[0],
- e.mac[1],
- e.mac[2],
- e.mac[3],
- e.mac[4],
- e.mac[5]);
- /* Only initialize environment variables that are blank
- * (i.e. have not yet been set)
- */
- if (!getenv("ethaddr"))
- setenv("ethaddr", ethaddr);
- }
-
- if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
- memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
- char serial_num[12];
-
- strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
- /* Only initialize environment variables that are blank
- * (i.e. have not yet been set)
- */
- if (!getenv("serial#"))
- setenv("serial#", serial_num);
- }
-
- /* decide which fpga file to load depending on orientation */
- if (is_portrait())
- setenv("fpgafilename", FILENAME_PORTRAIT);
- else
- setenv("fpgafilename", FILENAME_LANDSCAPE);
-
- /* TODO should I calculate CRC here? */
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *serial = getenv("serial#");
-
- if (serial && (strlen(serial) > 3)) {
- /* use the numerical part of the serial number LXnnnnnn */
- serialnr->high = 0;
- serialnr->low = simple_strtoul(serial + 2, NULL, 10);
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig
deleted file mode 100644
index fb12a70..0000000
--- a/configs/omap3_mvblx_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_MVBLX=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR="S"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="mvblx # "
diff --git a/doc/README.omap3 b/doc/README.omap3
index a62c357..e09ac03 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,10 +68,6 @@ make
make cm_t35_config
make
-* BlueLYNX-X:
-
-make omap3_mvblx_config
-make
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
deleted file mode 100644
index 9e2cf73..0000000
--- a/include/configs/omap3_mvblx.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the TI OMAP3530 Beagle board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
-#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT 1
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SERIAL_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
-
-/* silent console by default */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_SILENT_CONSOLE 1
-
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
-#define CONFIG_USBD_VENDORID 0x164c
-#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
-#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
-#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
-#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
-
-/* no FLASH available */
-#define CONFIG_SYS_NO_FLASH
-
-/* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_FPGA_LOADMK
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER 1
-
-/* Environment information */
-#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "silent=true\0" \
- "loadaddr=0x82000000\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO0,115200n8\0" \
- "mpurate=600\0" \
- "vram=12M\0" \
- "dvimode=1024x768-24@60\0" \
- "defaultdisplay=dvi\0" \
- "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
- "/lib/firmware/mvblx/${fpgafilename}; then " \
- "fpga load 0 ${loadaddr} ${filesize}; " \
- "fi;\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapfb.debug=y " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype} " \
- "mvfw.fpgavers=${fpgavers} " \
- "${cmdline_suffix}\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "mmcbootcmd= " \
- "echo Trying mmc${mmcdev}; " \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loading boot environment from mmc${mmcdev}; " \
- "run importbootenv; " \
- "fi;" \
- "run loadfpga; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi;" \
- "fi\0"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv mmcdev 1;" \
- "run mmcbootcmd || " \
- "setenv mmcdev 0;" \
- "run mmcbootcmd"
-
-
-#define CONFIG_AUTO_COMPLETE 1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
-#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
-#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-#define CONFIG_ENV_IS_NOWHERE 1
-
-/*----------------------------------------------------------------------------
- * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_SMC911X 1
- #define CONFIG_SMC911X_32_BIT
- #define CONFIG_SMC911X_BASE 0x2C000000
-#endif /* (CONFIG_CMD_NET) */
-
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_EEPROM_BUS_NUM 2
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_OMAP3_SPI
-
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 23/45] arm: Remove omap3_sdp3430 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (21 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 22/45] arm: Remove omap3_mvblx board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,23/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 24/45] arm: Remove openrd boards Simon Glass
` (22 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/armv7/omap3/Kconfig | 4 -
board/ti/sdp3430/Kconfig | 12 --
board/ti/sdp3430/MAINTAINERS | 6 -
board/ti/sdp3430/Makefile | 8 -
board/ti/sdp3430/config.mk | 17 --
board/ti/sdp3430/sdp.c | 203 --------------------
board/ti/sdp3430/sdp.h | 401 ---------------------------------------
configs/omap3_sdp3430_defconfig | 7 -
include/configs/omap3_sdp3430.h | 318 -------------------------------
9 files changed, 976 deletions(-)
delete mode 100644 board/ti/sdp3430/Kconfig
delete mode 100644 board/ti/sdp3430/MAINTAINERS
delete mode 100644 board/ti/sdp3430/Makefile
delete mode 100644 board/ti/sdp3430/config.mk
delete mode 100644 board/ti/sdp3430/sdp.c
delete mode 100644 board/ti/sdp3430/sdp.h
delete mode 100644 configs/omap3_sdp3430_defconfig
delete mode 100644 include/configs/omap3_sdp3430.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 967c0a5..c758038 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -12,9 +12,6 @@ config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
select SUPPORT_SPL
-config TARGET_OMAP3_SDP3430
- bool "TI OMAP3430 SDP"
-
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select SUPPORT_SPL
@@ -119,7 +116,6 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig
deleted file mode 100644
index 7e73d99..0000000
--- a/board/ti/sdp3430/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_SDP3430
-
-config SYS_BOARD
- default "sdp3430"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_sdp3430"
-
-endif
diff --git a/board/ti/sdp3430/MAINTAINERS b/board/ti/sdp3430/MAINTAINERS
deleted file mode 100644
index 943c196..0000000
--- a/board/ti/sdp3430/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SDP3430 BOARD
-M: Nishanth Menon <nm@ti.com>
-S: Maintained
-F: board/ti/sdp3430/
-F: include/configs/omap3_sdp3430.h
-F: configs/omap3_sdp3430_defconfig
diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile
deleted file mode 100644
index 753f099..0000000
--- a/board/ti/sdp3430/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sdp.o
diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk
deleted file mode 100644
index e4d9be1..0000000
--- a/board/ti/sdp3430/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
deleted file mode 100644
index 7171363..0000000
--- a/board/ti/sdp3430/sdp.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "sdp.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 SDP3430 board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#elif defined(CONFIG_ENV_IS_IN_NAND)
- "NAND",
-#else
- "NOR",
-#endif
-};
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-static const u32 gpmc_sdp_nor[] = {
- SDP3430_NOR_GPMC_CONF1,
- SDP3430_NOR_GPMC_CONF2,
- SDP3430_NOR_GPMC_CONF3,
- SDP3430_NOR_GPMC_CONF4,
- SDP3430_NOR_GPMC_CONF5,
- SDP3430_NOR_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-static const u32 gpmc_sdp_debug[] = {
- SDP3430_DEBUG_GPMC_CONF1,
- SDP3430_DEBUG_GPMC_CONF2,
- SDP3430_DEBUG_GPMC_CONF3,
- SDP3430_DEBUG_GPMC_CONF4,
- SDP3430_DEBUG_GPMC_CONF5,
- SDP3430_DEBUG_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* Timing defintions for GPMC OneNAND */
-static const u32 gpmc_sdp_onenand[] = {
- SDP3430_ONENAND_GPMC_CONF1,
- SDP3430_ONENAND_GPMC_CONF2,
- SDP3430_ONENAND_GPMC_CONF3,
- SDP3430_ONENAND_GPMC_CONF4,
- SDP3430_ONENAND_GPMC_CONF5,
- SDP3430_ONENAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* GPMC definitions for GPMC NAND */
-static const u32 gpmc_sdp_nand[] = {
- SDP3430_NAND_GPMC_CONF1,
- SDP3430_NAND_GPMC_CONF2,
- SDP3430_NAND_GPMC_CONF3,
- SDP3430_NAND_GPMC_CONF4,
- SDP3430_NAND_GPMC_CONF5,
- SDP3430_NAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/**
- * @brief board_init - gpmc and basic setup as phase1 of boot sequence
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* TODO: Dynamically pop out CS mapping and program accordingly */
- /* Configure devices for default ON ON ON settings */
- enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
- enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
- GPMC_SIZE_16M);
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
-#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
-
-/**
- * @brief board_eth_init Take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- */
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- writew(0x0, LAN_RESET_REGISTER);
- do {
- writew(0x1, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- writew(0x0, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x0000);
- udelay(1000);
-
- writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
- udelay(1000);
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-reset_err_out:
-
-#endif
- return rc;
-}
-
-/**
- * @brief misc_init_r - Configure SDP board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- /* Partial setup:
- * VAUX3 - 2.8V for DVI
- * VPLL1 - 1.8V
- * VDAC - 1.8V
- * and turns on LEDA/LEDB (not needed ... NOP?)
- */
- twl4030_power_init();
-
- /* FIXME finish setup:
- * VAUX1 - 2.8V for mainboard I/O
- * VAUX2 - 2.8V for camera
- * VAUX4 - 1.8V for OMAP3 CSI
- * VMMC1 - 3.15V (init, variable) for MMC1
- * VMMC2 - 1.85V for MMC2
- * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
- * VPLL2 - 1.8V
- */
-
- return 0;
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the hardware. Many pins need to be moved from protect
- * to primary mode.
- */
-void set_muxconf_regs(void)
-{
- /* platform specific muxes */
- MUX_SDP3430();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h
deleted file mode 100644
index 0e63189..0000000
--- a/board/ti/sdp3430/sdp.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _BOARD_SDP_H_
-#define _BOARD_SDP_H_
-
-#define OFF_IN_PD 0
-#define OFF_OUT_PD 0
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_SDP3430()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
- MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
- MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
- MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
- MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
- MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
- MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
- MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
- MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Audio InterfACe */\
- MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*Expansion Card */\
- MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
- MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
- MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
- MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
- MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
- MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
- MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
- MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
- MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
- MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
- MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
- MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
- MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
- MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
- MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
- MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
- MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
- MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
-
-/*
- * GPMC Timing definitions for SDP3430
- * at L3 = 166Mhz
- */
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-#define SDP3430_NOR_GPMC_CONF1 0x00001200
-#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
-#define SDP3430_NOR_GPMC_CONF3 0x00080802
-#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
-#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
-#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
-#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
-#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
-#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
-#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
-#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
-
-/* Timing defintions for GPMC OneNAND */
-#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
-#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
-#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
-#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
-#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
-#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
-
-/* GPMC definitions for GPMC NAND */
-#define SDP3430_NAND_GPMC_CONF1 0x00000800
-#define SDP3430_NAND_GPMC_CONF2 0x00141400
-#define SDP3430_NAND_GPMC_CONF3 0x00141400
-#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
-#define SDP3430_NAND_GPMC_CONF5 0x010C1414
-#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
-
-#endif /* _BOARD_SDP_H_ */
diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig
deleted file mode 100644
index 2e46091..0000000
--- a/configs/omap3_sdp3430_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_SDP3430=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="OMAP34XX SDP # "
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
deleted file mode 100644
index f43e477..0000000
--- a/include/configs/omap3_sdp3430.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * (C) Copyright 2006-2009
- * Texas Instruments Incorporated.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- * Nishanth Menon <nm@ti.com>
- *
- * Configuration settings for the 3430 TI SDP3430 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* TODO: REMOVE THE FOLLOWING
- * Retained the following till size.h is removed in u-boot
- */
-#include <linux/sizes.h>
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * NOTE: these #defines presume standard SDP jumper settings.
- * In particular:
- * - 26 MHz clock (not 19.2 or 38.4 MHz)
- * - Boot from 128MB NOR, not NAND or OneNAND
- *
- * At this writing, OMAP3 U-Boot support doesn't permit concurrent
- * support for all the flash types the board supports.
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Hardware drivers
- */
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER 1
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
- * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
- * support UART boot (that's only for UART3); it prevents sharing a Linux
- * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
- *
- * UART boot uses UART3 on J9, and the SDP user's guide says to use
- * that for console. Downsides of using J9: you can't use IRDA too;
- * since UART3 isn't in the CORE power domain, it may be a bit less
- * usable in certain PM-sensitive debug scenarios.
- */
-#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
-
-#ifdef CONSOLE_J9
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3 /* UART3 */
-#else
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * I2C for power management setup
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/* OMITTED: single 1 Gbit MT29F1G NAND flash */
-
-/*
- * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
- */
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH 2
-#define PHYS_FLASH_SIZE (128 << 20)
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
-
-/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
-#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
-/*--------------------------------------------------------------------------*/
-
-/* Enabled commands */
-#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_MMC /* MMC support */
-
-/*--------------------------------------------------------------------------*/
-/*
- * MMC boot support
- */
-
-#if defined(CONFIG_CMD_MMC)
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
-#endif
-
-/*----------------------------------------------------------------------------
- * SMSC9115 Ethernet from SMSC9118 family
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE DEBUG_BASE
-#define CONFIG_LAN91C96_EXT_PHY
-
-#define CONFIG_BOOTP_SEND_HOSTNAME
-/*
- * BOOTP fields
- */
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * Environment setup
- *
- * Default boot order: mmc bootscript, MMC uImage, NOR image.
- * Network booting environment must be configured at site.
- */
-
-/* allow overwriting serial config and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS0,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "norargs=setenv bootargs console=${console} " \
- "root=/dev/mtdblock3 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from MMC/SD ...; " \
- "autoscr ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from MMC/SD ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "norboot=echo Booting from NOR ...; " \
- "run norargs; " \
- "bootm 0x80000\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run norboot; " \
- "fi; " \
- "fi; " \
- "else run norboot; fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/* SDRAM Test range - start at 16 meg boundary -ends@32Meg -
- * a basic sanity check ONLY
- * IF you would like to increase coverage, increase the end address
- * or run the test with custom options
- */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * NOR FLASH usage ... default nCS0:
- * - one 256KB sector for U-Boot
- * - one 256KB sector for its parameters (not all used)
- * - eight sectors (2 MB) for kernel
- * - rest for JFFS2
- */
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
-/*
- * NAND FLASH usage ... default nCS1:
- * - four 128KB sectors for X-Loader
- * - four 128KB sectors for U-Boot
- * - two 128KB sector for its parameters
- * - 32 sectors (4 MB) for kernel
- * - rest for filesystem
- */
-
-/*
- * OneNAND FLASH usage ... default nCS2:
- * - four 128KB sectors for X-Loader
- * - two 128KB sectors for U-Boot
- * - one 128KB sector for its parameters
- * - sixteen sectors (2 MB) for kernel
- * - rest for filesystem
- */
-
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 24/45] arm: Remove openrd boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (22 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 23/45] arm: Remove omap3_sdp3430 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,24/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 25/45] arm: Remove otc570 board Simon Glass
` (21 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 4 -
board/Marvell/openrd/Kconfig | 12 ---
board/Marvell/openrd/MAINTAINERS | 12 ---
board/Marvell/openrd/Makefile | 14 ----
board/Marvell/openrd/kwbimage.cfg | 152 -----------------------------------
board/Marvell/openrd/openrd.c | 161 --------------------------------------
board/Marvell/openrd/openrd.h | 30 -------
configs/openrd_base_defconfig | 7 --
configs/openrd_client_defconfig | 7 --
configs/openrd_ultimate_defconfig | 7 --
include/configs/openrd.h | 137 --------------------------------
11 files changed, 543 deletions(-)
delete mode 100644 board/Marvell/openrd/Kconfig
delete mode 100644 board/Marvell/openrd/MAINTAINERS
delete mode 100644 board/Marvell/openrd/Makefile
delete mode 100644 board/Marvell/openrd/kwbimage.cfg
delete mode 100644 board/Marvell/openrd/openrd.c
delete mode 100644 board/Marvell/openrd/openrd.h
delete mode 100644 configs/openrd_base_defconfig
delete mode 100644 configs/openrd_client_defconfig
delete mode 100644 configs/openrd_ultimate_defconfig
delete mode 100644 include/configs/openrd.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ae29a11..9c6e398 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,9 +4,6 @@ choice
prompt "Marvell Kirkwood board select"
optional
-config TARGET_OPENRD
- bool "Marvell OpenRD Board"
-
config TARGET_RD6281A
bool "RD6281A Board"
@@ -54,7 +51,6 @@ endchoice
config SYS_SOC
default "kirkwood"
-source "board/Marvell/openrd/Kconfig"
source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig
deleted file mode 100644
index 124b66d..0000000
--- a/board/Marvell/openrd/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OPENRD
-
-config SYS_BOARD
- default "openrd"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "openrd"
-
-endif
diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS
deleted file mode 100644
index 7a189ab..0000000
--- a/board/Marvell/openrd/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-OPENRD BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/openrd/
-F: include/configs/openrd.h
-F: configs/openrd_base_defconfig
-
-OPENRD_CLIENT BOARD
-#M: -
-S: Maintained
-F: configs/openrd_client_defconfig
-F: configs/openrd_ultimate_defconfig
diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile
deleted file mode 100644
index 8f95b79..0000000
--- a/board/Marvell/openrd/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := openrd.o
diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
deleted file mode 100644
index 8e59937..0000000
--- a/board/Marvell/openrd/kwbimage.cfg
+++ /dev/null
@@ -1,152 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strength reduced
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
-# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
-# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
-# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-
-DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
-# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
-# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT: Enabled
-# bit15: 1, DDR IO ODT Unit: Use ODT block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
deleted file mode 100644
index 55cf525..0000000
--- a/board/Marvell/openrd/openrd.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.c:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "openrd.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(OPENRD_OE_VAL_LOW,
- OPENRD_OE_VAL_HIGH,
- OPENRD_OE_LOW, OPENRD_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD, /* Alt UART1_TXD */
- MPP14_SD_D0, /* Alt UART1_RXD */
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_TSMP9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO, /* UART1 / SD sel */
- MPP35_TDM_CH0_TX_QL,
- MPP36_TDM_SPI_CS1,
- MPP37_TDM_CH2_TX_QL,
- MPP38_TDM_CH2_RX_QL,
- MPP39_AUDIO_I2SBCLK,
- MPP40_AUDIO_I2SDO,
- MPP41_AUDIO_I2SLRC,
- MPP42_AUDIO_I2SMCLK,
- MPP43_AUDIO_I2SDI,
- MPP44_AUDIO_EXTCLK,
- MPP45_TDM_PCLK,
- MPP46_TDM_FS,
- MPP47_TDM_DRX,
- MPP48_TDM_DTX,
- MPP49_TDM_CH0_RX_QL,
- 0
- };
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
-#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
-#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
-#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116/88E1121 PHY */
-void mv_phy_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf(PHY_NO" Initialized on %s\n", name);
-}
-
-void reset_phy(void)
-{
- mv_phy_init("egiga0");
-
-#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
- /* Kirkwood ethernet driver is written with the assumption that in case
- * of multiple PHYs, their addresses are consecutive. But unfortunately
- * in case of OpenRD-Client, PHY addresses are not consecutive.*/
- miiphy_write("egiga1", 0xEE, 0xEE, 24);
-#endif
-
-#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
- defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
- /* configure and initialize both PHY's */
- mv_phy_init("egiga1");
-#endif
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h
deleted file mode 100644
index 56dfeea..0000000
--- a/board/Marvell/openrd/openrd.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.h:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OPENRD_BASE_H
-#define __OPENRD_BASE_H
-
-#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
-#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __OPENRD_BASE_H */
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
deleted file mode 100644
index 1686139..0000000
--- a/configs/openrd_base_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
deleted file mode 100644
index c342315..0000000
--- a/configs/openrd_client_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
deleted file mode 100644
index 530ba4d..0000000
--- a/configs/openrd_ultimate_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
deleted file mode 100644
index 7211314..0000000
--- a/include/configs/openrd.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.h:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_OPENRD_H
-#define _CONFIG_OPENRD_H
-
-/*
- * Version number information
- */
-#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
-#else
-# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
-# define CONFIG_IDENT_STRING "\nOpenRD-Client"
-# else
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_IDENT_STRING "\nOpenRD-Base"
-# else
-# error Unknown OpenRD board specified
-# endif
-# endif
-#endif
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_OPENRD_BASE /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x60000
-#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define MTDIDS_DEFAULT "nand0=nand_mtd"
-#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000 at 0x000000(uboot),"\
- "0x400000 at 0x100000(uImage),"\
- "0x1fb00000 at 0x500000(rootfs)"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
- "mtdids="MTDIDS_DEFAULT"\0" \
- "mtdparts="MTDPARTS_DEFAULT"\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-# else
-# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-# endif
-# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_PHY_BASE_ADR 0x0
-# define PHY_NO "88E1121"
-# else
-# define CONFIG_PHY_BASE_ADR 0x8
-# define PHY_NO "88E1116"
-# endif
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-#endif /* _CONFIG_OPENRD_BASE_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 25/45] arm: Remove otc570 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (23 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 24/45] arm: Remove openrd boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,25/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 26/45] arm: Remove palmld board Simon Glass
` (20 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 5 -
board/esd/otc570/Kconfig | 12 --
board/esd/otc570/MAINTAINERS | 7 -
board/esd/otc570/Makefile | 13 --
board/esd/otc570/otc570.c | 372 -------------------------------------
board/esd/otc570/partition.c | 23 ---
configs/otc570_dataflash_defconfig | 8 -
configs/otc570_defconfig | 8 -
include/configs/otc570.h | 252 -------------------------
9 files changed, 700 deletions(-)
delete mode 100644 board/esd/otc570/Kconfig
delete mode 100644 board/esd/otc570/MAINTAINERS
delete mode 100644 board/esd/otc570/Makefile
delete mode 100644 board/esd/otc570/otc570.c
delete mode 100644 board/esd/otc570/partition.c
delete mode 100644 configs/otc570_dataflash_defconfig
delete mode 100644 configs/otc570_defconfig
delete mode 100644 include/configs/otc570.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index d2d60f3..f70ccbc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -99,10 +99,6 @@ config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
select CPU_ARM926EJS
-config TARGET_OTC570
- bool "Support otc570"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
@@ -139,7 +135,6 @@ source "board/bluewater/snapper9260/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
-source "board/esd/otc570/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig
deleted file mode 100644
index 4966f5f..0000000
--- a/board/esd/otc570/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OTC570
-
-config SYS_BOARD
- default "otc570"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "otc570"
-
-endif
diff --git a/board/esd/otc570/MAINTAINERS b/board/esd/otc570/MAINTAINERS
deleted file mode 100644
index a7e165d..0000000
--- a/board/esd/otc570/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-OTC570 BOARD
-M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-S: Maintained
-F: board/esd/otc570/
-F: include/configs/otc570.h
-F: configs/otc570_defconfig
-F: configs/otc570_dataflash_defconfig
diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile
deleted file mode 100644
index 740bb0a..0000000
--- a/board/esd/otc570/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += otc570.o
-obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
deleted file mode 100644
index 4751d0a..0000000
--- a/board/esd/otc570/otc570.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <netdev.h>
-#ifdef CONFIG_LCD
-# include <atmel_lcdc.h>
-# include <lcd.h>
-# ifdef CONFIG_LCD_INFO
-# include <nand.h>
-# include <version.h>
-# endif
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-static int hw_rev = -1; /* hardware revision */
-
-int get_hw_rev(void)
-{
- if (hw_rev >= 0)
- return hw_rev;
-
- hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
-
- if (hw_rev == 15)
- hw_rev = 0;
-
- return hw_rev;
-}
-
-#ifdef CONFIG_CMD_NAND
-static void otc570_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa[0]);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
- &smc->cs[3].setup);
-
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
-
- writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(12),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif /* CONFIG_CMD_NAND */
-
-#ifdef CONFIG_MACB
-static void otc570_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
- at91_macb_hw_init();
-}
-#endif
-
-/*
- * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
- * controller debugging
- * The ET1100 is located at physical address 0x70000000
- * Its process memory is located at physical address 0x70001000
- */
-static void otc570_ethercat_hw_init(void)
-{
- at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
-
- /* Configure SMC EBI1_CS0 for EtherCAT */
- writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
- &smc1->cs[0].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
- AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
- &smc1->cs[0].pulse);
- writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
- &smc1->cs[0].cycle);
- /*
- * Configure behavior at external wait signal, byte-select mode, 16 bit
- * data bus width, none data float wait states and TDF optimization
- */
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
- AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
- AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
-
- /* Configure RDY/BSY */
- at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
-}
-
-#ifdef CONFIG_LCD
-/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
-vidinfo_t panel_info = {
- .vl_col = 640,
- .vl_row = 480,
- .vl_clk = 25175000,
- .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
-
- .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
- .vl_tft = 1, /* 0 = passive, 1 = TFT */
- .vl_vsync_len = 1, /* Length of vertical sync in NOL */
- .vl_upper_margin = 35, /* Idle lines at the frame start */
- .vl_lower_margin = 5, /* Idle lines at the end of the frame */
- .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
- .vl_left_margin = 112, /* Idle cycles at the line beginning */
- .vl_right_margin = 1, /* Idle cycles at the end of the line */
-
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
-}
-
-void lcd_disable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
-}
-
-static void otc570_lcd_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
- at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
- at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size;
- int i;
- char temp[32];
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
- nand_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
-
- lcd_printf("\n%s\n", U_BOOT_VERSION);
- lcd_printf("CPU@%s MHz\n", strmhz(temp, get_cpu_clk_rate()));
- lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
- dram_size >> 20,
- nand_size >> 20 );
- lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
- lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
- lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
-}
-#endif /* CONFIG_LCD_INFO */
-#endif /* CONFIG_LCD */
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
- return rc;
-}
-
-int checkboard(void)
-{
- char str[32];
-
- puts("Board : esd ARM9 HMI Panel - OTC570");
- if (getenv_f("serial#", str, sizeof(str)) > 0) {
- puts(", serial# ");
- puts(str);
- }
- printf("\n");
- printf("Hardware-revision: 1.%d\n", get_hw_rev());
- printf("Mach-type : %lu\n", gd->bd->bi_arch_number);
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *str;
-
- char *serial = getenv("serial#");
- if (serial) {
- str = strchr(serial, '_');
- if (str && (strlen(str) >= 4)) {
- serialnr->high = (*(str + 1) << 8) | *(str + 2);
- serialnr->low = simple_strtoul(str + 3, NULL, 16);
- }
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
- return hw_rev | 0x100;
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- char str[64];
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
- /* Set USART_MODE = 1 (RS485) */
- writel(1, 0xFFF8C004);
-
- printf("USART0: ");
-
- if (getenv_f("usart0", str, sizeof(str)) == -1) {
- printf("No entry - assuming 1-wire\n");
- /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- } else {
- if (strcmp(str, "1-wire") == 0) {
- printf("%s\n", str);
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- } else if (strcmp(str, "rs485") == 0) {
- printf("%s\n", str);
- at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
- } else {
- printf("Wrong entry - assuming 1-wire ");
- printf("(valid values are '1-wire' or 'rs485')\n");
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- }
- }
-#ifdef CONFIG_LCD
- printf("Display memory address: 0x%08lX\n", gd->fb_base);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* enable all clocks */
- writel((1 << ATMEL_ID_PIOA) |
- (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE) |
- (1 << ATMEL_ID_TWI) |
- (1 << ATMEL_ID_SPI0) |
-#ifdef CONFIG_LCD
- (1 << ATMEL_ID_LCDC) |
-#endif
- (1 << ATMEL_ID_UHP),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- /* arch number of OTC570-Board */
- gd->bd->bi_arch_number = MACH_TYPE_OTC570;
-
- return 0;
-}
-
-int board_init(void)
-{
- /* initialize ET1100 Controller */
- otc570_ethercat_hw_init();
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- otc570_nand_hw_init();
-#endif
-#ifdef CONFIG_HAS_DATAFLASH
- at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
- otc570_macb_hw_init();
-#endif
-#ifdef CONFIG_AT91_CAN
- at91_can_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
- at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
- otc570_lcd_hw_init();
-#endif
- return 0;
-}
diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c
deleted file mode 100644
index b6afafc..0000000
--- a/board/esd/otc570/partition.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
-};
-
-/* define the area offsets */
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
-};
diff --git a/configs/otc570_dataflash_defconfig b/configs/otc570_dataflash_defconfig
deleted file mode 100644
index c5ff59a..0000000
--- a/configs/otc570_dataflash_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_OTC570=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/otc570_defconfig b/configs/otc570_defconfig
deleted file mode 100644
index 8cc55ee..0000000
--- a/configs/otc570_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_OTC570=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
deleted file mode 100644
index 0cada63..0000000
--- a/include/configs/otc570.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * Configuation settings for the esd OTC570 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- * Since the linker has to swallow that define, we must use a pure
- * hex number here!
- */
-#define CONFIG_SYS_TEXT_BASE 0x20002000
-
-/*
- * since a number of boards are not being listed in linux
- * arch/arm/tools/mach-types any more, the mach-types have to be
- * defined here
- */
-#define MACH_TYPE_OTC570 2166
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
-
-/* Misc CPU related */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-
-#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-/*
- * Hardware drivers
- */
-
-/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-/* general purpose I/O */
-#define CONFIG_AT91_GPIO
-
-/* Console output */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* LCD */
-#define CONFIG_LCD
-#undef CONFIG_SPLASH_SCREEN
-
-#ifdef CONFIG_LCD
-# define LCD_BPP LCD_COLOR8
-
-# ifndef CONFIG_SPLASH_SCREEN
-# define CONFIG_LCD_LOGO
-# define CONFIG_LCD_INFO
-# undef CONFIG_LCD_INFO_BELOW_LOGO
-# endif /* CONFIG_SPLASH_SCREEN */
-
-# undef LCD_TEST_PATTERN
-# define CONFIG_SYS_WHITE_ON_BLACK
-# define CONFIG_ATMEL_LCD
-# define CONFIG_SYS_CONSOLE_IS_IN_ENV
-# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000)
-# define CONFIG_CMD_BMP
-#endif /* CONFIG_LCD */
-
-/* RTC and I2C stuff */
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-
-/* Configure data and clock pins for pio */
-# define I2C_INIT { \
- at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
- at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
-}
-# define I2C_SOFT_DECLARATIONS
-/* Configure data pin as output */
-# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
-/* Configure data pin as input */
-# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
-/* Read data pin */
-# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4)
-/* Set data pin */
-# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
-/* Set clock pin */
-# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
-# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-
-/* LED */
-#define CONFIG_AT91_LED
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-
-/*
- * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-/* DataFlash */
-#ifdef CONFIG_SYS_USE_DATAFLASH
-# define CONFIG_ATMEL_DATAFLASH_SPI
-# define CONFIG_HAS_DATAFLASH
-# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
-# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
-# define AT91_SPI_CLK 15000000
-# define DATAFLASH_TCSS (0x1a << 16)
-# define DATAFLASH_TCHS (0x1 << 24)
-#endif
-
-/* NOR flash is not populated, disable it */
-#define CONFIG_SYS_NO_FLASH
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-# define CONFIG_NAND_ATMEL
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */
-# define CONFIG_SYS_NAND_DBW_8
-# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_FIT
-#define CONFIG_NET_RETRY_COUNT 20
-#undef CONFIG_RESET_PHY_R
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
-
-/* CAN */
-#define CONFIG_AT91_CAN
-
-/* hw-controller addresses */
-#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */
-
-#ifdef CONFIG_SYS_USE_DATAFLASH
-
-/* bootstrap + u-boot + env in dataflash on CS0 */
-# define CONFIG_ENV_IS_IN_DATAFLASH
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- 0x8400)
-# define CONFIG_ENV_OFFSET 0x4200
-# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- CONFIG_ENV_OFFSET)
-# define CONFIG_ENV_SIZE 0x4200
-
-#elif CONFIG_SYS_USE_NANDFLASH
-
-/* bootstrap + u-boot + env + linux in nandflash */
-# define CONFIG_ENV_IS_IN_NAND 1
-# define CONFIG_ENV_OFFSET 0xC0000
-# define CONFIG_ENV_SIZE 0x20000
-
-#endif
-
-#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- 128*1024, 0x1000)
-
-#endif
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 26/45] arm: Remove palmld board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (24 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 25/45] arm: Remove otc570 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,26/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 27/45] arm: Remove palmtc board Simon Glass
` (19 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/palmld/Kconfig | 9 --
board/palmld/MAINTAINERS | 6 --
board/palmld/Makefile | 9 --
board/palmld/palmld.c | 61 ------------
configs/palmld_defconfig | 7 --
include/configs/palmld.h | 245 -----------------------------------------------
7 files changed, 342 deletions(-)
delete mode 100644 board/palmld/Kconfig
delete mode 100644 board/palmld/MAINTAINERS
delete mode 100644 board/palmld/Makefile
delete mode 100644 board/palmld/palmld.c
delete mode 100644 configs/palmld_defconfig
delete mode 100644 include/configs/palmld.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d1da69..370ee24 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -724,10 +724,6 @@ config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMLD
- bool "Support palmld"
- select CPU_PXA
-
config TARGET_PALMTC
bool "Support palmtc"
select CPU_PXA
@@ -894,7 +890,6 @@ source "board/kosagi/novena/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmld/Kconfig"
source "board/palmtc/Kconfig"
source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
diff --git a/board/palmld/Kconfig b/board/palmld/Kconfig
deleted file mode 100644
index 3111295..0000000
--- a/board/palmld/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PALMLD
-
-config SYS_BOARD
- default "palmld"
-
-config SYS_CONFIG_NAME
- default "palmld"
-
-endif
diff --git a/board/palmld/MAINTAINERS b/board/palmld/MAINTAINERS
deleted file mode 100644
index 7d21b7b..0000000
--- a/board/palmld/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PALMLD BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/palmld/
-F: include/configs/palmld.h
-F: configs/palmld_defconfig
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
deleted file mode 100644
index ea93ca8..0000000
--- a/board/palmld/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Palm LifeDrive Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := palmld.o
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
deleted file mode 100644
index fee4dcd..0000000
--- a/board/palmld/palmld.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Palm LifeDrive Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of PalmLD */
- gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Set PWM for LCD */
- writel(0x7, PWM_CTRL0);
- writel(0x16c, PWM_PERVAL0);
- writel(0x11a, PWM_PWDUTY0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
diff --git a/configs/palmld_defconfig b/configs/palmld_defconfig
deleted file mode 100644
index 354071a..0000000
--- a/configs/palmld_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_PALMLD=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
deleted file mode 100644
index ec48c14..0000000
--- a/include/configs/palmld.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Palm LifeDrive configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOOTCOMMAND \
- "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x0x60000; " \
- "fi; "
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 9600
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_IDE
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_LQ038J7DH53
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SIZE 0x4000
-
-/*
- * IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x10
-#define CONFIG_SYS_ATA_REG_OFFSET 0x10
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x10
-
-#define CONFIG_SYS_ATA_STRIDE 1
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012
-#define CONFIG_SYS_GAFR1_L_VAL 0x69988056
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa
-#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x01040001
-#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
-#define CONFIG_SYS_GAFR3_U_VAL 0x00000009
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0xc26b0000
-#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93
-#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff
-#define CONFIG_SYS_GPDR3_VAL 0x006ff38d
-#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee
-#define CONFIG_SYS_GPSR1_VAL 0x03affdae
-#define CONFIG_SYS_GPSR2_VAL 0x07554000
-#define CONFIG_SYS_GPSR3_VAL 0x01bc0785
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01ffffff
-#define CONFIG_SYS_CCCR 0x02000210
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
-#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
-#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
-#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
-#define CONFIG_SYS_MDREFR_VAL 0x201fa031
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
-#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
-#define CONFIG_SYS_MCATT0_VAL 0x0001c391
-#define CONFIG_SYS_MCATT1_VAL 0x0001c391
-#define CONFIG_SYS_MCIO0_VAL 0x00014611
-#define CONFIG_SYS_MCIO1_VAL 0x0001c391
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 27/45] arm: Remove palmtc board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (25 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 26/45] arm: Remove palmld board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,27/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards Simon Glass
` (18 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 --
board/palmtc/Kconfig | 9 --
board/palmtc/MAINTAINERS | 6 --
board/palmtc/Makefile | 9 --
board/palmtc/palmtc.c | 61 -------------
configs/palmtc_defconfig | 6 --
include/configs/palmtc.h | 219 -----------------------------------------------
7 files changed, 315 deletions(-)
delete mode 100644 board/palmtc/Kconfig
delete mode 100644 board/palmtc/MAINTAINERS
delete mode 100644 board/palmtc/Makefile
delete mode 100644 board/palmtc/palmtc.c
delete mode 100644 configs/palmtc_defconfig
delete mode 100644 include/configs/palmtc.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 370ee24..459c7db 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -724,10 +724,6 @@ config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMTC
- bool "Support palmtc"
- select CPU_PXA
-
config TARGET_PALMTREO680
bool "Support palmtreo680"
select CPU_PXA
@@ -890,7 +886,6 @@ source "board/kosagi/novena/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmtc/Kconfig"
source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
diff --git a/board/palmtc/Kconfig b/board/palmtc/Kconfig
deleted file mode 100644
index 3eb7198..0000000
--- a/board/palmtc/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PALMTC
-
-config SYS_BOARD
- default "palmtc"
-
-config SYS_CONFIG_NAME
- default "palmtc"
-
-endif
diff --git a/board/palmtc/MAINTAINERS b/board/palmtc/MAINTAINERS
deleted file mode 100644
index 57b6a22..0000000
--- a/board/palmtc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PALMTC BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/palmtc/
-F: include/configs/palmtc.h
-F: configs/palmtc_defconfig
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
deleted file mode 100644
index b4a682d..0000000
--- a/board/palmtc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Palm Tungsten|C Support
-#
-# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := palmtc.o
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
deleted file mode 100644
index a6207b4..0000000
--- a/board/palmtc/palmtc.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Palm Tungsten|C Support
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* Arch number of Palm Tungsten|C */
- gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
-
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Set PWM for LCD */
- writel(0x5f, PWM_CTRL1);
- writel(0x3ff, PWM_PERVAL1);
- writel(892, PWM_PWDUTY1);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
diff --git a/configs/palmtc_defconfig b/configs/palmtc_defconfig
deleted file mode 100644
index de617e1..0000000
--- a/configs/palmtc_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_PALMTC=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
deleted file mode 100644
index 81c3f02..0000000
--- a/include/configs/palmtc.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Palm Tungsten|C configuration file
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/pxa-regs.h>
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
-#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x80000; " \
- "fi; "
-#define CONFIG_BOOTARGS \
- "console=tty0 console=ttyS0,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- * STUART - the lower serial port on Colibri board
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_ACX517AKN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_ADDR 0x40000
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x00011004
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
-#define CONFIG_SYS_GAFR1_L_VAL 0x60888050
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
-#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
-#define CONFIG_SYS_GPCR0_VAL 0x0
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xcfff8140
-#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
-#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
-#define CONFIG_SYS_GPSR0_VAL 0x00010f8f
-#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
-#define CONFIG_SYS_GPSR2_VAL 0x03fe0800
-
-#define CONFIG_SYS_PSSR_VAL PSSR_RDH
-
-/* Clock setup:
- * CKEN[1] - PWM1 ; CKEN[6] - FFUART
- * CKEN[12] - MMC ; CKEN[16] - LCD
- */
-#define CONFIG_SYS_CKEN 0x00011042
-#define CONFIG_SYS_CCCR 0x00000161
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x800092c2
-#define CONFIG_SYS_MSC1_VAL 0x80008000
-#define CONFIG_SYS_MSC2_VAL 0x80008000
-#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
-#define CONFIG_SYS_MDREFR_VAL 0x00118018
-#define CONFIG_SYS_MDMRS_VAL 0x00220032
-#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00010e04
-#define CONFIG_SYS_MCIO1_VAL 0x00010e04
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (26 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 27/45] arm: Remove palmtc board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 6:41 ` Stefano Babic
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 29/45] arm: Remove portuxg20, stamp9g20 boards Simon Glass
` (17 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/trizepsiv/Kconfig | 9 --
board/trizepsiv/MAINTAINERS | 7 -
board/trizepsiv/Makefile | 8 --
board/trizepsiv/conxs.c | 148 ---------------------
board/trizepsiv/eeprom.c | 62 ---------
configs/polaris_defconfig | 4 -
configs/trizepsiv_defconfig | 3 -
include/configs/trizepsiv.h | 309 --------------------------------------------
9 files changed, 555 deletions(-)
delete mode 100644 board/trizepsiv/Kconfig
delete mode 100644 board/trizepsiv/MAINTAINERS
delete mode 100644 board/trizepsiv/Makefile
delete mode 100644 board/trizepsiv/conxs.c
delete mode 100644 board/trizepsiv/eeprom.c
delete mode 100644 configs/polaris_defconfig
delete mode 100644 configs/trizepsiv_defconfig
delete mode 100644 include/configs/trizepsiv.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 459c7db..93f5c89 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -733,10 +733,6 @@ config TARGET_PXA255_IDP
bool "Support pxa255_idp"
select CPU_PXA
-config TARGET_TRIZEPSIV
- bool "Support trizepsiv"
- select CPU_PXA
-
config TARGET_VPAC270
bool "Support vpac270"
select CPU_PXA
@@ -917,7 +913,6 @@ source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
-source "board/trizepsiv/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
diff --git a/board/trizepsiv/Kconfig b/board/trizepsiv/Kconfig
deleted file mode 100644
index 56b2557..0000000
--- a/board/trizepsiv/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TRIZEPSIV
-
-config SYS_BOARD
- default "trizepsiv"
-
-config SYS_CONFIG_NAME
- default "trizepsiv"
-
-endif
diff --git a/board/trizepsiv/MAINTAINERS b/board/trizepsiv/MAINTAINERS
deleted file mode 100644
index ba48c2e..0000000
--- a/board/trizepsiv/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-TRIZEPSIV BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/trizepsiv/
-F: include/configs/trizepsiv.h
-F: configs/polaris_defconfig
-F: configs/trizepsiv_defconfig
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
deleted file mode 100644
index c49686f..0000000
--- a/board/trizepsiv/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := conxs.o eeprom.o
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
deleted file mode 100644
index 1ddf05d..0000000
--- a/board/trizepsiv/conxs.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic at denx.de
- *
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-#if CONFIG_MK_POLARIS
-#define BOOT_CONSOLE "serial_stuart"
-#else
-#define BOOT_CONSOLE "serial_ffuart"
-#endif
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
- writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of ConXS Board */
- gd->bd->bi_arch_number = 776;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa000003c;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- char *console=getenv("boot_console");
-
- if ((console == NULL) || (strcmp(console,"serial_btuart") &&
- strcmp(console,"serial_stuart") &&
- strcmp(console,"serial_ffuart"))) {
- console = BOOT_CONSOLE;
- }
- setenv("stdout",console);
- setenv("stdin", console);
- setenv("stderr",console);
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
deleted file mode 100644
index 1318edc..0000000
--- a/board/trizepsiv/eeprom.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <dm9000.h>
-
-static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- unsigned int i;
- u8 data[2];
-
- for (i=0; i < 0x40; i++) {
- if (!(i % 0x10))
- printf("\n%08x:", i);
- dm9000_read_srom_word(i, data);
- printf(" %02x%02x", data[1], data[0]);
- }
- printf ("\n");
- return (0);
-}
-
-static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- int offset,value;
-
- if (argc < 4)
- return cmd_usage(cmdtp);
-
- offset=simple_strtoul(argv[2],NULL,16);
- value=simple_strtoul(argv[3],NULL,16);
- if (offset > 0x40) {
- printf("Wrong offset : 0x%x\n",offset);
- return cmd_usage(cmdtp);
- }
- dm9000_write_srom_word(offset, value);
- return (0);
-}
-
-int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if (strcmp (argv[1],"read") == 0)
- return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
- else if (strcmp (argv[1],"write") == 0)
- return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
- else
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- dm9000ee,4,1,do_dm9000_eeprom,
- "Read/Write eeprom connected to Ethernet Controller",
- "\ndm9000ee write <word offset> <value> \n"
- "\tdm9000ee read \n"
- "\tword:\t\t00-02 : MAC Address\n"
- "\t\t\t03-07 : DM9000 Configuration\n"
- "\t\t\t08-63 : User data"
-);
diff --git a/configs/polaris_defconfig b/configs/polaris_defconfig
deleted file mode 100644
index e209566..0000000
--- a/configs/polaris_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TRIZEPSIV=y
-CONFIG_SYS_EXTRA_OPTIONS="POLARIS"
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/trizepsiv_defconfig b/configs/trizepsiv_defconfig
deleted file mode 100644
index 1887983..0000000
--- a/configs/trizepsiv_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TRIZEPSIV=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
deleted file mode 100644
index 40c8d71..0000000
--- a/include/configs/trizepsiv.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic at denx.de
- *
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the LUBBOCK board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
-
-#define CONFIG_MMC 1
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define RTC
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
-#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
-#define CONFIG_STUART 1 /* we use STUART on Conxs */
-#define CONFIG_CONS_INDEX 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_SERVERIP 192.168.1.99
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
- " rw root=/dev/ram initrd=0xa0800000,5m"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "program_boot_mmc=" \
- "mw.b 0xa0010000 0xff 0x20000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x1ffff; " \
- "erase 0x0 0x1ffff; " \
- "cp.b 0xa0010000 0x0 0x20000; " \
- "fi\0" \
- "program_uzImage_mmc=" \
- "mw.b 0xa0010000 0xff 0x180000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 uzImage; " \
- "then " \
- "protect off 0x40000 0x1bffff; " \
- "erase 0x40000 0x1bffff; " \
- "cp.b 0xa0010000 0x40000 0x180000; " \
- "fi\0" \
- "program_ramdisk_mmc=" \
- "mw.b 0xa0010000 0xff 0x500000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 ramdisk.gz; " \
- "then " \
- "protect off 0x1c0000 0x6bffff; " \
- "erase 0x1c0000 0x6bffff; " \
- "cp.b 0xa0010000 0x1c0000 0x500000; " \
- "fi\0" \
- "boot_mmc=" \
- "if mmcinit && " \
- "fatload mmc 0 0xa0030000 uzImage && " \
- "fatload mmc 0 0xa0800000 ramdisk.gz; " \
- "then " \
- "bootm 0xa0030000; " \
- "fi\0" \
- "boot_flash=" \
- "cp.b 0x1c0000 0xa0800000 0x500000; " \
- "bootm 0x40000\0" \
-
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-/* #define CONFIG_INITRD_TAG 1 */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
-
-#ifdef CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x00018000
-#define CONFIG_SYS_GPSR1_VAL 0x00000000
-#define CONFIG_SYS_GPSR2_VAL 0x400dc000
-#define CONFIG_SYS_GPSR3_VAL 0x00000000
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0x00018000
-#define CONFIG_SYS_GPDR1_VAL 0x00028801
-#define CONFIG_SYS_GPDR2_VAL 0x520dc000
-#define CONFIG_SYS_GPDR3_VAL 0x0001E000
-#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
-#define CONFIG_SYS_GAFR0_U_VAL 0x00000013
-#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000003
-#define CONFIG_SYS_GAFR3_U_VAL 0x00002401
-#define CONFIG_SYS_GRER0_VAL 0x00000000
-#define CONFIG_SYS_GRER1_VAL 0x00000000
-#define CONFIG_SYS_GRER2_VAL 0x00000000
-#define CONFIG_SYS_GRER3_VAL 0x00000000
-
-#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER3_VAL 0x00000020
-
-#if CONFIG_POLARIS
-#define CONFIG_SYS_GFER0_VAL 0x00000001
-#define CONFIG_SYS_GFER2_VAL 0x00200000
-#else
-#define CONFIG_SYS_GFER0_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
-#endif
-
-#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
-#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
-
-/*
- * Memory settings
- */
-
-#define CONFIG_SYS_MSC0_VAL 0x4df84df0
-#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
-#if CONFIG_POLARIS
-#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
-#else
-#define CONFIG_SYS_MSC2_VAL 0xa26936d4
-#endif
-#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
-#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00004204
-#define CONFIG_SYS_MCMEM1_VAL 0x00010204
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00008407
-#define CONFIG_SYS_MCIO1_VAL 0x0000c108
-
-#define CONFIG_DRIVER_DM9000 1
-
-#if CONFIG_POLARIS
-#define CONFIG_DM9000_BASE 0x0C800000
-#else
-#define CONFIG_DM9000_BASE 0x08000000
-#endif
-
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
-
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-
-/*
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* write flash less slowly */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/* Unlock to be used with Intel chips */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-/* Flash environment locations */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 29/45] arm: Remove portuxg20, stamp9g20 boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (27 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 30/45] arm: Remove pxa255_idp, zipitz2 boards Simon Glass
` (16 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 5 -
board/taskit/stamp9g20/Kconfig | 12 --
board/taskit/stamp9g20/MAINTAINERS | 7 --
board/taskit/stamp9g20/Makefile | 17 ---
board/taskit/stamp9g20/led.c | 122 -------------------
board/taskit/stamp9g20/stamp9g20.c | 159 ------------------------
configs/portuxg20_defconfig | 10 --
configs/stamp9g20_defconfig | 11 --
include/configs/stamp9g20.h | 244 -------------------------------------
9 files changed, 587 deletions(-)
delete mode 100644 board/taskit/stamp9g20/Kconfig
delete mode 100644 board/taskit/stamp9g20/MAINTAINERS
delete mode 100644 board/taskit/stamp9g20/Makefile
delete mode 100644 board/taskit/stamp9g20/led.c
delete mode 100644 board/taskit/stamp9g20/stamp9g20.c
delete mode 100644 configs/portuxg20_defconfig
delete mode 100644 configs/stamp9g20_defconfig
delete mode 100644 include/configs/stamp9g20.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index f70ccbc..ba1b4f4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -43,10 +43,6 @@ config TARGET_PM9263
bool "Ronetix pm9263 board"
select CPU_ARM926EJS
-config TARGET_STAMP9G20
- bool "Support stamp9g20"
- select CPU_ARM926EJS
-
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select CPU_ARM926EJS
@@ -142,6 +138,5 @@ source "board/ronetix/pm9g45/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
-source "board/taskit/stamp9g20/Kconfig"
endif
diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig
deleted file mode 100644
index 1121dac..0000000
--- a/board/taskit/stamp9g20/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_STAMP9G20
-
-config SYS_BOARD
- default "stamp9g20"
-
-config SYS_VENDOR
- default "taskit"
-
-config SYS_CONFIG_NAME
- default "stamp9g20"
-
-endif
diff --git a/board/taskit/stamp9g20/MAINTAINERS b/board/taskit/stamp9g20/MAINTAINERS
deleted file mode 100644
index a91c196..0000000
--- a/board/taskit/stamp9g20/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-STAMP9G20 BOARD
-M: Markus Hubig <mhubig@imko.de>
-S: Maintained
-F: board/taskit/stamp9g20/
-F: include/configs/stamp9g20.h
-F: configs/portuxg20_defconfig
-F: configs/stamp9g20_defconfig
diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile
deleted file mode 100644
index d015e0f..0000000
--- a/board/taskit/stamp9g20/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# (C) Copyright 2012
-# Markus Hubig <mhubig@imko.de>
-# IMKO GmbH <www.imko.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += stamp9g20.o
-obj-y += led.o
diff --git a/board/taskit/stamp9g20/led.c b/board/taskit/stamp9g20/led.c
deleted file mode 100644
index c583125..0000000
--- a/board/taskit/stamp9g20/led.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * (C) Copyright 2012
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pmc.h>
-#include <status_led.h>
-
-static unsigned int saved_state[3] = {STATUS_LED_OFF,
- STATUS_LED_OFF, STATUS_LED_OFF};
-
-void coloured_LED_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable the clock */
- writel(ATMEL_ID_PIOC, &pmc->pcer);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
-}
-
-void red_led_on(void)
-{
- at91_set_gpio_value(CONFIG_RED_LED, 1);
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void red_led_off(void)
-{
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void green_led_on(void)
-{
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
-}
-
-void green_led_off(void)
-{
- at91_set_gpio_value(CONFIG_GREEN_LED, 0);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
-}
-
-void yellow_led_on(void)
-{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
-}
-
-void yellow_led_off(void)
-{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
-
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
- green_led_off();
- else
- green_led_on();
-
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
- yellow_led_off();
- else
- yellow_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
-
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
- green_led_on();
- else
- green_led_off();
-
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == state)
- yellow_led_on();
- else
- yellow_led_off();
- }
-}
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
deleted file mode 100644
index 27cdf77..0000000
--- a/board/taskit/stamp9g20/stamp9g20.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * Achim Ehrlich <aehrlich@taskit.de>
- * taskit GmbH <www.taskit.de>
- *
- * (C) Copyright 2012-
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_MACB
-# include <net.h>
-# include <netdev.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void stamp9G20_nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Assign CS3 to NAND/SmartMedia Interface */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
-
- /* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-
-#ifdef CONFIG_MACB
-static void stamp9G20_macb_hw_init(void)
-{
- struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
- /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
- at91_set_gpio_output(AT91_PIN_PA26, 0);
-
- /*
- * Disable pull-up on:
- * RXDV (PA17) => PHY normal mode (not Test mode)
- * ERX0 (PA14) => PHY ADDR0
- * ERX1 (PA15) => PHY ADDR1
- * ERX2 (PA25) => PHY ADDR2
- * ERX3 (PA26) => PHY ADDR3
- * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
- *
- * PHY has internal pull-down
- */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA18) |
- pin_to_mask(AT91_PIN_PA28),
- &pioa->pudr);
-
- at91_phy_reset();
-
- /* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA18) |
- pin_to_mask(AT91_PIN_PA28),
- &pioa->puer);
-
- /* Initialize EMAC=MACB hardware */
- at91_macb_hw_init();
-}
-#endif /* CONFIG_MACB */
-
-int board_early_init_f(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC), &pmc->pcer);
-
- return 0;
-}
-
-int board_postclk_init(void)
-{
- /*
- * Initialize the serial interface here, because be need a running
- * timer to set PC9 to high and wait for some time to enable the
- * level converter of the RS232 interface on the PortuxG20 board.
- */
-
-#ifdef CONFIG_PORTUXG20
- at91_set_gpio_output(AT91_PIN_PC9, 1);
- mdelay(1);
-#endif
- at91_seriald_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- stamp9G20_nand_hw_init();
-#ifdef CONFIG_MACB
- stamp9G20_macb_hw_init();
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_MACB
-int board_eth_init(bd_t *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
-}
-#endif /* CONFIG_MACB */
diff --git a/configs/portuxg20_defconfig b/configs/portuxg20_defconfig
deleted file mode 100644
index 1e8344f..0000000
--- a/configs/portuxg20_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_STAMP9G20=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20"
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/stamp9g20_defconfig b/configs/stamp9g20_defconfig
deleted file mode 100644
index 40d6232..0000000
--- a/configs/stamp9g20_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_STAMP9G20=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
deleted file mode 100644
index 87df70b..0000000
--- a/include/configs/stamp9g20.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Achim Ehrlich <aehrlich@taskit.de>
- * taskit GmbH <www.taskit.de>
- *
- * (C) Copyright 2012
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * Configuation settings for the stamp9g20 CPU module.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
- * program. Since the linker has to swallow that define, we must use a pure
- * hex number here!
- */
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
-
-/* misc settings */
-#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
-#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */
-#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */
-#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
-
-/* setting board specific options */
-#ifdef CONFIG_PORTUXG20
-# define CONFIG_MACH_TYPE MACH_TYPE_PORTUXG20
-# define CONFIG_MACB
-#else
-# define CONFIG_MACH_TYPE MACH_TYPE_STAMP9G20
-#endif
-
-/*
- * SDRAM: 1 bank, 64 MB, base address 0x20000000
- * Already initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 << 20)
-
-/*
- * Perform a SDRAM Memtest from the start of SDRAM
- * till the beginning of the U-Boot position in RAM.
- */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
-
-/*
- * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above that
- * address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-/* NAND flash settings */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO /* enable the GPIO features */
-#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-/* LED configuration */
-#define CONFIG_STATUS_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-
-/* The LED PINs */
-#define CONFIG_RED_LED AT91_PIN_PC5
-#define CONFIG_GREEN_LED AT91_PIN_PC4
-#define CONFIG_YELLOW_LED AT91_PIN_PC10
-
-#define STATUS_LED_RED 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_YELLOW 2
-
-/* Red LED */
-#define STATUS_LED_BIT STATUS_LED_RED
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-
-/* Green LED */
-#define STATUS_LED_BIT1 STATUS_LED_GREEN
-#define STATUS_LED_STATE1 STATUS_LED_ON
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-
-/* Yellow LED */
-#define STATUS_LED_BIT2 STATUS_LED_YELLOW
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
-
-/* Boot status LED */
-#define STATUS_LED_BOOT STATUS_LED_GREEN
-
-/*
- * Ethernet configuration
- *
- * PortuxG20 has always ethernet but for Stamp9G20 you
- * can enable it here if your baseboard features ethernet.
- */
-
-#define CONFIG_MACB
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-
-#ifdef CONFIG_MACB
-# define CONFIG_RMII /* use reduced MII inteface */
-# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-/* BOOTP and DHCP options */
-# define CONFIG_BOOTP_BOOTFILESIZE
-# define CONFIG_BOOTP_BOOTPATH
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_HOSTNAME
-# define CONFIG_NFSBOOTCOMMAND \
- "setenv autoload yes; setenv autoboot yes; " \
- "setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
- "dhcp"
-#endif /* CONFIG_MACB */
-
-/* Enable the watchdog */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
-/* USB configuration */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
-/* General Boot Parameter */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * RAM Memory address where to put the
- * Linux Kernel befor starting.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
-/*
- * The NAND Flash partitions:
- * ==========================================
- * 0x0000000-0x001ffff -> 128k, bootstrap
- * 0x0020000-0x005ffff -> 256k, u-boot
- * 0x0060000-0x007ffff -> 128k, env1
- * 0x0080000-0x009ffff -> 128k, env2 (backup)
- * 0x0100000-0x06fffff -> 6M, kernel
- * 0x0700000-0x8000000 -> 121M, RootFS
- */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET ((128 + 256) << 10)
-#define CONFIG_ENV_OFFSET_REDUND ((128 + 256 + 128) << 10)
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/*
- * Predefined environment variables.
- * Usefull to define some easy to use boot commands.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- \
- "basicargs=console=ttyS0,115200\0" \
- \
- "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \
- "256k(uboot)ro,128k(env1)ro," \
- "128k(env2)ro,6M(linux),-(root)rw\0" \
- \
- "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/mtdblock5 rootfstype=jffs2; " \
- "nand read 0x22000000 0x100000 0x600000; " \
- "bootm 22000000\0" \
- \
- "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/mmcblk0p1 rootwait; " \
- "nand read 0x22000000 0x100000 0x600000; " \
- "bootm 22000000"
-
-/* Command line & features configuration */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_LED
-
-#ifdef CONFIG_MACB
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-#endif /* CONFIG_MACB */
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 30/45] arm: Remove pxa255_idp, zipitz2 boards
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (28 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 29/45] arm: Remove portuxg20, stamp9g20 boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,30/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 31/45] arm: Remove qong board Simon Glass
` (15 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
These boards have not been converted to generic board by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 10 --
board/pxa255_idp/Kconfig | 9 -
board/pxa255_idp/MAINTAINERS | 6 -
board/pxa255_idp/Makefile | 8 -
board/pxa255_idp/README | 11 --
board/pxa255_idp/idp_notes.txt | 46 -----
board/pxa255_idp/pxa_idp.c | 140 ----------------
board/pxa255_idp/pxa_reg_calcs.out | 119 -------------
board/pxa255_idp/pxa_reg_calcs.py | 298 ---------------------------------
board/zipitz2/Kconfig | 9 -
board/zipitz2/MAINTAINERS | 6 -
board/zipitz2/Makefile | 10 --
board/zipitz2/zipitz2.c | 202 ----------------------
configs/pxa255_idp_defconfig | 3 -
configs/zipitz2_defconfig | 7 -
include/configs/pxa255_idp.h | 335 -------------------------------------
include/configs/zipitz2.h | 238 --------------------------
17 files changed, 1457 deletions(-)
delete mode 100644 board/pxa255_idp/Kconfig
delete mode 100644 board/pxa255_idp/MAINTAINERS
delete mode 100644 board/pxa255_idp/Makefile
delete mode 100644 board/pxa255_idp/README
delete mode 100644 board/pxa255_idp/idp_notes.txt
delete mode 100644 board/pxa255_idp/pxa_idp.c
delete mode 100644 board/pxa255_idp/pxa_reg_calcs.out
delete mode 100644 board/pxa255_idp/pxa_reg_calcs.py
delete mode 100644 board/zipitz2/Kconfig
delete mode 100644 board/zipitz2/MAINTAINERS
delete mode 100644 board/zipitz2/Makefile
delete mode 100644 board/zipitz2/zipitz2.c
delete mode 100644 configs/pxa255_idp_defconfig
delete mode 100644 configs/zipitz2_defconfig
delete mode 100644 include/configs/pxa255_idp.h
delete mode 100644 include/configs/zipitz2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93f5c89..511535c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -729,10 +729,6 @@ config TARGET_PALMTREO680
select CPU_PXA
select SUPPORT_SPL
-config TARGET_PXA255_IDP
- bool "Support pxa255_idp"
- select CPU_PXA
-
config TARGET_VPAC270
bool "Support vpac270"
select CPU_PXA
@@ -742,10 +738,6 @@ config TARGET_XAENIAX
bool "Support xaeniax"
select CPU_PXA
-config TARGET_ZIPITZ2
- bool "Support zipitz2"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@@ -885,7 +877,6 @@ source "board/olimex/mx23_olinuxino/Kconfig"
source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
-source "board/pxa255_idp/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
@@ -922,7 +913,6 @@ source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
-source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig
deleted file mode 100644
index 5448311..0000000
--- a/board/pxa255_idp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PXA255_IDP
-
-config SYS_BOARD
- default "pxa255_idp"
-
-config SYS_CONFIG_NAME
- default "pxa255_idp"
-
-endif
diff --git a/board/pxa255_idp/MAINTAINERS b/board/pxa255_idp/MAINTAINERS
deleted file mode 100644
index 24d7236..0000000
--- a/board/pxa255_idp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PXA255_IDP BOARD
-M: Cliff Brake <cliff.brake@gmail.com>
-S: Maintained
-F: board/pxa255_idp/
-F: include/configs/pxa255_idp.h
-F: configs/pxa255_idp_defconfig
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
deleted file mode 100644
index 59d6967..0000000
--- a/board/pxa255_idp/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pxa_idp.o
diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README
deleted file mode 100644
index 0cc2f2a..0000000
--- a/board/pxa255_idp/README
+++ /dev/null
@@ -1,11 +0,0 @@
-Tested:
-
-- MMC
-- Ethernet
-- BL console (on serial port connector J5)
-- flash support
-
-Todo:
-
-- display support
-- PCMCIA support
diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt
deleted file mode 100644
index 4746748..0000000
--- a/board/pxa255_idp/idp_notes.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Notes on the Vibren PXA255 IDP.
-
-Chip select usage:
-
-CS0 - flash
-CS1 - alt flash (Mdoc or main flash)
-CS2 - high speed expansion bus
-CS3 - Media Q, low speed exp bus
-CS4 - low speed exp bus
-CS5 - low speed exp bus
- - IDE: offset 0x03000000 (abs: 0x17000000)
- - Eth: offset 0x03400000 (abs: 0x17400000)
- - core voltage latch: offset 0x03800000 (abs: 0x17800000)
- - CPLD: offset 0x03C00000 (abs: 0x17C00000)
-
-PCMCIA Power control
-
-MAX1602EE w/ code pulled high (Cirrus code)
-vx = 5v
-vy = 3v
-
- Bit pattern
- PWR 3,2,1,0
-vcc vpp A1VCC A0VCC A1VPP A0VPP
-=====================================================
-0 0 0 0 0 0 0x0
-3 (vy) 0 1 0 1 1 0xB
-3 (vy) 3 (vy) 1 0 0 1 0x9
-3 (vy) 12(12in) 1 0 1 0 0xA
-5 (vx) 0 0 1 1 1 0x7
-5 (vx) 5 (vx) 0 1 0 1 0x5
-5 (vx 12(12in) 0 1 1 0 0x6
-
-Display power sequencing:
-
-- VDD applied
-- within 1sec, activate scanning signals
-- wait at least 50mS - scanning signals must be active before activating DISP
-
-Signal mapping:
-Schematic LV8V31 signal name
-=========================================
-LCD_ENAVLCD DISP
-LCD_PWR Applies VDD to board
-
-Both of the above signals are controlled by the CPLD
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
deleted file mode 100644
index 197ff3e..0000000
--- a/board/pxa255_idp/pxa_idp.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Support for Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of Lubbock-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* turn on serial ports */
- *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
-
- /* set PWM for LCD */
- /* a value that works is 60Hz, 77% duty cycle */
- writel(readl(CKEN) | CKEN0_PWM0, CKEN);
- writel(0x3f, PWM_CTRL0);
- writel(0x3ff, PWM_PERVAL0);
- writel(792, PWM_PWDUTY0);
-
- /* clear reset to AC97 codec */
- writel(readl(CKEN) | CKEN2_AC97, CKEN);
- writel(GCR_COLD_RST, GCR);
-
- /* enable LCD backlight */
- /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
-
- /* test display */
- /* lcd_puts("This is a test\nTest #2\n"); */
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-int board_late_init(void)
-{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef DEBUG_BLINKC_ENABLE
-
-void delay_c(void)
-{
- /* reset OSCR to 0 */
- writel(0, OSCR);
- while (readl(OSCR) > 0x10000)
- ;
-
- while (readl(OSCR) < 0xd4000)
- ;
-}
-
-void blink_c(void)
-{
- int led_bit = (1<<10);
-
- writel(led_bit, GPDR0);
- writel(led_bit, GPCR0);
- delay_c();
- writel(led_bit, GPSR0);
- delay_c();
- writel(led_bit, GPCR0);
-}
-
-int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("IDPCMD started\n");
- return 0;
-}
-
-U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
- "custom IDP command",
- "no args@this time"
-);
-
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out
deleted file mode 100644
index 39295fb..0000000
--- a/board/pxa255_idp/pxa_reg_calcs.out
+++ /dev/null
@@ -1,119 +0,0 @@
-gafr0_l: 0x80001005
-gafr0_u: 0xa5128012
-gafr1_l: 0x699a9558
-gafr1_u: 0xaaa5aa6a
-gafr2_l: 0xaaaaaaaa
-gafr2_u: 0x2
-gpcr0: 0x1800400
-gpcr1: 0x0
-gpcr2: 0x0
-gpdr0: 0xc1818440
-gpdr1: 0xfcffab82
-gpdr2: 0x1ffff
-gpsr0: 0x8000
-gpsr1: 0x3f0002
-gpsr2: 0x1c000
-
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x2
-#define CONFIG_SYS_GPCR0_VAL 0x1800400
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xc1818440
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL 0x1ffff
-#define CONFIG_SYS_GPSR0_VAL 0x8000
-#define CONFIG_SYS_GPSR1_VAL 0x3f0002
-#define CONFIG_SYS_GPSR2_VAL 0x1c000
-
-
-GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
-GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
-GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
-GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
-GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
-GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
-GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
-GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
-GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
-GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
-GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
-GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
-GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
-GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
-GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
-GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
-GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
-GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
-GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
-GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
-GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
-GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
-GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
-GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
-GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
-GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
-GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
-GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
-GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
-GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
-GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
-GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
-GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
-GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
-GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
-GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
-GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
-GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
-GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
-GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
-GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
-GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
-GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
-GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
-GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
-GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
-GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
-GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
-GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
-GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
-GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
-GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
-GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
-GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
-GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
-GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
-GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
-GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
-GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
-GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
-GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
-GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
-GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
-GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
-GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
-GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
-GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
-GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
-GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
-GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
-GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
-GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
-GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
-GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
-GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
-GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
-GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
-GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
-GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
-GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
-GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
-GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py
deleted file mode 100644
index 4a721d1..0000000
--- a/board/pxa255_idp/pxa_reg_calcs.py
+++ /dev/null
@@ -1,298 +0,0 @@
-#!/usr/bin/python
-
-# (C) Copyright 2004
-# BEC Systems <http://bec-systems.com>
-# Cliff Brake <cliff.brake@gmail.com>
-
-# SPDX-License-Identifier: GPL-2.0+
-
-# calculations for PXA255 registers
-
-class gpio:
- dir = '0'
- set = '0'
- clr = '0'
- alt = '0'
- desc = ''
-
- def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
- self.dir = dir
- self.set = set
- self.clr = clr
- self.alt = alt
- self.desc = desc
-
-
-# the following is a dictionary of all GPIOs in the system
-# the key is the GPIO number
-
-
-pxa255_alt_func = {
- 0: ['gpio', 'none', 'none', 'none'],
- 1: ['gpio', 'gpio reset', 'none', 'none'],
- 2: ['gpio', 'none', 'none', 'none'],
- 3: ['gpio', 'none', 'none', 'none'],
- 4: ['gpio', 'none', 'none', 'none'],
- 5: ['gpio', 'none', 'none', 'none'],
- 6: ['gpio', 'MMC clk', 'none', 'none'],
- 7: ['gpio', '48MHz clock', 'none', 'none'],
- 8: ['gpio', 'MMC CS0', 'none', 'none'],
- 9: ['gpio', 'MMC CS1', 'none', 'none'],
- 10: ['gpio', 'RTC Clock', 'none', 'none'],
- 11: ['gpio', '3.6MHz', 'none', 'none'],
- 12: ['gpio', '32KHz', 'none', 'none'],
- 13: ['gpio', 'none', 'MBGNT', 'none'],
- 14: ['gpio', 'MBREQ', 'none', 'none'],
- 15: ['gpio', 'none', 'nCS_1', 'none'],
- 16: ['gpio', 'none', 'PWM0', 'none'],
- 17: ['gpio', 'none', 'PWM1', 'none'],
- 18: ['gpio', 'RDY', 'none', 'none'],
- 19: ['gpio', 'DREQ[1]', 'none', 'none'],
- 20: ['gpio', 'DREQ[0]', 'none', 'none'],
- 21: ['gpio', 'none', 'none', 'none'],
- 22: ['gpio', 'none', 'none', 'none'],
- 23: ['gpio', 'none', 'SSP SCLK', 'none'],
- 24: ['gpio', 'none', 'SSP SFRM', 'none'],
- 25: ['gpio', 'none', 'SSP TXD', 'none'],
- 26: ['gpio', 'SSP RXD', 'none', 'none'],
- 27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
- 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
- 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
- 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
- 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
- 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
- 33: ['gpio', 'none', 'nCS_5', 'none'],
- 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
- 35: ['gpio', 'FF CTS', 'none', 'none'],
- 36: ['gpio', 'FF DCD', 'none', 'none'],
- 37: ['gpio', 'FF DSR', 'none', 'none'],
- 38: ['gpio', 'FF RI', 'none', 'none'],
- 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
- 40: ['gpio', 'none', 'FF DTR', 'none'],
- 41: ['gpio', 'none', 'FF RTS', 'none'],
- 42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
- 43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
- 44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
- 45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
- 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
- 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
- 48: ['gpio', 'HW TXD', 'nPOE', 'none'],
- 49: ['gpio', 'HW RXD', 'nPWE', 'none'],
- 50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
- 51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
- 52: ['gpio', 'none', 'nPCE[1]', 'none'],
- 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
- 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
- 55: ['gpio', 'none', 'nPREG', 'none'],
- 56: ['gpio', 'nPWAIT', 'none', 'none'],
- 57: ['gpio', 'nIOIS16', 'none', 'none'],
- 58: ['gpio', 'none', 'LDD[0]', 'none'],
- 59: ['gpio', 'none', 'LDD[1]', 'none'],
- 60: ['gpio', 'none', 'LDD[2]', 'none'],
- 61: ['gpio', 'none', 'LDD[3]', 'none'],
- 62: ['gpio', 'none', 'LDD[4]', 'none'],
- 63: ['gpio', 'none', 'LDD[5]', 'none'],
- 64: ['gpio', 'none', 'LDD[6]', 'none'],
- 65: ['gpio', 'none', 'LDD[7]', 'none'],
- 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
- 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
- 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
- 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
- 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
- 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
- 72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
- 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
- 74: ['gpio', 'none', 'LCD_FCLK', 'none'],
- 75: ['gpio', 'none', 'LCD_LCLK', 'none'],
- 76: ['gpio', 'none', 'LCD_PCLK', 'none'],
- 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
- 78: ['gpio', 'none', 'nCS_2', 'none'],
- 79: ['gpio', 'none', 'nCS_3', 'none'],
- 80: ['gpio', 'none', 'nCS_4', 'none'],
- 81: ['gpio', 'NSSPSCLK', 'none', 'none'],
- 82: ['gpio', 'NSSPSFRM', 'none', 'none'],
- 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
- 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
-}
-
-
-#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
-
-gpio_list = []
-
-for i in range(0,85):
- gpio_list.append(gpio())
-
-#chip select GPIOs
-gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
-gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
-gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
-gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
-gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
-gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
-gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
-gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
-gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
-gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
-
-# PCMCIA stuff
-gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
-gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
-gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
-gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
-gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
-gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
-gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
-gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
-gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
-gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
-
-# SSP port
-gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
-gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
-gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
-gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
-gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
-
-# audio codec
-gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
-gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
-gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
-gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
-gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
-
-# serial ports
-gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
-gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
-gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
-gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
-gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
-gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
-gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
-gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
-
-gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
-gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
-gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
-gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
-
-gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
-gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
-
-# misc GPIO signals
-gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
-gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
-gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
-gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
-gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
-gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
-gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
-gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
-gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
-gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
-gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
-gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
-gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
-gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
-gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
-
-# LCD GPIOs
-gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
-gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
-gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
-gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
-gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
-gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
-gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
-gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
-gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
-gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
-gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
-gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
-gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
-gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
-gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
-gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
-gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
-gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
-gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
-gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
-
-# calculate registers
-pxa_regs = {
- 'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
- 'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
- 'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
- 'gafr0_l':0, 'gafr0_u':0,
- 'gafr1_l':0, 'gafr1_u':0,
- 'gafr2_l':0, 'gafr2_u':0,
-}
-
-# U-boot define names
-uboot_reg_names = {
- 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
- 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
- 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
- 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
- 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
- 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
-}
-
-# bit mappings
-
-bit_mappings = [
-
-{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
-{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
-{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
-{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
-{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
-{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
-{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
-{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
-{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
-
-]
-
-def stuff_bits(bit_mapping, gpio_list):
- gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
-
- for gpio in gpios:
- for reg in bit_mapping['regs'].keys():
- value = eval( 'gpio_list[gpio].%s' % (reg) )
- if ( value ):
- # we have a high bit
- bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
- bit = value << (bit_shift)
- pxa_regs[bit_mapping['regs'][reg]] |= bit
-
-for i in bit_mappings:
- stuff_bits(i, gpio_list)
-
-# now print out all regs
-registers = pxa_regs.keys()
-registers.sort()
-for reg in registers:
- print '%s: 0x%x' % (reg, pxa_regs[reg])
-
-# print define to past right into U-Boot source code
-
-print
-print
-
-for reg in registers:
- print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
-
-# print all GPIOS
-print
-print
-
-for i in range(len(gpio_list)):
- gpio_i = gpio_list[i]
- alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
- print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
-
-
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
deleted file mode 100644
index c663504..0000000
--- a/board/zipitz2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ZIPITZ2
-
-config SYS_BOARD
- default "zipitz2"
-
-config SYS_CONFIG_NAME
- default "zipitz2"
-
-endif
diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS
deleted file mode 100644
index 55b0f64..0000000
--- a/board/zipitz2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ZIPITZ2 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/zipitz2/
-F: include/configs/zipitz2.h
-F: configs/zipitz2_defconfig
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
deleted file mode 100644
index 855f6bc..0000000
--- a/board/zipitz2/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (C) 2009
-# Marek Vasut <marek.vasut@gmail.com>
-#
-# Heavily based on pxa255_idp platform
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := zipitz2.o
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
deleted file mode 100644
index 90bba6a..0000000
--- a/board/zipitz2/zipitz2.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2009
- * Marek Vasut <marek.vasut@gmail.com>
- *
- * Heavily based on pxa255_idp platform
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <spi.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_SPI
-void lcd_start(void);
-#else
-inline void lcd_start(void) {};
-#endif
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of Z2 */
- gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Enable LCD */
- lcd_start();
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_SPI
-
-struct {
- unsigned char reg;
- unsigned short data;
- unsigned char mdelay;
-} lcd_data[] = {
- { 0x07, 0x0000, 0 },
- { 0x13, 0x0000, 10 },
- { 0x11, 0x3004, 0 },
- { 0x14, 0x200F, 0 },
- { 0x10, 0x1a20, 0 },
- { 0x13, 0x0040, 50 },
- { 0x13, 0x0060, 0 },
- { 0x13, 0x0070, 200 },
- { 0x01, 0x0127, 0 },
- { 0x02, 0x0700, 0 },
- { 0x03, 0x1030, 0 },
- { 0x08, 0x0208, 0 },
- { 0x0B, 0x0620, 0 },
- { 0x0C, 0x0110, 0 },
- { 0x30, 0x0120, 0 },
- { 0x31, 0x0127, 0 },
- { 0x32, 0x0000, 0 },
- { 0x33, 0x0503, 0 },
- { 0x34, 0x0727, 0 },
- { 0x35, 0x0124, 0 },
- { 0x36, 0x0706, 0 },
- { 0x37, 0x0701, 0 },
- { 0x38, 0x0F00, 0 },
- { 0x39, 0x0F00, 0 },
- { 0x40, 0x0000, 0 },
- { 0x41, 0x0000, 0 },
- { 0x42, 0x013f, 0 },
- { 0x43, 0x0000, 0 },
- { 0x44, 0x013f, 0 },
- { 0x45, 0x0000, 0 },
- { 0x46, 0xef00, 0 },
- { 0x47, 0x013f, 0 },
- { 0x48, 0x0000, 0 },
- { 0x07, 0x0015, 30 },
- { 0x07, 0x0017, 0 },
- { 0x20, 0x0000, 0 },
- { 0x21, 0x0000, 0 },
- { 0x22, 0x0000, 0 },
-};
-
-void zipitz2_spi_sda(int set)
-{
- /* GPIO 13 */
- if (set)
- writel((1 << 13), GPSR0);
- else
- writel((1 << 13), GPCR0);
-}
-
-void zipitz2_spi_scl(int set)
-{
- /* GPIO 22 */
- if (set)
- writel((1 << 22), GPCR0);
- else
- writel((1 << 22), GPSR0);
-}
-
-unsigned char zipitz2_spi_read(void)
-{
- /* GPIO 40 */
- return !!(readl(GPLR1) & (1 << 8));
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* Always valid */
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* GPIO 88 low */
- writel((1 << 24), GPCR2);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* GPIO 88 high */
- writel((1 << 24), GPSR2);
-
-}
-
-void lcd_start(void)
-{
- int i;
- unsigned char reg[3] = { 0x74, 0x00, 0 };
- unsigned char data[3] = { 0x76, 0, 0 };
- unsigned char dummy[3] = { 0, 0, 0 };
-
- /* PWM2 AF */
- writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
- /* Enable clock to all PWM */
- writel(readl(CKEN) | 0x3, CKEN);
- /* Configure PWM2 */
- writel(0x4f, PWM_CTRL2);
- writel(0x2ff, PWM_PWDUTY2);
- writel(792, PWM_PERVAL2);
-
- /* Toggle the reset pin to reset the LCD */
- writel((1 << 19), GPSR0);
- udelay(100000);
- writel((1 << 19), GPCR0);
- udelay(20000);
- writel((1 << 19), GPSR0);
- udelay(20000);
-
- /* Program the LCD init sequence */
- for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
- reg[0] = 0x74;
- reg[1] = 0x0;
- reg[2] = lcd_data[i].reg;
- spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
- data[0] = 0x76;
- data[1] = lcd_data[i].data >> 8;
- data[2] = lcd_data[i].data & 0xff;
- spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (lcd_data[i].mdelay)
- udelay(lcd_data[i].mdelay * 1000);
- }
-
- writel((1 << 11), GPSR0);
-}
-#endif
diff --git a/configs/pxa255_idp_defconfig b/configs/pxa255_idp_defconfig
deleted file mode 100644
index c7be4e9..0000000
--- a/configs/pxa255_idp_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_PXA255_IDP=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
deleted file mode 100644
index 2977ccc..0000000
--- a/configs/zipitz2_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_ZIPITZ2=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
deleted file mode 100644
index 332d79f..0000000
--- a/include/configs/pxa255_idp.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copied from lubbock.h
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Configuation settings for the Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/pxa-regs.h>
-
-/*
- * If we are developing, we might want to start U-Boot from RAM
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-/*
- * define the following to enable debug blinks. A debug blink function
- * must be defined in memsetup.S
- */
-#undef DEBUG_BLINK_ENABLE
-#undef DEBUG_BLINKC_ENABLE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
-
-#undef CONFIG_LCD
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-
-#define CONFIG_MMC 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_BOARD_LATE_INIT
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * PXA250 IDP memory map information
- */
-
-#define IDP_CS5_ETH_OFFSET 0x03400000
-
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
-#define CONFIG_SMC_USE_32_BIT 1
-/* #define CONFIG_SMC_USE_IOFUNCS */
-
-/* the following has to be set high -- suspect something is wrong with
- * with the tftp timeout routines. FIXME!!!
- */
-#define CONFIG_NET_RETRY_COUNT 100
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
-#define CONFIG_CONS_INDEX 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-/* #define CONFIG_INITRD_TAG 1 */
-
-/*
- * Current memory map for Vibren supplied Linux images:
- *
- * Flash:
- * 0 - 0x3ffff (size = 0x40000): bootloader
- * 0x40000 - 0x13ffff (size = 0x100000): kernel
- * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
- *
- * RAM:
- * 0xa0008000 - kernel is loaded
- * 0xa3000000 - Uboot runs (48MB into RAM)
- *
- */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "prog_boot_mmc=" \
- "mw.b 0xa0000000 0xff 0x40000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x3ffff; " \
- "erase 0x0 0x3ffff; " \
- "cp.b 0xa0000000 0x0 0x40000; " \
- "reset;" \
- "fi\0" \
- "prog_uzImage_mmc=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 uzImage; " \
- "then " \
- "protect off 0x40000 0xfffff; " \
- "erase 0x40000 0xfffff; " \
- "cp.b 0xa0000000 0x40000 0x100000; " \
- "fi\0" \
- "prog_jffs_mmc=" \
- "mw.b 0xa0000000 0xff 0x1e00000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 root.jffs; " \
- "then " \
- "protect off 0x140000 0x1f3ffff; " \
- "erase 0x140000 0x1f3ffff; " \
- "cp.b 0xa0000000 0x140000 0x1e00000; " \
- "fi\0" \
- "boot_mmc=" \
- "if mmcinit && " \
- "fatload mmc 0 0xa1000000 uzImage && " \
- "then " \
- "bootm 0xa1000000; " \
- "fi\0" \
- "prog_boot_net=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if bootp 0xa0000000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x3ffff; " \
- "erase 0x0 0x3ffff; " \
- "cp.b 0xa0000000 0x0 0x40000; " \
- "reset; " \
- "fi\0" \
- "prog_uzImage_net=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if bootp 0xa0000000 uzImage; " \
- "then " \
- "protect off 0x40000 0xfffff; " \
- "erase 0x40000 0xfffff; " \
- "cp.b 0xa0000000 0x40000 0x100000; " \
- "fi\0" \
- "prog_jffs_net=" \
- "mw.b 0xa0000000 0xff 0x1e00000; " \
- "if bootp 0xa0000000 root.jffs; " \
- "then " \
- "protect off 0x140000 0x1f3ffff; " \
- "erase 0x140000 0x1f3ffff; " \
- "cp.b 0xa0000000 0x140000 0x1e00000; " \
- "fi\0"
-
-
-/* "erase_env=" */
-/* "protect off" */
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
-
-#define RTC 1 /* enable 32KHz osc */
-
-#ifdef CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * GPIO settings
- */
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x2
-#define CONFIG_SYS_GPCR0_VAL 0x1800400
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xc1818440
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL 0x1ffff
-#define CONFIG_SYS_GPSR0_VAL 0x8000
-#define CONFIG_SYS_GPSR1_VAL 0x3f0002
-#define CONFIG_SYS_GPSR2_VAL 0x1c000
-
-#define CONFIG_SYS_PSSR_VAL 0x20
-
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-#define CONFIG_SYS_CKEN 0x0
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
-#define CONFIG_SYS_MSC1_VAL 0x43AC494C
-#define CONFIG_SYS_MSC2_VAL 0x39D449D4
-#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
-#define CONFIG_SYS_MDREFR_VAL 0x0085C017
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x00014405
-#define CONFIG_SYS_MCMEM1_VAL 0x00014405
-#define CONFIG_SYS_MCATT0_VAL 0x00014405
-#define CONFIG_SYS_MCATT1_VAL 0x00014405
-#define CONFIG_SYS_MCIO0_VAL 0x00014405
-#define CONFIG_SYS_MCIO1_VAL 0x00014405
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* put cfg at end of flash for now */
-#define CONFIG_ENV_IS_IN_FLASH 1
- /* Addr of Environment Sector */
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
-#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
deleted file mode 100644
index 0199190..0000000
--- a/include/configs/zipitz2.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Aeronix Zipit Z2 configuration file
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#undef CONFIG_BOARD_LATE_INIT
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_PREBOOT
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SIZE 0x20000
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
- "then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x60000; " \
- "fi; "
-#define CONFIG_BOOTARGS \
- "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- * STUART - the lower serial port on Colibri board
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_STUART 1
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_SPI
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * SPI and LCD
- */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_SOFT_SPI
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_LMS283GF05
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-#define SPI_DELAY udelay(10)
-#define SPI_SDA(val) zipitz2_spi_sda(val)
-#define SPI_SCL(val) zipitz2_spi_scl(val)
-#define SPI_READ zipitz2_spi_read()
-#ifndef __ASSEMBLY__
-void zipitz2_spi_sda(int);
-void zipitz2_spi_scl(int);
-unsigned char zipitz2_spi_read(void);
-#endif
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
-
-/*
- * SRAM Map
- */
-#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
-#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
-
-/*
- * NOR FLASH
- */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
-#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
-#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
-#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
-#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
-#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000020
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
-#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
-#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
-#define CONFIG_SYS_GPSR0_VAL 0x06080400
-#define CONFIG_SYS_GPSR1_VAL 0x007f0000
-#define CONFIG_SYS_GPSR2_VAL 0x032a0000
-#define CONFIG_SYS_GPSR3_VAL 0x00000180
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x00511220
-#define CONFIG_SYS_CCCR 0x00000190
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
-#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
-#define CONFIG_SYS_MSC2_VAL 0x0000b884
-#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
-#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 31/45] arm: Remove qong board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (29 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 30/45] arm: Remove pxa255_idp, zipitz2 boards Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,31/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 32/45] arm: Remove rd6281a board Simon Glass
` (14 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/davedenx/qong/Kconfig | 15 --
board/davedenx/qong/MAINTAINERS | 6 -
board/davedenx/qong/Makefile | 11 --
board/davedenx/qong/fpga.c | 77 ----------
board/davedenx/qong/lowlevel_init.S | 223 ----------------------------
board/davedenx/qong/qong.c | 259 ---------------------------------
board/davedenx/qong/qong_fpga.h | 23 ---
configs/qong_defconfig | 2 -
include/configs/qong.h | 283 ------------------------------------
10 files changed, 904 deletions(-)
delete mode 100644 board/davedenx/qong/Kconfig
delete mode 100644 board/davedenx/qong/MAINTAINERS
delete mode 100644 board/davedenx/qong/Makefile
delete mode 100644 board/davedenx/qong/fpga.c
delete mode 100644 board/davedenx/qong/lowlevel_init.S
delete mode 100644 board/davedenx/qong/qong.c
delete mode 100644 board/davedenx/qong/qong_fpga.h
delete mode 100644 configs/qong_defconfig
delete mode 100644 include/configs/qong.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 511535c..2636db3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -229,10 +229,6 @@ config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
-config TARGET_QONG
- bool "Support qong"
- select CPU_ARM1136
-
config TARGET_MX31ADS
bool "Support mx31ads"
select CPU_ARM1136
@@ -836,7 +832,6 @@ source "board/compulab/cm_t43/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
-source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
diff --git a/board/davedenx/qong/Kconfig b/board/davedenx/qong/Kconfig
deleted file mode 100644
index 76cf343..0000000
--- a/board/davedenx/qong/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_QONG
-
-config SYS_BOARD
- default "qong"
-
-config SYS_VENDOR
- default "davedenx"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "qong"
-
-endif
diff --git a/board/davedenx/qong/MAINTAINERS b/board/davedenx/qong/MAINTAINERS
deleted file mode 100644
index a275b5b..0000000
--- a/board/davedenx/qong/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-QONG BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/davedenx/qong/
-F: include/configs/qong.h
-F: configs/qong_defconfig
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
deleted file mode 100644
index 48c443d..0000000
--- a/board/davedenx/qong/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2009
-# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := qong.o fpga.o
-obj-y += lowlevel_init.o
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
deleted file mode 100644
index 2eaad1e..0000000
--- a/board/davedenx/qong/fpga.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic at denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-#include <fpga.h>
-#include <lattice.h>
-#include "qong_fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-static void qong_jtag_init(void)
-{
- return;
-}
-
-static void qong_fpga_jtag_set_tdi(int value)
-{
- gpio_set_value(QONG_FPGA_TDI_PIN, value);
-}
-
-static void qong_fpga_jtag_set_tms(int value)
-{
- gpio_set_value(QONG_FPGA_TMS_PIN, value);
-}
-
-static void qong_fpga_jtag_set_tck(int value)
-{
- gpio_set_value(QONG_FPGA_TCK_PIN, value);
-}
-
-static int qong_fpga_jtag_get_tdo(void)
-{
- return gpio_get_value(QONG_FPGA_TDO_PIN);
-}
-
-lattice_board_specific_func qong_fpga_fns = {
- qong_jtag_init,
- qong_fpga_jtag_set_tdi,
- qong_fpga_jtag_set_tms,
- qong_fpga_jtag_set_tck,
- qong_fpga_jtag_get_tdo
-};
-
-Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
- {
- Lattice_XP2,
- lattice_jtag_mode,
- 356519,
- (void *) &qong_fpga_fns,
- NULL,
- 0,
- "lfxp2_5e_ftbga256"
- },
-};
-
-int qong_fpga_init(void)
-{
- int i;
-
- fpga_init();
-
- for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
- fpga_add(fpga_lattice, &qong_fpga[i]);
- }
- return 0;
-}
-
-#endif
diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S
deleted file mode 100644
index 8887023..0000000
--- a/board/davedenx/qong/lowlevel_init.S
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * Based on board/freescale/mx31ads/lowlevel_init.S
- * by Guennadi Liakhovetski.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.macro SETUP_RAM cfg, ctl
- /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
- REG 0xB8001010, 0x00000004
- ldr r3, =\cfg
- ldr r2, =WEIM_ESDCFG0
- str r3, [r2]
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- ldr r3, =\ctl
- ldr r2, =WEIM_ESDCTL0
- str r3, [r2]
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
-.endm
-/* RedBoot: To support 133MHz DDR */
-.macro init_drive_strength
- /*
- * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
- * in SW_PAD_CTL registers
- */
-
- /* SDCLK */
- ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
- ldr r0, [r1, #0x6C]
- bic r0, r0, #(1 << 12)
- str r0, [r1, #0x6C]
-
- /* CAS */
- ldr r0, [r1, #0x70]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x70]
-
- /* RAS */
- ldr r0, [r1, #0x74]
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x74]
-
- /* CS2 (CSD0) */
- ldr r0, [r1, #0x7C]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x7C]
-
- /* DQM3 */
- ldr r0, [r1, #0x84]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x84]
-
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
- ldr r0, [r1, #0x88]
- bic r0, r0, #(1 << 22)
- bic r0, r0, #(1 << 12)
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x88]
- add r1, r1, #4
- subs r2, r2, #0x1
- bne pad_loop
-.endm /* init_drive_strength */
-
-.globl lowlevel_init
-lowlevel_init:
-
- init_drive_strength
-
- /* Image Processing Unit: */
- /* Too early to switch display on? */
- /* Switch on Display Interface */
- REG IPU_CONF, IPU_CONF_DI_EN
- /* Clock Control Module: */
- REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
- /* Switch to MCU PLL */
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- /* 399-133-66.5 */
- ldr r0, =CCM_BASE
- ldr r1, =0xFF871650
- /* PDR0 */
- str r1, [r0, #0x4]
- ldr r1, MPCTL_PARAM_399
- /* MPCTL */
- str r1, [r0, #0x10]
-
- /* Set UPLL=240MHz, USB=60MHz */
- ldr r1, =0x49FCFE7F
- /* PDR1 */
- str r1, [r0, #0x8]
- ldr r1, UPCTL_PARAM_240
- /* UPCTL */
- str r1, [r0, #0x14]
- /* default CLKO to 1/8 of the ARM core */
- mov r1, #0x00000208
- /* COSR */
- str r1, [r0, #0x1c]
-
- /* Default: 1, 4, 12, 1 */
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
-check_ddr_module:
-/* Set stackpointer in internal RAM to call get_ram_size */
- ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
- stmfd sp!, {r0-r11, ip, lr}
- mov ip, lr /* save link reg across call */
-
- ldr r0,=0x08000000
- SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
- ldr r0,=0x80000000
- ldr r1,=0x10000000
- bl get_ram_size
- ldr r1,=0x10000000
- cmp r0,r1
- beq restore_regs
- SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
- ldr r0,=0x80000000
- ldr r1,=0x08000000
- bl get_ram_size
- ldr r1,=0x08000000
- cmp r0,r1
- beq restore_regs
-
-restore_regs:
- ldmfd sp!, {r0-r11, ip, lr}
- mov lr, ip /* restore link reg */
-
- mov pc, lr
-
-
-MPCTL_PARAM_399:
- .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
-UPCTL_PARAM_240:
- .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
-
- .equ ESDCFG0_128MB, \
- (0 << 21) + /* tXP */ \
- (1 << 20) + /* tWTR */ \
- (2 << 18) + /* tRP */ \
- (1 << 16) + /* tMRD */ \
- (0 << 15) + /* tWR */ \
- (5 << 12) + /* tRAS */ \
- (1 << 10) + /* tRRD */ \
- (3 << 8) + /* tCAS */ \
- (2 << 4) + /* tRCD */ \
- (0x0F << 0) /* tRC */
-
- .equ ESDCTL0_128MB, \
- (1 << 31) + /* enable */ \
- (0 << 28) + /* mode */ \
- (0 << 27) + /* supervisor protect */ \
- (2 << 24) + /* 13 rows */ \
- (2 << 20) + /* 10 cols */ \
- (2 << 16) + /* 32 bit */ \
- (3 << 13) + /* 7.81us (64ms/8192) */ \
- (0 << 10) + /* power down timer */ \
- (0 << 8) + /* full page */ \
- (1 << 7) + /* burst length */ \
- (0 << 0) /* precharge timer */
-
- .equ ESDCFG0_256MB, \
- (3 << 21) + /* tXP */ \
- (0 << 20) + /* tWTR */ \
- (2 << 18) + /* tRP */ \
- (1 << 16) + /* tMRD */ \
- (0 << 15) + /* tWR */ \
- (5 << 12) + /* tRAS */ \
- (1 << 10) + /* tRRD */ \
- (3 << 8) + /* tCAS */ \
- (2 << 4) + /* tRCD */ \
- (7 << 0) /* tRC */
-
- .equ ESDCTL0_256MB, \
- (1 << 31) + \
- (0 << 28) + \
- (0 << 27) + \
- (3 << 24) + /* 14 rows */ \
- (2 << 20) + /* 10 cols */ \
- (2 << 16) + \
- (4 << 13) + /* 3.91us (64ms/16384) */ \
- (0 << 10) + \
- (0 << 8) + \
- (1 << 7) + \
- (0 << 0)
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
deleted file mode 100644
index ad1694b..0000000
--- a/board/davedenx/qong/qong.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- *
- * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <asm/gpio.h>
-#include "qong_fpga.h"
-#include <watchdog.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-static void qong_fpga_reset(void)
-{
- gpio_set_value(QONG_FPGA_RST_PIN, 0);
- udelay(30);
- gpio_set_value(QONG_FPGA_RST_PIN, 1);
-
- udelay(300);
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_QONG_FPGA
- /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
- static const struct mxc_weimcs cs1 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(1, &cs1);
-
- /* setup pins for FPGA */
- mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
-
- /* FPGA reset Pin */
- /* rstn = 0 */
- gpio_direction_output(QONG_FPGA_RST_PIN, 0);
-
- /* set interrupt pin as input */
- gpio_direction_input(QONG_FPGA_IRQ_PIN);
-
- /* FPGA JTAG Interface */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
- gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
- gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
- gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
- gpio_direction_input(QONG_FPGA_TDO_PIN);
-#endif
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* setup pins for SPI (pmic) */
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-
- /* Setup pins for USB2 Host */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-
-#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
- mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
- mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
- mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
- mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
- mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
- mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
- mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
- mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
-
- mx31_set_gpr(MUX_PGP_UH2, 1);
-
- return 0;
-
-}
-
-int board_init(void)
-{
- /* Chip selects */
- /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
- /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
-
- /* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_QONG;
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- qong_fpga_init();
-
- return 0;
-}
-
-int board_late_init(void)
-{
- u32 val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
- /* Enable RTC battery */
- pmic_reg_read(p, REG_POWER_CTL0, &val);
- pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
- pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
-
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: DAVE/DENX Qong\n");
- return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_QONG_FPGA
- u32 tmp;
-
- tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
- printf("FPGA: ");
- printf("version register = %u.%u.%u\n",
- (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
-#endif
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
- return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
-#else
- return 0;
-#endif
-}
-
-#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
-static void board_nand_setup(void)
-{
- /* CS3: NAND 8-bit */
- static const struct mxc_weimcs cs3 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(3, &cs3);
-
- mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
-
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
-
- /* Make sure to reset the fpga else you cannot access NAND */
- qong_fpga_reset();
-
- /* Enable NAND flash */
- gpio_set_value(15, 1);
- gpio_set_value(14, 1);
- gpio_direction_output(15, 0);
- gpio_direction_input(16);
- gpio_direction_input(14);
-
-}
-
-int qong_nand_rdy(void *chip)
-{
- udelay(1);
- return gpio_get_value(16);
-}
-
-void qong_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- if (chip >= 0)
- gpio_set_value(15, 0);
- else
- gpio_set_value(15, 1);
-
-}
-
-void qong_nand_plat_init(void *chip)
-{
- struct nand_chip *nand = (struct nand_chip *)chip;
- nand->chip_delay = 20;
- nand->select_chip = qong_nand_select_chip;
- nand->options &= ~NAND_BUSWIDTH_16;
- board_nand_setup();
-}
-
-#endif
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
deleted file mode 100644
index 2a619f7..0000000
--- a/board/davedenx/qong/qong_fpga.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *
- * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef QONG_FPGA_H
-#define QONG_FPGA_H
-
-#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
-#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
-#define QONG_FPGA_PERIPH_SIZE (1 << 24)
-
-#define QONG_FPGA_TCK_PIN 26
-#define QONG_FPGA_TMS_PIN 25
-#define QONG_FPGA_TDI_PIN 8
-#define QONG_FPGA_TDO_PIN 7
-#define QONG_FPGA_RST_PIN 48
-#define QONG_FPGA_IRQ_PIN 40
-
-int qong_fpga_init(void);
-#endif /* QONG_FPGA_H */
diff --git a/configs/qong_defconfig b/configs/qong_defconfig
deleted file mode 100644
index fddd836..0000000
--- a/configs/qong_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_QONG=y
diff --git a/include/configs/qong.h b/include/configs/qong.h
deleted file mode 100644
index f34a54f..0000000
--- a/include/configs/qong.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
- *
- * Configuration settings for the Dave/DENX QongEVB-LITE board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31 /* This is a mx31 */
-#define CONFIG_QONG
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-#define CONFIG_MXC_GPIO
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
-
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_RTC_MC13XXX
-
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 1
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 100000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-
-/* FPGA */
-#define CONFIG_FPGA
-#define CONFIG_QONG_FPGA
-#define CONFIG_FPGA_BASE (CS1_BASE)
-#define CONFIG_FPGA_LATTICE
-#define CONFIG_FPGA_COUNT 1
-
-#ifdef CONFIG_QONG_FPGA
-/* Ethernet */
-#define CONFIG_DNET
-#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_MX3
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
-
-/* USB */
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 2
-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
-#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#endif /* CONFIG_CMD_USB */
-
-/*
- * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
- * initial TFTP transfer, should the user wish one, significantly.
- */
-#define CONFIG_ARP_TIMEOUT 200UL
-
-#endif /* CONFIG_QONG_FPGA */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_UNZIP
-
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "uboot_addr=A0000000\0" \
- "kernel_addr=A00C0000\0" \
- "ramdisk_addr=A0300000\0" \
- "u-boot=qong/u-boot.bin\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=qong\0" \
- "bootfile=qong/uImage\0" \
- "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm\0" \
- "bootcmd=run flash_self\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
- " +${filesize};cp.b ${fileaddr} " \
- __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
- "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
- "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
- "vmode:0\0" \
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on first 255MB of RAM */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MISC_INIT_R
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
-
-/*
- * NAND driver
- */
-
-#ifndef __ASSEMBLY__
-extern void qong_nand_plat_init(void *chip);
-extern int qong_nand_rdy(void *chip);
-#endif
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CS3_BASE
-#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
-
-#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
-#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
-#define QONG_NAND_WRITE(addr, cmd) \
- do { \
- __REG8(addr) = cmd; \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-/* Monitor@beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* Flash memory is CFI compliant */
-#define CONFIG_SYS_FLASH_CFI
-/* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_CFI_DRIVER
-/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * Filesystem
- */
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
- "nand0=gen_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "512k(U-Boot),128k(env1),128k(env2)," \
- "2304k(kernel),13m(ramdisk),-(user);" \
- "gen_nand:" \
- "128m(nand)"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 32/45] arm: Remove rd6281a board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (30 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 31/45] arm: Remove qong board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,32/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 33/45] arm: Remove scb9328 board Simon Glass
` (13 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 4 -
board/Marvell/rd6281a/Kconfig | 12 ---
board/Marvell/rd6281a/MAINTAINERS | 6 --
board/Marvell/rd6281a/Makefile | 9 ---
board/Marvell/rd6281a/kwbimage.cfg | 151 -----------------------------------
board/Marvell/rd6281a/rd6281a.c | 157 -------------------------------------
board/Marvell/rd6281a/rd6281a.h | 25 ------
configs/rd6281a_defconfig | 6 --
include/configs/rd6281a.h | 96 -----------------------
9 files changed, 466 deletions(-)
delete mode 100644 board/Marvell/rd6281a/Kconfig
delete mode 100644 board/Marvell/rd6281a/MAINTAINERS
delete mode 100644 board/Marvell/rd6281a/Makefile
delete mode 100644 board/Marvell/rd6281a/kwbimage.cfg
delete mode 100644 board/Marvell/rd6281a/rd6281a.c
delete mode 100644 board/Marvell/rd6281a/rd6281a.h
delete mode 100644 configs/rd6281a_defconfig
delete mode 100644 include/configs/rd6281a.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 9c6e398..27c09a7 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,9 +4,6 @@ choice
prompt "Marvell Kirkwood board select"
optional
-config TARGET_RD6281A
- bool "RD6281A Board"
-
config TARGET_DREAMPLUG
bool "DreamPlug Board"
@@ -51,7 +48,6 @@ endchoice
config SYS_SOC
default "kirkwood"
-source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig
deleted file mode 100644
index 025ee26..0000000
--- a/board/Marvell/rd6281a/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RD6281A
-
-config SYS_BOARD
- default "rd6281a"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "rd6281a"
-
-endif
diff --git a/board/Marvell/rd6281a/MAINTAINERS b/board/Marvell/rd6281a/MAINTAINERS
deleted file mode 100644
index d4ad592..0000000
--- a/board/Marvell/rd6281a/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RD6281A BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/rd6281a/
-F: include/configs/rd6281a.h
-F: configs/rd6281a_defconfig
diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile
deleted file mode 100644
index cb77370..0000000
--- a/board/Marvell/rd6281a/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := rd6281a.o
diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg
deleted file mode 100644
index f969d92..0000000
--- a/board/Marvell/rd6281a/kwbimage.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000099 # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 1, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 0, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
-# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
-# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
deleted file mode 100644
index b0020c9..0000000
--- a/board/Marvell/rd6281a/rd6281a.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "rd6281a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(RD6281A_OE_VAL_LOW,
- RD6281A_OE_VAL_HIGH,
- RD6281A_OE_LOW, RD6281A_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GPIO,
- MPP36_AUDIO_SPDIFI,
- MPP37_AUDIO_SPDIFO,
- MPP38_GPIO,
- MPP39_TDM_SPI_CS0,
- MPP40_TDM_SPI_SCK,
- MPP41_TDM_SPI_MISO,
- MPP42_TDM_SPI_MOSI,
- MPP43_TDM_CODEC_INTn,
- MPP44_GPIO,
- MPP45_TDM_PCLK,
- MPP46_TDM_FS,
- MPP47_TDM_DRX,
- MPP48_TDM_DTX,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-void mv_phy_88e1116_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) {
- printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
- return;
- }
- if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
- printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
- return;
- }
-
- printf("88E1116 Initialized on %s\n", name);
-}
-
-/* Configure and enable Switch and PHY */
-void reset_phy(void)
-{
- /* configure and initialize switch */
- struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = (1 << 5),
- .ports_enabled = 0x3f,
- };
-
- mv88e61xx_switch_initialize(&swcfg);
-
- /* configure and initialize PHY */
- mv_phy_88e1116_init("egiga1");
-}
diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h
deleted file mode 100644
index 5e1f6a8..0000000
--- a/board/Marvell/rd6281a/rd6281a.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RD6281A_H
-#define __RD6281A_H
-
-#define RD6281A_OE_LOW (~(1 << 7))
-#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12))
-#define RD6281A_OE_VAL_LOW (0)
-#define RD6281A_OE_VAL_HIGH (1 << 12)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __RD6281A_H */
diff --git a/configs/rd6281a_defconfig b/configs/rd6281a_defconfig
deleted file mode 100644
index 8fe8594..0000000
--- a/configs/rd6281a_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_RD6281A=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
deleted file mode 100644
index a0120b0..0000000
--- a/include/configs/rd6281a.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_RD6281A_H
-#define _CONFIG_RD6281A_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_RD6281A /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
- "3m at 1m(kernel),1m at 4m(psm),13m at 5m(rootfs) rw\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
-#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
-#define CONFIG_PHY_BASE_ADR 0x0A
-#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_RD6281A_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 33/45] arm: Remove scb9328 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (31 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 32/45] arm: Remove rd6281a board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,33/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 34/45] arm: Remove tk71 board Simon Glass
` (12 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/scb9328/Kconfig | 12 --
board/scb9328/MAINTAINERS | 6 -
board/scb9328/Makefile | 9 --
board/scb9328/flash.c | 310 -----------------------------------------
board/scb9328/intel.h | 78 -----------
board/scb9328/lowlevel_init.S | 188 -------------------------
board/scb9328/scb9328.c | 54 --------
configs/scb9328_defconfig | 7 -
include/configs/scb9328.h | 312 ------------------------------------------
10 files changed, 981 deletions(-)
delete mode 100644 board/scb9328/Kconfig
delete mode 100644 board/scb9328/MAINTAINERS
delete mode 100644 board/scb9328/Makefile
delete mode 100644 board/scb9328/flash.c
delete mode 100644 board/scb9328/intel.h
delete mode 100644 board/scb9328/lowlevel_init.S
delete mode 100644 board/scb9328/scb9328.c
delete mode 100644 configs/scb9328_defconfig
delete mode 100644 include/configs/scb9328.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2636db3..0ab0c24 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -69,10 +69,6 @@ choice
config ARCH_AT91
bool "Atmel AT91"
-config TARGET_SCB9328
- bool "Support scb9328"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@@ -874,7 +870,6 @@ source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig
deleted file mode 100644
index 68e99ea..0000000
--- a/board/scb9328/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SCB9328
-
-config SYS_BOARD
- default "scb9328"
-
-config SYS_SOC
- default "imx"
-
-config SYS_CONFIG_NAME
- default "scb9328"
-
-endif
diff --git a/board/scb9328/MAINTAINERS b/board/scb9328/MAINTAINERS
deleted file mode 100644
index 0917266..0000000
--- a/board/scb9328/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SCB9328 BOARD
-M: Torsten Koschorrek <koschorrek@synertronixx.de>
-S: Maintained
-F: board/scb9328/
-F: include/configs/scb9328.h
-F: configs/scb9328_defconfig
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
deleted file mode 100644
index 0b08f1a..0000000
--- a/board/scb9328/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := scb9328.o flash.o
-obj-y += lowlevel_init.o
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
deleted file mode 100644
index 73bfa00..0000000
--- a/board/scb9328/flash.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- * hopefully may work with other configurations.
- */
-
-#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
-# define FLASH_BUS vu_char
-# define FLASH_BUS_RET u_char
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# else
-# error "With 8bit bus only one chip is allowed"
-# endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
-# define FLASH_BUS vu_short
-# define FLASH_BUS_RET u_short
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 8 )| x )
-# else
-# error "With 16bit bus only 1 or 2 chip(s) are allowed"
-# endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
-# define FLASH_BUS vu_long
-# define FLASH_BUS_RET u_long
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 16 )| x )
-# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
-# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-# else
-# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-# endif
-
-#else
-# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
- FLASH_BUS *addr = (FLASH_BUS *) 0;
-
- /* cppcheck-suppress nullPointer */
- *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
- /* cppcheck-suppress nullPointer */
- return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
- int ok = 1;
- ulong start;
-
- start = get_timer(0);
- while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
- FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer(start) > timeout && timeout != 0) {
- ok = 0;
- break;
- }
- }
- return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-# error "SCB9328 platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
- int i;
- unsigned long address = SCB9328_FLASH_BASE;
-
- flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
- flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[0].flash_id = INTEL_MANUFACT;
- memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
- flash_info[0].start[i] = address;
-#ifdef SCB9328_FLASH_UNLOCK
- /* Some devices are hw locked after start. */
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
- flash_ready (0);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
- address += SCB9328_FLASH_SECT_SIZE;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return SCB9328_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- printf (" Intel vendor\n");
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if (!(i % 5)) {
- printf ("\n");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, non_protected = 0, sector;
- int rc = ERR_OK;
-
- FLASH_BUS *address;
-
- for (sector = s_first; sector <= s_last; sector++) {
- if (!info->protect[sector]) {
- non_protected++;
- }
- }
-
- if (!non_protected) {
- return ERR_PROTECTED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
-
- /* Start erase on unprotected sectors */
- for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
- if (info->protect[sector]) {
- printf ("Protected sector %2d skipping...\n", sector);
- continue;
- } else {
- printf ("Erasing sector %2d ... ", sector);
- }
-
- address = (FLASH_BUS *) (info->start[sector]);
-
- *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
- *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
- if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- printf ("ok.\n");
- } else {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- break;
- }
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- }
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked (10000);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
- FLASH_BUS *address = (FLASH_BUS *) dest;
- int rc = ERR_OK;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*address & data) != data) {
- return ERR_NOT_ERASED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts ();
-
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
- *address = data;
-
- if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- }
-
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong read_addr, write_addr;
- FLASH_BUS data;
- int i, result = ERR_OK;
-
-
- read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
- write_addr = read_addr;
- if (read_addr != addr) {
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (read_addr < addr || cnt == 0) {
- data |= *((uchar *) read_addr) << i * 8;
- } else {
- data |= (*src++) << i * 8;
- cnt--;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- }
- for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
- if ((result = write_data (info, write_addr,
- *((FLASH_BUS *) src))) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- src += sizeof (FLASH_BUS);
- }
- if (cnt > 0) {
- read_addr = write_addr;
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (cnt > 0) {
- data |= (*src++) << i * 8;
- cnt--;
- } else {
- data |= *((uchar *) read_addr) << i * 8;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != 0) {
- return result;
- }
- }
- return ERR_OK;
-}
diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h
deleted file mode 100644
index 5596d27..0000000
--- a/board/scb9328/intel.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
deleted file mode 100644
index d572724..0000000
--- a/board/scb9328/lowlevel_init.S
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* Change PERCLK1DIV to 14 ie 14+1 */
- ldr r0, =PCDR
- ldr r1, =CONFIG_SYS_PCDR_VAL
- str r1, [r0]
-
-/* set MCU PLL Control Register 0 */
-
- ldr r0, =MPCTL0
- ldr r1, =CONFIG_SYS_MPCTL0_VAL
- str r1, [r0]
-
-/* set mpll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<21)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
-/* set System PLL Control Register 0 */
-
- ldr r0, =SPCTL0
- ldr r1, =CONFIG_SYS_SPCTL0_VAL
- str r1, [r0]
-
-/* set spll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<22)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
- ldr r0, =CSCR
- ldr r1, =CONFIG_SYS_CSCR_VAL
- str r1, [r0]
-
-/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
- *this.....
- *
- * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
- * register 1, this stops it using the output of the PLL and thus runs at the
- * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
- * use the value set in the CM_OSC registers...regardless of what you set it
- * too! Thus, although i thought i was running at 140MHz, i'm actually running
- *@40!..
-
- * Slapping this into my bootloader does the trick...
-
- * MRC p15,0,r0,c1,c0,0 ; read core configuration register
- * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
- * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
- * register
- */
- MRC p15,0,r0,c1,c0,0
- ORR r0,r0,#0xC0000000
- MCR p15,0,r0,c1,c0,0
-
- ldr r0, =GPR(0)
- ldr r1, =CONFIG_SYS_GPR_A_VAL
- str r1, [r0]
-
- ldr r0, =GIUS(0)
- ldr r1, =CONFIG_SYS_GIUS_A_VAL
- str r1, [r0]
-
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-
- ldr r0, =FMCR
- ldr r1, =CONFIG_SYS_FMCR_VAL
- str r1, [r0]
-
- ldr r0, =CS0U
- ldr r1, =CONFIG_SYS_CS0U_VAL
- str r1, [r0]
-
- ldr r0, =CS0L
- ldr r1, =CONFIG_SYS_CS0L_VAL
- str r1, [r0]
-
- ldr r0, =CS1U
- ldr r1, =CONFIG_SYS_CS1U_VAL
- str r1, [r0]
-
- ldr r0, =CS1L
- ldr r1, =CONFIG_SYS_CS1L_VAL
- str r1, [r0]
-
- ldr r0, =CS2U
- ldr r1, =CONFIG_SYS_CS2U_VAL
- str r1, [r0]
-
- ldr r0, =CS2L
- ldr r1, =CONFIG_SYS_CS2L_VAL
- str r1, [r0]
-
- ldr r0, =CS3U
- ldr r1, =CONFIG_SYS_CS3U_VAL
- str r1, [r0]
-
- ldr r0, =CS3L
- ldr r1, =CONFIG_SYS_CS3L_VAL
- str r1, [r0]
-
- ldr r0, =CS4U
- ldr r1, =CONFIG_SYS_CS4U_VAL
- str r1, [r0]
-
- ldr r0, =CS4L
- ldr r1, =CONFIG_SYS_CS4L_VAL
- str r1, [r0]
-
- ldr r0, =CS5U
- ldr r1, =CONFIG_SYS_CS5U_VAL
- str r1, [r0]
-
- ldr r0, =CS5L
- ldr r1, =CONFIG_SYS_CS5L_VAL
- str r1, [r0]
-
-/* SDRAM Setup */
-
- ldr r0, =SDCTL0
- ldr r1, =PRECHARGE_CMD
- str r1, [r0]
-
- ldr r0, =0x08200000
- ldr r1, =0x0 /* Issue Precharge all Command */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =AUTOREFRESH_CMD
- str r1, [r0]
-
- ldr r0, =0x08000000
- ldr r1, =0x0 /* Issue AutoRefresh Command */
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0xb10a8300
- str r1, [r0]
-
- ldr r0, =0x08223000 /* CAS Latency 2 */
- ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
- str r1, [r0]
-
- mov pc,r10
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
deleted file mode 100644
index 3463f52..0000000
--- a/board/scb9328/scb9328.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
- gd->bd->bi_boot_params = 0x08000100;
-
- return 0;
-}
-
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1,
- SCB9328_SDRAM_1_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
- gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
-}
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
- return;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
diff --git a/configs/scb9328_defconfig b/configs/scb9328_defconfig
deleted file mode 100644
index c9c5034..0000000
--- a/configs/scb9328_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_SCB9328=y
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="scb9328> "
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
deleted file mode 100644
index d4ffb46..0000000
--- a/include/configs/scb9328.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * SPDX-License-Identifier: GPL-2.0+
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- * 2003/13/06 Initial MP10 Support copied from wepep250
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
-#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
-
-#define CONFIG_IMX_SERIAL
-#define CONFIG_IMX_SERIAL1
-/*
- * Select serial console configuration
- */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
-#define CONFIG_BOOTCOMMAND "bootm 10040000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.10.10.9
-#define CONFIG_SERVERIP 10.10.10.10
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP /* undef saves memory */
-#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
-
-#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0x08F00000
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
-
-#define CONFIG_BAUDRATE 115200
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG 1 /* send initrd params */
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-/* SDRAM Setup Values
-0x910a8300 Precharge Command CAS 3
-0x910a8200 Precharge Command CAS 2
-
-0xa10a8300 AutoRefresh Command CAS 3
-0xa10a8200 Set AutoRefresh Command CAS 2 */
-
-#define PRECHARGE_CMD 0x910a8200
-#define AUTOREFRESH_CMD 0xa10a8200
-
-/*
- * SDRAM Memory Map
- */
-/* SH FIXME */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
-#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
-#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
-
-/*
- * Configuration for FLASH memory for the Synertronixx board
- */
-
-/* #define SCB9328_FLASH_32M */
-
-/* 32MB */
-#ifdef SCB9328_FLASH_32M
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
-#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
-#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
-#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
-#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
-#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
-#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
-#else
-
-/* 16MB */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
-#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
-#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
-#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
-#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
-#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
-#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
-#endif /* SCB9328_FLASH_32M */
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
- is not so clear to me. In other words we can provide more informations
- to user, but this expects more complex flash handling we do not provide
- now.*/
-#undef CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-/* Setup for PA23 which is Reset Default PA23 but has to become
- CS5 */
-
-#define CONFIG_SYS_GPR_A_VAL 0x00800000
-#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
-
-#define CONFIG_SYS_MONITOR_BASE 0x10000000
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x20000
-
-#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
-
-/*
- * CSxU_VAL:
- * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
- * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
- *
- * CSxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
- * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
- */
-
-#define CONFIG_SYS_CS0U_VAL 0x000F2000
-#define CONFIG_SYS_CS0L_VAL 0x11110d01
-#define CONFIG_SYS_CS1U_VAL 0x000F0a00
-#define CONFIG_SYS_CS1L_VAL 0x11110601
-#define CONFIG_SYS_CS2U_VAL 0x0
-#define CONFIG_SYS_CS2L_VAL 0x0
-
-#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
-#define CONFIG_SYS_CS3L_VAL 0x00000303
-
-#define CONFIG_SYS_CS4U_VAL 0x000F0a00
-#define CONFIG_SYS_CS4L_VAL 0x11110301
-
-/* CNC == 3 too long
- #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
-
-/* #define CONFIG_SYS_CS5U_VAL 0x00008400
- mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
- kaum langsamer ist */
-/* #define CONFIG_SYS_CS5U_VAL 0x00009400
- #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
-
-#define CONFIG_SYS_CS5U_VAL 0x00008400
-#define CONFIG_SYS_CS5L_VAL 0x00000D03
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x16000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE+4)
-
-/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
- f_ref=16,777MHz
-
- 0x002a141f: 191,9944MHz
- 0x040b2007: 144MHz
- 0x042a141f: 96MHz
- 0x0811140d: 64MHz
- 0x040e200e: 150MHz
- 0x00321431: 200MHz
-
- 0x08001800: 64MHz mit 16er Quarz
- 0x04001800: 96MHz mit 16er Quarz
- 0x04002400: 144MHz mit 16er Quarz
-
- 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
- |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
-
-#define CPU200
-
-#ifdef CPU200
-#define CONFIG_SYS_MPCTL0_VAL 0x00321431
-#else
-#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
-#endif
-
-/* #define BUS64 */
-#define BUS72
-
-#ifdef BUS72
-#define CONFIG_SYS_SPCTL0_VAL 0x04002400
-#endif
-
-#ifdef BUS96
-#define CONFIG_SYS_SPCTL0_VAL 0x04001800
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_SPCTL0_VAL 0x08001800
-#endif
-
-/* Das ist der BCLK Divider, der aus der System PLL
- BCLK und HCLK erzeugt:
- 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
- 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
- 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
- 0x2f001003 : 192MHz/5=38,4MHz
- 0x2f000003 : 64MHz/1
- Bit 22: SPLL Restart
- Bit 21: MPLL Restart */
-
-#ifdef BUS64
-#define CONFIG_SYS_CSCR_VAL 0x2f030003
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_CSCR_VAL 0x2f030403
-#endif
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR 0x08400000
-
-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-
-/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
-#define CONFIG_SYS_FMCR_VAL 0x00000001
-
-/* Bit[0:3] contain PERCLK1DIV for UART 1
- 0x000b00b ->b<- -> 192MHz/12=16MHz
- 0x000b00b ->8<- -> 144MHz/09=16MHz
- 0x000b00b ->3<- -> 64MHz/4=16MHz */
-
-#ifdef BUS96
-#define CONFIG_SYS_PCDR_VAL 0x000b00b5
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_PCDR_VAL 0x000b00b3
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_PCDR_VAL 0x000b00b8
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 34/45] arm: Remove tk71 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (32 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 33/45] arm: Remove scb9328 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,34/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 35/45] arm: Remove tt01 board Simon Glass
` (11 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 4 --
board/karo/tk71/Kconfig | 12 ----
board/karo/tk71/MAINTAINERS | 6 --
board/karo/tk71/Makefile | 9 ---
board/karo/tk71/kwbimage.cfg | 158 -----------------------------------------
board/karo/tk71/tk71.c | 150 --------------------------------------
configs/tk71_defconfig | 6 --
include/configs/tk71.h | 112 -----------------------------
8 files changed, 457 deletions(-)
delete mode 100644 board/karo/tk71/Kconfig
delete mode 100644 board/karo/tk71/MAINTAINERS
delete mode 100644 board/karo/tk71/Makefile
delete mode 100644 board/karo/tk71/kwbimage.cfg
delete mode 100644 board/karo/tk71/tk71.c
delete mode 100644 configs/tk71_defconfig
delete mode 100644 include/configs/tk71.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 27c09a7..c5491e4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -25,9 +25,6 @@ config TARGET_DNS325
config TARGET_ICONNECT
bool "iconnect Board"
-config TARGET_TK71
- bool "TK71 Board"
-
config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board"
@@ -55,7 +52,6 @@ source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
-source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig
deleted file mode 100644
index 7b3d548..0000000
--- a/board/karo/tk71/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TK71
-
-config SYS_BOARD
- default "tk71"
-
-config SYS_VENDOR
- default "karo"
-
-config SYS_CONFIG_NAME
- default "tk71"
-
-endif
diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS
deleted file mode 100644
index ac85d6b..0000000
--- a/board/karo/tk71/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TK71 BOARD
-#M: -
-S: Maintained
-F: board/karo/tk71/
-F: include/configs/tk71.h
-F: configs/tk71_defconfig
diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile
deleted file mode 100644
index 0e0df77..0000000
--- a/board/karo/tk71/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2012 Marek Vasut <marex@denx.de>
-# on behalf of DENX Software Engineering GmbH
-#
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tk71.o
diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg
deleted file mode 100644
index a32e27c..0000000
--- a/board/karo/tk71/kwbimage.cfg
+++ /dev/null
@@ -1,158 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# adopted to TK71 by
-# Nils Faerber <nils.faerber@kernelconcepts.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000000 # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 01, Cs1width=x16
-# bit7-6: 10, Cs1size=512Mb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000652 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low)
-# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
-# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
-# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
-# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
-# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
-# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT: Enabled
-# bit15: 1, DDR IO ODT Unit: Use ODT block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c
deleted file mode 100644
index 35546d2..0000000
--- a/board/karo/tk71/tk71.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TK71_OE_LOW (~0)
-#define TK71_OE_HIGH (~0)
-#define TK71_OE_VAL_LOW (0)
-#define TK71_OE_VAL_HIGH (0)
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(TK71_OE_VAL_LOW,
- TK71_OE_VAL_HIGH,
- TK71_OE_LOW, TK71_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-
-#define MV88E1116_MAC_CTRL2_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-static void mv_phy_88e1118_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1118 Initialized on %s\n", name);
-}
-
-/* Configure and enable Switch and PHY */
-void reset_phy(void)
-{
- /* configure and initialize PHY */
- mv_phy_88e1118_init("egiga0");
-
-}
-#endif
diff --git a/configs/tk71_defconfig b/configs/tk71_defconfig
deleted file mode 100644
index 5e2a0b8..0000000
--- a/configs/tk71_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_TK71=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/tk71.h b/include/configs/tk71.h
deleted file mode 100644
index 46e8c90..0000000
--- a/include/configs/tk71.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_TK71_H__
-#define __CONFIG_TK71_H__
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nKa-Ro TK71"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define MACH_TYPE_TK71 2399
-#define CONFIG_MACH_TYPE MACH_TYPE_TK71
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * NAND flash
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_DEV "nand0,3"
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0}
-#define CONFIG_PHY_BASE_ADR 0x08
-#endif
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_KIRKWOOD
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_ADDR 0x80000
-#define CONFIG_ENV_OFFSET 0x80000
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
-#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
- "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
- "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
- "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
- "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
-#define MTDIDS_DEFAULT "nand0=orion_nand"
-#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS
-
-#define PHYS_SDRAM_1 0x00000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-
-#endif /* __CONFIG_TK71_H__ */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 35/45] arm: Remove tt01 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (33 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 34/45] arm: Remove tk71 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,35/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 36/45] arm: Remove versatileab board Simon Glass
` (10 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/hale/tt01/Kconfig | 15 ---
board/hale/tt01/MAINTAINERS | 6 -
board/hale/tt01/Makefile | 10 --
board/hale/tt01/lowlevel_init.S | 16 ---
board/hale/tt01/tt01.c | 243 ------------------------------------
configs/tt01_defconfig | 4 -
include/configs/tt01.h | 266 ----------------------------------------
8 files changed, 565 deletions(-)
delete mode 100644 board/hale/tt01/Kconfig
delete mode 100644 board/hale/tt01/MAINTAINERS
delete mode 100644 board/hale/tt01/Makefile
delete mode 100644 board/hale/tt01/lowlevel_init.S
delete mode 100644 board/hale/tt01/tt01.c
delete mode 100644 configs/tt01_defconfig
delete mode 100644 include/configs/tt01.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ab0c24..8529bcd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -234,10 +234,6 @@ config TARGET_MX31PDK
select CPU_ARM1136
select SUPPORT_SPL
-config TARGET_TT01
- bool "Support tt01"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
@@ -857,7 +853,6 @@ source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
-source "board/hale/tt01/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/karo/tx25/Kconfig"
diff --git a/board/hale/tt01/Kconfig b/board/hale/tt01/Kconfig
deleted file mode 100644
index af9828a..0000000
--- a/board/hale/tt01/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TT01
-
-config SYS_BOARD
- default "tt01"
-
-config SYS_VENDOR
- default "hale"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "tt01"
-
-endif
diff --git a/board/hale/tt01/MAINTAINERS b/board/hale/tt01/MAINTAINERS
deleted file mode 100644
index 2f582be..0000000
--- a/board/hale/tt01/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TT01 BOARD
-M: Helmut Raiger <helmut.raiger@hale.at>
-S: Maintained
-F: board/hale/tt01/
-F: include/configs/tt01.h
-F: configs/tt01_defconfig
diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile
deleted file mode 100644
index e06a040..0000000
--- a/board/hale/tt01/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tt01.o
-obj-y += lowlevel_init.o
diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S
deleted file mode 100644
index 54132a1..0000000
--- a/board/hale/tt01/lowlevel_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
- mov pc, lr
diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
deleted file mode 100644
index 011aed0..0000000
--- a/board/hale/tt01/tt01.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13783.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOARD_STRING "Board: HALE TT-01"
-
-/* Clock configuration */
-#define CCM_CCMR_SETUP 0x074B0BF5
-
-static void board_setup_clocks(void)
-{
- struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
- volatile int wait = 0x10000;
-
- writel(CCM_CCMR_SETUP, &ccm->ccmr);
- while (wait--)
- ;
-
- writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
- writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
-
- /* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
- PDR0_MCU_PODF(0), &ccm->pdr0);
- writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
- &ccm->mpctl);
- writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
- &ccm->spctl);
-}
-
-/* DRAM configuration */
-
-#define ESDMISC_MDDR_SETUP 0x00000004
-#define ESDMISC_MDDR_RESET_DL 0x0000000c
-/*
- * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
- * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
- * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- * note: all but tWTR (1), tRC (111) are reset defaults,
- * the same values work in the jtag configuration
- *
- * Bluetechnix setup has 0x75e73a (for 128MB) =
- * 0b 0111 0101 1110 0111 0011 1010
- * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
- * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- */
-#define ESDCFG0_MDDR_SETUP 0x006ac73a
-#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
-#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
- ESDCTL_DSIZ(2) | ESDCTL_BL(1))
-#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
-#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
-#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
-#define ESDCTL_RW ESDCTL_SETTINGS
-
-static void board_setup_sdram(void)
-{
- u32 *pad;
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
- /*
- * setup pad control for the controller pins
- * no loopback, no pull, no keeper, no open drain,
- * standard input, standard drive, slow slew rate
- */
- for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
- pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
- *pad = 0;
-
- /* set up MX31 DDR Memory Controller */
- writel(ESDMISC_MDDR_SETUP, &esdc->misc);
- writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
-
- /* perform DDR init sequence for CSD0 */
- writel(ESDCTL_PRECHARGE, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE+0x0f00);
- writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE);
- writel(0x12344321, CSD0_BASE);
- writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
- writeb(0xda, CSD0_BASE+0x33);
- writeb(0xff, CSD0_BASE+0x1000000);
- writel(ESDCTL_RW, &esdc->ctl0);
- writel(0xDEADBEEF, CSD0_BASE);
- writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
-}
-
-static void tt01_spi3_hw_init(void)
-{
- /* CSPI3 */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
- /* CSPI3, SS0 = Atlas */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
-
- /* start CSPI3 clock (3 = always on except if PLL off) */
- setbits_le32(CCM_CGR0, 3 << 16);
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS4: FPGA incl. network controller */
- struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* this seems essential, won't start without, but why? */
- writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
-
- board_setup_clocks();
- board_setup_sdram();
- mxc_setup_weimcs(4, &cs4);
-
- /* Setup UART2 and SPI3 pins */
- mx31_uart2_hw_init();
- tt01_spi3_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts(BOARD_STRING "\n");
- return 0;
-}
-
-#ifdef CONFIG_MXC_MMC
-int board_mmc_init(bd_t *bis)
-{
- u32 val;
- struct pmic *p;
- int ret;
-
- /*
- * this is the first driver to use the pmic, so call
- * pmic_init() here. board_late_init() is too late for
- * the MMC driver.
- */
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- /* configure pins for SDHC1 only */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
-
- /* turn on power V_MMC1 */
- if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
- pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
-
- return mxc_mmc_init(bis);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-void video_get_info_str(int line_number, char *info)
-{
- u32 srev = get_cpu_rev();
-
- switch (line_number) {
- case 2:
- sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s@%d MHz",
- (srev & 0xF0) >> 4, (srev & 0x0F),
- ((srev & 0x8000) ? " unknown" : ""),
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- break;
- case 3:
- strcpy(info, " " BOARD_STRING);
- break;
- default:
- info[0] = 0;
- }
-}
-#endif
diff --git a/configs/tt01_defconfig b/configs/tt01_defconfig
deleted file mode 100644
index 08f9f7b..0000000
--- a/configs/tt01_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TT01=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="TT01> "
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
deleted file mode 100644
index ca1e2e2..0000000
--- a/include/configs/tt01.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * Configuration settings for the HALE TT-01 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-
-/*
- * Physical Memory Map:
- * CS settings are defined by i.MX31:
- * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
- * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
- * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
- *
- * HALE set-up of the bluetechnix board for now is:
- * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
- * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
- * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
- * the flash chip is a mirrorbit S29WS256N !
- * - the PSRAM is hooked to CS5 (0xB6000000)
- * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
- * - 64Mbit = 8MByte (will go away in the production set-up)
- * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
- * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
- * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
- *
- * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
- * is not used right now. We should be able to reduce the SOM to NAND flash
- * only and boot from there.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-/* default load address, 1MB up the road */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
-
-/* Size of malloc() pool, make sure possible frame buffer fits */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
-
-/* memtest works on all but the last 1MB (u-boot) and malloc area */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END \
- (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
-
-/* CFI FLASH driver setup */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-/*
- * TODO: Bluetechnix (the supplier of the SOM) did define these values
- * in their original version of u-boot (1.2 or so). This should be
- * reviewed.
- *
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- * #define CONFIG_SYS_FLASH_PROTECTION
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
-
-/*
- * FLASH and environment organization, only the Spansion chip is supported:
- * - it has 254 * 128kB + 8 * 32kB blocks
- * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
- * and 2 sectors with 128k as environment =
- * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
- * - this could be less, but this is only for developer versions of the board
- * and no-one is going to use the NOR flash anyway.
- *
- * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
- * way to large, but it avoids ENV overwrite (when updating u-boot) in case
- * size breaks the next boundary (as it has with 128k).
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/* Hardware drivers */
-
-/*
- * on TT-01 UART1 pins are used by Audio, so we use UART2
- * TT-01 implements a hardware that turns off components depending on
- * the power level. In PL=1 the RS232 transceiver is usually off,
- * make sure that the transceiver is enabled during PL=1 for testing!
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-#define CONFIG_MXC_SPI
-#define CONFIG_MXC_GPIO
-
-/* MC13783 connected to CSPI3 and SS0 */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-
-#define CONFIG_FSL_PMIC_BUS 2
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-/* console is UART2 on TT-01 */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* ethernet setup for the onboard smc9118 */
-#define CONFIG_MII
-#define CONFIG_SMC911X
-/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
-#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
-#define CONFIG_SMC911X_16_BIT
-
-/* mmc driver */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
-#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
-
-/* video support */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-/* splash image won't work with NAND boot, use preboot script */
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
-#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
-
-/* allow stdin, stdout and stderr variables to redirect output */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
-#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
-#define CONFIG_PREBOOT
-
-/* allow decompressing max. 4MB */
-#define CONFIG_VIDEO_BMP_GZIP
-/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
-
-/*
- * Command definition
- */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-/*
- * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
- * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
- * a software locking scheme.
- */
-#define CONFIG_CMD_BMP
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * currently a default setting for booting via script is implemented
- * set user to login name and serverip to tftp host, define your
- * boot behaviour in bootscript.loginname
- *
- * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
- *
- * This set-up is for the L5F30947T04 by Epson, which is
- * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
- * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"videomode=epson\0" \
-"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
- "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
-"bootcmd=dhcp bootscript.${user}; source\0"
-
-#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
-#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_CMDLINE_EDITING
-
-/* MMC boot support */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-#define CONFIG_NAND_MXC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*
- * actually this is nothing someone wants to configure!
- * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
- * is not used by the driver.
- */
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-
-/* the current u-boot driver does not use the nand flash setup! */
-#define CONFIG_SYS_NAND_LARGEPAGE
-/*
- * it's not 16 bit:
- * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- * the current u-boot mxc_nand.c tries to auto-detect, but this only
- * reads the boot settings during reset (which might be wrong)
- */
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 36/45] arm: Remove versatileab board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (34 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 35/45] arm: Remove tt01 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,36/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 37/45] arm: Remove vision2 board Simon Glass
` (9 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 8 +-
arch/arm/Makefile | 1 -
arch/arm/mach-versatile/Kconfig | 15 ---
board/armltd/versatile/MAINTAINERS | 8 --
board/armltd/versatile/Makefile | 9 --
board/armltd/versatile/lowlevel_init.S | 17 ---
board/armltd/versatile/versatile.c | 99 ---------------
configs/versatileab_defconfig | 18 ---
configs/versatilepb_defconfig | 18 ---
configs/versatileqemu_defconfig | 18 ---
include/configs/versatile.h | 214 ---------------------------------
11 files changed, 1 insertion(+), 424 deletions(-)
delete mode 100644 arch/arm/mach-versatile/Kconfig
delete mode 100644 board/armltd/versatile/MAINTAINERS
delete mode 100644 board/armltd/versatile/Makefile
delete mode 100644 board/armltd/versatile/lowlevel_init.S
delete mode 100644 board/armltd/versatile/versatile.c
delete mode 100644 configs/versatileab_defconfig
delete mode 100644 configs/versatilepb_defconfig
delete mode 100644 configs/versatileqemu_defconfig
delete mode 100644 include/configs/versatile.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8529bcd..e64c0b7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,7 +64,7 @@ config SEMIHOSTING
choice
prompt "Target select"
- default ARCH_VERSATILE
+ default TARGET_HIKEY
config ARCH_AT91
bool "Atmel AT91"
@@ -217,10 +217,6 @@ config TARGET_X600
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_VERSATILE
- bool "ARM Ltd. Versatile family"
- select CPU_ARM926EJS
-
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
@@ -787,8 +783,6 @@ source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
-source "arch/arm/mach-versatile/Kconfig"
-
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e84d6d3..9f0872b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -57,7 +57,6 @@ machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
-machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
deleted file mode 100644
index d2e76f4..0000000
--- a/arch/arm/mach-versatile/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if ARCH_VERSATILE
-
-config SYS_BOARD
- default "versatile"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_SOC
- default "versatile"
-
-config SYS_CONFIG_NAME
- default "versatile"
-
-endif
diff --git a/board/armltd/versatile/MAINTAINERS b/board/armltd/versatile/MAINTAINERS
deleted file mode 100644
index a56dd99..0000000
--- a/board/armltd/versatile/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-VERSATILE BOARD
-#M: -
-S: Maintained
-F: board/armltd/versatile/
-F: include/configs/versatile.h
-F: configs/versatileab_defconfig
-F: configs/versatilepb_defconfig
-F: configs/versatileqemu_defconfig
diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile
deleted file mode 100644
index a09a0ae..0000000
--- a/board/armltd/versatile/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := versatile.o
-obj-y += lowlevel_init.o
diff --git a/board/armltd/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S
deleted file mode 100644
index 539ba41..0000000
--- a/board/armltd/versatile/lowlevel_init.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* All done by Versatile's boot monitor! */
- mov pc, lr
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
deleted file mode 100644
index 4e2d342..0000000
--- a/board/armltd/versatile/versatile.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f (void)
-{
- /*
- * set clock frequency:
- * VERSATILE_REFCLK is 32KHz
- * VERSATILE_TIMCLK is 1MHz
- */
- *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
- ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
- (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
-
- return 0;
-}
-
-int board_init (void)
-{
- /* arch number of Versatile Board */
-#ifdef CONFIG_ARCH_VERSATILE_AB
- gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB;
-#else
- gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- gd->flags = 0;
-
- icache_enable ();
-
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- setenv("verify", "n");
- return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/configs/versatileab_defconfig b/configs/versatileab_defconfig
deleted file mode 100644
index 3dc7d19..0000000
--- a/configs/versatileab_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
diff --git a/configs/versatilepb_defconfig b/configs/versatilepb_defconfig
deleted file mode 100644
index 9fe83b9..0000000
--- a/configs/versatilepb_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
diff --git a/configs/versatileqemu_defconfig b/configs/versatileqemu_defconfig
deleted file mode 100644
index 9ddef4d..0000000
--- a/configs/versatileqemu_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
deleted file mode 100644
index 636ca43..0000000
--- a/include/configs/versatile.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Versatile PB.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
-#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
-
-#define CONFIG_SYS_MEMTEST_START 0x100000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-
-#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
-#define CONFIG_SYS_TIMER_RATE (1000000 / 256)
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
-/*
- * control registers
- */
-#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK 0
-#define VERSATILE_TIMCLK 1
-
-#define VERSATILE_TIMER1_EnSel 15
-#define VERSATILE_TIMER2_EnSel 17
-#define VERSATILE_TIMER3_EnSel 19
-#define VERSATILE_TIMER4_EnSel 21
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE 8192
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_SMC91111
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE 0x10010000
-#undef CONFIG_SMC91111_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS \
- {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_CONS_INDEX 0
-
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_SYS_SERIAL0 0x101F1000
-#define CONFIG_SYS_SERIAL1 0x101F2000
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
- "netdev=25,0,0xf1010000,0xf1010010,eth0 "\
- "console=ttyAMA0,38400n1"
-
-/*
- * Static configuration when assigning fixed address
- */
-#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Monitor Command Prompt */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_ARCH_VERSATILE_AB
-# define CONFIG_SYS_PROMPT "VersatileAB # "
-#else
-# define CONFIG_SYS_PROMPT "VersatilePB # "
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef CONFIG_ARCH_VERSATILE_QEMU
-#define CONFIG_SYS_TEXT_BASE 0x10000
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x01000000
-/*
- * Use the CFI flash driver for ease of use
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_ENV_IS_IN_FLASH 1
-/*
- * System control register
- */
-#define VERSATILE_SYS_BASE 0x10000000
-#define VERSATILE_SYS_FLASH_OFFSET 0x4C
-#define VERSATILE_FLASHCTRL \
- (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-/* Enable writing to flash */
-#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/*
- * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
- * i.e.
- * the bottom "sector" (bottom boot), or top "sector"
- * (top boot), is a seperate erase region divided into
- * 4 (equal) smaller sectors. This, notionally, allows
- * quicker erase/rewrire of the most frequently changed
- * area......
- * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
- */
-
-#ifdef CONFIG_ARCH_VERSATILE_AB
-#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
-#define CONFIG_SYS_MAX_FLASH_SECT (520)
-#endif
-
-#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
-#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
-#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
-#define CONFIG_SYS_MAX_FLASH_SECT (260)
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0x34000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
-
-/* The ARM Boot Monitor is shipped in the lowest sector of flash */
-
-#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
-#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 37/45] arm: Remove vision2 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (35 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 36/45] arm: Remove versatileab board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 6:40 ` Stefano Babic
2015-09-12 12:50 ` [U-Boot] [U-Boot,37/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 38/45] arm: Remove vl_ma2sc board Simon Glass
` (8 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/ttcontrol/vision2/Kconfig | 15 -
board/ttcontrol/vision2/MAINTAINERS | 6 -
board/ttcontrol/vision2/Makefile | 9 -
board/ttcontrol/vision2/imximage_hynix.cfg | 212 -----------
board/ttcontrol/vision2/vision2.c | 572 -----------------------------
configs/vision2_defconfig | 7 -
doc/README.watchdog | 1 +
include/configs/vision2.h | 199 ----------
9 files changed, 1 insertion(+), 1025 deletions(-)
delete mode 100644 board/ttcontrol/vision2/Kconfig
delete mode 100644 board/ttcontrol/vision2/MAINTAINERS
delete mode 100644 board/ttcontrol/vision2/Makefile
delete mode 100644 board/ttcontrol/vision2/imximage_hynix.cfg
delete mode 100644 board/ttcontrol/vision2/vision2.c
delete mode 100644 configs/vision2_defconfig
delete mode 100644 include/configs/vision2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e64c0b7..1a440b7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -463,10 +463,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
-config TARGET_VISION2
- bool "Support vision2"
- select CPU_V7
-
config TARGET_UDOO
bool "Support udoo"
select CPU_V7
@@ -883,7 +879,6 @@ source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
-source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
diff --git a/board/ttcontrol/vision2/Kconfig b/board/ttcontrol/vision2/Kconfig
deleted file mode 100644
index cacd2c5..0000000
--- a/board/ttcontrol/vision2/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_VISION2
-
-config SYS_BOARD
- default "vision2"
-
-config SYS_VENDOR
- default "ttcontrol"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "vision2"
-
-endif
diff --git a/board/ttcontrol/vision2/MAINTAINERS b/board/ttcontrol/vision2/MAINTAINERS
deleted file mode 100644
index cfc9903..0000000
--- a/board/ttcontrol/vision2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VISION2 BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/ttcontrol/vision2/
-F: include/configs/vision2.h
-F: configs/vision2_defconfig
diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile
deleted file mode 100644
index c3e1e87..0000000
--- a/board/ttcontrol/vision2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := vision2.o
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
deleted file mode 100644
index c74973e..0000000
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic at denx.de.
- *
- * (C) Copyright 2010
- * Klaus Steinhammer TTECH Control Gmbh kst at tttech.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, nand, onenand, sd
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * #######################
- * ### Disable WDOG ###
- * #######################
- */
-DATA 2 0x73f98000 0x30
-
-/*
- * #######################
- * ### SET DDR Clk ###
- * #######################
- */
-/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
-DATA 4 0x73FD4018 0x000024C0
-
-/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
-DATA 4 0x73FD4038 0x2010241
-
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8600 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8604 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8608 0x00000187
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa860c 0x00000187
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8614 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
-DATA 4 0x73fa86a8 0x00000187
-
-/*
- * #######################
- * ### Settings IOMUXC ###
- * #######################
- */
-/*
- * DDR IOMUX configuration
- * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
- * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
- */
-DATA 4 0x73fa84b8 0x000000e7
-/* PVTC MAX (at GPC, PGR reg) */
-/* DATA 4 0x73FD8004 0x1fc00000 */
-
-/* DQM0 DS high slew rate slow */
-DATA 4 0x73fa84d4 0x000000e4
-/* DQM1 DS high slew rate slow */
-DATA 4 0x73fa84d8 0x000000e4
-/* DQM2 DS high slew rate slow */
-DATA 4 0x73fa84dc 0x000000e4
-/* DQM3 DS high slew rate slow */
-DATA 4 0x73fa84e0 0x000000e4
-
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
-DATA 4 0x73fa84bc 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
-DATA 4 0x73fa84c0 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
-DATA 4 0x73fa84c4 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
-DATA 4 0x73fa84c8 0x000000c4
-
-/* DRAM_DATA B0 */
-DATA 4 0x73fa88a4 0x00000004
-/* DRAM_DATA B1 */
-DATA 4 0x73fa88ac 0x00000004
-/* DRAM_DATA B2 */
-DATA 4 0x73fa88b8 0x00000004
-/* DRAM_DATA B3 */
-DATA 4 0x73fa882c 0x00000004
-
-/* DRAM_DATA B0 slew rate */
-DATA 4 0x73fa8878 0x00000000
-/* DRAM_DATA B1 slew rate */
-DATA 4 0x73fa8880 0x00000000
-/* DRAM_DATA B2 slew rate */
-DATA 4 0x73fa888c 0x00000000
-/* DRAM_DATA B3 slew rate */
-DATA 4 0x73fa889c 0x00000000
-
-/*
- * #######################
- * ### Configure SDRAM ###
- * #######################
- */
-
-/* Configure CS0 */
-/* ####################### */
-
-/* ESDCTL0: Enable controller */
-DATA 4 0x83fd9000 0x83220000
-
-/* Init DRAM on CS0 */
-/* ESDSCR: Precharge command */
-DATA 4 0x83fd9014 0x04008008
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008010
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008010
-/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
-DATA 4 0x83fd9014 0x00338018
-/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
-DATA 4 0x83fd9014 0x0020801a
-/* ESDSCR */
-DATA 4 0x83fd9014 0x00008000
-
-/* ESDSCR: EMR with full Drive strength */
-/* DATA 4 0x83fd9014 0x0000801a */
-
-/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
-DATA 4 0x83fd9000 0xC3220000
-
-/*
- * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
- * DATA 4 0x83fd9004 0xC33574AA
- */
-/*
- * micron mDDR
- * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- * DATA 4 0x83FD9004 0x101564a8
- */
-/*
- * hynix mDDR
- * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- */
-DATA 4 0x83FD9004 0x704564a8
-
-/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
-DATA 4 0x83fd9010 0x000a1700
-
-/* Configure CS1 */
-/* ####################### */
-
-/* ESDCTL1: Enable controller */
-DATA 4 0x83fd9008 0x83220000
-
-/* Init DRAM on CS1 */
-/* ESDSCR: Precharge command */
-DATA 4 0x83fd9014 0x0400800c
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008014
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008014
-/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
-DATA 4 0x83fd9014 0x0033801c
-/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
-DATA 4 0x83fd9014 0x0020801e
-/* ESDSCR */
-DATA 4 0x83fd9014 0x00008004
-
-/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
-DATA 4 0x83fd9008 0xC3220000
-/*
- * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
- * DATA 4 0x83fd900c 0xC33574AA
- */
-/*
- * micron mDDR
- * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- * DATA 4 0x83FD900C 0x101564a8
- */
-/*
- * hynix mDDR
- * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- */
-DATA 4 0x83FD900C 0x704564a8
-
-/* ESDSCR (mDRAM configuration finished) */
-DATA 4 0x83FD9014 0x00000004
-
-/* ESDSCR - clear "configuration request" bit */
-DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
deleted file mode 100644
index 247991d..0000000
--- a/board/ttcontrol/vision2/vision2.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/spi.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <power/pmic.h>
-#include <fsl_esdhc.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-#include <linux/fb.h>
-
-#include <ipu_pixfmt.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct fb_videomode const nec_nl6448bc26_09c = {
- "NEC_NL6448BC26-09C",
- 60, /* Refresh */
- 640, /* xres */
- 480, /* yres */
- 37650, /* pixclock = 26.56Mhz */
- 48, /* left margin */
- 16, /* right margin */
- 31, /* upper margin */
- 12, /* lower margin */
- 96, /* hsync-len */
- 2, /* vsync-len */
- 0, /* sync */
- FB_VMODE_NONINTERLACED, /* vmode */
- 0, /* flag */
-};
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-void hw_watchdog_reset(void)
-{
- int val;
-
- /* toggle watchdog trigger pin */
- val = gpio_get_value(IMX_GPIO_NR(3, 2));
- val = val ? 0 : 1;
- gpio_set_value(IMX_GPIO_NR(3, 2), val);
-}
-#endif
-
-static void init_drive_strength(void)
-{
- static const iomux_v3_cfg_t ddr_pads[] = {
- NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
- NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
- NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
- NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
- NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
-
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-static void setup_weim(void)
-{
- struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
-
- pweim->cs0gcr1 = 0x004100b9;
- pweim->cs0gcr2 = 0x00000001;
- pweim->cs0rcr1 = 0x0a018000;
- pweim->cs0rcr2 = 0;
- pweim->cs0wcr1 = 0x0704a240;
-}
-
-static void setup_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
- MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 1) ? 121 : -1;
-}
-
-void spi_io_init(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-static void reset_peripherals(int reset)
-{
-#ifdef CONFIG_VISION2_HW_1_0
- static const iomux_v3_cfg_t fec_cfg_pads[] = {
- /* RXD1 */
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
- /* RXD2 */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
- /* RXD3 */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
- /* RXER */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
- /* COL */
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
- /* RCLK */
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
- /* RXD0 */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
- MX51_PAD_NANDF_D9__FEC_RDATA0,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
- MX51_PAD_EIM_CS4__FEC_RX_ER,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
- };
-#endif
-
- if (reset) {
-
- /* reset_n is on NANDF_D15 */
- gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
-
-#ifdef CONFIG_VISION2_HW_1_0
- /*
- * set FEC Configuration lines
- * set levels of FEC config lines
- */
- gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
- gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
-
- /* set direction of FEC config lines */
- gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
-
- imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
- ARRAY_SIZE(fec_cfg_pads));
-#endif
-
- /* activate reset_n pin */
- imx_iomux_v3_setup_pad(
- NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
- PAD_CTL_DSE_MAX));
- } else {
- /* set FEC Control lines */
- gpio_direction_input(IMX_GPIO_NR(3, 25));
- udelay(500);
-
-#ifdef CONFIG_VISION2_HW_1_0
- imx_iomux_v3_setup_multiple_pads(fec_pads,
- ARRAY_SIZE(fec_pads));
-#endif
- }
-}
-
-static void power_init_mx51(void)
-{
- unsigned int val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return;
-
- /* Write needed to Power Gate 2 register */
- pmic_reg_read(p, REG_POWER_MISC, &val);
-
- /* enable VCAM with 2.775V to enable read from PMIC */
- val = VCAMCONFIG | VCAMEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- /*
- * Set switchers in Auto in NORMAL mode & STANDBY mode
- * Setup the switcher mode for SW1 & SW2
- */
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
- (SWMODE_MASK << SWMODE3_SHIFT));
- val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
-
- /* Set VGEN3 to 1.8V, VCAM to 3.0V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VCAM_MASK | VGEN3_MASK);
- val |= VCAM_3_0;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
- pmic_reg_read(p, REG_SETTING_1, &val);
- val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
- val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
- pmic_reg_write(p, REG_SETTING_1, val);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(p, REG_MODE_1, val);
- udelay(200);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
- VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- pmic_reg_read(p, REG_POWER_CTL2, &val);
- val |= WDIRESET;
- pmic_reg_write(p, REG_POWER_CTL2, val);
-
- udelay(2500);
-
-}
-#endif
-
-static void setup_gpios(void)
-{
- static const iomux_v3_cfg_t gpio_pads_1[] = {
- NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* DAB Display EN */
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
- };
-
- static const iomux_v3_cfg_t gpio_pads_2[] = {
- NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* Display2 TxEN */
- NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* DAB Light EN */
- NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* AUDIO_MUTE */
- NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* SPARE_OUT */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* BEEPER_EN */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* POWER_OFF */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* FRAM_WE */
- NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* EXPANSION_EN */
- MX51_PAD_GPIO1_2__PWM1_PWMO,
- };
-
- unsigned int i;
-
- imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
-
- /* Now we need to trigger the watchdog */
- WATCHDOG_RESET();
-
- imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
-
- /*
- * Set GPIO1_4 to high and output; it is used to reset
- * the system on reboot
- */
- gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
-
- gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
- for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
- gpio_direction_output(i, 0);
-
- gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
-
- /* Set POWER_OFF high */
- gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
-
- gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
-
- gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
-
- gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
-
- WATCHDOG_RESET();
-}
-
-static void setup_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- MX51_PAD_NANDF_CS3__FEC_MDC,
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
- MX51_PAD_NANDF_D9__FEC_RDATA0,
- MX51_PAD_NANDF_CS6__FEC_TDATA3,
- MX51_PAD_NANDF_CS5__FEC_TDATA2,
- MX51_PAD_NANDF_CS4__FEC_TDATA1,
- MX51_PAD_NANDF_D8__FEC_TDATA0,
- MX51_PAD_NANDF_CS7__FEC_TX_EN,
- MX51_PAD_NANDF_CS2__FEC_TX_ER,
- MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
- MX51_PAD_EIM_CS5__FEC_CRS,
- MX51_PAD_EIM_CS4__FEC_RX_ER,
- NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR},
-};
-
-int get_mmc_getcd(u8 *cd, struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
- else
- *cd = 0;
-
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
- PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
- };
-
- imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
-void lcd_enable(void)
-{
- static const iomux_v3_cfg_t lcd_pads[] = {
- MX51_PAD_DI1_PIN2__DI1_PIN2,
- MX51_PAD_DI1_PIN3__DI1_PIN3,
- };
-
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-
- gpio_set_value(IMX_GPIO_NR(1, 2), 1);
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
- NO_PAD_CTRL));
-
- ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
- if (ret)
- puts("LCD cannot be configured\n");
-}
-
-int board_early_init_f(void)
-{
-
-
- init_drive_strength();
-
- /* Setup debug led */
- gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
-
- /* wait a little while to give the pll time to settle */
- sdelay(100000);
-
- setup_weim();
- setup_uart();
- setup_fec();
- setup_gpios();
-
- spi_io_init();
-
- return 0;
-}
-
-static void backlight(int on)
-{
- if (on) {
- gpio_set_value(IMX_GPIO_NR(3, 1), 1);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(3, 4), 1);
- } else {
- gpio_set_value(IMX_GPIO_NR(3, 1), 0);
- gpio_set_value(IMX_GPIO_NR(3, 4), 0);
- }
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- lcd_enable();
-
- backlight(1);
-
- return 0;
-}
-
-int board_late_init(void)
-{
- power_init_mx51();
-
- reset_peripherals(1);
- udelay(2000);
- reset_peripherals(0);
- udelay(2000);
-
- /* Early revisions require a second reset */
-#ifdef CONFIG_VISION2_HW_1_0
- reset_peripherals(1);
- udelay(2000);
- reset_peripherals(0);
- udelay(2000);
-#endif
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int checkboard(void)
-{
- puts("Board: TTControl Vision II CPU V\n");
-
- return 0;
-}
-
-int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int on;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- on = (strcmp(argv[1], "on") == 0);
- backlight(on);
-
- return 0;
-}
-
-U_BOOT_CMD(
- lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
- "Vision2 Backlight",
- "lcdbl [on|off]\n"
-);
diff --git a/configs/vision2_defconfig b/configs/vision2_defconfig
deleted file mode 100644
index 962dc5b..0000000
--- a/configs/vision2_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VISION2=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="Vision II U-boot > "
diff --git a/doc/README.watchdog b/doc/README.watchdog
index 59f306b..b66fd6c 100644
--- a/doc/README.watchdog
+++ b/doc/README.watchdog
@@ -27,6 +27,7 @@ CONFIG_IMX_WATCHDOG
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
their own hw_watchdog_reset routine.
+ TODO: vision2 is removed now, so perhaps this can be changed.
CONFIG_XILINX_TB_WATCHDOG
Available for Xilinx Axi platforms to service timebase watchdog timer.
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
deleted file mode 100644
index b43373f..0000000
--- a/include/configs/vision2.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX51-3Stack Freescale board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_SYS_TEXT_BASE 0x97800000
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_LATE_INIT
-
-#ifndef MACH_TYPE_TTC_VISION2
-#define MACH_TYPE_TTC_VISION2 2775
-#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_MXC_GPIO
-#define CONFIG_MXC_SPI
-#define CONFIG_HW_WATCHDOG
-
- /*
- * SPI Configs
- * */
-#define CONFIG_FSL_SF
-#define CONFIG_CMD_SF
-
-#define CONFIG_SPI_FLASH_STMICRO
-
-/*
- * Use gpio 4 pin 25 as chip select for SPI flash
- * This corresponds to gpio 121
- */
-#define CONFIG_SF_DEFAULT_CS 1
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
-#define CONFIG_ENV_SIZE (4 * 1024)
-
-#define CONFIG_FSL_ENV_IN_SF
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 0
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 2500000
-#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MMC Configs
- */
-#define CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-#define CONFIG_MMC
-
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_CMD_DATE
-
-/*
- * Eth Configs
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_MII
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#define CONFIG_CMD_SPI
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=0x90800000\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* 166 MHz DDR RAM */
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
-#define CONFIG_SYS_MAIN_PWR_ON
-
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * Framebuffer and LCD
- */
-#define CONFIG_PREBOOT
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#define CONFIG_IPUV3_CLK 133000000
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 38/45] arm: Remove vl_ma2sc board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (36 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 37/45] arm: Remove vision2 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,38/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 39/45] arm: Remove vpac270_nor_128 board Simon Glass
` (7 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 5 -
board/BuS/vl_ma2sc/Kconfig | 12 -
board/BuS/vl_ma2sc/MAINTAINERS | 7 -
board/BuS/vl_ma2sc/Makefile | 12 -
board/BuS/vl_ma2sc/vl_ma2sc.c | 519 -----------------------------------------
configs/vl_ma2sc_defconfig | 9 -
configs/vl_ma2sc_ram_defconfig | 9 -
include/configs/vl_ma2sc.h | 429 ----------------------------------
8 files changed, 1002 deletions(-)
delete mode 100644 board/BuS/vl_ma2sc/Kconfig
delete mode 100644 board/BuS/vl_ma2sc/MAINTAINERS
delete mode 100644 board/BuS/vl_ma2sc/Makefile
delete mode 100644 board/BuS/vl_ma2sc/vl_ma2sc.c
delete mode 100644 configs/vl_ma2sc_defconfig
delete mode 100644 configs/vl_ma2sc_ram_defconfig
delete mode 100644 include/configs/vl_ma2sc.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index ba1b4f4..6087d01 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -91,10 +91,6 @@ config TARGET_SAMA5D4EK
select CPU_V7
select SUPPORT_SPL
-config TARGET_VL_MA2SC
- bool "Support vl_ma2sc"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
@@ -128,7 +124,6 @@ source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig
deleted file mode 100644
index 848177f..0000000
--- a/board/BuS/vl_ma2sc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VL_MA2SC
-
-config SYS_BOARD
- default "vl_ma2sc"
-
-config SYS_VENDOR
- default "BuS"
-
-config SYS_CONFIG_NAME
- default "vl_ma2sc"
-
-endif
diff --git a/board/BuS/vl_ma2sc/MAINTAINERS b/board/BuS/vl_ma2sc/MAINTAINERS
deleted file mode 100644
index b70104d..0000000
--- a/board/BuS/vl_ma2sc/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-VL_MA2SC BOARD
-M: Jens Scharsig <esw@bus-elektronik.de>
-S: Maintained
-F: board/BuS/vl_ma2sc/
-F: include/configs/vl_ma2sc.h
-F: configs/vl_ma2sc_defconfig
-F: configs/vl_ma2sc_ram_defconfig
diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile
deleted file mode 100644
index d4b24ac..0000000
--- a/board/BuS/vl_ma2sc/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2009-2012
-# Jens Scharsig <esw@bus-elekronik.de>
-# BuS Elektronik GmbH & Co. KG
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += vl_ma2sc.o
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
deleted file mode 100644
index e4e1a85..0000000
--- a/board/BuS/vl_ma2sc/vl_ma2sc.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_common.h>
-#include <lcd.h>
-#include <i2c.h>
-#include <atmel_lcdc.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NAND
-static void vl_ma2sc_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
- at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
- at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
-
- /* Enable CS3 */
- csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa[0]);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
-
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
-
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
- writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
- &pmc->pcer);
-
- /* Configure RDY/BSY */
-#ifdef CONFIG_SYS_NAND_READY_PIN
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-#endif
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void vl_ma2sc_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 320,
- .vl_row = 240,
- .vl_clk = 6500000,
- .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
- ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVVD_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
- .vl_tft = 1,
- .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
- .vl_left_margin = 68, /* horiz back porch */
- .vl_right_margin = 20, /* horiz front porch */
- .vl_vsync_len = 2, /* vert Sync Pulse Width */
- .vl_upper_margin = 18, /* vert back porch */
- .vl_lower_margin = 4, /* vert front porch */
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-static void vl_ma2sc_lcd_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
- at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
-
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
-
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
-
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
-
- at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
-
- at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
- at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
- at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
- at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
- at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
- at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
-
- at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
- gd->fb_base = ATMEL_BASE_SRAM0;
-}
-#endif /* Config LCD */
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-#endif
-
-int board_init(void)
-{
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin;
-
- pin = 0x1F000001;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
- writel((1 << 25), &pio->pioa.codr);
-
- pin = 0x1F000100;
- writel(pin, &pio->piob.idr);
- writel(pin, &pio->piob.pudr);
- writel(pin, &pio->piob.per);
- writel(pin, &pio->piob.oer);
- writel(pin, &pio->piob.codr);
- writel((1 << 24), &pio->piob.sodr);
-
- pin = 0x40000000; /* Pullup DRxD enbable */
- writel(pin, &pio->pioc.puer);
-
- pin = 0x0000000F; /* HWversion als Input */
- writel(pin, &pio->piod.idr);
- writel(pin, &pio->piod.puer);
- writel(pin, &pio->piod.per);
- writel(pin, &pio->piod.odr);
- writel(pin, &pio->piod.owdr);
-
- gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
- writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
- writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
- writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
-
-#ifdef CONFIG_CMD_NAND
- vl_ma2sc_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- vl_ma2sc_macb_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
- at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
- vl_ma2sc_lcd_hw_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- uchar buffer[8];
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin;
-
- buffer[0] = 0x04;
- buffer[1] = 0x00;
- if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
- puts("error reseting rtc clock\n\0");
-
- /* read hardware version */
-
- pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
- printf("Board: revision %c\n", pin);
- buffer[0] = pin;
- buffer[1] = 0;
- setenv("revision", (char *) buffer);
-
- pin = 0x40000000; /* Pullup DRxD enbable */
- writel(pin, &pio->pioc.puer);
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init();
-#endif
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
-#endif
- return rc;
-}
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
- u32 pin;
-
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u8 sda = (1<<4);
- u8 scl = (1<<5);
-
- writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
- pin = sda | scl;
- writel(pin, &pio->piob.idr); /* Disable Interupt */
- writel(pin, &pio->piob.pudr);
- writel(pin, &pio->piob.per);
- writel(pin, &pio->piob.oer);
- writel(pin, &pio->piob.sodr);
-}
-#endif
-
-void watchdog_reset(void)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin = 0x1; /* PA0 */
-
- if ((readl(&pio->pioa.odsr) & pin) > 0)
- writel(pin, &pio->pioa.codr);
- else
- writel(pin, &pio->pioa.sodr);
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
-/*---------------------------------------------------------------------------*/
-
-int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- int row;
- int col;
- u32 pinz;
- u32 pins;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
-
- pins = 0x1F000000;
- writel(pins, &pio->pioa.idr);
- writel(pins, &pio->pioa.pudr);
- writel(pins, &pio->pioa.per);
- writel(pins, &pio->pioa.oer);
- writel(pins, &pio->pioa.sodr);
-
- pinz = 0x1F000000;
- writel(pinz, &pio->piob.idr);
- writel(pinz, &pio->piob.pudr);
- writel(pinz, &pio->piob.per);
- writel(pinz, &pio->piob.oer);
- writel(pinz, &pio->piob.sodr);
-
- for (row = 0; row < 5; row++) {
- for (col = 0; col < 5; col++) {
- writel((0x01000000 << col), &pio->piob.sodr);
- writel((0x01000000 << row), &pio->pioa.codr);
- printf("LED Test %d x %d\n", row, col);
- udelay(1000000);
- writel(pinz, &pio->piob.codr);
- writel(pins, &pio->pioa.sodr);
- }
- }
- return rcode;
-}
-
-void poweroff(void)
-{
- watchdog_reset();
- at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
- udelay(100);
- at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
- udelay(100);
- at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
- udelay(100);
- while (1)
- watchdog_reset();
-}
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- poweroff();
- return rcode;
-}
-
-int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- u32 freq;
- u32 durate;
- int rcode = 1;
-
- freq = 1000;
- durate = 2;
- switch (argc) {
- case 3:
- durate = simple_strtoul(argv[2], NULL, 10);
- case 2:
- freq = simple_strtoul(argv[1], NULL, 10);
- case 1:
- break;
- default:
- cmd_usage(cmdtp);
- rcode = 1;
- break;
- }
- durate = durate * freq;
- freq = 500000 / freq;
- for (i = 0; i < durate; i++) {
- at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
- udelay(freq);
- at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
- udelay(freq);
- }
- at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
- return rcode;
-}
-
-int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- int row;
- u32 col;
- u32 pinz;
- u32 pins;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
-
- pins = 0x001F0000;
- writel(pins, &pio->pioa.idr);
- writel(pins, &pio->pioa.pudr);
- writel(pins, &pio->pioa.per);
- writel(pins, &pio->pioa.odr);
-
- pinz = 0x000F0000;
- writel(pinz, &pio->piob.idr);
- writel(pinz, &pio->piob.pudr);
- writel(pinz, &pio->piob.per);
- writel(pinz, &pio->piob.oer);
- writel(pinz, &pio->piob.codr);
-
- while (1) {
- col = 0;
- for (row = 0; row < 4; row++) {
- writel((0x00010000 << row), &pio->piob.sodr);
- udelay(10000);
- col <<= 4;
- col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
- writel(pinz, &pio->piob.codr);
- }
- printf("Matix: ");
- for (row = 0; row < 16; row++) {
- printf("%1.1d", col & 1);
- col >>= 1;
- }
- printf(" SP %d\r ",
- 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
- /* SHUTDOWN */
- row = 0;
- while (row < 1000) {
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
- row++;
- udelay(100);
- }
- udelay(100000);
- row = 0;
- while (row < 1000) {
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
- row++;
- udelay(1000);
- }
- }
- poweroff();
- while (1)
- ;
- }
- }
- return rcode;
-}
-
-/*****************************************************************************/
-
-U_BOOT_CMD(
- ledtest, 1, 0, do_ledtest,
- "test ledmatrix",
- "\n"
- );
-
-U_BOOT_CMD(
- keytest, 1, 0, do_keytest,
- "test keymatix and special keys, poweroff on pressing ON key",
- "\n"
- );
-
-U_BOOT_CMD(
- poweroff, 1, 0, do_poweroff,
- "power off",
- "\n"
- );
-
-U_BOOT_CMD(
- beep, 3, 0, do_beep,
- "[freq [duration]]",
- "freq frequence of beep\nduration duration of beep\n"
- );
-
-/*****************************************************************************/
diff --git a/configs/vl_ma2sc_defconfig b/configs/vl_ma2sc_defconfig
deleted file mode 100644
index c908c6e..0000000
--- a/configs/vl_ma2sc_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/vl_ma2sc_ram_defconfig b/configs/vl_ma2sc_ram_defconfig
deleted file mode 100644
index 43a576f..0000000
--- a/configs/vl_ma2sc_ram_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
deleted file mode 100644
index 3facd7f..0000000
--- a/include/configs/vl_ma2sc.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * Configuation settings for the VL_MA2SC board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*--------------------------------------------------------------------------*/
-
-#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
-#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_MISC_INIT_R
-
-#include <asm/hardware.h>
-
-#define MACH_TYPE_VL_MA2SC 2412
-#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
-
-#define CONFIG_SYS_DCACHE_OFF
-
-#ifdef CONFIG_RAMLOAD
-#define CONFIG_SYS_TEXT_BASE 0x21000000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-
-#define CONFIG_IDENT_STRING " on MiS Activ 2"
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AT91_GPIO
-
-#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
-#define CONFIG_SYS_USE_NORFLASH
-#define CONFIG_SYS_USE_BOOT_NORFLASH
-#endif
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_WATCHDOG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_ATMEL_LCD
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_BLACK_ON_WHITE
-#define LCD_BPP LCD_COLOR8
-#define CONFIG_ATMEL_LCD_BGR555
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-/*
-#define CONFIG_CMD_SPI
-*/
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_MD5
-#define CONFIG_SHA1
-
-/*----------------------------------------------------------------------------
- * Hardware confuguration
- *---------------------------------------------------------------------------*/
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_AT91C_PQFP_UHPBUG
-
-/* I2C-Bus */
-
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
-
-#ifndef CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
-
-/* Software I2C driver configuration */
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
-#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
-#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
-#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
-#define I2C_SDA(bit) \
- do { \
- if (bit) \
- writel(AT91_PIN_SDA, &pio->piob.sodr); \
- else \
- writel(AT91_PIN_SDA, &pio->piob.codr); \
- } while (0);
-#define I2C_SCL(bit) \
- do { \
- if (bit) \
- writel(AT91_PIN_SCL, &pio->piob.sodr); \
- else \
- writel(AT91_PIN_SCL, &pio->piob.codr); \
- } while (0);
-#endif
-
-/* I2C-RTC */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/* EEPROM */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
- AT91_MATRIX_CSA_EBI_CS1A)
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_MR_URSTEN | \
- AT91_RSTC_MR_ERSTL(15))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
- AT91_WDT_MR_WDV(0xFFF) | \
- AT91_WDT_MR_WDDIS | \
- AT91_WDT_MR_WDD(0xFFF))
-
-/* clocks */
-
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
-
-#define MHZ180
-#if defined(MHZ199)
-/* 199,8994 MHZ */
-#define MASTER_PLL_MUL 911
-#define MASTER_PLL_DIV 56
-#define MASTER_PLL_OUT 2
-#elif defined(MHZ180)
-/* 180 MHZ */
-#define MASTER_PLL_MUL 1875
-#define MASTER_PLL_DIV 128
-#define MASTER_PLL_OUT 2
-#elif defined(MHZTEST)
-/* Test MHZ */
-#define CONFIG_DISPLAY_CPUINFO
-#define MASTER_PLL_MUL 8
-#define MASTER_PLL_DIV 1
-#define MASTER_PLL_OUT 2
-#else
-/* 176.9472 MHZ */
-#define MASTER_PLL_MUL 72
-#define MASTER_PLL_DIV 5
-#define MASTER_PLL_OUT 2
-#endif
-
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLAR_29 | \
- AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
- AT91_PMC_PLLXR_PLLCOUNT(63) | \
- AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
- AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
- AT91_PMC_MCKR_MDIV_2)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
- AT91_PMC_MCKR_MDIV_2)
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
-
-#define CONFIG_SYS_SDRC_MR_VAL1 0
-#define CONFIG_SYS_SDRC_TR_VAL1 700
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
-
-/* NOR flash */
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
- AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
- AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 5
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END 0x21e00000
-
-/* Address and size of Primary Environment Sector */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x20000
-#else
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
- 38400, 57600, 9600 }
-
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#ifndef CONFIG_RAMLOAD
-#define CONFIG_BOOTCOMMAND "run nfsboot"
-#endif
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_BOOT_RETRY_MIN 15
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp $(copy_addr) $(kernelname);" \
- "run bootargsdefaults;" \
- "set bootargs $(bootargs) boot=nfs " \
- ";echo $(bootargs)" \
- ";bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ubootaddr=10000000\0" \
- "splashimage=10080000\0" \
- "kerneladdr=100A0000\0" \
- "kernelsize=00800000\0" \
- "minifsaddr=108A0000\0" \
- "minifssize=00060000\0" \
- "rootfsaddr=10900000\0" \
- "copy_addr=20200000\0" \
- "rootfssize=01700000\0" \
- "kernelname=uImage_vl_ma2sc\0" \
- "bootargsdefaults=set bootargs " \
- "console=ttyS0,115200 " \
- "video=atmel_lcdfb " \
- "mem=62M " \
- "panic=10 " \
- "boardrevison=\\\"${revision}\\\" " \
- "uboot=\\\"${ver}\\\" " \
- "\0" \
- "update_all=run update_kernel;run update_root;" \
- "run update_splash; run update_uboot\0" \
- "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
- "dhcp $(copy_addr) $(kernelname);" \
- "erase $(kerneladdr) +$(kernelsize);" \
- "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
- "protect on $(kerneladdr) +$(kernelsize)" \
- "\0" \
- "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
- "dhcp $(copy_addr) vl_ma2sc.root;" \
- "erase $(rootfsaddr) +$(rootfssize);" \
- "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
- "\0" \
- "update_splash=protect off $(splashimage) +20000;" \
- "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
- "erase $(splashimage) +20000;" \
- "cp.b $(fileaddr) 10080000 $(filesize);" \
- "protect on $(splashimage) +20000\0" \
- "update_uboot=protect off 10000000 1005FFFF;" \
- "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
- "erase 10000000 1005FFFF;" \
- "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
- "protect on 10000000 1005FFFF;reset\0" \
- "emergency=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(kerneladdr)\0" \
- "netemergency=run bootargsdefaults;" \
- "dhcp $(copy_addr) $(kernelname);" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(copy_addr)\0" \
- "norboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=local quiet " \
- ";bootm $(kerneladdr)\0" \
- "nandboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=nand " \
- ";bootm $(kerneladdr)\0" \
- "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
- "clearenv=protect off 10060000 1007FFFF;" \
- "erase 10060000 1007FFFF;reset\0" \
- " "
-
-#endif
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 39/45] arm: Remove vpac270_nor_128 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (37 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 38/45] arm: Remove vl_ma2sc board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,39/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 40/45] arm: Remove xaeniax board Simon Glass
` (6 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 -
board/vpac270/Kconfig | 9 --
board/vpac270/MAINTAINERS | 8 -
board/vpac270/Makefile | 13 --
board/vpac270/onenand.c | 46 ------
board/vpac270/u-boot-spl.lds | 81 ----------
board/vpac270/vpac270.c | 126 ---------------
configs/vpac270_nor_128_defconfig | 6 -
configs/vpac270_nor_256_defconfig | 6 -
configs/vpac270_ond_256_defconfig | 8 -
include/configs/vpac270.h | 325 --------------------------------------
11 files changed, 634 deletions(-)
delete mode 100644 board/vpac270/Kconfig
delete mode 100644 board/vpac270/MAINTAINERS
delete mode 100644 board/vpac270/Makefile
delete mode 100644 board/vpac270/onenand.c
delete mode 100644 board/vpac270/u-boot-spl.lds
delete mode 100644 board/vpac270/vpac270.c
delete mode 100644 configs/vpac270_nor_128_defconfig
delete mode 100644 configs/vpac270_nor_256_defconfig
delete mode 100644 configs/vpac270_ond_256_defconfig
delete mode 100644 include/configs/vpac270.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1a440b7..da58c27 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -709,11 +709,6 @@ config TARGET_PALMTREO680
select CPU_PXA
select SUPPORT_SPL
-config TARGET_VPAC270
- bool "Support vpac270"
- select CPU_PXA
- select SUPPORT_SPL
-
config TARGET_XAENIAX
bool "Support xaeniax"
select CPU_PXA
@@ -880,7 +875,6 @@ source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/udoo/Kconfig"
-source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
diff --git a/board/vpac270/Kconfig b/board/vpac270/Kconfig
deleted file mode 100644
index 1701b35..0000000
--- a/board/vpac270/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_VPAC270
-
-config SYS_BOARD
- default "vpac270"
-
-config SYS_CONFIG_NAME
- default "vpac270"
-
-endif
diff --git a/board/vpac270/MAINTAINERS b/board/vpac270/MAINTAINERS
deleted file mode 100644
index 1c62765..0000000
--- a/board/vpac270/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-VPAC270 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/vpac270/
-F: include/configs/vpac270.h
-F: configs/vpac270_nor_128_defconfig
-F: configs/vpac270_nor_256_defconfig
-F: configs/vpac270_ond_256_defconfig
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
deleted file mode 100644
index ad7f7d8..0000000
--- a/board/vpac270/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Voipac PXA270 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifndef CONFIG_SPL_BUILD
-obj-y := vpac270.o
-else
-obj-y := onenand.o
-endif
diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c
deleted file mode 100644
index a749b31..0000000
--- a/board/vpac270/onenand.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Voipac PXA270 OneNAND SPL
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <onenand_uboot.h>
-#include <asm/arch/pxa.h>
-
-void board_init_f(unsigned long unused)
-{
- extern uint32_t _end;
- uint32_t tmp;
-
- asm volatile("mov %0, pc" : "=r"(tmp));
- tmp >>= 24;
-
- /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */
- if (tmp == 0) {
- tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE;
- onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE);
- asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE));
- }
-
- /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */
- arch_cpu_init();
- pxa2xx_dram_init();
- onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR,
- CONFIG_SPL_ONENAND_LOAD_SIZE,
- (void *)CONFIG_SYS_TEXT_BASE);
- asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE));
-
- for (;;)
- ;
-}
-
-void __attribute__((noreturn)) hang(void)
-{
- for (;;)
- ;
-}
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
deleted file mode 100644
index 954afb9..0000000
--- a/board/vpac270/u-boot-spl.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = CONFIG_SPL_TEXT_BASE;
- .text.0 :
- {
- *(.vectors)
- arch/arm/cpu/pxa/start.o (.text*)
- arch/arm/lib/built-in.o (.text*)
- board/vpac270/built-in.o (.text*)
- drivers/built-in.o (.text*)
- }
-
-
- /* Start of the rest of the SPL */
- . = CONFIG_SPL_TEXT_BASE + 0x800;
-
- .text.1 :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(0x800);
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
deleted file mode 100644
index 8d777df..0000000
--- a/board/vpac270/vpac270.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Voipac PXA270 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
-#include <asm/arch/pxa.h>
-#include <netdev.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* Arch number of vpac270 */
- gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int dram_init(void)
-{
-#ifndef CONFIG_ONENAND
- pxa2xx_dram_init();
-#endif
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_RAM_256M
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
diff --git a/configs/vpac270_nor_128_defconfig b/configs/vpac270_nor_128_defconfig
deleted file mode 100644
index 1d11653..0000000
--- a/configs/vpac270_nor_128_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vpac270_nor_256_defconfig b/configs/vpac270_nor_256_defconfig
deleted file mode 100644
index bcd1006..0000000
--- a/configs/vpac270_nor_256_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/configs/vpac270_ond_256_defconfig b/configs/vpac270_ond_256_defconfig
deleted file mode 100644
index d989819..0000000
--- a/configs/vpac270_ond_256_defconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
deleted file mode 100644
index 976ba5d..0000000
--- a/include/configs/vpac270.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * Voipac PXA270 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#ifdef CONFIG_ONENAND
-#define CONFIG_SPL_ONENAND_SUPPORT
-#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000
-#define CONFIG_SPL_ONENAND_LOAD_SIZE \
- (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
-#define CONFIG_SPL_TEXT_BASE 0x5c000000
-#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds"
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "if ide reset && fatload ide 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "bootm 0x60000;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "update_onenand=" \
- "onenand erase 0x0 0x80000 ; " \
- "onenand write 0xa0000000 0x0 0x80000"
-
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_LZMA /* LZMA compression support */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
-#undef CONFIG_LCD
-#define CONFIG_CMD_IDE
-
-#ifdef CONFIG_ONENAND
-#define CONFIG_CMD_ONENAND
-#else
-#undef CONFIG_CMD_ONENAND
-#endif
-
-/*
- * Networking Configuration
- * chip on the Voipac PXA270 board
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
-#define DM9000_IO (CONFIG_DM9000_BASE)
-#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
-#define CONFIG_NET_RETRY_COUNT 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#ifdef CONFIG_SYS_HUSH_PARSER
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
-
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-
-#ifdef CONFIG_RAM_256M
-#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#endif
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
-#else
-#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
-
-/*
- * NOR FLASH
- */
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-#if defined(CONFIG_CMD_FLASH) /* NOR */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#ifdef CONFIG_RAM_256M
-#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
-#endif
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-#else
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ONENAND_BASE 0x00000000
-
-#define CONFIG_ENV_IS_IN_ONENAND 1
-
-#else /* No flash */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-/*
- * IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
-#define CONFIG_SYS_ATA_REG_OFFSET 0x120
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
-
-#define CONFIG_SYS_ATA_STRIDE 2
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x01308800
-#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
-#define CONFIG_SYS_GPSR2_VAL 0x922ac000
-#define CONFIG_SYS_GPSR3_VAL 0x0161e800
-
-#define CONFIG_SYS_GPCR0_VAL 0x00010000
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
-#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
-#define CONFIG_SYS_GPDR2_VAL 0x922affff
-#define CONFIG_SYS_GPDR3_VAL 0x0161e904
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
-#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
-#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
-#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x00500240
-#define CONFIG_SYS_CCCR 0x02000290
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9
-#define CONFIG_SYS_MSC1_VAL 0x02ccf974
-#define CONFIG_SYS_MSC2_VAL 0x00000000
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
-#else
-#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
-#endif
-#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
-#define CONFIG_USB_STORAGE
-#endif
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 40/45] arm: Remove xaeniax board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (38 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 39/45] arm: Remove vpac270_nor_128 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,40/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board Simon Glass
` (5 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 5 -
board/xaeniax/Kconfig | 9 -
board/xaeniax/MAINTAINERS | 6 -
board/xaeniax/Makefile | 8 -
board/xaeniax/flash.c | 412 -----------------------------------
board/xaeniax/xaeniax.c | 69 ------
configs/xaeniax_defconfig | 3 -
drivers/net/smc91111.c | 51 +----
drivers/net/smc91111.h | 22 --
include/configs/xaeniax.h | 539 ----------------------------------------------
10 files changed, 1 insertion(+), 1123 deletions(-)
delete mode 100644 board/xaeniax/Kconfig
delete mode 100644 board/xaeniax/MAINTAINERS
delete mode 100644 board/xaeniax/Makefile
delete mode 100644 board/xaeniax/flash.c
delete mode 100644 board/xaeniax/xaeniax.c
delete mode 100644 configs/xaeniax_defconfig
delete mode 100644 include/configs/xaeniax.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da58c27..f22d5dc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -709,10 +709,6 @@ config TARGET_PALMTREO680
select CPU_PXA
select SUPPORT_SPL
-config TARGET_XAENIAX
- bool "Support xaeniax"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@@ -880,7 +876,6 @@ source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
-source "board/xaeniax/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/board/xaeniax/Kconfig b/board/xaeniax/Kconfig
deleted file mode 100644
index 519e21f..0000000
--- a/board/xaeniax/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_XAENIAX
-
-config SYS_BOARD
- default "xaeniax"
-
-config SYS_CONFIG_NAME
- default "xaeniax"
-
-endif
diff --git a/board/xaeniax/MAINTAINERS b/board/xaeniax/MAINTAINERS
deleted file mode 100644
index 44bb588..0000000
--- a/board/xaeniax/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XAENIAX BOARD
-#M: -
-S: Maintained
-F: board/xaeniax/
-F: include/configs/xaeniax.h
-F: configs/xaeniax_defconfig
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
deleted file mode 100644
index e5f116d..0000000
--- a/board/xaeniax/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := xaeniax.o flash.o
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
deleted file mode 100644
index 6ad6216..0000000
--- a/board/xaeniax/flash.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0] );
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type, start;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x00500050; /* clear status register cmd. */
- *addr = 0x00FF00FF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased@%08lx (%lx)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
deleted file mode 100644
index 995c262..0000000
--- a/board/xaeniax/xaeniax.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2004
- * Vincent Dubey, Xa SA, vincent.dubey at xa-ch.com
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of xaeniax */
- gd->bd->bi_arch_number = 585;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/configs/xaeniax_defconfig b/configs/xaeniax_defconfig
deleted file mode 100644
index 8634cc7..0000000
--- a/configs/xaeniax_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_XAENIAX=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index ade14cd..f31216f 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -499,15 +499,8 @@ again:
}
/* we have a packet address, so tell the card to use it */
-#ifndef CONFIG_XAENIAX
SMC_outb (dev, packet_no, PN_REG);
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl (dev, packet_no << 16, 0);
-#endif
+
/* do not write new ptr value if Write data fifo not empty */
while ( saved_ptr & PTR_NOTEMPTY )
printf ("Write data fifo not empty!\n");
@@ -542,39 +535,19 @@ again:
*/
#ifdef USE_32_BIT
SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
-#ifndef CONFIG_XAENIAX
if (length & 0x2)
SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
#else
- /* On XANEIAX, we can only use 32-bit writes, so we need to handle
- * unaligned tail part specially. The standard code doesn't work.
- */
- if ((length & 3) == 3) {
- u16 * ptr = (u16*) &buf[length-3];
- SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
- SMC91111_DATA_REG);
- } else if ((length & 2) == 2) {
- u16 * ptr = (u16*) &buf[length-2];
- SMC_outl(dev, *ptr, SMC91111_DATA_REG);
- } else if (length & 1) {
- SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
- } else {
- SMC_outl(dev, 0, SMC91111_DATA_REG);
- }
-#endif
-#else
SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
-#ifndef CONFIG_XAENIAX
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
SMC_outw (dev, 0, SMC91111_DATA_REG);
} else {
SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
-#endif
/* and let the chipset deal with it */
SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
@@ -588,9 +561,6 @@ again:
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
- SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
-#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
@@ -610,9 +580,6 @@ again:
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
- SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
-#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
@@ -625,15 +592,7 @@ again:
}
/* restore previously saved registers */
-#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl(dev, saved_pnr << 16, 0);
-#endif
SMC_outw( dev, saved_ptr, PTR_REG );
return length;
@@ -802,15 +761,7 @@ static int smc_rcv(struct eth_device *dev)
udelay(1); /* Wait until not busy */
/* restore saved registers */
-#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl( dev, saved_pnr << 16, 0);
-#endif
SMC_outw( dev, saved_ptr, PTR_REG );
if (!is_error) {
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index e19c491..5197f36 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -77,19 +77,6 @@ struct smc91111_priv{
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
-#elif defined(CONFIG_XAENIAX)
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
-#define SMC_inw(a,z) ({ \
- unsigned int __p = (unsigned int)((a)->iobase + (z)); \
- unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
- if (__p & 3) __v >>= 16; \
- else __v &= 0xffff; \
- __v; })
-#define SMC_inb(a,p) ({ \
- unsigned int ___v = SMC_inw((a),(p) & ~1); \
- if ((p) & 1) ___v >>= 8; \
- else ___v &= 0xff; \
- ___v; })
#else
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
@@ -104,15 +91,6 @@ struct smc91111_priv{
#ifdef CONFIG_XSENGINE
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
-#elif defined (CONFIG_XAENIAX)
-#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
-#define SMC_outw(a,d,p) ({ \
- dword __dwo = SMC_inl((a),(p) & ~3); \
- dword __dwn = (word)(d); \
- __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
- __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
- SMC_outl((a), __dwo, (p) & ~3); \
-})
#else
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
deleted file mode 100644
index 8d19bff..0000000
--- a/include/configs/xaeniax.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2004
- * Vincent Dubey, Xa SA, vincent.dubey at xa-ch.com
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.ne
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the xaeniax board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */
-#define CONFIG_XAENIAX 1 /* on a xaeniax board */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOARD_LATE_INIT
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
-#define CONFIG_CONS_INDEX 4
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_DTT
-
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.68.201
-#define CONFIG_SERVERIP 192.168.68.62
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "bootm 0x00100000"
-#define CONFIG_BOOTARGS "console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* FIXME */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
-#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-#undef CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-/*
- * GPIO settings
- */
-
-/*
- * GP05 == nUSBReset is 1
- * GP10 == CFReset is 1
- * GP13 == nCFDataEnable is 1
- * GP14 == nCFAddrEnable is 1
- * GP15 == nCS1 is 1
- * GP21 == ComBrdReset is 1
- * GP24 == SFRM is 1
- * GP25 == TXD is 1
- * GP31 == SYNC is 1
- * GP33 == nCS5 is 1
- * GP39 == FFTXD is 1
- * GP41 == RTS is 1
- * GP43 == BTTXD is 1
- * GP45 == BTRTS is 1
- * GP47 == TXD is 1
- * GP48 == nPOE is 1
- * GP49 == nPWE is 1
- * GP50 == nPIOR is 1
- * GP51 == nPIOW is 1
- * GP52 == nPCE[1] is 1
- * GP53 == nPCE[2] is 1
- * GP54 == nPSKTSEL is 1
- * GP55 == nPREG is 1
- * GP78 == nCS2 is 1
- * GP79 == nCS3 is 1
- * GP80 == nCS4 is 1
- * GP82 == NSSPSFRM is 1
- * GP83 == NSSPTXD is 1
- */
-#define CONFIG_SYS_GPSR0_VAL 0x8320E420
-#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82
-#define CONFIG_SYS_GPSR2_VAL 0x000DC000
-
-/*
- * GP03 == LANReset is 0
- * GP06 == USBWakeUp is 0
- * GP11 == USBControl is 0
- * GP12 == Buzzer is 0
- * GP16 == PWM0 is 0
- * GP17 == PWM1 is 0
- * GP23 == SCLK is 0
- * GP30 == SDATA_OUT is 0
- * GP81 == NSSPCLK is 0
- */
-#define CONFIG_SYS_GPCR0_VAL 0x40C31848
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00020000
-
-/*
- * GP00 == CPUWakeUpUSB is input
- * GP01 == GP reset is input
- * GP02 == LANInterrupt is input
- * GP03 == LANReset is output
- * GP04 == USBInterrupt is input
- * GP05 == nUSBReset is output
- * GP06 == USBWakeUp is output
- * GP07 == CFReady/nBusy is input
- * GP08 == nCFCardDetect1 is input
- * GP09 == nCFCardDetect2 is input
- * GP10 == nCFReset is output
- * GP11 == USBControl is output
- * GP12 == Buzzer is output
- * GP13 == CFDataEnable is output
- * GP14 == CFAddressEnable is output
- * GP15 == nCS1 is output
- * GP16 == PWM0 is output
- * GP17 == PWM1 is output
- * GP18 == RDY is input
- * GP19 == ReaderReady is input
- * GP20 == ReaderReset is input
- * GP21 == ComBrdReset is output
- * GP23 == SCLK is output
- * GP24 == SFRM is output
- * GP25 == TXD is output
- * GP26 == RXD is input
- * GP27 == EXTCLK is input
- * GP28 == BITCLK is output
- * GP29 == SDATA_IN0 is input
- * GP30 == SDATA_OUT is output
- * GP31 == SYNC is output
- * GP32 == SYSSCLK is output
- * GP33 == nCS5 is output
- * GP34 == FFRXD is input
- * GP35 == CTS is input
- * GP36 == DCD is input
- * GP37 == DSR is input
- * GP38 == RI is input
- * GP39 == FFTXD is output
- * GP40 == DTR is output
- * GP41 == RTS is output
- * GP42 == BTRXD is input
- * GP43 == BTTXD is output
- * GP44 == BTCTS is input
- * GP45 == BTRTS is output
- * GP46 == RXD is input
- * GP47 == TXD is output
- * GP48 == nPOE is output
- * GP49 == nPWE is output
- * GP50 == nPIOR is output
- * GP51 == nPIOW is output
- * GP52 == nPCE[1] is output
- * GP53 == nPCE[2] is output
- * GP54 == nPSKTSEL is output
- * GP55 == nPREG is output
- * GP56 == nPWAIT is input
- * GP57 == nPIOS16 is input
- * GP58 == LDD[0] is output
- * GP59 == LDD[1] is output
- * GP60 == LDD[2] is output
- * GP61 == LDD[3] is output
- * GP62 == LDD[4] is output
- * GP63 == LDD[5] is output
- * GP64 == LDD[6] is output
- * GP65 == LDD[7] is output
- * GP66 == LDD[8] is output
- * GP67 == LDD[9] is output
- * GP68 == LDD[10] is output
- * GP69 == LDD[11] is output
- * GP70 == LDD[12] is output
- * GP71 == LDD[13] is output
- * GP72 == LDD[14] is output
- * GP73 == LDD[15] is output
- * GP74 == LCD_FCLK is output
- * GP75 == LCD_LCLK is output
- * GP76 == LCD_PCLK is output
- * GP77 == LCD_ACBIAS is output
- * GP78 == nCS2 is output
- * GP79 == nCS3 is output
- * GP80 == nCS4 is output
- * GP81 == NSSPCLK is output
- * GP82 == NSSPSFRM is output
- * GP83 == NSSPTXD is output
- * GP84 == NSSPRXD is input
- */
-#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68
-#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83
-#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF
-
-/*
- * GP01 == GP reset is AF01
- * GP15 == nCS1 is AF10
- * GP16 == PWM0 is AF10
- * GP17 == PWM1 is AF10
- * GP18 == RDY is AF01
- * GP23 == SCLK is AF10
- * GP24 == SFRM is AF10
- * GP25 == TXD is AF10
- * GP26 == RXD is AF01
- * GP27 == EXTCLK is AF01
- * GP28 == BITCLK is AF01
- * GP29 == SDATA_IN0 is AF10
- * GP30 == SDATA_OUT is AF01
- * GP31 == SYNC is AF01
- * GP32 == SYSCLK is AF01
- * GP33 == nCS5 is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS is AF01
- * GP36 == DCD is AF01
- * GP37 == DSR is AF01
- * GP38 == RI is AF01
- * GP39 == FFTXD is AF10
- * GP40 == DTR is AF10
- * GP41 == RTS is AF10
- * GP42 == BTRXD is AF01
- * GP43 == BTTXD is AF10
- * GP44 == BTCTS is AF01
- * GP45 == BTRTS is AF10
- * GP46 == RXD is AF10
- * GP47 == TXD is AF01
- * GP48 == nPOE is AF10
- * GP49 == nPWE is AF10
- * GP50 == nPIOR is AF10
- * GP51 == nPIOW is AF10
- * GP52 == nPCE[1] is AF10
- * GP53 == nPCE[2] is AF10
- * GP54 == nPSKTSEL is AF10
- * GP55 == nPREG is AF10
- * GP56 == nPWAIT is AF01
- * GP57 == nPIOS16 is AF01
- * GP58 == LDD[0] is AF10
- * GP59 == LDD[1] is AF10
- * GP60 == LDD[2] is AF10
- * GP61 == LDD[3] is AF10
- * GP62 == LDD[4] is AF10
- * GP63 == LDD[5] is AF10
- * GP64 == LDD[6] is AF10
- * GP65 == LDD[7] is AF10
- * GP66 == LDD[8] is AF10
- * GP67 == LDD[9] is AF10
- * GP68 == LDD[10] is AF10
- * GP69 == LDD[11] is AF10
- * GP70 == LDD[12] is AF10
- * GP71 == LDD[13] is AF10
- * GP72 == LDD[14] is AF10
- * GP73 == LDD[15] is AF10
- * GP74 == LCD_FCLK is AF10
- * GP75 == LCD_LCLK is AF10
- * GP76 == LCD_PCLK is AF10
- * GP77 == LCD_ACBIAS is AF10
- * GP78 == nCS2 is AF10
- * GP79 == nCS3 is AF10
- * GP80 == nCS4 is AF10
- * GP81 == NSSPCLK is AF01
- * GP82 == NSSPSFRM is AF01
- * GP83 == NSSPTXD is AF01
- * GP84 == NSSPRXD is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
-#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A
-#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
-#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000256
-
-/*
- * clock settings
- */
-/* RDH = 1
- * PH = 0
- * VFS = 0
- * BFS = 0
- * SSS = 0
- */
-#define CONFIG_SYS_PSSR_VAL 0x00000030
-
-#define CONFIG_SYS_CKEN 0x00000080 /* */
-#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1 :
- * [31] 0 -
- * [30:28] 000 -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19] 0 -
- * [18:16] 000 -
- * configuration for nCS0:
- * [15] 0 - Slower Device
- * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
- * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
- * [03] 0 - 32 Bit bus width
- * [02:00] 010 - burst OF 4 ROM or FLASH
-*/
-#define CONFIG_SYS_MSC0_VAL 0x000023D2
-
-/* This is the configuration for nCS2/3 -> USB controller, LAN
- * configuration for nCS3: LAN
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
- * [19] 0 - 32 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS2: USB
- * [15] 1 - Faster Device
- * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL 0x1224A26C
-
-/* This is the configuration for nCS4/5 -> LAN
- * configuration for nCS5:
- * [31] 0 -
- * [30:28] 000 -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19] 0 -
- * [18:16] 000 -
- * configuration for nCS4: LAN
- * [15] 1 - Faster Device
- * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03] 0 - 32 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL 0x00001224
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29] 000 - reserved
- * [28] 0 - no SA1111 compatiblity mode
- * [27] 0 - latch return data with return clock
- * [26] 0 - alternate addressing for pair 2/3
- * [25:24] 00 - timings
- * [23] 0 - internal banks in lower partition 2/3 (not used)
- * [22:21] 00 - row address bits for partition 2/3 (not used)
- * [20:19] 00 - column address bits for partition 2/3 (not used)
- * [18] 0 - SDRAM partition 2/3 width is 32 bit
- * [17] 0 - SDRAM partition 3 disabled
- * [16] 0 - SDRAM partition 2 disabled
- * [15:13] 000 - reserved
- * [12] 0 - no SA1111 compatiblity mode
- * [11] 1 - latch return data with return clock
- * [10] 0 - no alternate addressing for pair 0/1
- * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7] 1 - 4 internal banks in lower partition pair
- * [06:05] 10 - 13 row address bits for partition 0/1
- * [04:03] 01 - 9 column address bits for partition 0/1
- * [02] 0 - SDRAM partition 0/1 width is 32 bit
- * [01] 0 - disable SDRAM partition 1
- * [00] 1 - enable SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0 - reserved
- * [25] 0 - K2FREE: not free running
- * [24] 0 - K1FREE: not free running
- * [23] 0 - K0FREE: not free running
- * [22] 0 - SLFRSH: self refresh disabled
- * [21] 0 - reserved
- * [20] 1 - APD: auto power down
- * [19] 0 - K2DB2: SDCLK2 is MemClk
- * [18] 0 - K2RUN: disable SDCLK2
- * [17] 0 - K1DB2: SDCLK1 is MemClk
- * [16] 1 - K1RUN: enable SDCLK1
- * [15] 1 - E1PIN: SDRAM clock enable
- * [14] 0 - K0DB2: SDCLK0 is MemClk
- * [13] 0 - K0RUN: disable SDCLK0
- * [12] 0 - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31] 0 - reserved
- * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used)
- * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
- * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
- * [15] 0 - reserved
- * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency.
- * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00004715
-#define CONFIG_SYS_MCIO1_VAL 0x00004715
-
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (39 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 40/45] arm: Remove xaeniax board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 14:38 ` Tom Rini
2015-08-31 14:50 ` Felipe Balbi
2015-08-31 1:19 ` [U-Boot] [PATCH 42/45] arm: Remove palmtreo680 board Simon Glass
` (4 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/armv7/omap3/Kconfig | 13 --
board/quipos/cairo/cairo.c | 12 -
board/ti/evm/Kconfig | 38 ----
board/ti/evm/MAINTAINERS | 10 -
board/ti/evm/Makefile | 8 -
board/ti/evm/evm.c | 274 -----------------------
board/ti/evm/evm.h | 394 ---------------------------------
configs/omap3_evm_defconfig | 10 -
configs/omap3_evm_quick_mmc_defconfig | 26 ---
configs/omap3_evm_quick_nand_defconfig | 26 ---
doc/README.omap3 | 5 -
drivers/usb/musb/omap3.c | 4 -
drivers/usb/musb/omap3.h | 4 -
include/configs/omap3_evm.h | 154 -------------
include/configs/omap3_evm_common.h | 289 ------------------------
include/configs/omap3_evm_quick_mmc.h | 92 --------
include/configs/omap3_evm_quick_nand.h | 92 --------
17 files changed, 1451 deletions(-)
delete mode 100644 board/ti/evm/Kconfig
delete mode 100644 board/ti/evm/MAINTAINERS
delete mode 100644 board/ti/evm/Makefile
delete mode 100644 board/ti/evm/evm.c
delete mode 100644 board/ti/evm/evm.h
delete mode 100644 configs/omap3_evm_defconfig
delete mode 100644 configs/omap3_evm_quick_mmc_defconfig
delete mode 100644 configs/omap3_evm_quick_nand_defconfig
delete mode 100644 include/configs/omap3_evm.h
delete mode 100644 include/configs/omap3_evm_common.h
delete mode 100644 include/configs/omap3_evm_quick_mmc.h
delete mode 100644 include/configs/omap3_evm_quick_nand.h
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index c758038..408bb76 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -33,18 +33,6 @@ config TARGET_DEVKIT8000
select DM_SERIAL
select DM_GPIO
-config TARGET_OMAP3_EVM
- bool "TI OMAP3 EVM"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_EVM_QUICK_MMC
- bool "TI OMAP3 EVM Quick MMC"
- select SUPPORT_SPL
-
-config TARGET_OMAP3_EVM_QUICK_NAND
- bool "TI OMAP3 EVM Quick NAND"
- select SUPPORT_SPL
-
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
select SUPPORT_SPL
@@ -120,7 +108,6 @@ source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
-source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index b97a09a..083e19a 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -26,18 +26,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
-u8 omap3_evm_need_extvbus(void)
-{
- u8 retval = 0;
-
- /* TODO: verify if cairo handheld platform needs extvbus programming */
-
- return retval;
-}
-
-/*
* Routine: board_init
* Description: Early hardware init.
*/
diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig
deleted file mode 100644
index f02aa31..0000000
--- a/board/ti/evm/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-if TARGET_OMAP3_EVM
-
-config SYS_BOARD
- default "evm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_evm"
-
-endif
-
-if TARGET_OMAP3_EVM_QUICK_MMC
-
-config SYS_BOARD
- default "evm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_evm_quick_mmc"
-
-endif
-
-if TARGET_OMAP3_EVM_QUICK_NAND
-
-config SYS_BOARD
- default "evm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_evm_quick_nand"
-
-endif
diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS
deleted file mode 100644
index 90c3f6b..0000000
--- a/board/ti/evm/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-EVM BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/evm/
-F: include/configs/omap3_evm.h
-F: include/configs/omap3_evm_quick_mmc.h
-F: include/configs/omap3_evm_quick_nand.h
-F: configs/omap3_evm_defconfig
-F: configs/omap3_evm_quick_mmc_defconfig
-F: configs/omap3_evm_quick_nand_defconfig
diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile
deleted file mode 100644
index b88ab8f..0000000
--- a/board/ti/evm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := evm.o
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
deleted file mode 100644
index 3f93d9c..0000000
--- a/board/ti/evm/evm.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2004-2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <twl4030.h>
-#include <asm/mach-types.h>
-#include <linux/mtd/nand.h>
-#include "evm.h"
-
-#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
-#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 omap3_evm_version;
-
-u32 get_omap3_evm_rev(void)
-{
- return omap3_evm_version;
-}
-
-static void omap3_evm_get_revision(void)
-{
-#if defined(CONFIG_CMD_NET)
- /*
- * Board revision can be ascertained only by identifying
- * the Ethernet chipset.
- */
- unsigned int smsc_id;
-
- /* Ethernet PHY ID is stored at ID_REV register */
- smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
- printf("Read back SMSC id 0x%x\n", smsc_id);
-
- switch (smsc_id) {
- /* SMSC9115 chipset */
- case 0x01150000:
- omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
- break;
- /* SMSC 9220 chipset */
- case 0x92200000:
- default:
- omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
- }
-#else
-#if defined(CONFIG_STATIC_BOARD_REV)
- /*
- * Look for static defintion of the board revision
- */
- omap3_evm_version = CONFIG_STATIC_BOARD_REV;
-#else
- /*
- * Fallback to the default above.
- */
- omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
-#endif
-#endif /* CONFIG_CMD_NET */
-}
-
-#ifdef CONFIG_USB_OMAP3
-/*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
-u8 omap3_evm_need_extvbus(void)
-{
- u8 retval = 0;
-
- if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
- retval = 1;
-
- return retval;
-}
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int pop_mfr, pop_id;
-
- /*
- * We need to identify what PoP memory is on the board so that
- * we know what timings to use. To map the ID values please see
- * nand_ids.c
- */
- identify_nand_chip(&pop_mfr, &pop_id);
-
- if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
- /* 256MB DDR */
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- } else {
- /* 128MB DDR */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- }
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- timings->mr = MICRON_V_MR_165;
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- */
-int misc_init_r(void)
-{
-
-#ifdef CONFIG_SYS_I2C_OMAP34XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif
- omap3_evm_get_revision();
-
-#if defined(CONFIG_CMD_NET)
- reset_net_chip();
-#endif
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_EVM();
-}
-
-#ifdef CONFIG_CMD_NET
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
-/**
- * Reset the ethernet chip.
- */
-static void reset_net_chip(void)
-{
- int ret;
- int rst_gpio;
-
- if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
- rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
- } else {
- rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
- }
-
- ret = gpio_request(rst_gpio, "");
- if (ret < 0) {
- printf("Unable to get GPIO %d\n", rst_gpio);
- return ;
- }
-
- /* Configure as output */
- gpio_direction_output(rst_gpio, 0);
-
- /* Send a pulse on the GPIO pin */
- gpio_set_value(rst_gpio, 1);
- udelay(1);
- gpio_set_value(rst_gpio, 0);
- udelay(1);
- gpio_set_value(rst_gpio, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
-#define STR_ENV_ETHADDR "ethaddr"
-
- struct eth_device *dev;
- uchar eth_addr[6];
-
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-
- if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
- dev = eth_get_dev_by_index(0);
- if (dev) {
- eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
- } else {
- printf("omap3evm: Couldn't get eth device\n");
- rc = -1;
- }
- }
-#endif
- return rc;
-}
-#endif /* CONFIG_CMD_NET */
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
deleted file mode 100644
index 91e9b88..0000000
--- a/board/ti/evm/evm.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2008
- * Nishanth Menon <menon.nishanth@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _EVM_H_
-#define _EVM_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 EVM board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#else
- "NAND",
-#endif
-};
-
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- * GEN_1 = 0x01150000
- * GEN_2 = 0x92200000
- */
-enum {
- OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
- OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
-};
-
-u32 get_omap3_evm_rev(void);
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-static void reset_net_chip(void);
-#endif
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_EVM() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- /* - ETH_nRESET*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- /* - CAM_RESET*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
- /* - LCD_INI*/\
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
- /* - LCD_ENVDD */\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
- /* - LCD_QVGA/nVGA */\
- MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
- /* - LCD_RESB */\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
- /* RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
- /* TS_PEN_IRQ */\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
- /* - LAN_INTR*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- /* - PEN_IRQ */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- /* - VIO_1V8*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
- MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\
- MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\
- MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\
- MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\
- MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\
- MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\
- MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\
- MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\
- MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\
- MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
-
-#endif
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
deleted file mode 100644
index de8fbd9..0000000
--- a/configs/omap3_evm_defconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_EVM=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
deleted file mode 100644
index 7d15b16..0000000
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
-CONFIG_SPL=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
deleted file mode 100644
index cd30134..0000000
--- a/configs/omap3_evm_quick_nand_defconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
-CONFIG_SPL=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/doc/README.omap3 b/doc/README.omap3
index e09ac03..d692374 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -43,11 +43,6 @@ make
make omap3_overo_config
make
-* TI EVM:
-
-make omap3_evm_config
-make
-
* Pandora:
make omap3_pandora_config
diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c
index 97da529..a61affc 100644
--- a/drivers/usb/musb/omap3.c
+++ b/drivers/usb/musb/omap3.c
@@ -118,10 +118,6 @@ int musb_platform_init(void)
stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
writel(stdby, &otg->forcestdby);
-#ifdef CONFIG_OMAP3_EVM
- musb_cfg.extvbus = omap3_evm_need_extvbus();
-#endif
-
#ifdef CONFIG_OMAP4430
u32 *usbotghs_control =
(u32 *)((*ctrl)->control_usbotghs_ctrl);
diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h
index ae645c7..b8a29e1 100644
--- a/drivers/usb/musb/omap3.h
+++ b/drivers/usb/musb/omap3.h
@@ -32,8 +32,4 @@
int musb_platform_init(void);
-#ifdef CONFIG_OMAP3_EVM
-extern u8 omap3_evm_need_extvbus(void);
-#endif
-
#endif /* _MUSB_OMAP3_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
deleted file mode 100644
index 1dd71a8..0000000
--- a/include/configs/omap3_evm.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Configuration settings for the TI OMAP3 EVM board.
- *
- * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OMAP3EVM_CONFIG_H
-#define __OMAP3EVM_CONFIG_H
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot commands
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_CMD_ASKENV
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot features
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Add auto-completion support */
-#define CONFIG_AUTO_COMPLETE
-
-/* ----------------------------------------------------------------------------
- * Supported hardware
- * ----------------------------------------------------------------------------
- */
-
-/* MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-
-/* SPL */
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-/* Partition tables */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB
- *
- * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
- */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_HCD
-/* #define CONFIG_USB_MUSB_UDC */
-
-/* NAND SPL */
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-
-/* -----------------------------------------------------------------------------
- * Include common board configuration
- * -----------------------------------------------------------------------------
- */
-#include "omap3_evm_common.h"
-
-/* -----------------------------------------------------------------------------
- * Default environment
- * -----------------------------------------------------------------------------
- */
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "usbtty=cdc_acm\0" \
- "mmcdev=0\0" \
- "console=ttyO0,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "onenand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
-
-#endif /* __OMAP3EVM_CONFIG_H */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
deleted file mode 100644
index 7e7f6f2..0000000
--- a/include/configs/omap3_evm_common.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Common configuration settings for the TI OMAP3 EVM board.
- *
- * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OMAP3_EVM_COMMON_H
-#define __OMAP3_EVM_COMMON_H
-
-/*
- * High level configuration options
- */
-#define CONFIG_OMAP /* This is TI OMAP core */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
-#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
-
-/*
- * Clock related definitions
- */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/* Size of environment - 128KB */
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/* Size of malloc pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Physical Memory Map
- * Note 1: CS1 may or may not be populated
- * Note 2: SDRAM size is expected to be at least 32MB
- */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/* Limits for memtest */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/* -----------------------------------------------------------------------------
- * Hardware drivers
- * -----------------------------------------------------------------------------
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * PISMO support
- */
-/* Monitor at start of flash - Reserve 2 sectors */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
-/* Start location & size of environment */
-#define ONENAND_ENV_OFFSET 0x260000
-#define SMNAND_ENV_OFFSET 0x260000
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-
-/*
- * NAND
- */
-/* Physical address to access NAND */
-#define CONFIG_SYS_NAND_ADDR NAND_BASE
-
-/* Physical address to access NAND at CS0 */
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-
-/* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-/* Timeout values (in ticks) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-
-#define CONFIG_SYS_JFFS2_MEM_NAND
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* Start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-/* Size of jffs2 partition */
-#define CONFIG_JFFS2_PART_SIZE 0xf980000
-
-/*
- * USB
- */
-#ifdef CONFIG_USB_OMAP3
-
-#ifdef CONFIG_USB_MUSB_HCD
-#define CONFIG_CMD_USB
-
-#define CONFIG_USB_STORAGE
-#define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HCD */
-
-#ifdef CONFIG_USB_MUSB_UDC
-/* USB device configuration */
-#define CONFIG_USB_DEVICE
-#define CONFIG_USB_TTY
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "EVM"
-#endif /* CONFIG_USB_MUSB_UDC */
-
-#endif /* CONFIG_USB_OMAP3 */
-
-/* ----------------------------------------------------------------------------
- * U-boot features
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of Console IO buffer */
-#define CONFIG_SYS_CBSIZE 512
-
-/* Size of print buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Size of bootarg buffer */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_BOOTFILE "uImage"
-
-/*
- * NAND / OneNAND
- */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#endif
-
-#if !defined(CONFIG_ENV_IS_NOWHERE)
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_ENV_IS_IN_ONENAND
-#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
-#endif
-#endif /* CONFIG_ENV_IS_NOWHERE */
-
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-#if defined(CONFIG_CMD_NET)
-
-/* Ethernet (SMSC9115 from SMSC9118 family) */
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
-
-/* BOOTP fields */
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-
-#endif /* CONFIG_CMD_NET */
-
-/* Support for relocation */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* -----------------------------------------------------------------------------
- * Board specific
- * -----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_NO_FLASH
-
-/* Uncomment to define the board revision statically */
-/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
-
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x40200800
-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
-#endif /* __OMAP3_EVM_COMMON_H */
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
deleted file mode 100644
index 27cd9be..0000000
--- a/include/configs/omap3_evm_quick_mmc.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Configuration settings for quick boot from MMC on OMAP3 EVM.
- *
- * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Author :
- * Sanjeev Premi <premi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OMAP3_EVM_QUICK_MMC_H
-#define __OMAP3_EVM_QUICK_MMC_H
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot commands
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-/*
- * Board revision is detected by probing the Ethernet chip.
- *
- * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
- * this option can be removed. Generated binary is leaner by ~16Kbytes.
- */
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot features
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_ENV_IS_NOWHERE
-
-/* ----------------------------------------------------------------------------
- * Supported hardware
- * ----------------------------------------------------------------------------
- */
-
-/* MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
-
-/* -----------------------------------------------------------------------------
- * Include common board configuration
- * -----------------------------------------------------------------------------
- */
-#include "omap3_evm_common.h"
-
-/* -----------------------------------------------------------------------------
- * Default environment
- * -----------------------------------------------------------------------------
- */
-#define CONFIG_BOOTDELAY 0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=no\0" \
- "silent=1"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan 0; " \
- "fatload mmc 0 0x82000000 uImage; " \
- "bootm 0x82000000;"
-
-/*
- * Update the bootargs as necessary e.g. size of memory, partition and fstype
- */
-#define CONFIG_BOOTARGS \
- "quiet " \
- "console=ttyO0,115200n8 " \
- "mem=128M " \
- "noinitrd " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait"
-
-/*
- * SPL
- */
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
deleted file mode 100644
index 124e8c6..0000000
--- a/include/configs/omap3_evm_quick_nand.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Configuration settings for quick boot from NAND on OMAP3 EVM.
- *
- * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Author :
- * Sanjeev Premi <premi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OMAP3_EVM_QUICK_NAND_H
-#define __OMAP3_EVM_QUICK_NAND_H
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot commands
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_CMD_NAND
-
-/*
- * Board revision is detected by probing the Ethernet chip.
- *
- * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
- * this option can be removed. Generated binary is leaner by ~16Kbytes.
- */
-
-/* ----------------------------------------------------------------------------
- * Supported U-boot features
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_ENV_IS_NOWHERE
-
-/* -----------------------------------------------------------------------------
- * Include common board configuration
- * -----------------------------------------------------------------------------
- */
-#include "omap3_evm_common.h"
-
-/* -----------------------------------------------------------------------------
- * Default environment
- * -----------------------------------------------------------------------------
- */
-#define CONFIG_BOOTDELAY 0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=no\0" \
- "silent=1"
-
-#define CONFIG_BOOTCOMMAND \
- "nandecc hw; " \
- "nand read.i 0x80000000 280000 300000; " \
- "bootm 0x80000000;"
-
-/*
- * Update the bootargs as necessary e.g. size of memory, partition and fstype
- */
-#define CONFIG_BOOTARGS \
- "quiet " \
- "console=ttyO0,115200n8 " \
- "mem=128M " \
- "noinitrd " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2 "
-
-/*
- * SPL
- */
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-
-#endif /* __OMAP3_EVM_QUICK_NAND_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 42/45] arm: Remove palmtreo680 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (40 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,42/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board Simon Glass
` (3 subsequent siblings)
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 -
board/palmtreo680/Kconfig | 9 -
board/palmtreo680/MAINTAINERS | 6 -
board/palmtreo680/Makefile | 9 -
board/palmtreo680/README | 563 ----------------------------------------
board/palmtreo680/palmtreo680.c | 148 -----------
configs/palmtreo680_defconfig | 12 -
include/configs/palmtreo680.h | 270 -------------------
8 files changed, 1023 deletions(-)
delete mode 100644 board/palmtreo680/Kconfig
delete mode 100644 board/palmtreo680/MAINTAINERS
delete mode 100644 board/palmtreo680/Makefile
delete mode 100644 board/palmtreo680/README
delete mode 100644 board/palmtreo680/palmtreo680.c
delete mode 100644 configs/palmtreo680_defconfig
delete mode 100644 include/configs/palmtreo680.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f22d5dc..8ef21a3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -704,11 +704,6 @@ config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMTREO680
- bool "Support palmtreo680"
- select CPU_PXA
- select SUPPORT_SPL
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@@ -841,7 +836,6 @@ source "board/kosagi/novena/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/samsung/smdk2410/Kconfig"
diff --git a/board/palmtreo680/Kconfig b/board/palmtreo680/Kconfig
deleted file mode 100644
index b5fdb9a..0000000
--- a/board/palmtreo680/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PALMTREO680
-
-config SYS_BOARD
- default "palmtreo680"
-
-config SYS_CONFIG_NAME
- default "palmtreo680"
-
-endif
diff --git a/board/palmtreo680/MAINTAINERS b/board/palmtreo680/MAINTAINERS
deleted file mode 100644
index b0ff9d0..0000000
--- a/board/palmtreo680/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PALMTREO680 BOARD
-#M: Mike Dunn <mikedunn@newsguy.com>
-S: Orphan (since 2014-06)
-F: board/palmtreo680/
-F: include/configs/palmtreo680.h
-F: configs/palmtreo680_defconfig
diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile
deleted file mode 100644
index 4f79e4b..0000000
--- a/board/palmtreo680/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Palm Treo680 Support
-#
-# Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
-#
-# This file is released under the terms of GPL v2 and any later version.
-# See the file COPYING in the root directory of the source tree for details.
-
-obj-y := palmtreo680.o
diff --git a/board/palmtreo680/README b/board/palmtreo680/README
deleted file mode 100644
index c8799c6..0000000
--- a/board/palmtreo680/README
+++ /dev/null
@@ -1,563 +0,0 @@
-
-README for the Palm Treo 680.
-
-Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
-
-You may reproduce the contents of this file entirely or in part, but please
-credit me by name if you do. Thanks.
-
-
-Intro
-=====
-
-Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot
-(then Linux, Android, ...) runs at power-up. This document describes how, and
-gives some implementation details on this port of u-boot and describes how the
-Treo 680 boots from reset.
-
-But first, I probably don't need to tell you that after doing this, your phone
-will no longer run PalmOS. You *may* be able to later restore your phone to its
-original state by creating a backup image of the flash before writing u-boot
-(details below), but this is not heavily tested and should not be relied upon.
-There is also the possibility that something may go wrong during the process of
-programming u-boot, leaving you with a bricked phone. If you follow these
-instructions carefully this chance will be minimized, but I do not recommend
-that you program u-boot onto a phone that you can not afford to lose, and
-certainly not one that contains important data that is not backed up elsewhere.
-I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE. DO THIS AT YOUR OWN RISK.
-Having said that, feel free to send me a note cursing me out if something does
-go wrong, but please tell me what happened exactly. For that matter, I'd love
-to hear from you if you succeed.
-
-
-Details on the SPL
-==================
-
-The docg4 features a 2k region at the start of its address space that interfaces
-to the system bus like a NOR flash. This allows the docg4 to function as a boot
-ROM. The Treo 680 uses this feature. The contents of this 2k region are
-write-protected and can not be reprogrammed. Fortunately, the code it contains
-does what we need to do, at least partially. After some essential hardware
-initialization (like the SDRAM controller), it runs an IPL (initial program
-loader) that copies 128K (no more, no less) from flash to a fixed address in
-SDRAM (0xa1700000) and jumps to it. 128K is too small for u-boot, so we use it
-to load a u-boot secondary program loader (SPL). But since our SPL only
-occupies a little over 1k, we can economize on flash usage by having the IPL
-load a portion of u-boot proper as well. We let the IPL load the first 128k of
-a concatenated spl + u-boot image, and because the SPL is placed before u-boot
-proper, the IPL jumps to the SPL, which copies the portion of u-boot that the
-IPL has already loaded to its correct SDRAM address, and then loads the
-remainder of u-boot and jumps to it.
-
-
-The docg4's "reliable mode"
-===========================
-
-This is a special mode of operation of the docg4's integrated controller whereby
-consecutive pairs of 2k regions are used in parallel (in some fashion) to store
-2k of data. In other words, the normal capacity is halved, but the data
-integrity is improved. In this mode, the data is read or written from pages in
-even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...). The
-odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are
-transparently used in parallel. In reliable mode, the odd-numbered 2k regions
-are not meant to be read or written directly.
-
-Reliable mode is used by the IPL because there is not enough space in its 2k
-footprint to implement the BCH ecc algorithm. Data that is read while reliable
-mode is enabled must have been written in reliable mode, or the read fails.
-However, data written in reliable mode can also be read in normal mode (just not
-as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k
-regions appear to contain junk, and will generate ecc errors. When the IPL and
-SPL read from flash, the odd-numbered 2k regions are explicitly skipped. The
-same is true for the flash_u-boot utility when it writes the u-boot image in
-reliable mode.
-
-The docg4 Linux driver supports writing in reliable mode (it is enabled by the
-module parameter), but not reading. However, the u-boot docg4_spl driver does
-read in reliable mode, in the same fashion as the IPL.
-
-
-Details on the IPL and its data format
-======================================
-
-Starting from block 5 and counting upward, the IPL will search for and load the
-first two blocks it finds that contain a magic number in the oob of the first
-page of the block. The contents are loaded to SDRAM starting at address
-0xa1700000. After two blocks have been loaded, it jumps to 0xa1700000. The
-number of blocks loaded and the load address in SDRAM are hard-coded; only the
-flash offset of the blocks can vary at run-time (based on the presence of the
-magic number).
-
-In addition to using the docg4's reliable mode, the IPL expects each 512 byte
-page to be written redundantly in the subsequent page. The hardware is capable
-of detecting bit errors (but not correcting them), and if a bit error is
-detected when a page is read, the page contents are discarded and the subsequent
-page is read.
-
-Reliable mode reduces the capacity of a block by half, and the redundant pages
-reduce it by half again. As a result, the normal 256k capacity of a block is
-reduced to 64k for the purposes of the IPL/SPL.
-
-For the sake of simplicity and uniformity, the u-boot SPL mimics the operation
-of the IPL, and expects the image to be stored in the same format.
-
-
-Instructions on Programming u-boot to flash
-===========================================
-
-To program u-boot to your flash, you will need to boot the Linux kernel on your
-phone using a PalmOS bootloader such as cocoboot. The details of building and
-running Linux on your Treo (cross-compiling, creating a root filesystem,
-configuring the kernel, etc) are beyond the scope of this document. The
-remainder of this document describes in detail how to program u-boot to the
-flash using Linux running on the Treo.
-
-
-Hardware Prerequisites
-======================
-
-A Palm Treo 680:
- (dugh)
-
-A Palm usb cable:
- You'll need this to establish a usbtty console connection to u-boot from a
- desktop PC. Currently there is no support in u-boot for the pxa27x keypad
- (coming soon), so a serial link must be used for the console.
- These cables are still widely available if you don't already have one.
-
-A Linux desktop PC.
- You may be able to use Windows for the u-boot console if you have a usb driver
- that is compatible with the Linux usbserial driver, but for programming u-boot
- to flash, you'll really want to use a Linux PC.
-
-
-Treo-side Software Prerequisites
-================================
-
-Linux bootloader for PalmOS:
-
- Cocoboot is the only one I'm aware of. If you don't already have this, you
- can download it from
- https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz
- which is a compressed tar archive of the contents of an sd card containing
- cocoboot. Use mkdosfs to create a fat16 filesystem on the first primary
- partition of the card, mount the partition, and extract the tar file to it.
- You will probably need to edit the cocoboot.conf file to customize the
- parameters passed to the kernel.
-
-
-Linux kernel:
-
- The kernel on the Treo 680 is still a little rough around the edges, and the
- official kernel frequently breaks on the Treo :( A development kernel
- specifically for the Treo 680 can be found on github:
- http://github.com/mike-dunn/linux-treo680
- The master branch of this tree has been tested on the Treo, and I recommend
- using this kernel for programming u-boot. As of this writing, there may be a
- bug in the docg4 nand flash driver that sometimes causes block erasures to
- fail. This has been fixed in the above tree.
-
- If you choose to use the official kernel, it must contain the docg4 driver that
- includes the reliable_mode module parameter. This was a later enhancement to
- the driver, and was merged to the kernel as of v3.8. Do not try to use an
- earlier kernel that contains the docg4 driver without support for writing in
- reliable mode. If you try to program u-boot to flash with the docg4 driver
- loaded without the reliable_mode parameter enabled, you *will* brick your
- phone!
-
- For the purpose of programming u-boot to flash, the following options must be
- enabled in the Treo kernel's .config:
-
- CONFIG_MTD=y
- CONFIG_MTD_CMDLINE_PARTS=y
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_NAND_DOCG4=m
-
- Note that the docg4 nand driver is configured as a module, because we will
- want to load and unload it with reliable_mode enabled or disabled as needed.
-
- You will also need to specify mtd partitions on the kernel command line. In
- the instructions that follow, we will assume that the flash blocks to which
- u-boot will be programmed are defined by the second partition on the device.
- The u-boot config file (include/configs/palmtreo680.h) places the u-boot image
- at the start of block 6 (offset 0x180000), which is the first writable
- (non-protected) block on the flash (this is also where the PalmOS SPL starts).
- The u-boot image occupies four blocks, so to create the u-boot partition, pass
- this command line to the kernel:
- mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part)
- This will create three partitions:
- protected_part: the first six blocks, which are read-only
- bootloader_part: the next four blocks, for the u-boot image
- filesys_part: the remainder of the device
- The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1,
- and /dev/mtd2 for these partitions, respectively. Ensure that your root file
- system at least has /dev/mtd1 if you are not running udev or mdev.
-
-Userspace Utilities:
-
- In addition to everything necessary to provide a useful userspace environment
- (busybox is indispensable, of course), you will need the mtd-utils package on
- your root filesystem. I use version 1.5.0 of mtd-utils, and I suggest you use
- this version as well, or at leat a version very close to this one, as
- mtd-utils has tended to be fluid.
-
- Note that busybox includes a version of mtd-utils. These are deficient and
- should not be used. When you run one of these utilities (nanddump, etc),
- ensure you are invoking the separate executable from mtd-utils, and not the
- one built into busybox. I recommend that you configure busybox with its
- mtd-utils disabled to avoid any possibility of confusion.
-
- You will also need to cross-compile the userspace Linux utility in
- tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the
- actual write of the u-boot image to flash. This utility links against libmtd
- from the mtd-utils package.
-
-
-Desktop PC-side Software Prerequisites
-======================================
-
-Terminal emulator application:
- minicom, kermit, etc.
-
-Linux kernel:
- Compiled with CONFIG_USB_SERIAL enabled. Build this as a module.
-
-
-Recommended (Not directly related to u-boot)
-============================================
-
-Working directly on the Treo's tiny screen and keypad is difficult and
-error-prone. I recommend that you log into the Linux kernel running on your
-Treo from your desktop PC using ethernet over usb. The desktop's kernel must be
-configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and
-CONFIG_USB_NET_CDC_SUBSET. The Treo's kernel will need CONFIG_USB_ETH, and its
-init script will need to start an ssh daemon like dropbear. Note that the usb0
-network interface will not appear on the desktop PC until the Treo kernel's usb
-ethernet gadget driver has initialized. You must wait for this to occur (watch
-the PC's kernel log) before you can assign usb0 an ip address and log in to the
-Treo. If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can
-pass its ip address on the kernel command line, and obviate the need to
-initialize the network interface in your init script.
-
-Having the Palm usb cable connected to the host has the added benefit of keeping
-power supplied to your Treo, reducing the drain on the battery. If something
-goes wrong while you're programming u-boot to the flash, you will have lots of
-time to correct it before the battery dies.
-
-I have encountered a situation where the kernel is sometimes unable to mount a
-root filesystem on the mmc card due to the mmc controller not initializing in
-time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that
-you build a minimal root filesystem into the kernel using the kernel's initramfs
-feature (CONFIG_BLK_DEV_INITRD). If you want your root filesystem on the mmc
-card, your init script can mount and switch_root to the mmc card after a short
-sleep. But keep in mind that in this case you won't be able to use an mmc card
-to transfer files between your desktop and the Treo once Linux is running.
-Another option for transfering files is to mount an nfs filesystem exported by
-the desktop PC. For greatest convenience, you can export the root filesystem
-itself from your desktop PC and switch_root to it in your init script. This
-will work if your initramfs init script contains a loop that waits for you to
-initialize the usb0 network interface on the desktop PC; e.g., loop while a ping
-to the desktop PC returns an error. After the loop exits, do the nfs mount and
-call switch_root. (You can not use the kernel nfsroot feature because the
-network will not be up when the kernel expects it to be; i.e., not until you
-configure the usb0 interface on the desktop.) Use the nfs 'nolock' option when
-mounting to avoid the need to run a portmapper like rpcbind.
-
-
-Preliminaries
-=============
-
-Once Linux is running on your Treo, you may want to perform a few sanity checks
-before programming u-boot. These checks will verify my assumptions regarding
-all the Treo 680s out there, and also ensure that the flash and mtd-utils are
-working correctly. If you are impatient and reckless, you may skip this
-section, but see disclaimer at the top of this file!
-
-Load the docg4 driver:
-
- $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
-
-We tell the driver to use the docg4's "reliable mode" when writing because this
-is the format required by the IPL, which runs from power-up and loads the first
-portion of u-boot. We must ignore bad blocks because linux mtd uses out-of-band
-(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to
-be misidentified as "bad" by libmtd.
-
-Check the kernel log to ensure that all's well:
-
- $ dmesg | tail
- <... snip ...>
- docg4 docg4: NAND device: 128MiB Diskonchip G4 detected
- 3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4
- Creating 3 MTD partitions on "Msys_Diskonchip_G4":
- 0x000000000000-0x000000180000 : "protected_part"
- 0x000000180000-0x000000280000 : "bootloader_part"
- 0x000000280000-0x000008000000 : "filesys_part"
-
-Ensure that the partition boundaries are as shown. (If no partitions are shown,
-did you remember to pass them to the kernel on the command line?) We will write
-u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4
-256k blocks. This partition is accessed through the device node /dev/mtd1.
-
-The docg4 contains a read-only table that identifies blocks that were marked as
-bad at the factory. This table is in the page at offset 0x2000, which is within
-the partition protected_part (/dev/mtd0). There is a slight chance that one or
-more of the four blocks that we will use for u-boot is listed in the table, so
-use nanddump to inspect the table to see if this is the case:
-
- $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0
- ECC failed: 0
- ECC corrected: 0
- Number of bad blocks: 0
- Number of bbt blocks: 0
- Block size 262144, page size 512, OOB size 16
- Dumping data starting at 0x00002000 and ending at 0x00002200...
- 0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
- <... snip ...>
-
-The format of the table is simple: one bit per block, with block numbers
-increasing from left to right, starting with block 0 as the most significant bit
-of the first byte. A bit will be clear if the corresponding block is bad. We
-want to use blocks 6 throgh 9, so both of the two least significant bits of the
-first byte must be set, as must the two most significant bits of the second
-byte. If this is not true in your case (you are very unlucky), you should use
-the first contiguous set of four good blocks after block 6, and adjust the
-partition boundaries accordingly. You will also have to change the value of
-CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile
-u-boot. Because the two blocks loaded by the IPL do not have to be contiguous,
-but our SPL expects them to be, you will need to erase any good blocks that are
-at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find
-the magic number in oob and load it. Once you have done all this, the
-instructions in this file still apply, except that the instructions below for
-restoring the original PalmOS block contents may need to be modified.
-
-Next, use nanddump to verify that the PalmOS SPL is where we expect it to be.
-The SPL can be identified by a magic number in the oob bytes of the first page
-of each of the two blocks containing the SPL image. Pages are 512 bytes in
-size, so to dump the first page, plus the oob:
-
- $ nanddump -p -l 512 -s 0 -o /dev/mtd1
- ECC failed: 0
- ECC corrected: 0
- Number of bad blocks: 0
- Number of bbt blocks: 0
- Block size 262144, page size 512, OOB size 16
- Dumping data starting at 0x00000000 and ending at 0x00000200...
- 0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
- <... snip ...>
- 0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42
- OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff
-
-Verify that the first seven bytes of oob data match those in the above line.
-(This is ASCII "BIPO000".)
-
-Do the same for the next block:
- $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1
-
-The first seven oob bytes in last line should read:
-
- OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff
-
-(This is ASCII "BIPO001".)
-
-For additional assurance, verify that the next block does *not* contain SPL
-data.
-
- $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1
-
-It doesn't matter what the oob contains, as long as the first four bytes are
-*not* ASCII "BIPO". PalmOS should only be using two blocks for the SPL
-(although we will need four for u-boot).
-
-If you want, you can back up the contents of bootloader_part to a file. You may
-be able to restore it later, if desired (see "Restoring PalmOS" below).
-
- $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1
-
-nanddump will spew voluminous warnings about uncorrectable ecc errors. This is
-a consequence of reading pages that were written in reliable mode, and is
-expected (these should all occur on pages in odd-numbered 2k regions; i.e.,
-0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...). The size of the file
-bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512
-plus 16 oob bytes. If you are using initramfs for the root filesystem, don't
-forget to copy the file to permanent storage, such as an mmc card.
-
-If all of the above went well, you can now program u-boot.
-
-
-Programming u-boot
-==================
-
-Our u-boot includes a small SPL that must be prepended to u-boot proper. From
-the base u-boot source directory on your desktop PC:
-
- $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin
-
-cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the
-Treo:
-
- $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd
-
-Substitute variable values from your cross-compilation environment as
-appropriate. Note that it links to libmtd from mtd-utils, and this must be
-included in $(LIBPATH) and $(INCLUDEPATH).
-
-Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's
-root filesystem. On the Treo, cd to the directory where these files were
-placed.
-
-Load the docg4 driver if you have not already done so.
-
- $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
-
-Erase the blocks to which we will write u-boot:
-
- $ flash_erase /dev/mtd1 0x00 4
-
-If no errors are reported, write u-boot to the flash:
-
- $ ./flash_u-boot u-boot-concat.bin /dev/mtd1
-
-You can use nanddump (see above) to verify that the data was written. This
-time, "BIPO" should be seen in the first four oob bytes of the first page of all
-four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000.
-
-Shutdown linux, remove and re-insert the battery, hold your breath...
-
-
-Enjoying u-boot
-===============
-
-After you insert the battery, the u-boot splash screen should appear on the lcd
-after a few seconds. With the usb cable connecting the Treo to your PC, in the
-kernel log of your PC you should see
-
- <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6
- <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
- <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty
- <6>usb 3-1: Manufacturer: Das U-Boot
-
-Load the usbserial module on your desktop PC:
-
- $ modprobe usbserial vendor=0x0525 product=0xa4a6
-
-and run your favorite terminal emulation utility (minicom, kermit, etc) with the
-serial device set to /dev/ttyUSB0 (assuming this is your only usb serial
-device). You should be at the u-boot console (type 'help').
-
-There is not much that is unique about using u-boot on the palm treo 680.
-Kernels can be loaded from mmc, flash, and from the desktop PC via kermit. You
-can expand the size of the second partition on the flash to contain a kernel, or
-else put the kernel(s) in their own partition.
-
-Nand commands work as expected, with the excepton that blocks not written by the
-linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if
-they contain data in the oob bytes. This will be the case for the blocks
-containing the u-boot image, for example. To work around this, use 'nand scrub'
-instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them
-to memory. (It would be useful if u-boot's nand commands provided a way to
-explicitly ignore "bad" blocks, because read.raw does not perform ecc.) The
-'nand dump' command will read these "bad" blocks, however.
-
-Currently u-boot itself can only be programmed to flash from Linux; there is no
-support for reliable mode in u-boot's docg4 flash driver. This should be
-corrected soon.
-
-
-Customizing
-===========
-
-If you change u-boot's configuration significantly (adding or removing
-features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE.
-This is the size of the concatenated spl + u-boot image, and tells the SPL how
-many flash blocks it needs to load. It will be rounded up to the next 64k
-boundary (the spl flash block capacity), so it does not have to be exact, but
-you must ensure that it is not less than the actual image size. If it is larger
-than the image, blocks may be needlessly loaded, but if too small, u-boot may
-only be partially loaded, resulting in a boot failure (bricked phone), so better
-to be too large. The flash_u-boot utility will work with any size image and
-write the required number of blocks, provided that the partition is large
-enough.
-
-As the first writable block on the device, block 6 seems to make the most sense
-as the flash offset for writing u-boot (and this is where PalmOS places its
-SPL). But you can place it elsewhere if you like. If you do, you need to
-adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks
-preceeding the ones containing u-boot do *not* have the magic number in oob (the
-IPL looks for this). In other words, make sure that any blocks that previously
-contained the u-boot image or PalmOS SPL are erased (and optionally written with
-something else) so that the IPL does not load it. Also make sure that the new
-u-boot starting offset is at the start of a flash partition (check the kernel
-log after loading the docg4 driver), and pass the corresponding mtd device file
-to the flash_u-boot utility.
-
-The u-boot built-in default environment is used because a writable environment
-in flash did not seem worth the cost of a 256k flash block. But adding this
-should be straightforward.
-
-
-Restoring PalmOS
-================
-
-If you backed up the contents of bootloader_part flash partition earlier, you
-should be able to restore it with the shell script shown below. The first two
-blocks of data contain the PalmOS SPL and were written in reliable mode, whereas
-the next two blocks were written in normal mode, so the script has to load and
-unload the docg4 driver. Make sure that the mtd-utils nandwrite and flash_erase
-are in your path (and are not those from busybox). Also double-check that the
-backup image file bootloader_part.orig is exactly 1081344 bytes in length. If
-not, it was not backed up correctly. Run the script as:
-
- ./restore_bootpart bootloader_part.orig /dev/mtd1
-
-The script will take a minute or so to run. When it finishes, you may want to
-verify with nanddump that the data looks correct before you cycle power, because
-if the backup or restore failed, your phone will be bricked. Note that as a
-consequence of reliable mode, the odd-numbered 2k regions in the first two
-blocks will not exactly match the contents of the backup file, (so unfortunately
-we can't simply dump the flash contents to a file and do a binary diff with the
-original back-up image to verify that it was restored correctly). Also,
-nanddump will report uncorrectable ecc errors when it reads those regions.
-
-#!/bin/sh
-
-if [ $# -ne 2 ]; then
- echo "usage: $0: <image file> <mtd device node>"
- exit 1
-fi
-
-# reliable mode used for the first two blocks
-modprobe -r docg4
-modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1
-
-# erase all four blocks
-flash_erase $2 0 4
-
-# Program the first two blocks in reliable mode.
-# 2k (4 pages) is written at a time, skipping alternate 2k regions
-# Note that "2k" is 2112 bytes, including 64 oob bytes
-file_ofs=0
-flash_ofs=0
-page=0
-while [ $page -ne 1024 ]; do
- dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1
- file_ofs=$((file_ofs+2))
- flash_ofs=$((flash_ofs+0x1000))
- page=$((page+8))
-done;
-
-# normal mode used for the next two blocks
-modprobe -r docg4
-modprobe docg4 ignore_badblocks=1 || exit 1
-dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1
-modprobe -r docg4
-
-TODO
-====
-
- - Keypad support.
- - Interactive boot menu using keypad and lcd.
- - Add reliable mode support to the u-boot docg4 driver.
- - U-boot command that will write a new image to the bootloader partition in
- flash.
- - Linux FTD support.
diff --git a/board/palmtreo680/palmtreo680.c b/board/palmtreo680/palmtreo680.c
deleted file mode 100644
index f4f6e1f..0000000
--- a/board/palmtreo680/palmtreo680.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Palm Treo 680 Support
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <nand.h>
-#include <malloc.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch-pxa/pxa.h>
-#include <asm/arch-pxa/regs-mmc.h>
-#include <asm/io.h>
-#include <asm/global_data.h>
-#include <u-boot/crc.h>
-#include <linux/mtd/docg4.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct nand_chip docg4_nand_chip;
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* IPL initializes SDRAM (we're already running from it) */
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_LCD
-void lcd_enable(void)
-{
- /*
- * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
- * driver code. We need it as an output gpio.
- */
- writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
-
- /* power-up and enable the lcd */
- writel(0x00400000, GPSR(86)); /* enable; drive high */
- writel(0x00002000, GPSR(77)); /* power; drive high */
- writel(0x02000000, GPCR(25)); /* enable_n; drive low */
-
- /* turn on LCD backlight and configure PWM for reasonable brightness */
- writel(0x00, PWM_CTRL0);
- writel(0x1b1, PWM_PERVAL0);
- writel(0xfd, PWM_PWDUTY0);
- writel(0x00000040, GPSR(38)); /* backlight power on */
-}
-#endif
-
-#ifdef CONFIG_MMC
-int board_mmc_init(bd_t *bis)
-{
- writel(1 << 10, GPSR(42)); /* power on */
- return pxa_mmc_register(0);
-}
-#endif
-
-void board_nand_init(void)
-{
- /* we have one 128M diskonchip G4 */
-
- struct mtd_info *mtd = &nand_info[0];
- struct nand_chip *nand = &docg4_nand_chip;
- if (docg4_nand_init(mtd, nand, 0))
- hang();
-}
-
-#ifdef CONFIG_SPL_BUILD
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- extern const void *_start, *_end; /* boundaries of spl in memory */
-
- /* size of spl; ipl loads this, and then a portion of u-boot */
- const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
-
- /* the flash offset of the blocks that are loaded by the spl */
- const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
- DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
-
- /* total number of bytes loaded by IPL */
- const size_t ipl_load_size =
- DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
-
- /* number of bytes of u-boot proper that was loaded by the IPL */
- const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
-
- /* number of remaining bytes of u-boot that the SPL must load */
- const size_t spl_load_size =
- CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
-
- /* memory address where we resume loading u-boot */
- void *const load_addr =
- (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
-
- /*
- * Copy the portion of u-boot already read from flash by the IPL to its
- * correct load address.
- */
- memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
-
- /*
- * Resume loading u-boot where the IPL left off.
- */
- nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
-
-#ifdef CONFIG_NAND_ENV_DST
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
-#endif
-#endif
- /*
- * Jump to U-Boot image
- */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- (*uboot)();
-}
-
-void board_init_f(ulong bootflag)
-{
- nand_boot();
-}
-
-#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/palmtreo680_defconfig b/configs/palmtreo680_defconfig
deleted file mode 100644
index b56191d..0000000
--- a/configs/palmtreo680_defconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_PALMTREO680=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h
deleted file mode 100644
index 5ffed82..0000000
--- a/include/configs/palmtreo680.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Palm Treo 680 configuration file
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X
-#define CONFIG_PALMTREO680
-#define CONFIG_MACH_TYPE MACH_TYPE_TREO680
-
-#define CONFIG_SYS_MALLOC_LEN (4096*1024)
-
-#define CONFIG_LZMA
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_CONS_INDEX 3
-
-/* we have nand (although technically nand *is* flash...) */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_LCD
-/* #define CONFIG_KEYBOARD */ /* TODO */
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_ACX544AKN
-#define CONFIG_LCD_LOGO
-#define LCD_BPP LCD_COLOR16
-#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */
-#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A
-#define CONFIG_SYS_GAFR1_L_VAL 0x60000002
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959
-#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08
-#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001401
-#define CONFIG_SYS_GPCR0_VAL 0x1FF80400
-#define CONFIG_SYS_GPCR1_VAL 0x03003FC1
-#define CONFIG_SYS_GPCR2_VAL 0x01C1E000
-#define CONFIG_SYS_GPCR3_VAL 0x01C1E000
-#define CONFIG_SYS_GPDR0_VAL 0xCFF90400
-#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1
-#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF
-#define CONFIG_SYS_GPDR3_VAL 0x0069FF81
-#define CONFIG_SYS_GPSR0_VAL 0x02000018
-#define CONFIG_SYS_GPSR1_VAL 0x00000000
-#define CONFIG_SYS_GPSR2_VAL 0x000C0000
-#define CONFIG_SYS_GPSR3_VAL 0x00080000
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01ffffff
-#define CONFIG_SYS_CCCR 0x02000210
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
-#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
-#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
-#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
-#define CONFIG_SYS_MDREFR_VAL 0x201fa031
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
-#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
-#define CONFIG_SYS_MCATT0_VAL 0x0001c391
-#define CONFIG_SYS_MCATT1_VAL 0x0001c391
-#define CONFIG_SYS_MCIO0_VAL 0x00014611
-#define CONFIG_SYS_MCIO1_VAL 0x0001c391
-
-/*
- * USB
- */
-#define CONFIG_USB_DEVICE
-#define CONFIG_USB_TTY
-#define CONFIG_USB_DEV_PULLUP_GPIO 114
-
-/*
- * SPL
- */
-#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */
-#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */
-#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
-#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */
-
-/*
- * NAND
- */
-#define CONFIG_NAND_DOCG4
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
-#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_BITREVERSE /* needed by docg4 driver */
-#define CONFIG_BCH /* needed by docg4 driver */
-
-/*
- * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It
- * will be rounded up to the next 64k boundary (the spl flash block size), so it
- * does not have to be exact, but you must ensure that it is not less than the
- * actual image size, or it may fail to boot (bricked phone)!
- * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
-*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
-
-/*
- * This is the byte offset into the flash at which the concatenated spl + u-boot
- * image is placed. It must be at the start of a block (256k boundary). Blocks
- * 0 - 5 are write-protected, so we start at block 6.
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */
-
-/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-
-/* passed to linker by Makefile as arg to -Ttext option */
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */
-
-/*
- * environment
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BUILD_ENVCRC
-#define CONFIG_ENV_SIZE 0x200
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=usbtty\0" \
- "stdout=usbtty\0" \
- "stderr=usbtty"
-#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
-ip=192.168.11.102:::255.255.255.0:treo:usb0"
-#define CONFIG_BOOTDELAY 3
-
-#if 0 /* example: try 2nd mmc partition, then nand */
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; " \
- "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \
- "bootm 0xa1000000; " \
- "elif nand read 0xa1000000 0x280000 0x240000; then " \
- "bootm 0xa1000000; " \
- "fi; "
-#endif
-
-/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
-#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
-
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (41 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 42/45] arm: Remove palmtreo680 board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 14:50 ` Felipe Balbi
2015-08-31 16:05 ` Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board Simon Glass
` (2 subsequent siblings)
45 siblings, 2 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 --
board/ti/ti814x/Kconfig | 15 ---
board/ti/ti814x/MAINTAINERS | 6 --
board/ti/ti814x/Makefile | 13 ---
board/ti/ti814x/evm.c | 188 -----------------------------------
board/ti/ti814x/evm.h | 8 --
board/ti/ti814x/mux.c | 86 ----------------
configs/ti814x_evm_defconfig | 7 --
include/configs/ti814x_evm.h | 230 -------------------------------------------
9 files changed, 559 deletions(-)
delete mode 100644 board/ti/ti814x/Kconfig
delete mode 100644 board/ti/ti814x/MAINTAINERS
delete mode 100644 board/ti/ti814x/Makefile
delete mode 100644 board/ti/ti814x/evm.c
delete mode 100644 board/ti/ti814x/evm.h
delete mode 100644 board/ti/ti814x/mux.c
delete mode 100644 configs/ti814x_evm_defconfig
delete mode 100644 include/configs/ti814x_evm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8ef21a3..1a171d1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -378,11 +378,6 @@ config TARGET_BAV335X
For more information, visit: http://birdland.com/oem
-config TARGET_TI814X_EVM
- bool "Support ti814x_evm"
- select CPU_V7
- select SUPPORT_SPL
-
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
select CPU_V7
@@ -859,7 +854,6 @@ source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
-source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
deleted file mode 100644
index 2960099..0000000
--- a/board/ti/ti814x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI814X_EVM
-
-config SYS_BOARD
- default "ti814x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "ti814x_evm"
-
-endif
diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS
deleted file mode 100644
index e39b253..0000000
--- a/board/ti/ti814x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI814X BOARD
-M: Matt Porter <matt.porter@linaro.org>
-S: Maintained
-F: board/ti/ti814x/
-F: include/configs/ti814x_evm.h
-F: configs/ti814x_evm_defconfig
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
deleted file mode 100644
index 93155de..0000000
--- a/board/ti/ti814x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y := mux.o
-endif
-
-obj-y += evm.o
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
deleted file mode 100644
index e406dab..0000000
--- a/board/ti/ti814x/evm.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * evm.c
- *
- * Board functions for TI814x EVM
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include "evm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-static const struct cmd_control evm_ddr2_cctrl_data = {
- .cmd0csratio = 0x80,
- .cmd0iclkout = 0x00,
-
- .cmd1csratio = 0x80,
- .cmd1iclkout = 0x00,
-
- .cmd2csratio = 0x80,
- .cmd2iclkout = 0x00,
-};
-
-static const struct emif_regs evm_ddr2_emif0_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-static const struct emif_regs evm_ddr2_emif1_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x806c0300,
- .dmm_lisa_map_3 = 0x806c0300,
-};
-
-static const struct ddr_data evm_ddr2_data = {
- .datardsratio0 = ((0x35<<10) | (0x35<<0)),
- .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
- .datawiratio0 = ((0<<10) | (0<<0)),
- .datagiratio0 = ((0<<10) | (0<<0)),
- .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
- .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
-};
-
-void set_uart_mux_conf(void)
-{
- /* Set UART pins */
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Set MMC pins */
- enable_mmc1_pin_mux();
-
- /* Set Ethernet pins */
- enable_enet_pin_mux();
-}
-
-void sdram_init(void)
-{
- config_dmm(&evm_lisa_map_regs);
-
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif0_regs, 0);
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif1_regs, 1);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- return 0;
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(1, 0, 0, -1, -1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x50,
- .sliver_reg_ofs = 0x700,
- .phy_addr = 1,
- },
- {
- .slave_reg_ofs = 0x90,
- .sliver_reg_ofs = 0x740,
- .phy_addr = 0,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x100,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0x600,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x28,
- .hw_stats_reg_ofs = 0x400,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_1,
-};
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- else
- printf("Unable to read MAC address. Set <ethaddr>\n");
- }
-
- return cpsw_register(&cpsw_data);
-}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
deleted file mode 100644
index 6aebec6..0000000
--- a/board/ti/ti814x/evm.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _EVM_H
-#define _EVM_H
-
-void enable_uart0_pin_mux(void);
-void enable_mmc1_pin_mux(void);
-void enable_enet_pin_mux(void);
-
-#endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
deleted file mode 100644
index fd9f364..0000000
--- a/board/ti/ti814x/mux.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "evm.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
- {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
- {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
- {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
- {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
- {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
- {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
- {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
- {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
- {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
- {-1},
-};
-
-static struct module_pin_mux enet_pin_mux[] = {
- {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
- {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
- {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
- {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
- {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
- {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
- {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
- {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
- {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
- {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
- {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
- {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
- {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
- {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
- {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
- {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
- {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
- {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
- {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
- {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
- {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
- {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
- {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
- {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
- {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
- {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
- {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_mmc1_pin_mux(void)
-{
- configure_module_pin_mux(mmc1_pin_mux);
-}
-
-void enable_enet_pin_mux(void)
-{
- configure_module_pin_mux(enet_pin_mux);
-}
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
deleted file mode 100644
index f7d1e11..0000000
--- a/configs/ti814x_evm_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TI814X_EVM=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
deleted file mode 100644
index 7fa35a1..0000000
--- a/include/configs/ti814x_evm.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * ti814x_evm.h
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_TI814X_EVM_H
-#define __CONFIG_TI814X_EVM_H
-
-#define CONFIG_TI81XX
-#define CONFIG_TI814X
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
-
-#include <asm/arch/omap.h>
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG /* for ramdisk support */
-
-/* commands to include */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "rdaddr=0x81000000\0" \
- "bootfile=/boot/uImage\0" \
- "fdtfile=\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
- "ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
- "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootm ${loadaddr}\0" \
- "fdtfile=ti814x-evm.dtb\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot;" \
- "fi;" \
- "fi;" \
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
- + PHYS_DRAM_1_SIZE - (8 << 12))
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
-
-#define CONFIG_OMAP_GPIO
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-/**
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */
-#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
- GENERATED_GBL_DATA_SIZE)
-
-/**
- * Platform/Board specific defs
- */
-#define CONFIG_SYS_TIMERBASE 0x4802E000
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
-
-#define CONFIG_BAUDRATE 115200
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x40300000
-#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#define CONFIG_SPL_BOARD_INIT
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80800000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80800000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
-/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
-/* Ethernet */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ET1011C
-#define CONFIG_PHY_ET1011C_TX_CLK_FIX
-
-#endif /* ! __CONFIG_TI814X_EVM_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (42 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-08-31 16:06 ` Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 45/45] arm: Remove tx25 board Simon Glass
2015-09-01 16:28 ` [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Masahiro Yamada
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 --
board/ti/ti816x/Kconfig | 15 ---
board/ti/ti816x/MAINTAINERS | 6 --
board/ti/ti816x/Makefile | 12 ---
board/ti/ti816x/evm.c | 216 -------------------------------------------
configs/ti816x_evm_defconfig | 7 --
include/configs/ti816x_evm.h | 172 ----------------------------------
7 files changed, 434 deletions(-)
delete mode 100644 board/ti/ti816x/Kconfig
delete mode 100644 board/ti/ti816x/MAINTAINERS
delete mode 100644 board/ti/ti816x/Makefile
delete mode 100644 board/ti/ti816x/evm.c
delete mode 100644 configs/ti816x_evm_defconfig
delete mode 100644 include/configs/ti816x_evm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1a171d1..a87c724 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -378,11 +378,6 @@ config TARGET_BAV335X
For more information, visit: http://birdland.com/oem
-config TARGET_TI816X_EVM
- bool "Support ti816x_evm"
- select CPU_V7
- select SUPPORT_SPL
-
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7
@@ -854,7 +849,6 @@ source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
-source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
deleted file mode 100644
index 95973b4..0000000
--- a/board/ti/ti816x/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TI816X_EVM
-
-config SYS_BOARD
- default "ti816x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "ti816x_evm"
-
-endif
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
deleted file mode 100644
index d3de144..0000000
--- a/board/ti/ti816x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TI816X BOARD
-#M: -
-S: Maintained
-F: board/ti/ti816x/
-F: include/configs/ti816x_evm.h
-F: configs/ti816x_evm_defconfig
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
deleted file mode 100644
index f1cc3d5..0000000
--- a/board/ti/ti816x/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
-# Antoine Tenart, <atenart@adeneo-embedded.com>
-#
-# Based on TI-PSP-04.00.02.14 :
-#
-# Copyright (C) 2009, Texas Instruments, Incorporated
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
deleted file mode 100644
index b6bf162..0000000
--- a/board/ti/ti816x/evm.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * evm.c
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-
-static struct module_pin_mux mmc_pin_mux[] = {
- { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
- { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { -1 },
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x80640300,
- .dmm_lisa_map_3 = 0xC0640320,
-};
-
-/*
- * DDR2 related definitions
- */
-#ifdef CONFIG_TI816X_EVM_DDR2
-static struct ddr_data ddr2_data = {
- .datardsratio0 = ((0x40<<10) | (0x40<<0)),
- .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
- .datawiratio0 = ((0x0<<10) | (0x0<<0)),
- .datagiratio0 = ((0x0<<10) | (0x0<<0)),
- .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
- .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
-};
-
-static struct cmd_control ddr2_ctrl = {
- .cmd0csratio = 0x80,
- .cmd0iclkout = 0x00,
-
- .cmd1csratio = 0x80,
- .cmd1iclkout = 0x00,
-
- .cmd2csratio = 0x80,
- .cmd2iclkout = 0x00,
-
-};
-
-static struct emif_regs ddr2_emif0_regs = {
- .sdram_config = 0x43801A3A,
- .ref_ctrl = 0x10000C30,
- .sdram_tim1 = 0x0AAB15E2,
- .sdram_tim2 = 0x423631D2,
- .sdram_tim3 = 0x0080032F,
- .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
-};
-
-static struct emif_regs ddr2_emif1_regs = {
- .sdram_config = 0x43801A3A,
- .ref_ctrl = 0x10000C30,
- .sdram_tim1 = 0x0AAB15E2,
- .sdram_tim2 = 0x423631D2,
- .sdram_tim3 = 0x0080032F,
- .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
-};
-#endif
-
-/*
- * DDR3 related definitions
- */
-
-#if defined(CONFIG_TI816X_DDR_PLL_400)
-#define RD_DQS 0x03B
-#define WR_DQS 0x0A6
-#define RD_DQS_GATE 0x12A
-#define EMIF_SDCFG 0x62A41032
-#define EMIF_SDREF 0x10000C30
-#define EMIF_TIM1 0x0CCCE524
-#define EMIF_TIM2 0x30308023
-#define EMIF_TIM3 0x009F82CF
-#define EMIF_PHYCFG 0x0000010B
-#elif defined(CONFIG_TI816X_DDR_PLL_531)
-#define RD_DQS 0x039
-#define WR_DQS 0x0B4
-#define RD_DQS_GATE 0x13D
-#define EMIF_SDCFG 0x62A51832
-#define EMIF_SDREF 0x1000102E
-#define EMIF_TIM1 0x0EF136AC
-#define EMIF_TIM2 0x30408063
-#define EMIF_TIM3 0x009F83AF
-#define EMIF_PHYCFG 0x0000010C
-#elif defined(CONFIG_TI816X_DDR_PLL_675)
-#define RD_DQS 0x039
-#define WR_DQS 0x091
-#define RD_DQS_GATE 0x196
-#define EMIF_SDCFG 0x62A63032
-#define EMIF_SDREF 0x10001491
-#define EMIF_TIM1 0x13358875
-#define EMIF_TIM2 0x5051806C
-#define EMIF_TIM3 0x009F84AF
-#define EMIF_PHYCFG 0x0000010F
-#elif defined(CONFIG_TI816X_DDR_PLL_796)
-#define RD_DQS 0x035
-#define WR_DQS 0x093
-#define RD_DQS_GATE 0x1B3
-#define EMIF_SDCFG 0x62A73832
-#define EMIF_SDREF 0x10001841
-#define EMIF_TIM1 0x1779C9FE
-#define EMIF_TIM2 0x50608074
-#define EMIF_TIM3 0x009F857F
-#define EMIF_PHYCFG 0x00000110
-#endif
-
-static struct ddr_data ddr3_data = {
- .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
- .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
- .datawiratio0 = ((0x20<<10) | 0x20<<0),
- .datagiratio0 = ((0x20<<10) | 0x20<<0),
- .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
- .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-};
-
-static const struct cmd_control ddr3_ctrl = {
- .cmd0csratio = 0x100,
- .cmd0iclkout = 0x001,
-
- .cmd1csratio = 0x100,
- .cmd1iclkout = 0x001,
-
- .cmd2csratio = 0x100,
- .cmd2iclkout = 0x001,
-};
-
-static const struct emif_regs ddr3_emif0_regs = {
- .sdram_config = EMIF_SDCFG,
- .ref_ctrl = EMIF_SDREF,
- .sdram_tim1 = EMIF_TIM1,
- .sdram_tim2 = EMIF_TIM2,
- .sdram_tim3 = EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
-};
-
-static const struct emif_regs ddr3_emif1_regs = {
- .sdram_config = EMIF_SDCFG,
- .ref_ctrl = EMIF_SDREF,
- .sdram_tim1 = EMIF_TIM1,
- .sdram_tim2 = EMIF_TIM2,
- .sdram_tim3 = EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
-};
-
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
- configure_module_pin_mux(mmc_pin_mux);
-}
-
-void sdram_init(void)
-{
- config_dmm(&evm_lisa_map_regs);
-
-#ifdef CONFIG_TI816X_EVM_DDR2
- if (CONFIG_TI816X_USE_EMIF0) {
- ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
- (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
- 0);
- }
-
- if (CONFIG_TI816X_USE_EMIF1) {
- ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
- (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
- 1);
- }
-#endif
-
-#ifdef CONFIG_TI816X_EVM_DDR3
- if (CONFIG_TI816X_USE_EMIF0)
- config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
- 0);
-
- if (CONFIG_TI816X_USE_EMIF1)
- config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
- 1);
-#endif
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
deleted file mode 100644
index 1fd2719..0000000
--- a/configs/ti816x_evm_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="u-boot/ti816x# "
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
deleted file mode 100644
index 01d8233..0000000
--- a/include/configs/ti816x_evm.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * ti816x_evm.h
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_TI816X_EVM_H
-#define __CONFIG_TI816X_EVM_H
-
-#define CONFIG_TI81XX
-#define CONFIG_TI816X
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_ARCH_CPU_INIT
-
-#include <asm/arch/omap.h>
-
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
-#define CONFIG_SYS_LONGHELP /* undef save memory */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG /* required for ramdisk support */
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x81000000\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan;" \
- "fatload mmc 0 ${loadaddr} uImage;" \
- "bootm ${loadaddr}" \
-
-#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-
-#define CONFIG_CMD_ASKEN
-#define CONFIG_OMAP_GPIO
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_FS_FAT
-
-/*
- * Only one of the following two options (DDR3/DDR2) should be enabled
- * CONFIG_TI816X_EVM_DDR2
- * CONFIG_TI816X_EVM_DDR3
- */
-#define CONFIG_TI816X_EVM_DDR3
-
-/*
- * Supported values: 400, 531, 675 or 796 MHz
- */
-#define CONFIG_TI816X_DDR_PLL_796
-
-#define CONFIG_TI816X_USE_EMIF0 1
-#define CONFIG_TI816X_USE_EMIF1 1
-
-
-#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
-#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
-#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
-#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
-#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
-
-#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
- GENERATED_GBL_DATA_SIZE)
-
-/**
- * Platform/Board specific defs
- */
-#define CONFIG_SYS_CLK_FREQ 27000000
-#define CONFIG_SYS_TIMERBASE 0x4802E000
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-#undef CONFIG_NAND_OMAP_GPMC
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
-
-#define CONFIG_BAUDRATE 115200
-
-/* allow overwriting serial config and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SERIAL1
-#define CONFIG_SERIAL2
-#define CONFIG_SERIAL3
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x40400000
-#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#define CONFIG_SPL_BOARD_INIT
-
-#define CONFIG_SYS_TEXT_BASE 0x80800000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
-/* Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
-#endif
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 45/45] arm: Remove tx25 board
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (43 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board Simon Glass
@ 2015-08-31 1:19 ` Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,45/45] " Tom Rini
2015-09-01 16:28 ` [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Masahiro Yamada
45 siblings, 1 reply; 119+ messages in thread
From: Simon Glass @ 2015-08-31 1:19 UTC (permalink / raw)
To: u-boot
This board has not been converted to generic board by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 6 --
board/karo/tx25/Kconfig | 15 ---
board/karo/tx25/MAINTAINERS | 6 --
board/karo/tx25/Makefile | 11 ---
board/karo/tx25/lowlevel_init.S | 98 -------------------
board/karo/tx25/tx25.c | 210 ----------------------------------------
configs/tx25_defconfig | 6 --
include/configs/tx25.h | 172 --------------------------------
8 files changed, 524 deletions(-)
delete mode 100644 board/karo/tx25/Kconfig
delete mode 100644 board/karo/tx25/MAINTAINERS
delete mode 100644 board/karo/tx25/Makefile
delete mode 100644 board/karo/tx25/lowlevel_init.S
delete mode 100644 board/karo/tx25/tx25.c
delete mode 100644 configs/tx25_defconfig
delete mode 100644 include/configs/tx25.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a87c724..fbf5840 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -124,11 +124,6 @@ config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
-config TARGET_TX25
- bool "Support tx25"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
config TARGET_ZMX25
bool "Support zmx25"
select CPU_ARM926EJS
@@ -821,7 +816,6 @@ source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/karo/tx25/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig
deleted file mode 100644
index 42746c1..0000000
--- a/board/karo/tx25/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TX25
-
-config SYS_BOARD
- default "tx25"
-
-config SYS_VENDOR
- default "karo"
-
-config SYS_SOC
- default "mx25"
-
-config SYS_CONFIG_NAME
- default "tx25"
-
-endif
diff --git a/board/karo/tx25/MAINTAINERS b/board/karo/tx25/MAINTAINERS
deleted file mode 100644
index 2defe34..0000000
--- a/board/karo/tx25/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TX25 BOARD
-M: John Rigby <jcrigby@gmail.com>
-S: Maintained
-F: board/karo/tx25/
-F: include/configs/tx25.h
-F: configs/tx25_defconfig
diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile
deleted file mode 100644
index add5dd3..0000000
--- a/board/karo/tx25/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2009 DENX Software Engineering
-# Author: John Rigby <jcrigby@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += lowlevel_init.o
-endif
-obj-y += tx25.o
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
deleted file mode 100644
index 11b80b4..0000000
--- a/board/karo/tx25/lowlevel_init.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on U-Boot and RedBoot sources for several different i.mx
- * platforms.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/macro.h>
-#include <asm/arch/macro.h>
-
-.macro init_clocks
- /*
- * clocks
- *
- * first enable CLKO debug output
- * 0x40000000 enables the debug CLKO signal
- * 0x05000000 sets CLKO divider to 6
- * 0x00600000 makes CLKO parent clk the USB clk
- */
- write32 0x53f80064, 0x45600000
-
- /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
- write32 0x53f80008, 0x20034000
-
- /*
- * PCDR2: NFC = 33.25 MHz
- * This is required for the NAND Flash of this board, which is a Samsung
- * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
- * the NFC driver in symmetric (i.e. one-cycle) mode.
- */
- write32 0x53f80020, 0x01010103
-
- /*
- * enable all implemented clocks in all three
- * clock control registers
- */
- write32 0x53f8000c, 0x1fffffff
- write32 0x53f80010, 0xffffffff
- write32 0x53f80014, 0xfdfff
-.endm
-
-.macro init_ddrtype
- /*
- * ddr_type is 3.3v SDRAM
- */
- write32 0x43fac454, 0x800
-.endm
-
-/*
- * sdram controller init
- */
-.macro init_sdram_bank bankaddr, ctl, cfg
- ldr r0, =0xb8001000
- ldr r2, =\bankaddr
- /*
- * reset SDRAM controller
- * then wait for initialization to complete
- */
- ldr r1, =(1 << 1)
- str r1, [r0, #0x10]
-1: ldr r3, [r0, #0x10]
- tst r3, #(1 << 31)
- beq 1b
-
- ldr r1, =0x95728
- str r1, [r0, #\cfg] /* config */
-
- ldr r1, =0x92116480 /* control | precharge */
- str r1, [r0, #\ctl] /* write command to controller */
- str r1, [r2, #0x400] /* command encoded in address */
-
- ldr r1, =0xa2116480 /* auto refresh */
- str r1, [r0, #\ctl]
- ldrb r3, [r2] /* read dram twice to auto refresh */
- ldrb r3, [r2]
-
- ldr r1, =0xb2116480 /* control | load mode */
- str r1, [r0, #\ctl] /* write command to controller */
- strb r1, [r2, #0x33] /* command encoded in address */
-
- ldr r1, =0x82116480 /* control | normal (0)*/
- str r1, [r0, #\ctl] /* write command to controller */
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- init_aips
- init_max
- init_m3if
- init_clocks
-
- init_sdram_bank 0x80000000, 0x0, 0x4
-
- init_sdram_bank 0x90000000, 0x8, 0xc
- mov pc, lr
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
deleted file mode 100644
index 4d1a0ec..0000000
--- a/board/karo/tx25/tx25.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on imx27lite.c:
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- * And:
- * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong bootflag)
-{
- /*
- * copy ourselves from where we are running to where we were
- * linked at. Use ulong pointers as all addresses involved
- * are 4-byte-aligned.
- */
- ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
- asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
- asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
- asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
- asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
- for (dst = start_ptr; dst < end_ptr; dst++)
- *dst = *(dst+(run_ptr-link_ptr));
- /*
- * branch to nand_boot's link-time address.
- */
- asm volatile("ldr pc, =nand_boot");
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL 0
-
-#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
-#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
-
-void tx25_fec_init(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
- NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
- NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
- };
-
- static const iomux_v3_cfg_t fec_cfg_pads[] = {
- MX25_PAD_FEC_RDATA0__GPIO_3_10,
- MX25_PAD_FEC_RDATA1__GPIO_3_11,
- MX25_PAD_FEC_RX_DV__GPIO_3_12,
- };
-
- debug("tx25_fec_init\n");
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* drop PHY power and assert reset (low) */
- gpio_direction_output(GPIO_FEC_RESET_B, 0);
- gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
-
- mdelay(5);
-
- debug("resetting phy\n");
-
- /* turn on PHY power leaving reset asserted */
- gpio_set_value(GPIO_FEC_ENABLE_B, 1);
-
- mdelay(10);
-
- /*
- * Setup some strapping pins that are latched by the PHY
- * as reset goes high.
- *
- * Set PHY mode to 111
- * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
- * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
- * mode2 is tied high so nothing to do
- *
- * Turn on RMII mode
- * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
- */
- /*
- * set each mux mode to gpio mode
- */
- imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
- ARRAY_SIZE(fec_cfg_pads));
-
- /*
- * set each to 1 and make each an output
- */
- gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 11), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 12), 1);
-
- mdelay(22); /* this value came from RedBoot */
-
- /*
- * deassert PHY reset
- */
- gpio_set_value(GPIO_FEC_RESET_B, 1);
-
- mdelay(5);
-
- /*
- * set FEC pins back
- */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-#else
-#define tx25_fec_init()
-#endif
-
-#ifdef CONFIG_MXC_UART
-/*
- * Set up input pins with hysteresis and 100-k pull-ups
- */
-#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define UART1_OUT_PAD_CTRL 0
-
-static void tx25_uart1_init(void)
-{
- static const iomux_v3_cfg_t uart1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-#else
-#define tx25_uart1_init()
-#endif
-
-int board_init()
-{
- tx25_uart1_init();
-
- /* board id for linux */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
- tx25_fec_init();
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
-#else
-
-#endif
-}
-
-int checkboard(void)
-{
- printf("KARO TX25\n");
- return 0;
-}
diff --git a/configs/tx25_defconfig b/configs/tx25_defconfig
deleted file mode 100644
index b752414..0000000
--- a/configs/tx25_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TX25=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
deleted file mode 100644
index 834b616..0000000
--- a/include/configs/tx25.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * KARO TX25 board - SoC Configuration
- */
-#define CONFIG_MX25
-#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */
-#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_MAX_SIZE 2048
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-#define CONFIG_SPL_TEXT_BASE 0x810c0000
-#define CONFIG_SYS_TEXT_BASE 0x81200000
-
-#ifndef MACH_TYPE_TX25
-#define MACH_TYPE_TX25 2177
-#endif
-
-#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-
-#ifdef CONFIG_SPL_BUILD
-/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#else
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Memory Info
- */
-/* malloc() len */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-/*
- * Board has 2 32MB banks of DRAM but there is a bug when using
- * both so only the first is configured
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE 0x02000000
-#if (CONFIG_NR_DRAM_BANKS == 2)
-#define PHYS_SDRAM_2 0x90000000
-#define PHYS_SDRAM_2_SIZE 0x02000000
-#endif
-/* 8MB DRAM test */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
-
-/*
- * Serial Info
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-#define CONFIG_MXC_GPIO
-
-/*
- * Flash & Environment
- */
-/* No NOR flash present */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-
-/* NAND */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (0xBB000000)
-#define CONFIG_JFFS2_NAND
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Print buffer sz */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-
-/* U-Boot commands */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_MII
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=tx25/u-boot.bin\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "hostname=tx25\0" \
- "bootfile=tx25/uImage\0" \
- "rootpath=/opt/eldk/arm\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm\0" \
- "bootcmd=run net_nfs\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
- "upd=run load update\0" \
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
-
-#endif /* __CONFIG_H */
--
2.5.0.457.gab17608
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards
2015-08-31 1:19 ` [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards Simon Glass
@ 2015-08-31 5:30 ` Daniel Gorsulowski
2015-08-31 5:32 ` [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board Daniel Gorsulowski
1 sibling, 0 replies; 119+ messages in thread
From: Daniel Gorsulowski @ 2015-08-31 5:30 UTC (permalink / raw)
To: u-boot
On 31.08.2015 at 03:19 Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-at91/Kconfig | 5 -
> board/esd/meesc/Kconfig | 12 --
> board/esd/meesc/MAINTAINERS | 7 -
> board/esd/meesc/Makefile | 13 --
> board/esd/meesc/meesc.c | 271 --------------------------------------
> board/esd/meesc/partition.c | 23 ----
> configs/meesc_dataflash_defconfig | 9 --
> configs/meesc_defconfig | 9 --
> include/configs/meesc.h | 199 ----------------------------
> 9 files changed, 548 deletions(-)
> delete mode 100644 board/esd/meesc/Kconfig
> delete mode 100644 board/esd/meesc/MAINTAINERS
> delete mode 100644 board/esd/meesc/Makefile
> delete mode 100644 board/esd/meesc/meesc.c
> delete mode 100644 board/esd/meesc/partition.c
> delete mode 100644 configs/meesc_dataflash_defconfig
> delete mode 100644 configs/meesc_defconfig
> delete mode 100644 include/configs/meesc.h
>
...
Hello,
I know, deadline is all over. But I was otherwise engaged within last
few years. Only this mail let me get awoke.
Maybe you'll accept coming patch anyway...
Kind regards,
Daniel
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board
2015-08-31 1:19 ` [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards Simon Glass
2015-08-31 5:30 ` Daniel Gorsulowski
@ 2015-08-31 5:32 ` Daniel Gorsulowski
2015-08-31 13:22 ` Simon Glass
2015-09-11 7:38 ` [U-Boot] [U-Boot, " Andreas Bießmann
1 sibling, 2 replies; 119+ messages in thread
From: Daniel Gorsulowski @ 2015-08-31 5:32 UTC (permalink / raw)
To: u-boot
Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
---
include/configs/meesc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index e5bb873..ab6c910 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -56,6 +56,8 @@
#define CONFIG_DISPLAY_CPUINFO /* display cpu info and
speed */
#define CONFIG_PREBOOT /* enable preboot
variable */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Hardware drivers
*/
--
2.5.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 37/45] arm: Remove vision2 board
2015-08-31 1:19 ` [U-Boot] [PATCH 37/45] arm: Remove vision2 board Simon Glass
@ 2015-08-31 6:40 ` Stefano Babic
2015-09-12 12:50 ` [U-Boot] [U-Boot,37/45] " Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Stefano Babic @ 2015-08-31 6:40 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 31/08/2015 03:19, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
I do not have this board anymore and any attempt to upgrade is useless.
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards
2015-08-31 1:19 ` [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards Simon Glass
@ 2015-08-31 6:41 ` Stefano Babic
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Stefano Babic @ 2015-08-31 6:41 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 31/08/2015 03:19, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
Board is not available anymore - it can be safely removed.
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 09/45] arm: Remove edb9315a board
2015-08-31 1:19 ` [U-Boot] [PATCH 09/45] arm: Remove edb9315a board Simon Glass
@ 2015-08-31 7:38 ` sergey kostanbaev
2015-08-31 13:13 ` Simon Glass
0 siblings, 1 reply; 119+ messages in thread
From: sergey kostanbaev @ 2015-08-31 7:38 UTC (permalink / raw)
To: u-boot
Hi Simon,
It seems I missed moving to generic board CONFIG_SYS_GENERIC_BOARD. So
could you point what is better to read to adopt it?
Thanks
On Mon, Aug 31, 2015 at 4:19 AM, Simon Glass <sjg@chromium.org> wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/Kconfig | 5 -
> board/cirrus/edb93xx/Kconfig | 15 --
> board/cirrus/edb93xx/MAINTAINERS | 6 -
> board/cirrus/edb93xx/Makefile | 11 --
> board/cirrus/edb93xx/edb93xx.c | 382
> ---------------------------------------
> board/cirrus/edb93xx/u-boot.lds | 116 ------------
> configs/edb9315a_defconfig | 6 -
> include/configs/edb93xx.h | 284 -----------------------------
> 8 files changed, 825 deletions(-)
> delete mode 100644 board/cirrus/edb93xx/Kconfig
> delete mode 100644 board/cirrus/edb93xx/MAINTAINERS
> delete mode 100644 board/cirrus/edb93xx/Makefile
> delete mode 100644 board/cirrus/edb93xx/edb93xx.c
> delete mode 100644 board/cirrus/edb93xx/u-boot.lds
> delete mode 100644 configs/edb9315a_defconfig
> delete mode 100644 include/configs/edb93xx.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5429dc8..fa52901 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -69,10 +69,6 @@ choice
> config ARCH_AT91
> bool "Atmel AT91"
>
> -config TARGET_EDB93XX
> - bool "Support edb93xx"
> - select CPU_ARM920T
> -
> config TARGET_SCB9328
> bool "Support scb9328"
> select CPU_ARM920T
> @@ -889,7 +885,6 @@ source "board/boundary/nitrogen6x/Kconfig"
> source "board/broadcom/bcm28155_ap/Kconfig"
> source "board/broadcom/bcmcygnus/Kconfig"
> source "board/broadcom/bcmnsp/Kconfig"
> -source "board/cirrus/edb93xx/Kconfig"
> source "board/compulab/cm_t335/Kconfig"
> source "board/compulab/cm_t43/Kconfig"
> source "board/compulab/cm_fx6/Kconfig"
> diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
> deleted file mode 100644
> index c5f4897..0000000
> --- a/board/cirrus/edb93xx/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_EDB93XX
> -
> -config SYS_BOARD
> - default "edb93xx"
> -
> -config SYS_VENDOR
> - default "cirrus"
> -
> -config SYS_SOC
> - default "ep93xx"
> -
> -config SYS_CONFIG_NAME
> - default "edb93xx"
> -
> -endif
> diff --git a/board/cirrus/edb93xx/MAINTAINERS
> b/board/cirrus/edb93xx/MAINTAINERS
> deleted file mode 100644
> index 3bb2843..0000000
> --- a/board/cirrus/edb93xx/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -EDB93XX BOARD
> -M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
> -S: Maintained
> -F: board/cirrus/edb93xx/
> -F: include/configs/edb93xx.h
> -F: configs/edb9315a_defconfig
> diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
> deleted file mode 100644
> index d03c498..0000000
> --- a/board/cirrus/edb93xx/Makefile
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -#
> -# (C) Copyright 2013
> -# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
> -#
> -# (C) Copyright 2003-2006
> -# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
> -#
> -# * SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := edb93xx.o
> diff --git a/board/cirrus/edb93xx/edb93xx.c
> b/board/cirrus/edb93xx/edb93xx.c
> deleted file mode 100644
> index 8963d3a..0000000
> --- a/board/cirrus/edb93xx/edb93xx.c
> +++ /dev/null
> @@ -1,382 +0,0 @@
> -/*
> - * Board initialization for EP93xx
> - *
> - * Copyright (C) 2013
> - * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
> - *
> - * Copyright (C) 2009
> - * Matthias Kaehlcke <matthias <at> kaehlcke.net>
> - *
> - * (C) Copyright 2002 2003
> - * Network Audio Technologies, Inc. <www.netaudiotech.com>
> - * Adam Bezanson <bezanson <at> netaudiotech.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <config.h>
> -#include <common.h>
> -#include <netdev.h>
> -#include <asm/io.h>
> -#include <asm/arch/ep93xx.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * usb_div: 4, nbyp2: 1, pll2_en: 1
> - * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
> - * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
> - */
> -#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
> - 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
> - 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
> - 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
> - SYSCON_CLKSET2_PLL2_EN | \
> - SYSCON_CLKSET2_NBYP2 | \
> - 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
> -
> -#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT
> | \
> - SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
> - 1 << SMC_BCR_MW_SHIFT)
> -
> -/* delay execution before timers are initialized */
> -static inline void early_udelay(uint32_t usecs)
> -{
> - /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz)
> */
> - register uint32_t loops = (usecs * 1000) / 20;
> -
> - __asm__ volatile ("1:\n"
> - "subs %0, %1, #1\n"
> - "bne 1b" : "=r" (loops) : "0" (loops));
> -}
> -
> -#ifndef CONFIG_EP93XX_NO_FLASH_CFG
> -static void flash_cfg(void)
> -{
> - struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
> -
> - writel(SMC_BCR6_VALUE, &smc->bcr6);
> -}
> -#else
> -#define flash_cfg()
> -#endif
> -
> -int board_init(void)
> -{
> - /*
> - * Setup PLL2, PPL1 has been set during lowlevel init
> - */
> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
> - writel(CLKSET2_VAL, &syscon->clkset2);
> -
> - /*
> - * the user's guide recommends to wait at least 1 ms for PLL2 to
> - * stabilize
> - */
> - early_udelay(1000);
> -
> - /* Go to Async mode */
> - __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
> - __asm__ volatile ("orr r0, r0, #0xc0000000");
> - __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
> -
> - icache_enable();
> -
> -#ifdef USE_920T_MMU
> - dcache_enable();
> -#endif
> -
> - /* Machine number, as defined in linux/arch/arm/tools/mach-types */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* adress of boot parameters */
> - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
> -
> - /* We have a console */
> - gd->have_console = 1;
> -
> - enable_interrupts();
> -
> - flash_cfg();
> -
> - green_led_on();
> - red_led_off();
> -
> - return 0;
> -}
> -
> -int board_early_init_f(void)
> -{
> - /*
> - * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
> - * 14.7456/2 MHz
> - */
> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
> - writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
> - return 0;
> -}
> -
> -int board_eth_init(bd_t *bd)
> -{
> - return ep93xx_eth_initialize(0, MAC_BASE);
> -}
> -
> -static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned
> dram_bank_cnt,
> - unsigned
> dram_bank_base[CONFIG_NR_DRAM_BANKS])
> -{
> - if (dram_bank_cnt == 1) {
> - dram_bank_base[0] = PHYS_SDRAM_1;
> - } else {
> - /* Table lookup for holes in address space. Maximum memory
> - * for the single SDCS may be up to 256Mb. We start
> scanning
> - * banks from 1Mb, so it could be up to 128 banks
> theoretically.
> - * We need at maximum 7 bits for the loockup, 8 slots is
> - * enough for the worst case.
> - */
> - unsigned tbl[8];
> - unsigned i = dram_bank_cnt / 2;
> - unsigned j = 0x00100000; /* 1 Mb */
> - unsigned *ptbl = tbl;
> - do {
> - while (!(dram_addr_mask & j)) {
> - j <<= 1;
> - }
> - *ptbl++ = j;
> - j <<= 1;
> - i >>= 1;
> - } while (i != 0);
> -
> - for (i = dram_bank_cnt, j = 0;
> - (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
> - unsigned addr = PHYS_SDRAM_1;
> - unsigned k;
> - unsigned bit;
> -
> - for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
> - if (bit & j)
> - addr |= tbl[k];
> - }
> -
> - dram_bank_base[j] = addr;
> - }
> - }
> -}
> -
> -/* called in board_init_f (before relocation) */
> -static unsigned dram_init_banksize_int(int print)
> -{
> - /*
> - * Collect information of banks that has been filled during
> lowlevel
> - * initialization
> - */
> - unsigned i;
> - unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
> - unsigned dram_total = 0;
> - unsigned dram_bank_size = *(unsigned *)
> - (PHYS_SDRAM_1 |
> UBOOT_MEMORYCNF_BANK_SIZE);
> - unsigned dram_addr_mask = *(unsigned *)
> - (PHYS_SDRAM_1 |
> UBOOT_MEMORYCNF_BANK_MASK);
> - unsigned dram_bank_cnt = *(unsigned *)
> - (PHYS_SDRAM_1 |
> UBOOT_MEMORYCNF_BANK_COUNT);
> -
> - dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
> -
> - for (i = 0; i < dram_bank_cnt; i++) {
> - gd->bd->bi_dram[i].start = dram_bank_base[i];
> - gd->bd->bi_dram[i].size = dram_bank_size;
> - dram_total += dram_bank_size;
> - }
> - for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> - gd->bd->bi_dram[i].start = 0;
> - gd->bd->bi_dram[i].size = 0;
> - }
> -
> - if (print) {
> - printf("DRAM mask: %08x\n", dram_addr_mask);
> - printf("DRAM total %u banks:\n", dram_bank_cnt);
> - printf("bank base-address size\n");
> -
> - if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
> - printf("WARNING! UBoot was configured for %u
> banks,\n"
> - "but %u has been found. "
> - "Supressing extra memory banks\n",
> - CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
> - dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
> - }
> -
> - for (i = 0; i < dram_bank_cnt; i++) {
> - printf(" %u %08x %08x\n",
> - i, dram_bank_base[i], dram_bank_size);
> - }
> - printf(" ------------------------------------------\n"
> - "Total %9d\n\n",
> - dram_total);
> - }
> -
> - return dram_total;
> -}
> -
> -void dram_init_banksize(void)
> -{
> - dram_init_banksize_int(0);
> -}
> -
> -/* called in board_init_f (before relocation) */
> -int dram_init(void)
> -{
> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
> - unsigned sec_id = readl(SECURITY_EXTENSIONID);
> - unsigned chip_id = readl(&syscon->chipid);
> -
> - printf("CPU: Cirrus Logic ");
> - switch (sec_id & 0x000001FE) {
> - case 0x00000008:
> - printf("EP9301");
> - break;
> - case 0x00000004:
> - printf("EP9307");
> - break;
> - case 0x00000002:
> - printf("EP931x");
> - break;
> - case 0x00000000:
> - printf("EP9315");
> - break;
> - default:
> - printf("<unknown>");
> - break;
> - }
> -
> - printf(" - Rev. ");
> - switch (chip_id & 0xF0000000) {
> - case 0x00000000:
> - printf("A");
> - break;
> - case 0x10000000:
> - printf("B");
> - break;
> - case 0x20000000:
> - printf("C");
> - break;
> - case 0x30000000:
> - printf("D0");
> - break;
> - case 0x40000000:
> - printf("D1");
> - break;
> - case 0x50000000:
> - printf("E0");
> - break;
> - case 0x60000000:
> - printf("E1");
> - break;
> - case 0x70000000:
> - printf("E2");
> - break;
> - default:
> - printf("?");
> - break;
> - }
> - printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
> -
> - gd->ram_size = dram_init_banksize_int(1);
> - return 0;
> -}
> -
> -
> -#ifdef CONFIG_EP93XX_SPI
> -#include <spi.h>
> -
> -/*
> - * EGIO0-EGIPO7 -> port A
> - * EGIO8-EGIP15 -> port B
> - */
> -
> -static void ep93xx_set_epgio(unsigned num)
> -{
> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
> - if (num < 8)
> - writel(readl(®s->padr) | (1<<num), ®s->padr);
> - else
> - writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
> -}
> -
> -static void ep93xx_clear_epgio(unsigned num)
> -{
> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
> - if (num < 8)
> - writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
> - else
> - writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
> -}
> -
> -static void ep93xx_dir_epgio_out(unsigned num)
> -{
> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
> - if (num < 8)
> - writel(readl(®s->paddr) | (1<<num), ®s->paddr);
> - else
> - writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
> -}
> -
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> - if (bus == 0 && cs < 16)
> - return 1;
> -
> - return 0;
> -}
> -
> -void spi_cs_activate(struct spi_slave *slave)
> -{
> - ep93xx_clear_epgio(slave->cs);
> -}
> -
> -void spi_cs_deactivate(struct spi_slave *slave)
> -{
> - ep93xx_set_epgio(slave->cs);
> -}
> -
> -#ifdef CONFIG_MMC_SPI
> -#include <mmc.h>
> -
> -#ifndef CONFIG_MMC_SPI_CS_EPGIO
> -# define CONFIG_MMC_SPI_CS_EPGIO 4
> -#endif
> -
> -#ifndef CONFIG_MMC_SPI_SPEED
> -# define CONFIG_MMC_SPI_SPEED 25000000
> -#endif
> -
> -#ifndef CONFIG_MMC_SPI_MODE
> -# define CONFIG_MMC_SPI_MODE SPI_MODE_0
> -#endif
> -
> -int board_mmc_init(bd_t *bis)
> -{
> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
> -
> - ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
> -
> -#ifdef CONFIG_MMC_SPI_POWER_EGPIO
> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
> - ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
> -#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
> - ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
> -#endif
> - struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
> - CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
> -
> - if (!mmc) {
> - printf("Failed to create MMC Device\n");
> - return 1;
> - }
> - mmc_init(mmc);
> - return 0;
> -}
> -
> -
> -#endif /* CONFIG_MMC_SPI */
> -#endif /* CONFIG_EP93XX_SPI */
> diff --git a/board/cirrus/edb93xx/u-boot.lds
> b/board/cirrus/edb93xx/u-boot.lds
> deleted file mode 100644
> index 4aa7891..0000000
> --- a/board/cirrus/edb93xx/u-boot.lds
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/*
> - *
> - * Copyright (C) 2013
> - * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
> - *
> - * Copyright (c) 2004-2008 Texas Instruments
> - *
> - * (C) Copyright 2002
> - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> -OUTPUT_ARCH(arm)
> -ENTRY(_start)
> -SECTIONS
> -{
> - . = 0x00000000;
> -
> - . = ALIGN(4);
> - .text : {
> - *(.__image_copy_start)
> - *(.vectors)
> - arch/arm/cpu/arm920t/start.o (.text*)
> - . = 0x1000;
> -
> - LONG(0x53555243)
> - *(.text*)
> - }
> -
> - . = ALIGN(4);
> - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> -
> - . = ALIGN(4);
> - .data : {
> - *(.data*)
> - }
> -
> - . = ALIGN(4);
> -
> - . = .;
> -
> - . = ALIGN(4);
> - .u_boot_list : {
> - KEEP(*(SORT(.u_boot_list*)));
> - }
> -
> - . = ALIGN(4);
> -
> - .image_copy_end :
> - {
> - *(.__image_copy_end)
> - }
> -
> - .rel_dyn_start :
> - {
> - *(.__rel_dyn_start)
> - }
> -
> - .rel.dyn : {
> - *(.rel*)
> - }
> -
> - .rel_dyn_end :
> - {
> - *(.__rel_dyn_end)
> - }
> -
> - .end :
> - {
> - *(.__end)
> - }
> -
> - _image_binary_end = .;
> -
> - /*
> - * Deprecated: this MMU section is used by pxa at present but
> - * should not be used by new boards/CPUs.
> - */
> - . = ALIGN(4096);
> - .mmutable : {
> - *(.mmutable)
> - }
> -
> -/*
> - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
> - * __bss_base and __bss_limit are for linker only (overlay ordering)
> - */
> -
> - .bss_start __rel_dyn_start (OVERLAY) : {
> - KEEP(*(.__bss_start));
> - __bss_base = .;
> - }
> -
> - .bss __bss_base (OVERLAY) : {
> - *(.bss*)
> - . = ALIGN(4);
> - __bss_limit = .;
> - }
> -
> - .bss_end __bss_limit (OVERLAY) : {
> - KEEP(*(.__bss_end));
> - }
> -
> - .dynsym _image_binary_end : { *(.dynsym) }
> - .dynbss : { *(.dynbss) }
> - .dynstr : { *(.dynstr*) }
> - .dynamic : { *(.dynamic*) }
> - .plt : { *(.plt*) }
> - .interp : { *(.interp*) }
> - .gnu.hash : { *(.gnu.hash) }
> - .gnu : { *(.gnu*) }
> - .ARM.exidx : { *(.ARM.exidx*) }
> - .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
> -}
> diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
> deleted file mode 100644
> index 452bf0d..0000000
> --- a/configs/edb9315a_defconfig
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_TARGET_EDB93XX=y
> -CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
> -# CONFIG_CMD_XIMG is not set
> -# CONFIG_CMD_FPGA is not set
> -# CONFIG_CMD_SETEXPR is not set
> diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
> deleted file mode 100644
> index efe2a9d..0000000
> --- a/include/configs/edb93xx.h
> +++ /dev/null
> @@ -1,284 +0,0 @@
> -/*
> - * U-boot - Configuration file for Cirrus Logic EDB93xx boards
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#ifdef CONFIG_MK_edb9301
> -#define CONFIG_EDB9301
> -#elif defined(CONFIG_MK_edb9302)
> -#define CONFIG_EDB9302
> -#elif defined(CONFIG_MK_edb9302a)
> -#define CONFIG_EDB9302A
> -#elif defined(CONFIG_MK_edb9307)
> -#define CONFIG_EDB9307
> -#elif defined(CONFIG_MK_edb9307a)
> -#define CONFIG_EDB9307A
> -#elif defined(CONFIG_MK_edb9312)
> -#define CONFIG_EDB9312
> -#elif defined(CONFIG_MK_edb9315)
> -#define CONFIG_EDB9315
> -#elif defined(CONFIG_MK_edb9315a)
> -#define CONFIG_EDB9315A
> -#else
> -#error "no board defined"
> -#endif
> -
> -/* Initial environment and monitor configuration options. */
> -#define CONFIG_BOOTDELAY 2
> -#define CONFIG_CMDLINE_TAG 1
> -#define CONFIG_INITRD_TAG 1
> -#define CONFIG_SETUP_MEMORY_TAGS 1
> -#define CONFIG_BOOTARGS "root=/dev/nfs
> console=ttyAM0,115200 ip=dhcp"
> -#define CONFIG_BOOTFILE "edb93xx.img"
> -
> -#define CONFIG_SYS_HUSH_PARSER 1
> -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> -
> -
> -#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
> -
> -#undef CONFIG_SYS_PROMPT
> -#ifdef CONFIG_EDB9301
> -#define CONFIG_EP9301
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
> -#define CONFIG_SYS_PROMPT "EDB9301> "
> -#define CONFIG_ENV_SECT_SIZE 0x00020000
> -#elif defined(CONFIG_EDB9302)
> -#define CONFIG_EP9302
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
> -#define CONFIG_SYS_PROMPT "EDB9302> "
> -#define CONFIG_ENV_SECT_SIZE 0x00020000
> -#elif defined(CONFIG_EDB9302A)
> -#define CONFIG_EP9302
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
> -#define CONFIG_SYS_PROMPT "EDB9302A> "
> -#define CONFIG_ENV_SECT_SIZE 0x00020000
> -#elif defined(CONFIG_EDB9307)
> -#define CONFIG_EP9307
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
> -#define CONFIG_SYS_PROMPT "EDB9307> "
> -#define CONFIG_ENV_SECT_SIZE 0x00040000
> -#elif defined(CONFIG_EDB9307A)
> -#define CONFIG_EP9307
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
> -#define CONFIG_SYS_PROMPT "EDB9307A> "
> -#define CONFIG_ENV_SECT_SIZE 0x00020000
> -#elif defined(CONFIG_EDB9312)
> -#define CONFIG_EP9312
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
> -#define CONFIG_SYS_PROMPT "EDB9312> "
> -#define CONFIG_ENV_SECT_SIZE 0x00040000
> -#elif defined(CONFIG_EDB9315)
> -#define CONFIG_EP9315
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
> -#define CONFIG_SYS_PROMPT "EDB9315> "
> -#define CONFIG_ENV_SECT_SIZE 0x00040000
> -#elif defined(CONFIG_EDB9315A)
> -#define CONFIG_EP9315
> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
> -#define CONFIG_SYS_PROMPT "EDB9315A> "
> -#define CONFIG_ENV_SECT_SIZE 0x00020000
> -#else
> -#error "no board defined"
> -#endif
> -
> -/* High-level configuration options */
> -#define CONFIG_EP93XX 1 /* This is a Cirrus Logic
> 93xx SoC */
> -
> -#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456
> clock */
> -#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
> -
> -/* Monitor configuration */
> -#undef CONFIG_CMD_DATE
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_JFFS2
> -
> -#define CONFIG_SYS_LONGHELP /* Enable "long" help in
> mon */
> -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size
> */
> -/* Print buffer size */
> -#define CONFIG_SYS_PBSIZE
> (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> -/* Boot argument buffer size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -#define CONFIG_SYS_MAXARGS 16 /* Max number of command
> args */
> -
> -/* Serial port hardware configuration */
> -#define CONFIG_PL010_SERIAL
> -#define CONFIG_CONS_INDEX 0
> -#define CONFIG_BAUDRATE 115200
> -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
> - 115200, 230400}
> -#define CONFIG_SYS_SERIAL0 0x808C0000
> -#define CONFIG_SYS_SERIAL1 0x808D0000
> -/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
> - (void *)CONFIG_SYS_SERIAL1} */
> -
> -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
> -
> -/* Status LED */
> -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
> -#define CONFIG_BOARD_SPECIFIC_LED 1
> -#define STATUS_LED_GREEN 0
> -#define STATUS_LED_RED 1
> -/* Green */
> -#define STATUS_LED_BIT STATUS_LED_GREEN
> -#define STATUS_LED_STATE STATUS_LED_ON
> -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
> -/* Red */
> -#define STATUS_LED_BIT1 STATUS_LED_RED
> -#define STATUS_LED_STATE1 STATUS_LED_OFF
> -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
> -/* Optional value */
> -#define STATUS_LED_BOOT STATUS_LED_BIT
> -
> -/* Network hardware configuration */
> -#define CONFIG_DRIVER_EP93XX_MAC
> -#define CONFIG_MII_SUPPRESS_PREAMBLE
> -#define CONFIG_MII
> -#define CONFIG_PHY_ADDR 1
> -#undef CONFIG_NETCONSOLE
> -
> -/* SDRAM configuration */
> -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
> - defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
> - defined(CONFIG_EDB9315)
> -/*
> - * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
> - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We
> set
> - * the SROMLL bit on the processor, resulting in this non-contiguous
> memory map.
> - *
> - * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
> - * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total
> of
> - * 64 MB of SDRAM.
> - */
> -
> -#define CONFIG_EDB93XX_SDCS3
> -
> -#elif defined(CONFIG_EDB9302A) || \
> - defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
> -/*
> - * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
> - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We
> set
> - * the SROMLL bit on the processor, resulting in this non-contiguous
> memory map.
> - *
> - * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x
> Samsung
> - * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of
> SDRAM.
> - */
> -#define CONFIG_EDB93XX_SDCS0
> -
> -#else
> -#error "no SDCS configuration for this board"
> -#endif
> -
> -
> -#if defined(CONFIG_EDB93XX_SDCS3)
> -#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
> -#define PHYS_SDRAM_1 0x00000000
> -#elif defined(CONFIG_EDB93XX_SDCS0)
> -#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
> -#define PHYS_SDRAM_1 0xc0000000
> -#endif
> -
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_NR_DRAM_BANKS 8
> -
> -#define CONFIG_SYS_INIT_SP_ADDR \
> - (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
> -
> -
> -/* Must match kernel config */
> -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
> -
> -/* Run-time memory allocatons */
> -#define CONFIG_SYS_GBL_DATA_SIZE 128
> -#define CONFIG_STACKSIZE (128 * 1024)
> -
> -#if defined(CONFIG_USE_IRQ)
> -#define CONFIG_STACKSIZE_IRQ (4 * 1024)
> -#define CONFIG_STACKSIZE_FIQ (4 * 1024)
> -#endif
> -
> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
> -
> -/*
> -----------------------------------------------------------------------------
> - * FLASH and environment organization
> - *
> - * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash
> memory at
> - * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a
> 16-bit
> - * data bus, for a total of 16 MB of CFI-compatible flash.
> - *
> - * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
> - * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a
> 32-bit
> - * data bus, for a total of 32 MB of CFI-compatible flash.
> - *
> - *
> - * EDB9301/02(a)7a/15a EDB9307/12/15
> - * 0x60000000 - 0x0003FFFF u-boot u-boot
> - * 0x60040000 - 0x0005FFFF environment #1 environment #1
> - * 0x60060000 - 0x0007FFFF environment #2 environment #1
> (continued)
> - * 0x60080000 - 0x0009FFFF unused environment #2
> - * 0x600A0000 - 0x000BFFFF unused environment #2
> (continued)
> - * 0x600C0000 - 0x00FFFFFF unused unused
> - * 0x61000000 - 0x01FFFFFF not present unused
> - */
> -#define CONFIG_SYS_FLASH_CFI
> -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> -
> -
> -#define CONFIG_SYS_FLASH_PROTECTION
> -#define CONFIG_FLASH_CFI_DRIVER
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1
> -#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
> -
> -#define CONFIG_SYS_TEXT_BASE 0x60000000
> -#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
> -
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
> -
> -#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
> -#define CONFIG_ENV_IS_IN_FLASH
> -
> -#define CONFIG_ENV_ADDR 0x60040000
> -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR +
> CONFIG_ENV_SECT_SIZE)
> -
> -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> -
> -/* Define to enable MMC on SPI support */
> -/* #define CONFIG_EP93XX_SPI_MMC */
> -
> -#ifdef CONFIG_EP93XX_SPI_MMC
> -#define CONFIG_EP93XX_SPI
> -#define CONFIG_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_MMC_SPI
> -#define CONFIG_CMD_MMC
> -#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
> -#endif
> -
> -#define CONFIG_USB_STORAGE
> -#define CONFIG_USB_OHCI_NEW
> -#define CONFIG_USB_OHCI_EP93XX
> -#define CONFIG_SYS_USB_OHCI_CPU_INIT
> -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
> -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
> -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
> -
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_EXT4
> -#define CONFIG_CMD_FAT
> -#define CONFIG_CMD_USB
> -
> -#define CONFIG_BOARD_EARLY_INIT_F
> -#define CONFIG_CMD_BOOTZ
> -
> -/* Define to disable flash configuration*/
> -/* #define CONFIG_EP93XX_NO_FLASH_CFG */
> -
> -/* Define this for indusrial rated chips */
> -/* #define CONFIG_EDB93XX_INDUSTRIAL */
> -
> -#endif /* !defined (__CONFIG_H) */
> --
> 2.5.0.457.gab17608
>
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-08-31 1:18 ` [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards Simon Glass
@ 2015-08-31 7:51 ` Simon Guinot
2015-08-31 13:16 ` Simon Glass
0 siblings, 1 reply; 119+ messages in thread
From: Simon Guinot @ 2015-08-31 7:51 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove all except edmini_v2 (which has been converted).
Hi Simon,
Great... Is it still time to convert this boards to "generic board"
support ?
You know, a direct email (I mean with my email address in the To or Cc
fields) to make me aware of this project would have been both fair and
very appreciated.
Thanks,
Simon
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-kirkwood/Kconfig | 12 --
> board/LaCie/net2big_v2/Kconfig | 12 --
> board/LaCie/net2big_v2/MAINTAINERS | 11 --
> board/LaCie/net2big_v2/Makefile | 15 --
> board/LaCie/net2big_v2/kwbimage.cfg | 151 -----------------
> board/LaCie/net2big_v2/net2big_v2.c | 253 ----------------------------
> board/LaCie/net2big_v2/net2big_v2.h | 29 ----
> board/LaCie/netspace_v2/Kconfig | 12 --
> board/LaCie/netspace_v2/MAINTAINERS | 14 --
> board/LaCie/netspace_v2/Makefile | 12 --
> board/LaCie/netspace_v2/kwbimage-is2.cfg | 151 -----------------
> board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 151 -----------------
> board/LaCie/netspace_v2/kwbimage.cfg | 151 -----------------
> board/LaCie/netspace_v2/netspace_v2.c | 117 -------------
> board/LaCie/netspace_v2/netspace_v2.h | 23 ---
> board/LaCie/wireless_space/Kconfig | 12 --
> board/LaCie/wireless_space/MAINTAINERS | 6 -
> board/LaCie/wireless_space/Makefile | 12 --
> board/LaCie/wireless_space/kwbimage.cfg | 71 --------
> board/LaCie/wireless_space/wireless_space.c | 165 ------------------
> configs/net2big_v2_defconfig | 8 -
> configs/netspace_lite_v2_defconfig | 8 -
> configs/netspace_max_v2_defconfig | 8 -
> configs/netspace_mini_v2_defconfig | 8 -
> configs/netspace_v2_defconfig | 8 -
> configs/wireless_space_defconfig | 7 -
> include/configs/lacie_kw.h | 214 -----------------------
> include/configs/wireless_space.h | 179 --------------------
> 28 files changed, 1820 deletions(-)
> delete mode 100644 board/LaCie/net2big_v2/Kconfig
> delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS
> delete mode 100644 board/LaCie/net2big_v2/Makefile
> delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg
> delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c
> delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h
> delete mode 100644 board/LaCie/netspace_v2/Kconfig
> delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS
> delete mode 100644 board/LaCie/netspace_v2/Makefile
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h
> delete mode 100644 board/LaCie/wireless_space/Kconfig
> delete mode 100644 board/LaCie/wireless_space/MAINTAINERS
> delete mode 100644 board/LaCie/wireless_space/Makefile
> delete mode 100644 board/LaCie/wireless_space/kwbimage.cfg
> delete mode 100644 board/LaCie/wireless_space/wireless_space.c
> delete mode 100644 configs/net2big_v2_defconfig
> delete mode 100644 configs/netspace_lite_v2_defconfig
> delete mode 100644 configs/netspace_max_v2_defconfig
> delete mode 100644 configs/netspace_mini_v2_defconfig
> delete mode 100644 configs/netspace_v2_defconfig
> delete mode 100644 configs/wireless_space_defconfig
> delete mode 100644 include/configs/lacie_kw.h
> delete mode 100644 include/configs/wireless_space.h
>
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index 1261885..1ac99b8 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -40,15 +40,6 @@ config TARGET_TK71
> config TARGET_KM_KIRKWOOD
> bool "KM_KIRKWOOD Board"
>
> -config TARGET_NET2BIG_V2
> - bool "LaCie 2Big Network v2 NAS Board"
> -
> -config TARGET_NETSPACE_V2
> - bool "LaCie netspace_v2 Board"
> -
> -config TARGET_WIRELESS_SPACE
> - bool "LaCie Wireless_space Board"
> -
> config TARGET_IB62X0
> bool "ib62x0 Board"
>
> @@ -78,9 +69,6 @@ source "board/d-link/dns325/Kconfig"
> source "board/iomega/iconnect/Kconfig"
> source "board/karo/tk71/Kconfig"
> source "board/keymile/km_arm/Kconfig"
> -source "board/LaCie/net2big_v2/Kconfig"
> -source "board/LaCie/netspace_v2/Kconfig"
> -source "board/LaCie/wireless_space/Kconfig"
> source "board/raidsonic/ib62x0/Kconfig"
> source "board/Seagate/dockstar/Kconfig"
> source "board/Seagate/goflexhome/Kconfig"
> diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig
> deleted file mode 100644
> index ba460db..0000000
> --- a/board/LaCie/net2big_v2/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_NET2BIG_V2
> -
> -config SYS_BOARD
> - default "net2big_v2"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "lacie_kw"
> -
> -endif
> diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
> deleted file mode 100644
> index 205c75e..0000000
> --- a/board/LaCie/net2big_v2/MAINTAINERS
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -NET2BIG_V2 BOARD
> -#M: -
> -S: Maintained
> -F: board/LaCie/net2big_v2/
> -F: include/configs/lacie_kw.h
> -F: configs/d2net_v2_defconfig
> -
> -NET2BIG_V2 BOARD
> -M: Simon Guinot <simon.guinot@sequanux.org>
> -S: Maintained
> -F: configs/net2big_v2_defconfig
> diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
> deleted file mode 100644
> index f3074af..0000000
> --- a/board/LaCie/net2big_v2/Makefile
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := net2big_v2.o ../common/common.o
> -ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
> -obj-y += ../common/cpld-gpio-bus.o
> -endif
> diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
> deleted file mode 100644
> index 453fcb2..0000000
> --- a/board/LaCie/net2big_v2/kwbimage.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000C30 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000CCCC # DDR Address Control
> -# bit1-0: 01, Cs0width=x16
> -# bit3-2: 11, Cs0size=1Gb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000662 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000044 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
> deleted file mode 100644
> index 263bb54..0000000
> --- a/board/LaCie/net2big_v2/net2big_v2.c
> +++ /dev/null
> @@ -1,253 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <i2c.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "net2big_v2.h"
> -#include "../common/common.h"
> -#include "../common/cpld-gpio-bus.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - /* GPIO configuration */
> - mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
> - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - static const u32 kwmpp_config[] = {
> - MPP0_SPI_SCn,
> - MPP1_SPI_MOSI,
> - MPP2_SPI_SCK,
> - MPP3_SPI_MISO,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Request power-off */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP13_GPIO, /* Rear power switch (on|auto) */
> - MPP14_GPIO, /* USB fuse alarm */
> - MPP15_GPIO, /* Rear power switch (auto|off) */
> - MPP16_GPIO, /* SATA HDD1 power */
> - MPP17_GPIO, /* SATA HDD2 power */
> - MPP20_SATA1_ACTn,
> - MPP21_SATA0_ACTn,
> - MPP24_GPIO, /* USB mode select */
> - MPP26_GPIO, /* USB device vbus */
> - MPP28_GPIO, /* USB enable host vbus */
> - MPP29_GPIO, /* CPLD GPIO bus ALE */
> - MPP34_GPIO, /* Rear Push button 0=on 1=off */
> - MPP35_GPIO, /* Inhibit switch power-off */
> - MPP36_GPIO, /* SATA HDD1 presence */
> - MPP37_GPIO, /* SATA HDD2 presence */
> - MPP40_GPIO, /* eSATA presence */
> - MPP44_GPIO, /* CPLD GPIO bus (data 0) */
> - MPP45_GPIO, /* CPLD GPIO bus (data 1) */
> - MPP46_GPIO, /* CPLD GPIO bus (data 2) */
> - MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
> - MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
> - MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
> - 0
> - };
> -
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
> -/*
> - * Start I2C fan (GMT G762 controller)
> - */
> -static void init_fan(void)
> -{
> - u8 data;
> -
> - i2c_set_bus_num(0);
> -
> - /* Enable open-loop and PWM modes */
> - data = 0x20;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_FAN_CMD1, 1, &data, 1) != 0)
> - goto err;
> - data = 0;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_SET_CNT, 1, &data, 1) != 0)
> - goto err;
> - /*
> - * RPM to PWM (set_out register) fan speed conversion array:
> - * 0 0x00
> - * 1500 0x04
> - * 2800 0x08
> - * 3400 0x0C
> - * 3700 0x10
> - * 4400 0x20
> - * 4700 0x30
> - * 4800 0x50
> - * 5200 0x80
> - * 5400 0xC0
> - * 5500 0xFF
> - *
> - * Start fan at low speed (2800 RPM):
> - */
> - data = 0x08;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_SET_OUT, 1, &data, 1) != 0)
> - goto err;
> -
> - return;
> -err:
> - printf("Error: failed to start I2C fan @%02x\n",
> - CONFIG_SYS_I2C_G762_ADDR);
> -}
> -#else
> -static void init_fan(void) {}
> -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
> -
> -#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
> -/*
> - * CPLD GPIO bus:
> - *
> - * - address register : bit [0-2] -> GPIO [47-49]
> - * - data register : bit [0-2] -> GPIO [44-46]
> - * - enable register : GPIO 29
> - */
> -static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
> -static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
> -
> -static struct cpld_gpio_bus cpld_gpio_bus = {
> - .addr = cpld_gpio_bus_addr,
> - .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
> - .data = cpld_gpio_bus_data,
> - .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
> - .enable = 29,
> -};
> -
> -/*
> - * LEDs configuration:
> - *
> - * The LEDs are controlled by a CPLD and can be configured through
> - * the CPLD GPIO bus.
> - *
> - * Address register selection:
> - *
> - * addr | register
> - * ----------------------------
> - * 0 | front LED
> - * 1 | front LED brightness
> - * 2 | SATA LED brightness
> - * 3 | SATA0 LED
> - * 4 | SATA1 LED
> - * 5 | SATA2 LED
> - * 6 | SATA3 LED
> - * 7 | SATA4 LED
> - *
> - * Data register configuration:
> - *
> - * data | LED brightness
> - * -------------------------------------------------
> - * 0 | min (off)
> - * - | -
> - * 7 | max
> - *
> - * data | front LED mode
> - * -------------------------------------------------
> - * 0 | fix off
> - * 1 | fix blue on
> - * 2 | fix red on
> - * 3 | blink blue on=1 sec and blue off=1 sec
> - * 4 | blink red on=1 sec and red off=1 sec
> - * 5 | blink blue on=2.5 sec and red on=0.5 sec
> - * 6 | blink blue on=1 sec and red on=1 sec
> - * 7 | blink blue on=0.5 sec and blue off=2.5 sec
> - *
> - * data | SATA LED mode
> - * -------------------------------------------------
> - * 0 | fix off
> - * 1 | SATA activity blink
> - * 2 | fix red on
> - * 3 | blink blue on=1 sec and blue off=1 sec
> - * 4 | blink red on=1 sec and red off=1 sec
> - * 5 | blink blue on=2.5 sec and red on=0.5 sec
> - * 6 | blink blue on=1 sec and red on=1 sec
> - * 7 | fix blue on
> - */
> -static void init_leds(void)
> -{
> - /* Enable the front blue LED */
> - cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
> -
> - /* Configure SATA LEDs to blink in relation with the SATA activity */
> - cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
> -}
> -#else
> -static void init_leds(void) {}
> -#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
> -
> -int misc_init_r(void)
> -{
> - init_fan();
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - init_leds();
> -
> - return 0;
> -}
> -#endif /* CONFIG_MISC_INIT_R */
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> - mv_phy_88e1116_init("egiga0", 8);
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO)
> -/* Return GPIO push button status */
> -static int
> -do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
> -}
> -
> -U_BOOT_CMD(button, 1, 1, do_read_push_button,
> - "Return GPIO push button status 0=off 1=on", "");
> -#endif
> diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
> deleted file mode 100644
> index 8dead89..0000000
> --- a/board/LaCie/net2big_v2/net2big_v2.h
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef NET2BIG_V2_H
> -#define NET2BIG_V2_H
> -
> -/* GPIO configuration */
> -#define NET2BIG_V2_OE_LOW 0x0600E000
> -#define NET2BIG_V2_OE_HIGH 0x00000134
> -#define NET2BIG_V2_OE_VAL_LOW 0x10030000
> -#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
> -
> -/* Buttons */
> -#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
> -
> -/* GMT G762 registers (I2C fan controller) */
> -#define G762_REG_SET_CNT 0x00
> -#define G762_REG_SET_OUT 0x03
> -#define G762_REG_FAN_CMD1 0x04
> -
> -#endif /* NET2BIG_V2_H */
> diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
> deleted file mode 100644
> index 930b822..0000000
> --- a/board/LaCie/netspace_v2/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_NETSPACE_V2
> -
> -config SYS_BOARD
> - default "netspace_v2"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "lacie_kw"
> -
> -endif
> diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
> deleted file mode 100644
> index 55fd50d..0000000
> --- a/board/LaCie/netspace_v2/MAINTAINERS
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -NETSPACE_V2 BOARD
> -M: Simon Guinot <simon.guinot@sequanux.org>
> -S: Maintained
> -F: board/LaCie/netspace_v2/
> -F: include/configs/lacie_kw.h
> -F: configs/inetspace_v2_defconfig
> -F: configs/netspace_max_v2_defconfig
> -F: configs/netspace_v2_defconfig
> -
> -NETSPACE_LITE_V2 BOARD
> -#M: -
> -S: Maintained
> -F: configs/netspace_lite_v2_defconfig
> -F: configs/netspace_mini_v2_defconfig
> diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
> deleted file mode 100644
> index 47778d8..0000000
> --- a/board/LaCie/netspace_v2/Makefile
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := netspace_v2.o ../common/common.o
> diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
> deleted file mode 100644
> index 98713ea..0000000
> --- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x00000008 # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> deleted file mode 100644
> index 6b32193..0000000
> --- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000DDDD # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
> deleted file mode 100644
> index 1515f81..0000000
> --- a/board/LaCie/netspace_v2/kwbimage.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000000C # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 11, Cs0size=1Gb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
> deleted file mode 100644
> index 17e6296..0000000
> --- a/board/LaCie/netspace_v2/netspace_v2.c
> +++ /dev/null
> @@ -1,117 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "netspace_v2.h"
> -#include "../common/common.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - /* Gpio configuration */
> - mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
> - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - static const u32 kwmpp_config[] = {
> - MPP0_SPI_SCn,
> - MPP1_SPI_MOSI,
> - MPP2_SPI_SCK,
> - MPP3_SPI_MISO,
> - MPP4_NF_IO6,
> - MPP5_NF_IO7,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Fan speed (bit 1) */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP12_GPO, /* Red led */
> - MPP14_GPIO, /* USB fuse */
> - MPP16_GPIO, /* SATA 0 power */
> - MPP17_GPIO, /* SATA 1 power */
> - MPP18_NF_IO0,
> - MPP19_NF_IO1,
> - MPP20_SATA1_ACTn,
> - MPP21_SATA0_ACTn,
> - MPP22_GPIO, /* Fan speed (bit 0) */
> - MPP23_GPIO, /* Fan power */
> - MPP24_GPIO, /* USB mode select */
> - MPP25_GPIO, /* Fan rotation fail */
> - MPP26_GPIO, /* USB vbus-in detection */
> - MPP28_GPIO, /* USB enable vbus-out */
> - MPP29_GPIO, /* Blue led (slow register) */
> - MPP30_GPIO, /* Blue led (command register) */
> - MPP31_GPIO, /* Board power off */
> - MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
> - MPP33_GPIO, /* Fan speed (bit 2) */
> - 0
> - };
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -int misc_init_r(void)
> -{
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> - mv_phy_88e1318_init("egiga0", 0);
> -#else
> - mv_phy_88e1116_init("egiga0", 8);
> -#endif
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO)
> -/* Return GPIO button status */
> -static int
> -do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
> -}
> -
> -U_BOOT_CMD(button, 1, 1, do_read_button,
> - "Return GPIO button status 0=off 1=on", "");
> -#endif
> diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h
> deleted file mode 100644
> index cdf5238..0000000
> --- a/board/LaCie/netspace_v2/netspace_v2.h
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef NETSPACE_V2_H
> -#define NETSPACE_V2_H
> -
> -/* GPIO configuration */
> -#define NETSPACE_V2_OE_LOW 0x06004000
> -#define NETSPACE_V2_OE_HIGH 0x00000031
> -#define NETSPACE_V2_OE_VAL_LOW 0x10030000
> -#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
> -
> -#define NETSPACE_V2_GPIO_BUTTON 32
> -
> -#endif /* NETSPACE_V2_H */
> diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig
> deleted file mode 100644
> index 75a2fc5..0000000
> --- a/board/LaCie/wireless_space/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_WIRELESS_SPACE
> -
> -config SYS_BOARD
> - default "wireless_space"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "wireless_space"
> -
> -endif
> diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
> deleted file mode 100644
> index c32ecb8..0000000
> --- a/board/LaCie/wireless_space/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -WIRELESS_SPACE BOARD
> -M: Albert ARIBAUD <albert.u.boot@aribaud.net>
> -S: Maintained
> -F: board/LaCie/wireless_space/
> -F: include/configs/wireless_space.h
> -F: configs/wireless_space_defconfig
> diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
> deleted file mode 100644
> index 90a84f4..0000000
> --- a/board/LaCie/wireless_space/Makefile
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := wireless_space.o ../common/common.o
> diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
> deleted file mode 100644
> index 037248b..0000000
> --- a/board/LaCie/wireless_space/kwbimage.cfg
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -#
> -# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
> -#
> -# Based on netspace_v2 kwbimage.cfg:
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM nand # Boot from NAND flash
> -NAND_PAGE_SIZE 800
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Values taken from image original LaCie U-Boot header dump!
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000c30 # DDR Configuration register
> -
> -DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -
> -DATA 0xFFD01410 0x0000CCCC # DDR Address Control
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -
> -DATA 0xFFD0141C 0x00000662 # DDR Mode
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -
> -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
> -
> -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -DATA 0xFFD20134 0x66666666
> -DATA 0xFFD20138 0x66666666
> -DATA 0xFFD10000 0x01112222
> -DATA 0xFFD1000C 0x00000000
> -DATA 0xFFD10104 0x00000000
> -DATA 0xFFD10100 0x40000000
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
> deleted file mode 100644
> index 8620e4b..0000000
> --- a/board/LaCie/wireless_space/wireless_space.c
> +++ /dev/null
> @@ -1,165 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "../common/common.h"
> -#include "netdev.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* GPIO configuration: start FAN at low speed, USB and HDD */
> -
> -#define WIRELESS_SPACE_OE_LOW 0xFF006808
> -#define WIRELESS_SPACE_OE_HIGH 0x0000F989
> -#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
> -#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
> -
> -#define WIRELESS_SPACE_REAR_BUTTON 13
> -#define WIRELESS_SPACE_FRONT_BUTTON 43
> -
> -const u32 kwmpp_config[] = {
> - MPP0_NF_IO2,
> - MPP1_NF_IO3,
> - MPP2_NF_IO4,
> - MPP3_NF_IO5,
> - MPP4_NF_IO6,
> - MPP5_NF_IO7,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Fan speed (bit 1) */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP13_GPIO, /* Red led */
> - MPP14_GPIO, /* USB fuse */
> - MPP15_SATA0_ACTn,
> - MPP16_GPIO, /* SATA 0 power */
> - MPP17_GPIO, /* SATA 1 power */
> - MPP18_NF_IO0,
> - MPP19_NF_IO1,
> - MPP20_GE1_0, /* Gigabit Ethernet 1 */
> - MPP21_GE1_1,
> - MPP22_GE1_2,
> - MPP23_GE1_3,
> - MPP24_GE1_4,
> - MPP25_GE1_5,
> - MPP26_GE1_6,
> - MPP27_GE1_7,
> - MPP28_GE1_8,
> - MPP29_GE1_9,
> - MPP30_GE1_10,
> - MPP31_GE1_11,
> - MPP32_GE1_12,
> - MPP33_GE1_13,
> - MPP34_GE1_14,
> - MPP35_GE1_15,
> - MPP36_GPIO, /* Fan speed (bit 2) */
> - MPP37_GPIO, /* Fan speed (bit 0) */
> - MPP38_GPIO, /* Fan power */
> - MPP39_GPIO, /* Fan rotation fail */
> - MPP40_GPIO, /* Ethernet switch link */
> - MPP41_GPIO, /* USB enable host vbus */
> - MPP42_GPIO, /* LED clock control */
> - MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
> - MPP44_GPIO, /* Red LED on/off */
> - MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
> - MPP46_GPIO, /* Green LED on/off */
> - MPP47_GPIO, /* LED (blue, green) SATA activity blink */
> - MPP48_GPIO, /* Blue LED on/off */
> - 0
> -};
> -
> -struct mv88e61xx_config swcfg = {
> - .name = "egiga0",
> - .vlancfg = MV88E61XX_VLANCFG_ROUTER,
> - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
> - .led_init = MV88E61XX_LED_INIT_EN,
> - .mdip = MV88E61XX_MDIP_NOCHANGE,
> - .portstate = MV88E61XX_PORTSTT_FORWARDING,
> - .cpuport = 0x20,
> - .ports_enabled = 0x3F,
> -};
> -
> -int board_early_init_f(void)
> -{
> - /* Gpio configuration */
> - mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
> - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -int misc_init_r(void)
> -{
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> - /* configure switch on egiga0 */
> - mv88e61xx_switch_initialize(&swcfg);
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
> -/* Return GPIO button status */
> -static int
> -do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - if (strcmp(argv[1], "button") == 0) {
> - if (strcmp(argv[2], "rear") == 0)
> - /* invert GPIO result for intuitive while/until use */
> - return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
> - else if (strcmp(argv[2], "front") == 0)
> - return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
> - else
> - return -1;
> - } else {
> - return -1;
> - }
> -}
> -
> -U_BOOT_CMD(ws, 3, 0, do_ws,
> - "Return GPIO button status 0=off 1=on",
> - "- ws button rear|front: test buttons' states\n"
> -);
> -#endif
> diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
> deleted file mode 100644
> index 09df520..0000000
> --- a/configs/net2big_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NET2BIG_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
> deleted file mode 100644
> index 862a9ae..0000000
> --- a/configs/netspace_lite_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
> deleted file mode 100644
> index 1829995..0000000
> --- a/configs/netspace_max_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
> deleted file mode 100644
> index 35cb154..0000000
> --- a/configs/netspace_mini_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
> deleted file mode 100644
> index a13452b..0000000
> --- a/configs/netspace_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig
> deleted file mode 100644
> index 63013f6..0000000
> --- a/configs/wireless_space_defconfig
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_WIRELESS_SPACE=y
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -ONFIG_SYS_PROMPT="ws> "
> diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
> deleted file mode 100644
> index 30810d3..0000000
> --- a/include/configs/lacie_kw.h
> +++ /dev/null
> @@ -1,214 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef _CONFIG_LACIE_KW_H
> -#define _CONFIG_LACIE_KW_H
> -
> -/*
> - * Machine number definition
> - */
> -#if defined(CONFIG_INETSPACE_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
> -#define CONFIG_IDENT_STRING " IS v2"
> -#elif defined(CONFIG_NETSPACE_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
> -#define CONFIG_IDENT_STRING " NS v2"
> -#elif defined(CONFIG_NETSPACE_LITE_V2)
> -#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
> -#define CONFIG_IDENT_STRING " NS v2 Lite"
> -#elif defined(CONFIG_NETSPACE_MINI_V2)
> -#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
> -#define CONFIG_IDENT_STRING " NS v2 Mini"
> -#elif defined(CONFIG_NETSPACE_MAX_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
> -#define CONFIG_IDENT_STRING " NS Max v2"
> -#elif defined(CONFIG_D2NET_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
> -#define CONFIG_IDENT_STRING " D2 v2"
> -#elif defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
> -#define CONFIG_IDENT_STRING " 2Big v2"
> -#else
> -#error "Unknown board"
> -#endif
> -
> -/*
> - * High Level Configuration Options (easy to change)
> - */
> -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
> -/* SoC name */
> -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> -#define CONFIG_KW88F6192
> -#else
> -#define CONFIG_KW88F6281
> -#endif
> -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
> -
> -/*
> - * Commands configuration
> - */
> -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
> -#define CONFIG_CMD_ENV
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_SF
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IDE
> -#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
> -#define CONFIG_CMD_USB
> -#endif
> -
> -/*
> - * Core clock definition
> - */
> -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
> -
> -/*
> - * SDRAM configuration
> - */
> -#define CONFIG_NR_DRAM_BANKS 1
> -
> -/*
> - * Different SDRAM configuration and size for some of the boards derived
> - * from the Network Space v2
> - */
> -#if defined(CONFIG_INETSPACE_V2)
> -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
> -#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
> -#endif
> -
> -/*
> - * mv-common.h should be defined after CMD configs since it used them
> - * to enable certain macros
> - */
> -#include "mv-common.h"
> -
> -/* Remove or override few declarations from mv-common.h */
> -#undef CONFIG_RBTREE
> -#undef CONFIG_ENV_SPI_MAX_HZ
> -#undef CONFIG_SYS_IDE_MAXBUS
> -#undef CONFIG_SYS_IDE_MAXDEVICE
> -#undef CONFIG_SYS_PROMPT
> -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
> -#define CONFIG_SYS_IDE_MAXBUS 1
> -#define CONFIG_SYS_IDE_MAXDEVICE 1
> -#if defined(CONFIG_D2NET_V2)
> -#define CONFIG_SYS_PROMPT "d2v2> "
> -#elif defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_PROMPT "2big2> "
> -#else
> -#define CONFIG_SYS_PROMPT "ns2> "
> -#endif
> -
> -/*
> - * Enable platform initialisation via misc_init_r() function
> - */
> -#define CONFIG_MISC_INIT_R
> -
> -/*
> - * Ethernet Driver configuration
> - */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
> -#define CONFIG_NETCONSOLE
> -#endif
> -
> -/*
> - * SATA Driver configuration
> - */
> -#ifdef CONFIG_MVSATA_IDE
> -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
> -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
> - defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
> -#endif
> -#endif /* CONFIG_MVSATA_IDE */
> -
> -/*
> - * Enable GPI0 support
> - */
> -#define CONFIG_KIRKWOOD_GPIO
> -
> -/*
> - * Enable I2C support
> - */
> -#ifdef CONFIG_CMD_I2C
> -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
> -#define CONFIG_CMD_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
> -#if defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_I2C_G762_ADDR 0x3e
> -#endif
> -#endif /* CONFIG_CMD_I2C */
> -
> -/*
> - * Partition support
> - */
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_EFI_PARTITION
> -
> -/*
> - * File systems support
> - */
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -
> -/*
> - * Use the HUSH parser
> - */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/*
> - * Console configuration
> - */
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -
> -/*
> - * Enable device tree support
> - */
> -#define CONFIG_OF_LIBFDT
> -
> -/*
> - * Environment variables configurations
> - */
> -#define CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
> -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
> -#define CONFIG_ENV_ADDR 0x70000
> -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
> -
> -/*
> - * Default environment variables
> - */
> -#define CONFIG_BOOTARGS "console=ttyS0,115200"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "dhcp && run netconsole; " \
> - "if run usbload || run diskload; then bootm; fi"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "stdin=serial\0" \
> - "stdout=serial\0" \
> - "stderr=serial\0" \
> - "bootfile=uImage\0" \
> - "loadaddr=0x800000\0" \
> - "autoload=no\0" \
> - "netconsole=" \
> - "set stdin $stdin,nc; " \
> - "set stdout $stdout,nc; " \
> - "set stderr $stderr,nc;\0" \
> - "diskload=ide reset && " \
> - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
> - "usbload=usb start && " \
> - "fatload usb 0:1 $loadaddr /boot/$bootfile\0"
> -
> -#endif /* _CONFIG_LACIE_KW_H */
> diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h
> deleted file mode 100644
> index 191ac1b..0000000
> --- a/include/configs/wireless_space.h
> +++ /dev/null
> @@ -1,179 +0,0 @@
> -/*
> - * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
> - *
> - * Based on the netspace_v2 code which is
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef _CONFIG_WIRELESS_SPACE_H
> -#define _CONFIG_WIRELESS_SPACE_H
> -
> -/*
> - * Machine number definition
> - */
> -#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE
> -#define CONFIG_IDENT_STRING " Wireless Space"
> -
> -/*
> - * High Level Configuration Options (easy to change)
> - */
> -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
> -/* SoC name */
> -#define CONFIG_KW88F6281
> -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
> -
> -/*
> - * Commands configuration
> - */
> -#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
> -#define CONFIG_CMD_ENV
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_NAND
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IDE
> -#define CONFIG_CMD_USB
> -
> -/*
> - * Core clock definition
> - */
> -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
> -
> -/*
> - * SDRAM configuration
> - */
> -#define CONFIG_NR_DRAM_BANKS 1
> -
> -/*
> - * Different SDRAM configuration and size for some of the boards derived
> - * from the Network Space v2
> - */
> -
> -/*
> - * mv-common.h should be defined after CMD configs since it used them
> - * to enable certain macros
> - */
> -#include "mv-common.h"
> -
> -/* Remove or override few declarations from mv-common.h */
> -#undef CONFIG_RBTREE
> -#undef CONFIG_SYS_IDE_MAXBUS
> -#undef CONFIG_SYS_IDE_MAXDEVICE
> -#define CONFIG_SYS_IDE_MAXBUS 1
> -#define CONFIG_SYS_IDE_MAXDEVICE 1
> -
> -/*
> - * Ethernet Driver configuration
> - */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
> -#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */
> -#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
> -#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */
> -#define CONFIG_MII
> -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> -#define CONFIG_NETCONSOLE
> -#define CONFIG_MV88E61XX_SWITCH
> -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
> -#define CONFIG_MV88E61XX_CMD
> -#define CONFIG_CMD_TFTPPUT
> -#endif /* CONFIG_CMD_NET */
> -
> -/*
> - * SATA Driver configuration
> - */
> -#ifdef CONFIG_MVSATA_IDE
> -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
> -#endif /* CONFIG_MVSATA_IDE */
> -
> -/*
> - * Enable GPI0 support
> - */
> -#define CONFIG_KIRKWOOD_GPIO
> -
> -/*
> - * Enable I2C support
> - */
> -#ifdef CONFIG_CMD_I2C
> -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
> -#define CONFIG_CMD_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
> -#endif /* CONFIG_CMD_I2C */
> -
> -/*
> - * Partition support
> - */
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_EFI_PARTITION
> -
> -/*
> - * File systems support
> - */
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -
> -/*
> - * Use the HUSH parser
> - */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/*
> - * Console configuration
> - */
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -
> -/*
> - * Enable device tree support
> - */
> -#define CONFIG_OF_LIBFDT
> -
> -/*
> - * Environment variables configurations
> - */
> -
> -#define CONFIG_ENV_IS_IN_NAND
> -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
> -#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
> -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
> -
> -/*
> - * Board-specific command to make using buttons etc easier
> - */
> -
> -#define CONFIG_WIRELESS_SPACE_CMD
> -
> -/*
> - * Default environment variables
> - */
> -#define CONFIG_PREBOOT
> -
> -#define CONFIG_BOOTARGS "console=ttyS0,115200"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "if run usbload || run diskload; then bootm; fi"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "stdin=serial\0" \
> - "stdout=serial\0" \
> - "stderr=serial\0" \
> - "bootfile=uImage\0" \
> - "loadaddr=0x800000\0" \
> - "autoload=no\0" \
> - "netconsole=" \
> - "set stdin $stdin,nc; " \
> - "set stdout $stdout,nc; " \
> - "set stderr $stderr,nc;\0" \
> - "diskload=ide reset && " \
> - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
> - "usbload=usb start && " \
> - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
> - "preboot=" \
> - "dhcp && run netconsole\0"
> -
> -#endif /* _CONFIG_WIRELESS_SPACE_H */
> --
> 2.5.0.457.gab17608
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* [U-Boot] [PATCH 09/45] arm: Remove edb9315a board
2015-08-31 7:38 ` sergey kostanbaev
@ 2015-08-31 13:13 ` Simon Glass
0 siblings, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 13:13 UTC (permalink / raw)
To: u-boot
Hi,
On 31 August 2015 at 01:38, sergey kostanbaev
<sergey.kostanbaev@gmail.com> wrote:
> Hi Simon,
>
> It seems I missed moving to generic board CONFIG_SYS_GENERIC_BOARD. So could
> you point what is better to read to adopt it?
Yes - please see doc/README.generic-board which has instructions. It
should be very simple.
Regards,
Simon
>
> Thanks
>
> On Mon, Aug 31, 2015 at 4:19 AM, Simon Glass <sjg@chromium.org> wrote:
>>
>> This board has not been converted to generic board by the deadline.
>> Remove it.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> arch/arm/Kconfig | 5 -
>> board/cirrus/edb93xx/Kconfig | 15 --
>> board/cirrus/edb93xx/MAINTAINERS | 6 -
>> board/cirrus/edb93xx/Makefile | 11 --
>> board/cirrus/edb93xx/edb93xx.c | 382
>> ---------------------------------------
>> board/cirrus/edb93xx/u-boot.lds | 116 ------------
>> configs/edb9315a_defconfig | 6 -
>> include/configs/edb93xx.h | 284 -----------------------------
>> 8 files changed, 825 deletions(-)
>> delete mode 100644 board/cirrus/edb93xx/Kconfig
>> delete mode 100644 board/cirrus/edb93xx/MAINTAINERS
>> delete mode 100644 board/cirrus/edb93xx/Makefile
>> delete mode 100644 board/cirrus/edb93xx/edb93xx.c
>> delete mode 100644 board/cirrus/edb93xx/u-boot.lds
>> delete mode 100644 configs/edb9315a_defconfig
>> delete mode 100644 include/configs/edb93xx.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 5429dc8..fa52901 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -69,10 +69,6 @@ choice
>> config ARCH_AT91
>> bool "Atmel AT91"
>>
>> -config TARGET_EDB93XX
>> - bool "Support edb93xx"
>> - select CPU_ARM920T
>> -
>> config TARGET_SCB9328
>> bool "Support scb9328"
>> select CPU_ARM920T
>> @@ -889,7 +885,6 @@ source "board/boundary/nitrogen6x/Kconfig"
>> source "board/broadcom/bcm28155_ap/Kconfig"
>> source "board/broadcom/bcmcygnus/Kconfig"
>> source "board/broadcom/bcmnsp/Kconfig"
>> -source "board/cirrus/edb93xx/Kconfig"
>> source "board/compulab/cm_t335/Kconfig"
>> source "board/compulab/cm_t43/Kconfig"
>> source "board/compulab/cm_fx6/Kconfig"
>> diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
>> deleted file mode 100644
>> index c5f4897..0000000
>> --- a/board/cirrus/edb93xx/Kconfig
>> +++ /dev/null
>> @@ -1,15 +0,0 @@
>> -if TARGET_EDB93XX
>> -
>> -config SYS_BOARD
>> - default "edb93xx"
>> -
>> -config SYS_VENDOR
>> - default "cirrus"
>> -
>> -config SYS_SOC
>> - default "ep93xx"
>> -
>> -config SYS_CONFIG_NAME
>> - default "edb93xx"
>> -
>> -endif
>> diff --git a/board/cirrus/edb93xx/MAINTAINERS
>> b/board/cirrus/edb93xx/MAINTAINERS
>> deleted file mode 100644
>> index 3bb2843..0000000
>> --- a/board/cirrus/edb93xx/MAINTAINERS
>> +++ /dev/null
>> @@ -1,6 +0,0 @@
>> -EDB93XX BOARD
>> -M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
>> -S: Maintained
>> -F: board/cirrus/edb93xx/
>> -F: include/configs/edb93xx.h
>> -F: configs/edb9315a_defconfig
>> diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
>> deleted file mode 100644
>> index d03c498..0000000
>> --- a/board/cirrus/edb93xx/Makefile
>> +++ /dev/null
>> @@ -1,11 +0,0 @@
>> -#
>> -# (C) Copyright 2013
>> -# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
>> -#
>> -# (C) Copyright 2003-2006
>> -# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
>> -#
>> -# * SPDX-License-Identifier: GPL-2.0+
>> -#
>> -
>> -obj-y := edb93xx.o
>> diff --git a/board/cirrus/edb93xx/edb93xx.c
>> b/board/cirrus/edb93xx/edb93xx.c
>> deleted file mode 100644
>> index 8963d3a..0000000
>> --- a/board/cirrus/edb93xx/edb93xx.c
>> +++ /dev/null
>> @@ -1,382 +0,0 @@
>> -/*
>> - * Board initialization for EP93xx
>> - *
>> - * Copyright (C) 2013
>> - * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
>> - *
>> - * Copyright (C) 2009
>> - * Matthias Kaehlcke <matthias <at> kaehlcke.net>
>> - *
>> - * (C) Copyright 2002 2003
>> - * Network Audio Technologies, Inc. <www.netaudiotech.com>
>> - * Adam Bezanson <bezanson <at> netaudiotech.com>
>> - *
>> - * SPDX-License-Identifier: GPL-2.0+
>> - */
>> -
>> -#include <config.h>
>> -#include <common.h>
>> -#include <netdev.h>
>> -#include <asm/io.h>
>> -#include <asm/arch/ep93xx.h>
>> -
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> -/*
>> - * usb_div: 4, nbyp2: 1, pll2_en: 1
>> - * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
>> - * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
>> - */
>> -#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
>> - 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
>> - 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
>> - 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
>> - SYSCON_CLKSET2_PLL2_EN | \
>> - SYSCON_CLKSET2_NBYP2 | \
>> - 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
>> -
>> -#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT
>> | \
>> - SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
>> - 1 << SMC_BCR_MW_SHIFT)
>> -
>> -/* delay execution before timers are initialized */
>> -static inline void early_udelay(uint32_t usecs)
>> -{
>> - /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz)
>> */
>> - register uint32_t loops = (usecs * 1000) / 20;
>> -
>> - __asm__ volatile ("1:\n"
>> - "subs %0, %1, #1\n"
>> - "bne 1b" : "=r" (loops) : "0" (loops));
>> -}
>> -
>> -#ifndef CONFIG_EP93XX_NO_FLASH_CFG
>> -static void flash_cfg(void)
>> -{
>> - struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
>> -
>> - writel(SMC_BCR6_VALUE, &smc->bcr6);
>> -}
>> -#else
>> -#define flash_cfg()
>> -#endif
>> -
>> -int board_init(void)
>> -{
>> - /*
>> - * Setup PLL2, PPL1 has been set during lowlevel init
>> - */
>> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
>> - writel(CLKSET2_VAL, &syscon->clkset2);
>> -
>> - /*
>> - * the user's guide recommends to wait at least 1 ms for PLL2 to
>> - * stabilize
>> - */
>> - early_udelay(1000);
>> -
>> - /* Go to Async mode */
>> - __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
>> - __asm__ volatile ("orr r0, r0, #0xc0000000");
>> - __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
>> -
>> - icache_enable();
>> -
>> -#ifdef USE_920T_MMU
>> - dcache_enable();
>> -#endif
>> -
>> - /* Machine number, as defined in linux/arch/arm/tools/mach-types
>> */
>> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
>> -
>> - /* adress of boot parameters */
>> - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
>> -
>> - /* We have a console */
>> - gd->have_console = 1;
>> -
>> - enable_interrupts();
>> -
>> - flash_cfg();
>> -
>> - green_led_on();
>> - red_led_off();
>> -
>> - return 0;
>> -}
>> -
>> -int board_early_init_f(void)
>> -{
>> - /*
>> - * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
>> - * 14.7456/2 MHz
>> - */
>> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
>> - writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
>> - return 0;
>> -}
>> -
>> -int board_eth_init(bd_t *bd)
>> -{
>> - return ep93xx_eth_initialize(0, MAC_BASE);
>> -}
>> -
>> -static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned
>> dram_bank_cnt,
>> - unsigned
>> dram_bank_base[CONFIG_NR_DRAM_BANKS])
>> -{
>> - if (dram_bank_cnt == 1) {
>> - dram_bank_base[0] = PHYS_SDRAM_1;
>> - } else {
>> - /* Table lookup for holes in address space. Maximum memory
>> - * for the single SDCS may be up to 256Mb. We start
>> scanning
>> - * banks from 1Mb, so it could be up to 128 banks
>> theoretically.
>> - * We need at maximum 7 bits for the loockup, 8 slots is
>> - * enough for the worst case.
>> - */
>> - unsigned tbl[8];
>> - unsigned i = dram_bank_cnt / 2;
>> - unsigned j = 0x00100000; /* 1 Mb */
>> - unsigned *ptbl = tbl;
>> - do {
>> - while (!(dram_addr_mask & j)) {
>> - j <<= 1;
>> - }
>> - *ptbl++ = j;
>> - j <<= 1;
>> - i >>= 1;
>> - } while (i != 0);
>> -
>> - for (i = dram_bank_cnt, j = 0;
>> - (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
>> - unsigned addr = PHYS_SDRAM_1;
>> - unsigned k;
>> - unsigned bit;
>> -
>> - for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
>> - if (bit & j)
>> - addr |= tbl[k];
>> - }
>> -
>> - dram_bank_base[j] = addr;
>> - }
>> - }
>> -}
>> -
>> -/* called in board_init_f (before relocation) */
>> -static unsigned dram_init_banksize_int(int print)
>> -{
>> - /*
>> - * Collect information of banks that has been filled during
>> lowlevel
>> - * initialization
>> - */
>> - unsigned i;
>> - unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
>> - unsigned dram_total = 0;
>> - unsigned dram_bank_size = *(unsigned *)
>> - (PHYS_SDRAM_1 |
>> UBOOT_MEMORYCNF_BANK_SIZE);
>> - unsigned dram_addr_mask = *(unsigned *)
>> - (PHYS_SDRAM_1 |
>> UBOOT_MEMORYCNF_BANK_MASK);
>> - unsigned dram_bank_cnt = *(unsigned *)
>> - (PHYS_SDRAM_1 |
>> UBOOT_MEMORYCNF_BANK_COUNT);
>> -
>> - dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt,
>> dram_bank_base);
>> -
>> - for (i = 0; i < dram_bank_cnt; i++) {
>> - gd->bd->bi_dram[i].start = dram_bank_base[i];
>> - gd->bd->bi_dram[i].size = dram_bank_size;
>> - dram_total += dram_bank_size;
>> - }
>> - for (; i < CONFIG_NR_DRAM_BANKS; i++) {
>> - gd->bd->bi_dram[i].start = 0;
>> - gd->bd->bi_dram[i].size = 0;
>> - }
>> -
>> - if (print) {
>> - printf("DRAM mask: %08x\n", dram_addr_mask);
>> - printf("DRAM total %u banks:\n", dram_bank_cnt);
>> - printf("bank base-address size\n");
>> -
>> - if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
>> - printf("WARNING! UBoot was configured for %u
>> banks,\n"
>> - "but %u has been found. "
>> - "Supressing extra memory banks\n",
>> - CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
>> - dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
>> - }
>> -
>> - for (i = 0; i < dram_bank_cnt; i++) {
>> - printf(" %u %08x %08x\n",
>> - i, dram_bank_base[i], dram_bank_size);
>> - }
>> - printf(" ------------------------------------------\n"
>> - "Total %9d\n\n",
>> - dram_total);
>> - }
>> -
>> - return dram_total;
>> -}
>> -
>> -void dram_init_banksize(void)
>> -{
>> - dram_init_banksize_int(0);
>> -}
>> -
>> -/* called in board_init_f (before relocation) */
>> -int dram_init(void)
>> -{
>> - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
>> - unsigned sec_id = readl(SECURITY_EXTENSIONID);
>> - unsigned chip_id = readl(&syscon->chipid);
>> -
>> - printf("CPU: Cirrus Logic ");
>> - switch (sec_id & 0x000001FE) {
>> - case 0x00000008:
>> - printf("EP9301");
>> - break;
>> - case 0x00000004:
>> - printf("EP9307");
>> - break;
>> - case 0x00000002:
>> - printf("EP931x");
>> - break;
>> - case 0x00000000:
>> - printf("EP9315");
>> - break;
>> - default:
>> - printf("<unknown>");
>> - break;
>> - }
>> -
>> - printf(" - Rev. ");
>> - switch (chip_id & 0xF0000000) {
>> - case 0x00000000:
>> - printf("A");
>> - break;
>> - case 0x10000000:
>> - printf("B");
>> - break;
>> - case 0x20000000:
>> - printf("C");
>> - break;
>> - case 0x30000000:
>> - printf("D0");
>> - break;
>> - case 0x40000000:
>> - printf("D1");
>> - break;
>> - case 0x50000000:
>> - printf("E0");
>> - break;
>> - case 0x60000000:
>> - printf("E1");
>> - break;
>> - case 0x70000000:
>> - printf("E2");
>> - break;
>> - default:
>> - printf("?");
>> - break;
>> - }
>> - printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
>> -
>> - gd->ram_size = dram_init_banksize_int(1);
>> - return 0;
>> -}
>> -
>> -
>> -#ifdef CONFIG_EP93XX_SPI
>> -#include <spi.h>
>> -
>> -/*
>> - * EGIO0-EGIPO7 -> port A
>> - * EGIO8-EGIP15 -> port B
>> - */
>> -
>> -static void ep93xx_set_epgio(unsigned num)
>> -{
>> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
>> - if (num < 8)
>> - writel(readl(®s->padr) | (1<<num), ®s->padr);
>> - else
>> - writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
>> -}
>> -
>> -static void ep93xx_clear_epgio(unsigned num)
>> -{
>> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
>> - if (num < 8)
>> - writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
>> - else
>> - writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
>> -}
>> -
>> -static void ep93xx_dir_epgio_out(unsigned num)
>> -{
>> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
>> - if (num < 8)
>> - writel(readl(®s->paddr) | (1<<num), ®s->paddr);
>> - else
>> - writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
>> -}
>> -
>> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
>> -{
>> - if (bus == 0 && cs < 16)
>> - return 1;
>> -
>> - return 0;
>> -}
>> -
>> -void spi_cs_activate(struct spi_slave *slave)
>> -{
>> - ep93xx_clear_epgio(slave->cs);
>> -}
>> -
>> -void spi_cs_deactivate(struct spi_slave *slave)
>> -{
>> - ep93xx_set_epgio(slave->cs);
>> -}
>> -
>> -#ifdef CONFIG_MMC_SPI
>> -#include <mmc.h>
>> -
>> -#ifndef CONFIG_MMC_SPI_CS_EPGIO
>> -# define CONFIG_MMC_SPI_CS_EPGIO 4
>> -#endif
>> -
>> -#ifndef CONFIG_MMC_SPI_SPEED
>> -# define CONFIG_MMC_SPI_SPEED 25000000
>> -#endif
>> -
>> -#ifndef CONFIG_MMC_SPI_MODE
>> -# define CONFIG_MMC_SPI_MODE SPI_MODE_0
>> -#endif
>> -
>> -int board_mmc_init(bd_t *bis)
>> -{
>> - struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
>> -
>> - ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
>> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
>> -
>> -#ifdef CONFIG_MMC_SPI_POWER_EGPIO
>> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
>> - ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
>> -#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
>> - ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
>> - ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
>> -#endif
>> - struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
>> - CONFIG_MMC_SPI_SPEED,
>> CONFIG_MMC_SPI_MODE);
>> -
>> - if (!mmc) {
>> - printf("Failed to create MMC Device\n");
>> - return 1;
>> - }
>> - mmc_init(mmc);
>> - return 0;
>> -}
>> -
>> -
>> -#endif /* CONFIG_MMC_SPI */
>> -#endif /* CONFIG_EP93XX_SPI */
>> diff --git a/board/cirrus/edb93xx/u-boot.lds
>> b/board/cirrus/edb93xx/u-boot.lds
>> deleted file mode 100644
>> index 4aa7891..0000000
>> --- a/board/cirrus/edb93xx/u-boot.lds
>> +++ /dev/null
>> @@ -1,116 +0,0 @@
>> -/*
>> - *
>> - * Copyright (C) 2013
>> - * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
>> - *
>> - * Copyright (c) 2004-2008 Texas Instruments
>> - *
>> - * (C) Copyright 2002
>> - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
>> - *
>> - * SPDX-License-Identifier: GPL-2.0+
>> - */
>> -
>> -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
>> -OUTPUT_ARCH(arm)
>> -ENTRY(_start)
>> -SECTIONS
>> -{
>> - . = 0x00000000;
>> -
>> - . = ALIGN(4);
>> - .text : {
>> - *(.__image_copy_start)
>> - *(.vectors)
>> - arch/arm/cpu/arm920t/start.o (.text*)
>> - . = 0x1000;
>> -
>> - LONG(0x53555243)
>> - *(.text*)
>> - }
>> -
>> - . = ALIGN(4);
>> - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
>> -
>> - . = ALIGN(4);
>> - .data : {
>> - *(.data*)
>> - }
>> -
>> - . = ALIGN(4);
>> -
>> - . = .;
>> -
>> - . = ALIGN(4);
>> - .u_boot_list : {
>> - KEEP(*(SORT(.u_boot_list*)));
>> - }
>> -
>> - . = ALIGN(4);
>> -
>> - .image_copy_end :
>> - {
>> - *(.__image_copy_end)
>> - }
>> -
>> - .rel_dyn_start :
>> - {
>> - *(.__rel_dyn_start)
>> - }
>> -
>> - .rel.dyn : {
>> - *(.rel*)
>> - }
>> -
>> - .rel_dyn_end :
>> - {
>> - *(.__rel_dyn_end)
>> - }
>> -
>> - .end :
>> - {
>> - *(.__end)
>> - }
>> -
>> - _image_binary_end = .;
>> -
>> - /*
>> - * Deprecated: this MMU section is used by pxa at present but
>> - * should not be used by new boards/CPUs.
>> - */
>> - . = ALIGN(4096);
>> - .mmutable : {
>> - *(.mmutable)
>> - }
>> -
>> -/*
>> - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
>> - * __bss_base and __bss_limit are for linker only (overlay ordering)
>> - */
>> -
>> - .bss_start __rel_dyn_start (OVERLAY) : {
>> - KEEP(*(.__bss_start));
>> - __bss_base = .;
>> - }
>> -
>> - .bss __bss_base (OVERLAY) : {
>> - *(.bss*)
>> - . = ALIGN(4);
>> - __bss_limit = .;
>> - }
>> -
>> - .bss_end __bss_limit (OVERLAY) : {
>> - KEEP(*(.__bss_end));
>> - }
>> -
>> - .dynsym _image_binary_end : { *(.dynsym) }
>> - .dynbss : { *(.dynbss) }
>> - .dynstr : { *(.dynstr*) }
>> - .dynamic : { *(.dynamic*) }
>> - .plt : { *(.plt*) }
>> - .interp : { *(.interp*) }
>> - .gnu.hash : { *(.gnu.hash) }
>> - .gnu : { *(.gnu*) }
>> - .ARM.exidx : { *(.ARM.exidx*) }
>> - .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
>> -}
>> diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
>> deleted file mode 100644
>> index 452bf0d..0000000
>> --- a/configs/edb9315a_defconfig
>> +++ /dev/null
>> @@ -1,6 +0,0 @@
>> -CONFIG_ARM=y
>> -CONFIG_TARGET_EDB93XX=y
>> -CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
>> -# CONFIG_CMD_XIMG is not set
>> -# CONFIG_CMD_FPGA is not set
>> -# CONFIG_CMD_SETEXPR is not set
>> diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
>> deleted file mode 100644
>> index efe2a9d..0000000
>> --- a/include/configs/edb93xx.h
>> +++ /dev/null
>> @@ -1,284 +0,0 @@
>> -/*
>> - * U-boot - Configuration file for Cirrus Logic EDB93xx boards
>> - */
>> -
>> -#ifndef __CONFIG_H
>> -#define __CONFIG_H
>> -
>> -#ifdef CONFIG_MK_edb9301
>> -#define CONFIG_EDB9301
>> -#elif defined(CONFIG_MK_edb9302)
>> -#define CONFIG_EDB9302
>> -#elif defined(CONFIG_MK_edb9302a)
>> -#define CONFIG_EDB9302A
>> -#elif defined(CONFIG_MK_edb9307)
>> -#define CONFIG_EDB9307
>> -#elif defined(CONFIG_MK_edb9307a)
>> -#define CONFIG_EDB9307A
>> -#elif defined(CONFIG_MK_edb9312)
>> -#define CONFIG_EDB9312
>> -#elif defined(CONFIG_MK_edb9315)
>> -#define CONFIG_EDB9315
>> -#elif defined(CONFIG_MK_edb9315a)
>> -#define CONFIG_EDB9315A
>> -#else
>> -#error "no board defined"
>> -#endif
>> -
>> -/* Initial environment and monitor configuration options. */
>> -#define CONFIG_BOOTDELAY 2
>> -#define CONFIG_CMDLINE_TAG 1
>> -#define CONFIG_INITRD_TAG 1
>> -#define CONFIG_SETUP_MEMORY_TAGS 1
>> -#define CONFIG_BOOTARGS "root=/dev/nfs
>> console=ttyAM0,115200 ip=dhcp"
>> -#define CONFIG_BOOTFILE "edb93xx.img"
>> -
>> -#define CONFIG_SYS_HUSH_PARSER 1
>> -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
>> -
>> -
>> -#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
>> -
>> -#undef CONFIG_SYS_PROMPT
>> -#ifdef CONFIG_EDB9301
>> -#define CONFIG_EP9301
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
>> -#define CONFIG_SYS_PROMPT "EDB9301> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00020000
>> -#elif defined(CONFIG_EDB9302)
>> -#define CONFIG_EP9302
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
>> -#define CONFIG_SYS_PROMPT "EDB9302> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00020000
>> -#elif defined(CONFIG_EDB9302A)
>> -#define CONFIG_EP9302
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
>> -#define CONFIG_SYS_PROMPT "EDB9302A> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00020000
>> -#elif defined(CONFIG_EDB9307)
>> -#define CONFIG_EP9307
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
>> -#define CONFIG_SYS_PROMPT "EDB9307> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00040000
>> -#elif defined(CONFIG_EDB9307A)
>> -#define CONFIG_EP9307
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
>> -#define CONFIG_SYS_PROMPT "EDB9307A> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00020000
>> -#elif defined(CONFIG_EDB9312)
>> -#define CONFIG_EP9312
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
>> -#define CONFIG_SYS_PROMPT "EDB9312> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00040000
>> -#elif defined(CONFIG_EDB9315)
>> -#define CONFIG_EP9315
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
>> -#define CONFIG_SYS_PROMPT "EDB9315> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00040000
>> -#elif defined(CONFIG_EDB9315A)
>> -#define CONFIG_EP9315
>> -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
>> -#define CONFIG_SYS_PROMPT "EDB9315A> "
>> -#define CONFIG_ENV_SECT_SIZE 0x00020000
>> -#else
>> -#error "no board defined"
>> -#endif
>> -
>> -/* High-level configuration options */
>> -#define CONFIG_EP93XX 1 /* This is a Cirrus Logic
>> 93xx SoC */
>> -
>> -#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456
>> clock */
>> -#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
>> -
>> -/* Monitor configuration */
>> -#undef CONFIG_CMD_DATE
>> -#define CONFIG_CMD_DHCP
>> -#define CONFIG_CMD_JFFS2
>> -
>> -#define CONFIG_SYS_LONGHELP /* Enable "long" help in
>> mon */
>> -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size
>> */
>> -/* Print buffer size */
>> -#define CONFIG_SYS_PBSIZE
>> (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
>> -/* Boot argument buffer size */
>> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>> -#define CONFIG_SYS_MAXARGS 16 /* Max number of command
>> args */
>> -
>> -/* Serial port hardware configuration */
>> -#define CONFIG_PL010_SERIAL
>> -#define CONFIG_CONS_INDEX 0
>> -#define CONFIG_BAUDRATE 115200
>> -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
>> - 115200, 230400}
>> -#define CONFIG_SYS_SERIAL0 0x808C0000
>> -#define CONFIG_SYS_SERIAL1 0x808D0000
>> -/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
>> - (void *)CONFIG_SYS_SERIAL1} */
>> -
>> -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
>> -
>> -/* Status LED */
>> -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
>> -#define CONFIG_BOARD_SPECIFIC_LED 1
>> -#define STATUS_LED_GREEN 0
>> -#define STATUS_LED_RED 1
>> -/* Green */
>> -#define STATUS_LED_BIT STATUS_LED_GREEN
>> -#define STATUS_LED_STATE STATUS_LED_ON
>> -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
>> -/* Red */
>> -#define STATUS_LED_BIT1 STATUS_LED_RED
>> -#define STATUS_LED_STATE1 STATUS_LED_OFF
>> -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
>> -/* Optional value */
>> -#define STATUS_LED_BOOT STATUS_LED_BIT
>> -
>> -/* Network hardware configuration */
>> -#define CONFIG_DRIVER_EP93XX_MAC
>> -#define CONFIG_MII_SUPPRESS_PREAMBLE
>> -#define CONFIG_MII
>> -#define CONFIG_PHY_ADDR 1
>> -#undef CONFIG_NETCONSOLE
>> -
>> -/* SDRAM configuration */
>> -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
>> - defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
>> - defined(CONFIG_EDB9315)
>> -/*
>> - * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung
>> K4S561632E-TC75
>> - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We
>> set
>> - * the SROMLL bit on the processor, resulting in this non-contiguous
>> memory map.
>> - *
>> - * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
>> - * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total
>> of
>> - * 64 MB of SDRAM.
>> - */
>> -
>> -#define CONFIG_EDB93XX_SDCS3
>> -
>> -#elif defined(CONFIG_EDB9302A) || \
>> - defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
>> -/*
>> - * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
>> - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We
>> set
>> - * the SROMLL bit on the processor, resulting in this non-contiguous
>> memory map.
>> - *
>> - * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x
>> Samsung
>> - * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of
>> SDRAM.
>> - */
>> -#define CONFIG_EDB93XX_SDCS0
>> -
>> -#else
>> -#error "no SDCS configuration for this board"
>> -#endif
>> -
>> -
>> -#if defined(CONFIG_EDB93XX_SDCS3)
>> -#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
>> -#define PHYS_SDRAM_1 0x00000000
>> -#elif defined(CONFIG_EDB93XX_SDCS0)
>> -#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
>> -#define PHYS_SDRAM_1 0xc0000000
>> -#endif
>> -
>> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
>> -#define CONFIG_NR_DRAM_BANKS 8
>> -
>> -#define CONFIG_SYS_INIT_SP_ADDR \
>> - (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
>> -
>> -
>> -/* Must match kernel config */
>> -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
>> -
>> -/* Run-time memory allocatons */
>> -#define CONFIG_SYS_GBL_DATA_SIZE 128
>> -#define CONFIG_STACKSIZE (128 * 1024)
>> -
>> -#if defined(CONFIG_USE_IRQ)
>> -#define CONFIG_STACKSIZE_IRQ (4 * 1024)
>> -#define CONFIG_STACKSIZE_FIQ (4 * 1024)
>> -#endif
>> -
>> -#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
>> -
>> -/*
>> -----------------------------------------------------------------------------
>> - * FLASH and environment organization
>> - *
>> - * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash
>> memory at
>> - * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a
>> 16-bit
>> - * data bus, for a total of 16 MB of CFI-compatible flash.
>> - *
>> - * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
>> - * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a
>> 32-bit
>> - * data bus, for a total of 32 MB of CFI-compatible flash.
>> - *
>> - *
>> - * EDB9301/02(a)7a/15a EDB9307/12/15
>> - * 0x60000000 - 0x0003FFFF u-boot u-boot
>> - * 0x60040000 - 0x0005FFFF environment #1 environment #1
>> - * 0x60060000 - 0x0007FFFF environment #2 environment #1
>> (continued)
>> - * 0x60080000 - 0x0009FFFF unused environment #2
>> - * 0x600A0000 - 0x000BFFFF unused environment #2
>> (continued)
>> - * 0x600C0000 - 0x00FFFFFF unused unused
>> - * 0x61000000 - 0x01FFFFFF not present unused
>> - */
>> -#define CONFIG_SYS_FLASH_CFI
>> -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
>> -
>> -
>> -#define CONFIG_SYS_FLASH_PROTECTION
>> -#define CONFIG_FLASH_CFI_DRIVER
>> -#define CONFIG_SYS_MAX_FLASH_BANKS 1
>> -#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
>> -
>> -#define CONFIG_SYS_TEXT_BASE 0x60000000
>> -#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
>> -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
>> -
>> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
>> -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
>> -
>> -#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
>> -#define CONFIG_ENV_IS_IN_FLASH
>> -
>> -#define CONFIG_ENV_ADDR 0x60040000
>> -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR +
>> CONFIG_ENV_SECT_SIZE)
>> -
>> -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
>> -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
>> -
>> -/* Define to enable MMC on SPI support */
>> -/* #define CONFIG_EP93XX_SPI_MMC */
>> -
>> -#ifdef CONFIG_EP93XX_SPI_MMC
>> -#define CONFIG_EP93XX_SPI
>> -#define CONFIG_MMC
>> -#define CONFIG_GENERIC_MMC
>> -#define CONFIG_MMC_SPI
>> -#define CONFIG_CMD_MMC
>> -#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
>> -#endif
>> -
>> -#define CONFIG_USB_STORAGE
>> -#define CONFIG_USB_OHCI_NEW
>> -#define CONFIG_USB_OHCI_EP93XX
>> -#define CONFIG_SYS_USB_OHCI_CPU_INIT
>> -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
>> -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
>> -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
>> -
>> -#define CONFIG_CMD_EXT2
>> -#define CONFIG_CMD_EXT4
>> -#define CONFIG_CMD_FAT
>> -#define CONFIG_CMD_USB
>> -
>> -#define CONFIG_BOARD_EARLY_INIT_F
>> -#define CONFIG_CMD_BOOTZ
>> -
>> -/* Define to disable flash configuration*/
>> -/* #define CONFIG_EP93XX_NO_FLASH_CFG */
>> -
>> -/* Define this for indusrial rated chips */
>> -/* #define CONFIG_EDB93XX_INDUSTRIAL */
>> -
>> -#endif /* !defined (__CONFIG_H) */
>> --
>> 2.5.0.457.gab17608
>>
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-08-31 7:51 ` Simon Guinot
@ 2015-08-31 13:16 ` Simon Glass
2015-08-31 14:07 ` Albert ARIBAUD
` (2 more replies)
0 siblings, 3 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 13:16 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 31 August 2015 at 01:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
>> These boards have not been converted to generic board by the deadline.
>> Remove all except edmini_v2 (which has been converted).
>
> Hi Simon,
>
> Great... Is it still time to convert this boards to "generic board"
> support ?
Yes if you are quick - please see doc/README.generic-board which has
instructions. It should be very simple.
>
> You know, a direct email (I mean with my email address in the To or Cc
> fields) to make me aware of this project would have been both fair and
> very appreciated.
OK well I'm sorry you haven't seen anything up until now. I wonder if
we should cc all the maintainers when we have an announcement that
affects their boards. There are a lot of maintainers though!
It is probably worth checking in every now and then to see what is going on.
[snip]
Regards,
Simon
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board
2015-08-31 5:32 ` [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board Daniel Gorsulowski
@ 2015-08-31 13:22 ` Simon Glass
2015-09-11 7:38 ` [U-Boot] [U-Boot, " Andreas Bießmann
1 sibling, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 13:22 UTC (permalink / raw)
To: u-boot
On 30 August 2015 at 23:32, Daniel Gorsulowski
<daniel.gorsulowski@esd.eu> wrote:
> Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
> ---
> include/configs/meesc.h | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board
2015-08-31 1:19 ` [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board Simon Glass
@ 2015-08-31 13:47 ` Adam Ford
2015-08-31 13:54 ` Simon Glass
2015-08-31 13:59 ` Tom Rini
0 siblings, 2 replies; 119+ messages in thread
From: Adam Ford @ 2015-08-31 13:47 UTC (permalink / raw)
To: u-boot
If I add the one-line patch to add generic support, can we keep this in
there for the short term? I am working on more patches to both the Kernel
and U-boot but I haven't pushed them for approvals yet.
adam
On Sun, Aug 30, 2015 at 8:19 PM, Simon Glass <sjg@chromium.org> wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/cpu/armv7/omap3/Kconfig | 4 -
> board/logicpd/omap3som/Kconfig | 12 --
> board/logicpd/omap3som/MAINTAINERS | 6 -
> board/logicpd/omap3som/Makefile | 8 -
> board/logicpd/omap3som/omap3logic.c | 242 ---------------------------
> board/logicpd/omap3som/omap3logic.h | 31 ----
> configs/omap3_logic_defconfig | 8 -
> include/configs/omap3_logic.h | 322
> ------------------------------------
> 8 files changed, 633 deletions(-)
> delete mode 100644 board/logicpd/omap3som/Kconfig
> delete mode 100644 board/logicpd/omap3som/MAINTAINERS
> delete mode 100644 board/logicpd/omap3som/Makefile
> delete mode 100644 board/logicpd/omap3som/omap3logic.c
> delete mode 100644 board/logicpd/omap3som/omap3logic.h
> delete mode 100644 configs/omap3_logic_defconfig
> delete mode 100644 include/configs/omap3_logic.h
>
> diff --git a/arch/arm/cpu/armv7/omap3/Kconfig
> b/arch/arm/cpu/armv7/omap3/Kconfig
> index 336da53..9665c95 100644
> --- a/arch/arm/cpu/armv7/omap3/Kconfig
> +++ b/arch/arm/cpu/armv7/omap3/Kconfig
> @@ -87,9 +87,6 @@ config TARGET_MCX
> bool "MCX"
> select SUPPORT_SPL
>
> -config TARGET_OMAP3_LOGIC
> - bool "OMAP3 Logic"
> -
> config TARGET_OMAP3_MVBLX
> bool "OMAP3 MVBLX"
>
> @@ -139,7 +136,6 @@ source "board/pandora/Kconfig"
> source "board/8dtech/eco5pk/Kconfig"
> source "board/corscience/tricorder/Kconfig"
> source "board/htkw/mcx/Kconfig"
> -source "board/logicpd/omap3som/Kconfig"
> source "board/matrix_vision/mvblx/Kconfig"
> source "board/nokia/rx51/Kconfig"
> source "board/technexion/tao3530/Kconfig"
> diff --git a/board/logicpd/omap3som/Kconfig
> b/board/logicpd/omap3som/Kconfig
> deleted file mode 100644
> index 03d272a..0000000
> --- a/board/logicpd/omap3som/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_OMAP3_LOGIC
> -
> -config SYS_BOARD
> - default "omap3som"
> -
> -config SYS_VENDOR
> - default "logicpd"
> -
> -config SYS_CONFIG_NAME
> - default "omap3_logic"
> -
> -endif
> diff --git a/board/logicpd/omap3som/MAINTAINERS
> b/board/logicpd/omap3som/MAINTAINERS
> deleted file mode 100644
> index ffe2201..0000000
> --- a/board/logicpd/omap3som/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -OMAP3SOM BOARD
> -M: Peter Barada <peter.barada@logicpd.com>
> -S: Maintained
> -F: board/logicpd/omap3som/
> -F: include/configs/omap3_logic.h
> -F: configs/omap3_logic_defconfig
> diff --git a/board/logicpd/omap3som/Makefile
> b/board/logicpd/omap3som/Makefile
> deleted file mode 100644
> index 87b86ad..0000000
> --- a/board/logicpd/omap3som/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# (C) Copyright 2000, 2001, 2002
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := omap3logic.o
> diff --git a/board/logicpd/omap3som/omap3logic.c
> b/board/logicpd/omap3som/omap3logic.c
> deleted file mode 100644
> index 609edf1..0000000
> --- a/board/logicpd/omap3som/omap3logic.c
> +++ /dev/null
> @@ -1,242 +0,0 @@
> -/*
> - * (C) Copyright 2011
> - * Logic Product Development <www.logicpd.com>
> - *
> - * Author :
> - * Peter Barada <peter.barada@logicpd.com>
> - *
> - * Derived from Beagle Board and 3430 SDP code by
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Syed Mohammed Khasim <khasim@ti.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#include <common.h>
> -#include <netdev.h>
> -#include <flash.h>
> -#include <nand.h>
> -#include <i2c.h>
> -#include <twl4030.h>
> -#include <asm/io.h>
> -#include <asm/arch/mmc_host_def.h>
> -#include <asm/arch/mux.h>
> -#include <asm/arch/mem.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/gpio.h>
> -#include <asm/mach-types.h>
> -#include "omap3logic.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * two dimensional array of strucures containining board name and Linux
> - * machine IDs; row it selected based on CPU column is slected based
> - * on hsusb0_data5 pin having a pulldown resistor
> - */
> -static struct board_id {
> - char *name;
> - int machine_id;
> -} boards[2][2] = {
> - {
> - {
> - .name = "OMAP35xx SOM LV",
> - .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
> - },
> - {
> - .name = "OMAP35xx Torpedo",
> - .machine_id = MACH_TYPE_OMAP3_TORPEDO,
> - },
> - },
> - {
> - {
> - .name = "DM37xx SOM LV",
> - .machine_id = MACH_TYPE_DM3730_SOM_LV,
> - },
> - {
> - .name = "DM37xx Torpedo",
> - .machine_id = MACH_TYPE_DM3730_TORPEDO,
> - },
> - },
> -};
> -
> -/*
> - * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
> - */
> -#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
> -
> -/*
> - * Routine: board_init
> - * Description: Early hardware init.
> - */
> -int board_init(void)
> -{
> - struct board_id *board;
> - unsigned int val;
> -
> - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> -
> - /* boot param addr */
> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> -
> - /*
> - * To identify between a SOM LV and Torpedo module,
> - * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
> - * Drive the pin (and let it soak), then read it back.
> - * If the pin is still high its a Torpedo. If low its a SOM LV
> - */
> -
> - /* Mux hsusb0_data5 as a GPIO */
> - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
> -
> - if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
> -
> - /*
> - * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM
> LV
> - * will drain the voltage.
> - */
> - gpio_direction_output(BOARD_ID_GPIO, 0);
> - gpio_set_value(BOARD_ID_GPIO, 1);
> -
> - /* Let it soak for a bit */
> - sdelay(0x100);
> -
> - /*
> - * Read state of BOARD_ID_GPIO as an input and if its set.
> - * If so the board is a Torpedo
> - */
> - gpio_direction_input(BOARD_ID_GPIO);
> - val = gpio_get_value(BOARD_ID_GPIO);
> - gpio_free(BOARD_ID_GPIO);
> -
> - board = &boards[!!(get_cpu_family() ==
> CPU_OMAP36XX)][!!val];
> - printf("Board: %s\n", board->name);
> -
> - /* Set the machine_id passed to Linux */
> - gd->bd->bi_arch_number = board->machine_id;
> - }
> -
> - /* restore hsusb0_data5 pin as hsusb0_data5 */
> - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
> -int board_mmc_init(bd_t *bis)
> -{
> - return omap_mmc_init(0, 0, 0, -1, -1);
> -}
> -#endif
> -
> -#if defined(CONFIG_GENERIC_MMC)
> -void board_mmc_power_init(void)
> -{
> - twl4030_power_mmc_init(0);
> -}
> -#endif
> -
> -#ifdef CONFIG_SMC911X
> -/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> -static const u32 gpmc_lan92xx_config[] = {
> - NET_LAN92XX_GPMC_CONFIG1,
> - NET_LAN92XX_GPMC_CONFIG2,
> - NET_LAN92XX_GPMC_CONFIG3,
> - NET_LAN92XX_GPMC_CONFIG4,
> - NET_LAN92XX_GPMC_CONFIG5,
> - NET_LAN92XX_GPMC_CONFIG6,
> -};
> -
> -int board_eth_init(bd_t *bis)
> -{
> - enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
> - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
> -
> - return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> -}
> -#endif
> -
> -/*
> - * IEN - Input Enable
> - * IDIS - Input Disable
> - * PTD - Pull type Down
> - * PTU - Pull type Up
> - * DIS - Pull type selection is inactive
> - * EN - Pull type selection is active
> - * M0 - Mode 0
> - * The commented string gives the final mux configuration for that pin
> - */
> -
> -/*
> - * Routine: set_muxconf_regs
> - * Description: Setting up the configuration Mux registers specific to the
> - * hardware. Many pins need to be moved from protect to
> primary
> - * mode.
> - */
> -void set_muxconf_regs(void)
> -{
> - /*GPMC*/
> - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
> - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
> - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1));
> /*GPMC_IO_DIR*/
> - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
> -
> - /*Expansion card */
> - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
> - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
> -
> - /* Serial Console */
> - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
> - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
> - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
> - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
> -
> - /* I2C */
> - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
> -
> - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
> -
> - /*Control and debug */
> - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
> - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
> - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
> - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
> - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
> -}
> diff --git a/board/logicpd/omap3som/omap3logic.h
> b/board/logicpd/omap3som/omap3logic.h
> deleted file mode 100644
> index 3a3ef6e..0000000
> --- a/board/logicpd/omap3som/omap3logic.h
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/*
> - * (C) Copyright 2011
> - * Logic Product Development <www.logicpd.com>
> - *
> - * Author:
> - * Peter Barada <peter.barada@logicpd.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#ifndef _OMAP3LOGIC_H_
> -#define _OMAP3LOGIC_H_
> -
> -/*
> - * OMAP3 GPMC register settings for CS1 LAN922x
> - */
> -#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
> -#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
> -#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
> -#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
> -#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
> -#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
> -
> -
> -const omap3_sysinfo sysinfo = {
> - DDR_DISCRETE,
> - "Logic DM37x/OMAP35x reference board",
> - "NAND",
> -};
> -
> -
> -#endif
> diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
> deleted file mode 100644
> index 5d0ac9e..0000000
> --- a/configs/omap3_logic_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_OMAP34XX=y
> -CONFIG_TARGET_OMAP3_LOGIC=y
> -# CONFIG_CMD_IMI is not set
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_FPGA is not set
> -CONFIG_SYS_PROMPT="OMAP Logic # "
> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> deleted file mode 100644
> index e09e617..0000000
> --- a/include/configs/omap3_logic.h
> +++ /dev/null
> @@ -1,322 +0,0 @@
> -/*
> - * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
> - * Peter Barada <peter.barada@logicpd.com>
> - *
> - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
> - * reference boards.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_OMAP /* in a TI OMAP core */
> -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards
> */
> -#define CONFIG_OMAP_GPIO
> -#define CONFIG_OMAP_COMMON
> -/* Common ARM Erratas */
> -#define CONFIG_ARM_ERRATA_454179
> -#define CONFIG_ARM_ERRATA_430973
> -#define CONFIG_ARM_ERRATA_621766
> -
> -#define CONFIG_SYS_TEXT_BASE 0x80400000
> -
> -#define CONFIG_SDRC /* The chip has SDRC controller */
> -
> -#include <asm/arch/cpu.h> /* get chip and board defs */
> -#include <asm/arch/omap.h>
> -
> -/*
> - * Display CPU and Board information
> - */
> -#define CONFIG_DISPLAY_CPUINFO
> -#define CONFIG_DISPLAY_BOARDINFO
> -
> -/* Clock Defines */
> -#define V_OSCK 26000000 /* Clock output from T2 */
> -#define V_SCLK (V_OSCK >> 1)
> -
> -#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
> -
> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs
> */
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_INITRD_TAG
> -#define CONFIG_REVISION_TAG
> -
> -#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
> -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no
> delay */
> -
> -/*
> - * Size of malloc() pool
> - */
> -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB
> */
> - /* Sector */
> -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
> -
> -/*
> - * Hardware drivers
> - */
> -
> -/*
> - * NS16550 Configuration
> - */
> -#define V_NS16550_CLK 48000000 /* 48MHz
> (APLL96/2) */
> -
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> -
> -/*
> - * select serial console configuration
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
> -#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic
> boards */
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -#define CONFIG_BAUDRATE 115200
> -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
> - 115200}
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_MMC
> -#define CONFIG_OMAP_HSMMC
> -#define CONFIG_DOS_PARTITION
> -
> -/* commands to include */
> -#define CONFIG_CMD_CACHE
> -#define CONFIG_CMD_EXT2 /* EXT2 Support */
> -#define CONFIG_CMD_FAT /* FAT support */
> -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
> -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
> -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
> -#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
> -#define MTDPARTS_DEFAULT
> "mtdparts=omap2-nand.0:512k(x-loader),"\
> - "1920k(u-boot),128k(u-boot-env),"\
> - "4m(kernel),-(fs)"
> -
> -#define CONFIG_CMD_I2C /* I2C serial bus support */
> -#define CONFIG_CMD_MMC /* MMC support */
> -#define CONFIG_CMD_NAND /* NAND support */
> -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_DHCP
> -
> -#define CONFIG_SYS_NO_FLASH
> -
> -/*
> - * I2C
> - */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
> -#define CONFIG_SYS_I2C_OMAP34XX
> -
> -/*
> - * TWL4030
> - */
> -#define CONFIG_TWL4030_POWER
> -
> -/*
> - * Board NAND Info.
> - */
> -#define CONFIG_SYS_NAND_QUIET_TEST
> -#define CONFIG_NAND_OMAP_GPMC
> -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical
> address */
> - /* to access nand
> */
> -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical
> address */
> - /* to access nand
> at */
> - /* CS0 */
> -
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
> - /* NAND devices */
> -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
> -#define CONFIG_JFFS2_NAND
> -/* nand device jffs2 lives on */
> -#define CONFIG_JFFS2_DEV "nand0"
> -/* start of jffs2 partition */
> -#define CONFIG_JFFS2_PART_OFFSET 0x680000
> -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
> - /* partition */
> -
> -/* Environment information */
> -#define CONFIG_BOOTDELAY 2
> -
> -/*
> - * PREBOOT assumes the 4.3" display is attached. User can interrupt
> - * and modify display variable to suit their needs.
> - */
> -#define CONFIG_PREBOOT \
> - "echo ======================NOTICE============================;"\
> - "echo \"The u-boot environment is not set.\";" \
> - "echo \"If using a display a valid display varible for your
> panel\";" \
> - "echo \"needs to be set.\";" \
> - "echo \"Valid display options are:\";" \
> - "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
> - "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp
> w/ASIC\";" \
> - "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
> - "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
> - "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp
> (DEFAULT)\";" \
> - "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
> - "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
> - "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
> - "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
> - "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
> - "setenv display 15;" \
> - "setenv preboot;" \
> - "saveenv;"
> -
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "loadaddr=0x81000000\0" \
> - "bootfile=uImage\0" \
> - "mtdids=" MTDIDS_DEFAULT "\0" \
> - "mtdparts=" MTDPARTS_DEFAULT "\0" \
> - "mmcdev=0\0" \
> - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
> - "if run loadbootscript; then " \
> - "run bootscript; " \
> - "else " \
> - "run defaultboot;" \
> - "fi; " \
> - "else run defaultboot; fi\0" \
> - "defaultboot=run mmcramboot\0" \
> - "consoledevice=ttyO0\0" \
> - "display=15\0" \
> - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
> - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
> - "rotation=0\0" \
> - "vrfb_arg=if itest ${rotation} -ne 0; then " \
> - "setenv bootargs ${bootargs} omapfb.vrfb=y " \
> - "omapfb.rotate=${rotation}; " \
> - "fi\0" \
> - "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
> - "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
> - "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
> - "${otherbootargs};" \
> - "run addmtdparts; " \
> - "run vrfb_arg\0" \
> - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> - "bootscript=echo 'Running bootscript from mmc ...'; " \
> - "source ${loadaddr}\0" \
> - "loaduimage=mmc rescan ${mmcdev}; " \
> - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
> - "ramdisksize=64000\0" \
> - "ramdiskaddr=0x82000000\0" \
> - "ramdiskimage=rootfs.ext2.gz.uboot\0" \
> - "ramargs=run setconsole; setenv bootargs console=${console} " \
> - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
> - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
> - "run ramargs; " \
> - "run common_bootargs; " \
> - "run dump_bootargs; " \
> - "run loaduimage; " \
> - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
> - "bootm ${loadaddr} ${ramdiskaddr}\0" \
> - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
> - "run ramargs; " \
> - "run common_bootargs; " \
> - "run dump_bootargs; " \
> - "tftpboot ${loadaddr} ${bootfile}; "\
> - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
> - "bootm ${loadaddr} ${ramdiskaddr}\0"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "run autoboot"
> -
> -#define CONFIG_AUTO_COMPLETE
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size
> */
> -/* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> - sizeof(CONFIG_SYS_PROMPT) + 16)
> -#define CONFIG_SYS_MAXARGS 16 /* max number of command
> args */
> -/* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> -/* memtest works on */
> -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> - 0x01F00000) /* 31MB */
> -
> -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default
> load */
> - /* address
> */
> -
> -/*
> - * OMAP3 has 12 GP timers, they can be driven by the system clock
> - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> - * This rate is divided by a local divisor.
> - */
> -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
> -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8
> */
> -
> -/*
> - * Physical Memory Map
> - */
> -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated
> */
> -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> -
> -/*
> - * FLASH and environment organization
> - */
> -
> -/* **** PISMO SUPPORT *** */
> -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2
> sectors */
> -
> -#if defined(CONFIG_CMD_NAND)
> -#define CONFIG_SYS_FLASH_BASE NAND_BASE
> -#elif defined(CONFIG_CMD_ONENAND)
> -#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
> -#endif
> -
> -/* Monitor at start of flash */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> -
> -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts
> here */
> -
> -#if defined(CONFIG_CMD_NAND)
> -#define CONFIG_NAND_OMAP_GPMC
> -#define CONFIG_ENV_IS_IN_NAND
> -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
> -#endif
> -
> -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
> -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
> -
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x800
> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR
> + \
> - CONFIG_SYS_INIT_RAM_SIZE - \
> - GENERATED_GBL_DATA_SIZE)
> -
> -/*
> - * SMSC922x Ethernet
> - */
> -#if defined(CONFIG_CMD_NET)
> -
> -#define CONFIG_SMC911X
> -#define CONFIG_SMC911X_16_BIT
> -#define CONFIG_SMC911X_BASE 0x08000000
> -
> -#endif /* (CONFIG_CMD_NET) */
> -
> -/*
> - * BOOTP fields
> - */
> -
> -#define CONFIG_BOOTP_SUBNETMASK 0x00000001
> -#define CONFIG_BOOTP_GATEWAY 0x00000002
> -#define CONFIG_BOOTP_HOSTNAME 0x00000004
> -#define CONFIG_BOOTP_BOOTPATH 0x00000010
> -
> -#endif /* __CONFIG_H */
> --
> 2.5.0.457.gab17608
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board
2015-08-31 13:47 ` Adam Ford
@ 2015-08-31 13:54 ` Simon Glass
2015-08-31 13:59 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 13:54 UTC (permalink / raw)
To: u-boot
Hi Adam,
On 31 August 2015 at 07:47, Adam Ford <aford173@gmail.com> wrote:
> If I add the one-line patch to add generic support, can we keep this in
> there for the short term? I am working on more patches to both the Kernel
> and U-boot but I haven't pushed them for approvals yet.
That's fine - make sure you run-test it.
[snip]
Regards,
Simon
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board
2015-08-31 13:47 ` Adam Ford
2015-08-31 13:54 ` Simon Glass
@ 2015-08-31 13:59 ` Tom Rini
2015-08-31 14:00 ` Adam Ford
1 sibling, 1 reply; 119+ messages in thread
From: Tom Rini @ 2015-08-31 13:59 UTC (permalink / raw)
To: u-boot
On Mon, Aug 31, 2015 at 08:47:16AM -0500, Adam Ford wrote:
> If I add the one-line patch to add generic support, can we keep this in
> there for the short term? I am working on more patches to both the Kernel
> and U-boot but I haven't pushed them for approvals yet.
Adding Peter. Yes. And you may want to check with Peter if he wants to
continue to be the maintainer of record for the board. Thanks!
>
> adam
>
> On Sun, Aug 30, 2015 at 8:19 PM, Simon Glass <sjg@chromium.org> wrote:
>
> > This board has not been converted to generic board by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > arch/arm/cpu/armv7/omap3/Kconfig | 4 -
> > board/logicpd/omap3som/Kconfig | 12 --
> > board/logicpd/omap3som/MAINTAINERS | 6 -
> > board/logicpd/omap3som/Makefile | 8 -
> > board/logicpd/omap3som/omap3logic.c | 242 ---------------------------
> > board/logicpd/omap3som/omap3logic.h | 31 ----
> > configs/omap3_logic_defconfig | 8 -
> > include/configs/omap3_logic.h | 322
> > ------------------------------------
> > 8 files changed, 633 deletions(-)
> > delete mode 100644 board/logicpd/omap3som/Kconfig
> > delete mode 100644 board/logicpd/omap3som/MAINTAINERS
> > delete mode 100644 board/logicpd/omap3som/Makefile
> > delete mode 100644 board/logicpd/omap3som/omap3logic.c
> > delete mode 100644 board/logicpd/omap3som/omap3logic.h
> > delete mode 100644 configs/omap3_logic_defconfig
> > delete mode 100644 include/configs/omap3_logic.h
> >
> > diff --git a/arch/arm/cpu/armv7/omap3/Kconfig
> > b/arch/arm/cpu/armv7/omap3/Kconfig
> > index 336da53..9665c95 100644
> > --- a/arch/arm/cpu/armv7/omap3/Kconfig
> > +++ b/arch/arm/cpu/armv7/omap3/Kconfig
> > @@ -87,9 +87,6 @@ config TARGET_MCX
> > bool "MCX"
> > select SUPPORT_SPL
> >
> > -config TARGET_OMAP3_LOGIC
> > - bool "OMAP3 Logic"
> > -
> > config TARGET_OMAP3_MVBLX
> > bool "OMAP3 MVBLX"
> >
> > @@ -139,7 +136,6 @@ source "board/pandora/Kconfig"
> > source "board/8dtech/eco5pk/Kconfig"
> > source "board/corscience/tricorder/Kconfig"
> > source "board/htkw/mcx/Kconfig"
> > -source "board/logicpd/omap3som/Kconfig"
> > source "board/matrix_vision/mvblx/Kconfig"
> > source "board/nokia/rx51/Kconfig"
> > source "board/technexion/tao3530/Kconfig"
> > diff --git a/board/logicpd/omap3som/Kconfig
> > b/board/logicpd/omap3som/Kconfig
> > deleted file mode 100644
> > index 03d272a..0000000
> > --- a/board/logicpd/omap3som/Kconfig
> > +++ /dev/null
> > @@ -1,12 +0,0 @@
> > -if TARGET_OMAP3_LOGIC
> > -
> > -config SYS_BOARD
> > - default "omap3som"
> > -
> > -config SYS_VENDOR
> > - default "logicpd"
> > -
> > -config SYS_CONFIG_NAME
> > - default "omap3_logic"
> > -
> > -endif
> > diff --git a/board/logicpd/omap3som/MAINTAINERS
> > b/board/logicpd/omap3som/MAINTAINERS
> > deleted file mode 100644
> > index ffe2201..0000000
> > --- a/board/logicpd/omap3som/MAINTAINERS
> > +++ /dev/null
> > @@ -1,6 +0,0 @@
> > -OMAP3SOM BOARD
> > -M: Peter Barada <peter.barada@logicpd.com>
> > -S: Maintained
> > -F: board/logicpd/omap3som/
> > -F: include/configs/omap3_logic.h
> > -F: configs/omap3_logic_defconfig
> > diff --git a/board/logicpd/omap3som/Makefile
> > b/board/logicpd/omap3som/Makefile
> > deleted file mode 100644
> > index 87b86ad..0000000
> > --- a/board/logicpd/omap3som/Makefile
> > +++ /dev/null
> > @@ -1,8 +0,0 @@
> > -#
> > -# (C) Copyright 2000, 2001, 2002
> > -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > -#
> > -# SPDX-License-Identifier: GPL-2.0+
> > -#
> > -
> > -obj-y := omap3logic.o
> > diff --git a/board/logicpd/omap3som/omap3logic.c
> > b/board/logicpd/omap3som/omap3logic.c
> > deleted file mode 100644
> > index 609edf1..0000000
> > --- a/board/logicpd/omap3som/omap3logic.c
> > +++ /dev/null
> > @@ -1,242 +0,0 @@
> > -/*
> > - * (C) Copyright 2011
> > - * Logic Product Development <www.logicpd.com>
> > - *
> > - * Author :
> > - * Peter Barada <peter.barada@logicpd.com>
> > - *
> > - * Derived from Beagle Board and 3430 SDP code by
> > - * Richard Woodruff <r-woodruff2@ti.com>
> > - * Syed Mohammed Khasim <khasim@ti.com>
> > - *
> > - * SPDX-License-Identifier: GPL-2.0+
> > - */
> > -#include <common.h>
> > -#include <netdev.h>
> > -#include <flash.h>
> > -#include <nand.h>
> > -#include <i2c.h>
> > -#include <twl4030.h>
> > -#include <asm/io.h>
> > -#include <asm/arch/mmc_host_def.h>
> > -#include <asm/arch/mux.h>
> > -#include <asm/arch/mem.h>
> > -#include <asm/arch/sys_proto.h>
> > -#include <asm/gpio.h>
> > -#include <asm/mach-types.h>
> > -#include "omap3logic.h"
> > -
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > -/*
> > - * two dimensional array of strucures containining board name and Linux
> > - * machine IDs; row it selected based on CPU column is slected based
> > - * on hsusb0_data5 pin having a pulldown resistor
> > - */
> > -static struct board_id {
> > - char *name;
> > - int machine_id;
> > -} boards[2][2] = {
> > - {
> > - {
> > - .name = "OMAP35xx SOM LV",
> > - .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
> > - },
> > - {
> > - .name = "OMAP35xx Torpedo",
> > - .machine_id = MACH_TYPE_OMAP3_TORPEDO,
> > - },
> > - },
> > - {
> > - {
> > - .name = "DM37xx SOM LV",
> > - .machine_id = MACH_TYPE_DM3730_SOM_LV,
> > - },
> > - {
> > - .name = "DM37xx Torpedo",
> > - .machine_id = MACH_TYPE_DM3730_TORPEDO,
> > - },
> > - },
> > -};
> > -
> > -/*
> > - * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
> > - */
> > -#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
> > -
> > -/*
> > - * Routine: board_init
> > - * Description: Early hardware init.
> > - */
> > -int board_init(void)
> > -{
> > - struct board_id *board;
> > - unsigned int val;
> > -
> > - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> > -
> > - /* boot param addr */
> > - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> > -
> > - /*
> > - * To identify between a SOM LV and Torpedo module,
> > - * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
> > - * Drive the pin (and let it soak), then read it back.
> > - * If the pin is still high its a Torpedo. If low its a SOM LV
> > - */
> > -
> > - /* Mux hsusb0_data5 as a GPIO */
> > - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
> > -
> > - if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
> > -
> > - /*
> > - * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM
> > LV
> > - * will drain the voltage.
> > - */
> > - gpio_direction_output(BOARD_ID_GPIO, 0);
> > - gpio_set_value(BOARD_ID_GPIO, 1);
> > -
> > - /* Let it soak for a bit */
> > - sdelay(0x100);
> > -
> > - /*
> > - * Read state of BOARD_ID_GPIO as an input and if its set.
> > - * If so the board is a Torpedo
> > - */
> > - gpio_direction_input(BOARD_ID_GPIO);
> > - val = gpio_get_value(BOARD_ID_GPIO);
> > - gpio_free(BOARD_ID_GPIO);
> > -
> > - board = &boards[!!(get_cpu_family() ==
> > CPU_OMAP36XX)][!!val];
> > - printf("Board: %s\n", board->name);
> > -
> > - /* Set the machine_id passed to Linux */
> > - gd->bd->bi_arch_number = board->machine_id;
> > - }
> > -
> > - /* restore hsusb0_data5 pin as hsusb0_data5 */
> > - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
> > -
> > - return 0;
> > -}
> > -
> > -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
> > -int board_mmc_init(bd_t *bis)
> > -{
> > - return omap_mmc_init(0, 0, 0, -1, -1);
> > -}
> > -#endif
> > -
> > -#if defined(CONFIG_GENERIC_MMC)
> > -void board_mmc_power_init(void)
> > -{
> > - twl4030_power_mmc_init(0);
> > -}
> > -#endif
> > -
> > -#ifdef CONFIG_SMC911X
> > -/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> > -static const u32 gpmc_lan92xx_config[] = {
> > - NET_LAN92XX_GPMC_CONFIG1,
> > - NET_LAN92XX_GPMC_CONFIG2,
> > - NET_LAN92XX_GPMC_CONFIG3,
> > - NET_LAN92XX_GPMC_CONFIG4,
> > - NET_LAN92XX_GPMC_CONFIG5,
> > - NET_LAN92XX_GPMC_CONFIG6,
> > -};
> > -
> > -int board_eth_init(bd_t *bis)
> > -{
> > - enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
> > - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
> > -
> > - return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> > -}
> > -#endif
> > -
> > -/*
> > - * IEN - Input Enable
> > - * IDIS - Input Disable
> > - * PTD - Pull type Down
> > - * PTU - Pull type Up
> > - * DIS - Pull type selection is inactive
> > - * EN - Pull type selection is active
> > - * M0 - Mode 0
> > - * The commented string gives the final mux configuration for that pin
> > - */
> > -
> > -/*
> > - * Routine: set_muxconf_regs
> > - * Description: Setting up the configuration Mux registers specific to the
> > - * hardware. Many pins need to be moved from protect to
> > primary
> > - * mode.
> > - */
> > -void set_muxconf_regs(void)
> > -{
> > - /*GPMC*/
> > - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
> > - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
> > - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1));
> > /*GPMC_IO_DIR*/
> > - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
> > -
> > - /*Expansion card */
> > - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
> > - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
> > -
> > - /* Serial Console */
> > - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
> > - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
> > - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
> > - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
> > -
> > - /* I2C */
> > - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
> > -
> > - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
> > -
> > - /*Control and debug */
> > - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
> > - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
> > - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
> > - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
> > - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
> > -}
> > diff --git a/board/logicpd/omap3som/omap3logic.h
> > b/board/logicpd/omap3som/omap3logic.h
> > deleted file mode 100644
> > index 3a3ef6e..0000000
> > --- a/board/logicpd/omap3som/omap3logic.h
> > +++ /dev/null
> > @@ -1,31 +0,0 @@
> > -/*
> > - * (C) Copyright 2011
> > - * Logic Product Development <www.logicpd.com>
> > - *
> > - * Author:
> > - * Peter Barada <peter.barada@logicpd.com>
> > - *
> > - * SPDX-License-Identifier: GPL-2.0+
> > - */
> > -#ifndef _OMAP3LOGIC_H_
> > -#define _OMAP3LOGIC_H_
> > -
> > -/*
> > - * OMAP3 GPMC register settings for CS1 LAN922x
> > - */
> > -#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
> > -#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
> > -#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
> > -#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
> > -#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
> > -#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
> > -
> > -
> > -const omap3_sysinfo sysinfo = {
> > - DDR_DISCRETE,
> > - "Logic DM37x/OMAP35x reference board",
> > - "NAND",
> > -};
> > -
> > -
> > -#endif
> > diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
> > deleted file mode 100644
> > index 5d0ac9e..0000000
> > --- a/configs/omap3_logic_defconfig
> > +++ /dev/null
> > @@ -1,8 +0,0 @@
> > -CONFIG_ARM=y
> > -CONFIG_OMAP34XX=y
> > -CONFIG_TARGET_OMAP3_LOGIC=y
> > -# CONFIG_CMD_IMI is not set
> > -# CONFIG_CMD_IMLS is not set
> > -# CONFIG_CMD_FLASH is not set
> > -# CONFIG_CMD_FPGA is not set
> > -CONFIG_SYS_PROMPT="OMAP Logic # "
> > diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> > deleted file mode 100644
> > index e09e617..0000000
> > --- a/include/configs/omap3_logic.h
> > +++ /dev/null
> > @@ -1,322 +0,0 @@
> > -/*
> > - * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
> > - * Peter Barada <peter.barada@logicpd.com>
> > - *
> > - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
> > - * reference boards.
> > - *
> > - * SPDX-License-Identifier: GPL-2.0+
> > - */
> > -
> > -#ifndef __CONFIG_H
> > -#define __CONFIG_H
> > -
> > -/*
> > - * High Level Configuration Options
> > - */
> > -#define CONFIG_OMAP /* in a TI OMAP core */
> > -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards
> > */
> > -#define CONFIG_OMAP_GPIO
> > -#define CONFIG_OMAP_COMMON
> > -/* Common ARM Erratas */
> > -#define CONFIG_ARM_ERRATA_454179
> > -#define CONFIG_ARM_ERRATA_430973
> > -#define CONFIG_ARM_ERRATA_621766
> > -
> > -#define CONFIG_SYS_TEXT_BASE 0x80400000
> > -
> > -#define CONFIG_SDRC /* The chip has SDRC controller */
> > -
> > -#include <asm/arch/cpu.h> /* get chip and board defs */
> > -#include <asm/arch/omap.h>
> > -
> > -/*
> > - * Display CPU and Board information
> > - */
> > -#define CONFIG_DISPLAY_CPUINFO
> > -#define CONFIG_DISPLAY_BOARDINFO
> > -
> > -/* Clock Defines */
> > -#define V_OSCK 26000000 /* Clock output from T2 */
> > -#define V_SCLK (V_OSCK >> 1)
> > -
> > -#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
> > -
> > -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs
> > */
> > -#define CONFIG_SETUP_MEMORY_TAGS
> > -#define CONFIG_INITRD_TAG
> > -#define CONFIG_REVISION_TAG
> > -
> > -#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
> > -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no
> > delay */
> > -
> > -/*
> > - * Size of malloc() pool
> > - */
> > -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB
> > */
> > - /* Sector */
> > -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
> > -
> > -/*
> > - * Hardware drivers
> > - */
> > -
> > -/*
> > - * NS16550 Configuration
> > - */
> > -#define V_NS16550_CLK 48000000 /* 48MHz
> > (APLL96/2) */
> > -
> > -#define CONFIG_SYS_NS16550
> > -#define CONFIG_SYS_NS16550_SERIAL
> > -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> > -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> > -
> > -/*
> > - * select serial console configuration
> > - */
> > -#define CONFIG_CONS_INDEX 1
> > -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
> > -#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic
> > boards */
> > -
> > -/* allow to overwrite serial and ethaddr */
> > -#define CONFIG_ENV_OVERWRITE
> > -#define CONFIG_BAUDRATE 115200
> > -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
> > - 115200}
> > -#define CONFIG_GENERIC_MMC
> > -#define CONFIG_MMC
> > -#define CONFIG_OMAP_HSMMC
> > -#define CONFIG_DOS_PARTITION
> > -
> > -/* commands to include */
> > -#define CONFIG_CMD_CACHE
> > -#define CONFIG_CMD_EXT2 /* EXT2 Support */
> > -#define CONFIG_CMD_FAT /* FAT support */
> > -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
> > -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
> > -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
> > -#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
> > -#define MTDPARTS_DEFAULT
> > "mtdparts=omap2-nand.0:512k(x-loader),"\
> > - "1920k(u-boot),128k(u-boot-env),"\
> > - "4m(kernel),-(fs)"
> > -
> > -#define CONFIG_CMD_I2C /* I2C serial bus support */
> > -#define CONFIG_CMD_MMC /* MMC support */
> > -#define CONFIG_CMD_NAND /* NAND support */
> > -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
> > -#define CONFIG_CMD_PING
> > -#define CONFIG_CMD_DHCP
> > -
> > -#define CONFIG_SYS_NO_FLASH
> > -
> > -/*
> > - * I2C
> > - */
> > -#define CONFIG_SYS_I2C
> > -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
> > -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
> > -#define CONFIG_SYS_I2C_OMAP34XX
> > -
> > -/*
> > - * TWL4030
> > - */
> > -#define CONFIG_TWL4030_POWER
> > -
> > -/*
> > - * Board NAND Info.
> > - */
> > -#define CONFIG_SYS_NAND_QUIET_TEST
> > -#define CONFIG_NAND_OMAP_GPMC
> > -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical
> > address */
> > - /* to access nand
> > */
> > -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical
> > address */
> > - /* to access nand
> > at */
> > - /* CS0 */
> > -
> > -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
> > - /* NAND devices */
> > -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
> > -#define CONFIG_JFFS2_NAND
> > -/* nand device jffs2 lives on */
> > -#define CONFIG_JFFS2_DEV "nand0"
> > -/* start of jffs2 partition */
> > -#define CONFIG_JFFS2_PART_OFFSET 0x680000
> > -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
> > - /* partition */
> > -
> > -/* Environment information */
> > -#define CONFIG_BOOTDELAY 2
> > -
> > -/*
> > - * PREBOOT assumes the 4.3" display is attached. User can interrupt
> > - * and modify display variable to suit their needs.
> > - */
> > -#define CONFIG_PREBOOT \
> > - "echo ======================NOTICE============================;"\
> > - "echo \"The u-boot environment is not set.\";" \
> > - "echo \"If using a display a valid display varible for your
> > panel\";" \
> > - "echo \"needs to be set.\";" \
> > - "echo \"Valid display options are:\";" \
> > - "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
> > - "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp
> > w/ASIC\";" \
> > - "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
> > - "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
> > - "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp
> > (DEFAULT)\";" \
> > - "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
> > - "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
> > - "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
> > - "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
> > - "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
> > - "setenv display 15;" \
> > - "setenv preboot;" \
> > - "saveenv;"
> > -
> > -
> > -#define CONFIG_EXTRA_ENV_SETTINGS \
> > - "loadaddr=0x81000000\0" \
> > - "bootfile=uImage\0" \
> > - "mtdids=" MTDIDS_DEFAULT "\0" \
> > - "mtdparts=" MTDPARTS_DEFAULT "\0" \
> > - "mmcdev=0\0" \
> > - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
> > - "if run loadbootscript; then " \
> > - "run bootscript; " \
> > - "else " \
> > - "run defaultboot;" \
> > - "fi; " \
> > - "else run defaultboot; fi\0" \
> > - "defaultboot=run mmcramboot\0" \
> > - "consoledevice=ttyO0\0" \
> > - "display=15\0" \
> > - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
> > - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
> > - "rotation=0\0" \
> > - "vrfb_arg=if itest ${rotation} -ne 0; then " \
> > - "setenv bootargs ${bootargs} omapfb.vrfb=y " \
> > - "omapfb.rotate=${rotation}; " \
> > - "fi\0" \
> > - "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
> > - "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
> > - "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
> > - "${otherbootargs};" \
> > - "run addmtdparts; " \
> > - "run vrfb_arg\0" \
> > - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> > - "bootscript=echo 'Running bootscript from mmc ...'; " \
> > - "source ${loadaddr}\0" \
> > - "loaduimage=mmc rescan ${mmcdev}; " \
> > - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
> > - "ramdisksize=64000\0" \
> > - "ramdiskaddr=0x82000000\0" \
> > - "ramdiskimage=rootfs.ext2.gz.uboot\0" \
> > - "ramargs=run setconsole; setenv bootargs console=${console} " \
> > - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
> > - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
> > - "run ramargs; " \
> > - "run common_bootargs; " \
> > - "run dump_bootargs; " \
> > - "run loaduimage; " \
> > - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
> > - "bootm ${loadaddr} ${ramdiskaddr}\0" \
> > - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
> > - "run ramargs; " \
> > - "run common_bootargs; " \
> > - "run dump_bootargs; " \
> > - "tftpboot ${loadaddr} ${bootfile}; "\
> > - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
> > - "bootm ${loadaddr} ${ramdiskaddr}\0"
> > -
> > -#define CONFIG_BOOTCOMMAND \
> > - "run autoboot"
> > -
> > -#define CONFIG_AUTO_COMPLETE
> > -/*
> > - * Miscellaneous configurable options
> > - */
> > -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> > -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size
> > */
> > -/* Print Buffer Size */
> > -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > - sizeof(CONFIG_SYS_PROMPT) + 16)
> > -#define CONFIG_SYS_MAXARGS 16 /* max number of command
> > args */
> > -/* Boot Argument Buffer Size */
> > -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> > -/* memtest works on */
> > -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> > -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> > - 0x01F00000) /* 31MB */
> > -
> > -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default
> > load */
> > - /* address
> > */
> > -
> > -/*
> > - * OMAP3 has 12 GP timers, they can be driven by the system clock
> > - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> > - * This rate is divided by a local divisor.
> > - */
> > -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
> > -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8
> > */
> > -
> > -/*
> > - * Physical Memory Map
> > - */
> > -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated
> > */
> > -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> > -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> > -
> > -/*
> > - * FLASH and environment organization
> > - */
> > -
> > -/* **** PISMO SUPPORT *** */
> > -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2
> > sectors */
> > -
> > -#if defined(CONFIG_CMD_NAND)
> > -#define CONFIG_SYS_FLASH_BASE NAND_BASE
> > -#elif defined(CONFIG_CMD_ONENAND)
> > -#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
> > -#endif
> > -
> > -/* Monitor at start of flash */
> > -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> > -
> > -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts
> > here */
> > -
> > -#if defined(CONFIG_CMD_NAND)
> > -#define CONFIG_NAND_OMAP_GPMC
> > -#define CONFIG_ENV_IS_IN_NAND
> > -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
> > -#endif
> > -
> > -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
> > -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
> > -
> > -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> > -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
> > -#define CONFIG_SYS_INIT_RAM_SIZE 0x800
> > -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR
> > + \
> > - CONFIG_SYS_INIT_RAM_SIZE - \
> > - GENERATED_GBL_DATA_SIZE)
> > -
> > -/*
> > - * SMSC922x Ethernet
> > - */
> > -#if defined(CONFIG_CMD_NET)
> > -
> > -#define CONFIG_SMC911X
> > -#define CONFIG_SMC911X_16_BIT
> > -#define CONFIG_SMC911X_BASE 0x08000000
> > -
> > -#endif /* (CONFIG_CMD_NET) */
> > -
> > -/*
> > - * BOOTP fields
> > - */
> > -
> > -#define CONFIG_BOOTP_SUBNETMASK 0x00000001
> > -#define CONFIG_BOOTP_GATEWAY 0x00000002
> > -#define CONFIG_BOOTP_HOSTNAME 0x00000004
> > -#define CONFIG_BOOTP_BOOTPATH 0x00000010
> > -
> > -#endif /* __CONFIG_H */
> > --
> > 2.5.0.457.gab17608
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board
2015-08-31 13:59 ` Tom Rini
@ 2015-08-31 14:00 ` Adam Ford
0 siblings, 0 replies; 119+ messages in thread
From: Adam Ford @ 2015-08-31 14:00 UTC (permalink / raw)
To: u-boot
I actually work with Peter at Logic PD. If he doesn't want to continue to
be the maintainer, I can take that over. I know he is busy.
Thank you,
adam
On Mon, Aug 31, 2015 at 8:59 AM, Tom Rini <trini@konsulko.com> wrote:
> On Mon, Aug 31, 2015 at 08:47:16AM -0500, Adam Ford wrote:
>
> > If I add the one-line patch to add generic support, can we keep this in
> > there for the short term? I am working on more patches to both the
> Kernel
> > and U-boot but I haven't pushed them for approvals yet.
>
> Adding Peter. Yes. And you may want to check with Peter if he wants to
> continue to be the maintainer of record for the board. Thanks!
>
> >
> > adam
> >
> > On Sun, Aug 30, 2015 at 8:19 PM, Simon Glass <sjg@chromium.org> wrote:
> >
> > > This board has not been converted to generic board by the deadline.
> > > Remove it.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > arch/arm/cpu/armv7/omap3/Kconfig | 4 -
> > > board/logicpd/omap3som/Kconfig | 12 --
> > > board/logicpd/omap3som/MAINTAINERS | 6 -
> > > board/logicpd/omap3som/Makefile | 8 -
> > > board/logicpd/omap3som/omap3logic.c | 242 ---------------------------
> > > board/logicpd/omap3som/omap3logic.h | 31 ----
> > > configs/omap3_logic_defconfig | 8 -
> > > include/configs/omap3_logic.h | 322
> > > ------------------------------------
> > > 8 files changed, 633 deletions(-)
> > > delete mode 100644 board/logicpd/omap3som/Kconfig
> > > delete mode 100644 board/logicpd/omap3som/MAINTAINERS
> > > delete mode 100644 board/logicpd/omap3som/Makefile
> > > delete mode 100644 board/logicpd/omap3som/omap3logic.c
> > > delete mode 100644 board/logicpd/omap3som/omap3logic.h
> > > delete mode 100644 configs/omap3_logic_defconfig
> > > delete mode 100644 include/configs/omap3_logic.h
> > >
> > > diff --git a/arch/arm/cpu/armv7/omap3/Kconfig
> > > b/arch/arm/cpu/armv7/omap3/Kconfig
> > > index 336da53..9665c95 100644
> > > --- a/arch/arm/cpu/armv7/omap3/Kconfig
> > > +++ b/arch/arm/cpu/armv7/omap3/Kconfig
> > > @@ -87,9 +87,6 @@ config TARGET_MCX
> > > bool "MCX"
> > > select SUPPORT_SPL
> > >
> > > -config TARGET_OMAP3_LOGIC
> > > - bool "OMAP3 Logic"
> > > -
> > > config TARGET_OMAP3_MVBLX
> > > bool "OMAP3 MVBLX"
> > >
> > > @@ -139,7 +136,6 @@ source "board/pandora/Kconfig"
> > > source "board/8dtech/eco5pk/Kconfig"
> > > source "board/corscience/tricorder/Kconfig"
> > > source "board/htkw/mcx/Kconfig"
> > > -source "board/logicpd/omap3som/Kconfig"
> > > source "board/matrix_vision/mvblx/Kconfig"
> > > source "board/nokia/rx51/Kconfig"
> > > source "board/technexion/tao3530/Kconfig"
> > > diff --git a/board/logicpd/omap3som/Kconfig
> > > b/board/logicpd/omap3som/Kconfig
> > > deleted file mode 100644
> > > index 03d272a..0000000
> > > --- a/board/logicpd/omap3som/Kconfig
> > > +++ /dev/null
> > > @@ -1,12 +0,0 @@
> > > -if TARGET_OMAP3_LOGIC
> > > -
> > > -config SYS_BOARD
> > > - default "omap3som"
> > > -
> > > -config SYS_VENDOR
> > > - default "logicpd"
> > > -
> > > -config SYS_CONFIG_NAME
> > > - default "omap3_logic"
> > > -
> > > -endif
> > > diff --git a/board/logicpd/omap3som/MAINTAINERS
> > > b/board/logicpd/omap3som/MAINTAINERS
> > > deleted file mode 100644
> > > index ffe2201..0000000
> > > --- a/board/logicpd/omap3som/MAINTAINERS
> > > +++ /dev/null
> > > @@ -1,6 +0,0 @@
> > > -OMAP3SOM BOARD
> > > -M: Peter Barada <peter.barada@logicpd.com>
> > > -S: Maintained
> > > -F: board/logicpd/omap3som/
> > > -F: include/configs/omap3_logic.h
> > > -F: configs/omap3_logic_defconfig
> > > diff --git a/board/logicpd/omap3som/Makefile
> > > b/board/logicpd/omap3som/Makefile
> > > deleted file mode 100644
> > > index 87b86ad..0000000
> > > --- a/board/logicpd/omap3som/Makefile
> > > +++ /dev/null
> > > @@ -1,8 +0,0 @@
> > > -#
> > > -# (C) Copyright 2000, 2001, 2002
> > > -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > > -#
> > > -# SPDX-License-Identifier: GPL-2.0+
> > > -#
> > > -
> > > -obj-y := omap3logic.o
> > > diff --git a/board/logicpd/omap3som/omap3logic.c
> > > b/board/logicpd/omap3som/omap3logic.c
> > > deleted file mode 100644
> > > index 609edf1..0000000
> > > --- a/board/logicpd/omap3som/omap3logic.c
> > > +++ /dev/null
> > > @@ -1,242 +0,0 @@
> > > -/*
> > > - * (C) Copyright 2011
> > > - * Logic Product Development <www.logicpd.com>
> > > - *
> > > - * Author :
> > > - * Peter Barada <peter.barada@logicpd.com>
> > > - *
> > > - * Derived from Beagle Board and 3430 SDP code by
> > > - * Richard Woodruff <r-woodruff2@ti.com>
> > > - * Syed Mohammed Khasim <khasim@ti.com>
> > > - *
> > > - * SPDX-License-Identifier: GPL-2.0+
> > > - */
> > > -#include <common.h>
> > > -#include <netdev.h>
> > > -#include <flash.h>
> > > -#include <nand.h>
> > > -#include <i2c.h>
> > > -#include <twl4030.h>
> > > -#include <asm/io.h>
> > > -#include <asm/arch/mmc_host_def.h>
> > > -#include <asm/arch/mux.h>
> > > -#include <asm/arch/mem.h>
> > > -#include <asm/arch/sys_proto.h>
> > > -#include <asm/gpio.h>
> > > -#include <asm/mach-types.h>
> > > -#include "omap3logic.h"
> > > -
> > > -DECLARE_GLOBAL_DATA_PTR;
> > > -
> > > -/*
> > > - * two dimensional array of strucures containining board name and
> Linux
> > > - * machine IDs; row it selected based on CPU column is slected based
> > > - * on hsusb0_data5 pin having a pulldown resistor
> > > - */
> > > -static struct board_id {
> > > - char *name;
> > > - int machine_id;
> > > -} boards[2][2] = {
> > > - {
> > > - {
> > > - .name = "OMAP35xx SOM LV",
> > > - .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
> > > - },
> > > - {
> > > - .name = "OMAP35xx Torpedo",
> > > - .machine_id = MACH_TYPE_OMAP3_TORPEDO,
> > > - },
> > > - },
> > > - {
> > > - {
> > > - .name = "DM37xx SOM LV",
> > > - .machine_id = MACH_TYPE_DM3730_SOM_LV,
> > > - },
> > > - {
> > > - .name = "DM37xx Torpedo",
> > > - .machine_id = MACH_TYPE_DM3730_TORPEDO,
> > > - },
> > > - },
> > > -};
> > > -
> > > -/*
> > > - * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM
> LV
> > > - */
> > > -#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
> > > -
> > > -/*
> > > - * Routine: board_init
> > > - * Description: Early hardware init.
> > > - */
> > > -int board_init(void)
> > > -{
> > > - struct board_id *board;
> > > - unsigned int val;
> > > -
> > > - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> > > -
> > > - /* boot param addr */
> > > - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> > > -
> > > - /*
> > > - * To identify between a SOM LV and Torpedo module,
> > > - * a pulldown resistor is on hsusb0_data5 for the SOM LV
> module.
> > > - * Drive the pin (and let it soak), then read it back.
> > > - * If the pin is still high its a Torpedo. If low its a SOM LV
> > > - */
> > > -
> > > - /* Mux hsusb0_data5 as a GPIO */
> > > - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
> > > -
> > > - if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
> > > -
> > > - /*
> > > - * Drive BOARD_ID_GPIO - the pulldown resistor on the
> SOM
> > > LV
> > > - * will drain the voltage.
> > > - */
> > > - gpio_direction_output(BOARD_ID_GPIO, 0);
> > > - gpio_set_value(BOARD_ID_GPIO, 1);
> > > -
> > > - /* Let it soak for a bit */
> > > - sdelay(0x100);
> > > -
> > > - /*
> > > - * Read state of BOARD_ID_GPIO as an input and if its
> set.
> > > - * If so the board is a Torpedo
> > > - */
> > > - gpio_direction_input(BOARD_ID_GPIO);
> > > - val = gpio_get_value(BOARD_ID_GPIO);
> > > - gpio_free(BOARD_ID_GPIO);
> > > -
> > > - board = &boards[!!(get_cpu_family() ==
> > > CPU_OMAP36XX)][!!val];
> > > - printf("Board: %s\n", board->name);
> > > -
> > > - /* Set the machine_id passed to Linux */
> > > - gd->bd->bi_arch_number = board->machine_id;
> > > - }
> > > -
> > > - /* restore hsusb0_data5 pin as hsusb0_data5 */
> > > - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
> > > -
> > > - return 0;
> > > -}
> > > -
> > > -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
> > > -int board_mmc_init(bd_t *bis)
> > > -{
> > > - return omap_mmc_init(0, 0, 0, -1, -1);
> > > -}
> > > -#endif
> > > -
> > > -#if defined(CONFIG_GENERIC_MMC)
> > > -void board_mmc_power_init(void)
> > > -{
> > > - twl4030_power_mmc_init(0);
> > > -}
> > > -#endif
> > > -
> > > -#ifdef CONFIG_SMC911X
> > > -/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> > > -static const u32 gpmc_lan92xx_config[] = {
> > > - NET_LAN92XX_GPMC_CONFIG1,
> > > - NET_LAN92XX_GPMC_CONFIG2,
> > > - NET_LAN92XX_GPMC_CONFIG3,
> > > - NET_LAN92XX_GPMC_CONFIG4,
> > > - NET_LAN92XX_GPMC_CONFIG5,
> > > - NET_LAN92XX_GPMC_CONFIG6,
> > > -};
> > > -
> > > -int board_eth_init(bd_t *bis)
> > > -{
> > > - enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
> > > - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
> > > -
> > > - return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> > > -}
> > > -#endif
> > > -
> > > -/*
> > > - * IEN - Input Enable
> > > - * IDIS - Input Disable
> > > - * PTD - Pull type Down
> > > - * PTU - Pull type Up
> > > - * DIS - Pull type selection is inactive
> > > - * EN - Pull type selection is active
> > > - * M0 - Mode 0
> > > - * The commented string gives the final mux configuration for that pin
> > > - */
> > > -
> > > -/*
> > > - * Routine: set_muxconf_regs
> > > - * Description: Setting up the configuration Mux registers specific
> to the
> > > - * hardware. Many pins need to be moved from protect to
> > > primary
> > > - * mode.
> > > - */
> > > -void set_muxconf_regs(void)
> > > -{
> > > - /*GPMC*/
> > > - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
> > > - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
> > > - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1));
> > > /*GPMC_IO_DIR*/
> > > - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
> > > -
> > > - /*Expansion card */
> > > - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
> > > - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
> > > -
> > > - /* Serial Console */
> > > - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
> > > - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
> > > - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
> > > - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
> > > -
> > > - /* I2C */
> > > - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
> > > -
> > > - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
> > > -
> > > - /*Control and debug */
> > > - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
> > > - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
> > > - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
> > > - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
> > > - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
> > > -}
> > > diff --git a/board/logicpd/omap3som/omap3logic.h
> > > b/board/logicpd/omap3som/omap3logic.h
> > > deleted file mode 100644
> > > index 3a3ef6e..0000000
> > > --- a/board/logicpd/omap3som/omap3logic.h
> > > +++ /dev/null
> > > @@ -1,31 +0,0 @@
> > > -/*
> > > - * (C) Copyright 2011
> > > - * Logic Product Development <www.logicpd.com>
> > > - *
> > > - * Author:
> > > - * Peter Barada <peter.barada@logicpd.com>
> > > - *
> > > - * SPDX-License-Identifier: GPL-2.0+
> > > - */
> > > -#ifndef _OMAP3LOGIC_H_
> > > -#define _OMAP3LOGIC_H_
> > > -
> > > -/*
> > > - * OMAP3 GPMC register settings for CS1 LAN922x
> > > - */
> > > -#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
> > > -#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
> > > -#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
> > > -#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
> > > -#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
> > > -#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
> > > -
> > > -
> > > -const omap3_sysinfo sysinfo = {
> > > - DDR_DISCRETE,
> > > - "Logic DM37x/OMAP35x reference board",
> > > - "NAND",
> > > -};
> > > -
> > > -
> > > -#endif
> > > diff --git a/configs/omap3_logic_defconfig
> b/configs/omap3_logic_defconfig
> > > deleted file mode 100644
> > > index 5d0ac9e..0000000
> > > --- a/configs/omap3_logic_defconfig
> > > +++ /dev/null
> > > @@ -1,8 +0,0 @@
> > > -CONFIG_ARM=y
> > > -CONFIG_OMAP34XX=y
> > > -CONFIG_TARGET_OMAP3_LOGIC=y
> > > -# CONFIG_CMD_IMI is not set
> > > -# CONFIG_CMD_IMLS is not set
> > > -# CONFIG_CMD_FLASH is not set
> > > -# CONFIG_CMD_FPGA is not set
> > > -CONFIG_SYS_PROMPT="OMAP Logic # "
> > > diff --git a/include/configs/omap3_logic.h
> b/include/configs/omap3_logic.h
> > > deleted file mode 100644
> > > index e09e617..0000000
> > > --- a/include/configs/omap3_logic.h
> > > +++ /dev/null
> > > @@ -1,322 +0,0 @@
> > > -/*
> > > - * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
> > > - * Peter Barada <peter.barada@logicpd.com>
> > > - *
> > > - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
> > > - * reference boards.
> > > - *
> > > - * SPDX-License-Identifier: GPL-2.0+
> > > - */
> > > -
> > > -#ifndef __CONFIG_H
> > > -#define __CONFIG_H
> > > -
> > > -/*
> > > - * High Level Configuration Options
> > > - */
> > > -#define CONFIG_OMAP /* in a TI OMAP core */
> > > -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP
> boards
> > > */
> > > -#define CONFIG_OMAP_GPIO
> > > -#define CONFIG_OMAP_COMMON
> > > -/* Common ARM Erratas */
> > > -#define CONFIG_ARM_ERRATA_454179
> > > -#define CONFIG_ARM_ERRATA_430973
> > > -#define CONFIG_ARM_ERRATA_621766
> > > -
> > > -#define CONFIG_SYS_TEXT_BASE 0x80400000
> > > -
> > > -#define CONFIG_SDRC /* The chip has SDRC controller */
> > > -
> > > -#include <asm/arch/cpu.h> /* get chip and board defs */
> > > -#include <asm/arch/omap.h>
> > > -
> > > -/*
> > > - * Display CPU and Board information
> > > - */
> > > -#define CONFIG_DISPLAY_CPUINFO
> > > -#define CONFIG_DISPLAY_BOARDINFO
> > > -
> > > -/* Clock Defines */
> > > -#define V_OSCK 26000000 /* Clock output from
> T2 */
> > > -#define V_SCLK (V_OSCK >> 1)
> > > -
> > > -#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die
> id */
> > > -
> > > -#define CONFIG_CMDLINE_TAG /* enable passing of
> ATAGs
> > > */
> > > -#define CONFIG_SETUP_MEMORY_TAGS
> > > -#define CONFIG_INITRD_TAG
> > > -#define CONFIG_REVISION_TAG
> > > -
> > > -#define CONFIG_CMDLINE_EDITING /* cmd line
> edit/history */
> > > -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no
> > > delay */
> > > -
> > > -/*
> > > - * Size of malloc() pool
> > > - */
> > > -#define CONFIG_ENV_SIZE (128 << 10) /* 128
> KiB
> > > */
> > > - /* Sector */
> > > -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
> > > -
> > > -/*
> > > - * Hardware drivers
> > > - */
> > > -
> > > -/*
> > > - * NS16550 Configuration
> > > - */
> > > -#define V_NS16550_CLK 48000000 /* 48MHz
> > > (APLL96/2) */
> > > -
> > > -#define CONFIG_SYS_NS16550
> > > -#define CONFIG_SYS_NS16550_SERIAL
> > > -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> > > -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> > > -
> > > -/*
> > > - * select serial console configuration
> > > - */
> > > -#define CONFIG_CONS_INDEX 1
> > > -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
> > > -#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic
> > > boards */
> > > -
> > > -/* allow to overwrite serial and ethaddr */
> > > -#define CONFIG_ENV_OVERWRITE
> > > -#define CONFIG_BAUDRATE 115200
> > > -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,
> 57600,\
> > > - 115200}
> > > -#define CONFIG_GENERIC_MMC
> > > -#define CONFIG_MMC
> > > -#define CONFIG_OMAP_HSMMC
> > > -#define CONFIG_DOS_PARTITION
> > > -
> > > -/* commands to include */
> > > -#define CONFIG_CMD_CACHE
> > > -#define CONFIG_CMD_EXT2 /* EXT2 Support
> */
> > > -#define CONFIG_CMD_FAT /* FAT support */
> > > -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
> > > -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
> > > -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
> > > -#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
> > > -#define MTDPARTS_DEFAULT
> > > "mtdparts=omap2-nand.0:512k(x-loader),"\
> > > -
> "1920k(u-boot),128k(u-boot-env),"\
> > > - "4m(kernel),-(fs)"
> > > -
> > > -#define CONFIG_CMD_I2C /* I2C serial bus support */
> > > -#define CONFIG_CMD_MMC /* MMC support */
> > > -#define CONFIG_CMD_NAND /* NAND support
> */
> > > -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands
> */
> > > -#define CONFIG_CMD_PING
> > > -#define CONFIG_CMD_DHCP
> > > -
> > > -#define CONFIG_SYS_NO_FLASH
> > > -
> > > -/*
> > > - * I2C
> > > - */
> > > -#define CONFIG_SYS_I2C
> > > -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
> > > -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
> > > -#define CONFIG_SYS_I2C_OMAP34XX
> > > -
> > > -/*
> > > - * TWL4030
> > > - */
> > > -#define CONFIG_TWL4030_POWER
> > > -
> > > -/*
> > > - * Board NAND Info.
> > > - */
> > > -#define CONFIG_SYS_NAND_QUIET_TEST
> > > -#define CONFIG_NAND_OMAP_GPMC
> > > -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical
> > > address */
> > > - /* to access
> nand
> > > */
> > > -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical
> > > address */
> > > - /* to access
> nand
> > > at */
> > > - /* CS0 */
> > > -
> > > -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number
> of */
> > > - /* NAND
> devices */
> > > -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
> > > -#define CONFIG_JFFS2_NAND
> > > -/* nand device jffs2 lives on */
> > > -#define CONFIG_JFFS2_DEV "nand0"
> > > -/* start of jffs2 partition */
> > > -#define CONFIG_JFFS2_PART_OFFSET 0x680000
> > > -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of
> jffs2 */
> > > - /* partition */
> > > -
> > > -/* Environment information */
> > > -#define CONFIG_BOOTDELAY 2
> > > -
> > > -/*
> > > - * PREBOOT assumes the 4.3" display is attached. User can interrupt
> > > - * and modify display variable to suit their needs.
> > > - */
> > > -#define CONFIG_PREBOOT \
> > > - "echo
> ======================NOTICE============================;"\
> > > - "echo \"The u-boot environment is not set.\";"
> \
> > > - "echo \"If using a display a valid display varible for your
> > > panel\";" \
> > > - "echo \"needs to be set.\";"
> \
> > > - "echo \"Valid display options are:\";"
> \
> > > - "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";"
> \
> > > - "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp
> > > w/ASIC\";" \
> > > - "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";"
> \
> > > - "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";"
> \
> > > - "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp
> > > (DEFAULT)\";" \
> > > - "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";"
> \
> > > - "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";"
> \
> > > - "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";"
> \
> > > - "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";"
> \
> > > - "echo \"Defaulting to 4.3 LCD panel (display=15).\";"
> \
> > > - "setenv display 15;"
> \
> > > - "setenv preboot;"
> \
> > > - "saveenv;"
> > > -
> > > -
> > > -#define CONFIG_EXTRA_ENV_SETTINGS \
> > > - "loadaddr=0x81000000\0" \
> > > - "bootfile=uImage\0" \
> > > - "mtdids=" MTDIDS_DEFAULT "\0" \
> > > - "mtdparts=" MTDPARTS_DEFAULT "\0" \
> > > - "mmcdev=0\0" \
> > > - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
> > > - "if run loadbootscript; then " \
> > > - "run bootscript; " \
> > > - "else " \
> > > - "run defaultboot;" \
> > > - "fi; " \
> > > - "else run defaultboot; fi\0" \
> > > - "defaultboot=run mmcramboot\0" \
> > > - "consoledevice=ttyO0\0" \
> > > - "display=15\0" \
> > > - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
> > > - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
> > > - "rotation=0\0" \
> > > - "vrfb_arg=if itest ${rotation} -ne 0; then " \
> > > - "setenv bootargs ${bootargs} omapfb.vrfb=y " \
> > > - "omapfb.rotate=${rotation}; " \
> > > - "fi\0" \
> > > - "otherbootargs=ignore_loglevel early_printk
> no_console_suspend\0" \
> > > - "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
> > > - "common_bootargs=setenv bootargs ${bootargs}
> display=${display} " \
> > > - "${otherbootargs};" \
> > > - "run addmtdparts; " \
> > > - "run vrfb_arg\0" \
> > > - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> > > - "bootscript=echo 'Running bootscript from mmc ...'; " \
> > > - "source ${loadaddr}\0" \
> > > - "loaduimage=mmc rescan ${mmcdev}; " \
> > > - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
> > > - "ramdisksize=64000\0" \
> > > - "ramdiskaddr=0x82000000\0" \
> > > - "ramdiskimage=rootfs.ext2.gz.uboot\0" \
> > > - "ramargs=run setconsole; setenv bootargs console=${console} " \
> > > - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
> > > - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
> > > - "run ramargs; " \
> > > - "run common_bootargs; " \
> > > - "run dump_bootargs; " \
> > > - "run loaduimage; " \
> > > - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage};
> "\
> > > - "bootm ${loadaddr} ${ramdiskaddr}\0" \
> > > - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
> > > - "run ramargs; " \
> > > - "run common_bootargs; " \
> > > - "run dump_bootargs; " \
> > > - "tftpboot ${loadaddr} ${bootfile}; "\
> > > - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
> > > - "bootm ${loadaddr} ${ramdiskaddr}\0"
> > > -
> > > -#define CONFIG_BOOTCOMMAND \
> > > - "run autoboot"
> > > -
> > > -#define CONFIG_AUTO_COMPLETE
> > > -/*
> > > - * Miscellaneous configurable options
> > > - */
> > > -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > > -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> > > -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer
> Size
> > > */
> > > -/* Print Buffer Size */
> > > -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> > > - sizeof(CONFIG_SYS_PROMPT) + 16)
> > > -#define CONFIG_SYS_MAXARGS 16 /* max number of
> command
> > > args */
> > > -/* Boot Argument Buffer Size */
> > > -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> > > -/* memtest works on */
> > > -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> > > -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> > > - 0x01F00000) /* 31MB */
> > > -
> > > -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default
> > > load */
> > > - /*
> address
> > > */
> > > -
> > > -/*
> > > - * OMAP3 has 12 GP timers, they can be driven by the system clock
> > > - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> > > - * This rate is divided by a local divisor.
> > > - */
> > > -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
> > > -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1)
> => 8
> > > */
> > > -
> > > -/*
> > > - * Physical Memory Map
> > > - */
> > > -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be
> populated
> > > */
> > > -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> > > -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> > > -
> > > -/*
> > > - * FLASH and environment organization
> > > - */
> > > -
> > > -/* **** PISMO SUPPORT *** */
> > > -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2
> > > sectors */
> > > -
> > > -#if defined(CONFIG_CMD_NAND)
> > > -#define CONFIG_SYS_FLASH_BASE NAND_BASE
> > > -#elif defined(CONFIG_CMD_ONENAND)
> > > -#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
> > > -#endif
> > > -
> > > -/* Monitor at start of flash */
> > > -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> > > -
> > > -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts
> > > here */
> > > -
> > > -#if defined(CONFIG_CMD_NAND)
> > > -#define CONFIG_NAND_OMAP_GPMC
> > > -#define CONFIG_ENV_IS_IN_NAND
> > > -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
> > > -#endif
> > > -
> > > -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
> > > -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
> > > -
> > > -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> > > -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
> > > -#define CONFIG_SYS_INIT_RAM_SIZE 0x800
> > > -#define CONFIG_SYS_INIT_SP_ADDR
> (CONFIG_SYS_INIT_RAM_ADDR
> > > + \
> > > - CONFIG_SYS_INIT_RAM_SIZE - \
> > > - GENERATED_GBL_DATA_SIZE)
> > > -
> > > -/*
> > > - * SMSC922x Ethernet
> > > - */
> > > -#if defined(CONFIG_CMD_NET)
> > > -
> > > -#define CONFIG_SMC911X
> > > -#define CONFIG_SMC911X_16_BIT
> > > -#define CONFIG_SMC911X_BASE 0x08000000
> > > -
> > > -#endif /* (CONFIG_CMD_NET) */
> > > -
> > > -/*
> > > - * BOOTP fields
> > > - */
> > > -
> > > -#define CONFIG_BOOTP_SUBNETMASK 0x00000001
> > > -#define CONFIG_BOOTP_GATEWAY 0x00000002
> > > -#define CONFIG_BOOTP_HOSTNAME 0x00000004
> > > -#define CONFIG_BOOTP_BOOTPATH 0x00000010
> > > -
> > > -#endif /* __CONFIG_H */
> > > --
> > > 2.5.0.457.gab17608
> > >
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot at lists.denx.de
> > > http://lists.denx.de/mailman/listinfo/u-boot
> > >
>
> --
> Tom
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-08-31 13:16 ` Simon Glass
@ 2015-08-31 14:07 ` Albert ARIBAUD
2015-09-01 17:01 ` [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for " Simon Guinot
2015-09-02 12:07 ` [U-Boot] [PATCH 03/45] arm: Remove most " Simon Guinot
2 siblings, 0 replies; 119+ messages in thread
From: Albert ARIBAUD @ 2015-08-31 14:07 UTC (permalink / raw)
To: u-boot
Hi SimonS,
Le Mon, 31 Aug 2015 07:16:16 -0600,
Simon Glass <sjg@chromium.org> a ?crit :
> Hi Simon,
>
> On 31 August 2015 at 01:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> > On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> >> These boards have not been converted to generic board by the deadline.
> >> Remove all except edmini_v2 (which has been converted).
> >
> > Hi Simon,
> >
> > Great... Is it still time to convert this boards to "generic board"
> > support ?
>
> Yes if you are quick - please see doc/README.generic-board which has
> instructions. It should be very simple.
>
> >
> > You know, a direct email (I mean with my email address in the To or Cc
> > fields) to make me aware of this project would have been both fair and
> > very appreciated.
>
> OK well I'm sorry you haven't seen anything up until now. I wonder if
> we should cc all the maintainers when we have an announcement that
> affects their boards. There are a lot of maintainers though!
>
> It is probably worth checking in every now and then to see what is going on.
>
> [snip]
>
> Regards,
> Simon
I'm the maintainer for Wireless Space, so I'll whip up the switch to
generic for this one, at least.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 1:19 ` [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board Simon Glass
@ 2015-08-31 14:38 ` Tom Rini
2015-08-31 15:59 ` Tom Rini
2015-08-31 14:50 ` Felipe Balbi
1 sibling, 1 reply; 119+ messages in thread
From: Tom Rini @ 2015-08-31 14:38 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:35PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board
2015-08-31 1:19 ` [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board Simon Glass
@ 2015-08-31 14:50 ` Felipe Balbi
2015-08-31 15:13 ` Tony Lindgren
2015-08-31 15:30 ` Simon Glass
2015-08-31 16:05 ` Tom Rini
1 sibling, 2 replies; 119+ messages in thread
From: Felipe Balbi @ 2015-08-31 14:50 UTC (permalink / raw)
To: u-boot
Hi,
On Sun, Aug 30, 2015 at 07:19:37PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
there are people using this and ti816x at least.
> ---
>
> arch/arm/Kconfig | 6 --
> board/ti/ti814x/Kconfig | 15 ---
> board/ti/ti814x/MAINTAINERS | 6 --
> board/ti/ti814x/Makefile | 13 ---
> board/ti/ti814x/evm.c | 188 -----------------------------------
> board/ti/ti814x/evm.h | 8 --
> board/ti/ti814x/mux.c | 86 ----------------
> configs/ti814x_evm_defconfig | 7 --
> include/configs/ti814x_evm.h | 230 -------------------------------------------
> 9 files changed, 559 deletions(-)
> delete mode 100644 board/ti/ti814x/Kconfig
> delete mode 100644 board/ti/ti814x/MAINTAINERS
> delete mode 100644 board/ti/ti814x/Makefile
> delete mode 100644 board/ti/ti814x/evm.c
> delete mode 100644 board/ti/ti814x/evm.h
> delete mode 100644 board/ti/ti814x/mux.c
> delete mode 100644 configs/ti814x_evm_defconfig
> delete mode 100644 include/configs/ti814x_evm.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8ef21a3..1a171d1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -378,11 +378,6 @@ config TARGET_BAV335X
>
> For more information, visit: http://birdland.com/oem
>
> -config TARGET_TI814X_EVM
> - bool "Support ti814x_evm"
> - select CPU_V7
> - select SUPPORT_SPL
> -
> config TARGET_TI816X_EVM
> bool "Support ti816x_evm"
> select CPU_V7
> @@ -859,7 +854,6 @@ source "board/tbs/tbs2910/Kconfig"
> source "board/ti/am335x/Kconfig"
> source "board/ti/am43xx/Kconfig"
> source "board/birdland/bav335x/Kconfig"
> -source "board/ti/ti814x/Kconfig"
> source "board/ti/ti816x/Kconfig"
> source "board/timll/devkit3250/Kconfig"
> source "board/toradex/colibri_pxa270/Kconfig"
> diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
> deleted file mode 100644
> index 2960099..0000000
> --- a/board/ti/ti814x/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_TI814X_EVM
> -
> -config SYS_BOARD
> - default "ti814x"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_SOC
> - default "am33xx"
> -
> -config SYS_CONFIG_NAME
> - default "ti814x_evm"
> -
> -endif
> diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS
> deleted file mode 100644
> index e39b253..0000000
> --- a/board/ti/ti814x/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -TI814X BOARD
> -M: Matt Porter <matt.porter@linaro.org>
> -S: Maintained
> -F: board/ti/ti814x/
> -F: include/configs/ti814x_evm.h
> -F: configs/ti814x_evm_defconfig
> diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
> deleted file mode 100644
> index 93155de..0000000
> --- a/board/ti/ti814x/Makefile
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -#
> -# Makefile
> -#
> -# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -ifdef CONFIG_SPL_BUILD
> -obj-y := mux.o
> -endif
> -
> -obj-y += evm.o
> diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
> deleted file mode 100644
> index e406dab..0000000
> --- a/board/ti/ti814x/evm.c
> +++ /dev/null
> @@ -1,188 +0,0 @@
> -/*
> - * evm.c
> - *
> - * Board functions for TI814x EVM
> - *
> - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <cpsw.h>
> -#include <errno.h>
> -#include <spl.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/omap.h>
> -#include <asm/arch/ddr_defs.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/gpio.h>
> -#include <asm/arch/mmc_host_def.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/io.h>
> -#include <asm/emif.h>
> -#include <asm/gpio.h>
> -#include "evm.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
> -
> -/* UART Defines */
> -#ifdef CONFIG_SPL_BUILD
> -static const struct cmd_control evm_ddr2_cctrl_data = {
> - .cmd0csratio = 0x80,
> - .cmd0iclkout = 0x00,
> -
> - .cmd1csratio = 0x80,
> - .cmd1iclkout = 0x00,
> -
> - .cmd2csratio = 0x80,
> - .cmd2iclkout = 0x00,
> -};
> -
> -static const struct emif_regs evm_ddr2_emif0_regs = {
> - .sdram_config = 0x40801ab2,
> - .ref_ctrl = 0x10000c30,
> - .sdram_tim1 = 0x0aaaf552,
> - .sdram_tim2 = 0x043631d2,
> - .sdram_tim3 = 0x00000327,
> - .emif_ddr_phy_ctlr_1 = 0x00000007
> -};
> -
> -static const struct emif_regs evm_ddr2_emif1_regs = {
> - .sdram_config = 0x40801ab2,
> - .ref_ctrl = 0x10000c30,
> - .sdram_tim1 = 0x0aaaf552,
> - .sdram_tim2 = 0x043631d2,
> - .sdram_tim3 = 0x00000327,
> - .emif_ddr_phy_ctlr_1 = 0x00000007
> -};
> -
> -const struct dmm_lisa_map_regs evm_lisa_map_regs = {
> - .dmm_lisa_map_0 = 0x00000000,
> - .dmm_lisa_map_1 = 0x00000000,
> - .dmm_lisa_map_2 = 0x806c0300,
> - .dmm_lisa_map_3 = 0x806c0300,
> -};
> -
> -static const struct ddr_data evm_ddr2_data = {
> - .datardsratio0 = ((0x35<<10) | (0x35<<0)),
> - .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
> - .datawiratio0 = ((0<<10) | (0<<0)),
> - .datagiratio0 = ((0<<10) | (0<<0)),
> - .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
> - .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
> -};
> -
> -void set_uart_mux_conf(void)
> -{
> - /* Set UART pins */
> - enable_uart0_pin_mux();
> -}
> -
> -void set_mux_conf_regs(void)
> -{
> - /* Set MMC pins */
> - enable_mmc1_pin_mux();
> -
> - /* Set Ethernet pins */
> - enable_enet_pin_mux();
> -}
> -
> -void sdram_init(void)
> -{
> - config_dmm(&evm_lisa_map_regs);
> -
> - config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
> - &evm_ddr2_emif0_regs, 0);
> - config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
> - &evm_ddr2_emif1_regs, 1);
> -}
> -#endif
> -
> -/*
> - * Basic board specific setup. Pinmux has been handled already.
> - */
> -int board_init(void)
> -{
> - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> - return 0;
> -}
> -
> -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
> -int board_mmc_init(bd_t *bis)
> -{
> - omap_mmc_init(1, 0, 0, -1, -1);
> -
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_DRIVER_TI_CPSW
> -static void cpsw_control(int enabled)
> -{
> - /* VTP can be added here */
> -
> - return;
> -}
> -
> -static struct cpsw_slave_data cpsw_slaves[] = {
> - {
> - .slave_reg_ofs = 0x50,
> - .sliver_reg_ofs = 0x700,
> - .phy_addr = 1,
> - },
> - {
> - .slave_reg_ofs = 0x90,
> - .sliver_reg_ofs = 0x740,
> - .phy_addr = 0,
> - },
> -};
> -
> -static struct cpsw_platform_data cpsw_data = {
> - .mdio_base = CPSW_MDIO_BASE,
> - .cpsw_base = CPSW_BASE,
> - .mdio_div = 0xff,
> - .channels = 8,
> - .cpdma_reg_ofs = 0x100,
> - .slaves = 1,
> - .slave_data = cpsw_slaves,
> - .ale_reg_ofs = 0x600,
> - .ale_entries = 1024,
> - .host_port_reg_ofs = 0x28,
> - .hw_stats_reg_ofs = 0x400,
> - .bd_ram_ofs = 0x2000,
> - .mac_control = (1 << 5),
> - .control = cpsw_control,
> - .host_port_num = 0,
> - .version = CPSW_CTRL_VERSION_1,
> -};
> -#endif
> -
> -int board_eth_init(bd_t *bis)
> -{
> - uint8_t mac_addr[6];
> - uint32_t mac_hi, mac_lo;
> -
> - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
> - printf("<ethaddr> not set. Reading from E-fuse\n");
> - /* try reading mac address from efuse */
> - mac_lo = readl(&cdev->macid0l);
> - mac_hi = readl(&cdev->macid0h);
> - mac_addr[0] = mac_hi & 0xFF;
> - mac_addr[1] = (mac_hi & 0xFF00) >> 8;
> - mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
> - mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
> - mac_addr[4] = mac_lo & 0xFF;
> - mac_addr[5] = (mac_lo & 0xFF00) >> 8;
> -
> - if (is_valid_ethaddr(mac_addr))
> - eth_setenv_enetaddr("ethaddr", mac_addr);
> - else
> - printf("Unable to read MAC address. Set <ethaddr>\n");
> - }
> -
> - return cpsw_register(&cpsw_data);
> -}
> diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
> deleted file mode 100644
> index 6aebec6..0000000
> --- a/board/ti/ti814x/evm.h
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#ifndef _EVM_H
> -#define _EVM_H
> -
> -void enable_uart0_pin_mux(void);
> -void enable_mmc1_pin_mux(void);
> -void enable_enet_pin_mux(void);
> -
> -#endif /* _EVM_H */
> diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
> deleted file mode 100644
> index fd9f364..0000000
> --- a/board/ti/ti814x/mux.c
> +++ /dev/null
> @@ -1,86 +0,0 @@
> -/*
> - * mux.c
> - *
> - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#include <common.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/mux.h>
> -#include <asm/io.h>
> -#include <i2c.h>
> -#include "evm.h"
> -
> -static struct module_pin_mux uart0_pin_mux[] = {
> - {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
> - {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
> - {-1},
> -};
> -
> -static struct module_pin_mux mmc1_pin_mux[] = {
> - {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
> - {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
> - {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
> - {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
> - {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
> - {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
> - {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
> - {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
> - {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
> - {-1},
> -};
> -
> -static struct module_pin_mux enet_pin_mux[] = {
> - {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
> - {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
> - {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
> - {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
> - {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
> - {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
> - {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
> - {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
> - {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
> - {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
> - {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
> - {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
> - {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
> - {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
> - {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
> - {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
> - {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
> - {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
> - {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
> - {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
> - {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
> - {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
> - {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
> - {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
> - {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
> - {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
> - {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
> -};
> -
> -void enable_uart0_pin_mux(void)
> -{
> - configure_module_pin_mux(uart0_pin_mux);
> -}
> -
> -void enable_mmc1_pin_mux(void)
> -{
> - configure_module_pin_mux(mmc1_pin_mux);
> -}
> -
> -void enable_enet_pin_mux(void)
> -{
> - configure_module_pin_mux(enet_pin_mux);
> -}
> diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
> deleted file mode 100644
> index f7d1e11..0000000
> --- a/configs/ti814x_evm_defconfig
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_TARGET_TI814X_EVM=y
> -CONFIG_SPL=y
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SYS_PROMPT="U-Boot# "
> diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
> deleted file mode 100644
> index 7fa35a1..0000000
> --- a/include/configs/ti814x_evm.h
> +++ /dev/null
> @@ -1,230 +0,0 @@
> -/*
> - * ti814x_evm.h
> - *
> - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef __CONFIG_TI814X_EVM_H
> -#define __CONFIG_TI814X_EVM_H
> -
> -#define CONFIG_TI81XX
> -#define CONFIG_TI814X
> -#define CONFIG_SYS_NO_FLASH
> -#define CONFIG_OMAP
> -#define CONFIG_OMAP_COMMON
> -
> -#include <asm/arch/omap.h>
> -
> -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
> -#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
> -#define CONFIG_SYS_LONGHELP /* undef to save memory */
> -#define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */
> -#define CONFIG_SYS_NO_FLASH
> -#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
> -
> -#define CONFIG_OF_LIBFDT
> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_INITRD_TAG /* for ramdisk support */
> -
> -/* commands to include */
> -#define CONFIG_CMD_ASKENV
> -#define CONFIG_VERSION_VARIABLE
> -
> -#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
> -#define CONFIG_ENV_VARS_UBOOT_CONFIG
> -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "loadaddr=0x80200000\0" \
> - "fdtaddr=0x80F80000\0" \
> - "rdaddr=0x81000000\0" \
> - "bootfile=/boot/uImage\0" \
> - "fdtfile=\0" \
> - "console=ttyO0,115200n8\0" \
> - "optargs=\0" \
> - "mmcdev=0\0" \
> - "mmcroot=/dev/mmcblk0p2 ro\0" \
> - "mmcrootfstype=ext4 rootwait\0" \
> - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
> - "ramrootfstype=ext2\0" \
> - "mmcargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "root=${mmcroot} " \
> - "rootfstype=${mmcrootfstype}\0" \
> - "bootenv=uEnv.txt\0" \
> - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
> - "importbootenv=echo Importing environment from mmc ...; " \
> - "env import -t $loadaddr $filesize\0" \
> - "ramargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "root=${ramroot} " \
> - "rootfstype=${ramrootfstype}\0" \
> - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
> - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
> - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
> - "mmcboot=echo Booting from mmc ...; " \
> - "run mmcargs; " \
> - "bootm ${loadaddr}\0" \
> - "ramboot=echo Booting from ramdisk ...; " \
> - "run ramargs; " \
> - "bootm ${loadaddr}\0" \
> - "fdtfile=ti814x-evm.dtb\0" \
> -
> -#define CONFIG_BOOTCOMMAND \
> - "mmc dev ${mmcdev}; if mmc rescan; then " \
> - "echo SD/MMC found on device ${mmcdev};" \
> - "if run loadbootenv; then " \
> - "echo Loaded environment from ${bootenv};" \
> - "run importbootenv;" \
> - "fi;" \
> - "if test -n $uenvcmd; then " \
> - "echo Running uenvcmd ...;" \
> - "run uenvcmd;" \
> - "fi;" \
> - "if run loaduimage; then " \
> - "run mmcboot;" \
> - "fi;" \
> - "fi;" \
> -
> -/* Clock Defines */
> -#define V_OSCK 24000000 /* Clock output from T2 */
> -#define V_SCLK (V_OSCK >> 1)
> -
> -/* max number of command args */
> -#define CONFIG_SYS_MAXARGS 16
> -
> -/* Console I/O Buffer Size */
> -#define CONFIG_SYS_CBSIZE 512
> -
> -/* Print Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
> - + sizeof(CONFIG_SYS_PROMPT) + 16)
> -
> -/* Boot Argument Buffer Size */
> -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> -
> -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
> - + PHYS_DRAM_1_SIZE - (8 << 12))
> -
> -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
> -
> -#define CONFIG_OMAP_GPIO
> -#define CONFIG_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_OMAP_HSMMC
> -#define CONFIG_CMD_MMC
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_CMD_FAT
> -#define CONFIG_CMD_EXT2
> -
> -/**
> - * Physical Memory Map
> - */
> -#define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */
> -#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
> -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
> -
> -#define CONFIG_SYS_SDRAM_BASE 0x80000000
> -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
> - GENERATED_GBL_DATA_SIZE)
> -
> -/**
> - * Platform/Board specific defs
> - */
> -#define CONFIG_SYS_TIMERBASE 0x4802E000
> -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
> -
> -/* NS16550 Configuration */
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> -#define CONFIG_SYS_NS16550_CLK (48000000)
> -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
> -
> -#define CONFIG_BAUDRATE 115200
> -
> -/* CPU */
> -#define CONFIG_ARCH_CPU_INIT
> -
> -#define CONFIG_ENV_OVERWRITE
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SYS_CONSOLE_INFO_QUIET
> -
> -#define CONFIG_ENV_IS_NOWHERE
> -
> -/* Defines for SPL */
> -#define CONFIG_SPL_FRAMEWORK
> -#define CONFIG_SPL_TEXT_BASE 0x40300000
> -#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
> -
> -#define CONFIG_SPL_BSS_START_ADDR 0x80000000
> -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
> -
> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
> -#define CONFIG_SPL_MMC_SUPPORT
> -#define CONFIG_SPL_FAT_SUPPORT
> -
> -#define CONFIG_SPL_LIBCOMMON_SUPPORT
> -#define CONFIG_SPL_LIBDISK_SUPPORT
> -#define CONFIG_SPL_LIBGENERIC_SUPPORT
> -#define CONFIG_SPL_SERIAL_SUPPORT
> -#define CONFIG_SPL_GPIO_SUPPORT
> -#define CONFIG_SPL_YMODEM_SUPPORT
> -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
> -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
> -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
> -
> -#define CONFIG_SPL_BOARD_INIT
> -
> -/*
> - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> - * 64 bytes before this address should be set aside for u-boot.img's
> - * header. That is 0x800FFFC0--0x80800000 should not be used for any
> - * other needs.
> - */
> -#define CONFIG_SYS_TEXT_BASE 0x80800000
> -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
> -
> -/*
> - * Since SPL did pll and ddr initialization for us,
> - * we don't need to do it twice.
> - */
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_SKIP_LOWLEVEL_INIT
> -#endif
> -
> -/* Unsupported features */
> -#undef CONFIG_USE_IRQ
> -
> -/* Ethernet */
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_MII
> -#define CONFIG_DRIVER_TI_CPSW
> -#define CONFIG_MII
> -#define CONFIG_BOOTP_DNS
> -#define CONFIG_BOOTP_DNS2
> -#define CONFIG_BOOTP_SEND_HOSTNAME
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_SUBNETMASK
> -#define CONFIG_NET_RETRY_COUNT 10
> -#define CONFIG_PHY_GIGE
> -#define CONFIG_PHYLIB
> -#define CONFIG_PHY_ET1011C
> -#define CONFIG_PHY_ET1011C_TX_CLK_FIX
> -
> -#endif /* ! __CONFIG_TI814X_EVM_H */
> --
> 2.5.0.457.gab17608
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
balbi
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 1:19 ` [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board Simon Glass
2015-08-31 14:38 ` Tom Rini
@ 2015-08-31 14:50 ` Felipe Balbi
2015-08-31 15:11 ` Tony Lindgren
1 sibling, 1 reply; 119+ messages in thread
From: Felipe Balbi @ 2015-08-31 14:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:35PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
I have a feeling people still this too.
> ---
>
> arch/arm/cpu/armv7/omap3/Kconfig | 13 --
> board/quipos/cairo/cairo.c | 12 -
> board/ti/evm/Kconfig | 38 ----
> board/ti/evm/MAINTAINERS | 10 -
> board/ti/evm/Makefile | 8 -
> board/ti/evm/evm.c | 274 -----------------------
> board/ti/evm/evm.h | 394 ---------------------------------
> configs/omap3_evm_defconfig | 10 -
> configs/omap3_evm_quick_mmc_defconfig | 26 ---
> configs/omap3_evm_quick_nand_defconfig | 26 ---
> doc/README.omap3 | 5 -
> drivers/usb/musb/omap3.c | 4 -
> drivers/usb/musb/omap3.h | 4 -
> include/configs/omap3_evm.h | 154 -------------
> include/configs/omap3_evm_common.h | 289 ------------------------
> include/configs/omap3_evm_quick_mmc.h | 92 --------
> include/configs/omap3_evm_quick_nand.h | 92 --------
> 17 files changed, 1451 deletions(-)
> delete mode 100644 board/ti/evm/Kconfig
> delete mode 100644 board/ti/evm/MAINTAINERS
> delete mode 100644 board/ti/evm/Makefile
> delete mode 100644 board/ti/evm/evm.c
> delete mode 100644 board/ti/evm/evm.h
> delete mode 100644 configs/omap3_evm_defconfig
> delete mode 100644 configs/omap3_evm_quick_mmc_defconfig
> delete mode 100644 configs/omap3_evm_quick_nand_defconfig
> delete mode 100644 include/configs/omap3_evm.h
> delete mode 100644 include/configs/omap3_evm_common.h
> delete mode 100644 include/configs/omap3_evm_quick_mmc.h
> delete mode 100644 include/configs/omap3_evm_quick_nand.h
>
> diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
> index c758038..408bb76 100644
> --- a/arch/arm/cpu/armv7/omap3/Kconfig
> +++ b/arch/arm/cpu/armv7/omap3/Kconfig
> @@ -33,18 +33,6 @@ config TARGET_DEVKIT8000
> select DM_SERIAL
> select DM_GPIO
>
> -config TARGET_OMAP3_EVM
> - bool "TI OMAP3 EVM"
> - select SUPPORT_SPL
> -
> -config TARGET_OMAP3_EVM_QUICK_MMC
> - bool "TI OMAP3 EVM Quick MMC"
> - select SUPPORT_SPL
> -
> -config TARGET_OMAP3_EVM_QUICK_NAND
> - bool "TI OMAP3 EVM Quick NAND"
> - select SUPPORT_SPL
> -
> config TARGET_OMAP3_IGEP00X0
> bool "IGEP"
> select SUPPORT_SPL
> @@ -120,7 +108,6 @@ source "board/ti/beagle/Kconfig"
> source "board/compulab/cm_t35/Kconfig"
> source "board/compulab/cm_t3517/Kconfig"
> source "board/timll/devkit8000/Kconfig"
> -source "board/ti/evm/Kconfig"
> source "board/isee/igep00x0/Kconfig"
> source "board/overo/Kconfig"
> source "board/logicpd/zoom1/Kconfig"
> diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
> index b97a09a..083e19a 100644
> --- a/board/quipos/cairo/cairo.c
> +++ b/board/quipos/cairo/cairo.c
> @@ -26,18 +26,6 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> /*
> - * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
> - */
> -u8 omap3_evm_need_extvbus(void)
> -{
> - u8 retval = 0;
> -
> - /* TODO: verify if cairo handheld platform needs extvbus programming */
> -
> - return retval;
> -}
> -
> -/*
> * Routine: board_init
> * Description: Early hardware init.
> */
> diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig
> deleted file mode 100644
> index f02aa31..0000000
> --- a/board/ti/evm/Kconfig
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -if TARGET_OMAP3_EVM
> -
> -config SYS_BOARD
> - default "evm"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_CONFIG_NAME
> - default "omap3_evm"
> -
> -endif
> -
> -if TARGET_OMAP3_EVM_QUICK_MMC
> -
> -config SYS_BOARD
> - default "evm"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_CONFIG_NAME
> - default "omap3_evm_quick_mmc"
> -
> -endif
> -
> -if TARGET_OMAP3_EVM_QUICK_NAND
> -
> -config SYS_BOARD
> - default "evm"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_CONFIG_NAME
> - default "omap3_evm_quick_nand"
> -
> -endif
> diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS
> deleted file mode 100644
> index 90c3f6b..0000000
> --- a/board/ti/evm/MAINTAINERS
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -EVM BOARD
> -M: Tom Rini <trini@konsulko.com>
> -S: Maintained
> -F: board/ti/evm/
> -F: include/configs/omap3_evm.h
> -F: include/configs/omap3_evm_quick_mmc.h
> -F: include/configs/omap3_evm_quick_nand.h
> -F: configs/omap3_evm_defconfig
> -F: configs/omap3_evm_quick_mmc_defconfig
> -F: configs/omap3_evm_quick_nand_defconfig
> diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile
> deleted file mode 100644
> index b88ab8f..0000000
> --- a/board/ti/evm/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# (C) Copyright 2000, 2001, 2002
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := evm.o
> diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
> deleted file mode 100644
> index 3f93d9c..0000000
> --- a/board/ti/evm/evm.c
> +++ /dev/null
> @@ -1,274 +0,0 @@
> -/*
> - * (C) Copyright 2004-2011
> - * Texas Instruments, <www.ti.com>
> - *
> - * Author :
> - * Manikandan Pillai <mani.pillai@ti.com>
> - *
> - * Derived from Beagle Board and 3430 SDP code by
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Syed Mohammed Khasim <khasim@ti.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#include <common.h>
> -#include <netdev.h>
> -#include <asm/io.h>
> -#include <asm/arch/mem.h>
> -#include <asm/arch/mux.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/arch/mmc_host_def.h>
> -#include <asm/gpio.h>
> -#include <i2c.h>
> -#include <twl4030.h>
> -#include <asm/mach-types.h>
> -#include <linux/mtd/nand.h>
> -#include "evm.h"
> -
> -#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
> -#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static u32 omap3_evm_version;
> -
> -u32 get_omap3_evm_rev(void)
> -{
> - return omap3_evm_version;
> -}
> -
> -static void omap3_evm_get_revision(void)
> -{
> -#if defined(CONFIG_CMD_NET)
> - /*
> - * Board revision can be ascertained only by identifying
> - * the Ethernet chipset.
> - */
> - unsigned int smsc_id;
> -
> - /* Ethernet PHY ID is stored at ID_REV register */
> - smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
> - printf("Read back SMSC id 0x%x\n", smsc_id);
> -
> - switch (smsc_id) {
> - /* SMSC9115 chipset */
> - case 0x01150000:
> - omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
> - break;
> - /* SMSC 9220 chipset */
> - case 0x92200000:
> - default:
> - omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
> - }
> -#else
> -#if defined(CONFIG_STATIC_BOARD_REV)
> - /*
> - * Look for static defintion of the board revision
> - */
> - omap3_evm_version = CONFIG_STATIC_BOARD_REV;
> -#else
> - /*
> - * Fallback to the default above.
> - */
> - omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
> -#endif
> -#endif /* CONFIG_CMD_NET */
> -}
> -
> -#ifdef CONFIG_USB_OMAP3
> -/*
> - * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
> - */
> -u8 omap3_evm_need_extvbus(void)
> -{
> - u8 retval = 0;
> -
> - if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
> - retval = 1;
> -
> - return retval;
> -}
> -#endif
> -
> -/*
> - * Routine: board_init
> - * Description: Early hardware init.
> - */
> -int board_init(void)
> -{
> - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> - /* board id for Linux */
> - gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
> - /* boot param addr */
> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -/*
> - * Routine: get_board_mem_timings
> - * Description: If we use SPL then there is no x-loader nor config header
> - * so we have to setup the DDR timings ourself on the first bank. This
> - * provides the timing values back to the function that configures
> - * the memory.
> - */
> -void get_board_mem_timings(struct board_sdrc_timings *timings)
> -{
> - int pop_mfr, pop_id;
> -
> - /*
> - * We need to identify what PoP memory is on the board so that
> - * we know what timings to use. To map the ID values please see
> - * nand_ids.c
> - */
> - identify_nand_chip(&pop_mfr, &pop_id);
> -
> - if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
> - /* 256MB DDR */
> - timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
> - timings->ctrla = HYNIX_V_ACTIMA_200;
> - timings->ctrlb = HYNIX_V_ACTIMB_200;
> - } else {
> - /* 128MB DDR */
> - timings->mcfg = MICRON_V_MCFG_165(128 << 20);
> - timings->ctrla = MICRON_V_ACTIMA_165;
> - timings->ctrlb = MICRON_V_ACTIMB_165;
> - }
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> - timings->mr = MICRON_V_MR_165;
> -}
> -#endif
> -
> -/*
> - * Routine: misc_init_r
> - * Description: Init ethernet (done here so udelay works)
> - */
> -int misc_init_r(void)
> -{
> -
> -#ifdef CONFIG_SYS_I2C_OMAP34XX
> - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
> -#endif
> -
> -#if defined(CONFIG_CMD_NET)
> - setup_net_chip();
> -#endif
> - omap3_evm_get_revision();
> -
> -#if defined(CONFIG_CMD_NET)
> - reset_net_chip();
> -#endif
> - dieid_num_r();
> -
> - return 0;
> -}
> -
> -/*
> - * Routine: set_muxconf_regs
> - * Description: Setting up the configuration Mux registers specific to the
> - * hardware. Many pins need to be moved from protect to primary
> - * mode.
> - */
> -void set_muxconf_regs(void)
> -{
> - MUX_EVM();
> -}
> -
> -#ifdef CONFIG_CMD_NET
> -/*
> - * Routine: setup_net_chip
> - * Description: Setting up the configuration GPMC registers specific to the
> - * Ethernet hardware.
> - */
> -static void setup_net_chip(void)
> -{
> - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> -
> - /* Configure GPMC registers */
> - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
> - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
> - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
> - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
> - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
> - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
> - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
> -
> - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> - writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> - &ctrl_base->gpmc_nadv_ale);
> -}
> -
> -/**
> - * Reset the ethernet chip.
> - */
> -static void reset_net_chip(void)
> -{
> - int ret;
> - int rst_gpio;
> -
> - if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
> - rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
> - } else {
> - rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
> - }
> -
> - ret = gpio_request(rst_gpio, "");
> - if (ret < 0) {
> - printf("Unable to get GPIO %d\n", rst_gpio);
> - return ;
> - }
> -
> - /* Configure as output */
> - gpio_direction_output(rst_gpio, 0);
> -
> - /* Send a pulse on the GPIO pin */
> - gpio_set_value(rst_gpio, 1);
> - udelay(1);
> - gpio_set_value(rst_gpio, 0);
> - udelay(1);
> - gpio_set_value(rst_gpio, 1);
> -}
> -
> -int board_eth_init(bd_t *bis)
> -{
> - int rc = 0;
> -#ifdef CONFIG_SMC911X
> -#define STR_ENV_ETHADDR "ethaddr"
> -
> - struct eth_device *dev;
> - uchar eth_addr[6];
> -
> - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> -
> - if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
> - dev = eth_get_dev_by_index(0);
> - if (dev) {
> - eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
> - } else {
> - printf("omap3evm: Couldn't get eth device\n");
> - rc = -1;
> - }
> - }
> -#endif
> - return rc;
> -}
> -#endif /* CONFIG_CMD_NET */
> -
> -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
> -int board_mmc_init(bd_t *bis)
> -{
> - return omap_mmc_init(0, 0, 0, -1, -1);
> -}
> -#endif
> -
> -#if defined(CONFIG_GENERIC_MMC)
> -void board_mmc_power_init(void)
> -{
> - twl4030_power_mmc_init(0);
> -}
> -#endif
> diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
> deleted file mode 100644
> index 91e9b88..0000000
> --- a/board/ti/evm/evm.h
> +++ /dev/null
> @@ -1,394 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Nishanth Menon <menon.nishanth@gmail.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -#ifndef _EVM_H_
> -#define _EVM_H_
> -
> -const omap3_sysinfo sysinfo = {
> - DDR_DISCRETE,
> - "OMAP3 EVM board",
> -#if defined(CONFIG_ENV_IS_IN_ONENAND)
> - "OneNAND",
> -#else
> - "NAND",
> -#endif
> -};
> -
> -/*
> - * OMAP35x EVM revision
> - * Run time detection of EVM revision is done by reading Ethernet
> - * PHY ID -
> - * GEN_1 = 0x01150000
> - * GEN_2 = 0x92200000
> - */
> -enum {
> - OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
> - OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
> -};
> -
> -u32 get_omap3_evm_rev(void);
> -
> -#if defined(CONFIG_CMD_NET)
> -static void setup_net_chip(void);
> -static void reset_net_chip(void);
> -#endif
> -
> -/*
> - * IEN - Input Enable
> - * IDIS - Input Disable
> - * PTD - Pull type Down
> - * PTU - Pull type Up
> - * DIS - Pull type selection is inactive
> - * EN - Pull type selection is active
> - * M0 - Mode 0
> - * The commented string gives the final mux configuration for that pin
> - */
> -#define MUX_EVM() \
> - /*SDRC*/\
> - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
> - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
> - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
> - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
> - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
> - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
> - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
> - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
> - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
> - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
> - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
> - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
> - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
> - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
> - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
> - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
> - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
> - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
> - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
> - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
> - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
> - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
> - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
> - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
> - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
> - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
> - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
> - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
> - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
> - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
> - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
> - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
> - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
> - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
> - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
> - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
> - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
> - /*GPMC*/\
> - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
> - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
> - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
> - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
> - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
> - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
> - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
> - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
> - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
> - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
> - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
> - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
> - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
> - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
> - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
> - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
> - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
> - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
> - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
> - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
> - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
> - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
> - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
> - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
> - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
> - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
> - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
> - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
> - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
> - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
> - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
> - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
> - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
> - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
> - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
> - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
> - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
> - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
> - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
> - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
> - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
> - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
> - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
> - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
> - /* - ETH_nRESET*/\
> - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
> - /*DSS*/\
> - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
> - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
> - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
> - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
> - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
> - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
> - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
> - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
> - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
> - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
> - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
> - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
> - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
> - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
> - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
> - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
> - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
> - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
> - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
> - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
> - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
> - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
> - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
> - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
> - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
> - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
> - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
> - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
> - /*CAMERA*/\
> - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
> - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
> - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
> - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
> - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
> - /* - CAM_RESET*/\
> - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
> - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
> - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
> - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
> - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
> - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
> - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
> - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
> - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
> - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
> - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
> - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
> - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
> - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
> - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
> - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
> - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
> - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
> - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
> - /*Audio Interface */\
> - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
> - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
> - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
> - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
> - /*Expansion card */\
> - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
> - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
> - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
> - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
> - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
> - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
> - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
> - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
> - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
> - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
> - /*Wireless LAN */\
> - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
> - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
> - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
> - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
> - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
> - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
> - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
> - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
> - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
> - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
> - /*Bluetooth*/\
> - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
> - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
> - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
> - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
> - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
> - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
> - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
> - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
> - /*Modem Interface */\
> - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
> - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
> - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
> - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
> - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
> - /* - LCD_INI*/\
> - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
> - /* - LCD_ENVDD */\
> - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
> - /* - LCD_QVGA/nVGA */\
> - MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
> - /* - LCD_RESB */\
> - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\
> - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\
> - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
> - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
> - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
> - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
> - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
> - /*Serial Interface*/\
> - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
> - /* RCTX*/\
> - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
> - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
> - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
> - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
> - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
> - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
> - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
> - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
> - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
> - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
> - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
> - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
> - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
> - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
> - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
> - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
> - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
> - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
> - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
> - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
> - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
> - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
> - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
> - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
> - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
> - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
> - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
> - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
> - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
> - /* TS_PEN_IRQ */\
> - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
> - /* - LAN_INTR*/\
> - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
> - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
> - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
> - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
> - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
> - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
> - /*Control and debug */\
> - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
> - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
> - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
> - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
> - /* - PEN_IRQ */\
> - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
> - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
> - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
> - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
> - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
> - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
> - /* - VIO_1V8*/\
> - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
> - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
> - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
> - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
> - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
> - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
> - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
> - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
> - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
> - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\
> - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
> - MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\
> - MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\
> - MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\
> - MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\
> - MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\
> - MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\
> - MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\
> - MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\
> - MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\
> - MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\
> - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\
> - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\
> - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\
> - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\
> - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\
> - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\
> - /*Die to Die */\
> - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
> - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
> - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
> - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
> - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
> - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
> - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
> - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
> - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
> - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
> - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
> - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
> - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
> - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
> - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
> - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
> - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
> - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
> - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
> - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
> - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
> - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
> - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
> - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
> - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
> - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
> - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
> - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
> - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
> - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
> - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
> - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
> - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
> - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
> - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
> - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
> - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
> - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
> - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
> - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
> - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
> - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
> - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
> - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
> - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
> - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
> - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
> - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
> - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
> - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
> - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
> - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
> - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
> - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
> - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
> - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
> - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
> - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
> - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
> - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
> - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
> - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
> - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
> - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
> - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
> -
> -#endif
> diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
> deleted file mode 100644
> index de8fbd9..0000000
> --- a/configs/omap3_evm_defconfig
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_OMAP34XX=y
> -CONFIG_TARGET_OMAP3_EVM=y
> -CONFIG_SPL=y
> -# CONFIG_CMD_IMI is not set
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_FPGA is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SYS_PROMPT="OMAP3_EVM # "
> diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
> deleted file mode 100644
> index 7d15b16..0000000
> --- a/configs/omap3_evm_quick_mmc_defconfig
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_OMAP34XX=y
> -CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
> -CONFIG_SPL=y
> -# CONFIG_CMD_BDI is not set
> -# CONFIG_CMD_CONSOLE is not set
> -# CONFIG_CMD_BOOTD is not set
> -# CONFIG_CMD_RUN is not set
> -# CONFIG_CMD_IMI is not set
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_XIMG is not set
> -# CONFIG_CMD_EDITENV is not set
> -# CONFIG_CMD_SAVEENV is not set
> -# CONFIG_CMD_ENV_EXISTS is not set
> -# CONFIG_CMD_MEMORY is not set
> -# CONFIG_CMD_LOADB is not set
> -# CONFIG_CMD_LOADS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_FPGA is not set
> -# CONFIG_CMD_ECHO is not set
> -# CONFIG_CMD_ITEST is not set
> -# CONFIG_CMD_SOURCE is not set
> -# CONFIG_CMD_SETEXPR is not set
> -# CONFIG_CMD_NFS is not set
> -# CONFIG_CMD_MISC is not set
> -CONFIG_SYS_PROMPT="OMAP3_EVM # "
> diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
> deleted file mode 100644
> index cd30134..0000000
> --- a/configs/omap3_evm_quick_nand_defconfig
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_OMAP34XX=y
> -CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
> -CONFIG_SPL=y
> -# CONFIG_CMD_BDI is not set
> -# CONFIG_CMD_CONSOLE is not set
> -# CONFIG_CMD_BOOTD is not set
> -# CONFIG_CMD_RUN is not set
> -# CONFIG_CMD_IMI is not set
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_XIMG is not set
> -# CONFIG_CMD_EDITENV is not set
> -# CONFIG_CMD_SAVEENV is not set
> -# CONFIG_CMD_ENV_EXISTS is not set
> -# CONFIG_CMD_MEMORY is not set
> -# CONFIG_CMD_LOADB is not set
> -# CONFIG_CMD_LOADS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_FPGA is not set
> -# CONFIG_CMD_ECHO is not set
> -# CONFIG_CMD_ITEST is not set
> -# CONFIG_CMD_SOURCE is not set
> -# CONFIG_CMD_SETEXPR is not set
> -# CONFIG_CMD_NFS is not set
> -# CONFIG_CMD_MISC is not set
> -CONFIG_SYS_PROMPT="OMAP3_EVM # "
> diff --git a/doc/README.omap3 b/doc/README.omap3
> index e09ac03..d692374 100644
> --- a/doc/README.omap3
> +++ b/doc/README.omap3
> @@ -43,11 +43,6 @@ make
> make omap3_overo_config
> make
>
> -* TI EVM:
> -
> -make omap3_evm_config
> -make
> -
> * Pandora:
>
> make omap3_pandora_config
> diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c
> index 97da529..a61affc 100644
> --- a/drivers/usb/musb/omap3.c
> +++ b/drivers/usb/musb/omap3.c
> @@ -118,10 +118,6 @@ int musb_platform_init(void)
> stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
> writel(stdby, &otg->forcestdby);
>
> -#ifdef CONFIG_OMAP3_EVM
> - musb_cfg.extvbus = omap3_evm_need_extvbus();
> -#endif
> -
> #ifdef CONFIG_OMAP4430
> u32 *usbotghs_control =
> (u32 *)((*ctrl)->control_usbotghs_ctrl);
> diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h
> index ae645c7..b8a29e1 100644
> --- a/drivers/usb/musb/omap3.h
> +++ b/drivers/usb/musb/omap3.h
> @@ -32,8 +32,4 @@
>
> int musb_platform_init(void);
>
> -#ifdef CONFIG_OMAP3_EVM
> -extern u8 omap3_evm_need_extvbus(void);
> -#endif
> -
> #endif /* _MUSB_OMAP3_H */
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> deleted file mode 100644
> index 1dd71a8..0000000
> --- a/include/configs/omap3_evm.h
> +++ /dev/null
> @@ -1,154 +0,0 @@
> -/*
> - * Configuration settings for the TI OMAP3 EVM board.
> - *
> - * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * Author :
> - * Manikandan Pillai <mani.pillai@ti.com>
> - * Derived from Beagle Board and 3430 SDP code by
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Syed Mohammed Khasim <khasim@ti.com>
> - *
> - * Manikandan Pillai <mani.pillai@ti.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __OMAP3EVM_CONFIG_H
> -#define __OMAP3EVM_CONFIG_H
> -
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/omap.h>
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot commands
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_CMD_ASKENV
> -
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -#define CONFIG_CMD_JFFS2
> -
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_MMC
> -#define CONFIG_CMD_NAND
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot features
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_SYS_LONGHELP
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/* Display CPU and Board information */
> -#define CONFIG_DISPLAY_CPUINFO
> -#define CONFIG_DISPLAY_BOARDINFO
> -
> -/* Allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -/* Add auto-completion support */
> -#define CONFIG_AUTO_COMPLETE
> -
> -/* ----------------------------------------------------------------------------
> - * Supported hardware
> - * ----------------------------------------------------------------------------
> - */
> -
> -/* MMC */
> -#define CONFIG_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_OMAP_HSMMC
> -
> -/* SPL */
> -#define CONFIG_SPL_MMC_SUPPORT
> -#define CONFIG_SPL_FAT_SUPPORT
> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
> -
> -/* Partition tables */
> -#define CONFIG_EFI_PARTITION
> -#define CONFIG_DOS_PARTITION
> -
> -/* USB
> - *
> - * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
> - * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
> - */
> -#define CONFIG_USB_OMAP3
> -#define CONFIG_USB_MUSB_HCD
> -/* #define CONFIG_USB_MUSB_UDC */
> -
> -/* NAND SPL */
> -#define CONFIG_SPL_NAND_SIMPLE
> -#define CONFIG_SPL_NAND_SUPPORT
> -#define CONFIG_SPL_NAND_BASE
> -#define CONFIG_SPL_NAND_DRIVERS
> -#define CONFIG_SPL_NAND_ECC
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_PAGE_COUNT 64
> -#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> -#define CONFIG_SYS_NAND_OOBSIZE 64
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
> -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
> -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
> - 10, 11, 12, 13}
> -#define CONFIG_SYS_NAND_ECCSIZE 512
> -#define CONFIG_SYS_NAND_ECCBYTES 3
> -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
> -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
> -
> -/* -----------------------------------------------------------------------------
> - * Include common board configuration
> - * -----------------------------------------------------------------------------
> - */
> -#include "omap3_evm_common.h"
> -
> -/* -----------------------------------------------------------------------------
> - * Default environment
> - * -----------------------------------------------------------------------------
> - */
> -#define CONFIG_BOOTDELAY 3
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "loadaddr=0x82000000\0" \
> - "usbtty=cdc_acm\0" \
> - "mmcdev=0\0" \
> - "console=ttyO0,115200n8\0" \
> - "mmcargs=setenv bootargs console=${console} " \
> - "root=/dev/mmcblk0p2 rw " \
> - "rootfstype=ext3 rootwait\0" \
> - "nandargs=setenv bootargs console=${console} " \
> - "root=/dev/mtdblock4 rw " \
> - "rootfstype=jffs2\0" \
> - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> - "bootscript=echo Running bootscript from mmc ...; " \
> - "source ${loadaddr}\0" \
> - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
> - "mmcboot=echo Booting from mmc ...; " \
> - "run mmcargs; " \
> - "bootm ${loadaddr}\0" \
> - "nandboot=echo Booting from nand ...; " \
> - "run nandargs; " \
> - "onenand read ${loadaddr} 280000 400000; " \
> - "bootm ${loadaddr}\0" \
> -
> -#define CONFIG_BOOTCOMMAND \
> - "mmc dev ${mmcdev}; if mmc rescan; then " \
> - "if run loadbootscript; then " \
> - "run bootscript; " \
> - "else " \
> - "if run loaduimage; then " \
> - "run mmcboot; " \
> - "else run nandboot; " \
> - "fi; " \
> - "fi; " \
> - "else run nandboot; fi"
> -
> -#endif /* __OMAP3EVM_CONFIG_H */
> diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
> deleted file mode 100644
> index 7e7f6f2..0000000
> --- a/include/configs/omap3_evm_common.h
> +++ /dev/null
> @@ -1,289 +0,0 @@
> -/*
> - * Common configuration settings for the TI OMAP3 EVM board.
> - *
> - * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __OMAP3_EVM_COMMON_H
> -#define __OMAP3_EVM_COMMON_H
> -
> -/*
> - * High level configuration options
> - */
> -#define CONFIG_OMAP /* This is TI OMAP core */
> -#define CONFIG_OMAP_GPIO
> -#define CONFIG_OMAP_COMMON
> -/* Common ARM Erratas */
> -#define CONFIG_ARM_ERRATA_454179
> -#define CONFIG_ARM_ERRATA_430973
> -#define CONFIG_ARM_ERRATA_621766
> -
> -#define CONFIG_SDRC /* The chip has SDRC controller */
> -
> -#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
> -#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
> -
> -/*
> - * Clock related definitions
> - */
> -#define V_OSCK 26000000 /* Clock output from T2 */
> -#define V_SCLK (V_OSCK >> 1)
> -
> -/*
> - * OMAP3 has 12 GP timers, they can be driven by the system clock
> - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> - * This rate is divided by a local divisor.
> - */
> -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
> -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
> -
> -/* Size of environment - 128KB */
> -#define CONFIG_ENV_SIZE (128 << 10)
> -
> -/* Size of malloc pool */
> -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
> -
> -/*
> - * Physical Memory Map
> - * Note 1: CS1 may or may not be populated
> - * Note 2: SDRAM size is expected to be at least 32MB
> - */
> -#define CONFIG_NR_DRAM_BANKS 2
> -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> -
> -/* Limits for memtest */
> -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> - 0x01F00000) /* 31MB */
> -
> -/* Default load address */
> -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
> -
> -/* -----------------------------------------------------------------------------
> - * Hardware drivers
> - * -----------------------------------------------------------------------------
> - */
> -
> -/*
> - * NS16550 Configuration
> - */
> -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
> -
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> -
> -/*
> - * select serial console configuration
> - */
> -#define CONFIG_CONS_INDEX 1
> -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
> -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
> -#define CONFIG_BAUDRATE 115200
> -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
> - 115200}
> -
> -/*
> - * I2C
> - */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
> -#define CONFIG_SYS_I2C_OMAP34XX
> -
> -/*
> - * PISMO support
> - */
> -/* Monitor at start of flash - Reserve 2 sectors */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> -
> -#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> -
> -/* Start location & size of environment */
> -#define ONENAND_ENV_OFFSET 0x260000
> -#define SMNAND_ENV_OFFSET 0x260000
> -
> -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
> -
> -/*
> - * NAND
> - */
> -/* Physical address to access NAND */
> -#define CONFIG_SYS_NAND_ADDR NAND_BASE
> -
> -/* Physical address to access NAND at CS0 */
> -#define CONFIG_SYS_NAND_BASE NAND_BASE
> -
> -/* Max number of NAND devices */
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
> -/* Timeout values (in ticks) */
> -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
> -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
> -
> -/* Flash banks JFFS2 should use */
> -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
> - CONFIG_SYS_MAX_NAND_DEVICE)
> -
> -#define CONFIG_SYS_JFFS2_MEM_NAND
> -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
> -#define CONFIG_SYS_JFFS2_NUM_BANKS 1
> -
> -#define CONFIG_JFFS2_NAND
> -/* nand device jffs2 lives on */
> -#define CONFIG_JFFS2_DEV "nand0"
> -/* Start of jffs2 partition */
> -#define CONFIG_JFFS2_PART_OFFSET 0x680000
> -/* Size of jffs2 partition */
> -#define CONFIG_JFFS2_PART_SIZE 0xf980000
> -
> -/*
> - * USB
> - */
> -#ifdef CONFIG_USB_OMAP3
> -
> -#ifdef CONFIG_USB_MUSB_HCD
> -#define CONFIG_CMD_USB
> -
> -#define CONFIG_USB_STORAGE
> -#define CONGIG_CMD_STORAGE
> -#define CONFIG_CMD_FAT
> -
> -#ifdef CONFIG_USB_KEYBOARD
> -#define CONFIG_SYS_USB_EVENT_POLL
> -#define CONFIG_PREBOOT "usb start"
> -#endif /* CONFIG_USB_KEYBOARD */
> -
> -#endif /* CONFIG_USB_MUSB_HCD */
> -
> -#ifdef CONFIG_USB_MUSB_UDC
> -/* USB device configuration */
> -#define CONFIG_USB_DEVICE
> -#define CONFIG_USB_TTY
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -
> -/* Change these to suit your needs */
> -#define CONFIG_USBD_VENDORID 0x0451
> -#define CONFIG_USBD_PRODUCTID 0x5678
> -#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
> -#define CONFIG_USBD_PRODUCT_NAME "EVM"
> -#endif /* CONFIG_USB_MUSB_UDC */
> -
> -#endif /* CONFIG_USB_OMAP3 */
> -
> -/* ----------------------------------------------------------------------------
> - * U-boot features
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
> -
> -#define CONFIG_MISC_INIT_R
> -
> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_INITRD_TAG
> -#define CONFIG_REVISION_TAG
> -
> -/* Size of Console IO buffer */
> -#define CONFIG_SYS_CBSIZE 512
> -
> -/* Size of print buffer */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> - sizeof(CONFIG_SYS_PROMPT) + 16)
> -
> -/* Size of bootarg buffer */
> -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> -
> -#define CONFIG_BOOTFILE "uImage"
> -
> -/*
> - * NAND / OneNAND
> - */
> -#if defined(CONFIG_CMD_NAND)
> -#define CONFIG_SYS_FLASH_BASE NAND_BASE
> -
> -#define CONFIG_NAND_OMAP_GPMC
> -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
> -#elif defined(CONFIG_CMD_ONENAND)
> -#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
> -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
> -#endif
> -
> -#if !defined(CONFIG_ENV_IS_NOWHERE)
> -#if defined(CONFIG_CMD_NAND)
> -#define CONFIG_ENV_IS_IN_NAND
> -#elif defined(CONFIG_CMD_ONENAND)
> -#define CONFIG_ENV_IS_IN_ONENAND
> -#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
> -#endif
> -#endif /* CONFIG_ENV_IS_NOWHERE */
> -
> -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
> -
> -#if defined(CONFIG_CMD_NET)
> -
> -/* Ethernet (SMSC9115 from SMSC9118 family) */
> -#define CONFIG_SMC911X
> -#define CONFIG_SMC911X_32_BIT
> -#define CONFIG_SMC911X_BASE 0x2C000000
> -
> -/* BOOTP fields */
> -#define CONFIG_BOOTP_SUBNETMASK 0x00000001
> -#define CONFIG_BOOTP_GATEWAY 0x00000002
> -#define CONFIG_BOOTP_HOSTNAME 0x00000004
> -#define CONFIG_BOOTP_BOOTPATH 0x00000010
> -
> -#endif /* CONFIG_CMD_NET */
> -
> -/* Support for relocation */
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x800
> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
> - CONFIG_SYS_INIT_RAM_SIZE - \
> - GENERATED_GBL_DATA_SIZE)
> -
> -/* -----------------------------------------------------------------------------
> - * Board specific
> - * -----------------------------------------------------------------------------
> - */
> -#define CONFIG_SYS_NO_FLASH
> -
> -/* Uncomment to define the board revision statically */
> -/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
> -
> -#define CONFIG_SYS_CACHELINE_SIZE 64
> -
> -/* Defines for SPL */
> -#define CONFIG_SPL_FRAMEWORK
> -#define CONFIG_SPL_TEXT_BASE 0x40200800
> -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
> -
> -#define CONFIG_SPL_BSS_START_ADDR 0x80000000
> -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
> -
> -#define CONFIG_SPL_BOARD_INIT
> -#define CONFIG_SPL_LIBCOMMON_SUPPORT
> -#define CONFIG_SPL_LIBDISK_SUPPORT
> -#define CONFIG_SPL_I2C_SUPPORT
> -#define CONFIG_SPL_LIBGENERIC_SUPPORT
> -#define CONFIG_SPL_SERIAL_SUPPORT
> -#define CONFIG_SPL_POWER_SUPPORT
> -#define CONFIG_SPL_OMAP3_ID_NAND
> -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
> -
> -/*
> - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> - * 64 bytes before this address should be set aside for u-boot.img's
> - * header. That is 0x800FFFC0--0x80100000 should not be used for any
> - * other needs.
> - */
> -#define CONFIG_SYS_TEXT_BASE 0x80100000
> -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
> -
> -#endif /* __OMAP3_EVM_COMMON_H */
> diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
> deleted file mode 100644
> index 27cd9be..0000000
> --- a/include/configs/omap3_evm_quick_mmc.h
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -/*
> - * Configuration settings for quick boot from MMC on OMAP3 EVM.
> - *
> - * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * Author :
> - * Sanjeev Premi <premi@ti.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __OMAP3_EVM_QUICK_MMC_H
> -#define __OMAP3_EVM_QUICK_MMC_H
> -
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/omap.h>
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot commands
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_CMD_MMC
> -#define CONFIG_CMD_FAT
> -
> -/*
> - * Board revision is detected by probing the Ethernet chip.
> - *
> - * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
> - * this option can be removed. Generated binary is leaner by ~16Kbytes.
> - */
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot features
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_SILENT_CONSOLE
> -#define CONFIG_ENV_IS_NOWHERE
> -
> -/* ----------------------------------------------------------------------------
> - * Supported hardware
> - * ----------------------------------------------------------------------------
> - */
> -
> -/* MMC */
> -#define CONFIG_MMC
> -#define CONFIG_GENERIC_MMC
> -#define CONFIG_OMAP_HSMMC
> -#define CONFIG_DOS_PARTITION
> -
> -/* -----------------------------------------------------------------------------
> - * Include common board configuration
> - * -----------------------------------------------------------------------------
> - */
> -#include "omap3_evm_common.h"
> -
> -/* -----------------------------------------------------------------------------
> - * Default environment
> - * -----------------------------------------------------------------------------
> - */
> -#define CONFIG_BOOTDELAY 0
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "verify=no\0" \
> - "silent=1"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "mmc rescan 0; " \
> - "fatload mmc 0 0x82000000 uImage; " \
> - "bootm 0x82000000;"
> -
> -/*
> - * Update the bootargs as necessary e.g. size of memory, partition and fstype
> - */
> -#define CONFIG_BOOTARGS \
> - "quiet " \
> - "console=ttyO0,115200n8 " \
> - "mem=128M " \
> - "noinitrd " \
> - "root=/dev/mmcblk0p2 rw " \
> - "rootfstype=ext3 rootwait"
> -
> -/*
> - * SPL
> - */
> -#define CONFIG_SPL_MMC_SUPPORT
> -#define CONFIG_SPL_FAT_SUPPORT
> -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
> -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
> -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
> -
> -#endif /* __OMAP3_EVM_QUICK_MMC_H */
> diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
> deleted file mode 100644
> index 124e8c6..0000000
> --- a/include/configs/omap3_evm_quick_nand.h
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -/*
> - * Configuration settings for quick boot from NAND on OMAP3 EVM.
> - *
> - * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * Author :
> - * Sanjeev Premi <premi@ti.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef __OMAP3_EVM_QUICK_NAND_H
> -#define __OMAP3_EVM_QUICK_NAND_H
> -
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/omap.h>
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot commands
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_CMD_NAND
> -
> -/*
> - * Board revision is detected by probing the Ethernet chip.
> - *
> - * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
> - * this option can be removed. Generated binary is leaner by ~16Kbytes.
> - */
> -
> -/* ----------------------------------------------------------------------------
> - * Supported U-boot features
> - * ----------------------------------------------------------------------------
> - */
> -#define CONFIG_SILENT_CONSOLE
> -#define CONFIG_ENV_IS_NOWHERE
> -
> -/* -----------------------------------------------------------------------------
> - * Include common board configuration
> - * -----------------------------------------------------------------------------
> - */
> -#include "omap3_evm_common.h"
> -
> -/* -----------------------------------------------------------------------------
> - * Default environment
> - * -----------------------------------------------------------------------------
> - */
> -#define CONFIG_BOOTDELAY 0
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "verify=no\0" \
> - "silent=1"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "nandecc hw; " \
> - "nand read.i 0x80000000 280000 300000; " \
> - "bootm 0x80000000;"
> -
> -/*
> - * Update the bootargs as necessary e.g. size of memory, partition and fstype
> - */
> -#define CONFIG_BOOTARGS \
> - "quiet " \
> - "console=ttyO0,115200n8 " \
> - "mem=128M " \
> - "noinitrd " \
> - "root=/dev/mtdblock4 rw " \
> - "rootfstype=jffs2 "
> -
> -/*
> - * SPL
> - */
> -#define CONFIG_SPL_NAND_SIMPLE
> -#define CONFIG_SPL_NAND_SUPPORT
> -#define CONFIG_SPL_NAND_BASE
> -#define CONFIG_SPL_NAND_DRIVERS
> -#define CONFIG_SPL_NAND_ECC
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_PAGE_COUNT 64
> -#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> -#define CONFIG_SYS_NAND_OOBSIZE 64
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
> -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
> -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
> - 10, 11, 12, 13}
> -#define CONFIG_SYS_NAND_ECCSIZE 512
> -#define CONFIG_SYS_NAND_ECCBYTES 3
> -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
> -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
> -
> -#endif /* __OMAP3_EVM_QUICK_NAND_H */
> --
> 2.5.0.457.gab17608
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
--
balbi
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 14:50 ` Felipe Balbi
@ 2015-08-31 15:11 ` Tony Lindgren
2015-08-31 15:31 ` Simon Glass
0 siblings, 1 reply; 119+ messages in thread
From: Tony Lindgren @ 2015-08-31 15:11 UTC (permalink / raw)
To: u-boot
* Felipe Balbi <balbi@ti.com> [150831 07:54]:
> On Sun, Aug 30, 2015 at 07:19:35PM -0600, Simon Glass wrote:
> > This board has not been converted to generic board by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
>
> I have a feeling people still this too.
Yeah it seems this is too early for the removal.. Sorry no idea
who's going to do the conversion work though.
Regards,
Tony
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board
2015-08-31 14:50 ` Felipe Balbi
@ 2015-08-31 15:13 ` Tony Lindgren
2015-08-31 15:30 ` Simon Glass
1 sibling, 0 replies; 119+ messages in thread
From: Tony Lindgren @ 2015-08-31 15:13 UTC (permalink / raw)
To: u-boot
* Felipe Balbi <balbi@ti.com> [150831 07:54]:
> Hi,
>
> On Sun, Aug 30, 2015 at 07:19:37PM -0600, Simon Glass wrote:
> > This board has not been converted to generic board by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
>
> there are people using this and ti816x at least.
Yes and it seems people will be using dm81xx with mainline
kernel more..
Regards,
Tony
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board
2015-08-31 14:50 ` Felipe Balbi
2015-08-31 15:13 ` Tony Lindgren
@ 2015-08-31 15:30 ` Simon Glass
1 sibling, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 15:30 UTC (permalink / raw)
To: u-boot
Hi,
On 31 August 2015 at 08:50, Felipe Balbi <balbi@ti.com> wrote:
> Hi,
>
> On Sun, Aug 30, 2015 at 07:19:37PM -0600, Simon Glass wrote:
>> This board has not been converted to generic board by the deadline.
>> Remove it.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> there are people using this and ti816x at least.
OK - let's see if one of them can send a patch.
>
>> ---
>>
>> arch/arm/Kconfig | 6 --
>> board/ti/ti814x/Kconfig | 15 ---
>> board/ti/ti814x/MAINTAINERS | 6 --
>> board/ti/ti814x/Makefile | 13 ---
>> board/ti/ti814x/evm.c | 188 -----------------------------------
>> board/ti/ti814x/evm.h | 8 --
>> board/ti/ti814x/mux.c | 86 ----------------
>> configs/ti814x_evm_defconfig | 7 --
>> include/configs/ti814x_evm.h | 230 -------------------------------------------
>> 9 files changed, 559 deletions(-)
>> delete mode 100644 board/ti/ti814x/Kconfig
>> delete mode 100644 board/ti/ti814x/MAINTAINERS
>> delete mode 100644 board/ti/ti814x/Makefile
>> delete mode 100644 board/ti/ti814x/evm.c
>> delete mode 100644 board/ti/ti814x/evm.h
>> delete mode 100644 board/ti/ti814x/mux.c
>> delete mode 100644 configs/ti814x_evm_defconfig
>> delete mode 100644 include/configs/ti814x_evm.h
>>
Regards,
Simon
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 15:11 ` Tony Lindgren
@ 2015-08-31 15:31 ` Simon Glass
0 siblings, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-08-31 15:31 UTC (permalink / raw)
To: u-boot
Hi,
On 31 August 2015 at 09:11, Tony Lindgren <tony@atomide.com> wrote:
> * Felipe Balbi <balbi@ti.com> [150831 07:54]:
>> On Sun, Aug 30, 2015 at 07:19:35PM -0600, Simon Glass wrote:
>> > This board has not been converted to generic board by the deadline.
>> > Remove it.
>> >
>> > Signed-off-by: Simon Glass <sjg@chromium.org>
>>
>> I have a feeling people still this too.
>
> Yeah it seems this is too early for the removal.. Sorry no idea
> who's going to do the conversion work though.
Perhaps someone who is still using it?
Regards,
Simon
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board
2015-08-31 14:38 ` Tom Rini
@ 2015-08-31 15:59 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-08-31 15:59 UTC (permalink / raw)
To: u-boot
On Mon, Aug 31, 2015 at 10:38:04AM -0400, Tom Rini wrote:
> On Sun, Aug 30, 2015 at 07:19:35PM -0600, Simon Glass wrote:
>
> > This board has not been converted to generic board by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Acked-by: Tom Rini <trini@konsulko.com>
OK, after further poking:
Nacked-by: Tom Rini <trini@konsulko.com>
And I'll dig mine out, do the one line conversion and boot-test it.
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board
2015-08-31 1:19 ` [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board Simon Glass
2015-08-31 14:50 ` Felipe Balbi
@ 2015-08-31 16:05 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-08-31 16:05 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:37PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Nacked-by: Tom Rini <trini@konsulko.com>
And I'll dig mine out, patch and post.
--
Tom
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* [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board
2015-08-31 1:19 ` [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board Simon Glass
@ 2015-08-31 16:06 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-08-31 16:06 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:38PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Nacked-by: Tom Rini <trini@konsulko.com>
And one is getting sent to me shortly, I'll patch now and confirm once
the board gets here.
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards
2015-08-31 1:18 ` [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards Simon Glass
@ 2015-09-01 14:44 ` Stefano Babic
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Stefano Babic @ 2015-09-01 14:44 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 31/08/2015 03:18, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
> sffsdr, sonata.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-davinci/Kconfig | 36 ----
> board/davinci/dm355evm/Kconfig | 12 --
> board/davinci/dm355evm/MAINTAINERS | 6 -
> board/davinci/dm355evm/Makefile | 10 -
> board/davinci/dm355evm/config.mk | 11 -
> board/davinci/dm355evm/dm355evm.c | 144 -------------
> board/davinci/dm355leopard/Kconfig | 12 --
> board/davinci/dm355leopard/MAINTAINERS | 6 -
> board/davinci/dm355leopard/Makefile | 10 -
> board/davinci/dm355leopard/config.mk | 6 -
> board/davinci/dm355leopard/dm355leopard.c | 86 --------
> board/davinci/dm365evm/Kconfig | 12 --
> board/davinci/dm365evm/MAINTAINERS | 6 -
> board/davinci/dm365evm/Makefile | 10 -
> board/davinci/dm365evm/config.mk | 11 -
> board/davinci/dm365evm/dm365evm.c | 139 ------------
> board/davinci/dm6467evm/Kconfig | 12 --
> board/davinci/dm6467evm/MAINTAINERS | 7 -
> board/davinci/dm6467evm/Makefile | 10 -
> board/davinci/dm6467evm/config.mk | 2 -
> board/davinci/dm6467evm/dm6467evm.c | 76 -------
> board/davinci/dvevm/Kconfig | 12 --
> board/davinci/dvevm/MAINTAINERS | 6 -
> board/davinci/dvevm/Makefile | 11 -
> board/davinci/dvevm/board_init.S | 16 --
> board/davinci/dvevm/config.mk | 39 ----
> board/davinci/dvevm/dvevm.c | 91 --------
> board/davinci/ea20/Kconfig | 12 --
> board/davinci/ea20/MAINTAINERS | 6 -
> board/davinci/ea20/Makefile | 10 -
> board/davinci/ea20/ea20.c | 339 ------------------------------
Only for ea20:
I checked, and it makes sense to maintain this board - I send the patch
for moving to generic board.
Thanks,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
` (44 preceding siblings ...)
2015-08-31 1:19 ` [U-Boot] [PATCH 45/45] arm: Remove tx25 board Simon Glass
@ 2015-09-01 16:28 ` Masahiro Yamada
2015-09-09 18:07 ` Simon Glass
45 siblings, 1 reply; 119+ messages in thread
From: Masahiro Yamada @ 2015-09-01 16:28 UTC (permalink / raw)
To: u-boot
Hi Simon,
2015-08-31 10:18 GMT+09:00 Simon Glass <sjg@chromium.org>:
> The follow boards have still not been moved to use CONFIG_SYS_GENERIC_BOARD.
> This series removes these boards in preparation for dropping the old board
> init file arch/arm/lib/board.c:
>
> https://patchwork.ozlabs.org/patch/508559/
>
> balloon3, cpu9260, cpu9260_128M, cpu9260_nand, cpu9260_nand_128M, cpu9G20,
> cpu9G20_128M, cpu9G20_nand, cpu9G20_nand_128M, cpuat91, cpuat91_ram, d2net_v2,
> da830evm, davinci_dm355evm, davinci_dm355leopard, davinci_dm365evm,
> davinci_dm6467evm, davinci_dm6467Tevm, davinci_dvevm, davinci_schmoogie,
> davinci_sffsdr, davinci_sonata, dig297, ea20, eb_cpux9k2, eb_cpux9k2_ram,
> edb9315a, enbw_cmc, ima3-mx53, imx27lite, imx31_litekit, inetspace_v2, jornada,
> lp8x4x, magnesium, meesc, meesc_dataflash, mv88f6281gtw_ge, mx51_efikamx,
> mx51_efikasb, net2big_v2, netspace_lite_v2, netspace_max_v2, netspace_mini_v2,
> netspace_v2, nhk8815, nhk8815_onenand, omap3_evm, omap3_evm_quick_mmc,
> omap3_evm_quick_nand, omap3_logic, omap3_mvblx, omap3_sdp3430, openrd_base,
> openrd_client, openrd_ultimate, otc570, otc570_dataflash, palmld, palmtc,
> palmtreo680, polaris, portuxg20, pxa255_idp, qong, rd6281a, scb9328, snowball,
> stamp9g20, ti814x_evm, ti816x_evm, tk71, trizepsiv, tt01, tx25, u8500_href,
> versatileab, versatilepb, versatileqemu, vision2, vl_ma2sc, vl_ma2sc_ram,
> vpac270_nor_128, vpac270_nor_256, vpac270_ond_256, wireless_space, xaeniax,
> zipitz2
Thanks for working on this!
I guess you will resend v2 later because some people promised to
convert their boards.
When you send it next time, could you add entries to doc/README.scrapyard?
I think my series for PowerPC will be merged shortly.
Before you start your removal work,
please run scripts/fill_scrapyard.py
This tool will fill "Commit" and "Removed" fields for you.
Then, add entries for removed boards in each patch.
Thanks!
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for LaCie boards
2015-08-31 13:16 ` Simon Glass
2015-08-31 14:07 ` Albert ARIBAUD
@ 2015-09-01 17:01 ` Simon Guinot
2015-09-12 10:51 ` Simon Guinot
2015-09-13 13:56 ` [U-Boot] " Tom Rini
2015-09-02 12:07 ` [U-Boot] [PATCH 03/45] arm: Remove most " Simon Guinot
2 siblings, 2 replies; 119+ messages in thread
From: Simon Guinot @ 2015-09-01 17:01 UTC (permalink / raw)
To: u-boot
From: Simon Guinot <simon.guinot@sequanux.org>
This patch enables generic board support for the following
Kirkwood-based LaCie boards:
- Network Space v2 (Mini, Lite and Max).
- Internet Space v2.
- D2 Network v2.
- 2Big Network v2.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
---
include/configs/lacie_kw.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 30810d375297..7f63ae0d2228 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -8,6 +8,11 @@
#define _CONFIG_LACIE_KW_H
/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
* Machine number definition
*/
#if defined(CONFIG_INETSPACE_V2)
--
2.1.4
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-08-31 13:16 ` Simon Glass
2015-08-31 14:07 ` Albert ARIBAUD
2015-09-01 17:01 ` [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for " Simon Guinot
@ 2015-09-02 12:07 ` Simon Guinot
2015-09-02 13:08 ` Tom Rini
2 siblings, 1 reply; 119+ messages in thread
From: Simon Guinot @ 2015-09-02 12:07 UTC (permalink / raw)
To: u-boot
On Mon, Aug 31, 2015 at 07:16:16AM -0600, Simon Glass wrote:
> Hi Simon,
>
> On 31 August 2015 at 01:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> > On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> >> These boards have not been converted to generic board by the deadline.
> >> Remove all except edmini_v2 (which has been converted).
> >
> > Hi Simon,
> >
> > Great... Is it still time to convert this boards to "generic board"
> > support ?
>
> Yes if you are quick - please see doc/README.generic-board which has
> instructions. It should be very simple.
OK. It is done.
>
> >
> > You know, a direct email (I mean with my email address in the To or Cc
> > fields) to make me aware of this project would have been both fair and
> > very appreciated.
>
> OK well I'm sorry you haven't seen anything up until now. I wonder if
> we should cc all the maintainers when we have an announcement that
> affects their boards. There are a lot of maintainers though!
The result of the current process is a patch series which removes
support for a _lot_ of boards. It can't be correct. Moreover the
conversion work consists in adding a single define. I think it would
be far better to add the missing define for all this boards rather
than kicking them out.
>
> It is probably worth checking in every now and then to see what is going on.
Sure.
Simon
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* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-09-02 12:07 ` [U-Boot] [PATCH 03/45] arm: Remove most " Simon Guinot
@ 2015-09-02 13:08 ` Tom Rini
2015-09-02 15:51 ` Simon Guinot
0 siblings, 1 reply; 119+ messages in thread
From: Tom Rini @ 2015-09-02 13:08 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 02:07:41PM +0200, Simon Guinot wrote:
> On Mon, Aug 31, 2015 at 07:16:16AM -0600, Simon Glass wrote:
> > Hi Simon,
> >
> > On 31 August 2015 at 01:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> > > On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> > >> These boards have not been converted to generic board by the deadline.
> > >> Remove all except edmini_v2 (which has been converted).
> > >
> > > Hi Simon,
> > >
> > > Great... Is it still time to convert this boards to "generic board"
> > > support ?
> >
> > Yes if you are quick - please see doc/README.generic-board which has
> > instructions. It should be very simple.
>
> OK. It is done.
>
> >
> > >
> > > You know, a direct email (I mean with my email address in the To or Cc
> > > fields) to make me aware of this project would have been both fair and
> > > very appreciated.
> >
> > OK well I'm sorry you haven't seen anything up until now. I wonder if
> > we should cc all the maintainers when we have an announcement that
> > affects their boards. There are a lot of maintainers though!
>
> The result of the current process is a patch series which removes
> support for a _lot_ of boards. It can't be correct. Moreover the
> conversion work consists in adding a single define. I think it would
> be far better to add the missing define for all this boards rather
> than kicking them out.
So, I understand your frustration. I thought we had sent out an email
or two to board maintainers at various points about this conversion
(which has been going on for over 2 years, and a single line change for
at least a year, pretty much everywhere) but it looks like some boards
slipped through the cracks and didn't get emailed.
But it's also been a bit over 2 years and I'm pretty sure that at least
3 or 4 times in my release emails I've said "we're going to delete
boards that aren't converted, please convert and test!".
So yes, Simon first made a series to blind-convert the straglers but
then we decided to delete instead as this is a good test for how
interested people are in the hardware and if we can drop some code that
will make other conversions which are going on now easier too.
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards
2015-09-02 13:08 ` Tom Rini
@ 2015-09-02 15:51 ` Simon Guinot
0 siblings, 0 replies; 119+ messages in thread
From: Simon Guinot @ 2015-09-02 15:51 UTC (permalink / raw)
To: u-boot
On Wed, Sep 02, 2015 at 09:08:48AM -0400, Tom Rini wrote:
> On Wed, Sep 02, 2015 at 02:07:41PM +0200, Simon Guinot wrote:
> > On Mon, Aug 31, 2015 at 07:16:16AM -0600, Simon Glass wrote:
> > > Hi Simon,
> > >
> > > On 31 August 2015 at 01:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> > > > On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> > > >> These boards have not been converted to generic board by the deadline.
> > > >> Remove all except edmini_v2 (which has been converted).
> > > >
> > > > Hi Simon,
> > > >
> > > > Great... Is it still time to convert this boards to "generic board"
> > > > support ?
> > >
> > > Yes if you are quick - please see doc/README.generic-board which has
> > > instructions. It should be very simple.
> >
> > OK. It is done.
> >
> > >
> > > >
> > > > You know, a direct email (I mean with my email address in the To or Cc
> > > > fields) to make me aware of this project would have been both fair and
> > > > very appreciated.
> > >
> > > OK well I'm sorry you haven't seen anything up until now. I wonder if
> > > we should cc all the maintainers when we have an announcement that
> > > affects their boards. There are a lot of maintainers though!
> >
> > The result of the current process is a patch series which removes
> > support for a _lot_ of boards. It can't be correct. Moreover the
> > conversion work consists in adding a single define. I think it would
> > be far better to add the missing define for all this boards rather
> > than kicking them out.
>
> So, I understand your frustration. I thought we had sent out an email
> or two to board maintainers at various points about this conversion
> (which has been going on for over 2 years, and a single line change for
> at least a year, pretty much everywhere) but it looks like some boards
> slipped through the cracks and didn't get emailed.
>
> But it's also been a bit over 2 years and I'm pretty sure that at least
> 3 or 4 times in my release emails I've said "we're going to delete
> boards that aren't converted, please convert and test!".
>
> So yes, Simon first made a series to blind-convert the straglers but
> then we decided to delete instead as this is a good test for how
> interested people are in the hardware and if we can drop some code that
> will make other conversions which are going on now easier too.
I understand. Thanks for the explanation.
Simon
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init
2015-09-01 16:28 ` [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Masahiro Yamada
@ 2015-09-09 18:07 ` Simon Glass
0 siblings, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-09-09 18:07 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Tuesday, 1 September 2015, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
>
> Hi Simon,
>
>
> 2015-08-31 10:18 GMT+09:00 Simon Glass <sjg@chromium.org>:
> > The follow boards have still not been moved to use CONFIG_SYS_GENERIC_BOARD.
> > This series removes these boards in preparation for dropping the old board
> > init file arch/arm/lib/board.c:
> >
> > https://patchwork.ozlabs.org/patch/508559/
> >
> > balloon3, cpu9260, cpu9260_128M, cpu9260_nand, cpu9260_nand_128M, cpu9G20,
> > cpu9G20_128M, cpu9G20_nand, cpu9G20_nand_128M, cpuat91, cpuat91_ram, d2net_v2,
> > da830evm, davinci_dm355evm, davinci_dm355leopard, davinci_dm365evm,
> > davinci_dm6467evm, davinci_dm6467Tevm, davinci_dvevm, davinci_schmoogie,
> > davinci_sffsdr, davinci_sonata, dig297, ea20, eb_cpux9k2, eb_cpux9k2_ram,
> > edb9315a, enbw_cmc, ima3-mx53, imx27lite, imx31_litekit, inetspace_v2, jornada,
> > lp8x4x, magnesium, meesc, meesc_dataflash, mv88f6281gtw_ge, mx51_efikamx,
> > mx51_efikasb, net2big_v2, netspace_lite_v2, netspace_max_v2, netspace_mini_v2,
> > netspace_v2, nhk8815, nhk8815_onenand, omap3_evm, omap3_evm_quick_mmc,
> > omap3_evm_quick_nand, omap3_logic, omap3_mvblx, omap3_sdp3430, openrd_base,
> > openrd_client, openrd_ultimate, otc570, otc570_dataflash, palmld, palmtc,
> > palmtreo680, polaris, portuxg20, pxa255_idp, qong, rd6281a, scb9328, snowball,
> > stamp9g20, ti814x_evm, ti816x_evm, tk71, trizepsiv, tt01, tx25, u8500_href,
> > versatileab, versatilepb, versatileqemu, vision2, vl_ma2sc, vl_ma2sc_ram,
> > vpac270_nor_128, vpac270_nor_256, vpac270_ond_256, wireless_space, xaeniax,
> > zipitz2
>
>
> Thanks for working on this!
>
> I guess you will resend v2 later because some people promised to
> convert their boards.
>
> When you send it next time, could you add entries to doc/README.scrapyard?
>
>
> I think my series for PowerPC will be merged shortly.
>
>
> Before you start your removal work,
> please run scripts/fill_scrapyard.py
> This tool will fill "Commit" and "Removed" fields for you.
>
> Then, add entries for removed boards in each patch.
How do you want to handle this? I can respin the patch once people are
finished converting boards, but I'd prefer to only do it once!
>
>
> Thanks!
>
>
> --
> Best Regards
> Masahiro Yamada
Regards,
Simon
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot, 1/1] arm: at91: convert meesc board to generic board
2015-08-31 5:32 ` [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board Daniel Gorsulowski
2015-08-31 13:22 ` Simon Glass
@ 2015-09-11 7:38 ` Andreas Bießmann
1 sibling, 0 replies; 119+ messages in thread
From: Andreas Bießmann @ 2015-09-11 7:38 UTC (permalink / raw)
To: u-boot
Dear Daniel Gorsulowski,
Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu> writes:
>Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
>Reviewed-by: Simon Glass <sjg@chromium.org>
>[fix corrupt line wraps in patch]
>Signed-off-by: Andreas Bie?mann <andreas.devel@googlemail.com>
>---
> include/configs/meesc.h | 2 ++
> 1 file changed, 2 insertions(+)
applied to u-boot-atmel/master, thanks!
Fixed patch while applying.
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for LaCie boards
2015-09-01 17:01 ` [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for " Simon Guinot
@ 2015-09-12 10:51 ` Simon Guinot
2015-09-12 16:34 ` Simon Glass
2015-09-13 13:56 ` [U-Boot] " Tom Rini
1 sibling, 1 reply; 119+ messages in thread
From: Simon Guinot @ 2015-09-12 10:51 UTC (permalink / raw)
To: u-boot
On Tue, Sep 01, 2015 at 07:01:02PM +0200, Simon Guinot wrote:
> From: Simon Guinot <simon.guinot@sequanux.org>
>
> This patch enables generic board support for the following
> Kirkwood-based LaCie boards:
>
> - Network Space v2 (Mini, Lite and Max).
> - Internet Space v2.
> - D2 Network v2.
> - 2Big Network v2.
Hi Luka and Prafulla,
Please, consider to apply this patch.
Thanks,
Simon
>
> Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
> ---
> include/configs/lacie_kw.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
> index 30810d375297..7f63ae0d2228 100644
> --- a/include/configs/lacie_kw.h
> +++ b/include/configs/lacie_kw.h
> @@ -8,6 +8,11 @@
> #define _CONFIG_LACIE_KW_H
>
> /*
> + * Generic board support
> + */
> +#define CONFIG_SYS_GENERIC_BOARD
> +
> +/*
> * Machine number definition
> */
> #if defined(CONFIG_INETSPACE_V2)
> --
> 2.1.4
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* [U-Boot] [U-Boot,01/45] arm: Remove balloon3 board
2015-08-31 1:18 ` [U-Boot] [PATCH 01/45] arm: Remove balloon3 board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:18:55PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,02/45] arm: Remove eukrea boards
2015-08-31 1:18 ` [U-Boot] [PATCH 02/45] arm: Remove eukrea boards Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:18:56PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove all cpu9260 and cpuat91 boards.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 04/45] arm: Remove snowball and u8500_href boards
2015-08-31 1:18 ` [U-Boot] [PATCH 04/45] arm: Remove snowball and u8500_href boards Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:18:58PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 05/45] arm: Remove unmaintained davinci boards
2015-08-31 1:18 ` [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards Simon Glass
2015-09-01 14:44 ` Stefano Babic
@ 2015-09-12 12:48 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:18:59PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
> sffsdr, sonata.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
After keeping ea20, applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,06/45] arm: Remove d2net_v2 defconfig file
2015-08-31 1:19 ` [U-Boot] [PATCH 06/45] arm: Remove d2net_v2 defconfig file Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:00PM -0600, Simon Glass wrote:
> This file appears to be an orphan with no board files. Drop it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,07/45] arm: Remove dig297 board
2015-08-31 1:19 ` [U-Boot] [PATCH 07/45] arm: Remove dig297 board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:01PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards
2015-08-31 1:19 ` [U-Boot] [PATCH 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:02PM -0600, Simon Glass wrote:
> These board have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,10/45] arm: Remove enbw_cmc board
2015-08-31 1:19 ` [U-Boot] [PATCH 10/45] arm: Remove enbw_cmc board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:04PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,11/45] arm: Remove ima3-mx53 board
2015-08-31 1:19 ` [U-Boot] [PATCH 11/45] arm: Remove ima3-mx53 board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:05PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards
2015-08-31 1:19 ` [U-Boot] [PATCH 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:06PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,13/45] arm: Remove mx31_litekit board
2015-08-31 1:19 ` [U-Boot] [PATCH 13/45] arm: Remove mx31_litekit board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:07PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,14/45] arm: Remove inetspace_v2_cmc board
2015-08-31 1:19 ` [U-Boot] [PATCH 14/45] arm: Remove inetspace_v2_cmc board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:08PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,15/45] arm: Remove jornada board
2015-08-31 1:19 ` [U-Boot] [PATCH 15/45] arm: Remove jornada board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:09PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,16/45] arm: Remove lp8x4x board
2015-08-31 1:19 ` [U-Boot] [PATCH 16/45] arm: Remove lp8x4x board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:10PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,18/45] arm: Remove mv88f6281gtw_ge board
2015-08-31 1:19 ` [U-Boot] [PATCH 18/45] arm: Remove mv88f6281gtw_ge board Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:12PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot, 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards
2015-08-31 1:19 ` [U-Boot] [PATCH 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards Simon Glass
@ 2015-09-12 12:48 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:48 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:13PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot, 20/45] arm: Remove nhk8815 boards and nomadik arch
2015-08-31 1:19 ` [U-Boot] [PATCH 20/45] arm: Remove nhk8815 boards and nomadik arch Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:14PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,22/45] arm: Remove omap3_mvblx board
2015-08-31 1:19 ` [U-Boot] [PATCH 22/45] arm: Remove omap3_mvblx board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:16PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,23/45] arm: Remove omap3_sdp3430 board
2015-08-31 1:19 ` [U-Boot] [PATCH 23/45] arm: Remove omap3_sdp3430 board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:17PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,24/45] arm: Remove openrd boards
2015-08-31 1:19 ` [U-Boot] [PATCH 24/45] arm: Remove openrd boards Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:18PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,25/45] arm: Remove otc570 board
2015-08-31 1:19 ` [U-Boot] [PATCH 25/45] arm: Remove otc570 board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:19PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,26/45] arm: Remove palmld board
2015-08-31 1:19 ` [U-Boot] [PATCH 26/45] arm: Remove palmld board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:20PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,27/45] arm: Remove palmtc board
2015-08-31 1:19 ` [U-Boot] [PATCH 27/45] arm: Remove palmtc board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:21PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot, 28/45] arm: Remove polaris and trizepsiv boards
2015-08-31 1:19 ` [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards Simon Glass
2015-08-31 6:41 ` Stefano Babic
@ 2015-09-12 12:49 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:22PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Stefano Babic <sbabic@denx.de>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot, 29/45] arm: Remove portuxg20, stamp9g20 boards
2015-08-31 1:19 ` [U-Boot] [PATCH 29/45] arm: Remove portuxg20, stamp9g20 boards Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:23PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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* [U-Boot] [U-Boot,30/45] arm: Remove pxa255_idp, zipitz2 boards
2015-08-31 1:19 ` [U-Boot] [PATCH 30/45] arm: Remove pxa255_idp, zipitz2 boards Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:24PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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* [U-Boot] [U-Boot,31/45] arm: Remove qong board
2015-08-31 1:19 ` [U-Boot] [PATCH 31/45] arm: Remove qong board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:25PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,32/45] arm: Remove rd6281a board
2015-08-31 1:19 ` [U-Boot] [PATCH 32/45] arm: Remove rd6281a board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:26PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,33/45] arm: Remove scb9328 board
2015-08-31 1:19 ` [U-Boot] [PATCH 33/45] arm: Remove scb9328 board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:27PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,34/45] arm: Remove tk71 board
2015-08-31 1:19 ` [U-Boot] [PATCH 34/45] arm: Remove tk71 board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:28PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,35/45] arm: Remove tt01 board
2015-08-31 1:19 ` [U-Boot] [PATCH 35/45] arm: Remove tt01 board Simon Glass
@ 2015-09-12 12:49 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:49 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:29PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,36/45] arm: Remove versatileab board
2015-08-31 1:19 ` [U-Boot] [PATCH 36/45] arm: Remove versatileab board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:30PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,37/45] arm: Remove vision2 board
2015-08-31 1:19 ` [U-Boot] [PATCH 37/45] arm: Remove vision2 board Simon Glass
2015-08-31 6:40 ` Stefano Babic
@ 2015-09-12 12:50 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:31PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Stefano Babic <sbabic@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,38/45] arm: Remove vl_ma2sc board
2015-08-31 1:19 ` [U-Boot] [PATCH 38/45] arm: Remove vl_ma2sc board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:32PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,39/45] arm: Remove vpac270_nor_128 board
2015-08-31 1:19 ` [U-Boot] [PATCH 39/45] arm: Remove vpac270_nor_128 board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:33PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,40/45] arm: Remove xaeniax board
2015-08-31 1:19 ` [U-Boot] [PATCH 40/45] arm: Remove xaeniax board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:34PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,42/45] arm: Remove palmtreo680 board
2015-08-31 1:19 ` [U-Boot] [PATCH 42/45] arm: Remove palmtreo680 board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:36PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [U-Boot,45/45] arm: Remove tx25 board
2015-08-31 1:19 ` [U-Boot] [PATCH 45/45] arm: Remove tx25 board Simon Glass
@ 2015-09-12 12:50 ` Tom Rini
0 siblings, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-12 12:50 UTC (permalink / raw)
To: u-boot
On Sun, Aug 30, 2015 at 07:19:39PM -0600, Simon Glass wrote:
> This board has not been converted to generic board by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for LaCie boards
2015-09-12 10:51 ` Simon Guinot
@ 2015-09-12 16:34 ` Simon Glass
0 siblings, 0 replies; 119+ messages in thread
From: Simon Glass @ 2015-09-12 16:34 UTC (permalink / raw)
To: u-boot
+Tom
On 12 September 2015 at 03:51, Simon Guinot <simon.guinot@sequanux.org> wrote:
> On Tue, Sep 01, 2015 at 07:01:02PM +0200, Simon Guinot wrote:
>> From: Simon Guinot <simon.guinot@sequanux.org>
>>
>> This patch enables generic board support for the following
>> Kirkwood-based LaCie boards:
>>
>> - Network Space v2 (Mini, Lite and Max).
>> - Internet Space v2.
>> - D2 Network v2.
>> - 2Big Network v2.
>
> Hi Luka and Prafulla,
>
> Please, consider to apply this patch.
>
> Thanks,
>
> Simon
>
>>
>> Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
>> ---
>> include/configs/lacie_kw.h | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
>> index 30810d375297..7f63ae0d2228 100644
>> --- a/include/configs/lacie_kw.h
>> +++ b/include/configs/lacie_kw.h
>> @@ -8,6 +8,11 @@
>> #define _CONFIG_LACIE_KW_H
>>
>> /*
>> + * Generic board support
>> + */
>> +#define CONFIG_SYS_GENERIC_BOARD
>> +
>> +/*
>> * Machine number definition
>> */
>> #if defined(CONFIG_INETSPACE_V2)
Reviewed-by: Simon Glass <sjg@chromium.org>
build-tested:
Tested-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 119+ messages in thread
* [U-Boot] ARM: Kirkwood: enable generic board support for LaCie boards
2015-09-01 17:01 ` [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for " Simon Guinot
2015-09-12 10:51 ` Simon Guinot
@ 2015-09-13 13:56 ` Tom Rini
1 sibling, 0 replies; 119+ messages in thread
From: Tom Rini @ 2015-09-13 13:56 UTC (permalink / raw)
To: u-boot
On Tue, Sep 01, 2015 at 07:01:02PM +0200, Simon Guinot wrote:
> From: Simon Guinot <simon.guinot@sequanux.org>
>
> This patch enables generic board support for the following
> Kirkwood-based LaCie boards:
>
> - Network Space v2 (Mini, Lite and Max).
> - Internet Space v2.
> - D2 Network v2.
> - 2Big Network v2.
>
> Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
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end of thread, other threads:[~2015-09-13 13:56 UTC | newest]
Thread overview: 119+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-31 1:18 [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Simon Glass
2015-08-31 1:18 ` [U-Boot] [PATCH 01/45] arm: Remove balloon3 board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,01/45] " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 02/45] arm: Remove eukrea boards Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,02/45] " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 03/45] arm: Remove most LaCie boards Simon Glass
2015-08-31 7:51 ` Simon Guinot
2015-08-31 13:16 ` Simon Glass
2015-08-31 14:07 ` Albert ARIBAUD
2015-09-01 17:01 ` [U-Boot] [PATCH] ARM: Kirkwood: enable generic board support for " Simon Guinot
2015-09-12 10:51 ` Simon Guinot
2015-09-12 16:34 ` Simon Glass
2015-09-13 13:56 ` [U-Boot] " Tom Rini
2015-09-02 12:07 ` [U-Boot] [PATCH 03/45] arm: Remove most " Simon Guinot
2015-09-02 13:08 ` Tom Rini
2015-09-02 15:51 ` Simon Guinot
2015-08-31 1:18 ` [U-Boot] [PATCH 04/45] arm: Remove snowball and u8500_href boards Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:18 ` [U-Boot] [PATCH 05/45] arm: Remove unmaintained davinci boards Simon Glass
2015-09-01 14:44 ` Stefano Babic
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 06/45] arm: Remove d2net_v2 defconfig file Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,06/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 07/45] arm: Remove dig297 board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,07/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 08/45] arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boards Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 09/45] arm: Remove edb9315a board Simon Glass
2015-08-31 7:38 ` sergey kostanbaev
2015-08-31 13:13 ` Simon Glass
2015-08-31 1:19 ` [U-Boot] [PATCH 10/45] arm: Remove enbw_cmc board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,10/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 11/45] arm: Remove ima3-mx53 board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,11/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 12/45] arm: Remove imx27lite, imx27_litekit and magnesium boards Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 13/45] arm: Remove mx31_litekit board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,13/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 14/45] arm: Remove inetspace_v2_cmc board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,14/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 15/45] arm: Remove jornada board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,15/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 16/45] arm: Remove lp8x4x board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,16/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 17/45] arm: Remove meesc and meesc_dataflash boards Simon Glass
2015-08-31 5:30 ` Daniel Gorsulowski
2015-08-31 5:32 ` [U-Boot] [PATCH 1/1] arm: at91: convert meesc board to generic board Daniel Gorsulowski
2015-08-31 13:22 ` Simon Glass
2015-09-11 7:38 ` [U-Boot] [U-Boot, " Andreas Bießmann
2015-08-31 1:19 ` [U-Boot] [PATCH 18/45] arm: Remove mv88f6281gtw_ge board Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot,18/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 19/45] arm: Remove mx51_efikamx, mx51_efikasb boards Simon Glass
2015-09-12 12:48 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 20/45] arm: Remove nhk8815 boards and nomadik arch Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 21/45] arm: Remove omap3_logic board Simon Glass
2015-08-31 13:47 ` Adam Ford
2015-08-31 13:54 ` Simon Glass
2015-08-31 13:59 ` Tom Rini
2015-08-31 14:00 ` Adam Ford
2015-08-31 1:19 ` [U-Boot] [PATCH 22/45] arm: Remove omap3_mvblx board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,22/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 23/45] arm: Remove omap3_sdp3430 board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,23/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 24/45] arm: Remove openrd boards Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,24/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 25/45] arm: Remove otc570 board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,25/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 26/45] arm: Remove palmld board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,26/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 27/45] arm: Remove palmtc board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,27/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 28/45] arm: Remove polaris and trizepsiv boards Simon Glass
2015-08-31 6:41 ` Stefano Babic
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 29/45] arm: Remove portuxg20, stamp9g20 boards Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 30/45] arm: Remove pxa255_idp, zipitz2 boards Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,30/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 31/45] arm: Remove qong board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,31/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 32/45] arm: Remove rd6281a board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,32/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 33/45] arm: Remove scb9328 board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,33/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 34/45] arm: Remove tk71 board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,34/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 35/45] arm: Remove tt01 board Simon Glass
2015-09-12 12:49 ` [U-Boot] [U-Boot,35/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 36/45] arm: Remove versatileab board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,36/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 37/45] arm: Remove vision2 board Simon Glass
2015-08-31 6:40 ` Stefano Babic
2015-09-12 12:50 ` [U-Boot] [U-Boot,37/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 38/45] arm: Remove vl_ma2sc board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,38/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 39/45] arm: Remove vpac270_nor_128 board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,39/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 40/45] arm: Remove xaeniax board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,40/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 41/45] arm: Remove omap3_evm board Simon Glass
2015-08-31 14:38 ` Tom Rini
2015-08-31 15:59 ` Tom Rini
2015-08-31 14:50 ` Felipe Balbi
2015-08-31 15:11 ` Tony Lindgren
2015-08-31 15:31 ` Simon Glass
2015-08-31 1:19 ` [U-Boot] [PATCH 42/45] arm: Remove palmtreo680 board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,42/45] " Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 43/45] arm: Remove ti814x_evm board Simon Glass
2015-08-31 14:50 ` Felipe Balbi
2015-08-31 15:13 ` Tony Lindgren
2015-08-31 15:30 ` Simon Glass
2015-08-31 16:05 ` Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 44/45] arm: Remove ti816x_evm board Simon Glass
2015-08-31 16:06 ` Tom Rini
2015-08-31 1:19 ` [U-Boot] [PATCH 45/45] arm: Remove tx25 board Simon Glass
2015-09-12 12:50 ` [U-Boot] [U-Boot,45/45] " Tom Rini
2015-09-01 16:28 ` [U-Boot] [PATCH 00/45] arm: Remove boards that have not moved to generic board init Masahiro Yamada
2015-09-09 18:07 ` Simon Glass
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.