* [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9
@ 2015-08-23 12:22 Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
` (4 more replies)
0 siblings, 5 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
Patch 1: On BXT, forcewake ACK is taking time more than 2ms sometimes. Setting it
to recommanded value of 50ms. This is maximum timeout limit.
Patch 2: On GT CPD Exit CS behavior is leading to hangs on BXT A0/A1. WA is to
disable turbo and frequency requests.
Patch 3 and Patch 4:
WaRsDisableCoarsePowerGating is applicable to Gen9 platforms with revision
prior to BXT B0 and until SKL E0. Per this WA, both render and media PG need to
be disabled. Due to this only blitter forcewake need to be used for all GT accesses.
Patch 5: When GuC is enabled, it need to be informed about status of Coarse Power
Gating (CPG) for GuC to know when to forcewake render/media domains.
Alex Dai (1):
drm/i915: Notify Coarse Power Gating changes to GuC
Sagar Arun Kamble (4):
drm/i915: Increase maximum polling time to 50ms for forcewake
request/clear ack
drm/i915/bxt: WaGsvDisableTurbo
drm/i915: WaRsDisableCoarsePowerGating
drm/i915: Use only blitter forcewake
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_guc_submission.c | 18 ++++++++++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++---
drivers/gpu/drm/i915/intel_uncore.c | 55 ++++++++++++++++++++++++------
6 files changed, 93 insertions(+), 16 deletions(-)
--
1.9.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
@ 2015-08-23 12:22 ` Sagar Arun Kamble
2015-08-26 9:26 ` Daniel Vetter
2015-09-21 16:43 ` Yu Dai
2015-08-23 12:22 ` [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
` (3 subsequent siblings)
4 siblings, 2 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
Polling for 50ms is recommended to avoid these timeouts.
Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9d3c2e4..2df03b1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -27,7 +27,7 @@
#include <linux/pm_runtime.h>
-#define FORCEWAKE_ACK_TIMEOUT_MS 2
+#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
@ 2015-08-23 12:22 ` Sagar Arun Kamble
2015-09-11 6:23 ` Kamble, Sagar A
2015-09-21 16:43 ` Yu Dai
2015-08-23 12:22 ` [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
` (2 subsequent siblings)
4 siblings, 2 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..75f1c8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4450,6 +4450,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+ if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
+ return;
+
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
WARN_ON(val > dev_priv->rps.max_freq);
WARN_ON(val < dev_priv->rps.min_freq);
@@ -4770,6 +4774,12 @@ static void gen9_enable_rps(struct drm_device *dev)
gen6_init_rps_frequencies(dev);
+ /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+ if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ return;
+ }
+
/* Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RC_VIDEO_FREQ,
GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
@ 2015-08-23 12:22 ` Sagar Arun Kamble
2015-09-11 6:22 ` Kamble, Sagar A
2015-09-21 16:43 ` [PATCH 3/5] " Yu Dai
2015-08-23 12:22 ` [PATCH 4/5] drm/i915: Use only blitter forcewake Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC Sagar Arun Kamble
4 siblings, 2 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and till SKL E0.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75f1c8c..c0345d2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4840,11 +4840,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
/*
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
- * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+ * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
*/
- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- GEN9_MEDIA_PG_ENABLE : 0);
-
+ if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+ (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+ I915_WRITE(GEN9_PG_ENABLE, 0);
+ else
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
` (2 preceding siblings ...)
2015-08-23 12:22 ` [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
@ 2015-08-23 12:22 ` Sagar Arun Kamble
2015-08-23 12:30 ` Chris Wilson
2015-09-11 13:37 ` Ville Syrjälä
2015-08-23 12:22 ` [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC Sagar Arun Kamble
4 siblings, 2 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
Coarse power gating is disabled prior to BXT B0 and till SKL E0,
hence even for render and media well registers blitter forcewake request
need to be used.
Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++-------
3 files changed, 48 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a28de5..8eea452 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1509,7 +1509,10 @@ static int gen6_drpc_info(struct seq_file *m)
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->uncore.lock);
- forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
+ if (use_blitter_forcewake(dev))
+ forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_BLITTER].wake_count;
+ else
+ forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
spin_unlock_irq(&dev_priv->uncore.lock);
if (forcewake_count) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0f3f05..c127175 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2691,6 +2691,7 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
+bool use_blitter_forcewake(struct drm_device *dev);
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
enum forcewake_domains domains);
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2df03b1..b7b6612 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -63,6 +63,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
return "unknown";
}
+bool use_blitter_forcewake(struct drm_device *dev)
+{
+ /*
+ * Due to WaRsDisableCoarsePowerGating, Only blitter forcewake need to
+ * be used on platforms previous to BXT B0 and until SKL E0.
+ */
+ if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+ (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+ return true;
+ else
+ return false;
+}
+
static void
assert_device_not_suspended(struct drm_i915_private *dev_priv)
{
@@ -129,6 +142,9 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
struct intel_uncore_forcewake_domain *d;
enum forcewake_domain_id id;
+ WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
+ (fw_domains & ~FORCEWAKE_BLITTER));
+
for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
fw_domain_wait_ack_clear(d);
fw_domain_get(d);
@@ -142,6 +158,9 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
struct intel_uncore_forcewake_domain *d;
enum forcewake_domain_id id;
+ WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
+ (fw_domains & ~FORCEWAKE_BLITTER));
+
for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
fw_domain_put(d);
fw_domain_posting_read(d);
@@ -313,6 +332,11 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
if (fw)
dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
+ if (use_blitter_forcewake(dev) && !restore) {
+ __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, _MASKED_BIT_DISABLE(0xffff));
+ __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, _MASKED_BIT_DISABLE(0xffff));
+ }
+
fw_domains_reset(dev_priv, FORCEWAKE_ALL);
if (restore) { /* If reset with a user forcewake, try to restore */
@@ -780,8 +804,11 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
else \
fw_engine = FORCEWAKE_BLITTER; \
- if (fw_engine) \
+ if (fw_engine) { \
+ if (use_blitter_forcewake(dev_priv->dev)) \
+ fw_engine = FORCEWAKE_BLITTER; \
__force_wake_get(dev_priv, fw_engine); \
+ } \
val = __raw_i915_read##x(dev_priv, reg); \
GEN6_READ_FOOTER; \
}
@@ -994,8 +1021,11 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
else \
fw_engine = FORCEWAKE_BLITTER; \
- if (fw_engine) \
+ if (fw_engine) { \
+ if (use_blitter_forcewake(dev_priv->dev)) \
+ fw_engine = FORCEWAKE_BLITTER; \
__force_wake_get(dev_priv, fw_engine); \
+ } \
__raw_i915_write##x(dev_priv, reg, val); \
GEN6_WRITE_FOOTER; \
}
@@ -1106,14 +1136,17 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
if (IS_GEN9(dev)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
- FORCEWAKE_RENDER_GEN9,
- FORCEWAKE_ACK_RENDER_GEN9);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
- FORCEWAKE_BLITTER_GEN9,
- FORCEWAKE_ACK_BLITTER_GEN9);
- fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
- FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
+ if (!use_blitter_forcewake(dev)) {
+ fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ FORCEWAKE_RENDER_GEN9,
+ FORCEWAKE_ACK_RENDER_GEN9);
+ fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
+ FORCEWAKE_MEDIA_GEN9,
+ FORCEWAKE_ACK_MEDIA_GEN9);
+ }
+ fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
+ FORCEWAKE_BLITTER_GEN9,
+ FORCEWAKE_ACK_BLITTER_GEN9);
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
if (!IS_CHERRYVIEW(dev))
--
1.9.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
` (3 preceding siblings ...)
2015-08-23 12:22 ` [PATCH 4/5] drm/i915: Use only blitter forcewake Sagar Arun Kamble
@ 2015-08-23 12:22 ` Sagar Arun Kamble
2015-08-27 19:55 ` O'Rourke, Tom
4 siblings, 1 reply; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-08-23 12:22 UTC (permalink / raw)
To: intel-gfx
From: Alex Dai <yu.dai@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
3 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index ec70393..462c679 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -877,6 +877,24 @@ int i915_guc_submission_enable(struct drm_device *dev)
return 0;
}
+void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
+ /* Notify GuC about CPG changes. */
+ if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS) {
+ u32 data[2];
+
+ data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
+ data[1] = fw_data;
+
+ if (host2guc_action(guc, data, 2))
+ DRM_ERROR("Unable to notify GuC of CPG change\n");
+ }
+}
+
void i915_guc_submission_disable(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4ec2d27..691574d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -118,5 +118,6 @@ int i915_guc_submit(struct i915_guc_client *client,
struct drm_i915_gem_request *rq);
void i915_guc_submission_disable(struct drm_device *dev);
void i915_guc_submission_fini(struct drm_device *dev);
+void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data);
#endif
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c0345d2..4a0483c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4616,6 +4616,9 @@ static void gen9_disable_rps(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ i915_guc_sample_forcewake(dev, 0);
+
I915_WRITE(GEN9_PG_ENABLE, 0);
}
@@ -4804,6 +4807,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
uint32_t rc6_mask = 0;
+ uint32_t cpg_data = 0;
int unused;
/* 1a: Software RC state - RC0 */
@@ -4843,11 +4847,15 @@ static void gen9_enable_rc6(struct drm_device *dev)
* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
*/
if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
- (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+ (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) {
+ i915_guc_sample_forcewake(dev, 0);
I915_WRITE(GEN9_PG_ENABLE, 0);
- else
- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+ } else {
+ cpg_data = (rc6_mask & GEN6_RC_CTL_RC6_ENABLE)?
+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE):0;
+ i915_guc_sample_forcewake(dev, cpg_data);
+ I915_WRITE(GEN9_PG_ENABLE, cpg_data);
+ }
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.9.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-08-23 12:22 ` [PATCH 4/5] drm/i915: Use only blitter forcewake Sagar Arun Kamble
@ 2015-08-23 12:30 ` Chris Wilson
2015-09-11 13:23 ` Kamble, Sagar A
2015-09-11 13:37 ` Ville Syrjälä
1 sibling, 1 reply; 31+ messages in thread
From: Chris Wilson @ 2015-08-23 12:30 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
> hence even for render and media well registers blitter forcewake request
> need to be used.
Just insert a custom force_wake_get/put for the w/a.
Something like
gen9_force_wake_get_wa()
{
return fw_domains_get(BLITTER);
}
The fw counting will make it work just fine.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
@ 2015-08-26 9:26 ` Daniel Vetter
2015-09-22 9:06 ` Tvrtko Ursulin
2015-09-21 16:43 ` Yu Dai
1 sibling, 1 reply; 31+ messages in thread
From: Daniel Vetter @ 2015-08-26 9:26 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
> On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
> [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
> Polling for 50ms is recommended to avoid these timeouts.
>
> Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Probably needs cc: stable plus a pile of bugzilla links all over ...
-Daniel
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9d3c2e4..2df03b1 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -27,7 +27,7 @@
>
> #include <linux/pm_runtime.h>
>
> -#define FORCEWAKE_ACK_TIMEOUT_MS 2
> +#define FORCEWAKE_ACK_TIMEOUT_MS 50
>
> #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
> #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC
2015-08-23 12:22 ` [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC Sagar Arun Kamble
@ 2015-08-27 19:55 ` O'Rourke, Tom
2015-09-11 6:16 ` Kamble, Sagar A
0 siblings, 1 reply; 31+ messages in thread
From: O'Rourke, Tom @ 2015-08-27 19:55 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Sun, Aug 23, 2015 at 05:52:51PM +0530, Sagar Arun Kamble wrote:
> From: Alex Dai <yu.dai@intel.com>
>
[TOR:] This commit message is inadequate. The
needed information is in the cover letter but
is lacking here. Please rebase with Alex's
previous patch "drm/i915: Notify GuC rc6 state"
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> 3 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index ec70393..462c679 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -877,6 +877,24 @@ int i915_guc_submission_enable(struct drm_device *dev)
> return 0;
> }
>
> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +
> + /* Notify GuC about CPG changes. */
> + if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS) {
> + u32 data[2];
> +
> + data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> + data[1] = fw_data;
> +
> + if (host2guc_action(guc, data, 2))
> + DRM_ERROR("Unable to notify GuC of CPG change\n");
> + }
> +}
> +
> void i915_guc_submission_disable(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 4ec2d27..691574d 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -118,5 +118,6 @@ int i915_guc_submit(struct i915_guc_client *client,
> struct drm_i915_gem_request *rq);
> void i915_guc_submission_disable(struct drm_device *dev);
> void i915_guc_submission_fini(struct drm_device *dev);
> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c0345d2..4a0483c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4616,6 +4616,9 @@ static void gen9_disable_rps(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> + i915_guc_sample_forcewake(dev, 0);
> +
> I915_WRITE(GEN9_PG_ENABLE, 0);
> }
>
> @@ -4804,6 +4807,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> uint32_t rc6_mask = 0;
> + uint32_t cpg_data = 0;
> int unused;
>
> /* 1a: Software RC state - RC0 */
> @@ -4843,11 +4847,15 @@ static void gen9_enable_rc6(struct drm_device *dev)
> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> */
> if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> - (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) {
> + i915_guc_sample_forcewake(dev, 0);
> I915_WRITE(GEN9_PG_ENABLE, 0);
> - else
> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> + } else {
> + cpg_data = (rc6_mask & GEN6_RC_CTL_RC6_ENABLE)?
> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE):0;
> + i915_guc_sample_forcewake(dev, cpg_data);
> + I915_WRITE(GEN9_PG_ENABLE, cpg_data);
> + }
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC
2015-08-27 19:55 ` O'Rourke, Tom
@ 2015-09-11 6:16 ` Kamble, Sagar A
2015-09-11 17:17 ` Yu Dai
0 siblings, 1 reply; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 6:16 UTC (permalink / raw)
To: O'Rourke, Tom, Dai, Yu; +Cc: intel-gfx
Hi Alex,
Kindly incorporate changes in this patch in your patch at:
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075668.html
- [PATCH 5/6] drm/i915/guc: Media domain bit needed when notify GuC rc6
state
This is because GuC sample forcewake parameters depend on Coarse power
gating configuration.
Thanks
Sagar
On 8/28/2015 1:25 AM, O'Rourke, Tom wrote:
> On Sun, Aug 23, 2015 at 05:52:51PM +0530, Sagar Arun Kamble wrote:
>> From: Alex Dai <yu.dai@intel.com>
>>
> [TOR:] This commit message is inadequate. The
> needed information is in the cover letter but
> is lacking here. Please rebase with Alex's
> previous patch "drm/i915: Notify GuC rc6 state"
>
>> Signed-off-by: Alex Dai <yu.dai@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_guc_submission.c | 18 ++++++++++++++++++
>> drivers/gpu/drm/i915/intel_guc.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
>> 3 files changed, 31 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
>> index ec70393..462c679 100644
>> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
>> @@ -877,6 +877,24 @@ int i915_guc_submission_enable(struct drm_device *dev)
>> return 0;
>> }
>>
>> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data)
>> +{
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_guc *guc = &dev_priv->guc;
>> + struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
>> +
>> + /* Notify GuC about CPG changes. */
>> + if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS) {
>> + u32 data[2];
>> +
>> + data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
>> + data[1] = fw_data;
>> +
>> + if (host2guc_action(guc, data, 2))
>> + DRM_ERROR("Unable to notify GuC of CPG change\n");
>> + }
>> +}
>> +
>> void i915_guc_submission_disable(struct drm_device *dev)
>> {
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
>> index 4ec2d27..691574d 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -118,5 +118,6 @@ int i915_guc_submit(struct i915_guc_client *client,
>> struct drm_i915_gem_request *rq);
>> void i915_guc_submission_disable(struct drm_device *dev);
>> void i915_guc_submission_fini(struct drm_device *dev);
>> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index c0345d2..4a0483c 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4616,6 +4616,9 @@ static void gen9_disable_rps(struct drm_device *dev)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>>
>> I915_WRITE(GEN6_RC_CONTROL, 0);
>> +
>> + i915_guc_sample_forcewake(dev, 0);
>> +
>> I915_WRITE(GEN9_PG_ENABLE, 0);
>> }
>>
>> @@ -4804,6 +4807,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct intel_engine_cs *ring;
>> uint32_t rc6_mask = 0;
>> + uint32_t cpg_data = 0;
>> int unused;
>>
>> /* 1a: Software RC state - RC0 */
>> @@ -4843,11 +4847,15 @@ static void gen9_enable_rc6(struct drm_device *dev)
>> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
>> */
>> if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
>> - (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
>> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) {
>> + i915_guc_sample_forcewake(dev, 0);
>> I915_WRITE(GEN9_PG_ENABLE, 0);
>> - else
>> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
>> + } else {
>> + cpg_data = (rc6_mask & GEN6_RC_CTL_RC6_ENABLE)?
>> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE):0;
>> + i915_guc_sample_forcewake(dev, cpg_data);
>> + I915_WRITE(GEN9_PG_ENABLE, cpg_data);
>> + }
>>
>> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating
2015-08-23 12:22 ` [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
@ 2015-09-11 6:22 ` Kamble, Sagar A
2015-09-11 9:11 ` [PATCH 1/2] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-21 16:43 ` [PATCH 3/5] " Yu Dai
1 sibling, 1 reply; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 6:22 UTC (permalink / raw)
To: intel-gfx
Hi Alex,
Kindly review this patch.
Thanks
Sagar
On 8/23/2015 5:52 PM, Sagar Arun Kamble wrote:
> WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> disabled for platforms prior to BXT B0 and till SKL E0.
>
> Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 75f1c8c..c0345d2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4840,11 +4840,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> - * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> + * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> */
> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - GEN9_MEDIA_PG_ENABLE : 0);
> -
> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> + I915_WRITE(GEN9_PG_ENABLE, 0);
> + else
> + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo
2015-08-23 12:22 ` [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
@ 2015-09-11 6:23 ` Kamble, Sagar A
2015-09-11 12:24 ` Kamble, Sagar A
2015-09-21 16:43 ` Yu Dai
1 sibling, 1 reply; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 6:23 UTC (permalink / raw)
To: intel-gfx
Gentle reminder for review.
Thanks
Sagar
On 8/23/2015 5:52 PM, Sagar Arun Kamble wrote:
> Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
>
> Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fff0c22..75f1c8c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4450,6 +4450,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
> + return;
> +
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> WARN_ON(val > dev_priv->rps.max_freq);
> WARN_ON(val < dev_priv->rps.min_freq);
> @@ -4770,6 +4774,12 @@ static void gen9_enable_rps(struct drm_device *dev)
>
> gen6_init_rps_frequencies(dev);
>
> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + return;
> + }
> +
> /* Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RC_VIDEO_FREQ,
> GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 1/2] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro.
2015-09-11 6:22 ` Kamble, Sagar A
@ 2015-09-11 9:11 ` Sagar Arun Kamble
2015-09-11 9:11 ` [PATCH 2/2] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
0 siblings, 1 reply; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-09-11 9:11 UTC (permalink / raw)
To: intel-gfx
It will be usefull to specify w/a that affects only SKL GT3 and GT4.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5db246..1e48c86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2491,6 +2491,11 @@ struct drm_i915_cmd_table {
#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
INTEL_DEVID(dev) == 0x1915 || \
INTEL_DEVID(dev) == 0x191E)
+#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
+ (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
+#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
+ (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
+
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
#define SKL_REVID_A0 (0x0)
--
1.9.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 2/2] drm/i915: WaRsDisableCoarsePowerGating
2015-09-11 9:11 ` [PATCH 1/2] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
@ 2015-09-11 9:11 ` Sagar Arun Kamble
2015-09-11 11:46 ` [PATCH v2 1/1] " Sagar Arun Kamble
0 siblings, 1 reply; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-09-11 9:11 UTC (permalink / raw)
To: intel-gfx
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f6b5bb..5b0b7ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
/*
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
- * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+ * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
*/
- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- GEN9_MEDIA_PG_ENABLE : 0);
-
+ if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+ ((IS_SKL_GT3(dev) || IS_SKL_GT4) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+ I915_WRITE(GEN9_PG_ENABLE, 0);
+ else
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.9.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 1/1] drm/i915: WaRsDisableCoarsePowerGating
2015-09-11 9:11 ` [PATCH 2/2] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
@ 2015-09-11 11:46 ` Sagar Arun Kamble
0 siblings, 0 replies; 31+ messages in thread
From: Sagar Arun Kamble @ 2015-09-11 11:46 UTC (permalink / raw)
To: intel-gfx
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f6b5bb..c93d3a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
/*
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
- * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+ * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
*/
- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- GEN9_MEDIA_PG_ENABLE : 0);
-
+ if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+ ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+ I915_WRITE(GEN9_PG_ENABLE, 0);
+ else
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.9.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo
2015-09-11 6:23 ` Kamble, Sagar A
@ 2015-09-11 12:24 ` Kamble, Sagar A
0 siblings, 0 replies; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 12:24 UTC (permalink / raw)
To: O'Rourke, Tom, akash.goel; +Cc: intel-gfx
Hi Tom, Akash
Kindly review this patch.
Thanks
Sagar
On 9/11/2015 11:53 AM, Kamble, Sagar A wrote:
> Gentle reminder for review.
>
> Thanks
> Sagar
>
> On 8/23/2015 5:52 PM, Sagar Arun Kamble wrote:
>> Disable Turbo on steppings prior to B0 on BXT due to hangs seen
>> during GT CPD exit.
>>
>> Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index fff0c22..75f1c8c 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4450,6 +4450,10 @@ static void gen6_set_rps(struct drm_device
>> *dev, u8 val)
>> {
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
>> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
>> + return;
>> +
>> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>> WARN_ON(val > dev_priv->rps.max_freq);
>> WARN_ON(val < dev_priv->rps.min_freq);
>> @@ -4770,6 +4774,12 @@ static void gen9_enable_rps(struct drm_device
>> *dev)
>> gen6_init_rps_frequencies(dev);
>> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
>> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
>> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>> + return;
>> + }
>> +
>> /* Program defaults and thresholds for RPS*/
>> I915_WRITE(GEN6_RC_VIDEO_FREQ,
>> GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-08-23 12:30 ` Chris Wilson
@ 2015-09-11 13:23 ` Kamble, Sagar A
0 siblings, 0 replies; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 13:23 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: akash.goel
[-- Attachment #1.1: Type: text/plain, Size: 1054 bytes --]
Thanks Chris.
Domain refcount tracking is not common single function.
its present in __force_wake_get, __intel_uncore_forcewake_get and
likewise for put functions.
Either we will have to bring them together in fw_domains_get and then
add change you have suggested
Or
Prepare WA version of __force_wake_get and __intel_uncore_forcewake_get
Or
approach in the current patch where we only init blitter domain.
This will work from __intel_uncore_forcewake_get as well as it filters
domains based on dev_priv->uncore.fw_domains.
Let me know which approach looks good.
On 8/23/2015 6:00 PM, Chris Wilson wrote:
> On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
>> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
>> hence even for render and media well registers blitter forcewake request
>> need to be used.
> Just insert a custom force_wake_get/put for the w/a.
>
> Something like
>
> gen9_force_wake_get_wa()
> {
> return fw_domains_get(BLITTER);
> }
>
> The fw counting will make it work just fine.
> -Chris
>
[-- Attachment #1.2: Type: text/html, Size: 39752 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-08-23 12:22 ` [PATCH 4/5] drm/i915: Use only blitter forcewake Sagar Arun Kamble
2015-08-23 12:30 ` Chris Wilson
@ 2015-09-11 13:37 ` Ville Syrjälä
2015-09-11 13:54 ` Kamble, Sagar A
1 sibling, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2015-09-11 13:37 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
> hence even for render and media well registers blitter forcewake request
> need to be used.
>
> Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++-------
> 3 files changed, 48 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a28de5..8eea452 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1509,7 +1509,10 @@ static int gen6_drpc_info(struct seq_file *m)
> intel_runtime_pm_get(dev_priv);
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
> + if (use_blitter_forcewake(dev))
> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_BLITTER].wake_count;
> + else
> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> if (forcewake_count) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e0f3f05..c127175 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2691,6 +2691,7 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
> extern void intel_uncore_fini(struct drm_device *dev);
> extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
> const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
> +bool use_blitter_forcewake(struct drm_device *dev);
> void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> enum forcewake_domains domains);
> void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 2df03b1..b7b6612 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -63,6 +63,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
> return "unknown";
> }
>
> +bool use_blitter_forcewake(struct drm_device *dev)
> +{
> + /*
> + * Due to WaRsDisableCoarsePowerGating, Only blitter forcewake need to
> + * be used on platforms previous to BXT B0 and until SKL E0.
> + */
You say only blitter forcewake need be used. OK, but how does that imply
that you need to grab the blitter forcewake for render/media wells as
well?
> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> + return true;
> + else
> + return false;
> +}
> +
> static void
> assert_device_not_suspended(struct drm_i915_private *dev_priv)
> {
> @@ -129,6 +142,9 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> struct intel_uncore_forcewake_domain *d;
> enum forcewake_domain_id id;
>
> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
> + (fw_domains & ~FORCEWAKE_BLITTER));
> +
> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
> fw_domain_wait_ack_clear(d);
> fw_domain_get(d);
> @@ -142,6 +158,9 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> struct intel_uncore_forcewake_domain *d;
> enum forcewake_domain_id id;
>
> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
> + (fw_domains & ~FORCEWAKE_BLITTER));
> +
> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
> fw_domain_put(d);
> fw_domain_posting_read(d);
> @@ -313,6 +332,11 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
> if (fw)
> dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
>
> + if (use_blitter_forcewake(dev) && !restore) {
> + __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, _MASKED_BIT_DISABLE(0xffff));
> + __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, _MASKED_BIT_DISABLE(0xffff));
> + }
> +
> fw_domains_reset(dev_priv, FORCEWAKE_ALL);
>
> if (restore) { /* If reset with a user forcewake, try to restore */
> @@ -780,8 +804,11 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
> else \
> fw_engine = FORCEWAKE_BLITTER; \
> - if (fw_engine) \
> + if (fw_engine) { \
> + if (use_blitter_forcewake(dev_priv->dev)) \
> + fw_engine = FORCEWAKE_BLITTER; \
> __force_wake_get(dev_priv, fw_engine); \
> + } \
> val = __raw_i915_read##x(dev_priv, reg); \
> GEN6_READ_FOOTER; \
> }
> @@ -994,8 +1021,11 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
> else \
> fw_engine = FORCEWAKE_BLITTER; \
> - if (fw_engine) \
> + if (fw_engine) { \
> + if (use_blitter_forcewake(dev_priv->dev)) \
> + fw_engine = FORCEWAKE_BLITTER; \
> __force_wake_get(dev_priv, fw_engine); \
> + } \
> __raw_i915_write##x(dev_priv, reg, val); \
> GEN6_WRITE_FOOTER; \
> }
> @@ -1106,14 +1136,17 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
> if (IS_GEN9(dev)) {
> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> - fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> - FORCEWAKE_RENDER_GEN9,
> - FORCEWAKE_ACK_RENDER_GEN9);
> - fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
> - FORCEWAKE_BLITTER_GEN9,
> - FORCEWAKE_ACK_BLITTER_GEN9);
> - fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
> - FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
> + if (!use_blitter_forcewake(dev)) {
> + fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> + FORCEWAKE_RENDER_GEN9,
> + FORCEWAKE_ACK_RENDER_GEN9);
> + fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
> + FORCEWAKE_MEDIA_GEN9,
> + FORCEWAKE_ACK_MEDIA_GEN9);
> + }
> + fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
> + FORCEWAKE_BLITTER_GEN9,
> + FORCEWAKE_ACK_BLITTER_GEN9);
> } else if (IS_VALLEYVIEW(dev)) {
> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> if (!IS_CHERRYVIEW(dev))
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-09-11 13:37 ` Ville Syrjälä
@ 2015-09-11 13:54 ` Kamble, Sagar A
2015-09-11 14:02 ` Ville Syrjälä
0 siblings, 1 reply; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-11 13:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On 9/11/2015 7:07 PM, Ville Syrjälä wrote:
> On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
>> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
>> hence even for render and media well registers blitter forcewake request
>> need to be used.
>>
>> Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++-------
>> 3 files changed, 48 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 7a28de5..8eea452 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1509,7 +1509,10 @@ static int gen6_drpc_info(struct seq_file *m)
>> intel_runtime_pm_get(dev_priv);
>>
>> spin_lock_irq(&dev_priv->uncore.lock);
>> - forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
>> + if (use_blitter_forcewake(dev))
>> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_BLITTER].wake_count;
>> + else
>> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
>> spin_unlock_irq(&dev_priv->uncore.lock);
>>
>> if (forcewake_count) {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e0f3f05..c127175 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2691,6 +2691,7 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
>> extern void intel_uncore_fini(struct drm_device *dev);
>> extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
>> const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
>> +bool use_blitter_forcewake(struct drm_device *dev);
>> void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
>> enum forcewake_domains domains);
>> void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 2df03b1..b7b6612 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -63,6 +63,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
>> return "unknown";
>> }
>>
>> +bool use_blitter_forcewake(struct drm_device *dev)
>> +{
>> + /*
>> + * Due to WaRsDisableCoarsePowerGating, Only blitter forcewake need to
>> + * be used on platforms previous to BXT B0 and until SKL E0.
>> + */
> You say only blitter forcewake need be used. OK, but how does that imply
> that you need to grab the blitter forcewake for render/media wells as
> well?
Ok. I need to reword the commit message. Change is to grab blitter fw
for all register accesses in GT.
>
>> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
>> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
>> + return true;
>> + else
>> + return false;
>> +}
>> +
>> static void
>> assert_device_not_suspended(struct drm_i915_private *dev_priv)
>> {
>> @@ -129,6 +142,9 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
>> struct intel_uncore_forcewake_domain *d;
>> enum forcewake_domain_id id;
>>
>> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
>> + (fw_domains & ~FORCEWAKE_BLITTER));
>> +
>> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
>> fw_domain_wait_ack_clear(d);
>> fw_domain_get(d);
>> @@ -142,6 +158,9 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
>> struct intel_uncore_forcewake_domain *d;
>> enum forcewake_domain_id id;
>>
>> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
>> + (fw_domains & ~FORCEWAKE_BLITTER));
>> +
>> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
>> fw_domain_put(d);
>> fw_domain_posting_read(d);
>> @@ -313,6 +332,11 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
>> if (fw)
>> dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
>>
>> + if (use_blitter_forcewake(dev) && !restore) {
>> + __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, _MASKED_BIT_DISABLE(0xffff));
>> + __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, _MASKED_BIT_DISABLE(0xffff));
>> + }
>> +
>> fw_domains_reset(dev_priv, FORCEWAKE_ALL);
>>
>> if (restore) { /* If reset with a user forcewake, try to restore */
>> @@ -780,8 +804,11 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
>> else \
>> fw_engine = FORCEWAKE_BLITTER; \
>> - if (fw_engine) \
>> + if (fw_engine) { \
>> + if (use_blitter_forcewake(dev_priv->dev)) \
>> + fw_engine = FORCEWAKE_BLITTER; \
>> __force_wake_get(dev_priv, fw_engine); \
>> + } \
>> val = __raw_i915_read##x(dev_priv, reg); \
>> GEN6_READ_FOOTER; \
>> }
>> @@ -994,8 +1021,11 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
>> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
>> else \
>> fw_engine = FORCEWAKE_BLITTER; \
>> - if (fw_engine) \
>> + if (fw_engine) { \
>> + if (use_blitter_forcewake(dev_priv->dev)) \
>> + fw_engine = FORCEWAKE_BLITTER; \
>> __force_wake_get(dev_priv, fw_engine); \
>> + } \
>> __raw_i915_write##x(dev_priv, reg, val); \
>> GEN6_WRITE_FOOTER; \
>> }
>> @@ -1106,14 +1136,17 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>> if (IS_GEN9(dev)) {
>> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>> - FORCEWAKE_RENDER_GEN9,
>> - FORCEWAKE_ACK_RENDER_GEN9);
>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
>> - FORCEWAKE_BLITTER_GEN9,
>> - FORCEWAKE_ACK_BLITTER_GEN9);
>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>> - FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
>> + if (!use_blitter_forcewake(dev)) {
>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>> + FORCEWAKE_RENDER_GEN9,
>> + FORCEWAKE_ACK_RENDER_GEN9);
>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>> + FORCEWAKE_MEDIA_GEN9,
>> + FORCEWAKE_ACK_MEDIA_GEN9);
>> + }
>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
>> + FORCEWAKE_BLITTER_GEN9,
>> + FORCEWAKE_ACK_BLITTER_GEN9);
>> } else if (IS_VALLEYVIEW(dev)) {
>> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>> if (!IS_CHERRYVIEW(dev))
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-09-11 13:54 ` Kamble, Sagar A
@ 2015-09-11 14:02 ` Ville Syrjälä
2015-09-12 18:15 ` Kamble, Sagar A
0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2015-09-11 14:02 UTC (permalink / raw)
To: Kamble, Sagar A; +Cc: intel-gfx
On Fri, Sep 11, 2015 at 07:24:31PM +0530, Kamble, Sagar A wrote:
>
>
> On 9/11/2015 7:07 PM, Ville Syrjälä wrote:
> > On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
> >> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
> >> hence even for render and media well registers blitter forcewake request
> >> need to be used.
> >>
> >> Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
> >> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
> >> drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++-------
> >> 3 files changed, 48 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >> index 7a28de5..8eea452 100644
> >> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -1509,7 +1509,10 @@ static int gen6_drpc_info(struct seq_file *m)
> >> intel_runtime_pm_get(dev_priv);
> >>
> >> spin_lock_irq(&dev_priv->uncore.lock);
> >> - forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
> >> + if (use_blitter_forcewake(dev))
> >> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_BLITTER].wake_count;
> >> + else
> >> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
> >> spin_unlock_irq(&dev_priv->uncore.lock);
> >>
> >> if (forcewake_count) {
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index e0f3f05..c127175 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2691,6 +2691,7 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
> >> extern void intel_uncore_fini(struct drm_device *dev);
> >> extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
> >> const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
> >> +bool use_blitter_forcewake(struct drm_device *dev);
> >> void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
> >> enum forcewake_domains domains);
> >> void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
> >> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> >> index 2df03b1..b7b6612 100644
> >> --- a/drivers/gpu/drm/i915/intel_uncore.c
> >> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> >> @@ -63,6 +63,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
> >> return "unknown";
> >> }
> >>
> >> +bool use_blitter_forcewake(struct drm_device *dev)
> >> +{
> >> + /*
> >> + * Due to WaRsDisableCoarsePowerGating, Only blitter forcewake need to
> >> + * be used on platforms previous to BXT B0 and until SKL E0.
> >> + */
> > You say only blitter forcewake need be used. OK, but how does that imply
> > that you need to grab the blitter forcewake for render/media wells as
> > well?
> Ok. I need to reword the commit message. Change is to grab blitter fw
> for all register accesses in GT.
Where is that documented BTW? I couldn't find anything solid.
> >
> >> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> >> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> >> + return true;
> >> + else
> >> + return false;
> >> +}
> >> +
> >> static void
> >> assert_device_not_suspended(struct drm_i915_private *dev_priv)
> >> {
> >> @@ -129,6 +142,9 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> >> struct intel_uncore_forcewake_domain *d;
> >> enum forcewake_domain_id id;
> >>
> >> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
> >> + (fw_domains & ~FORCEWAKE_BLITTER));
> >> +
> >> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
> >> fw_domain_wait_ack_clear(d);
> >> fw_domain_get(d);
> >> @@ -142,6 +158,9 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> >> struct intel_uncore_forcewake_domain *d;
> >> enum forcewake_domain_id id;
> >>
> >> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
> >> + (fw_domains & ~FORCEWAKE_BLITTER));
> >> +
> >> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
> >> fw_domain_put(d);
> >> fw_domain_posting_read(d);
> >> @@ -313,6 +332,11 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
> >> if (fw)
> >> dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
> >>
> >> + if (use_blitter_forcewake(dev) && !restore) {
> >> + __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, _MASKED_BIT_DISABLE(0xffff));
> >> + __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, _MASKED_BIT_DISABLE(0xffff));
> >> + }
> >> +
> >> fw_domains_reset(dev_priv, FORCEWAKE_ALL);
> >>
> >> if (restore) { /* If reset with a user forcewake, try to restore */
> >> @@ -780,8 +804,11 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> >> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
> >> else \
> >> fw_engine = FORCEWAKE_BLITTER; \
> >> - if (fw_engine) \
> >> + if (fw_engine) { \
> >> + if (use_blitter_forcewake(dev_priv->dev)) \
> >> + fw_engine = FORCEWAKE_BLITTER; \
> >> __force_wake_get(dev_priv, fw_engine); \
> >> + } \
> >> val = __raw_i915_read##x(dev_priv, reg); \
> >> GEN6_READ_FOOTER; \
> >> }
> >> @@ -994,8 +1021,11 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
> >> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
> >> else \
> >> fw_engine = FORCEWAKE_BLITTER; \
> >> - if (fw_engine) \
> >> + if (fw_engine) { \
> >> + if (use_blitter_forcewake(dev_priv->dev)) \
> >> + fw_engine = FORCEWAKE_BLITTER; \
> >> __force_wake_get(dev_priv, fw_engine); \
> >> + } \
> >> __raw_i915_write##x(dev_priv, reg, val); \
> >> GEN6_WRITE_FOOTER; \
> >> }
> >> @@ -1106,14 +1136,17 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
> >> if (IS_GEN9(dev)) {
> >> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> >> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> >> - fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> >> - FORCEWAKE_RENDER_GEN9,
> >> - FORCEWAKE_ACK_RENDER_GEN9);
> >> - fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
> >> - FORCEWAKE_BLITTER_GEN9,
> >> - FORCEWAKE_ACK_BLITTER_GEN9);
> >> - fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
> >> - FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
> >> + if (!use_blitter_forcewake(dev)) {
> >> + fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> >> + FORCEWAKE_RENDER_GEN9,
> >> + FORCEWAKE_ACK_RENDER_GEN9);
> >> + fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
> >> + FORCEWAKE_MEDIA_GEN9,
> >> + FORCEWAKE_ACK_MEDIA_GEN9);
> >> + }
> >> + fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
> >> + FORCEWAKE_BLITTER_GEN9,
> >> + FORCEWAKE_ACK_BLITTER_GEN9);
> >> } else if (IS_VALLEYVIEW(dev)) {
> >> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> >> if (!IS_CHERRYVIEW(dev))
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC
2015-09-11 6:16 ` Kamble, Sagar A
@ 2015-09-11 17:17 ` Yu Dai
0 siblings, 0 replies; 31+ messages in thread
From: Yu Dai @ 2015-09-11 17:17 UTC (permalink / raw)
To: Kamble, Sagar A, O'Rourke, Tom; +Cc: intel-gfx
On 09/10/2015 11:16 PM, Kamble, Sagar A wrote:
> Hi Alex,
>
> Kindly incorporate changes in this patch in your patch at:
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075668.html
> - [PATCH 5/6] drm/i915/guc: Media domain bit needed when notify GuC rc6
> state
>
> This is because GuC sample forcewake parameters depend on Coarse power
> gating configuration.
>
> Thanks
> Sagar
>
>
>
> On 8/28/2015 1:25 AM, O'Rourke, Tom wrote:
> > On Sun, Aug 23, 2015 at 05:52:51PM +0530, Sagar Arun Kamble wrote:
> >> From: Alex Dai <yu.dai@intel.com>
> >>
> > [TOR:] This commit message is inadequate. The
> > needed information is in the cover letter but
> > is lacking here. Please rebase with Alex's
> > previous patch "drm/i915: Notify GuC rc6 state"
> >
> >> Signed-off-by: Alex Dai <yu.dai@intel.com>
> >> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_guc_submission.c | 18 ++++++++++++++++++
> >> drivers/gpu/drm/i915/intel_guc.h | 1 +
> >> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++----
> >> 3 files changed, 31 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> >> index ec70393..462c679 100644
> >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> >> @@ -877,6 +877,24 @@ int i915_guc_submission_enable(struct drm_device *dev)
> >> return 0;
> >> }
> >>
> >> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data)
> >> +{
> >> + struct drm_i915_private *dev_priv = dev->dev_private;
> >> + struct intel_guc *guc = &dev_priv->guc;
> >> + struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> >> +
> >> + /* Notify GuC about CPG changes. */
> >> + if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS) {
This might not be safe to protect code below. In the case of suspend,
the guc_fw_fetch_status and guc_fw_load_status both are SUCCESS.
However, we need to reload fw before any host2guc calls.
> >> + u32 data[2];
> >> +
> >> + data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> >> + data[1] = fw_data;
> >> +
> >> + if (host2guc_action(guc, data, 2))
> >> + DRM_ERROR("Unable to notify GuC of CPG change\n");
> >> + }
> >> +}
> >> +
Please call host2guc_sample_forcewake rather than a host2guc_action.
> >> void i915_guc_submission_disable(struct drm_device *dev)
> >> {
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> >> index 4ec2d27..691574d 100644
> >> --- a/drivers/gpu/drm/i915/intel_guc.h
> >> +++ b/drivers/gpu/drm/i915/intel_guc.h
> >> @@ -118,5 +118,6 @@ int i915_guc_submit(struct i915_guc_client *client,
> >> struct drm_i915_gem_request *rq);
> >> void i915_guc_submission_disable(struct drm_device *dev);
> >> void i915_guc_submission_fini(struct drm_device *dev);
> >> +void i915_guc_sample_forcewake(struct drm_device *dev, u32 fw_data);
> >>
> >> #endif
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index c0345d2..4a0483c 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -4616,6 +4616,9 @@ static void gen9_disable_rps(struct drm_device *dev)
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >>
> >> I915_WRITE(GEN6_RC_CONTROL, 0);
> >> +
> >> + i915_guc_sample_forcewake(dev, 0);
> >> +
> >> I915_WRITE(GEN9_PG_ENABLE, 0);
> >> }
> >>
> >> @@ -4804,6 +4807,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >> struct intel_engine_cs *ring;
> >> uint32_t rc6_mask = 0;
> >> + uint32_t cpg_data = 0;
> >> int unused;
> >>
> >> /* 1a: Software RC state - RC0 */
> >> @@ -4843,11 +4847,15 @@ static void gen9_enable_rc6(struct drm_device *dev)
> >> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> >> */
> >> if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> >> - (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> >> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) {
> >> + i915_guc_sample_forcewake(dev, 0);
> >> I915_WRITE(GEN9_PG_ENABLE, 0);
> >> - else
> >> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> >> + } else {
> >> + cpg_data = (rc6_mask & GEN6_RC_CTL_RC6_ENABLE)?
> >> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE):0;
> >> + i915_guc_sample_forcewake(dev, cpg_data);
> >> + I915_WRITE(GEN9_PG_ENABLE, cpg_data);
> >> + }
> >>
> >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >>
> >> --
Be note that calling guc function here actually happens in another
thread. The host2guc action will fail if GuC is not loaded. So there is
a potential racing issue here. I believe the failure will happen during
suspend / resume. I believe calling i915_guc_sample_forcewake or
host2guc_sample_forcewake after GuC is initialized is good enough.
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 4/5] drm/i915: Use only blitter forcewake
2015-09-11 14:02 ` Ville Syrjälä
@ 2015-09-12 18:15 ` Kamble, Sagar A
0 siblings, 0 replies; 31+ messages in thread
From: Kamble, Sagar A @ 2015-09-12 18:15 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On 9/11/2015 7:32 PM, Ville Syrjälä wrote:
> On Fri, Sep 11, 2015 at 07:24:31PM +0530, Kamble, Sagar A wrote:
>>
>> On 9/11/2015 7:07 PM, Ville Syrjälä wrote:
>>> On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
>>>> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
>>>> hence even for render and media well registers blitter forcewake request
>>>> need to be used.
>>>>
>>>> Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
>>>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
>>>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>>>> drivers/gpu/drm/i915/intel_uncore.c | 53 ++++++++++++++++++++++++++++++-------
>>>> 3 files changed, 48 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>>> index 7a28de5..8eea452 100644
>>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>>> @@ -1509,7 +1509,10 @@ static int gen6_drpc_info(struct seq_file *m)
>>>> intel_runtime_pm_get(dev_priv);
>>>>
>>>> spin_lock_irq(&dev_priv->uncore.lock);
>>>> - forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
>>>> + if (use_blitter_forcewake(dev))
>>>> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_BLITTER].wake_count;
>>>> + else
>>>> + forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
>>>> spin_unlock_irq(&dev_priv->uncore.lock);
>>>>
>>>> if (forcewake_count) {
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index e0f3f05..c127175 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -2691,6 +2691,7 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
>>>> extern void intel_uncore_fini(struct drm_device *dev);
>>>> extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
>>>> const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
>>>> +bool use_blitter_forcewake(struct drm_device *dev);
>>>> void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
>>>> enum forcewake_domains domains);
>>>> void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
>>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>>>> index 2df03b1..b7b6612 100644
>>>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>>>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>>>> @@ -63,6 +63,19 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
>>>> return "unknown";
>>>> }
>>>>
>>>> +bool use_blitter_forcewake(struct drm_device *dev)
>>>> +{
>>>> + /*
>>>> + * Due to WaRsDisableCoarsePowerGating, Only blitter forcewake need to
>>>> + * be used on platforms previous to BXT B0 and until SKL E0.
>>>> + */
>>> You say only blitter forcewake need be used. OK, but how does that imply
>>> that you need to grab the blitter forcewake for render/media wells as
>>> well?
>> Ok. I need to reword the commit message. Change is to grab blitter fw
>> for all register accesses in GT.
> Where is that documented BTW? I couldn't find anything solid.
This is not documented as part of WaRsDisableCoarsePowerGating.
But if Coarse Power Gating is disabled it is as good as legacy RC6 flow
like in HSW/BDW.
And hence we need to take blitter forcewake for all accesses.
>>>> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
>>>> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
>>>> + return true;
>>>> + else
>>>> + return false;
>>>> +}
>>>> +
>>>> static void
>>>> assert_device_not_suspended(struct drm_i915_private *dev_priv)
>>>> {
>>>> @@ -129,6 +142,9 @@ fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
>>>> struct intel_uncore_forcewake_domain *d;
>>>> enum forcewake_domain_id id;
>>>>
>>>> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
>>>> + (fw_domains & ~FORCEWAKE_BLITTER));
>>>> +
>>>> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
>>>> fw_domain_wait_ack_clear(d);
>>>> fw_domain_get(d);
>>>> @@ -142,6 +158,9 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
>>>> struct intel_uncore_forcewake_domain *d;
>>>> enum forcewake_domain_id id;
>>>>
>>>> + WARN_ON(use_blitter_forcewake(dev_priv->dev) &&
>>>> + (fw_domains & ~FORCEWAKE_BLITTER));
>>>> +
>>>> for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
>>>> fw_domain_put(d);
>>>> fw_domain_posting_read(d);
>>>> @@ -313,6 +332,11 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
>>>> if (fw)
>>>> dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
>>>>
>>>> + if (use_blitter_forcewake(dev) && !restore) {
>>>> + __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, _MASKED_BIT_DISABLE(0xffff));
>>>> + __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, _MASKED_BIT_DISABLE(0xffff));
>>>> + }
>>>> +
>>>> fw_domains_reset(dev_priv, FORCEWAKE_ALL);
>>>>
>>>> if (restore) { /* If reset with a user forcewake, try to restore */
>>>> @@ -780,8 +804,11 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>>>> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
>>>> else \
>>>> fw_engine = FORCEWAKE_BLITTER; \
>>>> - if (fw_engine) \
>>>> + if (fw_engine) { \
>>>> + if (use_blitter_forcewake(dev_priv->dev)) \
>>>> + fw_engine = FORCEWAKE_BLITTER; \
>>>> __force_wake_get(dev_priv, fw_engine); \
>>>> + } \
>>>> val = __raw_i915_read##x(dev_priv, reg); \
>>>> GEN6_READ_FOOTER; \
>>>> }
>>>> @@ -994,8 +1021,11 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
>>>> fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
>>>> else \
>>>> fw_engine = FORCEWAKE_BLITTER; \
>>>> - if (fw_engine) \
>>>> + if (fw_engine) { \
>>>> + if (use_blitter_forcewake(dev_priv->dev)) \
>>>> + fw_engine = FORCEWAKE_BLITTER; \
>>>> __force_wake_get(dev_priv, fw_engine); \
>>>> + } \
>>>> __raw_i915_write##x(dev_priv, reg, val); \
>>>> GEN6_WRITE_FOOTER; \
>>>> }
>>>> @@ -1106,14 +1136,17 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>>>> if (IS_GEN9(dev)) {
>>>> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>>>> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>>>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>>>> - FORCEWAKE_RENDER_GEN9,
>>>> - FORCEWAKE_ACK_RENDER_GEN9);
>>>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
>>>> - FORCEWAKE_BLITTER_GEN9,
>>>> - FORCEWAKE_ACK_BLITTER_GEN9);
>>>> - fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>>>> - FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
>>>> + if (!use_blitter_forcewake(dev)) {
>>>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>>>> + FORCEWAKE_RENDER_GEN9,
>>>> + FORCEWAKE_ACK_RENDER_GEN9);
>>>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
>>>> + FORCEWAKE_MEDIA_GEN9,
>>>> + FORCEWAKE_ACK_MEDIA_GEN9);
>>>> + }
>>>> + fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
>>>> + FORCEWAKE_BLITTER_GEN9,
>>>> + FORCEWAKE_ACK_BLITTER_GEN9);
>>>> } else if (IS_VALLEYVIEW(dev)) {
>>>> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
>>>> if (!IS_CHERRYVIEW(dev))
>>>> --
>>>> 1.9.1
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
2015-08-26 9:26 ` Daniel Vetter
@ 2015-09-21 16:43 ` Yu Dai
2015-09-23 8:04 ` Daniel Vetter
1 sibling, 1 reply; 31+ messages in thread
From: Yu Dai @ 2015-09-21 16:43 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
Looks fine to me.
Reviewed by: Alex Dai <yu.dai@intel.com>.
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
> [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
> Polling for 50ms is recommended to avoid these timeouts.
>
> Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9d3c2e4..2df03b1 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -27,7 +27,7 @@
>
> #include <linux/pm_runtime.h>
>
> -#define FORCEWAKE_ACK_TIMEOUT_MS 2
> +#define FORCEWAKE_ACK_TIMEOUT_MS 50
>
> #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
> #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo
2015-08-23 12:22 ` [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-11 6:23 ` Kamble, Sagar A
@ 2015-09-21 16:43 ` Yu Dai
2015-09-23 7:46 ` Daniel Vetter
1 sibling, 1 reply; 31+ messages in thread
From: Yu Dai @ 2015-09-21 16:43 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
Looks fine to me.
Reviewed by: Alex Dai <yu.dai@intel.com>.
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
>
> Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fff0c22..75f1c8c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4450,6 +4450,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
> + return;
> +
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> WARN_ON(val > dev_priv->rps.max_freq);
> WARN_ON(val < dev_priv->rps.min_freq);
> @@ -4770,6 +4774,12 @@ static void gen9_enable_rps(struct drm_device *dev)
>
> gen6_init_rps_frequencies(dev);
>
> + /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> + return;
> + }
> +
> /* Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RC_VIDEO_FREQ,
> GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating
2015-08-23 12:22 ` [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-11 6:22 ` Kamble, Sagar A
@ 2015-09-21 16:43 ` Yu Dai
2015-09-23 7:47 ` Daniel Vetter
1 sibling, 1 reply; 31+ messages in thread
From: Yu Dai @ 2015-09-21 16:43 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> disabled for platforms prior to BXT B0 and till SKL E0.
>
> Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 75f1c8c..c0345d2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4840,11 +4840,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> - * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> + * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> */
> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - GEN9_MEDIA_PG_ENABLE : 0);
> -
> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> + (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> + I915_WRITE(GEN9_PG_ENABLE, 0);
> + else
> + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>
Reviewed by: Alex Dai <yu.dai@intel.com>.
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-08-26 9:26 ` Daniel Vetter
@ 2015-09-22 9:06 ` Tvrtko Ursulin
2015-09-22 9:15 ` Chris Wilson
0 siblings, 1 reply; 31+ messages in thread
From: Tvrtko Ursulin @ 2015-09-22 9:06 UTC (permalink / raw)
To: Daniel Vetter, Sagar Arun Kamble; +Cc: intel-gfx
On 08/26/2015 10:26 AM, Daniel Vetter wrote:
> On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
>> On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
>> [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
>> Polling for 50ms is recommended to avoid these timeouts.
>>
>> Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> Probably needs cc: stable plus a pile of bugzilla links all over ...
If the required wait is typically that long, shouldn't we be worried
about busy polling?
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-09-22 9:06 ` Tvrtko Ursulin
@ 2015-09-22 9:15 ` Chris Wilson
2015-09-22 9:48 ` Tvrtko Ursulin
0 siblings, 1 reply; 31+ messages in thread
From: Chris Wilson @ 2015-09-22 9:15 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Tue, Sep 22, 2015 at 10:06:47AM +0100, Tvrtko Ursulin wrote:
>
> On 08/26/2015 10:26 AM, Daniel Vetter wrote:
> >On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
> >>On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
> >>[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
> >>Polling for 50ms is recommended to avoid these timeouts.
> >>
> >>Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
> >>Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >
> >Probably needs cc: stable plus a pile of bugzilla links all over ...
>
> If the required wait is typically that long, shouldn't we be worried
> about busy polling?
With an exponential backoff (i.e. busyspin for the first ~jiffie/1ms)
then usleep_range 1, 2, 4, 8,..?
And also keeping the fw wakelock for longer than a jiffie to
optimistically avoid these multi-jiffie stalls. Whilst grumbling.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-09-22 9:15 ` Chris Wilson
@ 2015-09-22 9:48 ` Tvrtko Ursulin
0 siblings, 0 replies; 31+ messages in thread
From: Tvrtko Ursulin @ 2015-09-22 9:48 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, Sagar Arun Kamble, intel-gfx
On 09/22/2015 10:15 AM, Chris Wilson wrote:
> On Tue, Sep 22, 2015 at 10:06:47AM +0100, Tvrtko Ursulin wrote:
>>
>> On 08/26/2015 10:26 AM, Daniel Vetter wrote:
>>> On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
>>>> On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
>>>> [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
>>>> Polling for 50ms is recommended to avoid these timeouts.
>>>>
>>>> Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
>>>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>>
>>> Probably needs cc: stable plus a pile of bugzilla links all over ...
>>
>> If the required wait is typically that long, shouldn't we be worried
>> about busy polling?
>
> With an exponential backoff (i.e. busyspin for the first ~jiffie/1ms)
> then usleep_range 1, 2, 4, 8,..?
>
> And also keeping the fw wakelock for longer than a jiffie to
> optimistically avoid these multi-jiffie stalls. Whilst grumbling.
For the atomic case holding it longer is the only option.
But key is how typical or atypical these long waits are. Measuring that
together with power use sounds critical.
Spread of required waits would also give the answer to what the best
sleeping strategy for the non-atomic case is.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo
2015-09-21 16:43 ` Yu Dai
@ 2015-09-23 7:46 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2015-09-23 7:46 UTC (permalink / raw)
To: Yu Dai; +Cc: intel-gfx
On Mon, Sep 21, 2015 at 09:43:25AM -0700, Yu Dai wrote:
> Looks fine to me.
> Reviewed by: Alex Dai <yu.dai@intel.com>.
>
> On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> >Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
> >
> >Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> >---
> > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index fff0c22..75f1c8c 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4450,6 +4450,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >+ /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> >+ if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
> >+ return;
> >+
> > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > WARN_ON(val > dev_priv->rps.max_freq);
> > WARN_ON(val < dev_priv->rps.min_freq);
> >@@ -4770,6 +4774,12 @@ static void gen9_enable_rps(struct drm_device *dev)
> > gen6_init_rps_frequencies(dev);
> >+ /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> >+ if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
> >+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >+ return;
> >+ }
> >+
> > /* Program defaults and thresholds for RPS*/
> > I915_WRITE(GEN6_RC_VIDEO_FREQ,
> > GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating
2015-09-21 16:43 ` [PATCH 3/5] " Yu Dai
@ 2015-09-23 7:47 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2015-09-23 7:47 UTC (permalink / raw)
To: Yu Dai; +Cc: intel-gfx
On Mon, Sep 21, 2015 at 09:43:49AM -0700, Yu Dai wrote:
>
>
> On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> >WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> >disabled for platforms prior to BXT B0 and till SKL E0.
> >
> >Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >---
> > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 75f1c8c..c0345d2 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4840,11 +4840,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
> > /*
> > * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> >- * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> >+ * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
> > */
> >- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >- GEN9_MEDIA_PG_ENABLE : 0);
> >-
> >+ if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> >+ (IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> >+ I915_WRITE(GEN9_PG_ENABLE, 0);
> >+ else
> >+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>
> Reviewed by: Alex Dai <yu.dai@intel.com>.
You reviewed an old version of this patch.
-Daniel
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
2015-09-21 16:43 ` Yu Dai
@ 2015-09-23 8:04 ` Daniel Vetter
0 siblings, 0 replies; 31+ messages in thread
From: Daniel Vetter @ 2015-09-23 8:04 UTC (permalink / raw)
To: Yu Dai; +Cc: intel-gfx
On Mon, Sep 21, 2015 at 09:43:06AM -0700, Yu Dai wrote:
> Looks fine to me.
> Reviewed by: Alex Dai <yu.dai@intel.com>.
>
> On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
> >On BXT, We Observe timeout for forcewake request completion with 2ms polling period as given here:
> >[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
> >Polling for 50ms is recommended to avoid these timeouts.
> >
> >Change-Id: Ie715b0069a3049606e9602bc5e97a6511890864d
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> >---
> > drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> >index 9d3c2e4..2df03b1 100644
> >--- a/drivers/gpu/drm/i915/intel_uncore.c
> >+++ b/drivers/gpu/drm/i915/intel_uncore.c
> >@@ -27,7 +27,7 @@
> > #include <linux/pm_runtime.h>
> >-#define FORCEWAKE_ACK_TIMEOUT_MS 2
> >+#define FORCEWAKE_ACK_TIMEOUT_MS 50
> > #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
> > #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2015-09-23 8:01 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-23 12:22 [PATCH 0/5] RC6/Forcewake/Turbo related changes for Gen9 Sagar Arun Kamble
2015-08-23 12:22 ` [PATCH 1/5] drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack Sagar Arun Kamble
2015-08-26 9:26 ` Daniel Vetter
2015-09-22 9:06 ` Tvrtko Ursulin
2015-09-22 9:15 ` Chris Wilson
2015-09-22 9:48 ` Tvrtko Ursulin
2015-09-21 16:43 ` Yu Dai
2015-09-23 8:04 ` Daniel Vetter
2015-08-23 12:22 ` [PATCH 2/5] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-11 6:23 ` Kamble, Sagar A
2015-09-11 12:24 ` Kamble, Sagar A
2015-09-21 16:43 ` Yu Dai
2015-09-23 7:46 ` Daniel Vetter
2015-08-23 12:22 ` [PATCH 3/5] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-11 6:22 ` Kamble, Sagar A
2015-09-11 9:11 ` [PATCH 1/2] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-11 9:11 ` [PATCH 2/2] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-11 11:46 ` [PATCH v2 1/1] " Sagar Arun Kamble
2015-09-21 16:43 ` [PATCH 3/5] " Yu Dai
2015-09-23 7:47 ` Daniel Vetter
2015-08-23 12:22 ` [PATCH 4/5] drm/i915: Use only blitter forcewake Sagar Arun Kamble
2015-08-23 12:30 ` Chris Wilson
2015-09-11 13:23 ` Kamble, Sagar A
2015-09-11 13:37 ` Ville Syrjälä
2015-09-11 13:54 ` Kamble, Sagar A
2015-09-11 14:02 ` Ville Syrjälä
2015-09-12 18:15 ` Kamble, Sagar A
2015-08-23 12:22 ` [PATCH 5/5] drm/i915: Notify Coarse Power Gating changes to GuC Sagar Arun Kamble
2015-08-27 19:55 ` O'Rourke, Tom
2015-09-11 6:16 ` Kamble, Sagar A
2015-09-11 17:17 ` Yu Dai
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