Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[Arnd Bergmann]

On Monday 12 October 2015 23:20:17 John Garry wrote:
> +       interrupt_count = of_property_count_u32_elems(np, "interrupts");
> +       if (interrupt_count < 0)
> +               goto err_out;
> +
> +       if (of_property_read_u32(np, "#interrupt-cells", &interrupt_cells))
> +               goto err_out;
> +
> +       hisi_hba->int_names = devm_kcalloc(&pdev->dev,
> +                                          interrupt_count / interrupt_cells,
> +                                          HISI_SAS_NAME_LEN,
> +                                          GFP_KERNEL);
> 

This computation looks wrong: the "interrupts" property refers to interrupts
that are referenced by this node and provided by an interrupt-controller,
while the "#interrupt-cells" property refers to interrupts provided by
this node. They don't need to have any relation.

	Arnd

Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[Arnd Bergmann]

On Monday 12 October 2015 23:20:17 John Garry wrote:
> +       interrupt_count = of_property_count_u32_elems(np, "interrupts");
> +       if (interrupt_count < 0)
> +               goto err_out;
> +
> +       if (of_property_read_u32(np, "#interrupt-cells", &interrupt_cells))
> +               goto err_out;
> +
> +       hisi_hba->int_names = devm_kcalloc(&pdev->dev,
> +                                          interrupt_count / interrupt_cells,
> +                                          HISI_SAS_NAME_LEN,
> +                                          GFP_KERNEL);
> 

This computation looks wrong: the "interrupts" property refers to interrupts
that are referenced by this node and provided by an interrupt-controller,
while the "#interrupt-cells" property refers to interrupts provided by
this node. They don't need to have any relation.

	Arnd
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[PATCH 00/25] HiSilicon SAS driver

[John Garry]

This is the driver patchset for the HiSilicon SAS driver. The driver
is a platform driver.

The driver will support multiple revisions of HW. Currently only "v1"
HW is supported.

The driver uses libsas framework within the SCSI framework.

The v1 HW supports SSP and SMP, but not STP/SATA.


John Garry (25):
  [SCSI] sas: centralise ssp frame information units
  devicetree: bindings: scsi: HiSi SAS
  scsi: hisi_sas: add initial bare driver
  scsi: hisi_sas: add scsi host registration
  scsi: hisi_sas: allocate memories and create pools
  scsi: hisi_sas: add slot init code
  scsi: hisi_sas: add ioremap for device HW
  scsi: hisi_sas: add cq structure initialization
  scsi: hisi_sas: add phy SAS ADDR initialization
  scsi: hisi_sas: add misc HBA initialization
  scsi: hisi_sas: add v1 hardware register definitions
  scsi: hisi_sas: add v1 HW initialisation code
  scsi: hisi_sas: add path from phyup irq to SAS framework
  scsi: hisi_sas: add ssp command function
  scsi: hisi_sas: add cq interrupt handler
  scsi: hisi_sas: add dev_found and port_formed
  scsi: hisi_sas: add abnormal irq handler
  scsi: hisi_sas: add dev_gone and port_deformed
  scsi: hisi_sas: add bcast interrupt handler
  scsi: hisi_sas: add smp protocol support
  scsi: hisi_sas: add scan finished and start
  scsi: hisi_sas: add tmf methods
  scsi: hisi_sas: add control phy handler
  scsi: hisi_sas: add fatal irq handler
  MAINTAINERS: add maintainer for HiSi SAS driver

 .../devicetree/bindings/scsi/hisilicon-sas.txt     |   63 +
 MAINTAINERS                                        |    7 +
 drivers/scsi/Kconfig                               |    1 +
 drivers/scsi/Makefile                              |    1 +
 drivers/scsi/aic94xx/aic94xx_sas.h                 |   49 +-
 drivers/scsi/hisi_sas/Kconfig                      |    5 +
 drivers/scsi/hisi_sas/Makefile                     |    2 +
 drivers/scsi/hisi_sas/hisi_sas.h                   |  406 +++++
 drivers/scsi/hisi_sas/hisi_sas_init.c              |  489 ++++++
 drivers/scsi/hisi_sas/hisi_sas_main.c              | 1115 ++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c             | 1850 ++++++++++++++++++++
 include/scsi/sas.h                                 |   74 +
 12 files changed, 4019 insertions(+), 43 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
 create mode 100644 drivers/scsi/hisi_sas/Kconfig
 create mode 100644 drivers/scsi/hisi_sas/Makefile
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_main.c
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

-- 
1.9.1

[PATCH 01/25] [SCSI] sas: centralise ssp frame information units

[John Garry]

The xfer_rdy, command, and task frame's iu structures
are not available in <scsi/sas.h>, but only aic94xx
driver folder.
Add them to include/scsi/sas.h

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/aic94xx/aic94xx_sas.h | 49 ++++---------------------
 include/scsi/sas.h                 | 74 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+), 43 deletions(-)

diff --git a/drivers/scsi/aic94xx/aic94xx_sas.h b/drivers/scsi/aic94xx/aic94xx_sas.h
index 912e6b7..101072c 100644
--- a/drivers/scsi/aic94xx/aic94xx_sas.h
+++ b/drivers/scsi/aic94xx/aic94xx_sas.h
@@ -327,46 +327,9 @@ struct scb_header {
 
 #define LUN_SIZE                8
 
-/* See SAS spec, task IU
- */
-struct ssp_task_iu {
-	u8     lun[LUN_SIZE];	  /* BE */
-	u16    _r_a;
-	u8     tmf;
-	u8     _r_b;
-	__be16 tag;		  /* BE */
-	u8     _r_c[14];
-} __attribute__ ((packed));
-
-/* See SAS spec, command IU
- */
-struct ssp_command_iu {
-	u8     lun[LUN_SIZE];
-	u8     _r_a;
-	u8     efb_prio_attr;	  /* enable first burst, task prio & attr */
-#define EFB_MASK        0x80
-#define TASK_PRIO_MASK	0x78
-#define TASK_ATTR_MASK  0x07
-
-	u8    _r_b;
-	u8     add_cdb_len;	  /* in dwords, since bit 0,1 are reserved */
-	union {
-		u8     cdb[16];
-		struct {
-			__le64 long_cdb_addr;	  /* bus address, LE */
-			__le32 long_cdb_size;	  /* LE */
-			u8     _r_c[3];
-			u8     eol_ds;		  /* eol:6,6, ds:5,4 */
-		} long_cdb;	  /* sequencer extension */
-	};
-} __attribute__ ((packed));
-
-struct xfer_rdy_iu {
-	__be32 requested_offset;  /* BE */
-	__be32 write_data_len;	  /* BE */
-	__be32 _r_a;
-} __attribute__ ((packed));
-
+#define EFB_MASK                0x80
+#define TASK_PRIO_MASK          0x78
+#define TASK_ATTR_MASK          0x07
 /* ---------- SCB tasks ---------- */
 
 /* This is both ssp_task and long_ssp_task
@@ -511,7 +474,7 @@ struct abort_task {
 	u8     proto_conn_rate;
 	__le32 _r_a;
 	struct ssp_frame_hdr ssp_frame;
-	struct ssp_task_iu ssp_task;
+	struct ssp_tmf_iu ssp_task;
 	__le16 sister_scb;
 	__le16 conn_handle;
 	u8     flags;	  /* ovrd_itnl_timer:3,3, suspend_data_trans:2,2 */
@@ -549,7 +512,7 @@ struct clear_nexus {
 	u8     _r_b[3];
 	u8     conn_mask;
 	u8     _r_c[19];
-	struct ssp_task_iu ssp_task; /* LUN and TAG */
+	struct ssp_tmf_iu ssp_task; /* LUN and TAG */
 	__le16 _r_d;
 	__le16 conn_handle;
 	__le64 _r_e;
@@ -562,7 +525,7 @@ struct initiate_ssp_tmf {
 	u8     proto_conn_rate;
 	__le32 _r_a;
 	struct ssp_frame_hdr ssp_frame;
-	struct ssp_task_iu ssp_task;
+	struct ssp_tmf_iu ssp_task;
 	__le16 sister_scb;
 	__le16 conn_handle;
 	u8     flags;	  /* itnl override and suspend data tx */
diff --git a/include/scsi/sas.h b/include/scsi/sas.h
index 0d2607d..42a84ef 100644
--- a/include/scsi/sas.h
+++ b/include/scsi/sas.h
@@ -344,6 +344,43 @@ struct ssp_response_iu {
 	u8     sense_data[0];
 } __attribute__ ((packed));
 
+struct ssp_command_iu {
+	u8     lun[8];
+	u8     _r_a;
+
+	union {
+		struct {
+			u8  attr:3;
+			u8  prio:4;
+			u8  efb:1;
+		};
+		u8 efb_prio_attr;
+	};
+
+	u8    _r_b;
+
+	u8    _r_c:2;
+	u8    add_cdb_len:6;
+
+	u8    cdb[16];
+	u8    add_cdb[0];
+} __attribute__ ((packed));
+
+struct xfer_rdy_iu {
+	__be32 requested_offset;
+	__be32 write_data_len;
+	__be32 _r_a;
+} __attribute__ ((packed));
+
+struct ssp_tmf_iu {
+	u8     lun[8];
+	u16    _r_a;
+	u8     tmf;
+	u8     _r_b;
+	__be16 tag;
+	u8     _r_c[14];
+} __attribute__ ((packed));
+
 /* ---------- SMP ---------- */
 
 struct report_general_resp {
@@ -538,6 +575,43 @@ struct ssp_response_iu {
 	u8     sense_data[0];
 } __attribute__ ((packed));
 
+struct ssp_command_iu {
+	u8     lun[8];
+	u8     _r_a;
+
+	union {
+		struct {
+			u8  efb:1;
+			u8  prio:4;
+			u8  attr:3;
+		};
+		u8 efb_prio_attr;
+	};
+
+	u8    _r_b;
+
+	u8    add_cdb_len:6;
+	u8    _r_c:2;
+
+	u8    cdb[16];
+	u8    add_cdb[0];
+} __attribute__ ((packed));
+
+struct xfer_rdy_iu {
+	__be32 requested_offset;
+	__be32 write_data_len;
+	__be32 _r_a;
+} __attribute__ ((packed));
+
+struct ssp_tmf_iu {
+	u8     lun[8];
+	u16    _r_a;
+	u8     tmf;
+	u8     _r_b;
+	__be16 tag;
+	u8     _r_c[14];
+} __attribute__ ((packed));
+
 /* ---------- SMP ---------- */
 
 struct report_general_resp {
-- 
1.9.1

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[PATCH 02/25] devicetree: bindings: scsi: HiSi SAS

[John Garry]

Add devicetree bindings for HiSilicon SAS driver.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../devicetree/bindings/scsi/hisilicon-sas.txt     | 63 ++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt

diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
new file mode 100644
index 0000000..472c022
--- /dev/null
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -0,0 +1,63 @@
+* HiSilison SAS controller
+
+The HiSilicon SAS controller supports SAS/SATA.
+
+Main node required properties:
+  - compatible : value should be as follows:
+	(a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
+
+  - controller-id : identifier for controller in the SoC
+
+  - reg : Address and length of the register sets for the device
+   - SAS controller registers
+   - SAS controller control registers
+
+  - reset-reg : offset to reset, status, and clock registers in control registers
+
+  - queue-count : number of delivery and completion queues in the controller
+
+  - phy-count : number of phys accessible by the controller
+
+  - interrupts : Interrupts for phys, completion queues, and fatal
+		 interrupts:
+		  - Each phy has 3 interrupt sources:
+			- broadcast
+			- phyup
+			- abnormal
+		  - Each completion queue has 1 interrupt source
+		  - Each controller has 2 fatal interrupt sources:
+			- ECC
+			- AXI bus
+
+Example:
+	sas0: sas@c1000000 {
+		compatible = "hisilicon,sas-controller-v1";
+		controller-id = <0>;
+		reg = <0x0 0xc1000000 0x0 0x10000>,
+			<0x0 0xc0000000 0x0 0x10000>;
+		reset-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
+		queue-count = <32>;
+		phy-count = <8>;
+		#interrupt-cells = <2>;
+		dma-coherent;
+		interrupt-parent = <&mbigen_dsa>;
+		interrupts = <259 4>, <263 4>,<264 4>,/* phy irq(0~79) */
+				<269 4>,<273 4>,<274 4>,/* phy irq(0~79) */
+				<279 4>,<283 4>,<284 4>,/* phy irq(0~79) */
+				<289 4>,<293 4>,<294 4>,/* phy irq(0~79) */
+				<299 4>,<303 4>,<304 4>,/* phy irq(0~79) */
+				<309 4>,<313 4>,<314 4>,/* phy irq(0~79) */
+				<319 4>,<323 4>,<324 4>,/* phy irq(0~79) */
+				<329 4>,<333 4>,<334 4>,/* phy irq(0~79) */
+				<336 1>,<337 1>,<338 1>,<339 1>,<340 1>,
+				<341 1>,<342 1>,<343 1>,/* cq irq (80~111) */
+				<344 1>,<345 1>,<346 1>,<347 1>,<348 1>,
+				<349 1>,<350 1>,<351 1>,/* cq irq (80~111) */
+				<352 1>,<353 1>,<354 1>,<355 1>,<356 1>,
+				<357 1>,<358 1>,<359 1>,/* cq irq (80~111) */
+				<360 1>,<361 1>,<362 1>,<363 1>,<364 1>,
+				<365 1>,<366 1>,<367 1>,/* cq irq (80~111) */
+				<376 4>,/* chip fatal error irq(120) */
+				<381 4>;/* chip fatal error irq(125) */
+		status = "okay";
+	};
-- 
1.9.1

[PATCH 03/25] scsi: hisi_sas: add initial bare driver

[John Garry]

This patch adds the initial bare driver for the HiSilicon
SAS HBA. The driver includes no HW interaction, but only
the changes to build and load the driver module.

The HBA is a platform device.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/Kconfig                  |  1 +
 drivers/scsi/Makefile                 |  1 +
 drivers/scsi/hisi_sas/Kconfig         |  5 +++
 drivers/scsi/hisi_sas/Makefile        |  2 ++
 drivers/scsi/hisi_sas/hisi_sas.h      | 24 +++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 58 +++++++++++++++++++++++++++++++++++
 6 files changed, 91 insertions(+)
 create mode 100644 drivers/scsi/hisi_sas/Kconfig
 create mode 100644 drivers/scsi/hisi_sas/Makefile
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c

diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 95f7a76..5c345f9 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -1774,5 +1774,6 @@ source "drivers/scsi/pcmcia/Kconfig"
 source "drivers/scsi/device_handler/Kconfig"
 
 source "drivers/scsi/osd/Kconfig"
+source "drivers/scsi/hisi_sas/Kconfig"
 
 endmenu
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 1a8c9b5..03c30de 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -158,6 +158,7 @@ obj-$(CONFIG_CHR_DEV_SCH)	+= ch.o
 obj-$(CONFIG_SCSI_ENCLOSURE)	+= ses.o
 
 obj-$(CONFIG_SCSI_OSD_INITIATOR) += osd/
+obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas/
 
 # This goes last, so that "real" scsi devices probe earlier
 obj-$(CONFIG_SCSI_DEBUG)	+= scsi_debug.o
diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
new file mode 100644
index 0000000..a7f47a2
--- /dev/null
+++ b/drivers/scsi/hisi_sas/Kconfig
@@ -0,0 +1,5 @@
+config SCSI_HISI_SAS
+	tristate "HiSilicon SAS"
+	select SCSI_SAS_LIBSAS
+	help
+		This driver supports HiSilicon's SAS HBA
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
new file mode 100644
index 0000000..63c3c4d
--- /dev/null
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
+hisi_sas-y+= hisi_sas_init.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
new file mode 100644
index 0000000..50204a2
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef _HISI_SAS_H_
+#define _HISI_SAS_H_
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <scsi/libsas.h>
+
+#define DRV_NAME "hisi_sas"
+#define DRV_VERSION "v1.0"
+
+#endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
new file mode 100644
index 0000000..dd83430
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+
+static const struct of_device_id sas_of_match[] = {
+	{ .compatible = "hisilicon,sas-controller-v1",},
+	{},
+};
+MODULE_DEVICE_TABLE(of, sas_of_match);
+static int hisi_sas_probe(struct platform_device *pdev)
+{
+
+	return 0;
+}
+
+static int hisi_sas_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver hisi_sas_driver = {
+	.probe = hisi_sas_probe,
+	.remove = hisi_sas_remove,
+	.driver = {
+		.name = DRV_NAME,
+		.of_match_table = sas_of_match,
+	},
+};
+
+static __init int hisi_sas_init(void)
+{
+	pr_info("hisi_sas: driver version %s\n", DRV_VERSION);
+
+	return platform_driver_register(&hisi_sas_driver);
+}
+
+static __exit void hisi_sas_exit(void)
+{
+	platform_driver_unregister(&hisi_sas_driver);
+}
+
+module_init(hisi_sas_init);
+module_exit(hisi_sas_exit);
+
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
+MODULE_DESCRIPTION("HISILICON SAS controller driver");
+MODULE_ALIAS("platform:" DRV_NAME);
-- 
1.9.1

[PATCH 04/25] scsi: hisi_sas: add scsi host registration

[John Garry]

Add functionality to register device as a scsi host.

The SAS domain transport ops are empty at this point.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h      |  32 +++++++++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 125 ++++++++++++++++++++++++++++++++++
 2 files changed, 157 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 50204a2..1a90b54 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -21,4 +21,36 @@
 #define DRV_NAME "hisi_sas"
 #define DRV_VERSION "v1.0"
 
+#define HISI_SAS_MAX_PHYS	9
+#define HISI_SAS_MAX_ITCT_ENTRIES 4096
+#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
+#define HISI_SAS_COMMAND_ENTRIES 8192
+
+
+struct hisi_sas_phy {
+	struct hisi_sas_port	*port;
+	struct asd_sas_phy	sas_phy;
+};
+
+struct hisi_sas_port {
+	struct asd_sas_port	sas_port;
+};
+
+struct hisi_hba {
+	spinlock_t	lock;
+
+	struct platform_device *pdev;
+
+
+	u8 sas_addr[SAS_ADDR_SIZE];
+
+	int	n_phy;
+	/* SCSI/SAS glue */
+	struct sas_ha_struct sha;
+	struct Scsi_Host *shost;
+	struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
+	struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
+};
+
+#define HISI_SAS_SGE_PAGE_CNT SCSI_MAX_SG_SEGMENTS
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index dd83430..2cae458 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -10,20 +10,140 @@
  */
 
 #include "hisi_sas.h"
+static struct scsi_transport_template *hisi_sas_stt;
+
+static struct scsi_host_template hisi_sas_sht = {
+	.module			= THIS_MODULE,
+	.name			= DRV_NAME,
+	.queuecommand		= sas_queuecommand,
+	.target_alloc		= sas_target_alloc,
+	.slave_configure	= sas_slave_configure,
+	.change_queue_depth	= sas_change_queue_depth,
+	.bios_param		= sas_bios_param,
+	.can_queue		= 1,
+	.cmd_per_lun		= 1,
+	.this_id		= -1,
+	.sg_tablesize		= SG_ALL,
+	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
+	.use_clustering		= ENABLE_CLUSTERING,
+	.eh_device_reset_handler = sas_eh_device_reset_handler,
+	.eh_bus_reset_handler	= sas_eh_bus_reset_handler,
+	.target_destroy		= sas_target_destroy,
+	.ioctl			= sas_ioctl,
+};
+
+static struct sas_domain_function_template hisi_sas_transport_ops = {
+};
+
 
 static const struct of_device_id sas_of_match[] = {
 	{ .compatible = "hisilicon,sas-controller-v1",},
 	{},
 };
 MODULE_DEVICE_TABLE(of, sas_of_match);
+
+static struct hisi_hba *hisi_sas_hba_alloc(
+			struct platform_device *pdev,
+			struct Scsi_Host *shost,
+			struct device_node *np)
+{
+	int interrupt_count, interrupt_cells;
+	struct hisi_hba *hisi_hba;
+
+	hisi_hba = devm_kzalloc(&pdev->dev, sizeof(*hisi_hba), GFP_KERNEL);
+	if (!hisi_hba)
+		goto err_out;
+
+	hisi_hba->pdev = pdev;
+	hisi_hba->shost = shost;
+
+	return hisi_hba;
+err_out:
+	dev_err(&pdev->dev, "hba alloc failed\n");
+	return NULL;
+}
+
 static int hisi_sas_probe(struct platform_device *pdev)
 {
+	struct Scsi_Host *shost;
+	struct hisi_hba *hisi_hba;
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
+	struct asd_sas_phy **arr_phy;
+	struct asd_sas_port **arr_port;
+	struct sas_ha_struct *sha;
+	int rc, phy_nr, port_nr, i;
+
+	shost = scsi_host_alloc(&hisi_sas_sht, sizeof(void *));
+	if (!shost)
+		return -ENOMEM;
+
+	hisi_hba = hisi_sas_hba_alloc(pdev, shost, np);
+	if (!hisi_hba) {
+		rc = -ENOMEM;
+		goto err_out_ha;
+	}
+
+	sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
+	platform_set_drvdata(pdev, sha);
+
+	phy_nr = port_nr = HISI_SAS_MAX_PHYS;
+
+	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
+	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
+	if (!arr_phy || !arr_port)
+		return -ENOMEM;
+
+	sha->sas_phy = arr_phy;
+	sha->sas_port = arr_port;
+	sha->core.shost = shost;
+	sha->lldd_ha = hisi_hba;
+
+	shost->transportt = hisi_sas_stt;
+	shost->max_id = HISI_SAS_MAX_DEVICES;
+	shost->max_lun = ~0;
+	shost->max_channel = 1;
+	shost->max_cmd_len = 16;
+	shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
+	shost->can_queue = HISI_SAS_COMMAND_ENTRIES;
+	shost->cmd_per_lun = HISI_SAS_COMMAND_ENTRIES;
+
+	sha->sas_ha_name = DRV_NAME;
+	sha->dev = &hisi_hba->pdev->dev;
+	sha->lldd_module = THIS_MODULE;
+	sha->sas_addr = &hisi_hba->sas_addr[0];
+	sha->num_phys = hisi_hba->n_phy;
+	sha->core.shost = hisi_hba->shost;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
+		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
+	}
+	rc = scsi_add_host(shost, &pdev->dev);
+	if (rc)
+		goto err_out_ha;
+
+	rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
+	if (rc)
+		goto err_out_register_ha;
 
 	return 0;
+
+err_out_register_ha:
+	scsi_remove_host(shost);
+err_out_ha:
+	kfree(shost);
+	return rc;
 }
 
 static int hisi_sas_remove(struct platform_device *pdev)
 {
+	struct sas_ha_struct *sha = platform_get_drvdata(pdev);
+
+	sas_unregister_ha(sha);
+	sas_remove_host(sha->core.shost);
+	scsi_remove_host(sha->core.shost);
+
 	return 0;
 }
 
@@ -40,12 +160,17 @@ static __init int hisi_sas_init(void)
 {
 	pr_info("hisi_sas: driver version %s\n", DRV_VERSION);
 
+	hisi_sas_stt = sas_domain_attach_transport(&hisi_sas_transport_ops);
+	if (!hisi_sas_stt)
+		return -ENOMEM;
+
 	return platform_driver_register(&hisi_sas_driver);
 }
 
 static __exit void hisi_sas_exit(void)
 {
 	platform_driver_unregister(&hisi_sas_driver);
+	sas_release_transport(hisi_sas_stt);
 }
 
 module_init(hisi_sas_init);
-- 
1.9.1

[PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[John Garry]

Allocate DMA and non-DMA memories for the controller. Also
create DMA pools.

These include:
- Delivery queues
- Completion queues
- Command status buffer
- Command table
- ITCT (For device context)
- Host slot info
- IO status
- Breakpoint
- host slot indexing
- SG data
- FIS
- interrupts names

The device tree must be examined for relevant fields.

Also set controller id.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas.h      | 204 ++++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 191 ++++++++++++++++++++++++++++++-
 2 files changed, 394 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 1a90b54..2c15036 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -22,10 +22,18 @@
 #define DRV_VERSION "v1.0"
 
 #define HISI_SAS_MAX_PHYS	9
+#define HISI_SAS_MAX_QUEUES	32
+#define HISI_SAS_QUEUE_SLOTS 512
 #define HISI_SAS_MAX_ITCT_ENTRIES 4096
 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
 #define HISI_SAS_COMMAND_ENTRIES 8192
 
+#define HISI_SAS_STATUS_BUF_SZ \
+		(sizeof(struct hisi_sas_err_record) + 1024)
+#define HISI_SAS_COMMAND_TABLE_SZ \
+		(((sizeof(union hisi_sas_command_table)+3)/4)*4)
+
+#define HISI_SAS_NAME_LEN 32
 
 struct hisi_sas_phy {
 	struct hisi_sas_port	*port;
@@ -36,6 +44,26 @@ struct hisi_sas_port {
 	struct asd_sas_port	sas_port;
 };
 
+
+struct hisi_sas_slot {
+	struct list_head entry;
+	struct sas_task *task;
+	struct hisi_sas_port	*port;
+	u64	n_elem;
+	int	dlvry_queue;
+	int	dlvry_queue_slot;
+	int	cmplt_queue;
+	int	cmplt_queue_slot;
+	int	idx;
+	void	*cmd_hdr;
+	dma_addr_t cmd_hdr_dma;
+	void	*status_buffer;
+	dma_addr_t status_buffer_dma;
+	void *command_table;
+	dma_addr_t command_table_dma;
+	struct hisi_sas_sge_page *sge_page;
+	dma_addr_t sge_page_dma;
+};
 struct hisi_hba {
 	spinlock_t	lock;
 
@@ -44,13 +72,189 @@ struct hisi_hba {
 
 	u8 sas_addr[SAS_ADDR_SIZE];
 
+	struct hisi_sas_cmd_hdr	*cmd_hdr[HISI_SAS_MAX_QUEUES];
+	dma_addr_t	cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
+	struct hisi_sas_complete_hdr	*complete_hdr[HISI_SAS_MAX_QUEUES];
+	dma_addr_t	complete_hdr_dma[HISI_SAS_MAX_QUEUES];
+
+	struct hisi_sas_initial_fis *initial_fis;
+	dma_addr_t	initial_fis_dma;
+
 	int	n_phy;
+
+	int slot_index_count;
+	unsigned long *slot_index_tags;
+
+	struct dma_pool *sge_page_pool;
+
 	/* SCSI/SAS glue */
 	struct sas_ha_struct sha;
 	struct Scsi_Host *shost;
 	struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
 	struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
+	int	id;
+	int	queue_count;
+	char	*int_names;
+	struct dma_pool *command_table_pool;
+	struct dma_pool *status_buffer_pool;
+	struct hisi_sas_itct *itct;
+	dma_addr_t itct_dma;
+	struct hisi_sas_iost *iost;
+	dma_addr_t iost_dma;
+	struct hisi_sas_breakpoint *breakpoint;
+	dma_addr_t breakpoint_dma;
+	struct hisi_sas_breakpoint *sata_breakpoint;
+	dma_addr_t sata_breakpoint_dma;
+	struct hisi_sas_slot	*slot_info;
+};
+
+/* Generic HW DMA host memory structures */
+/* Delivery queue header */
+struct hisi_sas_cmd_hdr {
+	/* dw0 */
+	__le32 dw0;
+
+	/* dw1 */
+	__le32 dw1;
+
+	/* dw2 */
+	__le32 dw2;
+
+	/* dw3 */
+	__le32 transfer_tags;
+
+	/* dw4 */
+	__le32 data_transfer_len;
+
+	/* dw5 */
+	__le32 first_burst_num;
+
+	/* dw6 */
+	__le32 sg_len;
+
+	/* dw7 */
+	__le32 dw7;
+
+	/* dw8 */
+	__le32 cmd_table_addr_lo;
+
+	/* dw9 */
+	__le32 cmd_table_addr_hi;
+
+	/* dw10 */
+	__le32 sts_buffer_addr_lo;
+
+	/* dw11 */
+	__le32 sts_buffer_addr_hi;
+
+	/* dw12 */
+	__le32 prd_table_addr_lo;
+
+	/* dw13 */
+	__le32 prd_table_addr_hi;
+
+	/* dw14 */
+	__le32 dif_prd_table_addr_lo;
+
+	/* dw15 */
+	__le32 dif_prd_table_addr_hi;
+};
+
+/* Completion queue header */
+struct hisi_sas_complete_hdr {
+	__le32 data;
+};
+
+struct hisi_sas_itct {
+	__le64 qw0;
+	__le64 sas_addr;
+	__le64 qw2;
+	__le64 qw3;
+	__le64 qw4;
+	__le64 qw_sata_ncq0_3;
+	__le64 qw_sata_ncq7_4;
+	__le64 qw_sata_ncq11_8;
+	__le64 qw_sata_ncq15_12;
+	__le64 qw_sata_ncq19_16;
+	__le64 qw_sata_ncq23_20;
+	__le64 qw_sata_ncq27_24;
+	__le64 qw_sata_ncq31_28;
+	__le64 qw_non_ncq_iptt;
+	__le64 qw_rsvd0;
+	__le64 qw_rsvd1;
+};
+
+struct hisi_sas_iost {
+	__le64 qw0;
+	__le64 qw1;
+	__le64 qw2;
+	__le64 qw3;
+};
+
+struct hisi_sas_err_record {
+	/* dw0 */
+	__le32 dma_err_type;
+
+	/* dw1 */
+	__le32 trans_tx_fail_type;
+
+	/* dw2 */
+	__le32 trans_rx_fail_type;
+
+	/* dw3 */
+	u32 rsvd;
+};
+
+struct hisi_sas_initial_fis {
+	struct hisi_sas_err_record err_record;
+	struct dev_to_host_fis fis;
+	u32 rsvd[3];
+};
+
+struct hisi_sas_breakpoint {
+	u8	data[128];	/*io128 byte*/
+};
+
+struct hisi_sas_sge {
+	__le32 addr_lo;
+	__le32 addr_hi;
+	__le32 page_ctrl_0;
+	__le32 page_ctrl_1;
+	__le32 data_len;
+	__le32 data_off;
+};
+
+struct hisi_sas_command_table_smp {
+	u8 bytes[44];
+};
+
+struct hisi_sas_command_table_stp {
+	struct	host_to_dev_fis command_fis;
+	u8	dummy[12];
+	u8	atapi_cdb[ATAPI_CDB_LEN];
 };
 
 #define HISI_SAS_SGE_PAGE_CNT SCSI_MAX_SG_SEGMENTS
+struct hisi_sas_sge_page {
+	struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
+};
+
+struct hisi_sas_command_table_ssp {
+	struct ssp_frame_hdr hdr;
+	union {
+		struct {
+			struct ssp_command_iu task;
+			u32 prot[6];
+		};
+		struct ssp_tmf_iu ssp_task;
+		struct xfer_rdy_iu xfer_rdy;
+		struct ssp_response_iu ssp_res;
+	} u;
+};
+
+union hisi_sas_command_table {
+	struct hisi_sas_command_table_ssp ssp;
+	struct hisi_sas_command_table_smp smp;
+	struct hisi_sas_command_table_stp stp;
+};
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 2cae458..0116782 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -35,6 +35,164 @@ static struct scsi_host_template hisi_sas_sht = {
 static struct sas_domain_function_template hisi_sas_transport_ops = {
 };
 
+static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
+{
+	int i, s;
+	char name[32];
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	for (i = 0; i < hisi_hba->queue_count; i++) {
+		/* Delivery queue */
+		s = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
+		hisi_hba->cmd_hdr[i] = dma_alloc_coherent(dev, s,
+					&hisi_hba->cmd_hdr_dma[i], GFP_KERNEL);
+		if (!hisi_hba->cmd_hdr[i])
+			goto err_out;
+		memset(hisi_hba->cmd_hdr[i], 0, s);
+
+		/* Completion queue */
+		s = sizeof(struct hisi_sas_complete_hdr) * HISI_SAS_QUEUE_SLOTS;
+		hisi_hba->complete_hdr[i] = dma_alloc_coherent(dev, s,
+				&hisi_hba->complete_hdr_dma[i], GFP_KERNEL);
+		if (!hisi_hba->complete_hdr[i])
+			goto err_out;
+		memset(hisi_hba->complete_hdr[i], 0, s);
+	}
+
+	sprintf(name, "%s%d", "hisi_sas_status_buffer_pool",
+		hisi_hba->id);
+	s = HISI_SAS_STATUS_BUF_SZ;
+	hisi_hba->status_buffer_pool = dma_pool_create(name,
+						       dev, s, 16, 0);
+	if (!hisi_hba->status_buffer_pool)
+		goto err_out;
+
+	sprintf(name, "%s%d", "hisi_sas_command_table_pool",
+		hisi_hba->id);
+	s = HISI_SAS_COMMAND_TABLE_SZ;
+	hisi_hba->command_table_pool = dma_pool_create(name,
+						       dev, s, 16, 0);
+	if (!hisi_hba->command_table_pool)
+		goto err_out;
+
+	s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
+	hisi_hba->itct = dma_alloc_coherent(dev, s, &hisi_hba->itct_dma,
+					    GFP_KERNEL);
+	if (!hisi_hba->itct)
+		goto err_out;
+
+	memset(hisi_hba->itct, 0, s);
+
+	hisi_hba->slot_info = devm_kcalloc(dev, HISI_SAS_COMMAND_ENTRIES,
+					   sizeof(struct hisi_sas_slot),
+					   GFP_KERNEL);
+	if (!hisi_hba->slot_info)
+		goto err_out;
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_iost);
+	hisi_hba->iost = dma_alloc_coherent(dev, s, &hisi_hba->iost_dma,
+					    GFP_KERNEL);
+	if (!hisi_hba->iost)
+		goto err_out;
+
+	memset(hisi_hba->iost, 0, s);
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint);
+	hisi_hba->breakpoint = dma_alloc_coherent(dev, s,
+				&hisi_hba->breakpoint_dma, GFP_KERNEL);
+	if (!hisi_hba->breakpoint)
+		goto err_out;
+
+	memset(hisi_hba->breakpoint, 0, s);
+
+	hisi_hba->slot_index_count = HISI_SAS_COMMAND_ENTRIES;
+	s = hisi_hba->slot_index_count / sizeof(unsigned long);
+	hisi_hba->slot_index_tags = devm_kzalloc(dev, s, GFP_KERNEL);
+	if (!hisi_hba->slot_index_tags)
+		goto err_out;
+
+	sprintf(name, "%s%d", "hisi_sas_status_sge_pool", hisi_hba->id);
+	hisi_hba->sge_page_pool = dma_pool_create(name, dev,
+				sizeof(struct hisi_sas_sge_page), 16, 0);
+	if (!hisi_hba->sge_page_pool)
+		goto err_out;
+
+	s = sizeof(struct hisi_sas_initial_fis) * HISI_SAS_MAX_PHYS;
+	hisi_hba->initial_fis = dma_alloc_coherent(dev, s,
+				&hisi_hba->initial_fis_dma, GFP_KERNEL);
+	if (!hisi_hba->initial_fis)
+		goto err_out;
+	memset(hisi_hba->initial_fis, 0, s);
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint) * 2;
+	hisi_hba->sata_breakpoint = dma_alloc_coherent(dev, s,
+				&hisi_hba->sata_breakpoint_dma, GFP_KERNEL);
+	if (!hisi_hba->sata_breakpoint)
+		goto err_out;
+	memset(hisi_hba->sata_breakpoint, 0, s);
+
+	return 0;
+err_out:
+	return -ENOMEM;
+}
+
+static void hisi_sas_free(struct hisi_hba *hisi_hba)
+{
+	int i, s;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	for (i = 0; i < hisi_hba->queue_count; i++) {
+		s = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
+		if (hisi_hba->cmd_hdr[i])
+			dma_free_coherent(dev, s,
+					  hisi_hba->cmd_hdr[i],
+					  hisi_hba->cmd_hdr_dma[i]);
+
+		s = sizeof(struct hisi_sas_complete_hdr) * HISI_SAS_QUEUE_SLOTS;
+		if (hisi_hba->complete_hdr[i])
+			dma_free_coherent(dev, s,
+					  hisi_hba->complete_hdr[i],
+					  hisi_hba->complete_hdr_dma[i]);
+	}
+
+	if (hisi_hba->status_buffer_pool)
+		dma_pool_destroy(hisi_hba->status_buffer_pool);
+
+	if (hisi_hba->command_table_pool)
+		dma_pool_destroy(hisi_hba->command_table_pool);
+
+	s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
+	if (hisi_hba->itct)
+		dma_free_coherent(dev, s,
+				  hisi_hba->itct, hisi_hba->itct_dma);
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_iost);
+	if (hisi_hba->iost)
+		dma_free_coherent(dev, s,
+				  hisi_hba->iost, hisi_hba->iost_dma);
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint);
+	if (hisi_hba->breakpoint)
+		dma_free_coherent(dev, s,
+				  hisi_hba->breakpoint,
+				  hisi_hba->breakpoint_dma);
+
+	if (hisi_hba->sge_page_pool)
+		dma_pool_destroy(hisi_hba->sge_page_pool);
+
+	s = sizeof(struct hisi_sas_initial_fis) * HISI_SAS_MAX_PHYS;
+	if (hisi_hba->initial_fis)
+		dma_free_coherent(dev, s,
+				  hisi_hba->initial_fis,
+				  hisi_hba->initial_fis_dma);
+
+	s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint) * 2;
+	if (hisi_hba->sata_breakpoint)
+		dma_free_coherent(dev, s,
+				  hisi_hba->sata_breakpoint,
+				  hisi_hba->sata_breakpoint_dma);
+}
+
 
 static const struct of_device_id sas_of_match[] = {
 	{ .compatible = "hisilicon,sas-controller-v1",},
@@ -55,8 +213,37 @@ static struct hisi_hba *hisi_sas_hba_alloc(
 		goto err_out;
 
 	hisi_hba->pdev = pdev;
+
+	if (of_property_read_u32(np, "phy-count", &hisi_hba->n_phy))
+		goto err_out;
+
+	if (of_property_read_u32(np, "queue-count", &hisi_hba->queue_count))
+		goto err_out;
+
+	if (of_property_read_u32(np, "controller-id", &hisi_hba->id))
+		goto err_out;
+
+	interrupt_count = of_property_count_u32_elems(np, "interrupts");
+	if (interrupt_count < 0)
+		goto err_out;
+
+	if (of_property_read_u32(np, "#interrupt-cells", &interrupt_cells))
+		goto err_out;
+
+	hisi_hba->int_names = devm_kcalloc(&pdev->dev,
+					   interrupt_count / interrupt_cells,
+					   HISI_SAS_NAME_LEN,
+					   GFP_KERNEL);
+	if (!hisi_hba->int_names)
+		goto err_out;
+
 	hisi_hba->shost = shost;
 
+	if (hisi_sas_alloc(hisi_hba, shost)) {
+		hisi_sas_free(hisi_hba);
+		goto err_out;
+	}
+
 	return hisi_hba;
 err_out:
 	dev_err(&pdev->dev, "hba alloc failed\n");
@@ -87,7 +274,7 @@ static int hisi_sas_probe(struct platform_device *pdev)
 	sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
 	platform_set_drvdata(pdev, sha);
 
-	phy_nr = port_nr = HISI_SAS_MAX_PHYS;
+	phy_nr = port_nr = hisi_hba->n_phy;
 
 	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
 	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
@@ -139,11 +326,13 @@ err_out_ha:
 static int hisi_sas_remove(struct platform_device *pdev)
 {
 	struct sas_ha_struct *sha = platform_get_drvdata(pdev);
+	struct hisi_hba *hisi_hba = (struct hisi_hba *)sha->lldd_ha;
 
 	sas_unregister_ha(sha);
 	sas_remove_host(sha->core.shost);
 	scsi_remove_host(sha->core.shost);
 
+	hisi_sas_free(hisi_hba);
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 06/25] scsi: hisi_sas: add slot init code

[John Garry]

Add functionality to init slot indexing.

Slot indexing is for the host to track which slots
(or tags) are free and which are used.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/Makefile        |  2 +-
 drivers/scsi/hisi_sas/hisi_sas.h      |  2 ++
 drivers/scsi/hisi_sas/hisi_sas_init.c |  2 ++
 drivers/scsi/hisi_sas/hisi_sas_main.c | 28 ++++++++++++++++++++++++++++
 4 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_main.c

diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index 63c3c4d..33f30e8 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,2 +1,2 @@
 obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
-hisi_sas-y+= hisi_sas_init.o
+hisi_sas-y+= hisi_sas_init.o hisi_sas_main.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 2c15036..929c513 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -257,4 +257,6 @@ union hisi_sas_command_table {
 	struct hisi_sas_command_table_smp smp;
 	struct hisi_sas_command_table_stp stp;
 };
+
+void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 0116782..38b9ed2 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -131,6 +131,8 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
 		goto err_out;
 	memset(hisi_hba->sata_breakpoint, 0, s);
 
+	hisi_sas_slot_index_init(hisi_hba);
+
 	return 0;
 err_out:
 	return -ENOMEM;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
new file mode 100644
index 0000000..721412e
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+
+
+static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx)
+{
+	void *bitmap = hisi_hba->slot_index_tags;
+
+	clear_bit(slot_idx, bitmap);
+}
+
+void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
+{
+	int i;
+
+	for (i = 0; i < hisi_hba->slot_index_count; ++i)
+		hisi_sas_slot_index_clear(hisi_hba, i);
+}
-- 
1.9.1

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[PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[John Garry]

This includes registers for core SAS controllers
and also SAS control registers.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h      |  2 ++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 25 +++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 929c513..5f72d98 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -69,6 +69,8 @@ struct hisi_hba {
 
 	struct platform_device *pdev;
 
+	void __iomem *regs;
+	void __iomem *ctrl_regs;
 
 	u8 sas_addr[SAS_ADDR_SIZE];
 
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 38b9ed2..8f1e856 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -195,6 +195,28 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
 				  hisi_hba->sata_breakpoint_dma);
 }
 
+int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
+{
+	struct platform_device *pdev = hisi_hba->pdev;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hisi_hba->regs = devm_ioremap(dev,
+				      res->start,
+				      resource_size(res));
+	if (!hisi_hba->regs)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	hisi_hba->ctrl_regs = devm_ioremap(dev,
+					   res->start,
+					   resource_size(res));
+	if (!hisi_hba->ctrl_regs)
+		return -ENOMEM;
+
+	return 0;
+}
 
 static const struct of_device_id sas_of_match[] = {
 	{ .compatible = "hisilicon,sas-controller-v1",},
@@ -241,6 +263,9 @@ static struct hisi_hba *hisi_sas_hba_alloc(
 
 	hisi_hba->shost = shost;
 
+	if (hisi_sas_ioremap(hisi_hba))
+		goto err_out;
+
 	if (hisi_sas_alloc(hisi_hba, shost)) {
 		hisi_sas_free(hisi_hba);
 		goto err_out;
-- 
1.9.1

[PATCH 08/25] scsi: hisi_sas: add cq structure initialization

[John Garry]

Each completion queue has a structure. This is mainly for
passing to irq handler so we know which queue the irq occured
on.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h      | 6 ++++++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 5f72d98..6c5d22a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -44,6 +44,10 @@ struct hisi_sas_port {
 	struct asd_sas_port	sas_port;
 };
 
+struct hisi_sas_cq {
+	struct hisi_hba *hisi_hba;
+	int	id;
+};
 
 struct hisi_sas_slot {
 	struct list_head entry;
@@ -92,6 +96,8 @@ struct hisi_hba {
 	/* SCSI/SAS glue */
 	struct sas_ha_struct sha;
 	struct Scsi_Host *shost;
+
+	struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
 	struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
 	struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
 	int	id;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 8f1e856..44fc524 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -42,6 +42,12 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
 	struct device *dev = &hisi_hba->pdev->dev;
 
 	for (i = 0; i < hisi_hba->queue_count; i++) {
+		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
+
+		/* Completion queue structure */
+		cq->id = i;
+		cq->hisi_hba = hisi_hba;
+
 		/* Delivery queue */
 		s = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
 		hisi_hba->cmd_hdr[i] = dma_alloc_coherent(dev, s,
-- 
1.9.1

[PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[John Garry]

This SAS ID is chosen as Huawei IEEE id: 001882

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas_init.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 44fc524..c295c39 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -283,6 +283,19 @@ err_out:
 	return NULL;
 }
 
+static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
+{
+	u8 i;
+
+	/* Huawei IEEE id (001882) */
+	for (i = 0; i < hisi_hba->n_phy; i++)
+		hisi_hba->phy[i].dev_sas_addr =
+			cpu_to_be64(0x5001882016072015ULL);
+
+	memcpy(hisi_hba->sas_addr, &hisi_hba->phy[0].dev_sas_addr,
+	       SAS_ADDR_SIZE);
+}
+
 static int hisi_sas_probe(struct platform_device *pdev)
 {
 	struct Scsi_Host *shost;
@@ -339,6 +352,8 @@ static int hisi_sas_probe(struct platform_device *pdev)
 		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
 		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
 	}
+
+	hisi_sas_init_add(hisi_hba);
 	rc = scsi_add_host(shost, &pdev->dev);
 	if (rc)
 		goto err_out_ha;
-- 
1.9.1

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[PATCH 10/25] scsi: hisi_sas: add misc HBA initialization

[John Garry]

This includes:
- host port structure initialisation
- host device structure initialisation
- wq initialisation
- host structure timer init
- DMA mask configuration
- call to scan host

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h      | 56 +++++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_init.c | 35 ++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_main.c | 31 +++++++++++++++++++
 3 files changed, 122 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 6c5d22a..1a26f27 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -35,13 +35,36 @@
 
 #define HISI_SAS_NAME_LEN 32
 
+
+enum dev_status {
+	HISI_SAS_DEV_NORMAL,
+	HISI_SAS_DEV_EH,
+};
+
 struct hisi_sas_phy {
+	struct hisi_hba	*hisi_hba;
 	struct hisi_sas_port	*port;
 	struct asd_sas_phy	sas_phy;
+	struct sas_identify	identify;
+	struct timer_list	timer;
+	u64		port_id; /* from hw */
+	u64		dev_sas_addr;
+	u64		phy_type;
+	u64		frame_rcvd_size;
+	u8		frame_rcvd[32];
+	u8		phy_attached;
+	u8		reserved[3];
+	u64		phy_event;
+	int		eye_diag_done;
+	enum sas_linkrate	minimum_linkrate;
+	enum sas_linkrate	maximum_linkrate;
 };
 
 struct hisi_sas_port {
 	struct asd_sas_port	sas_port;
+	u8	port_attached;
+	u8	id; /* from hw */
+	struct list_head	list;
 };
 
 struct hisi_sas_cq {
@@ -49,6 +72,18 @@ struct hisi_sas_cq {
 	int	id;
 };
 
+struct hisi_sas_device {
+	enum sas_device_type	dev_type;
+	struct hisi_hba		*hisi_hba;
+	struct domain_device	*sas_device;
+	u64 attached_phy;
+	u64 device_id;
+	u64 running_req;
+	struct hisi_sas_itct *itct;
+	u8 dev_status;
+	u64 reserved;
+};
+
 struct hisi_sas_slot {
 	struct list_head entry;
 	struct sas_task *task;
@@ -68,6 +103,19 @@ struct hisi_sas_slot {
 	struct hisi_sas_sge_page *sge_page;
 	dma_addr_t sge_page_dma;
 };
+
+enum hisi_sas_wq_event {
+	PHYUP,
+};
+
+struct hisi_sas_wq {
+	struct work_struct	work_struct;
+	struct hisi_hba *hisi_hba;
+	int phy_no;
+	int event;
+	int data;
+};
+
 struct hisi_hba {
 	spinlock_t	lock;
 
@@ -88,6 +136,10 @@ struct hisi_hba {
 
 	int	n_phy;
 
+
+	struct timer_list timer;
+	struct workqueue_struct *wq;
+
 	int slot_index_count;
 	unsigned long *slot_index_tags;
 
@@ -103,6 +155,8 @@ struct hisi_hba {
 	int	id;
 	int	queue_count;
 	char	*int_names;
+
+	struct hisi_sas_device	devices[HISI_SAS_MAX_DEVICES];
 	struct dma_pool *command_table_pool;
 	struct dma_pool *status_buffer_pool;
 	struct hisi_sas_itct *itct;
@@ -267,4 +321,6 @@ union hisi_sas_command_table {
 };
 
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
+void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
+void hisi_sas_wq_process(struct work_struct *work);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index c295c39..558e0e7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -41,6 +41,20 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
 	char name[32];
 	struct device *dev = &hisi_hba->pdev->dev;
 
+	spin_lock_init(&hisi_hba->lock);
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		hisi_sas_phy_init(hisi_hba, i);
+		hisi_hba->port[i].port_attached = 0;
+		hisi_hba->port[i].id = -1;
+		INIT_LIST_HEAD(&hisi_hba->port[i].list);
+	}
+
+	for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
+		hisi_hba->devices[i].dev_type = SAS_PHY_UNUSED;
+		hisi_hba->devices[i].device_id = i;
+		hisi_hba->devices[i].dev_status = HISI_SAS_DEV_NORMAL;
+	}
+
 	for (i = 0; i < hisi_hba->queue_count; i++) {
 		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
 
@@ -139,6 +153,13 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
 
 	hisi_sas_slot_index_init(hisi_hba);
 
+	sprintf(name, "%s%d", "hisi_sas", hisi_hba->id);
+	hisi_hba->wq = create_singlethread_workqueue(name);
+	if (!hisi_hba->wq) {
+		dev_err(dev, "sas_alloc: failed to create workqueue\n");
+		goto err_out;
+	}
+
 	return 0;
 err_out:
 	return -ENOMEM;
@@ -199,6 +220,9 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
 		dma_free_coherent(dev, s,
 				  hisi_hba->sata_breakpoint,
 				  hisi_hba->sata_breakpoint_dma);
+
+	if (hisi_hba->wq)
+		destroy_workqueue(hisi_hba->wq);
 }
 
 int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
@@ -244,6 +268,8 @@ static struct hisi_hba *hisi_sas_hba_alloc(
 
 	hisi_hba->pdev = pdev;
 
+	init_timer(&hisi_hba->timer);
+
 	if (of_property_read_u32(np, "phy-count", &hisi_hba->n_phy))
 		goto err_out;
 
@@ -320,6 +346,13 @@ static int hisi_sas_probe(struct platform_device *pdev)
 	sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
 	platform_set_drvdata(pdev, sha);
 
+	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) &&
+	    dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) {
+		dev_err(dev, "No usable DMA addressing method\n");
+		rc = -EIO;
+		goto err_out_ha;
+	}
+
 	phy_nr = port_nr = hisi_hba->n_phy;
 
 	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
@@ -362,6 +395,8 @@ static int hisi_sas_probe(struct platform_device *pdev)
 	if (rc)
 		goto err_out_register_ha;
 
+	scsi_scan_host(shost);
+
 	return 0;
 
 err_out_register_ha:
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 721412e..882ff79 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -26,3 +26,34 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 	for (i = 0; i < hisi_hba->slot_index_count; ++i)
 		hisi_sas_slot_index_clear(hisi_hba, i);
 }
+
+void hisi_sas_wq_process(struct work_struct *work)
+{
+	struct hisi_sas_wq *wq =
+		container_of(work, struct hisi_sas_wq, work_struct);
+
+	kfree(wq);
+}
+
+void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
+{
+	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+
+	phy->hisi_hba = hisi_hba;
+	phy->port = NULL;
+	init_timer(&phy->timer);
+	sas_phy->enabled = (phy_no < hisi_hba->n_phy) ? 1 : 0;
+	sas_phy->class = SAS;
+	sas_phy->iproto = SAS_PROTOCOL_ALL;
+	sas_phy->tproto = 0;
+	sas_phy->type = PHY_TYPE_PHYSICAL;
+	sas_phy->role = PHY_ROLE_INITIATOR;
+	sas_phy->oob_mode = OOB_NOT_CONNECTED;
+	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
+	sas_phy->id = phy_no;
+	sas_phy->sas_addr = &hisi_hba->sas_addr[0];
+	sas_phy->frame_rcvd = &phy->frame_rcvd[0];
+	sas_phy->ha = (struct sas_ha_struct *)hisi_hba->shost->hostdata;
+	sas_phy->lldd_phy = phy;
+}
-- 
1.9.1

[PATCH 11/25] scsi: hisi_sas: add v1 hardware register definitions

[John Garry]

Add definitions for v1 controller HW.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/Makefile         |   2 +-
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 402 +++++++++++++++++++++++++++++++++
 2 files changed, 403 insertions(+), 1 deletion(-)
 create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index 33f30e8..7cc6514 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,2 +1,2 @@
 obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
-hisi_sas-y+= hisi_sas_init.o hisi_sas_main.o
+hisi_sas-y+= hisi_sas_init.o hisi_sas_main.o hisi_sas_v1_hw.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
new file mode 100644
index 0000000..ccc7aa7
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+
+/* global registers need init*/
+#define DLVRY_QUEUE_ENABLE		0x0
+#define IOST_BASE_ADDR_LO		0x8
+#define IOST_BASE_ADDR_HI		0xc
+#define ITCT_BASE_ADDR_LO		0x10
+#define ITCT_BASE_ADDR_HI		0x14
+#define BROKEN_MSG_ADDR_LO		0x18
+#define BROKEN_MSG_ADDR_HI		0x1c
+#define PHY_CONTEXT			0x20
+#define PHY_STATE			0x24
+#define PHY_PORT_NUM_MA			0x28
+#define PORT_STATE			0x2c
+#define PHY_CONN_RATE			0x30
+#define HGC_TRANS_TASK_CNT_LIMIT	0x38
+#define AXI_AHB_CLK_CFG			0x3c
+#define HGC_SAS_TXFAIL_RETRY_CTRL	0x84
+#define HGC_GET_ITV_TIME		0x90
+#define DEVICE_MSG_WORK_MODE		0x94
+#define I_T_NEXUS_LOSS_TIME		0xa0
+#define BUS_INACTIVE_LIMIT_TIME		0xa8
+#define REJECT_TO_OPEN_LIMIT_TIME	0xac
+#define CFG_AGING_TIME			0xbc
+#define CFG_AGING_TIME_ITCT_REL_OFF	0
+#define CFG_AGING_TIME_ITCT_REL_MSK	(0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
+#define HGC_DFX_CFG2			0xc0
+#define FIS_LIST_BADDR_L		0xc4
+#define CFG_1US_TIMER_TRSH		0xcc
+#define CFG_SAS_CONFIG			0xd4
+#define HGC_IOST_ECC_ADDR		0x140
+#define HGC_IOST_ECC_ADDR_BAD_OFF	16
+#define HGC_IOST_ECC_ADDR_BAD_MSK	(0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
+#define HGC_DQ_ECC_ADDR			0x144
+#define HGC_DQ_ECC_ADDR_BAD_OFF		16
+#define HGC_DQ_ECC_ADDR_BAD_MSK		(0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
+#define HGC_INVLD_DQE_INFO		0x148
+#define HGC_INVLD_DQE_INFO_DQ_OFF	0
+#define HGC_INVLD_DQE_INFO_DQ_MSK	(0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
+#define HGC_INVLD_DQE_INFO_TYPE_OFF	16
+#define HGC_INVLD_DQE_INFO_TYPE_MSK	(0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
+#define HGC_INVLD_DQE_INFO_FORCE_OFF	17
+#define HGC_INVLD_DQE_INFO_FORCE_MSK	(0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
+#define HGC_INVLD_DQE_INFO_PHY_OFF	18
+#define HGC_INVLD_DQE_INFO_PHY_MSK	(0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
+#define HGC_INVLD_DQE_INFO_ABORT_OFF	19
+#define HGC_INVLD_DQE_INFO_ABORT_MSK	(0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
+#define HGC_INVLD_DQE_INFO_IPTT_OF_OFF	20
+#define HGC_INVLD_DQE_INFO_IPTT_OF_MSK	(0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
+#define HGC_INVLD_DQE_INFO_SSP_ERR_OFF	21
+#define HGC_INVLD_DQE_INFO_SSP_ERR_MSK	(0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
+#define HGC_INVLD_DQE_INFO_OFL_OFF	22
+#define HGC_INVLD_DQE_INFO_OFL_MSK	(0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
+#define HGC_ITCT_ECC_ADDR		0x150
+#define HGC_ITCT_ECC_ADDR_BAD_OFF	16
+#define HGC_ITCT_ECC_ADDR_BAD_MSK	(0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
+#define HGC_AXI_FIFO_ERR_INFO		0x154
+#define INT_COAL_EN			0x1bc
+#define OQ_INT_COAL_TIME		0x1c0
+#define OQ_INT_COAL_CNT			0x1c4
+#define ENT_INT_COAL_TIME		0x1c8
+#define ENT_INT_COAL_CNT		0x1cc
+#define OQ_INT_SRC			0x1d0
+#define OQ_INT_SRC_MSK			0x1d4
+#define ENT_INT_SRC1			0x1d8
+#define ENT_INT_SRC2			0x1dc
+#define ENT_INT_SRC2_DQ_CFG_ERR_OFF	25
+#define ENT_INT_SRC2_DQ_CFG_ERR_MSK	(0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
+#define ENT_INT_SRC2_CQ_CFG_ERR_OFF	27
+#define ENT_INT_SRC2_CQ_CFG_ERR_MSK	(0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
+#define ENT_INT_SRC2_AXI_WRONG_INT_OFF	28
+#define ENT_INT_SRC2_AXI_WRONG_INT_MSK	(0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
+#define ENT_INT_SRC2_AXI_OVERLF_INT_OFF	29
+#define ENT_INT_SRC2_AXI_OVERLF_INT_MSK	(0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
+#define ENT_INT_SRC_MSK1		0x1e0
+#define ENT_INT_SRC_MSK2		0x1e4
+#define SAS_ECC_INTR			0x1e8
+#define SAS_ECC_INTR_DQ_ECC1B_OFF	0
+#define SAS_ECC_INTR_DQ_ECC1B_MSK	(0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
+#define SAS_ECC_INTR_DQ_ECCBAD_OFF	1
+#define SAS_ECC_INTR_DQ_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
+#define SAS_ECC_INTR_IOST_ECC1B_OFF	2
+#define SAS_ECC_INTR_IOST_ECC1B_MSK	(0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
+#define SAS_ECC_INTR_IOST_ECCBAD_OFF	3
+#define SAS_ECC_INTR_IOST_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
+#define SAS_ECC_INTR_ITCT_ECC1B_OFF	4
+#define SAS_ECC_INTR_ITCT_ECC1B_MSK	(0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
+#define SAS_ECC_INTR_ITCT_ECCBAD_OFF	5
+#define SAS_ECC_INTR_ITCT_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
+#define SAS_ECC_INTR_MSK		0x1ec
+#define HGC_ERR_STAT_EN			0x238
+#define DLVRY_Q_0_BASE_ADDR_LO		0x260
+#define DLVRY_Q_0_BASE_ADDR_HI		0x264
+#define DLVRY_Q_0_DEPTH			0x268
+#define DLVRY_Q_0_WR_PTR		0x26c
+#define DLVRY_Q_0_RD_PTR		0x270
+#define COMPL_Q_0_BASE_ADDR_LO		0x4e0
+#define COMPL_Q_0_BASE_ADDR_HI		0x4e4
+#define COMPL_Q_0_DEPTH			0x4e8
+#define COMPL_Q_0_WR_PTR		0x4ec
+#define COMPL_Q_0_RD_PTR		0x4f0
+#define HGC_ECC_ERR			0x7d0
+
+/* phy registers need init */
+#define PORT_BASE			(0x800)
+
+#define PHY_CFG				(PORT_BASE + 0x0)
+#define PHY_CFG_ENA_OFF			0
+#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
+#define PHY_CFG_DC_OPT_OFF		2
+#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
+#define PROG_PHY_LINK_RATE		(PORT_BASE + 0xc)
+#define PROG_PHY_LINK_RATE_MAX_OFF	0
+#define PROG_PHY_LINK_RATE_MAX_MSK	(0xf << PROG_PHY_LINK_RATE_MAX_OFF)
+#define PROG_PHY_LINK_RATE_MIN_OFF	4
+#define PROG_PHY_LINK_RATE_MIN_MSK	(0xf << PROG_PHY_LINK_RATE_MIN_OFF)
+#define PROG_PHY_LINK_RATE_OOB_OFF	8
+#define PROG_PHY_LINK_RATE_OOB_MSK	(0xf << PROG_PHY_LINK_RATE_OOB_OFF)
+#define PHY_CTRL			(PORT_BASE + 0x14)
+#define PHY_CTRL_RESET_OFF		0
+#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
+#define PHY_RATE_NEGO			(PORT_BASE + 0x30)
+#define PHY_PCN				(PORT_BASE + 0x44)
+#define SL_TOUT_CFG			(PORT_BASE + 0x8c)
+#define SL_CONTROL			(PORT_BASE + 0x94)
+#define SL_CONTROL_NOTIFY_EN_OFF	0
+#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
+#define TX_ID_DWORD0			(PORT_BASE + 0x9c)
+#define TX_ID_DWORD1			(PORT_BASE + 0xa0)
+#define TX_ID_DWORD2			(PORT_BASE + 0xa4)
+#define TX_ID_DWORD3			(PORT_BASE + 0xa8)
+#define TX_ID_DWORD4			(PORT_BASE + 0xaC)
+#define TX_ID_DWORD5			(PORT_BASE + 0xb0)
+#define TX_ID_DWORD6			(PORT_BASE + 0xb4)
+#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
+#define RX_IDAF_DWORD1			(PORT_BASE + 0xc8)
+#define RX_IDAF_DWORD2			(PORT_BASE + 0xcc)
+#define RX_IDAF_DWORD3			(PORT_BASE + 0xd0)
+#define RX_IDAF_DWORD4			(PORT_BASE + 0xd4)
+#define RX_IDAF_DWORD5			(PORT_BASE + 0xd8)
+#define RX_IDAF_DWORD6			(PORT_BASE + 0xdc)
+#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
+#define DONE_RECEIVED_TIME		(PORT_BASE + 0x12c)
+#define CON_CFG_DRIVER			(PORT_BASE + 0x130)
+#define PHY_CONFIG2			(PORT_BASE + 0x1a8)
+#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF	3
+#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK	(0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
+#define PHY_CONFIG2_TX_TRAIN_COMP_OFF	24
+#define PHY_CONFIG2_TX_TRAIN_COMP_MSK	(0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
+#define CHL_INT0			(PORT_BASE + 0x1b0)
+#define CHL_INT0_PHYCTRL_NOTRDY_OFF	0
+#define CHL_INT0_PHYCTRL_NOTRDY_MSK	(0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
+#define CHL_INT0_SN_FAIL_NGR_OFF	2
+#define CHL_INT0_SN_FAIL_NGR_MSK	(0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
+#define CHL_INT0_DWS_LOST_OFF		4
+#define CHL_INT0_DWS_LOST_MSK		(0x1 << CHL_INT0_DWS_LOST_OFF)
+#define CHL_INT0_SL_IDAF_FAIL_OFF	10
+#define CHL_INT0_SL_IDAF_FAIL_MSK	(0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
+#define CHL_INT0_ID_TIMEOUT_OFF		11
+#define CHL_INT0_ID_TIMEOUT_MSK		(0x1 << CHL_INT0_ID_TIMEOUT_OFF)
+#define CHL_INT0_SL_OPAF_FAIL_OFF	12
+#define CHL_INT0_SL_OPAF_FAIL_MSK	(0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
+#define CHL_INT0_SL_PS_FAIL_OFF		21
+#define CHL_INT0_SL_PS_FAIL_MSK		(0x1 << CHL_INT0_SL_PS_FAIL_OFF)
+#define CHL_INT1			(PORT_BASE + 0x1b4)
+#define CHL_INT2			(PORT_BASE + 0x1b8)
+#define CHL_INT2_SL_RX_BC_ACK_OFF	2
+#define CHL_INT2_SL_RX_BC_ACK_MSK	(0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
+#define CHL_INT2_SL_PHY_ENA_OFF		6
+#define CHL_INT2_SL_PHY_ENA_MSK		(0x1 << CHL_INT2_SL_PHY_ENA_OFF)
+#define CHL_INT0_MSK			(PORT_BASE + 0x1bc)
+#define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF	0
+#define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK	(0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
+#define CHL_INT1_MSK			(PORT_BASE + 0x1c0)
+#define CHL_INT2_MSK			(PORT_BASE + 0x1c4)
+#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
+#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
+#define DMA_TX_STATUS_BUSY_OFF		0
+#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
+#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
+#define DMA_RX_STATUS_BUSY_OFF		0
+#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
+
+#define AXI_CFG				(0x5100)
+#define CONTROLLER_RESET_VALUE		(0x7ffff)
+
+/* HW dma structures */
+/* Delivery queue header */
+/* dw0 */
+#define CMD_HDR_RESP_REPORT_OFF		5
+#define CMD_HDR_RESP_REPORT_MSK		0x20
+#define CMD_HDR_TLR_CTRL_OFF		6
+#define CMD_HDR_TLR_CTRL_MSK		0xc0
+#define CMD_HDR_PORT_OFF		17
+#define CMD_HDR_PORT_MSK		0xe0000
+#define CMD_HDR_PRIORITY_OFF		27
+#define CMD_HDR_PRIORITY_MSK		0x8000000
+#define CMD_HDR_MODE_OFF		28
+#define CMD_HDR_MODE_MSK		0x10000000
+#define CMD_HDR_CMD_OFF			29
+#define CMD_HDR_CMD_MSK			0xe0000000
+/* dw1 */
+#define CMD_HDR_VERIFY_DTL_OFF		10
+#define CMD_HDR_VERIFY_DTL_MSK		0x400
+#define CMD_HDR_SSP_FRAME_TYPE_OFF	13
+#define CMD_HDR_SSP_FRAME_TYPE_MSK	0xe000
+#define CMD_HDR_DEVICE_ID_OFF		16
+#define CMD_HDR_DEVICE_ID_MSK		0xffff0000
+/* dw2 */
+#define CMD_HDR_CFL_OFF			0
+#define CMD_HDR_CFL_MSK			0x1ff
+#define CMD_HDR_MRFL_OFF		15
+#define CMD_HDR_MRFL_MSK		0xff8000
+#define CMD_HDR_FIRST_BURST_OFF		25
+#define CMD_HDR_FIRST_BURST_MSK		0x2000000
+/* dw3 */
+#define CMD_HDR_IPTT_OFF		0
+#define CMD_HDR_IPTT_MSK		0xffff
+/* dw6 */
+#define CMD_HDR_DATA_SGL_LEN_OFF	16
+#define CMD_HDR_DATA_SGL_LEN_MSK	0xffff0000
+
+/* Completion header */
+#define CMPLT_HDR_IPTT_OFF		0
+#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
+#define CMPLT_HDR_CMD_CMPLT_OFF		17
+#define CMPLT_HDR_CMD_CMPLT_MSK		(0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
+#define CMPLT_HDR_ERR_RCRD_XFRD_OFF	18
+#define CMPLT_HDR_ERR_RCRD_XFRD_MSK	(0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
+#define CMPLT_HDR_RSPNS_XFRD_OFF	19
+#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
+#define CMPLT_HDR_IO_CFG_ERR_OFF	27
+#define CMPLT_HDR_IO_CFG_ERR_MSK	(0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
+
+/* ITCT header */
+/* qw0 */
+#define ITCT_HDR_DEV_TYPE_OFF		0
+#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
+#define ITCT_HDR_VALID_OFF		2
+#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
+#define ITCT_HDR_BREAK_REPLY_ENA_OFF	3
+#define ITCT_HDR_BREAK_REPLY_ENA_MSK	(0x1 << ITCT_HDR_BREAK_REPLY_ENA_OFF)
+#define ITCT_HDR_AWT_CONTROL_OFF	4
+#define ITCT_HDR_AWT_CONTROL_MSK	(0x1 << ITCT_HDR_AWT_CONTROL_OFF)
+#define ITCT_HDR_MAX_CONN_RATE_OFF	5
+#define ITCT_HDR_MAX_CONN_RATE_MSK	(0xf << ITCT_HDR_MAX_CONN_RATE_OFF)
+#define ITCT_HDR_VALID_LINK_NUM_OFF	9
+#define ITCT_HDR_VALID_LINK_NUM_MSK	(0xf << ITCT_HDR_VALID_LINK_NUM_OFF)
+#define ITCT_HDR_PORT_ID_OFF		13
+#define ITCT_HDR_PORT_ID_MSK		(0x7 << ITCT_HDR_PORT_ID_OFF)
+#define ITCT_HDR_SMP_TIMEOUT_OFF	16
+#define ITCT_HDR_SMP_TIMEOUT_MSK	(0xffff << ITCT_HDR_SMP_TIMEOUT_OFF)
+#define ITCT_HDR_MAX_BURST_BYTES_OFF	16
+#define ITCT_HDR_MAX_BURST_BYTES_MSK	(0xffffffff << \
+					ITCT_MAX_BURST_BYTES_OFF)
+/* qw1 */
+#define ITCT_HDR_MAX_SAS_ADDR_OFF	0
+#define ITCT_HDR_MAX_SAS_ADDR_MSK	(0xffffffffffffffff << \
+					ITCT_HDR_MAX_SAS_ADDR_OFF)
+/* qw2 */
+#define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF	0
+#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK	(0xffff << \
+					ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
+#define ITCT_HDR_BUS_INACTIVE_TL_OFF	16
+#define ITCT_HDR_BUS_INACTIVE_TL_MSK	(0xffff << \
+					ITCT_HDR_BUS_INACTIVE_TL_OFF)
+#define ITCT_HDR_MAX_CONN_TL_OFF	32
+#define ITCT_HDR_MAX_CONN_TL_MSK	(0xffff << \
+					ITCT_HDR_MAX_CONN_TL_OFF)
+#define ITCT_HDR_REJ_OPEN_TL_OFF	48
+#define ITCT_HDR_REJ_OPEN_TL_MSK	(0xffff << \
+					ITCT_REJ_OPEN_TL_OFF)
+
+/* Err record header */
+#define ERR_HDR_DMA_TX_ERR_TYPE_OFF	0
+#define ERR_HDR_DMA_TX_ERR_TYPE_MSK	(0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
+#define ERR_HDR_DMA_RX_ERR_TYPE_OFF	16
+#define ERR_HDR_DMA_RX_ERR_TYPE_MSK	(0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
+
+enum {
+	HISI_SAS_PHY_BCAST_ACK = 0,
+	HISI_SAS_PHY_SL_PHY_ENABLED,
+	HISI_SAS_PHY_INT_ABNORMAL,
+	HISI_SAS_PHY_INT_NR
+};
+
+enum {
+	DMA_TX_ERR_BASE = 0x0,
+	DMA_RX_ERR_BASE = 0x100,
+	TRANS_TX_FAIL_BASE = 0x200,
+	TRANS_RX_FAIL_BASE = 0x300,
+
+	/* dma tx */
+	DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
+	DMA_TX_DIF_APP_ERR, /* 0x1 */
+	DMA_TX_DIF_RPP_ERR, /* 0x2 */
+	DMA_TX_AXI_BUS_ERR, /* 0x3 */
+	DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
+	DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
+	DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
+	DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
+	DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
+	DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
+
+	/* dma rx */
+	DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
+	DMA_RX_DIF_CRC_ERR, /* 0x101 */
+	DMA_RX_DIF_APP_ERR, /* 0x102 */
+	DMA_RX_DIF_RPP_ERR, /* 0x103 */
+	DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
+	DMA_RX_AXI_BUS_ERR, /* 0x105 */
+	DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
+	DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
+	DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
+	DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
+	DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
+	DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
+	DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
+
+	/* trans tx */
+	TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
+	TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
+	TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
+	TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
+	TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
+	TRANS_TX_RSVD1_ERR, /* 0x205 */
+	TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
+	TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
+	TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
+	TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
+	TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
+	TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
+	TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
+	TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
+	TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
+	TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
+	TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
+	TRANS_TX_RSVD2_ERR, /* 0x211 */
+	TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
+	TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
+	TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
+	TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
+	TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
+	TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
+	TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
+	TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
+	TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
+	TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
+	TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
+	TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
+	TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
+	TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
+
+	/* trans rx */
+	TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
+	TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
+	TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
+	TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
+	TRANS_RX_RSVD0_ERR, /* 0x304 */
+	TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
+	TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
+	TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
+	TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
+	TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
+	TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
+	TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
+	TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
+	TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
+	TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
+	TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
+	TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
+	TRANS_RX_BAD_HASH_ERR, /* 0x311 */
+	TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
+	TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
+	TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
+	TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
+	TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
+	TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
+	TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
+	TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
+	TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
+};
+
+#define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
+#define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
+#define HISI_SAS_FATAL_INT_NR (2)
+
+#define HISI_SAS_MAX_INT_NR \
+	(HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
+	HISI_SAS_FATAL_INT_NR)
+
-- 
1.9.1

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[PATCH 12/25] scsi: hisi_sas: add v1 HW initialisation code

[John Garry]

Add complete code to initialise HW to the point where
we can get a phy up interrupt when a disk is connected.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  10 +
 drivers/scsi/hisi_sas/hisi_sas_init.c  |  20 ++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 502 +++++++++++++++++++++++++++++++++
 3 files changed, 532 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 1a26f27..18fd30b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -34,7 +34,12 @@
 		(((sizeof(union hisi_sas_command_table)+3)/4)*4)
 
 #define HISI_SAS_NAME_LEN 32
+#define HISI_SAS_RESET_REG_CNT 5
 
+enum {
+	PORT_TYPE_SAS = (1U << 1),
+	PORT_TYPE_SATA = (1U << 0),
+};
 
 enum dev_status {
 	HISI_SAS_DEV_NORMAL,
@@ -123,6 +128,7 @@ struct hisi_hba {
 
 	void __iomem *regs;
 	void __iomem *ctrl_regs;
+	u32 reset_reg[HISI_SAS_RESET_REG_CNT];
 
 	u8 sas_addr[SAS_ADDR_SIZE];
 
@@ -323,4 +329,8 @@ union hisi_sas_command_table {
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 void hisi_sas_wq_process(struct work_struct *work);
+extern int interrupt_init_v1_hw(struct hisi_hba *hisi_hba);
+extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
+extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
+extern int phys_init_v1_hw(struct hisi_hba *hisi_hba);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 558e0e7..67bfa58 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -270,6 +270,11 @@ static struct hisi_hba *hisi_sas_hba_alloc(
 
 	init_timer(&hisi_hba->timer);
 
+	if (of_property_read_u32_array(np, "reset-reg",
+				       (u32 *) &hisi_hba->reset_reg,
+				       HISI_SAS_RESET_REG_CNT))
+		goto err_out;
+
 	if (of_property_read_u32(np, "phy-count", &hisi_hba->n_phy))
 		goto err_out;
 
@@ -387,6 +392,21 @@ static int hisi_sas_probe(struct platform_device *pdev)
 	}
 
 	hisi_sas_init_add(hisi_hba);
+
+	rc = hw_init_v1_hw(hisi_hba);
+	if (rc)
+		goto err_out_ha;
+
+	rc = interrupt_init_v1_hw(hisi_hba);
+	if (rc)
+		goto err_out_ha;
+
+	rc = interrupt_openall_v1_hw(hisi_hba);
+	if (rc)
+		goto err_out_ha;
+
+	phys_init_v1_hw(hisi_hba);
+
 	rc = scsi_add_host(shost, &pdev->dev);
 	if (rc)
 		goto err_out_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index ccc7aa7..20291b4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -400,3 +400,505 @@ enum {
 	(HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
 	HISI_SAS_FATAL_INT_NR)
 
+static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
+{
+	void __iomem *regs = hisi_hba->regs + off;
+
+	return readl(regs);
+}
+
+static void hisi_sas_write32(struct hisi_hba *hisi_hba,
+				    u32 off, u32 val)
+{
+	void __iomem *regs = hisi_hba->regs + off;
+
+	writel(val, regs);
+}
+
+static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
+					int phy_no, u32 off, u32 val)
+{
+	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+	writel(val, regs);
+}
+
+static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
+				      int phy_no, u32 off)
+{
+	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+	return readl(regs);
+}
+
+static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+	cfg &= ~PHY_CFG_DC_OPT_MSK;
+	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
+	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
+
+	cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
+	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
+}
+
+static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	struct sas_identify_frame identify_frame;
+	u32 *identify_buffer;
+
+	memset(&identify_frame, 0, sizeof(identify_frame));
+	identify_frame.dev_type = SAS_END_DEVICE;
+	identify_frame.frame_type = 0;
+	identify_frame._un1 = 1;
+	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
+	identify_frame.target_bits = SAS_PROTOCOL_NONE;
+	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
+	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
+	identify_frame.phy_id = phy_no;
+	identify_buffer = (u32 *)(&identify_frame);
+
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
+			__swab32(identify_buffer[0]));
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
+			identify_buffer[2]);
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
+			identify_buffer[1]);
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
+			identify_buffer[4]);
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
+			identify_buffer[3]);
+	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
+			__swab32(identify_buffer[5]));
+}
+
+static void init_id_frame_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i;
+
+	for (i = 0; i < hisi_hba->n_phy; i++)
+		config_id_frame_v1_hw(hisi_hba, i);
+}
+
+static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i;
+	unsigned long end_time;
+	u32 reg_val;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
+
+		phy_ctrl |= PHY_CTRL_RESET_MSK;
+		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
+	}
+	msleep(1); /* It is safe to wait for 50us */
+
+	/* Ensure DMA tx & rx idle */
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		u32 dma_tx_status, dma_rx_status;
+
+		end_time = jiffies + msecs_to_jiffies(1000);
+
+		while (1) {
+			dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
+							    DMA_TX_STATUS);
+			dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
+							    DMA_RX_STATUS);
+
+			if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
+				!(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
+				break;
+
+			msleep(20);
+			if (time_after(jiffies, end_time))
+				return -EIO;
+		}
+	}
+
+	/* Ensure axi bus idle */
+	end_time = jiffies + msecs_to_jiffies(1000);
+	while (1) {
+		u32 axi_status =
+			hisi_sas_read32(hisi_hba, AXI_CFG);
+
+		if (axi_status == 0)
+			break;
+
+		msleep(20);
+		if (time_after(jiffies, end_time))
+			return -EIO;
+	}
+
+	/* Apply reset */
+	writel(CONTROLLER_RESET_VALUE,
+	       hisi_hba->ctrl_regs + hisi_hba->reset_reg[0]);
+	writel(CONTROLLER_RESET_VALUE,
+	       hisi_hba->ctrl_regs + hisi_hba->reset_reg[1]);
+	msleep(1);
+	reg_val = readl(hisi_hba->ctrl_regs + hisi_hba->reset_reg[2]);
+	if (CONTROLLER_RESET_VALUE != (reg_val & CONTROLLER_RESET_VALUE)) {
+		dev_err(dev, "Reset failed\n");
+		return -EIO;
+	}
+
+	/* De-reset */
+	writel(CONTROLLER_RESET_VALUE,
+	       hisi_hba->ctrl_regs + hisi_hba->reset_reg[3]);
+	writel(CONTROLLER_RESET_VALUE,
+	       hisi_hba->ctrl_regs + hisi_hba->reset_reg[4]);
+	msleep(1);
+	reg_val = readl(hisi_hba->ctrl_regs + hisi_hba->reset_reg[2]);
+	if (reg_val & CONTROLLER_RESET_VALUE) {
+		dev_err(dev, "De-reset failed\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i;
+
+	/* Global registers init*/
+	hisi_sas_write32(hisi_hba,
+		DLVRY_QUEUE_ENABLE,
+		(u32)((1ULL << hisi_hba->queue_count) - 1));
+	hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
+	hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
+	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
+	hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
+	hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
+	hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
+	hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
+	hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
+	hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
+	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
+	hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
+	hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
+	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
+	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
+	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
+	hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
+	hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
+	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
+	hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
+	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
+	hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
+	hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
+		hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
+		hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
+		hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
+
+		hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
+		hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
+		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
+		hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
+		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
+		hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
+	}
+
+	for (i = 0; i < hisi_hba->queue_count; i++) {
+		/* Delivery queue */
+		hisi_sas_write32(hisi_hba,
+				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
+				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+		hisi_sas_write32(hisi_hba,
+				 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
+				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+		hisi_sas_write32(hisi_hba,
+				 DLVRY_Q_0_DEPTH + (i * 0x14),
+				 HISI_SAS_QUEUE_SLOTS);
+
+		/* Completion queue */
+		hisi_sas_write32(hisi_hba,
+				 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
+				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+		hisi_sas_write32(hisi_hba,
+				 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
+				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
+				 HISI_SAS_QUEUE_SLOTS);
+	}
+
+	/* itct */
+	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
+			 lower_32_bits(hisi_hba->itct_dma));
+
+	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
+			 upper_32_bits(hisi_hba->itct_dma));
+
+	/* iost */
+	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
+			 lower_32_bits(hisi_hba->iost_dma));
+
+	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
+			 upper_32_bits(hisi_hba->iost_dma));
+
+	/* breakpoint */
+	hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
+			 lower_32_bits(hisi_hba->breakpoint_dma));
+
+	hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
+			 upper_32_bits(hisi_hba->breakpoint_dma));
+}
+
+int hw_init_v1_hw(struct hisi_hba *hisi_hba)
+{
+	struct device *dev = &hisi_hba->pdev->dev;
+	int rc;
+
+	rc = reset_hw_v1_hw(hisi_hba);
+	if (rc) {
+		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
+		return rc;
+	}
+
+	msleep(100);
+	init_reg_v1_hw(hisi_hba);
+
+	init_id_frame_v1_hw(hisi_hba);
+
+	return 0;
+}
+
+void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+	cfg |= PHY_CFG_ENA_MSK;
+	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+
+static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	config_id_frame_v1_hw(hisi_hba, phy_no);
+	config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
+	config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
+	enable_phy_v1_hw(hisi_hba, phy_no);
+}
+
+static void start_phys_v1_hw(unsigned long data)
+{
+	struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
+	int i;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
+		start_phy_v1_hw(hisi_hba, i);
+	}
+}
+
+static void phys_up_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
+		hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
+	}
+}
+
+static int start_phy_layer_v1_hw(struct hisi_hba *hisi_hba)
+{
+	struct timer_list *timer = &hisi_hba->timer;
+
+	setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba);
+	mod_timer(timer, jiffies + HZ);
+
+	return 0;
+}
+
+int phys_init_v1_hw(struct hisi_hba *hisi_hba)
+{
+	phys_up_v1_hw(hisi_hba);
+	start_phy_layer_v1_hw(hisi_hba);
+
+	return 0;
+}
+
+/* Interrupts */
+static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
+{
+	struct hisi_sas_phy *phy = p;
+	struct hisi_hba *hisi_hba = phy->hisi_hba;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+	int phy_no = sas_phy->id;
+	u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
+	struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
+	u32 irq_value, context, port_id, link_rate;
+	int i;
+	irqreturn_t res = IRQ_HANDLED;
+
+	irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
+
+	if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
+		dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
+			irq_value);
+		res = IRQ_NONE;
+		goto end;
+	}
+
+	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
+	if (context & 1 << phy_no) {
+		dev_err(dev, "phyup: phy%d SATA attached equipment\n",
+			phy_no);
+		goto end;
+	}
+
+	port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
+		  & 0xf;
+	if (port_id == 0xf) {
+		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
+		res = IRQ_NONE;
+		goto end;
+	}
+
+	for (i = 0; i < 6; i++) {
+		u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
+					RX_IDAF_DWORD0 + (i * 4));
+		frame_rcvd[i] = __swab32(idaf);
+	}
+
+	/* Get the linkrate */
+	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
+	link_rate = (link_rate >> (phy_no * 4)) & 0xf;
+	sas_phy->linkrate = link_rate;
+	sas_phy->oob_mode = SAS_OOB_MODE;
+	memcpy(sas_phy->attached_sas_addr,
+		&id->sas_addr, SAS_ADDR_SIZE);
+	dev_info(dev, "phyup: phy%d id=%d link_rate=%d\n",
+		 phy_no, hisi_hba->id, link_rate);
+	phy->port_id = port_id;
+	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
+	phy->phy_type |= PORT_TYPE_SAS;
+	phy->phy_attached = 1;
+	phy->identify.device_type = id->dev_type;
+	phy->frame_rcvd_size =	sizeof(struct sas_identify_frame);
+	if (phy->identify.device_type == SAS_END_DEVICE)
+		phy->identify.target_port_protocols =
+			SAS_PROTOCOL_SSP;
+	else if (phy->identify.device_type != SAS_PHY_UNUSED)
+		phy->identify.target_port_protocols =
+			SAS_PROTOCOL_SMP;
+
+
+end:
+	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
+			CHL_INT2_SL_PHY_ENA_MSK);
+
+	if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
+		u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
+
+		chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
+		hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
+		hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
+	}
+
+	return res;
+}
+
+
+static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
+	{"Phy Up"},
+};
+
+
+static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
+	int_phyup_v1_hw,
+};
+
+int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i, j, irq, rc, id = hisi_hba->id;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct device_node *np = dev->of_node;
+	char *int_names = hisi_hba->int_names;
+
+	if (!np)
+		return -ENOENT;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
+
+		for (j = 0; j < HISI_SAS_PHY_INT_NR; j++) {
+			int idx = (i * HISI_SAS_PHY_INT_NR) + j;
+
+			irq = irq_of_parse_and_map(np, idx);
+			if (!irq) {
+				dev_err(dev, "irq init: [%d] fail map phy interrupt %d\n",
+					hisi_hba->id, idx);
+				return -ENOENT;
+			}
+
+			(void)snprintf(&int_names[idx * HISI_SAS_NAME_LEN],
+					HISI_SAS_NAME_LEN,
+					DRV_NAME" %s [%d %d]", phy_int_names[j],
+					id, i);
+			rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
+					&int_names[idx * HISI_SAS_NAME_LEN],
+					phy);
+			if (rc) {
+				dev_err(dev, "irq init: [%d] could not request "
+					"phy interrupt %d, rc=%d\n",
+					hisi_hba->id, irq, rc);
+				return -ENOENT;
+			}
+		}
+	}
+
+
+	return 0;
+}
+
+int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int i;
+	u32 val;
+
+	for (i = 0; i < hisi_hba->n_phy; i++) {
+		/* Clear interrupt status */
+		val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
+		val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
+		val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
+
+		/* Unmask interrupt */
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
+		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
+
+		/* bypass chip bug mask abnormal intr */
+		hisi_sas_phy_write32(hisi_hba,
+				     i,
+				     CHL_INT0_MSK,
+				     0x3fffff &
+				     ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
+	}
+
+	return 0;
+}
-- 
1.9.1

[PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  1 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 55 ++++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 24 +++++++++++++++
 3 files changed, 80 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 18fd30b..802c000 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -333,4 +333,5 @@ extern int interrupt_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int phys_init_v1_hw(struct hisi_hba *hisi_hba);
+extern void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 882ff79..72831db 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -27,10 +27,65 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 		hisi_sas_slot_index_clear(hisi_hba, i);
 }
 
+
+void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
+{
+	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+	struct sas_ha_struct *sas_ha;
+
+	if (!phy->phy_attached)
+		return;
+
+	sas_ha = &hisi_hba->sha;
+	sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
+
+	if (sas_phy->phy) {
+		struct sas_phy *sphy = sas_phy->phy;
+
+		sphy->negotiated_linkrate = sas_phy->linkrate;
+		sphy->minimum_linkrate = phy->minimum_linkrate;
+		sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
+		sphy->maximum_linkrate = phy->maximum_linkrate;
+	}
+
+	if (phy->phy_type & PORT_TYPE_SAS) {
+		struct sas_identify_frame *id;
+
+		id = (struct sas_identify_frame *)phy->frame_rcvd;
+		id->dev_type = phy->identify.device_type;
+		id->initiator_bits = SAS_PROTOCOL_ALL;
+		id->target_bits = phy->identify.target_port_protocols;
+	} else if (phy->phy_type & PORT_TYPE_SATA) {
+		/*Nothing*/
+	}
+
+	sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
+
+	sas_ha->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
+}
+
+
+static void hisi_sas_phyup_work(struct hisi_hba *hisi_hba,
+				      int phy_no)
+{
+	sl_notify_v1_hw(hisi_hba, phy_no); /* This requires a sleep */
+	hisi_sas_bytes_dmaed(hisi_hba, phy_no);
+}
+
 void hisi_sas_wq_process(struct work_struct *work)
 {
 	struct hisi_sas_wq *wq =
 		container_of(work, struct hisi_sas_wq, work_struct);
+	struct hisi_hba *hisi_hba = wq->hisi_hba;
+	int event = wq->event;
+	int phy_no = wq->phy_no;
+
+	switch (event) {
+	case PHYUP:
+		hisi_sas_phyup_work(hisi_hba, phy_no);
+		break;
+	}
 
 	kfree(wq);
 }
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 20291b4..df56b3a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -738,6 +738,19 @@ int phys_init_v1_hw(struct hisi_hba *hisi_hba)
 	return 0;
 }
 
+void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	u32 sl_control;
+
+	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
+	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+	msleep(1);
+	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
+	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+}
+
 /* Interrupts */
 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
 {
@@ -750,6 +763,7 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
 	struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
 	u32 irq_value, context, port_id, link_rate;
 	int i;
+	struct hisi_sas_wq *wq = NULL;
 	irqreturn_t res = IRQ_HANDLED;
 
 	irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
@@ -804,6 +818,16 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
 		phy->identify.target_port_protocols =
 			SAS_PROTOCOL_SMP;
 
+	wq = kmalloc(sizeof(*wq), GFP_ATOMIC);
+	if (!wq)
+		goto end;
+
+	wq->event = PHYUP;
+	wq->hisi_hba = hisi_hba;
+	wq->phy_no = phy_no;
+
+	INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
+	queue_work(hisi_hba->wq, &wq->work_struct);
 
 end:
 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
-- 
1.9.1

[PATCH 14/25] scsi: hisi_sas: add ssp command function

[John Garry]

Add path to send ssp command to HW.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  23 +++
 drivers/scsi/hisi_sas/hisi_sas_init.c  |   1 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 246 +++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 206 +++++++++++++++++++++++++++
 4 files changed, 476 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 802c000..908baf3 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -33,6 +33,7 @@
 #define HISI_SAS_COMMAND_TABLE_SZ \
 		(((sizeof(union hisi_sas_command_table)+3)/4)*4)
 
+#define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
 #define HISI_SAS_NAME_LEN 32
 #define HISI_SAS_RESET_REG_CNT 5
 
@@ -109,6 +110,20 @@ struct hisi_sas_slot {
 	dma_addr_t sge_page_dma;
 };
 
+struct hisi_sas_tmf_task {
+	u8 tmf;
+	u16 tag_of_task_to_be_managed;
+};
+
+struct hisi_sas_tei {
+	struct sas_task	*task;
+	struct hisi_sas_cmd_hdr	*hdr;
+	struct hisi_sas_port	*port;
+	struct hisi_sas_slot	*slot;
+	int	n_elem;
+	int	iptt;
+};
+
 enum hisi_sas_wq_event {
 	PHYUP,
 };
@@ -158,9 +173,11 @@ struct hisi_hba {
 	struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
 	struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
 	struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
+
 	int	id;
 	int	queue_count;
 	char	*int_names;
+	struct hisi_sas_slot	*slot_prep;
 
 	struct hisi_sas_device	devices[HISI_SAS_MAX_DEVICES];
 	struct dma_pool *command_table_pool;
@@ -328,7 +345,13 @@ union hisi_sas_command_table {
 
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
+int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
 void hisi_sas_wq_process(struct work_struct *work);
+extern void start_delivery_v1_hw(struct hisi_hba *hisi_hba);
+extern int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s);
+extern int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
+			  struct hisi_sas_tei *tei, int is_tmf,
+			  struct hisi_sas_tmf_task *tmf);
 extern int interrupt_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 67bfa58..c681b21 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -33,6 +33,7 @@ static struct scsi_host_template hisi_sas_sht = {
 };
 
 static struct sas_domain_function_template hisi_sas_transport_ops = {
+	.lldd_execute_task	= hisi_sas_queue_command,
 };
 
 static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 72831db..3a82262 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -12,6 +12,14 @@
 #include "hisi_sas.h"
 
 
+#define DEV_IS_GONE(dev) \
+	((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
+
+static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
+{
+	return device->port->ha->lldd_ha;
+}
+
 static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx)
 {
 	void *bitmap = hisi_hba->slot_index_tags;
@@ -19,6 +27,31 @@ static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx)
 	clear_bit(slot_idx, bitmap);
 }
 
+static void hisi_sas_slot_index_free(struct hisi_hba *hisi_hba, int slot_idx)
+{
+	hisi_sas_slot_index_clear(hisi_hba, slot_idx);
+}
+
+static void hisi_sas_slot_index_set(struct hisi_hba *hisi_hba, int slot_idx)
+{
+	void *bitmap = hisi_hba->slot_index_tags;
+
+	set_bit(slot_idx, bitmap);
+}
+
+static int hisi_sas_slot_index_alloc(struct hisi_hba *hisi_hba, int *slot_idx)
+{
+	unsigned int index;
+	void *bitmap = hisi_hba->slot_index_tags;
+
+	index = find_first_zero_bit(bitmap, hisi_hba->slot_index_count);
+	if (index >= hisi_hba->slot_index_count)
+		return -SAS_QUEUE_FULL;
+	hisi_sas_slot_index_set(hisi_hba, index);
+	*slot_idx = index;
+	return 0;
+}
+
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 {
 	int i;
@@ -28,6 +61,214 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 }
 
 
+static int hisi_sas_task_prep_ssp(struct hisi_hba *hisi_hba,
+				  struct hisi_sas_tei *tei, int is_tmf,
+				  struct hisi_sas_tmf_task *tmf)
+{
+	return prep_ssp_v1_hw(hisi_hba, tei, is_tmf, tmf);
+}
+
+static int hisi_sas_task_prep(struct sas_task *task,
+				struct hisi_hba *hisi_hba,
+				int is_tmf, struct hisi_sas_tmf_task *tmf,
+				int *pass)
+{
+	struct domain_device *device = task->dev;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_sas_tei tei;
+	struct hisi_sas_slot *slot;
+	struct hisi_sas_cmd_hdr	*cmd_hdr_base;
+	struct device *dev = &hisi_hba->pdev->dev;
+	int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
+
+	if (!device->port) {
+		struct task_status_struct *tsm = &task->task_status;
+
+		tsm->resp = SAS_TASK_UNDELIVERED;
+		tsm->stat = SAS_PHY_DOWN;
+		/*
+		 * libsas will use dev->port, should
+		 * not call task_done for sata
+		 */
+		if (device->dev_type != SAS_SATA_DEV)
+			task->task_done(task);
+		return 0;
+	}
+
+	if (DEV_IS_GONE(sas_dev)) {
+		if (sas_dev)
+			dev_info(dev, "task prep: device %llu not ready\n",
+				 sas_dev->device_id);
+		else
+			dev_info(dev, "task prep: device %016llx not ready\n",
+				 SAS_ADDR(device->sas_addr));
+
+		rc = SAS_PHY_DOWN;
+		return rc;
+	}
+	tei.port = device->port->lldd_port;
+	if (tei.port && !tei.port->port_attached && !tmf) {
+		if (sas_protocol_ata(task->task_proto)) {
+			struct task_status_struct *ts = &task->task_status;
+
+			dev_info(dev,
+				 "task prep: SATA/STP port%d not attach device\n",
+				 device->port->id);
+			ts->resp = SAS_TASK_COMPLETE;
+			ts->stat = SAS_PHY_DOWN;
+			task->task_done(task);
+		} else {
+			struct task_status_struct *ts = &task->task_status;
+
+			dev_info(dev,
+				 "task prep: SAS port%d does not attach device\n",
+				 device->port->id);
+			ts->resp = SAS_TASK_UNDELIVERED;
+			ts->stat = SAS_PHY_DOWN;
+			task->task_done(task);
+		}
+		return 0;
+	}
+
+	if (!sas_protocol_ata(task->task_proto)) {
+		if (task->num_scatter) {
+			n_elem = dma_map_sg(dev,
+					task->scatter,
+					task->num_scatter,
+					task->data_dir);
+			if (!n_elem) {
+				rc = -ENOMEM;
+				goto prep_out;
+			}
+		}
+	} else {
+		n_elem = task->num_scatter;
+	}
+
+	rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
+	if (rc)
+		goto err_out;
+	rc = get_free_slot_v1_hw(hisi_hba,
+				 &dlvry_queue,
+				 &dlvry_queue_slot);
+	if (rc)
+		goto err_out_tag;
+
+	slot = &hisi_hba->slot_info[slot_idx];
+	memset(slot, 0, sizeof(struct hisi_sas_slot));
+
+	task->lldd_task = NULL;
+	slot->idx = slot_idx;
+	tei.iptt = slot_idx;
+	slot->n_elem = n_elem;
+	slot->dlvry_queue = dlvry_queue;
+	slot->dlvry_queue_slot = dlvry_queue_slot;
+	cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];
+	slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];
+
+	slot->status_buffer = dma_pool_alloc(hisi_hba->status_buffer_pool,
+					     GFP_ATOMIC,
+					     &slot->status_buffer_dma);
+	if (!slot->status_buffer)
+		goto err_out_slot_buf;
+	memset(slot->status_buffer, 0, HISI_SAS_STATUS_BUF_SZ);
+
+	slot->command_table = dma_pool_alloc(hisi_hba->command_table_pool,
+					     GFP_ATOMIC,
+					     &slot->command_table_dma);
+	if (!slot->command_table)
+		goto err_out_status_buf;
+	memset(slot->command_table, 0, HISI_SAS_COMMAND_TABLE_SZ);
+	memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));
+
+	tei.hdr = slot->cmd_hdr;
+	tei.task = task;
+	tei.n_elem = n_elem;
+	tei.slot = slot;
+	switch (task->task_proto) {
+	case SAS_PROTOCOL_SSP:
+		rc = hisi_sas_task_prep_ssp(hisi_hba, &tei, is_tmf, tmf);
+		break;
+	case SAS_PROTOCOL_SMP:
+	case SAS_PROTOCOL_SATA:
+	case SAS_PROTOCOL_STP:
+	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+	default:
+		dev_err(dev, "task prep: unknown/unsupported proto (0x%x)\n",
+			task->task_proto);
+		rc = -EINVAL;
+		break;
+	}
+
+	if (rc) {
+		dev_err(dev, "task prep: rc = 0x%x\n", rc);
+		if (slot->sge_page)
+			goto err_out_sge;
+		goto err_out_command_table;
+	}
+
+	slot->task = task;
+	slot->port = tei.port;
+	task->lldd_task = slot;
+	list_add_tail(&slot->entry, &tei.port->list);
+	spin_lock(&task->task_state_lock);
+	task->task_state_flags |= SAS_TASK_AT_INITIATOR;
+	spin_unlock(&task->task_state_lock);
+
+	hisi_hba->slot_prep = slot;
+
+	sas_dev->running_req++;
+	++(*pass);
+
+	return rc;
+
+err_out_sge:
+	dma_pool_free(hisi_hba->sge_page_pool, slot->sge_page,
+		slot->sge_page_dma);
+err_out_command_table:
+	dma_pool_free(hisi_hba->command_table_pool, slot->command_table,
+		slot->command_table_dma);
+err_out_status_buf:
+	dma_pool_free(hisi_hba->status_buffer_pool, slot->status_buffer,
+		slot->status_buffer_dma);
+err_out_slot_buf:
+	/* Nothing to be done */
+err_out_tag:
+	hisi_sas_slot_index_free(hisi_hba, slot_idx);
+err_out:
+	dev_err(dev, "task prep: failed[%d]!\n", rc);
+	if (!sas_protocol_ata(task->task_proto))
+		if (n_elem)
+			dma_unmap_sg(dev, task->scatter, n_elem,
+				     task->data_dir);
+prep_out:
+	return rc;
+}
+
+static int hisi_sas_task_exec(struct sas_task *task,
+	gfp_t gfp_flags,
+	struct completion *completion,
+	int is_tmf,
+	struct hisi_sas_tmf_task *tmf)
+{
+	u32 rc;
+	u32 pass = 0;
+	unsigned long flags = 0;
+	struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	spin_lock_irqsave(&hisi_hba->lock, flags);
+	rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass);
+	if (rc)
+		dev_err(dev, "task exec: failed[%d]!\n", rc);
+
+	if (likely(pass))
+		start_delivery_v1_hw(hisi_hba);
+	spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+	return rc;
+}
+
 void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
 {
 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
@@ -112,3 +353,8 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
 	sas_phy->ha = (struct sas_ha_struct *)hisi_hba->shost->hostdata;
 	sas_phy->lldd_phy = phy;
 }
+
+int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
+{
+	return hisi_sas_task_exec(task, gfp_flags, NULL, 0, NULL);
+}
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index df56b3a..6e54054 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -407,6 +407,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 	return readl(regs);
 }
 
+static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
+{
+	void __iomem *regs = hisi_hba->regs + off;
+
+	return readl_relaxed(regs);
+}
+
 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
 				    u32 off, u32 val)
 {
@@ -751,6 +758,205 @@ void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 }
 
+/**
+ * This function allocates across all queues to load balance.
+ * It uses the current cpu as the method to balance the
+ * queues.
+ *
+ * The callpath to this function and upto writing the write
+ * queue pointer should be safe from interruption.
+ */
+int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s)
+{
+	struct device *dev = &hisi_hba->pdev->dev;
+	u32 r, w;
+	int queue = smp_processor_id() % hisi_hba->queue_count;
+
+	while (1) {
+		w = hisi_sas_read32_relaxed(hisi_hba,
+				    DLVRY_Q_0_WR_PTR + (queue * 0x14));
+		r = hisi_sas_read32_relaxed(hisi_hba,
+				    DLVRY_Q_0_RD_PTR + (queue * 0x14));
+
+		if (r == w+1 % HISI_SAS_QUEUE_SLOTS) {
+			dev_warn(dev, "delivery queue%d full, r=%d w=%d\n",
+				 queue, r, w);
+			queue = (queue + 1) % hisi_hba->queue_count;
+			continue;
+		}
+		break;
+	}
+
+	*q = queue;
+	*s = w;
+
+	return 0;
+}
+
+void start_delivery_v1_hw(struct hisi_hba *hisi_hba)
+{
+	int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
+	int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
+
+	hisi_sas_write32(hisi_hba,
+			 DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
+			 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
+}
+
+static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
+				 struct hisi_sas_slot *slot,
+				 struct hisi_sas_cmd_hdr *hdr,
+				 struct scatterlist *scatter,
+				 int n_elem)
+{
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct scatterlist *sg;
+	int i;
+
+	if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
+		dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
+			n_elem);
+		return -EINVAL;
+	}
+
+	slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
+					&slot->sge_page_dma);
+	if (!slot->sge_page)
+		return -ENOMEM;
+
+	for_each_sg(scatter, sg, n_elem, i) {
+		struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
+
+		entry->addr_lo = cpu_to_le32(lower_32_bits(sg_dma_address(sg)));
+		entry->addr_hi = cpu_to_le32(upper_32_bits(sg_dma_address(sg)));
+		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
+		entry->data_len = cpu_to_le32(sg_dma_len(sg));
+		entry->data_off = 0;
+	}
+
+	hdr->prd_table_addr_lo =
+		cpu_to_le32(lower_32_bits(slot->sge_page_dma));
+	hdr->prd_table_addr_hi =
+		cpu_to_le32(upper_32_bits(slot->sge_page_dma));
+
+	hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
+
+	return 0;
+}
+
+
+int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
+		   struct hisi_sas_tei *tei, int is_tmf,
+		   struct hisi_sas_tmf_task *tmf)
+{
+	struct sas_task *task = tei->task;
+	struct hisi_sas_cmd_hdr *hdr = tei->hdr;
+	struct domain_device *device = task->dev;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_sas_port *port = tei->port;
+	struct sas_ssp_task *ssp_task = &task->ssp_task;
+	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
+	int has_data = 0, rc;
+	struct hisi_sas_slot *slot = tei->slot;
+	u8 *buf_cmd, fburst = 0;
+	int priority = is_tmf;
+	u32 dw1, dw2;
+
+	/* create header */
+	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
+			       (0x2 << CMD_HDR_TLR_CTRL_OFF) |
+			       (port->id << CMD_HDR_PORT_OFF) |
+			       (priority << CMD_HDR_PRIORITY_OFF) |
+			       (1 << CMD_HDR_MODE_OFF) | /* ini mode */
+			       (1 << CMD_HDR_CMD_OFF)); /* ssp */
+
+	dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
+
+	if (is_tmf) {
+		dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+	} else {
+		switch (scsi_cmnd->sc_data_direction) {
+		case DMA_TO_DEVICE:
+			dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+			has_data = 1;
+			break;
+		case DMA_FROM_DEVICE:
+			dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+			has_data = 1;
+			break;
+		default:
+			dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+		}
+	}
+
+	/* map itct entry */
+	dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
+	hdr->dw1 = cpu_to_le32(dw1);
+
+	if (is_tmf) {
+		dw2 = ((sizeof(struct ssp_tmf_iu) +
+			sizeof(struct ssp_frame_hdr)+3)/4) <<
+			CMD_HDR_CFL_OFF;
+	} else {
+		dw2 = ((sizeof(struct ssp_command_iu) +
+			sizeof(struct ssp_frame_hdr)+3)/4) <<
+			CMD_HDR_CFL_OFF;
+	}
+
+	dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
+
+	hdr->transfer_tags = cpu_to_le32(tei->iptt << CMD_HDR_IPTT_OFF);
+
+	if (has_data) {
+		rc = prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
+					tei->n_elem);
+		if (rc)
+			return rc;
+	}
+
+	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+
+	hdr->cmd_table_addr_lo =
+			cpu_to_le32(lower_32_bits(slot->command_table_dma));
+	hdr->cmd_table_addr_hi =
+			cpu_to_le32(upper_32_bits(slot->command_table_dma));
+
+	hdr->sts_buffer_addr_lo =
+			cpu_to_le32(lower_32_bits(slot->status_buffer_dma));
+	hdr->sts_buffer_addr_hi =
+			cpu_to_le32(upper_32_bits(slot->status_buffer_dma));
+
+	buf_cmd = (u8 *)slot->command_table + sizeof(struct ssp_frame_hdr);
+	if (task->ssp_task.enable_first_burst) {
+		fburst = (1 << 7);
+		dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
+	}
+	hdr->dw2 = cpu_to_le32(dw2);
+
+	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
+	if (!is_tmf) {
+		buf_cmd[9] = fburst | task->ssp_task.task_attr |
+				(task->ssp_task.task_prio << 3);
+		memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
+				task->ssp_task.cmd->cmd_len);
+	} else {
+		buf_cmd[10] = tmf->tmf;
+		switch (tmf->tmf) {
+		case TMF_ABORT_TASK:
+		case TMF_QUERY_TASK:
+			buf_cmd[12] =
+				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
+			buf_cmd[13] =
+				tmf->tag_of_task_to_be_managed & 0xff;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return 0;
+}
+
 /* Interrupts */
 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
 {
-- 
1.9.1

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[PATCH 15/25] scsi: hisi_sas: add cq interrupt handler

[John Garry]

Add cq interrupt handler and also slot error handler
function.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |   4 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  |  46 +++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 327 +++++++++++++++++++++++++++++++++
 3 files changed, 377 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 908baf3..976964f 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -347,6 +347,10 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
 void hisi_sas_wq_process(struct work_struct *work);
+void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
+			struct hisi_sas_slot *slot);
+
+/* hw specific functions */
 extern void start_delivery_v1_hw(struct hisi_hba *hisi_hba);
 extern int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s);
 extern int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 3a82262..74084c2 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -60,6 +60,52 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 		hisi_sas_slot_index_clear(hisi_hba, i);
 }
 
+void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
+			struct sas_task *task,
+			struct hisi_sas_slot *slot)
+{
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	if (!slot->task)
+		return;
+
+	if (!sas_protocol_ata(task->task_proto))
+		if (slot->n_elem)
+			dma_unmap_sg(dev, task->scatter, slot->n_elem,
+				     task->data_dir);
+
+	switch (task->task_proto) {
+	case SAS_PROTOCOL_SMP:
+		break;
+
+	case SAS_PROTOCOL_SATA:
+	case SAS_PROTOCOL_STP:
+	case SAS_PROTOCOL_SSP:
+	default:
+		/* do nothing */
+		break;
+	}
+
+	if (slot->command_table)
+		dma_pool_free(hisi_hba->command_table_pool,
+			      slot->command_table, slot->command_table_dma);
+
+	if (slot->status_buffer)
+		dma_pool_free(hisi_hba->status_buffer_pool,
+			      slot->status_buffer, slot->status_buffer_dma);
+
+	if (slot->sge_page)
+		dma_pool_free(hisi_hba->sge_page_pool, slot->sge_page,
+			slot->sge_page_dma);
+
+	list_del_init(&slot->entry);
+	task->lldd_task = NULL;
+	slot->task = NULL;
+	slot->port = NULL;
+	hisi_sas_slot_index_free(hisi_hba, slot->idx);
+	memset(slot, 0, sizeof(*slot));
+}
+
 
 static int hisi_sas_task_prep_ssp(struct hisi_hba *hisi_hba,
 				  struct hisi_sas_tei *tei, int is_tmf,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 6e54054..4cb0e1b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -957,6 +957,257 @@ int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 	return 0;
 }
 
+/* by default, task resp is complete */
+static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
+			   struct sas_task *task,
+			   struct hisi_sas_slot *slot)
+{
+	struct task_status_struct *tstat = &task->task_status;
+	struct hisi_sas_err_record *err_record = slot->status_buffer;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	switch (task->task_proto) {
+	case SAS_PROTOCOL_SSP:
+	{
+		int error = -1;
+		u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
+		u32 dma_tx_err_type = ((dma_err_type &
+					ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
+					ERR_HDR_DMA_TX_ERR_TYPE_OFF;
+		u32 dma_rx_err_type = ((dma_err_type &
+					ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
+					ERR_HDR_DMA_RX_ERR_TYPE_OFF;
+		u32 trans_tx_fail_type =
+				cpu_to_le32(err_record->trans_tx_fail_type);
+		u32 trans_rx_fail_type =
+				cpu_to_le32(err_record->trans_rx_fail_type);
+
+		if (dma_tx_err_type) {
+			/* dma tx err */
+			error = ffs(dma_tx_err_type)
+				- 1 + DMA_TX_ERR_BASE;
+		} else if (dma_rx_err_type) {
+			/* dma rx err */
+			error = ffs(dma_rx_err_type)
+				- 1 + DMA_RX_ERR_BASE;
+		} else if (trans_tx_fail_type) {
+			/* trans tx err */
+			error = ffs(trans_tx_fail_type)
+				- 1 + TRANS_TX_FAIL_BASE;
+		} else if (trans_rx_fail_type) {
+			/* trans rx err */
+			error = ffs(trans_rx_fail_type)
+				- 1 + TRANS_RX_FAIL_BASE;
+		}
+
+		switch (error) {
+		case DMA_TX_DATA_UNDERFLOW_ERR:
+		case DMA_RX_DATA_UNDERFLOW_ERR:
+		{
+			tstat->residual = 0;
+			tstat->stat = SAS_DATA_UNDERRUN;
+
+			break;
+		}
+		case DMA_TX_DATA_SGL_OVERFLOW_ERR:
+		case DMA_TX_DIF_SGL_OVERFLOW_ERR:
+		case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
+		case DMA_RX_DATA_OVERFLOW_ERR:
+		case TRANS_RX_FRAME_OVERRUN_ERR:
+		case TRANS_RX_LINK_BUF_OVERRUN_ERR:
+		{
+			tstat->stat = SAS_DATA_OVERRUN;
+			tstat->residual = 0;
+			break;
+		}
+		case TRANS_TX_PHY_NOT_ENABLE_ERR:
+		{
+			tstat->stat = SAS_PHY_DOWN;
+			tstat->resp = SAS_TASK_UNDELIVERED;
+			break;
+		}
+		case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
+		case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
+		case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
+		case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
+		case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
+		case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
+		case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
+		case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
+		case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
+		case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
+		case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
+		case TRANS_TX_OPEN_RETRY_ERR:
+		{
+			tstat->stat = SAS_OPEN_REJECT;
+			tstat->open_rej_reason = SAS_OREJ_UNKNOWN;
+			break;
+		}
+		case TRANS_TX_OPEN_TIMEOUT_ERR:
+		{
+			tstat->stat = SAS_OPEN_TO;
+			break;
+		}
+		case TRANS_TX_NAK_RECEIVE_ERR:
+		case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
+		{
+			tstat->stat = SAS_NAK_R_ERR;
+			break;
+		}
+		default:
+		{
+			tstat->stat = SAM_STAT_CHECK_CONDITION;
+			break;
+		}
+		}
+	}
+		break;
+	case SAS_PROTOCOL_SMP:
+	case SAS_PROTOCOL_SATA:
+	case SAS_PROTOCOL_STP:
+	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+	{
+		dev_err(dev, "slot err: SMP/SATA/STP not supported");
+	}
+		break;
+	default:
+		break;
+	}
+
+}
+
+int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
+			struct hisi_sas_slot *slot,
+			int abort)
+{
+	struct sas_task *task = slot->task;
+	struct hisi_sas_device *sas_dev;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct task_status_struct *tstat;
+	struct domain_device *device;
+	enum exec_status sts;
+	struct hisi_sas_complete_hdr *complete_queue =
+			hisi_hba->complete_hdr[slot->cmplt_queue];
+	struct hisi_sas_complete_hdr *complete_hdr;
+	u32 cmplt_hdr_data;
+
+	complete_hdr = &complete_queue[slot->cmplt_queue_slot];
+	cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
+
+	if (unlikely(!task || !task->lldd_task || !task->dev))
+		return -1;
+
+	tstat = &task->task_status;
+	device = task->dev;
+	sas_dev = device->lldd_dev;
+
+	task->task_state_flags &=
+		~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
+	task->task_state_flags |= SAS_TASK_STATE_DONE;
+
+	memset(tstat, 0, sizeof(*tstat));
+	tstat->resp = SAS_TASK_COMPLETE;
+
+	if (unlikely(!sas_dev || abort)) {
+		if (!sas_dev)
+			dev_dbg(dev, "slot complete: port has not device\n");
+		tstat->stat = SAS_PHY_DOWN;
+		goto out;
+	}
+
+	if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
+		u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq type err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
+			dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
+				slot->cmplt_queue, slot->cmplt_queue_slot);
+
+		tstat->resp = SAS_TASK_UNDELIVERED;
+		tstat->stat = SAS_OPEN_REJECT;
+		tstat->open_rej_reason = SAS_OREJ_UNKNOWN;
+		goto out;
+	}
+
+	if (!(cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK)) {
+		if (!(cmplt_hdr_data & CMPLT_HDR_CMD_CMPLT_MSK) ||
+		    !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
+			tstat->stat = SAS_DATA_OVERRUN;
+			goto out;
+		}
+	} else {
+		slot_err_v1_hw(hisi_hba, task, slot);
+		goto out;
+	}
+
+	switch (task->task_proto) {
+	case SAS_PROTOCOL_SSP:
+	{
+		struct ssp_response_iu *iu = slot->status_buffer +
+			sizeof(struct hisi_sas_err_record);
+		sas_ssp_task_response(dev, task, iu);
+		break;
+	}
+	case SAS_PROTOCOL_SMP:
+		dev_err(dev, "slot complete: SMP not supported");
+		break;
+	case SAS_PROTOCOL_SATA:
+	case SAS_PROTOCOL_STP:
+	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+		dev_err(dev, "slot complete: SATA/STP not supported");
+		break;
+
+	default:
+		tstat->stat = SAM_STAT_CHECK_CONDITION;
+		break;
+	}
+
+	if (!slot->port->port_attached) {
+		dev_err(dev, "slot complete: port %d has removed\n",
+			slot->port->sas_port.id);
+		tstat->stat = SAS_PHY_DOWN;
+	}
+
+out:
+	if (sas_dev && sas_dev->running_req)
+		sas_dev->running_req--;
+
+	hisi_sas_slot_task_free(hisi_hba, task, slot);
+	sts = tstat->stat;
+
+	if (task->task_done)
+		task->task_done(task);
+
+	return sts;
+}
+
 /* Interrupts */
 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
 {
@@ -1051,10 +1302,63 @@ end:
 }
 
 
+
+static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
+{
+	struct hisi_sas_cq *cq = p;
+	struct hisi_hba *hisi_hba = cq->hisi_hba;
+	struct hisi_sas_slot *slot;
+	int queue = cq->id;
+	struct hisi_sas_complete_hdr *complete_queue =
+			(struct hisi_sas_complete_hdr *)
+			hisi_hba->complete_hdr[queue];
+	u32 irq_value;
+	u32 rd_point, wr_point;
+
+	irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
+
+	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
+
+	rd_point = hisi_sas_read32(hisi_hba,
+			COMPL_Q_0_RD_PTR + (0x14 * queue));
+	wr_point = hisi_sas_read32(hisi_hba,
+			COMPL_Q_0_WR_PTR + (0x14 * queue));
+
+	while (rd_point != wr_point) {
+		struct hisi_sas_complete_hdr *complete_hdr;
+		int iptt, slot_idx;
+		u32 cmplt_hdr_data;
+
+		complete_hdr = &complete_queue[rd_point];
+		cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
+		iptt = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
+			CMPLT_HDR_IPTT_OFF;
+		slot_idx = iptt;
+		slot = &hisi_hba->slot_info[slot_idx];
+
+		/* The completion queue and queue slot index are not
+		 * necessarily the same as the delivery queue and
+		 * queue slot index.
+		 */
+		slot->cmplt_queue_slot = rd_point;
+		slot->cmplt_queue = queue;
+		slot_complete_v1_hw(hisi_hba, slot, 0);
+
+		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
+			rd_point = 0;
+	}
+
+	/* update rd_point */
+	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
+
+	return IRQ_HANDLED;
+}
+
 static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 	{"Phy Up"},
 };
 
+static const char cq_int_name[32] = "cq";
 
 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
 	int_phyup_v1_hw,
@@ -1099,6 +1403,29 @@ int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
 		}
 	}
 
+	for (i = 0; i < hisi_hba->queue_count; i++) {
+		int idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + i;
+
+		irq = irq_of_parse_and_map(np, idx);
+		if (!irq) {
+			dev_err(dev, "irq init: [%d] could not map cq interrupt %d\n",
+				hisi_hba->id, idx);
+			return -ENOENT;
+		}
+		(void)snprintf(&int_names[idx * HISI_SAS_NAME_LEN],
+				HISI_SAS_NAME_LEN,
+				DRV_NAME" %s [%d %d]", cq_int_name, id, i);
+		rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
+				      &int_names[idx * HISI_SAS_NAME_LEN],
+				      &hisi_hba->cq[i]);
+		if (rc) {
+			dev_err(dev, "irq init: [%d] could not request cq interrupt %d, rc=%d\n",
+				hisi_hba->id, irq, rc);
+			return -ENOENT;
+		}
+		idx++;
+	}
+
 
 	return 0;
 }
-- 
1.9.1

[PATCH 16/25] scsi: hisi_sas: add dev_found and port_formed

[John Garry]

Add functions to deal with lldd_dev_found and lldd_port_formed.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  12 ++++
 drivers/scsi/hisi_sas/hisi_sas_init.c  |   2 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 125 +++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c |  41 +++++++++++
 4 files changed, 180 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 976964f..3516d6f 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -47,6 +47,12 @@ enum dev_status {
 	HISI_SAS_DEV_EH,
 };
 
+enum hisi_sas_dev_type {
+	HISI_SAS_DEV_TYPE_STP = 0,
+	HISI_SAS_DEV_TYPE_SSP,
+	HISI_SAS_DEV_TYPE_SATA,
+};
+
 struct hisi_sas_phy {
 	struct hisi_hba	*hisi_hba;
 	struct hisi_sas_port	*port;
@@ -345,12 +351,16 @@ union hisi_sas_command_table {
 
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
+int hisi_sas_dev_found(struct domain_device *dev);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
+void hisi_sas_port_formed(struct asd_sas_phy *sas_phy);
 void hisi_sas_wq_process(struct work_struct *work);
 void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
 			struct hisi_sas_slot *slot);
 
 /* hw specific functions */
+extern void hisi_sas_setup_itct_v1_hw(struct hisi_hba *hisi_hba,
+				      struct hisi_sas_device *device);
 extern void start_delivery_v1_hw(struct hisi_hba *hisi_hba);
 extern int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s);
 extern int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
@@ -361,4 +371,6 @@ extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int phys_init_v1_hw(struct hisi_hba *hisi_hba);
 extern void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
+extern void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
+			     struct hisi_sas_device *device);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index c681b21..703527b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -33,7 +33,9 @@ static struct scsi_host_template hisi_sas_sht = {
 };
 
 static struct sas_domain_function_template hisi_sas_transport_ops = {
+	.lldd_dev_found		= hisi_sas_dev_found,
 	.lldd_execute_task	= hisi_sas_queue_command,
+	.lldd_port_formed	= hisi_sas_port_formed,
 };
 
 static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 74084c2..44cb9085 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -11,6 +11,9 @@
 
 #include "hisi_sas.h"
 
+#define DEV_IS_EXPANDER(type) \
+	((type == SAS_EDGE_EXPANDER_DEVICE) || \
+	(type == SAS_FANOUT_EXPANDER_DEVICE))
 
 #define DEV_IS_GONE(dev) \
 	((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
@@ -352,6 +355,79 @@ void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
 	sas_ha->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
 }
 
+struct hisi_sas_device *hisi_sas_alloc_dev(struct hisi_hba *hisi_hba)
+{
+	int dev_id;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	for (dev_id = 0; dev_id < HISI_SAS_MAX_DEVICES; dev_id++) {
+		if (hisi_hba->devices[dev_id].dev_type == SAS_PHY_UNUSED) {
+			hisi_hba->devices[dev_id].device_id = dev_id;
+			return &hisi_hba->devices[dev_id];
+		}
+	}
+
+	dev_err(dev, "alloc dev: max support %d devices - could not alloc\n",
+		HISI_SAS_MAX_DEVICES);
+
+	return NULL;
+}
+
+int hisi_sas_dev_found_notify(struct domain_device *device, int lock)
+{
+	unsigned long flags = 0;
+	int res = 0;
+	struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
+	struct domain_device *parent_dev = device->parent;
+	struct hisi_sas_device *sas_dev;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	if (lock)
+		spin_lock_irqsave(&hisi_hba->lock, flags);
+
+	sas_dev = hisi_sas_alloc_dev(hisi_hba);
+	if (!sas_dev) {
+		res = -EINVAL;
+		goto found_out;
+	}
+
+	device->lldd_dev = sas_dev;
+	sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+	sas_dev->dev_type = device->dev_type;
+	sas_dev->hisi_hba = hisi_hba;
+	sas_dev->sas_device = device;
+	setup_itct_v1_hw(hisi_hba, sas_dev);
+
+	if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
+		int phy_no;
+		u8 phy_num = parent_dev->ex_dev.num_phys;
+		struct ex_phy *phy;
+
+		for (phy_no = 0; phy_no < phy_num; phy_no++) {
+			phy = &parent_dev->ex_dev.ex_phy[phy_no];
+			if (SAS_ADDR(phy->attached_sas_addr) ==
+				SAS_ADDR(device->sas_addr)) {
+				sas_dev->attached_phy = phy_no;
+				break;
+			}
+		}
+
+		if (phy_no == phy_num) {
+			dev_info(dev,
+				 "dev found: no attached "
+				 "dev:%016llx at ex:%016llx\n",
+				 SAS_ADDR(device->sas_addr),
+				SAS_ADDR(parent_dev->sas_addr));
+			res = -EINVAL;
+		}
+	}
+
+found_out:
+	if (lock)
+		spin_unlock_irqrestore(&hisi_hba->lock, flags);
+	return res;
+}
+
 
 static void hisi_sas_phyup_work(struct hisi_hba *hisi_hba,
 				      int phy_no)
@@ -400,7 +476,56 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
 	sas_phy->lldd_phy = phy;
 }
 
+void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
+{
+	struct sas_ha_struct *sas_ha = sas_phy->ha;
+	struct hisi_hba *hisi_hba = NULL;
+	int i = 0;
+	struct hisi_sas_phy *phy = sas_phy->lldd_phy;
+	struct asd_sas_port *sas_port = sas_phy->port;
+	struct hisi_sas_port *port;
+	unsigned long flags = 0;
+
+	if (!sas_port)
+		return;
+
+	while (sas_ha->sas_phy[i]) {
+		if (sas_ha->sas_phy[i] == sas_phy) {
+			hisi_hba = (struct hisi_hba *)sas_ha->lldd_ha;
+			port = &hisi_hba->port[i];
+			break;
+		}
+		i++;
+	}
+
+	if (hisi_hba == NULL) {
+		pr_err("%s: could not find hba\n", __func__);
+		return;
+	}
+
+	if (lock)
+		spin_lock_irqsave(&hisi_hba->lock, flags);
+	port->port_attached = 1;
+	port->id = phy->port_id;
+	phy->port = port;
+	sas_port->lldd_port = port;
+
+	if (lock)
+		spin_unlock_irqrestore(&hisi_hba->lock, flags);
+}
+
+
+int hisi_sas_dev_found(struct domain_device *device)
+{
+	return hisi_sas_dev_found_notify(device, 1);
+}
+
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
 {
 	return hisi_sas_task_exec(task, gfp_flags, NULL, 0, NULL);
 }
+
+void hisi_sas_port_formed(struct asd_sas_phy *sas_phy)
+{
+	hisi_sas_port_notify_formed(sas_phy, 1);
+}
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 4cb0e1b..e8b9dc3 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -493,6 +493,47 @@ static void init_id_frame_v1_hw(struct hisi_hba *hisi_hba)
 		config_id_frame_v1_hw(hisi_hba, i);
 }
 
+void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
+		      struct hisi_sas_device *sas_dev)
+{
+	struct domain_device *device = sas_dev->sas_device;
+	struct device *dev = &hisi_hba->pdev->dev;
+	u64 qw0, device_id = sas_dev->device_id;
+	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
+
+	memset(itct, 0, sizeof(*itct));
+
+	/* qw0 */
+	qw0 = 0;
+	switch (sas_dev->dev_type) {
+	case SAS_END_DEVICE:
+	case SAS_EDGE_EXPANDER_DEVICE:
+	case SAS_FANOUT_EXPANDER_DEVICE:
+		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
+		break;
+	default:
+		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
+			 sas_dev->dev_type);
+	}
+
+	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
+		(1 << ITCT_HDR_AWT_CONTROL_OFF) |
+		(device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
+		(1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
+		(device->port->id << ITCT_HDR_PORT_ID_OFF));
+	itct->qw0 = cpu_to_le64(qw0);
+
+	/* qw1 */
+	memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+	itct->sas_addr = __swab64(itct->sas_addr);
+
+	/* qw2 */
+	itct->qw2 = cpu_to_le64((500 < ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
+				(0xff00 < ITCT_HDR_BUS_INACTIVE_TL_OFF) |
+				(0xff00 < ITCT_HDR_MAX_CONN_TL_OFF) |
+				(0xff00 < ITCT_HDR_REJ_OPEN_TL_OFF));
+}
+
 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
 {
 	int i;
-- 
1.9.1

[PATCH 17/25] scsi: hisi_sas: add abnormal irq handler

[John Garry]

Add abnormal irq handler. This handler is concerned with
phy down event.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  1 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 24 +++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 56 ++++++++++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 3516d6f..3f61a4a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -354,6 +354,7 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_dev_found(struct domain_device *dev);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
 void hisi_sas_port_formed(struct asd_sas_phy *sas_phy);
+void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
 void hisi_sas_wq_process(struct work_struct *work);
 void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
 			struct hisi_sas_slot *slot);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 44cb9085..fbc2cca 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -529,3 +529,27 @@ void hisi_sas_port_formed(struct asd_sas_phy *sas_phy)
 {
 	hisi_sas_port_notify_formed(sas_phy, 1);
 }
+static void hisi_sas_phy_disconnected(struct hisi_sas_phy *phy)
+{
+	phy->phy_attached = 0;
+	phy->phy_type = 0;
+}
+
+void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy)
+{
+	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+	struct sas_ha_struct *sas_ha = &hisi_hba->sha;
+
+	if (rdy) {
+		/* Phy down but ready */
+		hisi_sas_bytes_dmaed(hisi_hba, phy_no);
+		hisi_sas_port_notify_formed(sas_phy, 0);
+	} else {
+		/* Phy down and not ready */
+		sas_ha->notify_phy_event(sas_phy, PHYE_LOSS_OF_SIGNAL);
+		phy->phy_attached = 0;
+		sas_phy_disconnected(sas_phy);
+		hisi_sas_phy_disconnected(phy);
+	}
+}
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index e8b9dc3..fadd163 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -1342,7 +1342,61 @@ end:
 	return res;
 }
 
+static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
+{
+	struct hisi_sas_phy *phy = p;
+	struct hisi_hba *hisi_hba = phy->hisi_hba;
+	u32 irq_value, irq_mask_old;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+	int phy_no = sas_phy->id;
 
+	/* mask_int0 */
+	irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
+	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
+
+	/* read int0 */
+	irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
+
+	if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
+		u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
+
+		hisi_sas_phy_down(hisi_hba,
+			phy_no,
+			(phy_state & 1 << phy_no) ? 1 : 0);
+	}
+
+	if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
+		dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
+			phy_no);
+
+	if (irq_value & CHL_INT0_DWS_LOST_MSK)
+		dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
+
+	if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
+		dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
+			phy_no);
+
+	if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
+		irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
+		dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
+			phy_no);
+
+	if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
+		dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
+
+	/* write to zero */
+	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
+
+	if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
+		hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
+				0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
+	else
+		hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
+				irq_mask_old);
+
+	return IRQ_HANDLED;
+}
 
 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
 {
@@ -1397,12 +1451,14 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
 
 static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 	{"Phy Up"},
+	{"Abnormal"},
 };
 
 static const char cq_int_name[32] = "cq";
 
 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
 	int_phyup_v1_hw,
+	int_abnormal_v1_hw
 };
 
 int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
-- 
1.9.1

[PATCH 18/25] scsi: hisi_sas: add dev_gone and port_deformed

[John Garry]

Add function calls for lldd_dev_gone and lldd_port_deformed.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  7 +++
 drivers/scsi/hisi_sas/hisi_sas_init.c  |  2 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 80 ++++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 ++++++++++++
 4 files changed, 117 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 3f61a4a..265d9bd 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -352,14 +352,19 @@ union hisi_sas_command_table {
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_dev_found(struct domain_device *dev);
+void hisi_sas_dev_gone(struct domain_device *dev);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
 void hisi_sas_port_formed(struct asd_sas_phy *sas_phy);
+void hisi_sas_port_deformed(struct asd_sas_phy *sas_phy);
 void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
 void hisi_sas_wq_process(struct work_struct *work);
 void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
 			struct hisi_sas_slot *slot);
 
 /* hw specific functions */
+extern int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
+			       struct hisi_sas_slot *slot,
+			       int abort);
 extern void hisi_sas_setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 				      struct hisi_sas_device *device);
 extern void start_delivery_v1_hw(struct hisi_hba *hisi_hba);
@@ -370,6 +375,8 @@ extern int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 extern int interrupt_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
+extern int free_device_v1_hw(struct hisi_hba *hisi_hba,
+			     struct hisi_sas_device *dev);
 extern int phys_init_v1_hw(struct hisi_hba *hisi_hba);
 extern void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 extern void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 703527b..ba64562 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -34,8 +34,10 @@ static struct scsi_host_template hisi_sas_sht = {
 
 static struct sas_domain_function_template hisi_sas_transport_ops = {
 	.lldd_dev_found		= hisi_sas_dev_found,
+	.lldd_dev_gone		= hisi_sas_dev_gone,
 	.lldd_execute_task	= hisi_sas_queue_command,
 	.lldd_port_formed	= hisi_sas_port_formed,
+	.lldd_port_deformed	= hisi_sas_port_deformed,
 };
 
 static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index fbc2cca..36ef8cd 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -514,12 +514,86 @@ void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
 		spin_unlock_irqrestore(&hisi_hba->lock, flags);
 }
 
+void hisi_sas_do_release_task(struct hisi_hba *hisi_hba,
+		int phy_no, struct domain_device *device)
+{
+	struct hisi_sas_phy *phy;
+	struct hisi_sas_port *port;
+	struct hisi_sas_slot *slot, *slot2;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	phy = &hisi_hba->phy[phy_no];
+	port = phy->port;
+	if (!port)
+		return;
+
+	list_for_each_entry_safe(slot, slot2, &port->list, entry) {
+		struct sas_task *task;
+
+		task = slot->task;
+		if (device && task->dev != device)
+			continue;
+
+		dev_info(dev, "Release slot [%d:%d], task [%p]:\n",
+			 slot->dlvry_queue, slot->dlvry_queue_slot, task);
+		slot_complete_v1_hw(hisi_hba, slot, 1);
+	}
+}
+
+static void hisi_sas_port_notify_deformed(struct asd_sas_phy *sas_phy,
+					  int lock)
+{
+	struct domain_device *device;
+	struct hisi_sas_phy *phy = sas_phy->lldd_phy;
+	struct hisi_hba *hisi_hba = phy->hisi_hba;
+	struct asd_sas_port *sas_port = sas_phy->port;
+	struct hisi_sas_port *port = sas_port->lldd_port;
+	int phy_no = 0;
+
+	port->port_attached = 0;
+	port->id = -1;
+
+	while (phy != &hisi_hba->phy[phy_no]) {
+		phy_no++;
+
+		if (phy_no >= hisi_hba->n_phy)
+			return;
+	}
+	list_for_each_entry(device, &sas_port->dev_list, dev_list_node)
+		hisi_sas_do_release_task(phy->hisi_hba, phy_no, device);
+}
 
 int hisi_sas_dev_found(struct domain_device *device)
 {
 	return hisi_sas_dev_found_notify(device, 1);
 }
 
+
+static void hisi_sas_dev_gone_notify(struct domain_device *device)
+{
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	if (!sas_dev) {
+		pr_warn("%s: found dev has gone\n", __func__);
+		return;
+	}
+
+	dev_info(dev, "found dev[%lld:%x] is gone\n",
+		 sas_dev->device_id, sas_dev->dev_type);
+
+	free_device_v1_hw(hisi_hba, sas_dev);
+
+	device->lldd_dev = NULL;
+	sas_dev->sas_device = NULL;
+}
+
+void hisi_sas_dev_gone(struct domain_device *device)
+{
+	hisi_sas_dev_gone_notify(device);
+}
+
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
 {
 	return hisi_sas_task_exec(task, gfp_flags, NULL, 0, NULL);
@@ -529,6 +603,12 @@ void hisi_sas_port_formed(struct asd_sas_phy *sas_phy)
 {
 	hisi_sas_port_notify_formed(sas_phy, 1);
 }
+
+void hisi_sas_port_deformed(struct asd_sas_phy *sas_phy)
+{
+	hisi_sas_port_notify_deformed(sas_phy, 1);
+}
+
 static void hisi_sas_phy_disconnected(struct hisi_sas_phy *phy)
 {
 	phy->phy_attached = 0;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index fadd163..2de54a7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -534,6 +534,34 @@ void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 				(0xff00 < ITCT_HDR_REJ_OPEN_TL_OFF));
 }
 
+int free_device_v1_hw(struct hisi_hba *hisi_hba,
+		      struct hisi_sas_device *sas_dev)
+{
+	u64 dev_id = sas_dev->device_id;
+	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
+	u32 qw0, reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
+
+	reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
+	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
+
+	/* free itct */
+	udelay(1);
+	reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
+	reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
+	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
+
+	qw0 = cpu_to_le64(itct->qw0);
+	qw0 &= ~ITCT_HDR_VALID_MSK;
+	itct->qw0 = cpu_to_le64(qw0);
+
+	memset(sas_dev, 0, sizeof(*sas_dev));
+	sas_dev->device_id = dev_id;
+	sas_dev->dev_type = SAS_PHY_UNUSED;
+	sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+
+	return 0;
+}
+
 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
 {
 	int i;
-- 
1.9.1

[PATCH 19/25] scsi: hisi_sas: add bcast interrupt handler

[John Garry]

This is for expander broadcast event.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 2de54a7..2ad2ffa 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -1370,6 +1370,35 @@ end:
 	return res;
 }
 
+static irqreturn_t int_bcast_v1_hw(int irq, void *p)
+{
+	struct hisi_sas_phy *phy = p;
+	struct hisi_hba *hisi_hba = phy->hisi_hba;
+	u32 irq_value;
+	irqreturn_t res = IRQ_HANDLED;
+	struct asd_sas_phy *sas_phy = &phy->sas_phy;
+	int phy_no = sas_phy->id;
+	struct sas_ha_struct *sha = &hisi_hba->sha;
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
+
+	if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
+		dev_err(dev, "bcast: irq_value = %x not set enable bit",
+			irq_value);
+		res = IRQ_NONE;
+		goto end;
+	}
+
+	sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
+
+end:
+	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
+			CHL_INT2_SL_RX_BC_ACK_MSK);
+
+	return res;
+}
+
 static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
 {
 	struct hisi_sas_phy *phy = p;
@@ -1478,6 +1507,7 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
 }
 
 static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
+	{"Bcast"},
 	{"Phy Up"},
 	{"Abnormal"},
 };
@@ -1485,6 +1515,7 @@ static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 static const char cq_int_name[32] = "cq";
 
 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
+	int_bcast_v1_hw,
 	int_phyup_v1_hw,
 	int_abnormal_v1_hw
 };
-- 
1.9.1

[PATCH 20/25] scsi: hisi_sas: add smp protocol support

[John Garry]

Add support for smp function, which allows devices
attached by expander to be controlled.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  4 ++
 drivers/scsi/hisi_sas/hisi_sas_main.c  |  9 +++-
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 97 +++++++++++++++++++++++++++++++++-
 3 files changed, 107 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 265d9bd..be2cdf5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -34,6 +34,8 @@
 		(((sizeof(union hisi_sas_command_table)+3)/4)*4)
 
 #define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
+#define HISI_SAS_MAX_SMP_RESP_SZ 1028
+
 #define HISI_SAS_NAME_LEN 32
 #define HISI_SAS_RESET_REG_CNT 5
 
@@ -372,6 +374,8 @@ extern int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s);
 extern int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 			  struct hisi_sas_tei *tei, int is_tmf,
 			  struct hisi_sas_tmf_task *tmf);
+extern int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
+			  struct hisi_sas_tei *tei);
 extern int interrupt_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 36ef8cd..91620b0 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -109,6 +109,11 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
 	memset(slot, 0, sizeof(*slot));
 }
 
+static int hisi_sas_task_prep_smp(struct hisi_hba *hisi_hba,
+				struct hisi_sas_tei *tei)
+{
+	return prep_smp_v1_hw(hisi_hba, tei);
+}
 
 static int hisi_sas_task_prep_ssp(struct hisi_hba *hisi_hba,
 				  struct hisi_sas_tei *tei, int is_tmf,
@@ -235,10 +240,12 @@ static int hisi_sas_task_prep(struct sas_task *task,
 	tei.n_elem = n_elem;
 	tei.slot = slot;
 	switch (task->task_proto) {
+	case SAS_PROTOCOL_SMP:
+		rc = hisi_sas_task_prep_smp(hisi_hba, &tei);
+		break;
 	case SAS_PROTOCOL_SSP:
 		rc = hisi_sas_task_prep_ssp(hisi_hba, &tei, is_tmf, tmf);
 		break;
-	case SAS_PROTOCOL_SMP:
 	case SAS_PROTOCOL_SATA:
 	case SAS_PROTOCOL_STP:
 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 2ad2ffa..b470c72 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -913,6 +913,80 @@ static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
 	return 0;
 }
 
+int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
+		   struct hisi_sas_tei *tei)
+{
+	struct sas_task *task = tei->task;
+	struct hisi_sas_cmd_hdr *hdr = tei->hdr;
+	struct domain_device *device = task->dev;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct hisi_sas_port *port = tei->port;
+	struct scatterlist *sg_req, *sg_resp;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	dma_addr_t req_dma_addr;
+	unsigned int req_len, resp_len;
+	int elem, rc;
+	struct hisi_sas_slot *slot = tei->slot;
+
+	/*
+	* DMA-map SMP request, response buffers
+	*/
+	/* req */
+	sg_req = &task->smp_task.smp_req;
+	elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
+	if (!elem)
+		return -ENOMEM;
+	req_len = sg_dma_len(sg_req);
+	req_dma_addr = sg_dma_address(sg_req);
+
+	/* resp */
+	sg_resp = &task->smp_task.smp_resp;
+	elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
+	if (!elem) {
+		rc = -ENOMEM;
+		goto err_out_req;
+	}
+	resp_len = sg_dma_len(sg_resp);
+	if ((req_len & 0x3) || (resp_len & 0x3)) {
+		rc = -EINVAL;
+		goto err_out_resp;
+	}
+
+	/* create header */
+	/* dw0 */
+	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
+			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
+			       (1 << CMD_HDR_MODE_OFF) | /* ini mode */
+			       (2 << CMD_HDR_CMD_OFF)); /* smp */
+
+	/* map itct entry */
+	hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
+
+	/* dw2 */
+	hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
+			       (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
+			       CMD_HDR_MRFL_OFF));
+
+	hdr->transfer_tags = cpu_to_le32(tei->iptt << CMD_HDR_IPTT_OFF);
+
+	hdr->cmd_table_addr_lo = cpu_to_le32(lower_32_bits(req_dma_addr));
+	hdr->cmd_table_addr_hi = cpu_to_le32(upper_32_bits(req_dma_addr));
+
+	hdr->sts_buffer_addr_lo =
+			cpu_to_le32(lower_32_bits(slot->status_buffer_dma));
+	hdr->sts_buffer_addr_hi =
+			cpu_to_le32(upper_32_bits(slot->status_buffer_dma));
+
+	return 0;
+
+err_out_resp:
+	dma_unmap_sg(dev, &tei->task->smp_task.smp_resp, 1,
+		     DMA_FROM_DEVICE);
+err_out_req:
+	dma_unmap_sg(dev, &tei->task->smp_task.smp_req, 1,
+		     DMA_TO_DEVICE);
+	return rc;
+}
 
 int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 		   struct hisi_sas_tei *tei, int is_tmf,
@@ -1132,11 +1206,14 @@ static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
 	}
 		break;
 	case SAS_PROTOCOL_SMP:
+		tstat->stat = SAM_STAT_CHECK_CONDITION;
+		break;
+
 	case SAS_PROTOCOL_SATA:
 	case SAS_PROTOCOL_STP:
 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
 	{
-		dev_err(dev, "slot err: SMP/SATA/STP not supported");
+		dev_err(dev, "slot err: SATA/STP not supported");
 	}
 		break;
 	default:
@@ -1245,8 +1322,24 @@ int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
 		break;
 	}
 	case SAS_PROTOCOL_SMP:
-		dev_err(dev, "slot complete: SMP not supported");
+	{
+		void *to;
+		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
+
+		tstat->stat = SAM_STAT_GOOD;
+		to = kmap_atomic(sg_page(sg_resp));
+
+		dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
+			     DMA_FROM_DEVICE);
+		dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
+			     DMA_TO_DEVICE);
+		memcpy(to + sg_resp->offset,
+		       slot->status_buffer +
+		       sizeof(struct hisi_sas_err_record),
+		       sg_dma_len(sg_resp));
+		kunmap_atomic(to);
 		break;
+	}
 	case SAS_PROTOCOL_SATA:
 	case SAS_PROTOCOL_STP:
 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
-- 
1.9.1

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[PATCH 21/25] scsi: hisi_sas: add scan finished and start

[John Garry]

Add functions for scsi host template scan_finished
and scan_start methods.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas.h      |  4 ++++
 drivers/scsi/hisi_sas/hisi_sas_init.c |  2 ++
 drivers/scsi/hisi_sas/hisi_sas_main.c | 24 ++++++++++++++++++++++++
 3 files changed, 30 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index be2cdf5..9565a2a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -165,6 +165,7 @@ struct hisi_hba {
 
 	int	n_phy;
 
+	int scan_finished;
 
 	struct timer_list timer;
 	struct workqueue_struct *wq;
@@ -351,6 +352,9 @@ union hisi_sas_command_table {
 	struct hisi_sas_command_table_stp stp;
 };
 
+int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time);
+void hisi_sas_scan_start(struct Scsi_Host *shost);
+
 void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba);
 void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_dev_found(struct domain_device *dev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index ba64562..caab645 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -18,6 +18,8 @@ static struct scsi_host_template hisi_sas_sht = {
 	.queuecommand		= sas_queuecommand,
 	.target_alloc		= sas_target_alloc,
 	.slave_configure	= sas_slave_configure,
+	.scan_finished		= hisi_sas_scan_finished,
+	.scan_start		= hisi_sas_scan_start,
 	.change_queue_depth	= sas_change_queue_depth,
 	.bios_param		= sas_bios_param,
 	.can_queue		= 1,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 91620b0..393d22a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -435,6 +435,30 @@ found_out:
 	return res;
 }
 
+void hisi_sas_scan_start(struct Scsi_Host *shost)
+{
+	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
+	struct hisi_hba *hisi_hba = sha->lldd_ha;
+	int i;
+
+	for (i = 0; i < hisi_hba->n_phy; ++i)
+		hisi_sas_bytes_dmaed(hisi_hba, i);
+
+	hisi_hba->scan_finished = 1;
+}
+
+int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time)
+{
+	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
+	struct hisi_hba *hisi_hba = sha->lldd_ha;
+
+	if (hisi_hba->scan_finished == 0)
+		return 0;
+
+	sas_drain_work(sha);
+	return 1;
+}
+
 
 static void hisi_sas_phyup_work(struct hisi_hba *hisi_hba,
 				      int phy_no)
-- 
1.9.1

[PATCH 22/25] scsi: hisi_sas: add tmf methods

[John Garry]

Add function methods for tmf's.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas.h      |   7 +
 drivers/scsi/hisi_sas/hisi_sas_init.c |   6 +
 drivers/scsi/hisi_sas/hisi_sas_main.c | 385 ++++++++++++++++++++++++++++++++++
 3 files changed, 398 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 9565a2a..b488fe3 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -360,6 +360,13 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_dev_found(struct domain_device *dev);
 void hisi_sas_dev_gone(struct domain_device *dev);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
+int hisi_sas_abort_task(struct sas_task *task);
+int hisi_sas_abort_task_set(struct domain_device *dev, u8 *lun);
+int hisi_sas_clear_aca(struct domain_device *dev, u8 *lun);
+int hisi_sas_clear_task_set(struct domain_device *dev, u8 *lun);
+int hisi_sas_I_T_nexus_reset(struct domain_device *dev);
+int hisi_sas_lu_reset(struct domain_device *dev, u8 *lun);
+int hisi_sas_query_task(struct sas_task *task);
 void hisi_sas_port_formed(struct asd_sas_phy *sas_phy);
 void hisi_sas_port_deformed(struct asd_sas_phy *sas_phy);
 void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index caab645..b6272d8 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -38,6 +38,12 @@ static struct sas_domain_function_template hisi_sas_transport_ops = {
 	.lldd_dev_found		= hisi_sas_dev_found,
 	.lldd_dev_gone		= hisi_sas_dev_gone,
 	.lldd_execute_task	= hisi_sas_queue_command,
+	.lldd_abort_task	= hisi_sas_abort_task,
+	.lldd_abort_task_set	= hisi_sas_abort_task_set,
+	.lldd_clear_aca		= hisi_sas_clear_aca,
+	.lldd_I_T_nexus_reset	= hisi_sas_I_T_nexus_reset,
+	.lldd_lu_reset		= hisi_sas_lu_reset,
+	.lldd_query_task	= hisi_sas_query_task,
 	.lldd_port_formed	= hisi_sas_port_formed,
 	.lldd_port_deformed	= hisi_sas_port_deformed,
 };
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 393d22a..12af29c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -23,6 +23,19 @@ static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
 	return device->port->ha->lldd_ha;
 }
 
+static int hisi_sas_find_tag(struct hisi_hba *hisi_hba,
+			     struct sas_task *task, u32 *tag)
+{
+	if (task->lldd_task) {
+		struct hisi_sas_slot *slot;
+
+		slot = task->lldd_task;
+		*tag = slot->idx;
+		return 1;
+	}
+	return 0;
+}
+
 static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx)
 {
 	void *bitmap = hisi_hba->slot_index_tags;
@@ -599,6 +612,44 @@ int hisi_sas_dev_found(struct domain_device *device)
 	return hisi_sas_dev_found_notify(device, 1);
 }
 
+int hisi_sas_find_dev_phyno(struct domain_device *device, int *phyno)
+{
+	int i = 0, j = 0, num = 0, n = 0;
+	struct sas_ha_struct *sha = device->port->ha;
+
+	while (sha->sas_port[i]) {
+		if (sha->sas_port[i] == device->port) {
+			struct asd_sas_phy *phy;
+
+			list_for_each_entry(phy,
+				&sha->sas_port[i]->phy_list, port_phy_el) {
+				j = 0;
+
+				while (sha->sas_phy[j]) {
+					if (sha->sas_phy[j] == phy)
+						break;
+					j++;
+				}
+				phyno[n] = j;
+				num++;
+				n++;
+			}
+			break;
+		}
+		i++;
+	}
+	return num;
+}
+
+static void hisi_sas_release_task(struct hisi_hba *hisi_hba,
+			struct domain_device *device)
+{
+	int i, phyno[4], num;
+
+	num = hisi_sas_find_dev_phyno(device, phyno);
+	for (i = 0; i < num; i++)
+		hisi_sas_do_release_task(hisi_hba, phyno[i], device);
+}
 
 static void hisi_sas_dev_gone_notify(struct domain_device *device)
 {
@@ -630,6 +681,340 @@ int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
 	return hisi_sas_task_exec(task, gfp_flags, NULL, 0, NULL);
 }
 
+
+static void hisi_sas_task_done(struct sas_task *task)
+{
+	if (!del_timer(&task->slow_task->timer))
+		return;
+	complete(&task->slow_task->completion);
+}
+
+static void hisi_sas_tmf_timedout(unsigned long data)
+{
+	struct sas_task *task = (struct sas_task *)data;
+
+	task->task_state_flags |= SAS_TASK_STATE_ABORTED;
+	complete(&task->slow_task->completion);
+}
+
+#define TASK_TIMEOUT 20
+static int hisi_sas_exec_internal_tmf_task(struct domain_device *device,
+					   void *parameter,
+					   u32 para_len,
+					   struct hisi_sas_tmf_task *tmf)
+{
+	int res, retry;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
+	struct device *dev = &hisi_hba->pdev->dev;
+	struct sas_task *task = NULL;
+
+	for (retry = 0; retry < 3; retry++) {
+		task = sas_alloc_slow_task(GFP_KERNEL);
+		if (!task)
+			return -ENOMEM;
+
+		task->dev = device;
+		task->task_proto = device->tproto;
+
+		memcpy(&task->ssp_task, parameter, para_len);
+		task->task_done = hisi_sas_task_done;
+
+		task->slow_task->timer.data = (unsigned long) task;
+		task->slow_task->timer.function = hisi_sas_tmf_timedout;
+		task->slow_task->timer.expires = jiffies + TASK_TIMEOUT*HZ;
+		add_timer(&task->slow_task->timer);
+
+		res = hisi_sas_task_exec(task, GFP_KERNEL, NULL, 1, tmf);
+
+		if (res) {
+			del_timer(&task->slow_task->timer);
+			dev_err(dev, "executing internal task failed: %d\n",
+				res);
+			goto ex_err;
+		}
+
+		wait_for_completion(&task->slow_task->completion);
+		res = TMF_RESP_FUNC_FAILED;
+		/* Even TMF timed out, return direct. */
+		if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
+			if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
+				dev_err(dev, "TMF task[%d] timeout\n",
+				       tmf->tag_of_task_to_be_managed);
+				if (task->lldd_task) {
+					struct hisi_sas_slot *slot;
+
+					slot = (struct hisi_sas_slot *)
+						task->lldd_task;
+					hisi_sas_slot_task_free(hisi_hba,
+								task, slot);
+				}
+
+				goto ex_err;
+			}
+		}
+
+		if (task->task_status.resp == SAS_TASK_COMPLETE &&
+		    task->task_status.stat == SAM_STAT_GOOD) {
+			res = TMF_RESP_FUNC_COMPLETE;
+			break;
+		}
+
+		if (task->task_status.resp == SAS_TASK_COMPLETE &&
+		      task->task_status.stat == SAS_DATA_UNDERRUN) {
+			/* no error, but return the number of bytes of
+			 * underrun */
+			pr_warn(" ok: task to dev %016llx response: 0x%x "
+				    "status 0x%x underrun\n",
+				    SAS_ADDR(device->sas_addr),
+				    task->task_status.resp,
+				    task->task_status.stat);
+			res = task->task_status.residual;
+			break;
+		}
+
+		if (task->task_status.resp == SAS_TASK_COMPLETE &&
+			task->task_status.stat == SAS_DATA_OVERRUN) {
+			pr_warn("%s: blocked task error\n", __func__);
+			res = -EMSGSIZE;
+			break;
+		}
+
+		pr_warn("%s: task to dev %016llx response: 0x%x "
+			"status 0x%x\n", __func__,
+			SAS_ADDR(device->sas_addr),
+			task->task_status.resp,
+			task->task_status.stat);
+		sas_free_task(task);
+		task = NULL;
+	}
+ex_err:
+	BUG_ON(retry == 3 && task != NULL);
+	sas_free_task(task);
+	return res;
+}
+
+static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device,
+				u8 *lun, struct hisi_sas_tmf_task *tmf)
+{
+	struct sas_ssp_task ssp_task;
+
+	if (!(device->tproto & SAS_PROTOCOL_SSP))
+		return TMF_RESP_FUNC_ESUPP;
+
+	memcpy(ssp_task.LUN, lun, 8);
+
+	return hisi_sas_exec_internal_tmf_task(device, &ssp_task,
+				sizeof(ssp_task), tmf);
+}
+
+int hisi_sas_abort_task(struct sas_task *task)
+{
+	struct scsi_lun lun;
+	struct hisi_sas_tmf_task tmf_task;
+	struct domain_device *device = task->dev;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_hba *hisi_hba;
+	struct device *dev;
+	int rc = TMF_RESP_FUNC_FAILED;
+	unsigned long flags;
+	u32 tag;
+
+	if (!sas_dev) {
+		pr_warn("%s: Device has been removed\n", __func__);
+		return TMF_RESP_FUNC_FAILED;
+	}
+
+	hisi_hba = dev_to_hisi_hba(task->dev);
+	dev = &hisi_hba->pdev->dev;
+
+	spin_lock_irqsave(&task->task_state_lock, flags);
+	if (task->task_state_flags & SAS_TASK_STATE_DONE) {
+		spin_unlock_irqrestore(&task->task_state_lock, flags);
+		rc = TMF_RESP_FUNC_COMPLETE;
+		goto out;
+	}
+
+	spin_unlock_irqrestore(&task->task_state_lock, flags);
+	sas_dev->dev_status = HISI_SAS_DEV_EH;
+	if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
+		struct scsi_cmnd *cmnd = (struct scsi_cmnd *)task->uldd_task;
+
+		int_to_scsilun(cmnd->device->lun, &lun);
+		rc = hisi_sas_find_tag(hisi_hba, task, &tag);
+		if (rc == 0) {
+			dev_notice(dev, "abort task: No such tag\n");
+			rc = TMF_RESP_FUNC_FAILED;
+			return rc;
+		}
+
+		tmf_task.tmf = TMF_ABORT_TASK;
+		tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
+
+		rc = hisi_sas_debug_issue_ssp_tmf(task->dev,
+						  lun.scsi_lun,
+						  &tmf_task);
+
+		/* if successful, clear the task and callback forwards.*/
+		if (rc == TMF_RESP_FUNC_COMPLETE) {
+			if (task->lldd_task) {
+				struct hisi_sas_slot *slot;
+
+				slot = &hisi_hba->slot_info
+					[tmf_task.tag_of_task_to_be_managed];
+				spin_lock_irqsave(&hisi_hba->lock, flags);
+				slot_complete_v1_hw(hisi_hba, slot, 1);
+				spin_unlock_irqrestore(&hisi_hba->lock, flags);
+			}
+		}
+
+	} else if (task->task_proto & SAS_PROTOCOL_SATA ||
+		task->task_proto & SAS_PROTOCOL_STP) {
+		if (SAS_SATA_DEV == task->dev->dev_type) {
+			struct hisi_slot_info *slot = task->lldd_task;
+
+			dev_notice(dev, "abort task: hba=%p task=%p slot=%p\n",
+				   hisi_hba, task, slot);
+			task->task_state_flags |= SAS_TASK_STATE_ABORTED;
+			rc = TMF_RESP_FUNC_COMPLETE;
+			goto out;
+		}
+
+	}
+
+out:
+	if (rc != TMF_RESP_FUNC_COMPLETE)
+		dev_notice(dev, "abort task: rc=%d\n", rc);
+	return rc;
+}
+
+int hisi_sas_abort_task_set(struct domain_device *device, u8 *lun)
+{
+	int rc = TMF_RESP_FUNC_FAILED;
+	struct hisi_sas_tmf_task tmf_task;
+
+	tmf_task.tmf = TMF_ABORT_TASK_SET;
+	rc = hisi_sas_debug_issue_ssp_tmf(device, lun, &tmf_task);
+
+	return rc;
+}
+
+int hisi_sas_clear_aca(struct domain_device *device, u8 *lun)
+{
+	int rc = TMF_RESP_FUNC_FAILED;
+	struct hisi_sas_tmf_task tmf_task;
+
+	tmf_task.tmf = TMF_CLEAR_ACA;
+	rc = hisi_sas_debug_issue_ssp_tmf(device, lun, &tmf_task);
+
+	return rc;
+}
+
+int hisi_sas_clear_task_set(struct domain_device *device, u8 *lun)
+{
+	int rc = TMF_RESP_FUNC_FAILED;
+	struct hisi_sas_tmf_task tmf_task;
+
+	tmf_task.tmf = TMF_CLEAR_TASK_SET;
+	rc = hisi_sas_debug_issue_ssp_tmf(device, lun, &tmf_task);
+
+	return rc;
+}
+
+static int hisi_sas_debug_I_T_nexus_reset(struct domain_device *device)
+{
+	int rc;
+	struct sas_phy *phy = sas_get_local_phy(device);
+	int reset_type = (device->dev_type == SAS_SATA_DEV ||
+			(device->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
+	rc = sas_phy_reset(phy, reset_type);
+	sas_put_local_phy(phy);
+	msleep(2000);
+	return rc;
+}
+
+int hisi_sas_I_T_nexus_reset(struct domain_device *device)
+{
+	unsigned long flags;
+	int rc = TMF_RESP_FUNC_FAILED;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
+
+	if (sas_dev->dev_status != HISI_SAS_DEV_EH)
+		return TMF_RESP_FUNC_FAILED;
+	sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+
+	rc = hisi_sas_debug_I_T_nexus_reset(device);
+
+	spin_lock_irqsave(&hisi_hba->lock, flags);
+	hisi_sas_release_task(hisi_hba, device);
+	spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+	return 0;
+}
+
+int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
+{
+	unsigned long flags;
+	int rc = TMF_RESP_FUNC_FAILED;
+	struct hisi_sas_tmf_task tmf_task;
+	struct hisi_sas_device *sas_dev = device->lldd_dev;
+	struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	tmf_task.tmf = TMF_LU_RESET;
+	sas_dev->dev_status = HISI_SAS_DEV_EH;
+	rc = hisi_sas_debug_issue_ssp_tmf(device, lun, &tmf_task);
+	if (rc == TMF_RESP_FUNC_COMPLETE) {
+		spin_lock_irqsave(&hisi_hba->lock, flags);
+		hisi_sas_release_task(hisi_hba, device);
+		spin_unlock_irqrestore(&hisi_hba->lock, flags);
+	}
+	/* If failed, fall-through I_T_Nexus reset */
+	dev_err(dev, "lu_reset: for device[%llx]:rc= %d\n",
+		sas_dev->device_id, rc);
+	return rc;
+}
+
+int hisi_sas_query_task(struct sas_task *task)
+{
+	u32 tag;
+	struct scsi_lun lun;
+	struct hisi_sas_tmf_task tmf_task;
+	int rc = TMF_RESP_FUNC_FAILED;
+
+	if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
+		struct scsi_cmnd *cmnd = (struct scsi_cmnd *)task->uldd_task;
+		struct domain_device *device = task->dev;
+		struct hisi_sas_device *sas_dev = device->lldd_dev;
+		struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
+
+		int_to_scsilun(cmnd->device->lun, &lun);
+		rc = hisi_sas_find_tag(hisi_hba, task, &tag);
+		if (rc == 0) {
+			rc = TMF_RESP_FUNC_FAILED;
+			return rc;
+		}
+
+		tmf_task.tmf = TMF_QUERY_TASK;
+		tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
+
+		rc = hisi_sas_debug_issue_ssp_tmf(device,
+						  lun.scsi_lun,
+						  &tmf_task);
+		switch (rc) {
+		/* The task is still in Lun, release it then */
+		case TMF_RESP_FUNC_SUCC:
+		/* The task is not in Lun or failed, reset the phy */
+		case TMF_RESP_FUNC_FAILED:
+		case TMF_RESP_FUNC_COMPLETE:
+			break;
+		}
+	}
+	pr_info("%s: rc=%d\n", __func__, rc);
+	return rc;
+}
+
 void hisi_sas_port_formed(struct asd_sas_phy *sas_phy)
 {
 	hisi_sas_port_notify_formed(sas_phy, 1);
-- 
1.9.1

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[PATCH 23/25] scsi: hisi_sas: add control phy handler

[John Garry]

Add method for lldd_control_phy. Currently link rate
control and spinup hold is unsupported.

Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
---
 drivers/scsi/hisi_sas/hisi_sas.h       |  7 ++++
 drivers/scsi/hisi_sas/hisi_sas_init.c  |  1 +
 drivers/scsi/hisi_sas/hisi_sas_main.c  | 64 ++++++++++++++++++++++++++++++++++
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 22 ++++++++++++
 4 files changed, 94 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index b488fe3..be91b8c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -133,6 +133,7 @@ struct hisi_sas_tei {
 };
 
 enum hisi_sas_wq_event {
+	CONTROL_PHY,
 	PHYUP,
 };
 
@@ -360,6 +361,9 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int i);
 int hisi_sas_dev_found(struct domain_device *dev);
 void hisi_sas_dev_gone(struct domain_device *dev);
 int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags);
+int hisi_sas_control_phy(struct asd_sas_phy *sas_phy,
+			enum phy_func func,
+			void *funcdata);
 int hisi_sas_abort_task(struct sas_task *task);
 int hisi_sas_abort_task_set(struct domain_device *dev, u8 *lun);
 int hisi_sas_clear_aca(struct domain_device *dev, u8 *lun);
@@ -375,6 +379,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
 			struct hisi_sas_slot *slot);
 
 /* hw specific functions */
+extern void hard_phy_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 extern int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
 			       struct hisi_sas_slot *slot,
 			       int abort);
@@ -392,8 +397,10 @@ extern int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba);
 extern int hw_init_v1_hw(struct hisi_hba *hisi_hba);
 extern int free_device_v1_hw(struct hisi_hba *hisi_hba,
 			     struct hisi_sas_device *dev);
+extern void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 extern int phys_init_v1_hw(struct hisi_hba *hisi_hba);
 extern void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 extern void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 			     struct hisi_sas_device *device);
+extern void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no);
 #endif
diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index b6272d8..af4d613e1 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -38,6 +38,7 @@ static struct sas_domain_function_template hisi_sas_transport_ops = {
 	.lldd_dev_found		= hisi_sas_dev_found,
 	.lldd_dev_gone		= hisi_sas_dev_gone,
 	.lldd_execute_task	= hisi_sas_queue_command,
+	.lldd_control_phy	= hisi_sas_control_phy,
 	.lldd_abort_task	= hisi_sas_abort_task,
 	.lldd_abort_task_set	= hisi_sas_abort_task_set,
 	.lldd_clear_aca		= hisi_sas_clear_aca,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 12af29c..1e42611 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -472,6 +472,32 @@ int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time)
 	return 1;
 }
 
+static void hisi_sas_control_phy_work(struct hisi_hba *hisi_hba,
+				int func,
+				int phy_no)
+{
+	struct device *dev = &hisi_hba->pdev->dev;
+
+	switch (func) {
+	case PHY_FUNC_HARD_RESET:
+		hard_phy_reset_v1_hw(hisi_hba, phy_no);
+		break;
+
+	case PHY_FUNC_LINK_RESET:
+		enable_phy_v1_hw(hisi_hba, phy_no);
+		hard_phy_reset_v1_hw(hisi_hba, phy_no);
+		break;
+
+	case PHY_FUNC_DISABLE:
+		disable_phy_v1_hw(hisi_hba, phy_no);
+		break;
+
+	case PHY_FUNC_SET_LINK_RATE:
+	case PHY_FUNC_RELEASE_SPINUP_HOLD:
+	default:
+		dev_err(dev, "Control phy func %d unsupported\n", func);
+	}
+}
 
 static void hisi_sas_phyup_work(struct hisi_hba *hisi_hba,
 				      int phy_no)
@@ -487,8 +513,12 @@ void hisi_sas_wq_process(struct work_struct *work)
 	struct hisi_hba *hisi_hba = wq->hisi_hba;
 	int event = wq->event;
 	int phy_no = wq->phy_no;
+	int func = wq->data;
 
 	switch (event) {
+	case CONTROL_PHY:
+		hisi_sas_control_phy_work(hisi_hba, func, phy_no);
+		break;
 	case PHYUP:
 		hisi_sas_phyup_work(hisi_hba, phy_no);
 		break;
@@ -681,6 +711,40 @@ int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
 	return hisi_sas_task_exec(task, gfp_flags, NULL, 0, NULL);
 }
 
+int hisi_sas_control_phy(struct asd_sas_phy *sas_phy,
+			enum phy_func func,
+			void *funcdata)
+{
+	struct sas_ha_struct *sas_ha = sas_phy->ha;
+	struct hisi_hba *hisi_hba = NULL;
+	struct hisi_sas_phy *phy = NULL;
+	int phy_no = 0;
+	struct hisi_sas_wq *wq = kmalloc(sizeof(*wq), GFP_ATOMIC);
+
+	if (!wq)
+		return -ENOMEM;
+
+	while (sas_ha->sas_phy[phy_no]) {
+		if (sas_ha->sas_phy[phy_no] == sas_phy) {
+			hisi_hba = (struct hisi_hba *)sas_ha->lldd_ha;
+			break;
+		}
+		phy_no++;
+	}
+
+	phy = &hisi_hba->phy[phy_no];
+
+	wq->event = CONTROL_PHY;
+	wq->data = func;
+	wq->hisi_hba = hisi_hba;
+	wq->phy_no = phy_no;
+
+	INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
+
+	queue_work(hisi_hba->wq, &wq->work_struct);
+
+	return 0;
+}
 
 static void hisi_sas_task_done(struct sas_task *task)
 {
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index b470c72..b5ba46a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -766,6 +766,13 @@ void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 }
 
+void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+	cfg &= ~PHY_CFG_ENA_MSK;
+	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
 
 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 {
@@ -775,6 +782,21 @@ static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 	enable_phy_v1_hw(hisi_hba, phy_no);
 }
 
+static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	disable_phy_v1_hw(hisi_hba, phy_no);
+}
+
+void hard_phy_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+	struct sas_ha_struct *sha = &hisi_hba->sha;
+
+	stop_phy_v1_hw(hisi_hba, phy_no);
+	sas_drain_work(sha);
+	msleep(100);
+	start_phy_v1_hw(hisi_hba, phy_no);
+}
+
 static void start_phys_v1_hw(unsigned long data)
 {
 	struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
-- 
1.9.1

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[PATCH 24/25] scsi: hisi_sas: add fatal irq handler

[John Garry]

Add handlers for fatal interrupts.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 118 +++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index b5ba46a..bc8e23e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -1621,6 +1621,91 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
+{
+	struct hisi_hba *hisi_hba = p;
+	u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+
+	if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("Fatal DQ 1b ECC interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, ecc_err);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
+				HGC_DQ_ECC_ADDR_BAD_MSK) >>
+				HGC_DQ_ECC_ADDR_BAD_OFF;
+
+		panic("Fatal DQ RAM ECC interrupt on controller %d @ 0x%08x\n",
+			hisi_hba->id, addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("Fatal IOST 1b ECC interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, ecc_err);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
+				HGC_IOST_ECC_ADDR_BAD_MSK) >>
+				HGC_IOST_ECC_ADDR_BAD_OFF;
+
+		panic("Fatal IOST RAM ECC interrupt on controller %d @ 0x%08x\n",
+			hisi_hba->id, addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
+				HGC_ITCT_ECC_ADDR_BAD_MSK) >>
+				HGC_ITCT_ECC_ADDR_BAD_OFF;
+
+		panic("Fatal TCT RAM ECC interrupt on controller %d @ 0x%08x\n",
+			hisi_hba->id, addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("Fatal ITCT 1b ECC interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, ecc_err);
+	}
+
+	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
+{
+	struct hisi_hba *hisi_hba = p;
+	u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
+	u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
+
+	if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
+		panic("Fatal DQ_CFG_ERR interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, axi_info);
+
+	if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
+		panic("Fatal CQ_CFG_ERR interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, axi_info);
+
+	if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
+		panic("Fatal AXI_WRONG_INT interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, axi_info);
+
+	if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
+		panic("Fatal AXI_OVERLF_INT incorrect interrupt on controller %d (0x%x)\n",
+			hisi_hba->id, axi_info);
+
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
+
+	return IRQ_HANDLED;
+}
+
 static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 	{"Bcast"},
 	{"Phy Up"},
@@ -1628,6 +1713,10 @@ static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 };
 
 static const char cq_int_name[32] = "cq";
+static const char fatal_int_name[HISI_SAS_FATAL_INT_NR][32] = {
+	"fatal ecc",
+	"fatal axi"
+};
 
 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
 	int_bcast_v1_hw,
@@ -1635,6 +1724,11 @@ static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
 	int_abnormal_v1_hw
 };
 
+static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
+	fatal_ecc_int_v1_hw,
+	fatal_axi_int_v1_hw
+};
+
 int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
 {
 	int i, j, irq, rc, id = hisi_hba->id;
@@ -1697,6 +1791,30 @@ int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
 		idx++;
 	}
 
+	for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++) {
+		int idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) +
+				hisi_hba->queue_count + i;
+
+		irq = irq_of_parse_and_map(np, idx);
+		if (!irq) {
+			dev_err(dev, "irq init: [%d] could not map fatal interrupt %d\n",
+				hisi_hba->id, idx);
+			return -ENOENT;
+		}
+		(void)snprintf(&int_names[idx * HISI_SAS_NAME_LEN],
+				HISI_SAS_NAME_LEN,
+				DRV_NAME" %s [%d]", fatal_int_name[i], id);
+		rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
+				&int_names[idx * HISI_SAS_NAME_LEN],
+				hisi_hba);
+		if (rc) {
+			dev_err(dev,
+				"irq init: [%d] could not request fatal interrupt %d, rc=%d\n",
+				hisi_hba->id, irq, rc);
+			return -ENOENT;
+		}
+		idx++;
+	}
 
 	return 0;
 }
-- 
1.9.1

[PATCH 25/25] MAINTAINERS: add maintainer for HiSi SAS driver

[John Garry]

Add maintainer for HiSilicon SAS driver.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 797236b..edea297 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4935,6 +4935,13 @@ F:	include/uapi/linux/if_hippi.h
 F:	net/802/hippi.c
 F:	drivers/net/hippi/
 
+HISILICON SAS Controller
+M:	John Garry <john.garry@hisilicon.com>
+W:	http://www.hisilicon.com
+S:	Supported
+F:	drivers/scsi/hisi_sas/
+F:	Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+
 HOST AP DRIVER
 M:	Jouni Malinen <j@w1.fi>
 L:	hostap@shmoo.com (subscribers-only)
-- 
1.9.1

Re: [PATCH 04/25] scsi: hisi_sas: add scsi host registration

[Arnd Bergmann]

On Monday 12 October 2015 23:20:16 John Garry wrote:
> +
> +       shost = scsi_host_alloc(&hisi_sas_sht, sizeof(void *));
> +       if (!shost)
> +               return -ENOMEM;
> +
> +       hisi_hba = hisi_sas_hba_alloc(pdev, shost, np);
> +       if (!hisi_hba) {
> +               rc = -ENOMEM;
> +               goto err_out_ha;
> +       }

You can collapse the allocations into one and just pass sizeof(*hisi_hba)
instead of sizeof(void *) above.


> +       sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
> +       platform_set_drvdata(pdev, sha);
> +
> +       phy_nr = port_nr = HISI_SAS_MAX_PHYS;
> +
> +       arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
> +       arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
> +       if (!arr_phy || !arr_port)
> +               return -ENOMEM;

And since these are fixed-size arrays, they can be moved in there as well.

	Arnd

Re: [PATCH 04/25] scsi: hisi_sas: add scsi host registration

[Arnd Bergmann]

On Monday 12 October 2015 23:20:16 John Garry wrote:
> +
> +       shost = scsi_host_alloc(&hisi_sas_sht, sizeof(void *));
> +       if (!shost)
> +               return -ENOMEM;
> +
> +       hisi_hba = hisi_sas_hba_alloc(pdev, shost, np);
> +       if (!hisi_hba) {
> +               rc = -ENOMEM;
> +               goto err_out_ha;
> +       }

You can collapse the allocations into one and just pass sizeof(*hisi_hba)
instead of sizeof(void *) above.


> +       sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
> +       platform_set_drvdata(pdev, sha);
> +
> +       phy_nr = port_nr = HISI_SAS_MAX_PHYS;
> +
> +       arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
> +       arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
> +       if (!arr_phy || !arr_port)
> +               return -ENOMEM;

And since these are fixed-size arrays, they can be moved in there as well.

	Arnd
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Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[Arnd Bergmann]

On Monday 12 October 2015 23:20:19 John Garry wrote:
> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
> +{
> +       struct platform_device *pdev = hisi_hba->pdev;
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       hisi_hba->regs = devm_ioremap(dev,
> +                                     res->start,
> +                                     resource_size(res));
> +       if (!hisi_hba->regs)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
> +                                          res->start,
> +                                          resource_size(res));
> +       if (!hisi_hba->ctrl_regs)
> +               return -ENOMEM;
> +
> +       return 0;
> +}
>  
>  static const struct of_device_id sas_of_match[] = {
> 

Better use devm_ioremap_resource() here, which registers the resource so they
are checked for conflicts and listed in /proc/iomem.

	Arnd

[RFC PATCH] scsi: hisi_sas: hisi_sas_ioremap() can be static

[kbuild test robot]

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
 hisi_sas_init.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
index 8f1e856..066c339 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
@@ -195,7 +195,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
 				  hisi_hba->sata_breakpoint_dma);
 }
 
-int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
+static int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
 {
 	struct platform_device *pdev = hisi_hba->pdev;
 	struct device *dev = &pdev->dev;

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/scsi/hisi_sas/hisi_sas_init.c:198:5: sparse: symbol 'hisi_sas_ioremap' was not declared. Should it be static?

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Re: [PATCH 12/25] scsi: hisi_sas: add v1 HW initialisation code

[Arnd Bergmann]

On Monday 12 October 2015 23:20:24 John Garry wrote:
> @@ -387,6 +392,21 @@ static int hisi_sas_probe(struct platform_device *pdev)
>         }
>  
>         hisi_sas_init_add(hisi_hba);
> +
> +       rc = hw_init_v1_hw(hisi_hba);
> +       if (rc)
> +               goto err_out_ha;
> +
> +       rc = interrupt_init_v1_hw(hisi_hba);
> +       if (rc)
> +               goto err_out_ha;
> +
> +       rc = interrupt_openall_v1_hw(hisi_hba);
> +       if (rc)
> +               goto err_out_ha;
> +
> +       phys_init_v1_hw(hisi_hba);
> +
>         rc = scsi_add_host(shost, &pdev->dev);
>         if (rc)
>                 goto err_out_ha;
> 

As the probe function matches against the "hisilicon,sas-controller-v1"
compatible string and contains mostly code that is specific to v1, I
think it would be cleaner to move that to the hisi_sas_v1_hw.c as well
and make the functions above static but make the common functions
called here (hisi_sas_init_add etc) global.

That would also include the hisi_sas_driver structure.

	Arnd

Re: [PATCH 10/25] scsi: hisi_sas: add misc HBA initialization

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/scsi/hisi_sas/hisi_sas_init.c:228:5: sparse: symbol 'hisi_sas_ioremap' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_init.c:318:47: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_init.c:318:47:    expected unsigned long long [unsigned] [usertype] dev_sas_addr
   drivers/scsi/hisi_sas/hisi_sas_init.c:318:47:    got restricted __be64 [usertype] <noident>

vim +318 drivers/scsi/hisi_sas/hisi_sas_init.c

307b867d John Garry 2015-10-12  222  				  hisi_hba->sata_breakpoint_dma);
ac2334d3 John Garry 2015-10-12  223  
ac2334d3 John Garry 2015-10-12  224  	if (hisi_hba->wq)
ac2334d3 John Garry 2015-10-12  225  		destroy_workqueue(hisi_hba->wq);
307b867d John Garry 2015-10-12  226  }
307b867d John Garry 2015-10-12  227  
2b5563f7 John Garry 2015-10-12 @228  int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
2b5563f7 John Garry 2015-10-12  229  {
2b5563f7 John Garry 2015-10-12  230  	struct platform_device *pdev = hisi_hba->pdev;
2b5563f7 John Garry 2015-10-12  231  	struct device *dev = &pdev->dev;
2b5563f7 John Garry 2015-10-12  232  	struct resource *res;
2b5563f7 John Garry 2015-10-12  233  
2b5563f7 John Garry 2015-10-12  234  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2b5563f7 John Garry 2015-10-12  235  	hisi_hba->regs = devm_ioremap(dev,
2b5563f7 John Garry 2015-10-12  236  				      res->start,
2b5563f7 John Garry 2015-10-12  237  				      resource_size(res));
2b5563f7 John Garry 2015-10-12  238  	if (!hisi_hba->regs)
2b5563f7 John Garry 2015-10-12  239  		return -ENOMEM;
2b5563f7 John Garry 2015-10-12  240  
2b5563f7 John Garry 2015-10-12  241  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2b5563f7 John Garry 2015-10-12  242  	hisi_hba->ctrl_regs = devm_ioremap(dev,
2b5563f7 John Garry 2015-10-12  243  					   res->start,
2b5563f7 John Garry 2015-10-12  244  					   resource_size(res));
2b5563f7 John Garry 2015-10-12  245  	if (!hisi_hba->ctrl_regs)
2b5563f7 John Garry 2015-10-12  246  		return -ENOMEM;
2b5563f7 John Garry 2015-10-12  247  
2b5563f7 John Garry 2015-10-12  248  	return 0;
2b5563f7 John Garry 2015-10-12  249  }
28e5387c John Garry 2015-10-12  250  
28e5387c John Garry 2015-10-12  251  static const struct of_device_id sas_of_match[] = {
28e5387c John Garry 2015-10-12  252  	{ .compatible = "hisilicon,sas-controller-v1",},
28e5387c John Garry 2015-10-12  253  	{},
28e5387c John Garry 2015-10-12  254  };
28e5387c John Garry 2015-10-12  255  MODULE_DEVICE_TABLE(of, sas_of_match);
b94d2f2e John Garry 2015-10-12  256  
b94d2f2e John Garry 2015-10-12  257  static struct hisi_hba *hisi_sas_hba_alloc(
b94d2f2e John Garry 2015-10-12  258  			struct platform_device *pdev,
b94d2f2e John Garry 2015-10-12  259  			struct Scsi_Host *shost,
b94d2f2e John Garry 2015-10-12  260  			struct device_node *np)
b94d2f2e John Garry 2015-10-12  261  {
b94d2f2e John Garry 2015-10-12  262  	int interrupt_count, interrupt_cells;
b94d2f2e John Garry 2015-10-12  263  	struct hisi_hba *hisi_hba;
b94d2f2e John Garry 2015-10-12  264  
b94d2f2e John Garry 2015-10-12  265  	hisi_hba = devm_kzalloc(&pdev->dev, sizeof(*hisi_hba), GFP_KERNEL);
b94d2f2e John Garry 2015-10-12  266  	if (!hisi_hba)
b94d2f2e John Garry 2015-10-12  267  		goto err_out;
b94d2f2e John Garry 2015-10-12  268  
b94d2f2e John Garry 2015-10-12  269  	hisi_hba->pdev = pdev;
307b867d John Garry 2015-10-12  270  
ac2334d3 John Garry 2015-10-12  271  	init_timer(&hisi_hba->timer);
ac2334d3 John Garry 2015-10-12  272  
307b867d John Garry 2015-10-12  273  	if (of_property_read_u32(np, "phy-count", &hisi_hba->n_phy))
307b867d John Garry 2015-10-12  274  		goto err_out;
307b867d John Garry 2015-10-12  275  
307b867d John Garry 2015-10-12  276  	if (of_property_read_u32(np, "queue-count", &hisi_hba->queue_count))
307b867d John Garry 2015-10-12  277  		goto err_out;
307b867d John Garry 2015-10-12  278  
307b867d John Garry 2015-10-12  279  	if (of_property_read_u32(np, "controller-id", &hisi_hba->id))
307b867d John Garry 2015-10-12  280  		goto err_out;
307b867d John Garry 2015-10-12  281  
307b867d John Garry 2015-10-12  282  	interrupt_count = of_property_count_u32_elems(np, "interrupts");
307b867d John Garry 2015-10-12  283  	if (interrupt_count < 0)
307b867d John Garry 2015-10-12  284  		goto err_out;
307b867d John Garry 2015-10-12  285  
307b867d John Garry 2015-10-12  286  	if (of_property_read_u32(np, "#interrupt-cells", &interrupt_cells))
307b867d John Garry 2015-10-12  287  		goto err_out;
307b867d John Garry 2015-10-12  288  
307b867d John Garry 2015-10-12  289  	hisi_hba->int_names = devm_kcalloc(&pdev->dev,
307b867d John Garry 2015-10-12  290  					   interrupt_count / interrupt_cells,
307b867d John Garry 2015-10-12  291  					   HISI_SAS_NAME_LEN,
307b867d John Garry 2015-10-12  292  					   GFP_KERNEL);
307b867d John Garry 2015-10-12  293  	if (!hisi_hba->int_names)
307b867d John Garry 2015-10-12  294  		goto err_out;
307b867d John Garry 2015-10-12  295  
b94d2f2e John Garry 2015-10-12  296  	hisi_hba->shost = shost;
b94d2f2e John Garry 2015-10-12  297  
2b5563f7 John Garry 2015-10-12  298  	if (hisi_sas_ioremap(hisi_hba))
2b5563f7 John Garry 2015-10-12  299  		goto err_out;
2b5563f7 John Garry 2015-10-12  300  
307b867d John Garry 2015-10-12  301  	if (hisi_sas_alloc(hisi_hba, shost)) {
307b867d John Garry 2015-10-12  302  		hisi_sas_free(hisi_hba);
307b867d John Garry 2015-10-12  303  		goto err_out;
307b867d John Garry 2015-10-12  304  	}
307b867d John Garry 2015-10-12  305  
b94d2f2e John Garry 2015-10-12  306  	return hisi_hba;
b94d2f2e John Garry 2015-10-12  307  err_out:
b94d2f2e John Garry 2015-10-12  308  	dev_err(&pdev->dev, "hba alloc failed\n");
b94d2f2e John Garry 2015-10-12  309  	return NULL;
b94d2f2e John Garry 2015-10-12  310  }
b94d2f2e John Garry 2015-10-12  311  
f6486930 John Garry 2015-10-12  312  static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
f6486930 John Garry 2015-10-12  313  {
f6486930 John Garry 2015-10-12  314  	u8 i;
f6486930 John Garry 2015-10-12  315  
f6486930 John Garry 2015-10-12  316  	/* Huawei IEEE id (001882) */
f6486930 John Garry 2015-10-12  317  	for (i = 0; i < hisi_hba->n_phy; i++)
f6486930 John Garry 2015-10-12 @318  		hisi_hba->phy[i].dev_sas_addr =
f6486930 John Garry 2015-10-12  319  			cpu_to_be64(0x5001882016072015ULL);
f6486930 John Garry 2015-10-12  320  
f6486930 John Garry 2015-10-12  321  	memcpy(hisi_hba->sas_addr, &hisi_hba->phy[0].dev_sas_addr,

:::::: The code at line 318 was first introduced by commit
:::::: f6486930094e8da780099095ad77e86b3b766008 scsi: hisi_sas: add phy SAS ADDR initialization

:::::: TO: John Garry <john.garry@huawei.com>
:::::: CC: 0day robot <fengguang.wu@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)


Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[RFC PATCH] scsi: hisi_sas: hisi_sas_bytes_dmaed() can be static

[kbuild test robot]

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
 hisi_sas_main.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 72831db..08b2af8 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -28,7 +28,7 @@ void hisi_sas_slot_index_init(struct hisi_hba *hisi_hba)
 }
 
 
-void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
+static void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
 {
 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 	struct asd_sas_phy *sas_phy = &phy->sas_phy;

Re: [PATCH 15/25] scsi: hisi_sas: add cq interrupt handler

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:692:6: sparse: symbol 'enable_phy_v1_hw' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:973:36: sparse: cast from restricted __le32
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:973:36: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:973:36:    expected unsigned int [unsigned] [usertype] dma_err_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:973:36:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:981:33: sparse: cast from restricted __le32
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:981:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:981:33:    expected unsigned int [unsigned] [usertype] trans_tx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:981:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:983:33: sparse: cast from restricted __le32
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:983:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:983:33:    expected unsigned int [unsigned] [usertype] trans_rx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:983:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1079:5: sparse: symbol 'slot_complete_v1_hw' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1333:34: sparse: cast from restricted __le32
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1333:32: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1333:32:    expected unsigned int [unsigned] [usertype] cmplt_hdr_data
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1333:32:    got restricted __le32 [usertype] <noident>

vim +973 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

   967		struct device *dev = &hisi_hba->pdev->dev;
   968	
   969		switch (task->task_proto) {
   970		case SAS_PROTOCOL_SSP:
   971		{
   972			int error = -1;
 > 973			u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
   974			u32 dma_tx_err_type = ((dma_err_type &
   975						ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
   976						ERR_HDR_DMA_TX_ERR_TYPE_OFF;
   977			u32 dma_rx_err_type = ((dma_err_type &
   978						ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
   979						ERR_HDR_DMA_RX_ERR_TYPE_OFF;
   980			u32 trans_tx_fail_type =
 > 981					cpu_to_le32(err_record->trans_tx_fail_type);
   982			u32 trans_rx_fail_type =
 > 983					cpu_to_le32(err_record->trans_rx_fail_type);
   984	
   985			if (dma_tx_err_type) {
   986				/* dma tx err */

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Re: [PATCH 16/25] scsi: hisi_sas: add dev_found and port_formed

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/scsi/hisi_sas/hisi_sas_main.c:321:6: sparse: symbol 'hisi_sas_bytes_dmaed' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:358:24: sparse: symbol 'hisi_sas_alloc_dev' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:376:5: sparse: symbol 'hisi_sas_dev_found_notify' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:479:6: sparse: symbol 'hisi_sas_port_notify_formed' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:428:9: sparse: context imbalance in 'hisi_sas_dev_found_notify' - different lock contexts for basic block
>> drivers/scsi/hisi_sas/hisi_sas_main.c:479:6: sparse: context imbalance in 'hisi_sas_port_notify_formed' - different lock contexts for basic block
--
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: incorrect type in argument 1 (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26:    expected unsigned long long [unsigned] [usertype] val
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26:    got restricted __le64 [usertype] sas_addr
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24:    expected restricted __le64 [usertype] sas_addr
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24:    got unsigned long long
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:733:6: sparse: symbol 'enable_phy_v1_hw' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1014:36: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1014:36: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1014:36:    expected unsigned int [unsigned] [usertype] dma_err_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1014:36:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1022:33: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1022:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1022:33:    expected unsigned int [unsigned] [usertype] trans_tx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1022:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1024:33: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1024:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1024:33:    expected unsigned int [unsigned] [usertype] trans_rx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1024:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1120:5: sparse: symbol 'slot_complete_v1_hw' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1374:34: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1374:32: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1374:32:    expected unsigned int [unsigned] [usertype] cmplt_hdr_data
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1374:32:    got restricted __le32 [usertype] <noident>

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[RFC PATCH] scsi: hisi_sas: hisi_sas_alloc_dev() can be static

[kbuild test robot]

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
 hisi_sas_main.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 44cb9085..f7ee97a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -355,7 +355,7 @@ void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no)
 	sas_ha->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
 }
 
-struct hisi_sas_device *hisi_sas_alloc_dev(struct hisi_hba *hisi_hba)
+static struct hisi_sas_device *hisi_sas_alloc_dev(struct hisi_hba *hisi_hba)
 {
 	int dev_id;
 	struct device *dev = &hisi_hba->pdev->dev;
@@ -373,7 +373,7 @@ struct hisi_sas_device *hisi_sas_alloc_dev(struct hisi_hba *hisi_hba)
 	return NULL;
 }
 
-int hisi_sas_dev_found_notify(struct domain_device *device, int lock)
+static int hisi_sas_dev_found_notify(struct domain_device *device, int lock)
 {
 	unsigned long flags = 0;
 	int res = 0;
@@ -476,7 +476,7 @@ void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
 	sas_phy->lldd_phy = phy;
 }
 
-void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
+static void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
 {
 	struct sas_ha_struct *sas_ha = sas_phy->ha;
 	struct hisi_hba *hisi_hba = NULL;

Re: [PATCH 18/25] scsi: hisi_sas: add dev_gone and port_deformed

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/scsi/hisi_sas/hisi_sas_main.c:321:6: sparse: symbol 'hisi_sas_bytes_dmaed' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:358:24: sparse: symbol 'hisi_sas_alloc_dev' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:376:5: sparse: symbol 'hisi_sas_dev_found_notify' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:479:6: sparse: symbol 'hisi_sas_port_notify_formed' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:517:6: sparse: symbol 'hisi_sas_do_release_task' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:428:9: sparse: context imbalance in 'hisi_sas_dev_found_notify' - different lock contexts for basic block
   drivers/scsi/hisi_sas/hisi_sas_main.c:479:6: sparse: context imbalance in 'hisi_sas_port_notify_formed' - different lock contexts for basic block
--
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: incorrect type in argument 1 (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26:    expected unsigned long long [unsigned] [usertype] val
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26:    got restricted __le64 [usertype] sas_addr
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:26: sparse: cast from restricted __le64
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24:    expected restricted __le64 [usertype] sas_addr
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:528:24:    got unsigned long long
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:553:15: sparse: cast from restricted __le64
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:553:13: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:553:13:    expected unsigned int [unsigned] [usertype] qw0
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:553:13:    got restricted __le64 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:761:6: sparse: symbol 'enable_phy_v1_hw' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1042:36: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1042:36: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1042:36:    expected unsigned int [unsigned] [usertype] dma_err_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1042:36:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1050:33: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1050:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1050:33:    expected unsigned int [unsigned] [usertype] trans_tx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1050:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1052:33: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1052:33: sparse: incorrect type in initializer (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1052:33:    expected unsigned int [unsigned] [usertype] trans_rx_fail_type
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1052:33:    got restricted __le32 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1456:34: sparse: cast from restricted __le32
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1456:32: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1456:32:    expected unsigned int [unsigned] [usertype] cmplt_hdr_data
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:1456:32:    got restricted __le32 [usertype] <noident>

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructure                Open Source Technology Center
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[RFC PATCH] scsi: hisi_sas: hisi_sas_do_release_task() can be static

[kbuild test robot]

Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
 hisi_sas_main.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 36ef8cd..38f581f 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -514,7 +514,7 @@ void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
 		spin_unlock_irqrestore(&hisi_hba->lock, flags);
 }
 
-void hisi_sas_do_release_task(struct hisi_hba *hisi_hba,
+static void hisi_sas_do_release_task(struct hisi_hba *hisi_hba,
 		int phy_no, struct domain_device *device)
 {
 	struct hisi_sas_phy *phy;

[RFC PATCH] scsi: hisi_sas: hisi_sas_find_dev_phyno() can be static

[kbuild test robot]

Signed-off-by: Fengguang Wu <fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
 hisi_sas_main.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 12af29c..a01e8c0 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -612,7 +612,7 @@ int hisi_sas_dev_found(struct domain_device *device)
 	return hisi_sas_dev_found_notify(device, 1);
 }
 
-int hisi_sas_find_dev_phyno(struct domain_device *device, int *phyno)
+static int hisi_sas_find_dev_phyno(struct domain_device *device, int *phyno)
 {
 	int i = 0, j = 0, num = 0, n = 0;
 	struct sas_ha_struct *sha = device->port->ha;
--
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Re: [PATCH 22/25] scsi: hisi_sas: add tmf methods

[kbuild test robot]

Hi John,

[auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

   drivers/scsi/hisi_sas/hisi_sas_main.c:341:6: sparse: symbol 'hisi_sas_bytes_dmaed' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:378:24: sparse: symbol 'hisi_sas_alloc_dev' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:396:5: sparse: symbol 'hisi_sas_dev_found_notify' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:523:6: sparse: symbol 'hisi_sas_port_notify_formed' was not declared. Should it be static?
   drivers/scsi/hisi_sas/hisi_sas_main.c:561:6: sparse: symbol 'hisi_sas_do_release_task' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:615:5: sparse: symbol 'hisi_sas_find_dev_phyno' was not declared. Should it be static?
>> drivers/scsi/hisi_sas/hisi_sas_main.c:852:52: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_main.c:852:52:    expected unsigned short [unsigned] [assigned] [usertype] tag_of_task_to_be_managed
   drivers/scsi/hisi_sas/hisi_sas_main.c:852:52:    got restricted __le16 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_main.c:1000:52: sparse: incorrect type in assignment (different base types)
   drivers/scsi/hisi_sas/hisi_sas_main.c:1000:52:    expected unsigned short [unsigned] [assigned] [usertype] tag_of_task_to_be_managed
   drivers/scsi/hisi_sas/hisi_sas_main.c:1000:52:    got restricted __le16 [usertype] <noident>
   drivers/scsi/hisi_sas/hisi_sas_main.c:448:9: sparse: context imbalance in 'hisi_sas_dev_found_notify' - different lock contexts for basic block
   drivers/scsi/hisi_sas/hisi_sas_main.c:523:6: sparse: context imbalance in 'hisi_sas_port_notify_formed' - different lock contexts for basic block

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Julian Calaby]

Hi kbuild test robot people,

On Tue, Oct 13, 2015 at 9:03 AM, kbuild test robot <lkp@intel.com> wrote:
> Hi John,
>
> [auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
>
> url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
> reproduce:
>         # apt-get install sparse
>         make ARCH=x86_64 allmodconfig
>         make C=1 CF=-D__CHECK_ENDIAN__
>
>
> sparse warnings: (new ones prefixed by >>)

Your script seems to have lost the actual warnings here.

> Please review and possibly fold the followup patch.

Thanks,

-- 
Julian Calaby

Email: julian.calaby@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/

Re: [lkp] [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Fengguang Wu]

Hi Julian,

Oops, this is awkward.. I'll check it, thank you for the reminder!

Thanks,
Fengguang

On Tue, Oct 13, 2015 at 11:27:05AM +1100, Julian Calaby wrote:
> Hi kbuild test robot people,
> 
> On Tue, Oct 13, 2015 at 9:03 AM, kbuild test robot <lkp@intel.com> wrote:
> > Hi John,
> >
> > [auto build test WARNING on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
> >
> > url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
> > reproduce:
> >         # apt-get install sparse
> >         make ARCH=x86_64 allmodconfig
> >         make C=1 CF=-D__CHECK_ENDIAN__
> >
> >
> > sparse warnings: (new ones prefixed by >>)
> 
> Your script seems to have lost the actual warnings here.
> 
> > Please review and possibly fold the followup patch.
> 
> Thanks,
> 
> -- 
> Julian Calaby
> 
> Email: julian.calaby@gmail.com
> Profile: http://www.google.com/profiles/julian.calaby/

Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 5845 bytes --]

Hi John,

[auto build test ERROR on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
config: m68k-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=m68k 

All error/warnings (new ones prefixed by >>):

   drivers/scsi/hisi_sas/hisi_sas_init.c: In function 'hisi_sas_alloc':
>> drivers/scsi/hisi_sas/hisi_sas_init.c:65:2: error: implicit declaration of function 'dma_pool_create' [-Werror=implicit-function-declaration]
     hisi_hba->status_buffer_pool = dma_pool_create(name,
     ^
>> drivers/scsi/hisi_sas/hisi_sas_init.c:65:31: warning: assignment makes pointer from integer without a cast
     hisi_hba->status_buffer_pool = dma_pool_create(name,
                                  ^
   drivers/scsi/hisi_sas/hisi_sas_init.c:73:31: warning: assignment makes pointer from integer without a cast
     hisi_hba->command_table_pool = dma_pool_create(name,
                                  ^
   drivers/scsi/hisi_sas/hisi_sas_init.c:115:26: warning: assignment makes pointer from integer without a cast
     hisi_hba->sge_page_pool = dma_pool_create(name, dev,
                             ^
   drivers/scsi/hisi_sas/hisi_sas_init.c: In function 'hisi_sas_free':
>> drivers/scsi/hisi_sas/hisi_sas_init.c:159:3: error: implicit declaration of function 'dma_pool_destroy' [-Werror=implicit-function-declaration]
      dma_pool_destroy(hisi_hba->status_buffer_pool);
      ^
   cc1: some warnings being treated as errors

vim +/dma_pool_create +65 drivers/scsi/hisi_sas/hisi_sas_init.c

    59			memset(hisi_hba->complete_hdr[i], 0, s);
    60		}
    61	
    62		sprintf(name, "%s%d", "hisi_sas_status_buffer_pool",
    63			hisi_hba->id);
    64		s = HISI_SAS_STATUS_BUF_SZ;
  > 65		hisi_hba->status_buffer_pool = dma_pool_create(name,
    66							       dev, s, 16, 0);
    67		if (!hisi_hba->status_buffer_pool)
    68			goto err_out;
    69	
    70		sprintf(name, "%s%d", "hisi_sas_command_table_pool",
    71			hisi_hba->id);
    72		s = HISI_SAS_COMMAND_TABLE_SZ;
  > 73		hisi_hba->command_table_pool = dma_pool_create(name,
    74							       dev, s, 16, 0);
    75		if (!hisi_hba->command_table_pool)
    76			goto err_out;
    77	
    78		s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
    79		hisi_hba->itct = dma_alloc_coherent(dev, s, &hisi_hba->itct_dma,
    80						    GFP_KERNEL);
    81		if (!hisi_hba->itct)
    82			goto err_out;
    83	
    84		memset(hisi_hba->itct, 0, s);
    85	
    86		hisi_hba->slot_info = devm_kcalloc(dev, HISI_SAS_COMMAND_ENTRIES,
    87						   sizeof(struct hisi_sas_slot),
    88						   GFP_KERNEL);
    89		if (!hisi_hba->slot_info)
    90			goto err_out;
    91	
    92		s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_iost);
    93		hisi_hba->iost = dma_alloc_coherent(dev, s, &hisi_hba->iost_dma,
    94						    GFP_KERNEL);
    95		if (!hisi_hba->iost)
    96			goto err_out;
    97	
    98		memset(hisi_hba->iost, 0, s);
    99	
   100		s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint);
   101		hisi_hba->breakpoint = dma_alloc_coherent(dev, s,
   102					&hisi_hba->breakpoint_dma, GFP_KERNEL);
   103		if (!hisi_hba->breakpoint)
   104			goto err_out;
   105	
   106		memset(hisi_hba->breakpoint, 0, s);
   107	
   108		hisi_hba->slot_index_count = HISI_SAS_COMMAND_ENTRIES;
   109		s = hisi_hba->slot_index_count / sizeof(unsigned long);
   110		hisi_hba->slot_index_tags = devm_kzalloc(dev, s, GFP_KERNEL);
   111		if (!hisi_hba->slot_index_tags)
   112			goto err_out;
   113	
   114		sprintf(name, "%s%d", "hisi_sas_status_sge_pool", hisi_hba->id);
   115		hisi_hba->sge_page_pool = dma_pool_create(name, dev,
   116					sizeof(struct hisi_sas_sge_page), 16, 0);
   117		if (!hisi_hba->sge_page_pool)
   118			goto err_out;
   119	
   120		s = sizeof(struct hisi_sas_initial_fis) * HISI_SAS_MAX_PHYS;
   121		hisi_hba->initial_fis = dma_alloc_coherent(dev, s,
   122					&hisi_hba->initial_fis_dma, GFP_KERNEL);
   123		if (!hisi_hba->initial_fis)
   124			goto err_out;
   125		memset(hisi_hba->initial_fis, 0, s);
   126	
   127		s = HISI_SAS_COMMAND_ENTRIES * sizeof(struct hisi_sas_breakpoint) * 2;
   128		hisi_hba->sata_breakpoint = dma_alloc_coherent(dev, s,
   129					&hisi_hba->sata_breakpoint_dma, GFP_KERNEL);
   130		if (!hisi_hba->sata_breakpoint)
   131			goto err_out;
   132		memset(hisi_hba->sata_breakpoint, 0, s);
   133	
   134		return 0;
   135	err_out:
   136		return -ENOMEM;
   137	}
   138	
   139	static void hisi_sas_free(struct hisi_hba *hisi_hba)
   140	{
   141		int i, s;
   142		struct device *dev = &hisi_hba->pdev->dev;
   143	
   144		for (i = 0; i < hisi_hba->queue_count; i++) {
   145			s = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
   146			if (hisi_hba->cmd_hdr[i])
   147				dma_free_coherent(dev, s,
   148						  hisi_hba->cmd_hdr[i],
   149						  hisi_hba->cmd_hdr_dma[i]);
   150	
   151			s = sizeof(struct hisi_sas_complete_hdr) * HISI_SAS_QUEUE_SLOTS;
   152			if (hisi_hba->complete_hdr[i])
   153				dma_free_coherent(dev, s,
   154						  hisi_hba->complete_hdr[i],
   155						  hisi_hba->complete_hdr_dma[i]);
   156		}
   157	
   158		if (hisi_hba->status_buffer_pool)
 > 159			dma_pool_destroy(hisi_hba->status_buffer_pool);
   160	
   161		if (hisi_hba->command_table_pool)
   162			dma_pool_destroy(hisi_hba->command_table_pool);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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Re: [PATCH 14/25] scsi: hisi_sas: add ssp command function

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4642 bytes --]

Hi John,

[auto build test ERROR on scsi/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/John-Garry/HiSilicon-SAS-driver/20151012-231929
config: m68k-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=m68k 

All error/warnings (new ones prefixed by >>):

   drivers/scsi/hisi_sas/hisi_sas_main.c: In function 'hisi_sas_task_prep':
>> drivers/scsi/hisi_sas/hisi_sas_main.c:169:2: error: implicit declaration of function 'dma_pool_alloc' [-Werror=implicit-function-declaration]
     slot->status_buffer = dma_pool_alloc(hisi_hba->status_buffer_pool,
     ^
>> drivers/scsi/hisi_sas/hisi_sas_main.c:169:22: warning: assignment makes pointer from integer without a cast
     slot->status_buffer = dma_pool_alloc(hisi_hba->status_buffer_pool,
                         ^
   drivers/scsi/hisi_sas/hisi_sas_main.c:176:22: warning: assignment makes pointer from integer without a cast
     slot->command_table = dma_pool_alloc(hisi_hba->command_table_pool,
                         ^
>> drivers/scsi/hisi_sas/hisi_sas_main.c:226:2: error: implicit declaration of function 'dma_pool_free' [-Werror=implicit-function-declaration]
     dma_pool_free(hisi_hba->sge_page_pool, slot->sge_page,
     ^
   cc1: some warnings being treated as errors
--
   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c: In function 'prep_prd_sge_v1_hw':
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:822:2: error: implicit declaration of function 'dma_pool_alloc' [-Werror=implicit-function-declaration]
     slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
     ^
>> drivers/scsi/hisi_sas/hisi_sas_v1_hw.c:822:17: warning: assignment makes pointer from integer without a cast
     slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
                    ^
   cc1: some warnings being treated as errors

vim +/dma_pool_alloc +169 drivers/scsi/hisi_sas/hisi_sas_main.c

   163		slot->n_elem = n_elem;
   164		slot->dlvry_queue = dlvry_queue;
   165		slot->dlvry_queue_slot = dlvry_queue_slot;
   166		cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];
   167		slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];
   168	
 > 169		slot->status_buffer = dma_pool_alloc(hisi_hba->status_buffer_pool,
   170						     GFP_ATOMIC,
   171						     &slot->status_buffer_dma);
   172		if (!slot->status_buffer)
   173			goto err_out_slot_buf;
   174		memset(slot->status_buffer, 0, HISI_SAS_STATUS_BUF_SZ);
   175	
   176		slot->command_table = dma_pool_alloc(hisi_hba->command_table_pool,
   177						     GFP_ATOMIC,
   178						     &slot->command_table_dma);
   179		if (!slot->command_table)
   180			goto err_out_status_buf;
   181		memset(slot->command_table, 0, HISI_SAS_COMMAND_TABLE_SZ);
   182		memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));
   183	
   184		tei.hdr = slot->cmd_hdr;
   185		tei.task = task;
   186		tei.n_elem = n_elem;
   187		tei.slot = slot;
   188		switch (task->task_proto) {
   189		case SAS_PROTOCOL_SSP:
   190			rc = hisi_sas_task_prep_ssp(hisi_hba, &tei, is_tmf, tmf);
   191			break;
   192		case SAS_PROTOCOL_SMP:
   193		case SAS_PROTOCOL_SATA:
   194		case SAS_PROTOCOL_STP:
   195		case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
   196		default:
   197			dev_err(dev, "task prep: unknown/unsupported proto (0x%x)\n",
   198				task->task_proto);
   199			rc = -EINVAL;
   200			break;
   201		}
   202	
   203		if (rc) {
   204			dev_err(dev, "task prep: rc = 0x%x\n", rc);
   205			if (slot->sge_page)
   206				goto err_out_sge;
   207			goto err_out_command_table;
   208		}
   209	
   210		slot->task = task;
   211		slot->port = tei.port;
   212		task->lldd_task = slot;
   213		list_add_tail(&slot->entry, &tei.port->list);
   214		spin_lock(&task->task_state_lock);
   215		task->task_state_flags |= SAS_TASK_AT_INITIATOR;
   216		spin_unlock(&task->task_state_lock);
   217	
   218		hisi_hba->slot_prep = slot;
   219	
   220		sas_dev->running_req++;
   221		++(*pass);
   222	
   223		return rc;
   224	
   225	err_out_sge:
 > 226		dma_pool_free(hisi_hba->sge_page_pool, slot->sge_page,
   227			slot->sge_page_dma);
   228	err_out_command_table:
   229		dma_pool_free(hisi_hba->command_table_pool, slot->command_table,

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[Hannes Reinecke]

On 10/12/2015 05:20 PM, John Garry wrote:
> This SAS ID is chosen as Huawei IEEE id: 001882
> 
> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
>  drivers/scsi/hisi_sas/hisi_sas_init.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
> index 44fc524..c295c39 100644
> --- a/drivers/scsi/hisi_sas/hisi_sas_init.c
> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
> @@ -283,6 +283,19 @@ err_out:
>  	return NULL;
>  }
>  
> +static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
> +{
> +	u8 i;
> +
> +	/* Huawei IEEE id (001882) */
> +	for (i = 0; i < hisi_hba->n_phy; i++)
> +		hisi_hba->phy[i].dev_sas_addr =
> +			cpu_to_be64(0x5001882016072015ULL);
> +
Ouch. Each phy has the same SAS address?
For all boards? Ever?

Not sure if that's a good idea, nor even valid.
It'll confuse the hell out of any SAS array.

Please provide a means of having individual SAS addresses for each HBA.

Cheers,

Hannes
-- 
Dr. Hannes Reinecke		               zSeries & Storage
hare@suse.de			               +49 911 74053 688
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
HRB 21284 (AG Nürnberg)
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Re: [PATCH 04/25] scsi: hisi_sas: add scsi host registration

[John Garry]

On 12/10/2015 16:21, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:16 John Garry wrote:
>> +
>> +       shost = scsi_host_alloc(&hisi_sas_sht, sizeof(void *));
>> +       if (!shost)
>> +               return -ENOMEM;
>> +
>> +       hisi_hba = hisi_sas_hba_alloc(pdev, shost, np);
>> +       if (!hisi_hba) {
>> +               rc = -ENOMEM;
>> +               goto err_out_ha;
>> +       }
>
> You can collapse the allocations into one and just pass sizeof(*hisi_hba)
> instead of sizeof(void *) above.
>
Will address.

>
>> +       sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
>> +       platform_set_drvdata(pdev, sha);
>> +
>> +       phy_nr = port_nr = HISI_SAS_MAX_PHYS;
>> +
>> +       arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
>> +       arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
>> +       if (!arr_phy || !arr_port)
>> +               return -ENOMEM;
>
> And since these are fixed-size arrays, they can be moved in there as well.
>
In a later patch we set as follows:
phy_nr = port_nr = hisi_hba->n_phy;

You did say in our earlier private review that we could add statically 
to hba strcut, but I commented that other vendors do similar so I would 
wait for more input.

> 	Arnd
>
> .
>

Thanks,
John

Re: [PATCH 04/25] scsi: hisi_sas: add scsi host registration

[John Garry]

On 12/10/2015 16:21, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:16 John Garry wrote:
>> +
>> +       shost = scsi_host_alloc(&hisi_sas_sht, sizeof(void *));
>> +       if (!shost)
>> +               return -ENOMEM;
>> +
>> +       hisi_hba = hisi_sas_hba_alloc(pdev, shost, np);
>> +       if (!hisi_hba) {
>> +               rc = -ENOMEM;
>> +               goto err_out_ha;
>> +       }
>
> You can collapse the allocations into one and just pass sizeof(*hisi_hba)
> instead of sizeof(void *) above.
>
Will address.

>
>> +       sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
>> +       platform_set_drvdata(pdev, sha);
>> +
>> +       phy_nr = port_nr = HISI_SAS_MAX_PHYS;
>> +
>> +       arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
>> +       arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
>> +       if (!arr_phy || !arr_port)
>> +               return -ENOMEM;
>
> And since these are fixed-size arrays, they can be moved in there as well.
>
In a later patch we set as follows:
phy_nr = port_nr = hisi_hba->n_phy;

You did say in our earlier private review that we could add statically 
to hba strcut, but I commented that other vendors do similar so I would 
wait for more input.

> 	Arnd
>
> .
>

Thanks,
John

Re: [PATCH 05/25] scsi: hisi_sas: allocate memories and create pools

[zhangfei]

Hi, Arnd

On 10/12/2015 11:15 PM, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:17 John Garry wrote:
>> +       interrupt_count = of_property_count_u32_elems(np, "interrupts");
>> +       if (interrupt_count < 0)
>> +               goto err_out;
>> +
>> +       if (of_property_read_u32(np, "#interrupt-cells", &interrupt_cells))
>> +               goto err_out;
>> +
>> +       hisi_hba->int_names = devm_kcalloc(&pdev->dev,
>> +                                          interrupt_count / interrupt_cells,
>> +                                          HISI_SAS_NAME_LEN,
>> +                                          GFP_KERNEL);
>>
>
> This computation looks wrong: the "interrupts" property refers to interrupts
> that are referenced by this node and provided by an interrupt-controller,
> while the "#interrupt-cells" property refers to interrupts provided by
> this node. They don't need to have any relation.
>
We will use of_irq_count instead.

Thanks

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[zhangfei]

On 10/12/2015 11:21 PM, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:19 John Garry wrote:
>> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
>> +{
>> +       struct platform_device *pdev = hisi_hba->pdev;
>> +       struct device *dev = &pdev->dev;
>> +       struct resource *res;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       hisi_hba->regs = devm_ioremap(dev,
>> +                                     res->start,
>> +                                     resource_size(res));
>> +       if (!hisi_hba->regs)
>> +               return -ENOMEM;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
>> +                                          res->start,
>> +                                          resource_size(res));
>> +       if (!hisi_hba->ctrl_regs)
>> +               return -ENOMEM;
>> +
>> +       return 0;
>> +}
>>
>>   static const struct of_device_id sas_of_match[] = {
>>
>
> Better use devm_ioremap_resource() here, which registers the resource so they
> are checked for conflicts and listed in /proc/iomem.
>

Yes, hisi_hba->regs can use devm_ioremap_resource.

However ctrl_regs have to use devm_ioremap, since the address are 
sharing among different nodes, unfortunately, and devm_ioremap_resource 
will fail.

Thanks

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[zhangfei]

On 10/12/2015 11:21 PM, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:19 John Garry wrote:
>> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
>> +{
>> +       struct platform_device *pdev = hisi_hba->pdev;
>> +       struct device *dev = &pdev->dev;
>> +       struct resource *res;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       hisi_hba->regs = devm_ioremap(dev,
>> +                                     res->start,
>> +                                     resource_size(res));
>> +       if (!hisi_hba->regs)
>> +               return -ENOMEM;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
>> +                                          res->start,
>> +                                          resource_size(res));
>> +       if (!hisi_hba->ctrl_regs)
>> +               return -ENOMEM;
>> +
>> +       return 0;
>> +}
>>
>>   static const struct of_device_id sas_of_match[] = {
>>
>
> Better use devm_ioremap_resource() here, which registers the resource so they
> are checked for conflicts and listed in /proc/iomem.
>

Yes, hisi_hba->regs can use devm_ioremap_resource.

However ctrl_regs have to use devm_ioremap, since the address are 
sharing among different nodes, unfortunately, and devm_ioremap_resource 
will fail.

Thanks
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Re: [PATCH 04/25] scsi: hisi_sas: add scsi host registration

[Arnd Bergmann]

On Tuesday 13 October 2015 10:16:55 John Garry wrote:
> 
> >
> >> +       sha = SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
> >> +       platform_set_drvdata(pdev, sha);
> >> +
> >> +       phy_nr = port_nr = HISI_SAS_MAX_PHYS;
> >> +
> >> +       arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
> >> +       arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
> >> +       if (!arr_phy || !arr_port)
> >> +               return -ENOMEM;
> >
> > And since these are fixed-size arrays, they can be moved in there as well.
> >
> In a later patch we set as follows:
> phy_nr = port_nr = hisi_hba->n_phy;
> 
> You did say in our earlier private review that we could add statically 
> to hba strcut, but I commented that other vendors do similar so I would 
> wait for more input.

Ok, I forgot about that.

	Arnd

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[Arnd Bergmann]

On Tuesday 13 October 2015 17:47:02 zhangfei wrote:
> On 10/12/2015 11:21 PM, Arnd Bergmann wrote:
> > On Monday 12 October 2015 23:20:19 John Garry wrote:
> >> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
> >> +{
> >> +       struct platform_device *pdev = hisi_hba->pdev;
> >> +       struct device *dev = &pdev->dev;
> >> +       struct resource *res;
> >> +
> >> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >> +       hisi_hba->regs = devm_ioremap(dev,
> >> +                                     res->start,
> >> +                                     resource_size(res));
> >> +       if (!hisi_hba->regs)
> >> +               return -ENOMEM;
> >> +
> >> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> >> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
> >> +                                          res->start,
> >> +                                          resource_size(res));
> >> +       if (!hisi_hba->ctrl_regs)
> >> +               return -ENOMEM;
> >> +
> >> +       return 0;
> >> +}
> >>
> >>   static const struct of_device_id sas_of_match[] = {
> >>
> >
> > Better use devm_ioremap_resource() here, which registers the resource so they
> > are checked for conflicts and listed in /proc/iomem.
> >
> 
> Yes, hisi_hba->regs can use devm_ioremap_resource.
> 
> However ctrl_regs have to use devm_ioremap, since the address are 
> sharing among different nodes, unfortunately, and devm_ioremap_resource 
> will fail.

This sounds like it should be fixed in the DT binding then, to ensure
that the ranges don't overlap.

Mapping the same register region multiple times is generally considered
a bad idea because the drivers that map them often don't have global
locks that serialize the access, so it's better to have code in place
that ensures that they are distinct.

What is the purpose of the ctrl_regs region, and why is it shared
across multiple devices?

Are all users of these registers in the same driver?

	Arnd

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[Arnd Bergmann]

On Tuesday 13 October 2015 17:47:02 zhangfei wrote:
> On 10/12/2015 11:21 PM, Arnd Bergmann wrote:
> > On Monday 12 October 2015 23:20:19 John Garry wrote:
> >> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
> >> +{
> >> +       struct platform_device *pdev = hisi_hba->pdev;
> >> +       struct device *dev = &pdev->dev;
> >> +       struct resource *res;
> >> +
> >> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >> +       hisi_hba->regs = devm_ioremap(dev,
> >> +                                     res->start,
> >> +                                     resource_size(res));
> >> +       if (!hisi_hba->regs)
> >> +               return -ENOMEM;
> >> +
> >> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> >> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
> >> +                                          res->start,
> >> +                                          resource_size(res));
> >> +       if (!hisi_hba->ctrl_regs)
> >> +               return -ENOMEM;
> >> +
> >> +       return 0;
> >> +}
> >>
> >>   static const struct of_device_id sas_of_match[] = {
> >>
> >
> > Better use devm_ioremap_resource() here, which registers the resource so they
> > are checked for conflicts and listed in /proc/iomem.
> >
> 
> Yes, hisi_hba->regs can use devm_ioremap_resource.
> 
> However ctrl_regs have to use devm_ioremap, since the address are 
> sharing among different nodes, unfortunately, and devm_ioremap_resource 
> will fail.

This sounds like it should be fixed in the DT binding then, to ensure
that the ranges don't overlap.

Mapping the same register region multiple times is generally considered
a bad idea because the drivers that map them often don't have global
locks that serialize the access, so it's better to have code in place
that ensures that they are distinct.

What is the purpose of the ctrl_regs region, and why is it shared
across multiple devices?

Are all users of these registers in the same driver?

	Arnd
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Re: [PATCH 12/25] scsi: hisi_sas: add v1 HW initialisation code

[John Garry]

On 12/10/2015 19:46, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:24 John Garry wrote:
>> @@ -387,6 +392,21 @@ static int hisi_sas_probe(struct platform_device *pdev)
>>          }
>>
>>          hisi_sas_init_add(hisi_hba);
>> +
>> +       rc = hw_init_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       rc = interrupt_init_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       rc = interrupt_openall_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       phys_init_v1_hw(hisi_hba);
>> +
>>          rc = scsi_add_host(shost, &pdev->dev);
>>          if (rc)
>>                  goto err_out_ha;
>>
>
> As the probe function matches against the "hisilicon,sas-controller-v1"
> compatible string and contains mostly code that is specific to v1, I
> think it would be cleaner to move that to the hisi_sas_v1_hw.c as well
> and make the functions above static but make the common functions
> called here (hisi_sas_init_add etc) global.
>
> That would also include the hisi_sas_driver structure.
>
> 	Arnd
>
> .
>
Hello,

Just to be clear, are you saying that you would prefer hisi_sas_probe() 
and struct hisi_sas_driver to be relocated to hisi_sas_v1_hw.c?

I wanted to keep hisi_sas_v1_hw.c containing only code which accesses HW.

I could consoldate the calls of hw_init_v1_hw(), interrupt_init_v1_hw(), 
interrupt_openall_v1_hw(), and phys_init_v1_hw() to a single function hw 
init function call. Then most of the code in the probe function will not 
be specific to v1.

Regards,
John

Re: [PATCH 12/25] scsi: hisi_sas: add v1 HW initialisation code

[John Garry]

On 12/10/2015 19:46, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:24 John Garry wrote:
>> @@ -387,6 +392,21 @@ static int hisi_sas_probe(struct platform_device *pdev)
>>          }
>>
>>          hisi_sas_init_add(hisi_hba);
>> +
>> +       rc = hw_init_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       rc = interrupt_init_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       rc = interrupt_openall_v1_hw(hisi_hba);
>> +       if (rc)
>> +               goto err_out_ha;
>> +
>> +       phys_init_v1_hw(hisi_hba);
>> +
>>          rc = scsi_add_host(shost, &pdev->dev);
>>          if (rc)
>>                  goto err_out_ha;
>>
>
> As the probe function matches against the "hisilicon,sas-controller-v1"
> compatible string and contains mostly code that is specific to v1, I
> think it would be cleaner to move that to the hisi_sas_v1_hw.c as well
> and make the functions above static but make the common functions
> called here (hisi_sas_init_add etc) global.
>
> That would also include the hisi_sas_driver structure.
>
> 	Arnd
>
> .
>
Hello,

Just to be clear, are you saying that you would prefer hisi_sas_probe() 
and struct hisi_sas_driver to be relocated to hisi_sas_v1_hw.c?

I wanted to keep hisi_sas_v1_hw.c containing only code which accesses HW.

I could consoldate the calls of hw_init_v1_hw(), interrupt_init_v1_hw(), 
interrupt_openall_v1_hw(), and phys_init_v1_hw() to a single function hw 
init function call. Then most of the code in the probe function will not 
be specific to v1.

Regards,
John

Re: [PATCH 12/25] scsi: hisi_sas: add v1 HW initialisation code

[Arnd Bergmann]

On Tuesday 13 October 2015 13:44:26 John Garry wrote:
> Hello,
> 
> Just to be clear, are you saying that you would prefer hisi_sas_probe() 
> and struct hisi_sas_driver to be relocated to hisi_sas_v1_hw.c?

Correct.

> I wanted to keep hisi_sas_v1_hw.c containing only code which accesses HW.
> 
> I could consoldate the calls of hw_init_v1_hw(), interrupt_init_v1_hw(), 
> interrupt_openall_v1_hw(), and phys_init_v1_hw() to a single function hw 
> init function call. Then most of the code in the probe function will not 
> be specific to v1.

This is more about correct layering of the code. Generally we want the
more specific modules on top to call into the more general code in
the bottom of the stack. Shared code should know as little as possible
about the specific implementations it is shared with.

	Arnd

Re: [PATCH 07/25] scsi: hisi_sas: add ioremap for device HW

[zhangfei]

On 10/13/2015 08:20 PM, Arnd Bergmann wrote:
> On Tuesday 13 October 2015 17:47:02 zhangfei wrote:
>> On 10/12/2015 11:21 PM, Arnd Bergmann wrote:
>>> On Monday 12 October 2015 23:20:19 John Garry wrote:
>>>> +int hisi_sas_ioremap(struct hisi_hba *hisi_hba)
>>>> +{
>>>> +       struct platform_device *pdev = hisi_hba->pdev;
>>>> +       struct device *dev = &pdev->dev;
>>>> +       struct resource *res;
>>>> +
>>>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> +       hisi_hba->regs = devm_ioremap(dev,
>>>> +                                     res->start,
>>>> +                                     resource_size(res));
>>>> +       if (!hisi_hba->regs)
>>>> +               return -ENOMEM;
>>>> +
>>>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>>> +       hisi_hba->ctrl_regs = devm_ioremap(dev,
>>>> +                                          res->start,
>>>> +                                          resource_size(res));
>>>> +       if (!hisi_hba->ctrl_regs)
>>>> +               return -ENOMEM;
>>>> +
>>>> +       return 0;
>>>> +}
>>>>
>>>>    static const struct of_device_id sas_of_match[] = {
>>>>
>>>
>>> Better use devm_ioremap_resource() here, which registers the resource so they
>>> are checked for conflicts and listed in /proc/iomem.
>>>
>>
>> Yes, hisi_hba->regs can use devm_ioremap_resource.
>>
>> However ctrl_regs have to use devm_ioremap, since the address are
>> sharing among different nodes, unfortunately, and devm_ioremap_resource
>> will fail.
>
> This sounds like it should be fixed in the DT binding then, to ensure
> that the ranges don't overlap.
>
> Mapping the same register region multiple times is generally considered
> a bad idea because the drivers that map them often don't have global
> locks that serialize the access, so it's better to have code in place
> that ensures that they are distinct.
>
> What is the purpose of the ctrl_regs region, and why is it shared
> across multiple devices?
>
> Are all users of these registers in the same driver?
>

We are considering using syscon for ctrl_regs.

Thanks Arnd.

Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[John Garry]

On 13/10/2015 07:12, Hannes Reinecke wrote:
> On 10/12/2015 05:20 PM, John Garry wrote:
>> This SAS ID is chosen as Huawei IEEE id: 001882
>>
>> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>> ---
>>   drivers/scsi/hisi_sas/hisi_sas_init.c | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
>> index 44fc524..c295c39 100644
>> --- a/drivers/scsi/hisi_sas/hisi_sas_init.c
>> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
>> @@ -283,6 +283,19 @@ err_out:
>>   	return NULL;
>>   }
>>
>> +static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
>> +{
>> +	u8 i;
>> +
>> +	/* Huawei IEEE id (001882) */
>> +	for (i = 0; i < hisi_hba->n_phy; i++)
>> +		hisi_hba->phy[i].dev_sas_addr =
>> +			cpu_to_be64(0x5001882016072015ULL);
>> +
> Ouch. Each phy has the same SAS address?
> For all boards? Ever?
>
> Not sure if that's a good idea, nor even valid.
> It'll confuse the hell out of any SAS array.
>
> Please provide a means of having individual SAS addresses for each HBA.
>
> Cheers,
>
> Hannes
>
Hello,

Are you saying we should be getting the SAS address from fw with 
sas_request_addr() or the like?

Marvell solution seems to hardcode it.

thanks,
John

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Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[Hannes Reinecke]

On 10/13/2015 07:14 PM, John Garry wrote:
> On 13/10/2015 07:12, Hannes Reinecke wrote:
>> On 10/12/2015 05:20 PM, John Garry wrote:
>>> This SAS ID is chosen as Huawei IEEE id: 001882
>>>
>>> Signed-off-by: John Garry <john.garry@huawei.com>
>>> ---
>>>   drivers/scsi/hisi_sas/hisi_sas_init.c | 15 +++++++++++++++
>>>   1 file changed, 15 insertions(+)
>>>
>>> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> index 44fc524..c295c39 100644
>>> --- a/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> @@ -283,6 +283,19 @@ err_out:
>>>       return NULL;
>>>   }
>>>
>>> +static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
>>> +{
>>> +    u8 i;
>>> +
>>> +    /* Huawei IEEE id (001882) */
>>> +    for (i = 0; i < hisi_hba->n_phy; i++)
>>> +        hisi_hba->phy[i].dev_sas_addr =
>>> +            cpu_to_be64(0x5001882016072015ULL);
>>> +
>> Ouch. Each phy has the same SAS address?
>> For all boards? Ever?
>>
>> Not sure if that's a good idea, nor even valid.
>> It'll confuse the hell out of any SAS array.
>>
>> Please provide a means of having individual SAS addresses for each
>> HBA.
>>
>> Cheers,
>>
>> Hannes
>>
> Hello,
> 
> Are you saying we should be getting the SAS address from fw with
> sas_request_addr() or the like?
> 
> Marvell solution seems to hardcode it.
> 
Doesn't make it any better, nor even valid.

Problem is that using a hardcoded SAS address makes it impossible
do any resource allocation on a SAS target array.
The SAS target array is allocating / mapping the LUNs based on the
SAS address, so if HBAs from different machines coming in with the
same SAS address the SAS array will assume that all ports belong to
the same machine, thus allowing access to all of them.

And don't try to _ever_ connect these HBAs to a SAS switch; that
will be even more confused.

So please, if you have a chance _DO_ get the SAS address from fw.
If the firmware doesn't provide it you really should get in touch
with the firmware team to get you one.

To clarify the situation the SAS spec states:

  Device names are worldwide unique names for devices within a
  transport protocol (see SAM-3).

and:
  The VENDOR - SPECIFIC IDENTIFIER contains a 36-bit numeric value
  that is uniquely assigned by the organization associated with the
  company identifier in the IEEE COMPANY ID field.

So as you are using the Huawei Vendor ID Huawei as a company needs
to ensure uniqueness of the vendor-specific identifier (ie the last
36 bits of the SAS address). Which the above patch most patently
fails to address.

Cheers,

Hannes
-- 
Dr. Hannes Reinecke		               zSeries & Storage
hare@suse.de			               +49 911 74053 688
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
HRB 21284 (AG Nürnberg)
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Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[John Garry]

On 14/10/2015 09:40, Hannes Reinecke wrote:
> On 10/13/2015 07:14 PM, John Garry wrote:
>> On 13/10/2015 07:12, Hannes Reinecke wrote:
>>> On 10/12/2015 05:20 PM, John Garry wrote:
>>>> This SAS ID is chosen as Huawei IEEE id: 001882
>>>>
>>>> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>>>> ---
>>>>    drivers/scsi/hisi_sas/hisi_sas_init.c | 15 +++++++++++++++
>>>>    1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c
>>>> b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>>> index 44fc524..c295c39 100644
>>>> --- a/drivers/scsi/hisi_sas/hisi_sas_init.c
>>>> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>>> @@ -283,6 +283,19 @@ err_out:
>>>>        return NULL;
>>>>    }
>>>>
>>>> +static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
>>>> +{
>>>> +    u8 i;
>>>> +
>>>> +    /* Huawei IEEE id (001882) */
>>>> +    for (i = 0; i < hisi_hba->n_phy; i++)
>>>> +        hisi_hba->phy[i].dev_sas_addr =
>>>> +            cpu_to_be64(0x5001882016072015ULL);
>>>> +
>>> Ouch. Each phy has the same SAS address?
>>> For all boards? Ever?
>>>
>>> Not sure if that's a good idea, nor even valid.
>>> It'll confuse the hell out of any SAS array.
>>>
>>> Please provide a means of having individual SAS addresses for each
>>> HBA.
>>>
>>> Cheers,
>>>
>>> Hannes
>>>
>> Hello,
>>
>> Are you saying we should be getting the SAS address from fw with
>> sas_request_addr() or the like?
>>
>> Marvell solution seems to hardcode it.
>>
> Doesn't make it any better, nor even valid.
>
> Problem is that using a hardcoded SAS address makes it impossible
> do any resource allocation on a SAS target array.
> The SAS target array is allocating / mapping the LUNs based on the
> SAS address, so if HBAs from different machines coming in with the
> same SAS address the SAS array will assume that all ports belong to
> the same machine, thus allowing access to all of them.
>
> And don't try to _ever_ connect these HBAs to a SAS switch; that
> will be even more confused.
>
> So please, if you have a chance _DO_ get the SAS address from fw.
> If the firmware doesn't provide it you really should get in touch
> with the firmware team to get you one.
>
> To clarify the situation the SAS spec states:
>
>    Device names are worldwide unique names for devices within a
>    transport protocol (see SAM-3).
>
> and:
>    The VENDOR - SPECIFIC IDENTIFIER contains a 36-bit numeric value
>    that is uniquely assigned by the organization associated with the
>    company identifier in the IEEE COMPANY ID field.
>
> So as you are using the Huawei Vendor ID Huawei as a company needs
> to ensure uniqueness of the vendor-specific identifier (ie the last
> 36 bits of the SAS address). Which the above patch most patently
> fails to address.
>
> Cheers,
>
> Hannes
>
Hi,

OK, we can look at adding the ability to read the SAS HBA address from a 
FW image or EFI variables.

Thanks,
John

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Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[Arnd Bergmann]

On Wednesday 14 October 2015 16:05:21 John Garry wrote:
> 
> OK, we can look at adding the ability to read the SAS HBA address from a 
> FW image or EFI variables.
> 

The easiest way is usually to have a DT property that gets updated
by the firmware.

	Arnd

Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[zhangfei]

On 10/14/2015 11:18 PM, Arnd Bergmann wrote:
> On Wednesday 14 October 2015 16:05:21 John Garry wrote:
>>
>> OK, we can look at adding the ability to read the SAS HBA address from a
>> FW image or EFI variables.
>>
>
> The easiest way is usually to have a DT property that gets updated
> by the firmware.
>

Yes
In net subsystem, there is mac-address.

In dts, we set default mac-address, which will be modified by 
boot-loader, if all 0 random address will be used.
mac-address = [00 00 00 00 00 00];

In driver, mac-address can be get via of_get_mac_address.

Can we use the similar method here?

Thanks

Re: [PATCH 09/25] scsi: hisi_sas: add phy SAS ADDR initialization

[Arnd Bergmann]

On Thursday 15 October 2015 11:36:53 zhangfei wrote:
> On 10/14/2015 11:18 PM, Arnd Bergmann wrote:
> > On Wednesday 14 October 2015 16:05:21 John Garry wrote:
> >>
> >> OK, we can look at adding the ability to read the SAS HBA address from a
> >> FW image or EFI variables.
> >>
> >
> > The easiest way is usually to have a DT property that gets updated
> > by the firmware.
> >
> 
> Yes
> In net subsystem, there is mac-address.
> 
> In dts, we set default mac-address, which will be modified by 
> boot-loader, if all 0 random address will be used.
> mac-address = [00 00 00 00 00 00];
> 
> In driver, mac-address can be get via of_get_mac_address.
> 
> Can we use the similar method here?

Good idea, I think this is the best way.

	Arnd

Re: [PATCH 03/25] scsi: hisi_sas: add initial bare driver

[Xinwei Kong]

On 2015/10/12 23:20, John Garry wrote:
> This patch adds the initial bare driver for the HiSilicon
> SAS HBA. The driver includes no HW interaction, but only
> the changes to build and load the driver module.
> 
> The HBA is a platform device.
> 
> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> ---
>  drivers/scsi/Kconfig                  |  1 +
>  drivers/scsi/Makefile                 |  1 +
>  drivers/scsi/hisi_sas/Kconfig         |  5 +++
>  drivers/scsi/hisi_sas/Makefile        |  2 ++
>  drivers/scsi/hisi_sas/hisi_sas.h      | 24 +++++++++++++++
>  drivers/scsi/hisi_sas/hisi_sas_init.c | 58 +++++++++++++++++++++++++++++++++++
>  6 files changed, 91 insertions(+)
>  create mode 100644 drivers/scsi/hisi_sas/Kconfig
>  create mode 100644 drivers/scsi/hisi_sas/Makefile
>  create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
>  create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
> 
> diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
> index 95f7a76..5c345f9 100644
> --- a/drivers/scsi/Kconfig
> +++ b/drivers/scsi/Kconfig
> @@ -1774,5 +1774,6 @@ source "drivers/scsi/pcmcia/Kconfig"
>  source "drivers/scsi/device_handler/Kconfig"
>  
>  source "drivers/scsi/osd/Kconfig"
> +source "drivers/scsi/hisi_sas/Kconfig"
>  
>  endmenu
> diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
> index 1a8c9b5..03c30de 100644
> --- a/drivers/scsi/Makefile
> +++ b/drivers/scsi/Makefile
> @@ -158,6 +158,7 @@ obj-$(CONFIG_CHR_DEV_SCH)	+= ch.o
>  obj-$(CONFIG_SCSI_ENCLOSURE)	+= ses.o
>  
>  obj-$(CONFIG_SCSI_OSD_INITIATOR) += osd/
> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas/
>  
>  # This goes last, so that "real" scsi devices probe earlier
>  obj-$(CONFIG_SCSI_DEBUG)	+= scsi_debug.o
> diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
> new file mode 100644
> index 0000000..a7f47a2
> --- /dev/null
> +++ b/drivers/scsi/hisi_sas/Kconfig
> @@ -0,0 +1,5 @@
> +config SCSI_HISI_SAS
> +	tristate "HiSilicon SAS"
> +	select SCSI_SAS_LIBSAS
> +	help
> +		This driver supports HiSilicon's SAS HBA
> diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
> new file mode 100644
> index 0000000..63c3c4d
> --- /dev/null
> +++ b/drivers/scsi/hisi_sas/Makefile
> @@ -0,0 +1,2 @@
> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
> +hisi_sas-y+= hisi_sas_init.o
> diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
> new file mode 100644
> index 0000000..50204a2
> --- /dev/null
> +++ b/drivers/scsi/hisi_sas/hisi_sas.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (c) 2015 Linaro Ltd.
> + * Copyright (c) 2015 Hisilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#ifndef _HISI_SAS_H_
> +#define _HISI_SAS_H_
> +
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <scsi/libsas.h>
> +
why place some "include" head in .h file rather than .c file?
> +#define DRV_NAME "hisi_sas"
> +#define DRV_VERSION "v1.0"
> +
> +#endif
> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
> new file mode 100644
> index 0000000..dd83430
> --- /dev/null
> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright (c) 2015 Linaro Ltd.
> + * Copyright (c) 2015 Hisilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include "hisi_sas.h"
> +
> +static const struct of_device_id sas_of_match[] = {
> +	{ .compatible = "hisilicon,sas-controller-v1",},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sas_of_match);
> +static int hisi_sas_probe(struct platform_device *pdev)
> +{
> +
> +	return 0;
> +}
> +
> +static int hisi_sas_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}
> +
> +static struct platform_driver hisi_sas_driver = {
> +	.probe = hisi_sas_probe,
> +	.remove = hisi_sas_remove,
> +	.driver = {
> +		.name = DRV_NAME,
> +		.of_match_table = sas_of_match,
> +	},
> +};
> +
> +static __init int hisi_sas_init(void)
> +{
> +	pr_info("hisi_sas: driver version %s\n", DRV_VERSION);
> +
> +	return platform_driver_register(&hisi_sas_driver);
> +}
> +
> +static __exit void hisi_sas_exit(void)
> +{
> +	platform_driver_unregister(&hisi_sas_driver);
> +}
> +
> +module_init(hisi_sas_init);
> +module_exit(hisi_sas_exit);
> +
> +MODULE_VERSION(DRV_VERSION);
> +MODULE_LICENSE("GPL");
V2
> +MODULE_AUTHOR("John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>");
> +MODULE_DESCRIPTION("HISILICON SAS controller driver");
> +MODULE_ALIAS("platform:" DRV_NAME);
> 

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Re: [PATCH 03/25] scsi: hisi_sas: add initial bare driver

[John Garry]

On 15/10/2015 09:49, Xinwei Kong wrote:
>
>
> On 2015/10/12 23:20, John Garry wrote:
>> This patch adds the initial bare driver for the HiSilicon
>> SAS HBA. The driver includes no HW interaction, but only
>> the changes to build and load the driver module.
>>
>> The HBA is a platform device.
>>
>> Signed-off-by: John Garry <john.garry@huawei.com>
>> ---
>>   drivers/scsi/Kconfig                  |  1 +
>>   drivers/scsi/Makefile                 |  1 +
>>   drivers/scsi/hisi_sas/Kconfig         |  5 +++
>>   drivers/scsi/hisi_sas/Makefile        |  2 ++
>>   drivers/scsi/hisi_sas/hisi_sas.h      | 24 +++++++++++++++
>>   drivers/scsi/hisi_sas/hisi_sas_init.c | 58 +++++++++++++++++++++++++++++++++++
>>   6 files changed, 91 insertions(+)
>>   create mode 100644 drivers/scsi/hisi_sas/Kconfig
>>   create mode 100644 drivers/scsi/hisi_sas/Makefile
>>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
>>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
>>
>> diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
>> index 95f7a76..5c345f9 100644
>> --- a/drivers/scsi/Kconfig
>> +++ b/drivers/scsi/Kconfig
>> @@ -1774,5 +1774,6 @@ source "drivers/scsi/pcmcia/Kconfig"
>>   source "drivers/scsi/device_handler/Kconfig"
>>
>>   source "drivers/scsi/osd/Kconfig"
>> +source "drivers/scsi/hisi_sas/Kconfig"
>>
>>   endmenu
>> diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
>> index 1a8c9b5..03c30de 100644
>> --- a/drivers/scsi/Makefile
>> +++ b/drivers/scsi/Makefile
>> @@ -158,6 +158,7 @@ obj-$(CONFIG_CHR_DEV_SCH)	+= ch.o
>>   obj-$(CONFIG_SCSI_ENCLOSURE)	+= ses.o
>>
>>   obj-$(CONFIG_SCSI_OSD_INITIATOR) += osd/
>> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas/
>>
>>   # This goes last, so that "real" scsi devices probe earlier
>>   obj-$(CONFIG_SCSI_DEBUG)	+= scsi_debug.o
>> diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
>> new file mode 100644
>> index 0000000..a7f47a2
>> --- /dev/null
>> +++ b/drivers/scsi/hisi_sas/Kconfig
>> @@ -0,0 +1,5 @@
>> +config SCSI_HISI_SAS
>> +	tristate "HiSilicon SAS"
>> +	select SCSI_SAS_LIBSAS
>> +	help
>> +		This driver supports HiSilicon's SAS HBA
>> diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
>> new file mode 100644
>> index 0000000..63c3c4d
>> --- /dev/null
>> +++ b/drivers/scsi/hisi_sas/Makefile
>> @@ -0,0 +1,2 @@
>> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
>> +hisi_sas-y+= hisi_sas_init.o
>> diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
>> new file mode 100644
>> index 0000000..50204a2
>> --- /dev/null
>> +++ b/drivers/scsi/hisi_sas/hisi_sas.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (c) 2015 Linaro Ltd.
>> + * Copyright (c) 2015 Hisilicon Limited.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + */
>> +
>> +#ifndef _HISI_SAS_H_
>> +#define _HISI_SAS_H_
>> +
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/platform_device.h>
>> +#include <scsi/libsas.h>
>> +
> why place some "include" head in .h file rather than .c file?
This is private header within the module, which:
- makes the code more concise
- relocate functions within c files is cleaner
- easier to change the kernel APIs we use in the module

>> +#define DRV_NAME "hisi_sas"
>> +#define DRV_VERSION "v1.0"
>> +
>> +#endif
>> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c b/drivers/scsi/hisi_sas/hisi_sas_init.c
>> new file mode 100644
>> index 0000000..dd83430
>> --- /dev/null
>> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
>> @@ -0,0 +1,58 @@
>> +/*
>> + * Copyright (c) 2015 Linaro Ltd.
>> + * Copyright (c) 2015 Hisilicon Limited.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + */
>> +
>> +#include "hisi_sas.h"
>> +
>> +static const struct of_device_id sas_of_match[] = {
>> +	{ .compatible = "hisilicon,sas-controller-v1",},
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, sas_of_match);
>> +static int hisi_sas_probe(struct platform_device *pdev)
>> +{
>> +
>> +	return 0;
>> +}
>> +
>> +static int hisi_sas_remove(struct platform_device *pdev)
>> +{
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver hisi_sas_driver = {
>> +	.probe = hisi_sas_probe,
>> +	.remove = hisi_sas_remove,
>> +	.driver = {
>> +		.name = DRV_NAME,
>> +		.of_match_table = sas_of_match,
>> +	},
>> +};
>> +
>> +static __init int hisi_sas_init(void)
>> +{
>> +	pr_info("hisi_sas: driver version %s\n", DRV_VERSION);
>> +
>> +	return platform_driver_register(&hisi_sas_driver);
>> +}
>> +
>> +static __exit void hisi_sas_exit(void)
>> +{
>> +	platform_driver_unregister(&hisi_sas_driver);
>> +}
>> +
>> +module_init(hisi_sas_init);
>> +module_exit(hisi_sas_exit);
>> +
>> +MODULE_VERSION(DRV_VERSION);
>> +MODULE_LICENSE("GPL");
> V2
Can add. We do say in the header that it is v2.

>> +MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
>> +MODULE_DESCRIPTION("HISILICON SAS controller driver");
>> +MODULE_ALIAS("platform:" DRV_NAME);
>>
>
>
> .
>

thanks,
John

Re: [PATCH 03/25] scsi: hisi_sas: add initial bare driver

[zhangfei]

On 10/15/2015 05:23 PM, John Garry wrote:
> On 15/10/2015 09:49, Xinwei Kong wrote:
>>
>>

>>> +++ b/drivers/scsi/hisi_sas/hisi_sas.h
>>> @@ -0,0 +1,24 @@
>>> +/*
>>> + * Copyright (c) 2015 Linaro Ltd.
>>> + * Copyright (c) 2015 Hisilicon Limited.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.

>>> +MODULE_VERSION(DRV_VERSION);
>>> +MODULE_LICENSE("GPL");
>> V2
> Can add. We do say in the header that it is v2.
>
No, should use MODULE_LICENSE("GPL");

include/linux/module.h

/*
  * The following license idents are currently accepted as indicating free
  * software modules
  *
  *      "GPL"                           [GNU Public License v2 or later]
  *      "GPL v2"                        [GNU Public License v2]

Thanks

Re: [PATCH 03/25] scsi: hisi_sas: add initial bare driver

[Xinwei Kong]

On 2015/10/15 17:23, John Garry wrote:
> On 15/10/2015 09:49, Xinwei Kong wrote:
>>
>>
>> On 2015/10/12 23:20, John Garry wrote:
>>> This patch adds the initial bare driver for the HiSilicon
>>> SAS HBA. The driver includes no HW interaction, but only
>>> the changes to build and load the driver module.
>>>
>>> The HBA is a platform device.
>>>
>>> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>>> ---
>>>   drivers/scsi/Kconfig                  |  1 +
>>>   drivers/scsi/Makefile                 |  1 +
>>>   drivers/scsi/hisi_sas/Kconfig         |  5 +++
>>>   drivers/scsi/hisi_sas/Makefile        |  2 ++
>>>   drivers/scsi/hisi_sas/hisi_sas.h      | 24 +++++++++++++++
>>>   drivers/scsi/hisi_sas/hisi_sas_init.c | 58 
>>> +++++++++++++++++++++++++++++++++++
>>>   6 files changed, 91 insertions(+)
>>>   create mode 100644 drivers/scsi/hisi_sas/Kconfig
>>>   create mode 100644 drivers/scsi/hisi_sas/Makefile
>>>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
>>>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
>>>
>>> diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
>>> index 95f7a76..5c345f9 100644
>>> --- a/drivers/scsi/Kconfig
>>> +++ b/drivers/scsi/Kconfig
>>> @@ -1774,5 +1774,6 @@ source "drivers/scsi/pcmcia/Kconfig"
>>>   source "drivers/scsi/device_handler/Kconfig"
>>>
>>>   source "drivers/scsi/osd/Kconfig"
>>> +source "drivers/scsi/hisi_sas/Kconfig"
>>>
>>>   endmenu
>>> diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
>>> index 1a8c9b5..03c30de 100644
>>> --- a/drivers/scsi/Makefile
>>> +++ b/drivers/scsi/Makefile
>>> @@ -158,6 +158,7 @@ obj-$(CONFIG_CHR_DEV_SCH)    += ch.o
>>>   obj-$(CONFIG_SCSI_ENCLOSURE)    += ses.o
>>>
>>>   obj-$(CONFIG_SCSI_OSD_INITIATOR) += osd/
>>> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas/
>>>
>>>   # This goes last, so that "real" scsi devices probe earlier
>>>   obj-$(CONFIG_SCSI_DEBUG)    += scsi_debug.o
>>> diff --git a/drivers/scsi/hisi_sas/Kconfig 
>>> b/drivers/scsi/hisi_sas/Kconfig
>>> new file mode 100644
>>> index 0000000..a7f47a2
>>> --- /dev/null
>>> +++ b/drivers/scsi/hisi_sas/Kconfig
>>> @@ -0,0 +1,5 @@
>>> +config SCSI_HISI_SAS
>>> +    tristate "HiSilicon SAS"
>>> +    select SCSI_SAS_LIBSAS
>>> +    help
>>> +        This driver supports HiSilicon's SAS HBA
>>> diff --git a/drivers/scsi/hisi_sas/Makefile 
>>> b/drivers/scsi/hisi_sas/Makefile
>>> new file mode 100644
>>> index 0000000..63c3c4d
>>> --- /dev/null
>>> +++ b/drivers/scsi/hisi_sas/Makefile
>>> @@ -0,0 +1,2 @@
>>> +obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas.o
>>> +hisi_sas-y+= hisi_sas_init.o
>>> diff --git a/drivers/scsi/hisi_sas/hisi_sas.h 
>>> b/drivers/scsi/hisi_sas/hisi_sas.h
>>> new file mode 100644
>>> index 0000000..50204a2
>>> --- /dev/null
>>> +++ b/drivers/scsi/hisi_sas/hisi_sas.h
>>> @@ -0,0 +1,24 @@
>>> +/*
>>> + * Copyright (c) 2015 Linaro Ltd.
>>> + * Copyright (c) 2015 Hisilicon Limited.
>>> + *
>>> + * This program is free software; you can redistribute it and/or 
>>> modify
>>> + * it under the terms of the GNU General Public License as 
>>> published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + */
>>> +
>>> +#ifndef _HISI_SAS_H_
>>> +#define _HISI_SAS_H_
>>> +
>>> +#include <linux/module.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_irq.h>
>>> +#include <linux/platform_device.h>
>>> +#include <scsi/libsas.h>
>>> +
>> why place some "include" head in .h file rather than .c file?
> This is private header within the module, which:
> - makes the code more concise
> - relocate functions within c files is cleaner
> - easier to change the kernel APIs we use in the module
>
this  .h file  wil be included by  "hisi_sas_main.c"   and 
"hisi_sas_init.c" file.
if all "include" term can't be used in both  ".c" file.  When you build 
this code,
it will add  some burden work.

Thank you
xinwei
>>> +#define DRV_NAME "hisi_sas"
>>> +#define DRV_VERSION "v1.0"
>>> +
>>> +#endif
>>> diff --git a/drivers/scsi/hisi_sas/hisi_sas_init.c 
>>> b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> new file mode 100644
>>> index 0000000..dd83430
>>> --- /dev/null
>>> +++ b/drivers/scsi/hisi_sas/hisi_sas_init.c
>>> @@ -0,0 +1,58 @@
>>> +/*
>>> + * Copyright (c) 2015 Linaro Ltd.
>>> + * Copyright (c) 2015 Hisilicon Limited.
>>> + *
>>> + * This program is free software; you can redistribute it and/or 
>>> modify
>>> + * it under the terms of the GNU General Public License as 
>>> published by
>>> + * the Free Software Foundation; either version 2 of the License, or
>>> + * (at your option) any later version.
>>> + *
>>> + */
>>> +
>>> +#include "hisi_sas.h"
>>> +
>>> +static const struct of_device_id sas_of_match[] = {
>>> +    { .compatible = "hisilicon,sas-controller-v1",},
>>> +    {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, sas_of_match);
>>> +static int hisi_sas_probe(struct platform_device *pdev)
>>> +{
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int hisi_sas_remove(struct platform_device *pdev)
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +static struct platform_driver hisi_sas_driver = {
>>> +    .probe = hisi_sas_probe,
>>> +    .remove = hisi_sas_remove,
>>> +    .driver = {
>>> +        .name = DRV_NAME,
>>> +        .of_match_table = sas_of_match,
>>> +    },
>>> +};
>>> +
>>> +static __init int hisi_sas_init(void)
>>> +{
>>> +    pr_info("hisi_sas: driver version %s\n", DRV_VERSION);
>>> +
>>> +    return platform_driver_register(&hisi_sas_driver);
>>> +}
>>> +
>>> +static __exit void hisi_sas_exit(void)
>>> +{
>>> +    platform_driver_unregister(&hisi_sas_driver);
>>> +}
>>> +
>>> +module_init(hisi_sas_init);
>>> +module_exit(hisi_sas_exit);
>>> +
>>> +MODULE_VERSION(DRV_VERSION);
>>> +MODULE_LICENSE("GPL");
>> V2
> Can add. We do say in the header that it is v2.
>
>>> +MODULE_AUTHOR("John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>");
>>> +MODULE_DESCRIPTION("HISILICON SAS controller driver");
>>> +MODULE_ALIAS("platform:" DRV_NAME);
>>>
>>
>>
>> .
>>
>
> thanks,
> John
>
>
>
> .
>


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Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Arnd Bergmann]

On Monday 12 October 2015 23:20:25 John Garry wrote:
> @@ -804,6 +818,16 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
>                 phy->identify.target_port_protocols =
>                         SAS_PROTOCOL_SMP;
>  
> +       wq = kmalloc(sizeof(*wq), GFP_ATOMIC);
> +       if (!wq)
> +               goto end;
> +
> +       wq->event = PHYUP;
> +       wq->hisi_hba = hisi_hba;
> +       wq->phy_no = phy_no;
> +
> +       INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
> +       queue_work(hisi_hba->wq, &wq->work_struct);
>  
>  end:
>         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
> 

While rereading some other parts of the code, I stumbled over this piece.
You should generally not allocate work structs dynamically. Why not embed
the work struct inside of the phy structure and then just queue that?

	Arnd

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

On 16/10/2015 13:55, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:25 John Garry wrote:
>> @@ -804,6 +818,16 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
>>                  phy->identify.target_port_protocols =
>>                          SAS_PROTOCOL_SMP;
>>
>> +       wq = kmalloc(sizeof(*wq), GFP_ATOMIC);
>> +       if (!wq)
>> +               goto end;
>> +
>> +       wq->event = PHYUP;
>> +       wq->hisi_hba = hisi_hba;
>> +       wq->phy_no = phy_no;
>> +
>> +       INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
>> +       queue_work(hisi_hba->wq, &wq->work_struct);
>>
>>   end:
>>          hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
>>
>
> While rereading some other parts of the code, I stumbled over this piece.
> You should generally not allocate work structs dynamically. Why not embed
> the work struct inside of the phy structure and then just queue that?
>
> 	Arnd
>
> .
>

It could be considered.

A potential issue I see is with hisi_sas_control_phy() for 
PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes 
the reset in the queue work. When we re-enable the phy for the reset, 
the phyup irq will want to use the same hisi_sas_wq struct which may be 
in use.

hisi_sas_control_phy() is added in 23/35.

John

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

On 16/10/2015 13:55, Arnd Bergmann wrote:
> On Monday 12 October 2015 23:20:25 John Garry wrote:
>> @@ -804,6 +818,16 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
>>                  phy->identify.target_port_protocols =
>>                          SAS_PROTOCOL_SMP;
>>
>> +       wq = kmalloc(sizeof(*wq), GFP_ATOMIC);
>> +       if (!wq)
>> +               goto end;
>> +
>> +       wq->event = PHYUP;
>> +       wq->hisi_hba = hisi_hba;
>> +       wq->phy_no = phy_no;
>> +
>> +       INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
>> +       queue_work(hisi_hba->wq, &wq->work_struct);
>>
>>   end:
>>          hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
>>
>
> While rereading some other parts of the code, I stumbled over this piece.
> You should generally not allocate work structs dynamically. Why not embed
> the work struct inside of the phy structure and then just queue that?
>
> 	Arnd
>
> .
>

It could be considered.

A potential issue I see is with hisi_sas_control_phy() for 
PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes 
the reset in the queue work. When we re-enable the phy for the reset, 
the phyup irq will want to use the same hisi_sas_wq struct which may be 
in use.

hisi_sas_control_phy() is added in 23/35.

John

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Arnd Bergmann]

On Friday 16 October 2015 14:29:55 John Garry wrote:
> 
> It could be considered.
> 
> A potential issue I see is with hisi_sas_control_phy() for 
> PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes 
> the reset in the queue work. When we re-enable the phy for the reset, 
> the phyup irq will want to use the same hisi_sas_wq struct which may be 
> in use.
> 
> hisi_sas_control_phy() is added in 23/35.

I'd have to review more closely, but I think that's fine, as this
is how most work queues are used: you can queue the same function
multiple times, and it's guaranteed to run at least once after
the last queue, so if you queue it while it's already running,
it will be called again, otherwise it won't.

	Arnd

Re: [PATCH 02/25] devicetree: bindings: scsi: HiSi SAS

[Rob Herring]

On Mon, Oct 12, 2015 at 10:20 AM, John Garry <john.garry@huawei.com> wrote:
> Add devicetree bindings for HiSilicon SAS driver.

In the future, please use get_maintainers.pl.

> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
>  .../devicetree/bindings/scsi/hisilicon-sas.txt     | 63 ++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>
> diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
> new file mode 100644
> index 0000000..472c022
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
> @@ -0,0 +1,63 @@
> +* HiSilison SAS controller
> +
> +The HiSilicon SAS controller supports SAS/SATA.
> +
> +Main node required properties:
> +  - compatible : value should be as follows:
> +       (a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
> +
> +  - controller-id : identifier for controller in the SoC

We don't do indexes in DT (mostly). Why do you need this?

> +  - reg : Address and length of the register sets for the device
> +   - SAS controller registers
> +   - SAS controller control registers
> +
> +  - reset-reg : offset to reset, status, and clock registers in control registers

Within the above register range? If so and if this varies, then that
implies there is more than 1 version of IP. In that case you should
have a more specific compatible string.

How long is this property I count 3 cells here, but the example has 5.
Define what each cell corresponds to specifically.

> +
> +  - queue-count : number of delivery and completion queues in the controller
> +
> +  - phy-count : number of phys accessible by the controller
> +
> +  - interrupts : Interrupts for phys, completion queues, and fatal
> +                interrupts:
> +                 - Each phy has 3 interrupt sources:
> +                       - broadcast
> +                       - phyup
> +                       - abnormal
> +                 - Each completion queue has 1 interrupt source
> +                 - Each controller has 2 fatal interrupt sources:
> +                       - ECC
> +                       - AXI bus
> +
> +Example:
> +       sas0: sas@c1000000 {
> +               compatible = "hisilicon,sas-controller-v1";
> +               controller-id = <0>;
> +               reg = <0x0 0xc1000000 0x0 0x10000>,
> +                       <0x0 0xc0000000 0x0 0x10000>;
> +               reset-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
> +               queue-count = <32>;
> +               phy-count = <8>;
> +               #interrupt-cells = <2>;
> +               dma-coherent;
> +               interrupt-parent = <&mbigen_dsa>;
> +               interrupts = <259 4>, <263 4>,<264 4>,/* phy irq(0~79) */
> +                               <269 4>,<273 4>,<274 4>,/* phy irq(0~79) */
> +                               <279 4>,<283 4>,<284 4>,/* phy irq(0~79) */
> +                               <289 4>,<293 4>,<294 4>,/* phy irq(0~79) */
> +                               <299 4>,<303 4>,<304 4>,/* phy irq(0~79) */
> +                               <309 4>,<313 4>,<314 4>,/* phy irq(0~79) */
> +                               <319 4>,<323 4>,<324 4>,/* phy irq(0~79) */
> +                               <329 4>,<333 4>,<334 4>,/* phy irq(0~79) */
> +                               <336 1>,<337 1>,<338 1>,<339 1>,<340 1>,
> +                               <341 1>,<342 1>,<343 1>,/* cq irq (80~111) */
> +                               <344 1>,<345 1>,<346 1>,<347 1>,<348 1>,
> +                               <349 1>,<350 1>,<351 1>,/* cq irq (80~111) */
> +                               <352 1>,<353 1>,<354 1>,<355 1>,<356 1>,
> +                               <357 1>,<358 1>,<359 1>,/* cq irq (80~111) */
> +                               <360 1>,<361 1>,<362 1>,<363 1>,<364 1>,
> +                               <365 1>,<366 1>,<367 1>,/* cq irq (80~111) */
> +                               <376 4>,/* chip fatal error irq(120) */
> +                               <381 4>;/* chip fatal error irq(125) */
> +               status = "okay";
> +       };
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 00/25] HiSilicon SAS driver

[John Garry]

Hi James,

Could we please get a review for our driver? We have got some good input 
on changes we need to make, and we will produce another patchset in the 
coming days. However it would good to get a subsystem maintainer 
review/acknowledgement to progress our upstreaming.

Thanks in advance,
John

On 12/10/2015 16:20, John Garry wrote:
> This is the driver patchset for the HiSilicon SAS driver. The driver
> is a platform driver.
>
> The driver will support multiple revisions of HW. Currently only "v1"
> HW is supported.
>
> The driver uses libsas framework within the SCSI framework.
>
> The v1 HW supports SSP and SMP, but not STP/SATA.
>
>
> John Garry (25):
>    [SCSI] sas: centralise ssp frame information units
>    devicetree: bindings: scsi: HiSi SAS
>    scsi: hisi_sas: add initial bare driver
>    scsi: hisi_sas: add scsi host registration
>    scsi: hisi_sas: allocate memories and create pools
>    scsi: hisi_sas: add slot init code
>    scsi: hisi_sas: add ioremap for device HW
>    scsi: hisi_sas: add cq structure initialization
>    scsi: hisi_sas: add phy SAS ADDR initialization
>    scsi: hisi_sas: add misc HBA initialization
>    scsi: hisi_sas: add v1 hardware register definitions
>    scsi: hisi_sas: add v1 HW initialisation code
>    scsi: hisi_sas: add path from phyup irq to SAS framework
>    scsi: hisi_sas: add ssp command function
>    scsi: hisi_sas: add cq interrupt handler
>    scsi: hisi_sas: add dev_found and port_formed
>    scsi: hisi_sas: add abnormal irq handler
>    scsi: hisi_sas: add dev_gone and port_deformed
>    scsi: hisi_sas: add bcast interrupt handler
>    scsi: hisi_sas: add smp protocol support
>    scsi: hisi_sas: add scan finished and start
>    scsi: hisi_sas: add tmf methods
>    scsi: hisi_sas: add control phy handler
>    scsi: hisi_sas: add fatal irq handler
>    MAINTAINERS: add maintainer for HiSi SAS driver
>
>   .../devicetree/bindings/scsi/hisilicon-sas.txt     |   63 +
>   MAINTAINERS                                        |    7 +
>   drivers/scsi/Kconfig                               |    1 +
>   drivers/scsi/Makefile                              |    1 +
>   drivers/scsi/aic94xx/aic94xx_sas.h                 |   49 +-
>   drivers/scsi/hisi_sas/Kconfig                      |    5 +
>   drivers/scsi/hisi_sas/Makefile                     |    2 +
>   drivers/scsi/hisi_sas/hisi_sas.h                   |  406 +++++
>   drivers/scsi/hisi_sas/hisi_sas_init.c              |  489 ++++++
>   drivers/scsi/hisi_sas/hisi_sas_main.c              | 1115 ++++++++++++
>   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c             | 1850 ++++++++++++++++++++
>   include/scsi/sas.h                                 |   74 +
>   12 files changed, 4019 insertions(+), 43 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>   create mode 100644 drivers/scsi/hisi_sas/Kconfig
>   create mode 100644 drivers/scsi/hisi_sas/Makefile
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_main.c
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
>

Re: [PATCH 00/25] HiSilicon SAS driver

[John Garry]

Hi James,

Could we please get a review for our driver? We have got some good input 
on changes we need to make, and we will produce another patchset in the 
coming days. However it would good to get a subsystem maintainer 
review/acknowledgement to progress our upstreaming.

Thanks in advance,
John

On 12/10/2015 16:20, John Garry wrote:
> This is the driver patchset for the HiSilicon SAS driver. The driver
> is a platform driver.
>
> The driver will support multiple revisions of HW. Currently only "v1"
> HW is supported.
>
> The driver uses libsas framework within the SCSI framework.
>
> The v1 HW supports SSP and SMP, but not STP/SATA.
>
>
> John Garry (25):
>    [SCSI] sas: centralise ssp frame information units
>    devicetree: bindings: scsi: HiSi SAS
>    scsi: hisi_sas: add initial bare driver
>    scsi: hisi_sas: add scsi host registration
>    scsi: hisi_sas: allocate memories and create pools
>    scsi: hisi_sas: add slot init code
>    scsi: hisi_sas: add ioremap for device HW
>    scsi: hisi_sas: add cq structure initialization
>    scsi: hisi_sas: add phy SAS ADDR initialization
>    scsi: hisi_sas: add misc HBA initialization
>    scsi: hisi_sas: add v1 hardware register definitions
>    scsi: hisi_sas: add v1 HW initialisation code
>    scsi: hisi_sas: add path from phyup irq to SAS framework
>    scsi: hisi_sas: add ssp command function
>    scsi: hisi_sas: add cq interrupt handler
>    scsi: hisi_sas: add dev_found and port_formed
>    scsi: hisi_sas: add abnormal irq handler
>    scsi: hisi_sas: add dev_gone and port_deformed
>    scsi: hisi_sas: add bcast interrupt handler
>    scsi: hisi_sas: add smp protocol support
>    scsi: hisi_sas: add scan finished and start
>    scsi: hisi_sas: add tmf methods
>    scsi: hisi_sas: add control phy handler
>    scsi: hisi_sas: add fatal irq handler
>    MAINTAINERS: add maintainer for HiSi SAS driver
>
>   .../devicetree/bindings/scsi/hisilicon-sas.txt     |   63 +
>   MAINTAINERS                                        |    7 +
>   drivers/scsi/Kconfig                               |    1 +
>   drivers/scsi/Makefile                              |    1 +
>   drivers/scsi/aic94xx/aic94xx_sas.h                 |   49 +-
>   drivers/scsi/hisi_sas/Kconfig                      |    5 +
>   drivers/scsi/hisi_sas/Makefile                     |    2 +
>   drivers/scsi/hisi_sas/hisi_sas.h                   |  406 +++++
>   drivers/scsi/hisi_sas/hisi_sas_init.c              |  489 ++++++
>   drivers/scsi/hisi_sas/hisi_sas_main.c              | 1115 ++++++++++++
>   drivers/scsi/hisi_sas/hisi_sas_v1_hw.c             | 1850 ++++++++++++++++++++
>   include/scsi/sas.h                                 |   74 +
>   12 files changed, 4019 insertions(+), 43 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>   create mode 100644 drivers/scsi/hisi_sas/Kconfig
>   create mode 100644 drivers/scsi/hisi_sas/Makefile
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas.h
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_init.c
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_main.c
>   create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
>


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Re: [PATCH 00/25] HiSilicon SAS driver

[Hannes Reinecke]

On 10/19/2015 10:47 AM, John Garry wrote:
> Hi James,
> 
> Could we please get a review for our driver? We have got some good
> input on changes we need to make, and we will produce another
> patchset in the coming days. However it would good to get a
> subsystem maintainer review/acknowledgement to progress our
> upstreaming.
> 
In general any change will need to have at least two reviews, of
which one should be independent (ie not affiliated with the company)
from the original submitter.

Once the reviews are done the maintainer will/should do a final
round of reviews and then include the patch in the next submission.

However, you seem to be on a good course with your driver.
Please prepare for the next round of patches and we'll be reviewing
them.

Cheers,

Hannes
-- 
Dr. Hannes Reinecke		               zSeries & Storage
hare@suse.de			               +49 911 74053 688
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH 00/25] HiSilicon SAS driver

[John Garry]

On 19/10/2015 09:55, Hannes Reinecke wrote:
> On 10/19/2015 10:47 AM, John Garry wrote:
>> Hi James,
>>
>> Could we please get a review for our driver? We have got some good
>> input on changes we need to make, and we will produce another
>> patchset in the coming days. However it would good to get a
>> subsystem maintainer review/acknowledgement to progress our
>> upstreaming.
>>
> In general any change will need to have at least two reviews, of
> which one should be independent (ie not affiliated with the company)
> from the original submitter.
>
> Once the reviews are done the maintainer will/should do a final
> round of reviews and then include the patch in the next submission.
>
> However, you seem to be on a good course with your driver.
> Please prepare for the next round of patches and we'll be reviewing
> them.
>
> Cheers,
>
> Hannes
>

OK, thanks. I just want to make sure we're on the right path.

Regards,
john

Re: [PATCH 00/25] HiSilicon SAS driver

[John Garry]

On 19/10/2015 09:55, Hannes Reinecke wrote:
> On 10/19/2015 10:47 AM, John Garry wrote:
>> Hi James,
>>
>> Could we please get a review for our driver? We have got some good
>> input on changes we need to make, and we will produce another
>> patchset in the coming days. However it would good to get a
>> subsystem maintainer review/acknowledgement to progress our
>> upstreaming.
>>
> In general any change will need to have at least two reviews, of
> which one should be independent (ie not affiliated with the company)
> from the original submitter.
>
> Once the reviews are done the maintainer will/should do a final
> round of reviews and then include the patch in the next submission.
>
> However, you seem to be on a good course with your driver.
> Please prepare for the next round of patches and we'll be reviewing
> them.
>
> Cheers,
>
> Hannes
>

OK, thanks. I just want to make sure we're on the right path.

Regards,
john

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Re: [PATCH 02/25] devicetree: bindings: scsi: HiSi SAS

[John Garry]

On 16/10/2015 14:47, Rob Herring wrote:
> On Mon, Oct 12, 2015 at 10:20 AM, John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> wrote:
>> Add devicetree bindings for HiSilicon SAS driver.
>
> In the future, please use get_maintainers.pl.
>
Will do.

>> Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>> ---
>>   .../devicetree/bindings/scsi/hisilicon-sas.txt     | 63 ++++++++++++++++++++++
>>   1 file changed, 63 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>>
>> diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>> new file mode 100644
>> index 0000000..472c022
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>> @@ -0,0 +1,63 @@
>> +* HiSilison SAS controller
>> +
>> +The HiSilicon SAS controller supports SAS/SATA.
>> +
>> +Main node required properties:
>> +  - compatible : value should be as follows:
>> +       (a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
>> +
>> +  - controller-id : identifier for controller in the SoC
>
> We don't do indexes in DT (mostly). Why do you need this?

We don't strictly require it. A soc may have multiple instances of this 
IP, so having an index is useful for memory pools/workqueue/etc name 
string associated with each instance.

>
>> +  - reg : Address and length of the register sets for the device
>> +   - SAS controller registers
>> +   - SAS controller control registers
>> +
>> +  - reset-reg : offset to reset, status, and clock registers in control registers
>
> Within the above register range? If so and if this varies, then that
> implies there is more than 1 version of IP. In that case you should
> have a more specific compatible string.
>
The registers in the second region are for syscon register offsets. See 
last note, below.

> How long is this property I count 3 cells here, but the example has 5.
> Define what each cell corresponds to specifically.
>
We will add all the cells to the decription, which are:
Reset assert, clock disable, reset status, reset de-assert, and clock 
enable.
>> +
>> +  - queue-count : number of delivery and completion queues in the controller
>> +
>> +  - phy-count : number of phys accessible by the controller
>> +
>> +  - interrupts : Interrupts for phys, completion queues, and fatal
>> +                interrupts:
>> +                 - Each phy has 3 interrupt sources:
>> +                       - broadcast
>> +                       - phyup
>> +                       - abnormal
>> +                 - Each completion queue has 1 interrupt source
>> +                 - Each controller has 2 fatal interrupt sources:
>> +                       - ECC
>> +                       - AXI bus
>> +
>> +Example:
>> +       sas0: sas@c1000000 {
>> +               compatible = "hisilicon,sas-controller-v1";
>> +               controller-id = <0>;
>> +               reg = <0x0 0xc1000000 0x0 0x10000>,
>> +                       <0x0 0xc0000000 0x0 0x10000>;

We have decided to remove the second memory region and access the 
relevant memories through syscon interface.

>> +               reset-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
>> +               queue-count = <32>;
>> +               phy-count = <8>;
>> +               #interrupt-cells = <2>;
>> +               dma-coherent;
>> +               interrupt-parent = <&mbigen_dsa>;
>> +               interrupts = <259 4>, <263 4>,<264 4>,/* phy irq(0~79) */
>> +                               <269 4>,<273 4>,<274 4>,/* phy irq(0~79) */
>> +                               <279 4>,<283 4>,<284 4>,/* phy irq(0~79) */
>> +                               <289 4>,<293 4>,<294 4>,/* phy irq(0~79) */
>> +                               <299 4>,<303 4>,<304 4>,/* phy irq(0~79) */
>> +                               <309 4>,<313 4>,<314 4>,/* phy irq(0~79) */
>> +                               <319 4>,<323 4>,<324 4>,/* phy irq(0~79) */
>> +                               <329 4>,<333 4>,<334 4>,/* phy irq(0~79) */
>> +                               <336 1>,<337 1>,<338 1>,<339 1>,<340 1>,
>> +                               <341 1>,<342 1>,<343 1>,/* cq irq (80~111) */
>> +                               <344 1>,<345 1>,<346 1>,<347 1>,<348 1>,
>> +                               <349 1>,<350 1>,<351 1>,/* cq irq (80~111) */
>> +                               <352 1>,<353 1>,<354 1>,<355 1>,<356 1>,
>> +                               <357 1>,<358 1>,<359 1>,/* cq irq (80~111) */
>> +                               <360 1>,<361 1>,<362 1>,<363 1>,<364 1>,
>> +                               <365 1>,<366 1>,<367 1>,/* cq irq (80~111) */
>> +                               <376 4>,/* chip fatal error irq(120) */
>> +                               <381 4>;/* chip fatal error irq(125) */
>> +               status = "okay";
>> +       };
>> --
>> 1.9.1
>>
>> --
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>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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>
> .
>
Thanks,
John


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Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

On 16/10/2015 14:36, Arnd Bergmann wrote:
> On Friday 16 October 2015 14:29:55 John Garry wrote:
>>
>> It could be considered.
>>
>> A potential issue I see is with hisi_sas_control_phy() for
>> PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes
>> the reset in the queue work. When we re-enable the phy for the reset,
>> the phyup irq will want to use the same hisi_sas_wq struct which may be
>> in use.
>>
>> hisi_sas_control_phy() is added in 23/35.
>
> I'd have to review more closely, but I think that's fine, as this
> is how most work queues are used: you can queue the same function
> multiple times, and it's guaranteed to run at least once after
> the last queue, so if you queue it while it's already running,
> it will be called again, otherwise it won't.
>
> 	Arnd
>
> .
>
In the scenario I described the issue is not that the second call to 
queue the work function is lost. The problem is that when we setup the 
second call we may overwrite elements of the phy's hisi_sas_wq struct 
which may be still being referenced in the work function for the first call.

Regards,
John

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

On 16/10/2015 14:36, Arnd Bergmann wrote:
> On Friday 16 October 2015 14:29:55 John Garry wrote:
>>
>> It could be considered.
>>
>> A potential issue I see is with hisi_sas_control_phy() for
>> PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes
>> the reset in the queue work. When we re-enable the phy for the reset,
>> the phyup irq will want to use the same hisi_sas_wq struct which may be
>> in use.
>>
>> hisi_sas_control_phy() is added in 23/35.
>
> I'd have to review more closely, but I think that's fine, as this
> is how most work queues are used: you can queue the same function
> multiple times, and it's guaranteed to run at least once after
> the last queue, so if you queue it while it's already running,
> it will be called again, otherwise it won't.
>
> 	Arnd
>
> .
>
In the scenario I described the issue is not that the second call to 
queue the work function is lost. The problem is that when we setup the 
second call we may overwrite elements of the phy's hisi_sas_wq struct 
which may be still being referenced in the work function for the first call.

Regards,
John

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Arnd Bergmann]

On Monday 19 October 2015 15:11:47 John Garry wrote:
> On 16/10/2015 14:36, Arnd Bergmann wrote:
> > On Friday 16 October 2015 14:29:55 John Garry wrote:
> >>
> >> It could be considered.
> >>
> >> A potential issue I see is with hisi_sas_control_phy() for
> >> PHY_FUNC_HARD_RESET: this allocates a hisi_sas_wq struct and processes
> >> the reset in the queue work. When we re-enable the phy for the reset,
> >> the phyup irq will want to use the same hisi_sas_wq struct which may be
> >> in use.
> >>
> >> hisi_sas_control_phy() is added in 23/35.
> >
> > I'd have to review more closely, but I think that's fine, as this
> > is how most work queues are used: you can queue the same function
> > multiple times, and it's guaranteed to run at least once after
> > the last queue, so if you queue it while it's already running,
> > it will be called again, otherwise it won't.
> >
> In the scenario I described the issue is not that the second call to 
> queue the work function is lost. The problem is that when we setup the 
> second call we may overwrite elements of the phy's hisi_sas_wq struct 
> which may be still being referenced in the work function for the first call.

Do you mean these members?

> +       wq->event = PHYUP;
> +       wq->hisi_hba = hisi_hba;
> +       wq->phy_no = phy_no;

Sorry for being unclear, I implied getting rid of them, by having a
work queue per phy. You can create a structure for each phy like

	struct hisi_sas_phy {
		struct hisi_sas *dev; /* pointer to the device */
		unsigned int phy_no;
		struct work_struct phyup_work;
	};

There are probably other things you can put into the same structure.
When the phy is brought up, you then just start the phyup work for
that phy, which can retrieve its hisi_sas_phy structure from the
work_struct pointer, and from there get to the device.

	Arnd

Re: [PATCH 02/25] devicetree: bindings: scsi: HiSi SAS

[zhangfei]

On 10/19/2015 06:48 PM, John Garry wrote:
> On 16/10/2015 14:47, Rob Herring wrote:

>>> +  - reg : Address and length of the register sets for the device
>>> +   - SAS controller registers
>>> +   - SAS controller control registers
>>> +
>>> +  - reset-reg : offset to reset, status, and clock registers in
>>> control registers
>>
>> Within the above register range? If so and if this varies, then that
>> implies there is more than 1 version of IP. In that case you should
>> have a more specific compatible string.
>>
> The registers in the second region are for syscon register offsets. See
> last note, below.
>
>> How long is this property I count 3 cells here, but the example has 5.
>> Define what each cell corresponds to specifically.
>>
> We will add all the cells to the decription, which are:
> Reset assert, clock disable, reset status, reset de-assert, and clock
> enable.
>>> +

We have switch to using syscon,
The dts has been changed to

         sas_ctrl0: sas_ctrl@c0000000 {
                 compatible = "hisilicon,sas-ctrl", "syscon";
                 reg = <0x0 0xc0000000 0x0 0x10000>;
         };

         sas0: sas@c1000000 {
                 compatible = "hisilicon,sas-controller-v1";
                 reg = <0x0 0xc1000000 0x0 0x10000>;
                 hisilicon,sas-syscon = <&sas_ctrl0>;
                 ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;

ctrl-reg contains several regs in sas-ctrl, which need to be accessed 
since some complicated requirement of the silicon.

Have considered using
hisilicon,sas-syscon = <&sas_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;
But of_property_read_u32_array cat not get array from index 1.
Then we have to use of_property_read_u32_index one by one.

So instead we add additional ctrl-reg, and get the array one time via 
of_property_read_u32_array.

Thanks

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

>>> I'd have to review more closely, but I think that's fine, as this
>>> is how most work queues are used: you can queue the same function
>>> multiple times, and it's guaranteed to run at least once after
>>> the last queue, so if you queue it while it's already running,
>>> it will be called again, otherwise it won't.
>>>
>> In the scenario I described the issue is not that the second call to
>> queue the work function is lost. The problem is that when we setup the
>> second call we may overwrite elements of the phy's hisi_sas_wq struct
>> which may be still being referenced in the work function for the first call.
>
> Do you mean these members?
>
>> +       wq->event = PHYUP;
>> +       wq->hisi_hba = hisi_hba;
>> +       wq->phy_no = phy_no;
>
Yes, these are the members I was referring to. However there is also an 
element "data" in hisi_sas_wq. This is used in control phy as follows:
int hisi_sas_control_phy(struct asd_sas_phy *sas_phy,
			enum phy_func func,
			void *funcdata)
{
	...
	wq->event = CONTROL_PHY;
	wq->data = func;
	...
	INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
	queue_work(hisi_hba->wq, &wq->work_struct);
}

void hisi_sas_wq_process(struct work_struct *work)
{
	struct hisi_sas_wq *wq =
		container_of(work, struct hisi_sas_wq, work_struct);
	switch (wq->event) {
	case CONTROL_PHY:
		hisi_sas_control_phy_work(hisi_hba, wq->data, phy_no);
}

static void hisi_sas_control_phy_work(struct hisi_hba *hisi_hba,
				int func,
				int phy_no)
{
	switch (func) {
	case PHY_FUNC_HARD_RESET:
		hard_phy_reset_v1_hw(hisi_hba, phy_no)

> Sorry for being unclear, I implied getting rid of them, by having a
> work queue per phy. You can create a structure for each phy like
>
> 	struct hisi_sas_phy {
> 		struct hisi_sas *dev; /* pointer to the device */
> 		unsigned int phy_no;
> 		struct work_struct phyup_work;
> 	};
>
> There are probably other things you can put into the same structure.
> When the phy is brought up, you then just start the phyup work for
> that phy, which can retrieve its hisi_sas_phy structure from the
> work_struct pointer, and from there get to the device.
>
> 	Arnd
>
> .
>
We could create a work_struct for each event, which would be fine. 
However we would sometimes still need some way of passing data to the 
event, like the phy control example.

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

>>> I'd have to review more closely, but I think that's fine, as this
>>> is how most work queues are used: you can queue the same function
>>> multiple times, and it's guaranteed to run at least once after
>>> the last queue, so if you queue it while it's already running,
>>> it will be called again, otherwise it won't.
>>>
>> In the scenario I described the issue is not that the second call to
>> queue the work function is lost. The problem is that when we setup the
>> second call we may overwrite elements of the phy's hisi_sas_wq struct
>> which may be still being referenced in the work function for the first call.
>
> Do you mean these members?
>
>> +       wq->event = PHYUP;
>> +       wq->hisi_hba = hisi_hba;
>> +       wq->phy_no = phy_no;
>
Yes, these are the members I was referring to. However there is also an 
element "data" in hisi_sas_wq. This is used in control phy as follows:
int hisi_sas_control_phy(struct asd_sas_phy *sas_phy,
			enum phy_func func,
			void *funcdata)
{
	...
	wq->event = CONTROL_PHY;
	wq->data = func;
	...
	INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
	queue_work(hisi_hba->wq, &wq->work_struct);
}

void hisi_sas_wq_process(struct work_struct *work)
{
	struct hisi_sas_wq *wq =
		container_of(work, struct hisi_sas_wq, work_struct);
	switch (wq->event) {
	case CONTROL_PHY:
		hisi_sas_control_phy_work(hisi_hba, wq->data, phy_no);
}

static void hisi_sas_control_phy_work(struct hisi_hba *hisi_hba,
				int func,
				int phy_no)
{
	switch (func) {
	case PHY_FUNC_HARD_RESET:
		hard_phy_reset_v1_hw(hisi_hba, phy_no)

> Sorry for being unclear, I implied getting rid of them, by having a
> work queue per phy. You can create a structure for each phy like
>
> 	struct hisi_sas_phy {
> 		struct hisi_sas *dev; /* pointer to the device */
> 		unsigned int phy_no;
> 		struct work_struct phyup_work;
> 	};
>
> There are probably other things you can put into the same structure.
> When the phy is brought up, you then just start the phyup work for
> that phy, which can retrieve its hisi_sas_phy structure from the
> work_struct pointer, and from there get to the device.
>
> 	Arnd
>
> .
>
We could create a work_struct for each event, which would be fine. 
However we would sometimes still need some way of passing data to the 
event, like the phy control example.

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Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[Arnd Bergmann]

On Monday 19 October 2015 15:55:47 John Garry wrote:
> > Do you mean these members?
> >
> >> +       wq->event = PHYUP;
> >> +       wq->hisi_hba = hisi_hba;
> >> +       wq->phy_no = phy_no;
> >
> Yes, these are the members I was referring to. However there is also an 
> element "data" in hisi_sas_wq. This is used in control phy as follows:
> int hisi_sas_control_phy(struct asd_sas_phy *sas_phy,
>                         enum phy_func func,
>                         void *funcdata)
> {
>         ...
>         wq->event = CONTROL_PHY;
>         wq->data = func;
>         ...
>         INIT_WORK(&wq->work_struct, hisi_sas_wq_process);
>         queue_work(hisi_hba->wq, &wq->work_struct);
> }
> 
> void hisi_sas_wq_process(struct work_struct *work)
> {
>         struct hisi_sas_wq *wq =
>                 container_of(work, struct hisi_sas_wq, work_struct);
>         switch (wq->event) {
>         case CONTROL_PHY:
>                 hisi_sas_control_phy_work(hisi_hba, wq->data, phy_no);
> }
> 
> static void hisi_sas_control_phy_work(struct hisi_hba *hisi_hba,
>                                 int func,
>                                 int phy_no)
> {
>         switch (func) {
>         case PHY_FUNC_HARD_RESET:
>                 hard_phy_reset_v1_hw(hisi_hba, phy_no)

Ok.

> > Sorry for being unclear, I implied getting rid of them, by having a
> > work queue per phy. You can create a structure for each phy like
> >
> >       struct hisi_sas_phy {
> >               struct hisi_sas *dev; /* pointer to the device */
> >               unsigned int phy_no;
> >               struct work_struct phyup_work;
> >       };
> >
> > There are probably other things you can put into the same structure.
> > When the phy is brought up, you then just start the phyup work for
> > that phy, which can retrieve its hisi_sas_phy structure from the
> > work_struct pointer, and from there get to the device.
> >
> We could create a work_struct for each event, which would be fine.

Yes, that would be the normal way to do it. You initialize the work
structures from the initial probe function to have the right callbacks,
and then you just queue the right one when you need to defer an event.

 How many different events are there?

> However we would sometimes still need some way of passing data to the 
> event, like the phy control example.

Do you mean the 'int func' argument to hisi_sas_control_phy_work?
It sounds like that would again just be more different work_structs.

At some point that might get silly (having 10 or more work structs
per phy), but then you could restructure the code to use something
other that work queues to get from interrupt context to process
context, e.g. a threaded interrupt handler.

Note that the current code is not only unusual but also fragile
because you rely on GFP_ATOMIC memory allocations from the interrupt
handler, and they tend to eventually fail.

	Arnd

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

>> We could create a work_struct for each event, which would be fine.
>
> Yes, that would be the normal way to do it. You initialize the work
> structures from the initial probe function to have the right
> callbacks, and then you just queue the right one when you need to
> defer an event.
>
> How many different events are there?
>
We currently only support processing 2 events in the workqueue: phy up 
and control phy. However we may want to use more in the future, like
hotplug (for phy down) event.

>> However we would sometimes still need some way of passing data to
>> the event, like the phy control example.
>
> Do you mean the 'int func' argument to hisi_sas_control_phy_work?
Yes
> It sounds like that would again just be more different work_structs.
>
> At some point that might get silly (having 10 or more work structs
> per phy), but then you could restructure the code to use something
> other that work queues to get from interrupt context to process
> context, e.g. a threaded interrupt handler.
I'll check on this. We need to consider how to pass the argument for the 
control phy case.
>
> Note that the current code is not only unusual but also fragile
> because you rely on GFP_ATOMIC memory allocations from the interrupt
> handler, and they tend to eventually fail.
Understood. For what it's worth, I was just following other SAS drivers
as a refernce: see pm8001_handle_event() and mvs_handle_event()

>
> Arnd -- To unsubscribe from this list: send the line "unsubscribe
> linux-scsi" in the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> .
>
Thanks, John

Re: [PATCH 13/25] scsi: hisi_sas: add path from phyup irq to SAS framework

[John Garry]

>> We could create a work_struct for each event, which would be fine.
>
> Yes, that would be the normal way to do it. You initialize the work
> structures from the initial probe function to have the right
> callbacks, and then you just queue the right one when you need to
> defer an event.
>
> How many different events are there?
>
We currently only support processing 2 events in the workqueue: phy up 
and control phy. However we may want to use more in the future, like
hotplug (for phy down) event.

>> However we would sometimes still need some way of passing data to
>> the event, like the phy control example.
>
> Do you mean the 'int func' argument to hisi_sas_control_phy_work?
Yes
> It sounds like that would again just be more different work_structs.
>
> At some point that might get silly (having 10 or more work structs
> per phy), but then you could restructure the code to use something
> other that work queues to get from interrupt context to process
> context, e.g. a threaded interrupt handler.
I'll check on this. We need to consider how to pass the argument for the 
control phy case.
>
> Note that the current code is not only unusual but also fragile
> because you rely on GFP_ATOMIC memory allocations from the interrupt
> handler, and they tend to eventually fail.
Understood. For what it's worth, I was just following other SAS drivers
as a refernce: see pm8001_handle_event() and mvs_handle_event()

>
> Arnd -- To unsubscribe from this list: send the line "unsubscribe
> linux-scsi" in the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> .
>
Thanks, John