[PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Petri Gynther]

BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310
BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338

WAIT instruction:
Thread enters wait state. No instructions are executed until an
interrupt occurs. The processor's clocks are stopped if both threads
are in idle mode.

Description:
Execution of this instruction puts the thread into wait state, an idle
mode in which no instructions are fetched or executed. The thread remains
in wait state until an interrupt occurs that is not masked by the
interrupt mask field in the Status register. Then, if interrupts are
enabled by the IE bit in the Status register, the interrupt is serviced.
The ERET instruction returns to the instruction following the WAIT
instruction. If interrupts are disabled, the processor resumes executing
instructions with the next sequential instruction.

Programming notes:
The WAIT instruction should be executed while interrupts are disabled
by the IE bit in the Status register. This avoids a potential timing
hazard, which occurs if an interrupt is taken between testing the counter
and executing the WAIT instruction. In this hazard case, the interrupt
will have been completed before the WAIT instruction is executed, so
the processor will remain indefinitely in wait state until the next
interrupt.

Signed-off-by: Petri Gynther <pgynther@google.com>
---
 arch/mips/kernel/idle.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index ab1478d..d636c70 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -160,7 +160,6 @@ void __init check_wait(void)
 	case CPU_BMIPS3300:
 	case CPU_BMIPS4350:
 	case CPU_BMIPS4380:
-	case CPU_BMIPS5000:
 	case CPU_CAVIUM_OCTEON:
 	case CPU_CAVIUM_OCTEON_PLUS:
 	case CPU_CAVIUM_OCTEON2:
@@ -171,7 +170,9 @@ void __init check_wait(void)
 	case CPU_XLP:
 		cpu_wait = r4k_wait;
 		break;
-
+	case CPU_BMIPS5000:
+		cpu_wait = r4k_wait_irqoff;
+		break;
 	case CPU_RM7000:
 		cpu_wait = rm7k_wait_irqoff;
 		break;
-- 
2.6.0.rc2.230.g3dd15c0

Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Florian Fainelli]

Le 19/10/2015 11:44, Petri Gynther a écrit :
> BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310
> BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338
> 
> WAIT instruction:
> Thread enters wait state. No instructions are executed until an
> interrupt occurs. The processor's clocks are stopped if both threads
> are in idle mode.
> 
> Description:
> Execution of this instruction puts the thread into wait state, an idle
> mode in which no instructions are fetched or executed. The thread remains
> in wait state until an interrupt occurs that is not masked by the
> interrupt mask field in the Status register. Then, if interrupts are
> enabled by the IE bit in the Status register, the interrupt is serviced.
> The ERET instruction returns to the instruction following the WAIT
> instruction. If interrupts are disabled, the processor resumes executing
> instructions with the next sequential instruction.
> 
> Programming notes:
> The WAIT instruction should be executed while interrupts are disabled
> by the IE bit in the Status register. This avoids a potential timing
> hazard, which occurs if an interrupt is taken between testing the counter
> and executing the WAIT instruction. In this hazard case, the interrupt
> will have been completed before the WAIT instruction is executed, so
> the processor will remain indefinitely in wait state until the next
> interrupt.
> 
> Signed-off-by: Petri Gynther <pgynther@google.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  arch/mips/kernel/idle.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
> index ab1478d..d636c70 100644
> --- a/arch/mips/kernel/idle.c
> +++ b/arch/mips/kernel/idle.c
> @@ -160,7 +160,6 @@ void __init check_wait(void)
>  	case CPU_BMIPS3300:
>  	case CPU_BMIPS4350:
>  	case CPU_BMIPS4380:
> -	case CPU_BMIPS5000:
>  	case CPU_CAVIUM_OCTEON:
>  	case CPU_CAVIUM_OCTEON_PLUS:
>  	case CPU_CAVIUM_OCTEON2:
> @@ -171,7 +170,9 @@ void __init check_wait(void)
>  	case CPU_XLP:
>  		cpu_wait = r4k_wait;
>  		break;
> -
> +	case CPU_BMIPS5000:
> +		cpu_wait = r4k_wait_irqoff;
> +		break;
>  	case CPU_RM7000:
>  		cpu_wait = rm7k_wait_irqoff;
>  		break;
> 


-- 
Florian

Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Petri Gynther]

On Mon, Oct 19, 2015 at 8:18 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Le 19/10/2015 11:44, Petri Gynther a écrit :
>> BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310
>> BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338
>>
>> WAIT instruction:
>> Thread enters wait state. No instructions are executed until an
>> interrupt occurs. The processor's clocks are stopped if both threads
>> are in idle mode.
>>
>> Description:
>> Execution of this instruction puts the thread into wait state, an idle
>> mode in which no instructions are fetched or executed. The thread remains
>> in wait state until an interrupt occurs that is not masked by the
>> interrupt mask field in the Status register. Then, if interrupts are
>> enabled by the IE bit in the Status register, the interrupt is serviced.
>> The ERET instruction returns to the instruction following the WAIT
>> instruction. If interrupts are disabled, the processor resumes executing
>> instructions with the next sequential instruction.
>>
>> Programming notes:
>> The WAIT instruction should be executed while interrupts are disabled
>> by the IE bit in the Status register. This avoids a potential timing
>> hazard, which occurs if an interrupt is taken between testing the counter
>> and executing the WAIT instruction. In this hazard case, the interrupt
>> will have been completed before the WAIT instruction is executed, so
>> the processor will remain indefinitely in wait state until the next
>> interrupt.
>>
>> Signed-off-by: Petri Gynther <pgynther@google.com>
>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
>

Thanks Florian.

We have been using this patch on our BMIPS5000 systems for a while
now. No issues.

>> ---
>>  arch/mips/kernel/idle.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
>> index ab1478d..d636c70 100644
>> --- a/arch/mips/kernel/idle.c
>> +++ b/arch/mips/kernel/idle.c
>> @@ -160,7 +160,6 @@ void __init check_wait(void)
>>       case CPU_BMIPS3300:
>>       case CPU_BMIPS4350:
>>       case CPU_BMIPS4380:
>> -     case CPU_BMIPS5000:
>>       case CPU_CAVIUM_OCTEON:
>>       case CPU_CAVIUM_OCTEON_PLUS:
>>       case CPU_CAVIUM_OCTEON2:
>> @@ -171,7 +170,9 @@ void __init check_wait(void)
>>       case CPU_XLP:
>>               cpu_wait = r4k_wait;
>>               break;
>> -
>> +     case CPU_BMIPS5000:
>> +             cpu_wait = r4k_wait_irqoff;
>> +             break;
>>       case CPU_RM7000:
>>               cpu_wait = rm7k_wait_irqoff;
>>               break;
>>
>
>
> --
> Florian

Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Ralf Baechle]

On Mon, Oct 19, 2015 at 11:44:24AM -0700, Petri Gynther wrote:

> BCM7425 CPU Interface Zephyr Processor, pages 5-309 and 5-310
> BCM7428B0 CPU Interface Zephyr Processor, pages 5-337 and 5-338
> 
> WAIT instruction:
> Thread enters wait state. No instructions are executed until an
> interrupt occurs. The processor's clocks are stopped if both threads
> are in idle mode.
> 
> Description:
> Execution of this instruction puts the thread into wait state, an idle
> mode in which no instructions are fetched or executed. The thread remains
> in wait state until an interrupt occurs that is not masked by the
> interrupt mask field in the Status register. Then, if interrupts are
> enabled by the IE bit in the Status register, the interrupt is serviced.
> The ERET instruction returns to the instruction following the WAIT
> instruction. If interrupts are disabled, the processor resumes executing
> instructions with the next sequential instruction.
> 
> Programming notes:
> The WAIT instruction should be executed while interrupts are disabled
> by the IE bit in the Status register. This avoids a potential timing
> hazard, which occurs if an interrupt is taken between testing the counter
> and executing the WAIT instruction. In this hazard case, the interrupt
> will have been completed before the WAIT instruction is executed, so
> the processor will remain indefinitely in wait state until the next
> interrupt.

Note that this is the opposite restriction than many older MIPS CPUs
where it is undefined if an interrupt will restart execution of
instructions if interrupts are disabled.  So this might be a violation
of the architecture specification.  However I rather have it the BMIPS
way than the other way ...

  Ralf

Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Maciej W. Rozycki]

On Mon, 9 Nov 2015, Ralf Baechle wrote:

> > Programming notes:
> > The WAIT instruction should be executed while interrupts are disabled
> > by the IE bit in the Status register. This avoids a potential timing
> > hazard, which occurs if an interrupt is taken between testing the counter
> > and executing the WAIT instruction. In this hazard case, the interrupt
> > will have been completed before the WAIT instruction is executed, so
> > the processor will remain indefinitely in wait state until the next
> > interrupt.
> 
> Note that this is the opposite restriction than many older MIPS CPUs
> where it is undefined if an interrupt will restart execution of
> instructions if interrupts are disabled.  So this might be a violation
> of the architecture specification.  However I rather have it the BMIPS
> way than the other way ...

 It's been implementation-dependent since MIPSr1 whether a non-enabled 
interrupt breaks out of WAIT, so no architecture specification violation 
here.

  Maciej

Re: [PATCH] MIPS: switch BMIPS5000 to use r4k_wait_irqoff()

[Ralf Baechle]

On Tue, Jan 12, 2016 at 12:42:14AM +0000, Maciej W. Rozycki wrote:

> > > Programming notes:
> > > The WAIT instruction should be executed while interrupts are disabled
> > > by the IE bit in the Status register. This avoids a potential timing
> > > hazard, which occurs if an interrupt is taken between testing the counter
> > > and executing the WAIT instruction. In this hazard case, the interrupt
> > > will have been completed before the WAIT instruction is executed, so
> > > the processor will remain indefinitely in wait state until the next
> > > interrupt.
> > 
> > Note that this is the opposite restriction than many older MIPS CPUs
> > where it is undefined if an interrupt will restart execution of
> > instructions if interrupts are disabled.  So this might be a violation
> > of the architecture specification.  However I rather have it the BMIPS
> > way than the other way ...
> 
>  It's been implementation-dependent since MIPSr1 whether a non-enabled 
> interrupt breaks out of WAIT, so no architecture specification violation 
> here.

I probably should have clarified that in the commit message but alas
too late, this commit is long upstream.

  Ralf