* [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
@ 2015-09-21 18:11 Kumar, Mahesh
2015-10-23 16:53 ` Matt Roper
0 siblings, 1 reply; 5+ messages in thread
From: Kumar, Mahesh @ 2015-09-21 18:11 UTC (permalink / raw)
To: intel-gfx
In case of Y-Tiling, "plane_blocks_per_line" calculation is different
than X/None-Tiling case.
This patch corrects this calculation according to Bspec.
plane blocks per line = Plane memory format is Y tile ?
ceiling[4 * plane bytes per line / 512]/4 :
ceiling[plane bytes per line / 512]
As per BSpec Don't increment selected "result_blocks" & "result_lines"
in case of BROXTON.
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a1ed920..5cfb5d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
latency);
plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
- plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
+
+ if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
+ p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line, 512);
+ plane_blocks_per_line /= 4;
+ } else
+ plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
@@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
res_blocks = selected_result + 1;
res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
- if (level >= 1 && level <= 7) {
+ if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
res_lines += 4;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
2015-09-21 18:11 [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton Kumar, Mahesh
@ 2015-10-23 16:53 ` Matt Roper
2015-11-17 14:19 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Matt Roper @ 2015-10-23 16:53 UTC (permalink / raw)
To: Kumar, Mahesh; +Cc: intel-gfx
On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
> In case of Y-Tiling, "plane_blocks_per_line" calculation is different
> than X/None-Tiling case.
> This patch corrects this calculation according to Bspec.
> plane blocks per line = Plane memory format is Y tile ?
> ceiling[4 * plane bytes per line / 512]/4 :
> ceiling[plane bytes per line / 512]
> As per BSpec Don't increment selected "result_blocks" & "result_lines"
> in case of BROXTON.
>
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Confirmed both changes against bspec. Note that your first hunk here is
technically a fix for both SKL and BXT, only the second one is a
BXT-specific fix.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a1ed920..5cfb5d9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> latency);
>
> plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
> - plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
> +
> + if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> + p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> + plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line, 512);
> + plane_blocks_per_line /= 4;
> + } else
> + plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>
> if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> @@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> res_blocks = selected_result + 1;
> res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
>
> - if (level >= 1 && level <= 7) {
> + if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
> if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
> res_lines += 4;
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
2015-10-23 16:53 ` Matt Roper
@ 2015-11-17 14:19 ` Daniel Vetter
2015-11-17 14:52 ` Jani Nikula
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2015-11-17 14:19 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote:
> On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
> > In case of Y-Tiling, "plane_blocks_per_line" calculation is different
> > than X/None-Tiling case.
> > This patch corrects this calculation according to Bspec.
> > plane blocks per line = Plane memory format is Y tile ?
> > ceiling[4 * plane bytes per line / 512]/4 :
> > ceiling[plane bytes per line / 512]
> > As per BSpec Don't increment selected "result_blocks" & "result_lines"
> > in case of BROXTON.
> >
> > Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
>
> Confirmed both changes against bspec. Note that your first hunk here is
> technically a fix for both SKL and BXT, only the second one is a
> BXT-specific fix.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
This needs to be rebased (p_params is gone).
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a1ed920..5cfb5d9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > latency);
> >
> > plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
> > - plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
> > +
> > + if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> > + p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> > + plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line, 512);
> > + plane_blocks_per_line /= 4;
> > + } else
> > + plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
> >
> > if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> > p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> > @@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > res_blocks = selected_result + 1;
> > res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
> >
> > - if (level >= 1 && level <= 7) {
> > + if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
> > if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> > p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
> > res_lines += 4;
> > --
> > 1.9.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
2015-11-17 14:19 ` Daniel Vetter
@ 2015-11-17 14:52 ` Jani Nikula
2015-11-17 15:11 ` Tvrtko Ursulin
0 siblings, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2015-11-17 14:52 UTC (permalink / raw)
To: Daniel Vetter, Matt Roper; +Cc: intel-gfx
On Tue, 17 Nov 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote:
>> On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
>> > In case of Y-Tiling, "plane_blocks_per_line" calculation is different
>> > than X/None-Tiling case.
>> > This patch corrects this calculation according to Bspec.
>> > plane blocks per line = Plane memory format is Y tile ?
>> > ceiling[4 * plane bytes per line / 512]/4 :
>> > ceiling[plane bytes per line / 512]
>> > As per BSpec Don't increment selected "result_blocks" & "result_lines"
>> > in case of BROXTON.
>> >
>> > Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
>>
>> Confirmed both changes against bspec. Note that your first hunk here is
>> technically a fix for both SKL and BXT, only the second one is a
>> BXT-specific fix.
>>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> This needs to be rebased (p_params is gone).
And we already have this for skl
commit 0fda65680e92545caea5be7805a7f0a617fb6c20
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri Feb 27 15:12:35 2015 +0000
drm/i915/skl: Update watermarks for Y tiling
Mahesh, please check if you still need to make changes for BXT.
BR,
Jani.
> -Daniel
>>
>> > ---
>> > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
>> > 1 file changed, 8 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index a1ed920..5cfb5d9 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> > latency);
>> >
>> > plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
>> > - plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>> > +
>> > + if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> > + p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
>> > + plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line, 512);
>> > + plane_blocks_per_line /= 4;
>> > + } else
>> > + plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>> >
>> > if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> > p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
>> > @@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> > res_blocks = selected_result + 1;
>> > res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
>> >
>> > - if (level >= 1 && level <= 7) {
>> > + if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
>> > if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> > p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
>> > res_lines += 4;
>> > --
>> > 1.9.1
>> >
>>
>> --
>> Matt Roper
>> Graphics Software Engineer
>> IoTG Platform Enabling & Development
>> Intel Corporation
>> (916) 356-2795
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
2015-11-17 14:52 ` Jani Nikula
@ 2015-11-17 15:11 ` Tvrtko Ursulin
0 siblings, 0 replies; 5+ messages in thread
From: Tvrtko Ursulin @ 2015-11-17 15:11 UTC (permalink / raw)
To: Jani Nikula, Daniel Vetter, Matt Roper; +Cc: intel-gfx
On 17/11/15 14:52, Jani Nikula wrote:
> On Tue, 17 Nov 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote:
>>> On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
>>>> In case of Y-Tiling, "plane_blocks_per_line" calculation is different
>>>> than X/None-Tiling case.
>>>> This patch corrects this calculation according to Bspec.
>>>> plane blocks per line = Plane memory format is Y tile ?
>>>> ceiling[4 * plane bytes per line / 512]/4 :
>>>> ceiling[plane bytes per line / 512]
>>>> As per BSpec Don't increment selected "result_blocks" & "result_lines"
>>>> in case of BROXTON.
>>>>
>>>> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
>>>
>>> Confirmed both changes against bspec. Note that your first hunk here is
>>> technically a fix for both SKL and BXT, only the second one is a
>>> BXT-specific fix.
>>>
>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> This needs to be rebased (p_params is gone).
>
> And we already have this for skl
>
> commit 0fda65680e92545caea5be7805a7f0a617fb6c20
> Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Date: Fri Feb 27 15:12:35 2015 +0000
>
> drm/i915/skl: Update watermarks for Y tiling
>
> Mahesh, please check if you still need to make changes for BXT.
Mahesh's patch seems to be on top of that one, so either a new doc
change or something I've missed back then.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-11-17 15:11 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-09-21 18:11 [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton Kumar, Mahesh
2015-10-23 16:53 ` Matt Roper
2015-11-17 14:19 ` Daniel Vetter
2015-11-17 14:52 ` Jani Nikula
2015-11-17 15:11 ` Tvrtko Ursulin
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.