Re: [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

Re: [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

[Daniel Vetter]

On Wed, Dec 09, 2015 at 05:29:58PM +0530, Deepak M wrote:
> Pipe is assigned based on the port, but it should be
> based on current crtc. Correcting the same in this patch.
> 
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index f5df49b..0654b33 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  			I915_WRITE(MIPI_CTRL(port), tmp |
>  					READ_REQUEST_PRIORITY_HIGH);
>  		} else if (IS_BROXTON(dev)) {
> -			/*
> -			 * FIXME:
> -			 * BXT can connect any PIPE to any MIPI port.
> -			 * Select the pipe based on the MIPI port read from
> -			 * VBT for now. Pick PIPE A for MIPI port A and C
> -			 * for port C.
> -			 */
> +			enum pipe pipe = intel_crtc->pipe;
> +
>  			tmp = I915_READ(MIPI_CTRL(port));
>  			tmp &= ~BXT_PIPE_SELECT_MASK;
>  
> -			if (port == PORT_A)
> +			switch (pipe) {
> +			case PIPE_A:
>  				tmp |= BXT_PIPE_SELECT_A;
> -			else if (port == PORT_C)
> +				break;
> +			case PIPE_B:
> +				tmp |= BXT_PIPE_SELECT_B;
> +				break;
> +			case PIPE_C:
>  				tmp |= BXT_PIPE_SELECT_C;

Please create a BXT_PIPE_SELECT(pipe) macro like we have for all the other
outputs that support more than 1 pipe selection bit. See e.g.
DP_PIPE_SELECT_CHV.
-Daniel

> +				break;
> +			default:
> +				DRM_ERROR("Unknown pipe used\n");
> +				return;
> +			}
>  
>  			I915_WRITE(MIPI_CTRL(port), tmp);
>  		}
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

[Deepak, M]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, December 9, 2015 1:50 PM
> To: Deepak, M <m.deepak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual link pipe
> selection for bxt
> 
> On Wed, Dec 09, 2015 at 05:29:58PM +0530, Deepak M wrote:
> > Pipe is assigned based on the port, but it should be based on current
> > crtc. Correcting the same in this patch.
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++---------
> >  1 file changed, 14 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index f5df49b..0654b33 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder)
> >  			I915_WRITE(MIPI_CTRL(port), tmp |
> >  					READ_REQUEST_PRIORITY_HIGH);
> >  		} else if (IS_BROXTON(dev)) {
> > -			/*
> > -			 * FIXME:
> > -			 * BXT can connect any PIPE to any MIPI port.
> > -			 * Select the pipe based on the MIPI port read from
> > -			 * VBT for now. Pick PIPE A for MIPI port A and C
> > -			 * for port C.
> > -			 */
> > +			enum pipe pipe = intel_crtc->pipe;
> > +
> >  			tmp = I915_READ(MIPI_CTRL(port));
> >  			tmp &= ~BXT_PIPE_SELECT_MASK;
> >
> > -			if (port == PORT_A)
> > +			switch (pipe) {
> > +			case PIPE_A:
> >  				tmp |= BXT_PIPE_SELECT_A;
> > -			else if (port == PORT_C)
> > +				break;
> > +			case PIPE_B:
> > +				tmp |= BXT_PIPE_SELECT_B;
> > +				break;
> > +			case PIPE_C:
> >  				tmp |= BXT_PIPE_SELECT_C;
> 
> Please create a BXT_PIPE_SELECT(pipe) macro like we have for all the other
> outputs that support more than 1 pipe selection bit. See e.g.
> DP_PIPE_SELECT_CHV.
> -Daniel
> 
[Deepak, M] Agreed,  Have tried to address this comment http://lists.freedesktop.org/archives/intel-gfx/2015-December/082431.html 
> > +				break;
> > +			default:
> > +				DRM_ERROR("Unknown pipe used\n");
> > +				return;
> > +			}
> >
> >  			I915_WRITE(MIPI_CTRL(port), tmp);
> >  		}
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[BXT MIPI PATCH 1/2] drm/i915: Set the Z inversion overlap field for BXT

[Deepak M]

For broxton dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the other platforms, hence
setting the same in this patch.

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
 drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 009f474..fa72be9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {
 #define  BXT_PIPE_SELECT_B				(1 << 7)
 #define  BXT_PIPE_SELECT_A				(0 << 7)
 
+/* BXT has dual link Z inversion overlap field */
+#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
+
 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
 #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index eff982b..f5df49b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	u32 port_ctrl;
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-		temp = I915_READ(VLV_CHICKEN_3);
-		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+		if (IS_BROXTON(dev)) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				temp = I915_READ(MIPI_CTRL(port));
+				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 					intel_dsi->pixel_overlap <<
+					BXT_PIXEL_OVERLAP_CNT_SHIFT;
+				I915_WRITE(MIPI_CTRL(port), temp);
+			}
+		} else {
+			temp = I915_READ(VLV_CHICKEN_3);
+			temp &= ~PIXEL_OVERLAP_CNT_MASK |
+				intel_dsi->pixel_overlap <<
 					PIXEL_OVERLAP_CNT_SHIFT;
-		I915_WRITE(VLV_CHICKEN_3, temp);
+			I915_WRITE(VLV_CHICKEN_3, temp);
+		}
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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[BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

[Deepak M]

Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f5df49b..0654b33 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			I915_WRITE(MIPI_CTRL(port), tmp |
 					READ_REQUEST_PRIORITY_HIGH);
 		} else if (IS_BROXTON(dev)) {
-			/*
-			 * FIXME:
-			 * BXT can connect any PIPE to any MIPI port.
-			 * Select the pipe based on the MIPI port read from
-			 * VBT for now. Pick PIPE A for MIPI port A and C
-			 * for port C.
-			 */
+			enum pipe pipe = intel_crtc->pipe;
+
 			tmp = I915_READ(MIPI_CTRL(port));
 			tmp &= ~BXT_PIPE_SELECT_MASK;
 
-			if (port == PORT_A)
+			switch (pipe) {
+			case PIPE_A:
 				tmp |= BXT_PIPE_SELECT_A;
-			else if (port == PORT_C)
+				break;
+			case PIPE_B:
+				tmp |= BXT_PIPE_SELECT_B;
+				break;
+			case PIPE_C:
 				tmp |= BXT_PIPE_SELECT_C;
+				break;
+			default:
+				DRM_ERROR("Unknown pipe used\n");
+				return;
+			}
 
 			I915_WRITE(MIPI_CTRL(port), tmp);
 		}
-- 
1.9.1

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Re: [BXT MIPI PATCH 1/2] drm/i915: Set the Z inversion overlap field for BXT

[Ville Syrjälä]

On Wed, Dec 09, 2015 at 05:29:57PM +0530, Deepak M wrote:
> For broxton dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the other platforms, hence
> setting the same in this patch.
> 
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++---
>  2 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 009f474..fa72be9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {
>  #define  BXT_PIPE_SELECT_B				(1 << 7)
>  #define  BXT_PIPE_SELECT_A				(0 << 7)
>  
> +/* BXT has dual link Z inversion overlap field */
> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10

This could be parametrized. eg:
BXT_PIXEL_OVERLAP_CNT(x) ((x) << 10))

And so could the VLV version.

> +
>  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
>  #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index eff982b..f5df49b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	u32 port_ctrl;
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -		temp = I915_READ(VLV_CHICKEN_3);
> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +		if (IS_BROXTON(dev)) {
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				temp = I915_READ(MIPI_CTRL(port));
> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
>  					intel_dsi->pixel_overlap <<
> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;

That won't do anything sane.

> +				I915_WRITE(MIPI_CTRL(port), temp);
> +			}
> +		} else {
> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +				intel_dsi->pixel_overlap <<
>  					PIXEL_OVERLAP_CNT_SHIFT;
> -		I915_WRITE(VLV_CHICKEN_3, temp);
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH] drm/i915: dual link pipe selection for bxt

[Ville Syrjälä]

On Wed, Dec 09, 2015 at 08:14:04PM +0530, Deepak M wrote:
> Pipe is assigned based on the port, but it should be
> based on current crtc. Correcting the same in this patch.
> 
> v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)
> 
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 +---
>  drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------
>  2 files changed, 4 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa72be9..91dbb32 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {
>  #define  RGB_FLIP_TO_BGR				(1 << 2)
>  
>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
> -#define  BXT_PIPE_SELECT_C				(2 << 7)
> -#define  BXT_PIPE_SELECT_B				(1 << 7)
> -#define  BXT_PIPE_SELECT_A				(0 << 7)
> +#define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
>  
>  /* BXT has dual link Z inversion overlap field */
>  #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index f5df49b..12cfcf5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  			I915_WRITE(MIPI_CTRL(port), tmp |
>  					READ_REQUEST_PRIORITY_HIGH);
>  		} else if (IS_BROXTON(dev)) {
> -			/*
> -			 * FIXME:
> -			 * BXT can connect any PIPE to any MIPI port.
> -			 * Select the pipe based on the MIPI port read from
> -			 * VBT for now. Pick PIPE A for MIPI port A and C
> -			 * for port C.
> -			 */
> +			enum pipe pipe = intel_crtc->pipe;
> +
>  			tmp = I915_READ(MIPI_CTRL(port));
>  			tmp &= ~BXT_PIPE_SELECT_MASK;
>  
> -			if (port == PORT_A)
> -				tmp |= BXT_PIPE_SELECT_A;
> -			else if (port == PORT_C)
> -				tmp |= BXT_PIPE_SELECT_C;
> -
> +			tmp |= BXT_PIPE_SELECT(pipe);
>  			I915_WRITE(MIPI_CTRL(port), tmp);

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

There's way too much RMW going on in the DSI code though. Someone should
probably do something about it.

>  		}
>  
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH] drm/i915: dual link pipe selection for bxt

[Deepak M]

Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.

v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 +---
 drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa72be9..91dbb32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {
 #define  RGB_FLIP_TO_BGR				(1 << 2)
 
 #define  BXT_PIPE_SELECT_MASK				(7 << 7)
-#define  BXT_PIPE_SELECT_C				(2 << 7)
-#define  BXT_PIPE_SELECT_B				(1 << 7)
-#define  BXT_PIPE_SELECT_A				(0 << 7)
+#define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
 
 /* BXT has dual link Z inversion overlap field */
 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f5df49b..12cfcf5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			I915_WRITE(MIPI_CTRL(port), tmp |
 					READ_REQUEST_PRIORITY_HIGH);
 		} else if (IS_BROXTON(dev)) {
-			/*
-			 * FIXME:
-			 * BXT can connect any PIPE to any MIPI port.
-			 * Select the pipe based on the MIPI port read from
-			 * VBT for now. Pick PIPE A for MIPI port A and C
-			 * for port C.
-			 */
+			enum pipe pipe = intel_crtc->pipe;
+
 			tmp = I915_READ(MIPI_CTRL(port));
 			tmp &= ~BXT_PIPE_SELECT_MASK;
 
-			if (port == PORT_A)
-				tmp |= BXT_PIPE_SELECT_A;
-			else if (port == PORT_C)
-				tmp |= BXT_PIPE_SELECT_C;
-
+			tmp |= BXT_PIPE_SELECT(pipe);
 			I915_WRITE(MIPI_CTRL(port), tmp);
 		}
 
-- 
1.9.1

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Re: [PATCH] drm/i915: dual link pipe selection for bxt

[Daniel Vetter]

On Wed, Dec 09, 2015 at 03:54:33PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 09, 2015 at 08:14:04PM +0530, Deepak M wrote:
> > Pipe is assigned based on the port, but it should be
> > based on current crtc. Correcting the same in this patch.
> > 
> > v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)
> > 
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  4 +---
> >  drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------
> >  2 files changed, 4 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index fa72be9..91dbb32 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {
> >  #define  RGB_FLIP_TO_BGR				(1 << 2)
> >  
> >  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
> > -#define  BXT_PIPE_SELECT_C				(2 << 7)
> > -#define  BXT_PIPE_SELECT_B				(1 << 7)
> > -#define  BXT_PIPE_SELECT_A				(0 << 7)
> > +#define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
> >  
> >  /* BXT has dual link Z inversion overlap field */
> >  #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index f5df49b..12cfcf5 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
> >  			I915_WRITE(MIPI_CTRL(port), tmp |
> >  					READ_REQUEST_PRIORITY_HIGH);
> >  		} else if (IS_BROXTON(dev)) {
> > -			/*
> > -			 * FIXME:
> > -			 * BXT can connect any PIPE to any MIPI port.
> > -			 * Select the pipe based on the MIPI port read from
> > -			 * VBT for now. Pick PIPE A for MIPI port A and C
> > -			 * for port C.
> > -			 */
> > +			enum pipe pipe = intel_crtc->pipe;
> > +
> >  			tmp = I915_READ(MIPI_CTRL(port));
> >  			tmp &= ~BXT_PIPE_SELECT_MASK;
> >  
> > -			if (port == PORT_A)
> > -				tmp |= BXT_PIPE_SELECT_A;
> > -			else if (port == PORT_C)
> > -				tmp |= BXT_PIPE_SELECT_C;
> > -
> > +			tmp |= BXT_PIPE_SELECT(pipe);
> >  			I915_WRITE(MIPI_CTRL(port), tmp);
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There's way too much RMW going on in the DSI code though. Someone should
> probably do something about it.

Yeah that'd be nice.

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [BXT MIPI PATCH 1/2] drm/i915: Set the Z inversion overlap field for BXT

[Mika Kahola]

On Wed, 2015-12-09 at 17:29 +0530, Deepak M wrote:
> For broxton dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the other platforms, hence
> setting the same in this patch.
> 
Tested-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_dsi.c | 16 +++++++++++++---
>  2 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 009f474..fa72be9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {
>  #define  BXT_PIPE_SELECT_B				(1 << 7)
>  #define  BXT_PIPE_SELECT_A				(0 << 7)
>  
> +/* BXT has dual link Z inversion overlap field */
> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
> +
>  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
>  #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index eff982b..f5df49b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	u32 port_ctrl;
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -		temp = I915_READ(VLV_CHICKEN_3);
> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +		if (IS_BROXTON(dev)) {
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				temp = I915_READ(MIPI_CTRL(port));
> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
>  					intel_dsi->pixel_overlap <<
> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> +				I915_WRITE(MIPI_CTRL(port), temp);
> +			}
> +		} else {
> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +				intel_dsi->pixel_overlap <<
>  					PIXEL_OVERLAP_CNT_SHIFT;
> -		I915_WRITE(VLV_CHICKEN_3, temp);
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {


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