* [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered
@ 2015-11-02 1:30 Boqun Feng
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Boqun Feng @ 2015-11-02 1:30 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Peter Zijlstra, Ingo Molnar, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Thomas Gleixner, Will Deacon,
Paul E. McKenney, Boqun Feng, stable
According to memory-barriers.txt:
> Any atomic operation that modifies some state in memory and returns
> information about the state (old or new) implies an SMP-conditional
> general memory barrier (smp_mb()) on each side of the actual
> operation ...
Which mean these operations should be fully ordered. However on PPC,
PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
which is currently "lwsync" if SMP=y. The leading "lwsync" can not
guarantee fully ordered atomics, according to Paul Mckenney:
https://lkml.org/lkml/2015/10/14/970
To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
the fully-ordered semantics.
This also makes futex atomics fully ordered, which can avoid possible
memory ordering problems if userspace code relies on futex system call
for fully ordered semantics.
Cc: <stable@vger.kernel.org> # 3.4+
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
---
These two are separated and splited from the patchset of powerpc atomic
variants implementation, whose link is:
https://lkml.org/lkml/2015/10/26/141
Based on next branch of powerpc tree, tested by 0day.
arch/powerpc/include/asm/synch.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index e682a71..c508686 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -44,7 +44,7 @@ static inline void isync(void)
MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
-#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n"
+#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n"
#define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
#else
#define PPC_ACQUIRE_BARRIER
--
2.6.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
2015-11-02 1:30 [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng
@ 2015-11-02 1:30 ` Boqun Feng
2015-11-02 2:28 ` Paul E. McKenney
` (2 more replies)
2015-11-02 2:26 ` [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics " Paul E. McKenney
` (2 subsequent siblings)
3 siblings, 3 replies; 8+ messages in thread
From: Boqun Feng @ 2015-11-02 1:30 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Peter Zijlstra, Ingo Molnar, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Thomas Gleixner, Will Deacon,
Paul E. McKenney, Boqun Feng, stable
According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
versions all need to be fully ordered, however they are now just
RELEASE+ACQUIRE, which are not fully ordered.
So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
__{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
This patch depends on patch "powerpc: Make value-returning atomics fully
ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
Cc: <stable@vger.kernel.org> # 3.4+
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
---
arch/powerpc/include/asm/cmpxchg.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h
index ad6263c..d1a8d93 100644
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -18,12 +18,12 @@ __xchg_u32(volatile void *p, unsigned long val)
unsigned long prev;
__asm__ __volatile__(
- PPC_RELEASE_BARRIER
+ PPC_ATOMIC_ENTRY_BARRIER
"1: lwarx %0,0,%2 \n"
PPC405_ERR77(0,%2)
" stwcx. %3,0,%2 \n\
bne- 1b"
- PPC_ACQUIRE_BARRIER
+ PPC_ATOMIC_EXIT_BARRIER
: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
: "r" (p), "r" (val)
: "cc", "memory");
@@ -61,12 +61,12 @@ __xchg_u64(volatile void *p, unsigned long val)
unsigned long prev;
__asm__ __volatile__(
- PPC_RELEASE_BARRIER
+ PPC_ATOMIC_ENTRY_BARRIER
"1: ldarx %0,0,%2 \n"
PPC405_ERR77(0,%2)
" stdcx. %3,0,%2 \n\
bne- 1b"
- PPC_ACQUIRE_BARRIER
+ PPC_ATOMIC_EXIT_BARRIER
: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
: "r" (p), "r" (val)
: "cc", "memory");
@@ -151,14 +151,14 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
unsigned int prev;
__asm__ __volatile__ (
- PPC_RELEASE_BARRIER
+ PPC_ATOMIC_ENTRY_BARRIER
"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
cmpw 0,%0,%3\n\
bne- 2f\n"
PPC405_ERR77(0,%2)
" stwcx. %4,0,%2\n\
bne- 1b"
- PPC_ACQUIRE_BARRIER
+ PPC_ATOMIC_EXIT_BARRIER
"\n\
2:"
: "=&r" (prev), "+m" (*p)
@@ -197,13 +197,13 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
unsigned long prev;
__asm__ __volatile__ (
- PPC_RELEASE_BARRIER
+ PPC_ATOMIC_ENTRY_BARRIER
"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
cmpd 0,%0,%3\n\
bne- 2f\n\
stdcx. %4,0,%2\n\
bne- 1b"
- PPC_ACQUIRE_BARRIER
+ PPC_ATOMIC_EXIT_BARRIER
"\n\
2:"
: "=&r" (prev), "+m" (*p)
--
2.6.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered
2015-11-02 1:30 [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
@ 2015-11-02 2:26 ` Paul E. McKenney
2015-11-02 9:14 ` Peter Zijlstra
2015-12-15 11:27 ` [powerpc/next, " Michael Ellerman
3 siblings, 0 replies; 8+ messages in thread
From: Paul E. McKenney @ 2015-11-02 2:26 UTC (permalink / raw)
To: Boqun Feng
Cc: linux-kernel, linuxppc-dev, Peter Zijlstra, Ingo Molnar,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Thomas Gleixner, Will Deacon, stable
On Mon, Nov 02, 2015 at 09:30:31AM +0800, Boqun Feng wrote:
> According to memory-barriers.txt:
>
> > Any atomic operation that modifies some state in memory and returns
> > information about the state (old or new) implies an SMP-conditional
> > general memory barrier (smp_mb()) on each side of the actual
> > operation ...
>
> Which mean these operations should be fully ordered. However on PPC,
> PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
> which is currently "lwsync" if SMP=y. The leading "lwsync" can not
> guarantee fully ordered atomics, according to Paul Mckenney:
>
> https://lkml.org/lkml/2015/10/14/970
>
> To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
> the fully-ordered semantics.
>
> This also makes futex atomics fully ordered, which can avoid possible
> memory ordering problems if userspace code relies on futex system call
> for fully ordered semantics.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> ---
> These two are separated and splited from the patchset of powerpc atomic
> variants implementation, whose link is:
>
> https://lkml.org/lkml/2015/10/26/141
>
> Based on next branch of powerpc tree, tested by 0day.
>
> arch/powerpc/include/asm/synch.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
> index e682a71..c508686 100644
> --- a/arch/powerpc/include/asm/synch.h
> +++ b/arch/powerpc/include/asm/synch.h
> @@ -44,7 +44,7 @@ static inline void isync(void)
> MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
> #define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
> #define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
> -#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n"
> +#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n"
> #define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
> #else
> #define PPC_ACQUIRE_BARRIER
> --
> 2.6.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
@ 2015-11-02 2:28 ` Paul E. McKenney
2015-11-02 9:14 ` Peter Zijlstra
2015-12-15 11:27 ` [powerpc/next, " Michael Ellerman
2 siblings, 0 replies; 8+ messages in thread
From: Paul E. McKenney @ 2015-11-02 2:28 UTC (permalink / raw)
To: Boqun Feng
Cc: linux-kernel, linuxppc-dev, Peter Zijlstra, Ingo Molnar,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Thomas Gleixner, Will Deacon, stable
On Mon, Nov 02, 2015 at 09:30:32AM +0800, Boqun Feng wrote:
> According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
> versions all need to be fully ordered, however they are now just
> RELEASE+ACQUIRE, which are not fully ordered.
>
> So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
> PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
> __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
> of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
> b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
>
> This patch depends on patch "powerpc: Make value-returning atomics fully
> ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/cmpxchg.h | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h
> index ad6263c..d1a8d93 100644
> --- a/arch/powerpc/include/asm/cmpxchg.h
> +++ b/arch/powerpc/include/asm/cmpxchg.h
> @@ -18,12 +18,12 @@ __xchg_u32(volatile void *p, unsigned long val)
> unsigned long prev;
>
> __asm__ __volatile__(
> - PPC_RELEASE_BARRIER
> + PPC_ATOMIC_ENTRY_BARRIER
> "1: lwarx %0,0,%2 \n"
> PPC405_ERR77(0,%2)
> " stwcx. %3,0,%2 \n\
> bne- 1b"
> - PPC_ACQUIRE_BARRIER
> + PPC_ATOMIC_EXIT_BARRIER
> : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
> : "r" (p), "r" (val)
> : "cc", "memory");
> @@ -61,12 +61,12 @@ __xchg_u64(volatile void *p, unsigned long val)
> unsigned long prev;
>
> __asm__ __volatile__(
> - PPC_RELEASE_BARRIER
> + PPC_ATOMIC_ENTRY_BARRIER
> "1: ldarx %0,0,%2 \n"
> PPC405_ERR77(0,%2)
> " stdcx. %3,0,%2 \n\
> bne- 1b"
> - PPC_ACQUIRE_BARRIER
> + PPC_ATOMIC_EXIT_BARRIER
> : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
> : "r" (p), "r" (val)
> : "cc", "memory");
> @@ -151,14 +151,14 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
> unsigned int prev;
>
> __asm__ __volatile__ (
> - PPC_RELEASE_BARRIER
> + PPC_ATOMIC_ENTRY_BARRIER
> "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
> cmpw 0,%0,%3\n\
> bne- 2f\n"
> PPC405_ERR77(0,%2)
> " stwcx. %4,0,%2\n\
> bne- 1b"
> - PPC_ACQUIRE_BARRIER
> + PPC_ATOMIC_EXIT_BARRIER
> "\n\
> 2:"
> : "=&r" (prev), "+m" (*p)
> @@ -197,13 +197,13 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
> unsigned long prev;
>
> __asm__ __volatile__ (
> - PPC_RELEASE_BARRIER
> + PPC_ATOMIC_ENTRY_BARRIER
> "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
> cmpd 0,%0,%3\n\
> bne- 2f\n\
> stdcx. %4,0,%2\n\
> bne- 1b"
> - PPC_ACQUIRE_BARRIER
> + PPC_ATOMIC_EXIT_BARRIER
> "\n\
> 2:"
> : "=&r" (prev), "+m" (*p)
> --
> 2.6.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered
2015-11-02 1:30 [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
2015-11-02 2:26 ` [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics " Paul E. McKenney
@ 2015-11-02 9:14 ` Peter Zijlstra
2015-12-15 11:27 ` [powerpc/next, " Michael Ellerman
3 siblings, 0 replies; 8+ messages in thread
From: Peter Zijlstra @ 2015-11-02 9:14 UTC (permalink / raw)
To: Boqun Feng
Cc: linux-kernel, linuxppc-dev, Ingo Molnar, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Thomas Gleixner, Will Deacon,
Paul E. McKenney, stable
On Mon, Nov 02, 2015 at 09:30:31AM +0800, Boqun Feng wrote:
> According to memory-barriers.txt:
>
> > Any atomic operation that modifies some state in memory and returns
> > information about the state (old or new) implies an SMP-conditional
> > general memory barrier (smp_mb()) on each side of the actual
> > operation ...
>
> Which mean these operations should be fully ordered. However on PPC,
> PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
> which is currently "lwsync" if SMP=y. The leading "lwsync" can not
> guarantee fully ordered atomics, according to Paul Mckenney:
>
> https://lkml.org/lkml/2015/10/14/970
>
> To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
> the fully-ordered semantics.
>
> This also makes futex atomics fully ordered, which can avoid possible
> memory ordering problems if userspace code relies on futex system call
> for fully ordered semantics.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
2015-11-02 2:28 ` Paul E. McKenney
@ 2015-11-02 9:14 ` Peter Zijlstra
2015-12-15 11:27 ` [powerpc/next, " Michael Ellerman
2 siblings, 0 replies; 8+ messages in thread
From: Peter Zijlstra @ 2015-11-02 9:14 UTC (permalink / raw)
To: Boqun Feng
Cc: linux-kernel, linuxppc-dev, Ingo Molnar, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Thomas Gleixner, Will Deacon,
Paul E. McKenney, stable
On Mon, Nov 02, 2015 at 09:30:32AM +0800, Boqun Feng wrote:
> According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
> versions all need to be fully ordered, however they are now just
> RELEASE+ACQUIRE, which are not fully ordered.
>
> So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
> PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
> __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
> of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
> b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
>
> This patch depends on patch "powerpc: Make value-returning atomics fully
> ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [powerpc/next, 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
2015-11-02 2:28 ` Paul E. McKenney
2015-11-02 9:14 ` Peter Zijlstra
@ 2015-12-15 11:27 ` Michael Ellerman
2 siblings, 0 replies; 8+ messages in thread
From: Michael Ellerman @ 2015-12-15 11:27 UTC (permalink / raw)
To: Boqun Feng, linux-kernel, linuxppc-dev
Cc: Peter Zijlstra, Boqun Feng, Will Deacon, stable, Paul Mackerras,
Thomas Gleixner, Paul E. McKenney, Ingo Molnar
On Mon, 2015-02-11 at 01:30:32 UTC, Boqun Feng wrote:
> According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
> versions all need to be fully ordered, however they are now just
> RELEASE+ACQUIRE, which are not fully ordered.
>
> So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
> PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
> __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
> of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
> b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
>
> This patch depends on patch "powerpc: Make value-returning atomics fully
> ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
> Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/81d7a3294de7e9828310bbf9
cheers
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [powerpc/next, 1/2] powerpc: Make value-returning atomics fully ordered
2015-11-02 1:30 [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng
` (2 preceding siblings ...)
2015-11-02 9:14 ` Peter Zijlstra
@ 2015-12-15 11:27 ` Michael Ellerman
3 siblings, 0 replies; 8+ messages in thread
From: Michael Ellerman @ 2015-12-15 11:27 UTC (permalink / raw)
To: Boqun Feng, linux-kernel, linuxppc-dev
Cc: Peter Zijlstra, Boqun Feng, Will Deacon, stable, Paul Mackerras,
Thomas Gleixner, Paul E. McKenney, Ingo Molnar
On Mon, 2015-02-11 at 01:30:31 UTC, Boqun Feng wrote:
> According to memory-barriers.txt:
>
> > Any atomic operation that modifies some state in memory and returns
> > information about the state (old or new) implies an SMP-conditional
> > general memory barrier (smp_mb()) on each side of the actual
> > operation ...
>
> Which mean these operations should be fully ordered. However on PPC,
> PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
> which is currently "lwsync" if SMP=y. The leading "lwsync" can not
> guarantee fully ordered atomics, according to Paul Mckenney:
>
> https://lkml.org/lkml/2015/10/14/970
>
> To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
> the fully-ordered semantics.
>
> This also makes futex atomics fully ordered, which can avoid possible
> memory ordering problems if userspace code relies on futex system call
> for fully ordered semantics.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
> Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/49e9cf3f0c04bf76ffa59242
cheers
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-12-15 11:27 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2015-11-02 1:30 [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng
2015-11-02 1:30 ` [PATCH powerpc/next 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions " Boqun Feng
2015-11-02 2:28 ` Paul E. McKenney
2015-11-02 9:14 ` Peter Zijlstra
2015-12-15 11:27 ` [powerpc/next, " Michael Ellerman
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