* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
@ 2015-12-22 7:22 shengjiangwu
2015-12-22 7:24 ` Chin Liang See
2015-12-22 20:18 ` Marek Vasut
0 siblings, 2 replies; 11+ messages in thread
From: shengjiangwu @ 2015-12-22 7:22 UTC (permalink / raw)
To: u-boot
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++------------
board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..442b1e0 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
1, /* MIXED1IO15 */
1, /* MIXED1IO16 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..9e336e3 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
2015-12-22 7:22 [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board shengjiangwu
@ 2015-12-22 7:24 ` Chin Liang See
2015-12-22 20:18 ` Marek Vasut
1 sibling, 0 replies; 11+ messages in thread
From: Chin Liang See @ 2015-12-22 7:24 UTC (permalink / raw)
To: u-boot
On Tue, 2015-12-22 at 15:22 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> ---
> board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++--
> ----------
> board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
> 2 files changed, 15 insertions(+), 15 deletions(-)
>
>
Acked-by: Chin Liang See <clsee@altera.com>
Thanks
Chin Liang
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
2015-12-22 7:22 [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board shengjiangwu
2015-12-22 7:24 ` Chin Liang See
@ 2015-12-22 20:18 ` Marek Vasut
1 sibling, 0 replies; 11+ messages in thread
From: Marek Vasut @ 2015-12-22 20:18 UTC (permalink / raw)
To: u-boot
On Tuesday, December 22, 2015 at 08:22:02 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Applied, thanks.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
@ 2015-12-22 7:21 圣江 吴
0 siblings, 0 replies; 11+ messages in thread
From: 圣江 吴 @ 2015-12-22 7:21 UTC (permalink / raw)
To: u-boot
Hi all,
I have to resend a new patch, please have a check. Thanks
Best Regards
Shengjiang Wu
On Dec 21, 2015, at 11:20 PM, shengjiangwu <shengjiangwu@icloud.com> wrote:
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++------------
board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..442b1e0 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
?0, /* GENERALIO29 */
?0, /* GENERALIO30 */
?0, /* GENERALIO31 */
- ?0, /* MIXED1IO0 */
- ? ? ?1, /* MIXED1IO1 */
- ? ? ?1, /* MIXED1IO2 */
- ? ? ?1, /* MIXED1IO3 */
- ? ? ?1, /* MIXED1IO4 */
- ? ? ?0, /* MIXED1IO5 */
- ? ? ?0, /* MIXED1IO6 */
- ? ? ?0, /* MIXED1IO7 */
- ? ? ?1, /* MIXED1IO8 */
- ? ? ?1, /* MIXED1IO9 */
- ? ? ?1, /* MIXED1IO10 */
- ? ?1, /* MIXED1IO11 */
- ? ? ? ?0, /* MIXED1IO12 */
- ? ? ? ?0, /* MIXED1IO13 */
+ ? ? ? ?2, /* MIXED1IO0 */
+ ?2, /* MIXED1IO1 */
+ ? ? ?2, /* MIXED1IO2 */
+ ? ? ?2, /* MIXED1IO3 */
+ ? ? ?2, /* MIXED1IO4 */
+ ? ? ?2, /* MIXED1IO5 */
+ ? ? ?2, /* MIXED1IO6 */
+ ? ? ?2, /* MIXED1IO7 */
+ ? ? ?2, /* MIXED1IO8 */
+ ? ? ?2, /* MIXED1IO9 */
+ ? ? ?2, /* MIXED1IO10 */
+ ? ?2, /* MIXED1IO11 */
+ ? ? ? ?2, /* MIXED1IO12 */
+ ? ? ? ?2, /* MIXED1IO13 */
? ? ? ?0, /* MIXED1IO14 */
? ? ? ?1, /* MIXED1IO15 */
? ? ? ?1, /* MIXED1IO16 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..9e336e3 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread[parent not found: <d2ada9b7-2c4d-48e2-a338-79bce558bcdb@me.com>]
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
[not found] <d2ada9b7-2c4d-48e2-a338-79bce558bcdb@me.com>
@ 2015-12-18 12:35 ` Marek Vasut
0 siblings, 0 replies; 11+ messages in thread
From: Marek Vasut @ 2015-12-18 12:35 UTC (permalink / raw)
To: u-boot
On Friday, December 18, 2015 at 07:36:28 AM, ?? ? wrote:
> Hi Marek Vasut,
Hi,
> I'm not sure if the format is correct, I don't know why patch is plain text
> instead of a .patch file. Could you please help to review? Thanks.
please keep the list on Cc and do not top-post. It seems your mailer is
corrupting patches, it replaces tabs with spaces. The established procedure
is to submit patches inline, so they can be reviewed ; patch file does not
allow that.
> Best Regards
> ShengjiangWu
>
> On Dec 17, 2015, at 10:18 PM, shengjiangwu <shengjiangwu@icloud.com> wrote:
>
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> ---
> board/altera/cyclone5-socdk/qts/pinmux_config.h | 28
> +++++++++++------------ board/altera/cyclone5-socdk/qts/pll_config.h | 4
> ++--
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0
> 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
> 0, /* GENERALIO29 */
> 0, /* GENERALIO30 */
> 0, /* GENERALIO31 */
> - 0, /* MIXED1IO0 */
> - 1, /* MIXED1IO1 */
> - 1, /* MIXED1IO2 */
> - 1, /* MIXED1IO3 */
> - 1, /* MIXED1IO4 */
> - 0, /* MIXED1IO5 */
> - 0, /* MIXED1IO6 */
> - 0, /* MIXED1IO7 */
> - 1, /* MIXED1IO8 */
> - 1, /* MIXED1IO9 */
> - 1, /* MIXED1IO10 */
> - 1, /* MIXED1IO11 */
> - 0, /* MIXED1IO12 */
> - 0, /* MIXED1IO13 */
> + 2, /* MIXED1IO0 */
> + 2, /* MIXED1IO1 */
> + 2, /* MIXED1IO2 */
> + 2, /* MIXED1IO3 */
> + 2, /* MIXED1IO4 */
> + 2, /* MIXED1IO5 */
> + 2, /* MIXED1IO6 */
> + 2, /* MIXED1IO7 */
> + 2, /* MIXED1IO8 */
> + 2, /* MIXED1IO9 */
> + 2, /* MIXED1IO10 */
> + 2, /* MIXED1IO11 */
> + 2, /* MIXED1IO12 */
> + 2, /* MIXED1IO13 */
> 0, /* MIXED1IO14 */
> 1, /* MIXED1IO15 */
> 1, /* MIXED1IO16 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..42905f4
> 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -31,7 +31,7 @@
> #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
> #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> @@ -65,7 +65,7 @@
> #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
> #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
> #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
> #define CONFIG_HPS_CLK_NAND_HZ 50000000
> #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
@ 2015-12-18 7:55 圣江 吴
2015-12-18 8:06 ` Chin Liang See
0 siblings, 1 reply; 11+ messages in thread
From: 圣江 吴 @ 2015-12-18 7:55 UTC (permalink / raw)
To: u-boot
On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee@altera.com> wrote:
Hi Shengjiang,
On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Thanks for the patch.
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++--
----------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..442b1e0 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
? ? ? ?0, /* GENERALIO29 */
? ? ?0, /* GENERALIO30 */
?0, /* GENERALIO31 */
- ?0, /* MIXED1IO0 */
- ? ? ?1, /* MIXED1IO1 */
- ? ? ?1, /* MIXED1IO2 */
- ? ? ?1, /* MIXED1IO3 */
- ? ? ?1, /* MIXED1IO4 */
- ? ? ?0, /* MIXED1IO5 */
- ? ? ?0, /* MIXED1IO6 */
- ? ? ?0, /* MIXED1IO7 */
- ? ? ?1, /* MIXED1IO8 */
- ? ? ?1, /* MIXED1IO9 */
- ? ? ?1, /* MIXED1IO10 */
- ? ?1, /* MIXED1IO11 */
- ? ? ? ?0, /* MIXED1IO12 */
- ? ? ? ?0, /* MIXED1IO13 */
+ ? ? ? ?2, /* MIXED1IO0 */
+ ?2, /* MIXED1IO1 */
+ ? ? ?2, /* MIXED1IO2 */
+ ? ? ?2, /* MIXED1IO3 */
+ ? ? ?2, /* MIXED1IO4 */
+ ? ? ?2, /* MIXED1IO5 */
+ ? ? ?2, /* MIXED1IO6 */
+ ? ? ?2, /* MIXED1IO7 */
+ ? ? ?2, /* MIXED1IO8 */
+ ? ? ?2, /* MIXED1IO9 */
+ ? ? ?2, /* MIXED1IO10 */
+ ? ?2, /* MIXED1IO11 */
+ ? ? ? ?2, /* MIXED1IO12 */
+ ? ? ? ?2, /* MIXED1IO13 */
? ? ? ?0, /* MIXED1IO14 */
? ? ? ?1, /* MIXED1IO15 */
? ? ? ?1, /* MIXED1IO16 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..42905f4 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
@@ -65,7 +65,7 @@
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
I believe the EMAC1 clock is still 250MHz which result of 25MHz *
(79+1) / (1+1) / (3+1).
Thanks
Chin Liang
?
Thanks for your comments, then I will?restore it CONFIG_HPS_CLK_EMAC1_HZ as?250000000
Shengjiangwu
?
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
2015-12-18 7:55 圣江 吴
@ 2015-12-18 8:06 ` Chin Liang See
0 siblings, 0 replies; 11+ messages in thread
From: Chin Liang See @ 2015-12-18 8:06 UTC (permalink / raw)
To: u-boot
On Fri, 2015-12-18 at 07:55 +0000, ?? ? wrote:
>
>
> On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee@altera.com>
> wrote:
>
> > Hi Shengjiang,
> >
> > On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> > > Updated pinmux group MIXED1IO[0-13] for RGMII1.
> > > Updated EMAC1 clock.
> > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > Cc: Chin Liang See <clsee@altera.com>
> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > Cc: Pavel Machek <pavel@denx.de>
> > > Cc: Marek Vasut <marex@denx.de>
> > > Cc: Stefan Roese <sr@denx.de>
> > Thanks for the patch.
> >
> > > ---
> > > board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++-
> > > -
> > > ----------
> > > board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
> > > 2 files changed, 16 insertions(+), 16 deletions(-)
> > > diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > index 33cf1fd..442b1e0 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
> > > 0, /* GENERALIO29 */
> > > 0, /* GENERALIO30 */
> > > 0, /* GENERALIO31 */
> > > - 0, /* MIXED1IO0 */
> > > - 1, /* MIXED1IO1 */
> > > - 1, /* MIXED1IO2 */
> > > - 1, /* MIXED1IO3 */
> > > - 1, /* MIXED1IO4 */
> > > - 0, /* MIXED1IO5 */
> > > - 0, /* MIXED1IO6 */
> > > - 0, /* MIXED1IO7 */
> > > - 1, /* MIXED1IO8 */
> > > - 1, /* MIXED1IO9 */
> > > - 1, /* MIXED1IO10 */
> > > - 1, /* MIXED1IO11 */
> > > - 0, /* MIXED1IO12 */
> > > - 0, /* MIXED1IO13 */
> > > + 2, /* MIXED1IO0 */
> > > + 2, /* MIXED1IO1 */
> > > + 2, /* MIXED1IO2 */
> > > + 2, /* MIXED1IO3 */
> > > + 2, /* MIXED1IO4 */
> > > + 2, /* MIXED1IO5 */
> > > + 2, /* MIXED1IO6 */
> > > + 2, /* MIXED1IO7 */
> > > + 2, /* MIXED1IO8 */
> > > + 2, /* MIXED1IO9 */
> > > + 2, /* MIXED1IO10 */
> > > + 2, /* MIXED1IO11 */
> > > + 2, /* MIXED1IO12 */
> > > + 2, /* MIXED1IO13 */
> > > 0, /* MIXED1IO14 */
> > > 1, /* MIXED1IO15 */
> > > 1, /* MIXED1IO16 */
> > > diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > index 3d621ed..42905f4 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > @@ -31,7 +31,7 @@
> > > #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
> > > #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> > > #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> > > -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> > > +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> > > #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> > > #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> > > #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> > > @@ -65,7 +65,7 @@
> > > #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> > > #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
> > > #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> > > -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> > > +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
> > I believe the EMAC1 clock is still 250MHz which result of 25MHz *
> > (79+1) / (1+1) / (3+1).
> >
> > Thanks
> > Chin Liang
>
> Thanks for your comments, then I will restore it
> CONFIG_HPS_CLK_EMAC1_HZ as 250000000
> Shengjiangwu
>
Thanks, looking for your v2 patch then
Chin Liang
>
> >
> > > #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
> > > #define CONFIG_HPS_CLK_NAND_HZ 50000000
> > > #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
@ 2015-12-18 7:39 圣江 吴
2015-12-18 7:48 ` Chin Liang See
0 siblings, 1 reply; 11+ messages in thread
From: 圣江 吴 @ 2015-12-18 7:39 UTC (permalink / raw)
To: u-boot
Hi Chin,
I will check it.
Best Regards
ShengjiangWu
On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee@altera.com> wrote:
Hi Shengjiang,
On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Thanks for the patch.
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++--
----------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..442b1e0 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
? ? ? ?0, /* GENERALIO29 */
? ? ?0, /* GENERALIO30 */
?0, /* GENERALIO31 */
- ?0, /* MIXED1IO0 */
- ? ? ?1, /* MIXED1IO1 */
- ? ? ?1, /* MIXED1IO2 */
- ? ? ?1, /* MIXED1IO3 */
- ? ? ?1, /* MIXED1IO4 */
- ? ? ?0, /* MIXED1IO5 */
- ? ? ?0, /* MIXED1IO6 */
- ? ? ?0, /* MIXED1IO7 */
- ? ? ?1, /* MIXED1IO8 */
- ? ? ?1, /* MIXED1IO9 */
- ? ? ?1, /* MIXED1IO10 */
- ? ?1, /* MIXED1IO11 */
- ? ? ? ?0, /* MIXED1IO12 */
- ? ? ? ?0, /* MIXED1IO13 */
+ ? ? ? ?2, /* MIXED1IO0 */
+ ?2, /* MIXED1IO1 */
+ ? ? ?2, /* MIXED1IO2 */
+ ? ? ?2, /* MIXED1IO3 */
+ ? ? ?2, /* MIXED1IO4 */
+ ? ? ?2, /* MIXED1IO5 */
+ ? ? ?2, /* MIXED1IO6 */
+ ? ? ?2, /* MIXED1IO7 */
+ ? ? ?2, /* MIXED1IO8 */
+ ? ? ?2, /* MIXED1IO9 */
+ ? ? ?2, /* MIXED1IO10 */
+ ? ?2, /* MIXED1IO11 */
+ ? ? ? ?2, /* MIXED1IO12 */
+ ? ? ? ?2, /* MIXED1IO13 */
? ? ? ?0, /* MIXED1IO14 */
? ? ? ?1, /* MIXED1IO15 */
? ? ? ?1, /* MIXED1IO16 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..42905f4 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
@@ -65,7 +65,7 @@
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
I believe the EMAC1 clock is still 250MHz which result of 25MHz *
(79+1) / (1+1) / (3+1).
Thanks
Chin Liang
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
2015-12-18 7:39 圣江 吴
@ 2015-12-18 7:48 ` Chin Liang See
0 siblings, 0 replies; 11+ messages in thread
From: Chin Liang See @ 2015-12-18 7:48 UTC (permalink / raw)
To: u-boot
Hi Shengjiangm
On Fri, 2015-12-18 at 07:39 +0000, ?? ? wrote:
> Hi Chin,
>
> I will check it.
>
> Best Regards
> ShengjiangWu
>
To ease reading, we will put comment below previous comments.
In the mean time, opensource will always use plaintext email. FYI, I
use evoluation to handle email communication instead of company default
outlook. Or you can use gmail if you email software don't support
plaintext.
Thanks
Chin Liang
> On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee@altera.com>
> wrote:
>
> > Hi Shengjiang,
> >
> > On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> > > Updated pinmux group MIXED1IO[0-13] for RGMII1.
> > > Updated EMAC1 clock.
> > > Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> > > Cc: Chin Liang See <clsee@altera.com>
> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > Cc: Dinh Nguyen <dinh.linux@gmail.com>
> > > Cc: Pavel Machek <pavel@denx.de>
> > > Cc: Marek Vasut <marex@denx.de>
> > > Cc: Stefan Roese <sr@denx.de>
> > Thanks for the patch.
> >
> > > ---
> > > board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++-
> > > -
> > > ----------
> > > board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
> > > 2 files changed, 16 insertions(+), 16 deletions(-)
> > > diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > index 33cf1fd..442b1e0 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
> > > 0, /* GENERALIO29 */
> > > 0, /* GENERALIO30 */
> > > 0, /* GENERALIO31 */
> > > - 0, /* MIXED1IO0 */
> > > - 1, /* MIXED1IO1 */
> > > - 1, /* MIXED1IO2 */
> > > - 1, /* MIXED1IO3 */
> > > - 1, /* MIXED1IO4 */
> > > - 0, /* MIXED1IO5 */
> > > - 0, /* MIXED1IO6 */
> > > - 0, /* MIXED1IO7 */
> > > - 1, /* MIXED1IO8 */
> > > - 1, /* MIXED1IO9 */
> > > - 1, /* MIXED1IO10 */
> > > - 1, /* MIXED1IO11 */
> > > - 0, /* MIXED1IO12 */
> > > - 0, /* MIXED1IO13 */
> > > + 2, /* MIXED1IO0 */
> > > + 2, /* MIXED1IO1 */
> > > + 2, /* MIXED1IO2 */
> > > + 2, /* MIXED1IO3 */
> > > + 2, /* MIXED1IO4 */
> > > + 2, /* MIXED1IO5 */
> > > + 2, /* MIXED1IO6 */
> > > + 2, /* MIXED1IO7 */
> > > + 2, /* MIXED1IO8 */
> > > + 2, /* MIXED1IO9 */
> > > + 2, /* MIXED1IO10 */
> > > + 2, /* MIXED1IO11 */
> > > + 2, /* MIXED1IO12 */
> > > + 2, /* MIXED1IO13 */
> > > 0, /* MIXED1IO14 */
> > > 1, /* MIXED1IO15 */
> > > 1, /* MIXED1IO16 */
> > > diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > index 3d621ed..42905f4 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > @@ -31,7 +31,7 @@
> > > #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
> > > #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> > > #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> > > -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> > > +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> > > #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> > > #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> > > #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> > > @@ -65,7 +65,7 @@
> > > #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> > > #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
> > > #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> > > -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> > > +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
> > I believe the EMAC1 clock is still 250MHz which result of 25MHz *
> > (79+1) / (1+1) / (3+1).
> >
> > Thanks
> > Chin Liang
> >
> > > #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
> > > #define CONFIG_HPS_CLK_NAND_HZ 50000000
> > > #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
@ 2015-12-18 7:13 shengjiangwu
2015-12-18 7:27 ` Chin Liang See
0 siblings, 1 reply; 11+ messages in thread
From: shengjiangwu @ 2015-12-18 7:13 UTC (permalink / raw)
To: u-boot
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++------------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..442b1e0 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
1, /* MIXED1IO15 */
1, /* MIXED1IO16 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..42905f4 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
@@ -65,7 +65,7 @@
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
2015-12-18 7:13 shengjiangwu
@ 2015-12-18 7:27 ` Chin Liang See
0 siblings, 0 replies; 11+ messages in thread
From: Chin Liang See @ 2015-12-18 7:27 UTC (permalink / raw)
To: u-boot
Hi Shengjiang,
On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
>
> Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
Thanks for the patch.
> ---
> board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++--
> ----------
> board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 33cf1fd..442b1e0 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
> 0, /* GENERALIO29 */
> 0, /* GENERALIO30 */
> 0, /* GENERALIO31 */
> - 0, /* MIXED1IO0 */
> - 1, /* MIXED1IO1 */
> - 1, /* MIXED1IO2 */
> - 1, /* MIXED1IO3 */
> - 1, /* MIXED1IO4 */
> - 0, /* MIXED1IO5 */
> - 0, /* MIXED1IO6 */
> - 0, /* MIXED1IO7 */
> - 1, /* MIXED1IO8 */
> - 1, /* MIXED1IO9 */
> - 1, /* MIXED1IO10 */
> - 1, /* MIXED1IO11 */
> - 0, /* MIXED1IO12 */
> - 0, /* MIXED1IO13 */
> + 2, /* MIXED1IO0 */
> + 2, /* MIXED1IO1 */
> + 2, /* MIXED1IO2 */
> + 2, /* MIXED1IO3 */
> + 2, /* MIXED1IO4 */
> + 2, /* MIXED1IO5 */
> + 2, /* MIXED1IO6 */
> + 2, /* MIXED1IO7 */
> + 2, /* MIXED1IO8 */
> + 2, /* MIXED1IO9 */
> + 2, /* MIXED1IO10 */
> + 2, /* MIXED1IO11 */
> + 2, /* MIXED1IO12 */
> + 2, /* MIXED1IO13 */
> 0, /* MIXED1IO14 */
> 1, /* MIXED1IO15 */
> 1, /* MIXED1IO16 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 3d621ed..42905f4 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -31,7 +31,7 @@
> #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
> #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> @@ -65,7 +65,7 @@
> #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
> #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
I believe the EMAC1 clock is still 250MHz which result of 25MHz *
(79+1) / (1+1) / (3+1).
Thanks
Chin Liang
> #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
> #define CONFIG_HPS_CLK_NAND_HZ 50000000
> #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-12-22 20:18 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-22 7:22 [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board shengjiangwu
2015-12-22 7:24 ` Chin Liang See
2015-12-22 20:18 ` Marek Vasut
-- strict thread matches above, loose matches on Subject: below --
2015-12-22 7:21 圣江 吴
[not found] <d2ada9b7-2c4d-48e2-a338-79bce558bcdb@me.com>
2015-12-18 12:35 ` Marek Vasut
2015-12-18 7:55 圣江 吴
2015-12-18 8:06 ` Chin Liang See
2015-12-18 7:39 圣江 吴
2015-12-18 7:48 ` Chin Liang See
2015-12-18 7:13 shengjiangwu
2015-12-18 7:27 ` Chin Liang See
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