[PATCH v4 00/13] ASoC: Intel: Skylake: Update to SKL driver

[PATCH v4 00/13] ASoC: Intel: Skylake: Update to SKL driver

[Vinod Koul]

This update bring in new APIs in core and usage of those in SKL driver.

The series is broadly of three parts
 - first two are fixes on the driver
 - then we add DMA resume capability in HDA core and use it to save restore
   DMA link values and add DMA resume capability in driver
 - lastly, we add support for MISCBDCGE configuration in core and use it
   while resetting and also for phrase detection per HW recommendation

This should be merged thru ASoC tree due to obvious dependencies. Takashi
would need your ack on core patches

change in v4:
 - fix the circular depends on two ko's

change is v3:
 - fix the missing export symbol, reported by lkp

changes in v2:
 - move msicbdge api to driver and as a consequence sqash into into first
   use
 - fix lkp warning

Dharageswari.R (1):
  ASoC: Intel: Skylake: Use CGCTL.MISCBDCGE for Phrase detection
    notification

Jayachandran B (2):
  ALSA: hdac: Increase timeout value for link power check
  ASoC: Intel: Skylake: fix reset controller sequencing

Jeeja KP (8):
  ASoC: Intel: Skylake: Clear stream registers before stream setup
  ASoC: Intel: Skylake: Fix to set pipe state to invalid when deleting
  ALSA: hdac: Add support for hda DMA Resume capability
  ALSA: hdac: couple the hda DMA stream in cleanup
  ASoC: Intel: Skylake: enable interrupt as wake source in active
    suspend
  ASoC: Intel: Skylake: Add DMA resume position in Trigger
    resume/suspend
  ASoC: Intel: Skylake: Reconfigure Link stream on suspend/resume
  ASoC: Intel: Skylake: Add Resume capability in PCM info.

Vinod Koul (2):
  ALSA: hdac: add snd_hdac_ext_bus_link_power_up_all
  ASoC: Intel: Skylake: manage link power in active suspend

 include/sound/hda_register.h            |  9 +++++
 include/sound/hdaudio_ext.h             | 15 +++++++
 sound/hda/ext/hdac_ext_controller.c     | 29 ++++++++++++-
 sound/hda/ext/hdac_ext_stream.c         | 72 +++++++++++++++++++++++++++++++++
 sound/soc/intel/skylake/skl-messages.c  |  2 +
 sound/soc/intel/skylake/skl-pcm.c       | 56 ++++++++++++++++++++-----
 sound/soc/intel/skylake/skl-sst-cldma.c | 38 ++++++++++-------
 sound/soc/intel/skylake/skl-sst-ipc.c   | 15 +++++++
 sound/soc/intel/skylake/skl-sst-ipc.h   |  5 +++
 sound/soc/intel/skylake/skl.c           | 61 ++++++++++++++++++++++++++--
 sound/soc/intel/skylake/skl.h           |  3 ++
 11 files changed, 275 insertions(+), 30 deletions(-)

-- 
1.9.1

[PATCH v4 01/13] ASoC: Intel: Skylake: Clear stream registers before stream setup

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds clean up routine to clear the stream registers and
calls this routine before setting up stream registers.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-sst-cldma.c | 38 ++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-cldma.c b/sound/soc/intel/skylake/skl-sst-cldma.c
index 8c7e8576cba3..da2329d17f4d 100644
--- a/sound/soc/intel/skylake/skl-sst-cldma.c
+++ b/sound/soc/intel/skylake/skl-sst-cldma.c
@@ -60,6 +60,27 @@ static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
 		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
 }
 
+static void skl_cldma_stream_clear(struct sst_dsp  *ctx)
+{
+	/* make sure Run bit is cleared before setting stream register */
+	skl_cldma_stream_run(ctx, 0);
+
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
+
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
+
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
+}
+
 /* Code loader helper APIs */
 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 		struct snd_dma_buffer *dmab_data,
@@ -95,6 +116,7 @@ static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
 		struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
 		u32 count)
 {
+	skl_cldma_stream_clear(ctx);
 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
 			CL_SD_BDLPLBA(dmab_bdl->addr));
 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
@@ -137,21 +159,7 @@ static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
 {
 	skl_cldma_cleanup_spb(ctx);
-
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
-
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
-
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
+	skl_cldma_stream_clear(ctx);
 
 	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
 	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
-- 
1.9.1

[PATCH v4 02/13] ASoC: Intel: Skylake: Fix to set pipe state to invalid when deleting

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

When pipeline is deleted, set the pipeline state to invalid state.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-messages.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/soc/intel/skylake/skl-messages.c b/sound/soc/intel/skylake/skl-messages.c
index 46310d9ac008..de6dac496a0d 100644
--- a/sound/soc/intel/skylake/skl-messages.c
+++ b/sound/soc/intel/skylake/skl-messages.c
@@ -849,6 +849,8 @@ int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
 		ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id);
 		if (ret < 0)
 			dev_err(ctx->dev, "Failed to delete pipeline\n");
+
+		pipe->state = SKL_PIPE_INVALID;
 	}
 
 	return ret;
-- 
1.9.1

[PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

Skylake sports new capability of DMA resume, DRSM where we can
resume the DMA. This capability is defined by presence of
AZX_DRSM_CAP_ID.

If this capability is present, we use this capability.
So we add:

snd_hdac_ext_stream_drsm_enable() - DMA resume caps
snd_hdac_ext_stream_set_dpibr() - set the DMA position
snd_hdac_ext_stream_set_lpib() - set the lpib

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 include/sound/hda_register.h        |  9 +++++
 include/sound/hdaudio_ext.h         | 14 ++++++++
 sound/hda/ext/hdac_ext_controller.c |  6 ++++
 sound/hda/ext/hdac_ext_stream.c     | 71 +++++++++++++++++++++++++++++++++++++
 4 files changed, 100 insertions(+)

diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index 2ae8812d7b1a..28ac1f9a18ac 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -230,6 +230,15 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define AZX_MLCTL_SPA			(1<<16)
 #define AZX_MLCTL_CPA			23
 
+
+/* registers for DMA Resume Capability Structure */
+#define AZX_DRSM_CAP_ID			0x5
+#define AZX_REG_DRSM_CTL		0x4
+/* Base used to calculate the iterating register offset */
+#define AZX_DRSM_BASE			0x08
+/* Interval used to calculate the iterating register offset */
+#define AZX_DRSM_INTERVAL		0x08
+
 /*
  * helpers to read the stream position
  */
diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
index 425af0674557..f3454950ee0b 100644
--- a/include/sound/hdaudio_ext.h
+++ b/include/sound/hdaudio_ext.h
@@ -12,6 +12,7 @@
  * @spbcap: SPIB capabilities pointer
  * @mlcap: MultiLink capabilities pointer
  * @gtscap: gts capabilities pointer
+ * @drsmcap: dma resume capabilities pointer
  * @hlink_list: link list of HDA links
  */
 struct hdac_ext_bus {
@@ -23,6 +24,7 @@ struct hdac_ext_bus {
 	void __iomem *spbcap;
 	void __iomem *mlcap;
 	void __iomem *gtscap;
+	void __iomem *drsmcap;
 
 	struct list_head hlink_list;
 };
@@ -72,6 +74,9 @@ enum hdac_ext_stream_type {
  * @pplc_addr: processing pipe link stream pointer
  * @spib_addr: software position in buffers stream pointer
  * @fifo_addr: software position Max fifos stream pointer
+ * @dpibr_addr: DMA position in buffer resume pointer
+ * @dpib: DMA position in buffer
+ * @lpib: Linear position in buffer
  * @decoupled: stream host and link is decoupled
  * @link_locked: link is locked
  * @link_prepared: link is prepared
@@ -86,6 +91,10 @@ struct hdac_ext_stream {
 	void __iomem *spib_addr;
 	void __iomem *fifo_addr;
 
+	void __iomem *dpibr_addr;
+
+	u32 dpib;
+	u32 lpib;
 	bool decoupled:1;
 	bool link_locked:1;
 	bool link_prepared;
@@ -116,6 +125,11 @@ int snd_hdac_ext_stream_set_spib(struct hdac_ext_bus *ebus,
 				 struct hdac_ext_stream *stream, u32 value);
 int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_ext_bus *ebus,
 				 struct hdac_ext_stream *stream);
+void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
+				bool enable, int index);
+int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
+				struct hdac_ext_stream *stream, u32 value);
+int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value);
 
 void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hstream);
 void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hstream);
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 63215b17247c..556267e75591 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -77,6 +77,12 @@ int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *ebus)
 			ebus->spbcap = bus->remap_addr + offset;
 			break;
 
+		case AZX_DRSM_CAP_ID:
+			/* DMA resume  capability found, handler function */
+			dev_dbg(bus->dev, "Found DRSM capability\n");
+			ebus->drsmcap = bus->remap_addr + offset;
+			break;
+
 		default:
 			dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
 			break;
diff --git a/sound/hda/ext/hdac_ext_stream.c b/sound/hda/ext/hdac_ext_stream.c
index cb89ec7c8147..8f30e8836818 100644
--- a/sound/hda/ext/hdac_ext_stream.c
+++ b/sound/hda/ext/hdac_ext_stream.c
@@ -59,6 +59,10 @@ void snd_hdac_ext_stream_init(struct hdac_ext_bus *ebus,
 					AZX_SPB_MAXFIFO;
 	}
 
+	if (ebus->drsmcap)
+		stream->dpibr_addr = ebus->drsmcap + AZX_DRSM_BASE +
+					AZX_DRSM_INTERVAL * idx;
+
 	stream->decoupled = false;
 	snd_hdac_stream_init(bus, &stream->hstream, idx, direction, tag);
 }
@@ -497,3 +501,70 @@ void snd_hdac_ext_stop_streams(struct hdac_ext_bus *ebus)
 	}
 }
 EXPORT_SYMBOL_GPL(snd_hdac_ext_stop_streams);
+
+/**
+ * snd_hdac_ext_stream_drsm_enable - enable DMA resume for a stream
+ * @ebus: HD-audio ext core bus
+ * @enable: flag to enable/disable DRSM
+ * @index: stream index for which DRSM need to be enabled
+ */
+void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
+				bool enable, int index)
+{
+	u32 mask = 0;
+	u32 register_mask = 0;
+	struct hdac_bus *bus = &ebus->bus;
+
+	if (!ebus->drsmcap) {
+		dev_err(bus->dev, "Address of DRSM capability is NULL");
+		return;
+	}
+
+	mask |= (1 << index);
+
+	register_mask = readl(ebus->drsmcap + AZX_REG_SPB_SPBFCCTL);
+
+	mask |= register_mask;
+
+	if (enable)
+		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, 0, mask);
+	else
+		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_drsm_enable);
+
+/**
+ * snd_hdac_ext_stream_set_dpibr - sets the dpibr value of a stream
+ * @ebus: HD-audio ext core bus
+ * @stream: hdac_ext_stream
+ * @value: dpib value to set
+ */
+int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
+				 struct hdac_ext_stream *stream, u32 value)
+{
+	struct hdac_bus *bus = &ebus->bus;
+
+	if (!ebus->drsmcap) {
+		dev_err(bus->dev, "Address of DRSM capability is NULL");
+		return -EINVAL;
+	}
+
+	writel(value, stream->dpibr_addr);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_dpibr);
+
+/**
+ * snd_hdac_ext_stream_set_lpib - sets the lpib value of a stream
+ * @ebus: HD-audio ext core bus
+ * @stream: hdac_ext_stream
+ * @value: lpib value to set
+ */
+int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value)
+{
+	snd_hdac_stream_writel(&stream->hstream, SD_LPIB, value);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_lpib);
-- 
1.9.1

[PATCH v4 04/13] ALSA: hdac: couple the hda DMA stream in cleanup

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

A stream is by default in coupled mode, in DSP operation we move
it to decoupled mode. On cleanup HW expects that we leave it back
to default state so couple the DMA on cleanup.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/hda/ext/hdac_ext_stream.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/hda/ext/hdac_ext_stream.c b/sound/hda/ext/hdac_ext_stream.c
index 8f30e8836818..023cc4cad5c1 100644
--- a/sound/hda/ext/hdac_ext_stream.c
+++ b/sound/hda/ext/hdac_ext_stream.c
@@ -111,6 +111,7 @@ void snd_hdac_stream_free_all(struct hdac_ext_bus *ebus)
 	while (!list_empty(&bus->stream_list)) {
 		s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
 		stream = stream_to_hdac_ext_stream(s);
+		snd_hdac_ext_stream_decouple(ebus, stream, false);
 		list_del(&s->list);
 		kfree(stream);
 	}
-- 
1.9.1

[PATCH v4 05/13] ALSA: hdac: Increase timeout value for link power check

[Vinod Koul]

From: Jayachandran B <jayachandran.b@intel.com>

HW recommends 180us for worst case values for link power up
delay, so change the current delay value from 50 (150us) to 150
(450us)

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/hda/ext/hdac_ext_controller.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 556267e75591..1a55a781270d 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -246,7 +246,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
 	int mask = (1 << AZX_MLCTL_CPA);
 
 	udelay(3);
-	timeout = 50;
+	timeout = 150;
 
 	do {
 		val = readl(link->ml_addr + AZX_REG_ML_LCTL);
-- 
1.9.1

[PATCH v4 06/13] ALSA: hdac: add snd_hdac_ext_bus_link_power_up_all

[Vinod Koul]

We have an API for powering down all links, we need a similar one
for powering up links, so add for power up as well

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 include/sound/hdaudio_ext.h         |  1 +
 sound/hda/ext/hdac_ext_controller.c | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
index f3454950ee0b..07fa59237feb 100644
--- a/include/sound/hdaudio_ext.h
+++ b/include/sound/hdaudio_ext.h
@@ -147,6 +147,7 @@ struct hdac_ext_link {
 
 int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link);
 int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link);
+int snd_hdac_ext_bus_link_power_up_all(struct hdac_ext_bus *ebus);
 int snd_hdac_ext_bus_link_power_down_all(struct hdac_ext_bus *ebus);
 void snd_hdac_ext_link_set_stream_id(struct hdac_ext_link *link,
 				 int stream);
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 1a55a781270d..548cc1e4114b 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -288,6 +288,27 @@ int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down);
 
 /**
+ * snd_hdac_ext_bus_link_power_up_all -power up all hda link
+ * @ebus: HD-audio extended bus
+ */
+int snd_hdac_ext_bus_link_power_up_all(struct hdac_ext_bus *ebus)
+{
+	struct hdac_ext_link *hlink = NULL;
+	int ret;
+
+	list_for_each_entry(hlink, &ebus->hlink_list, list) {
+		snd_hdac_updatel(hlink->ml_addr,
+				AZX_REG_ML_LCTL, 0, AZX_MLCTL_SPA);
+		ret = check_hdac_link_power_active(hlink, true);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up_all);
+
+/**
  * snd_hdac_ext_bus_link_power_down_all -power down all hda link
  * @ebus: HD-audio extended bus
  */
-- 
1.9.1

[PATCH v4 07/13] ASoC: Intel: Skylake: fix reset controller sequencing

[Vinod Koul]

From: Jayachandran B <jayachandran.b@intel.com>

MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-sst-ipc.h |  5 ++++
 sound/soc/intel/skylake/skl.c         | 55 +++++++++++++++++++++++++++++++++--
 sound/soc/intel/skylake/skl.h         |  3 ++
 3 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-ipc.h b/sound/soc/intel/skylake/skl-sst-ipc.h
index 1bbcdb471cf2..d59d1ba62a43 100644
--- a/sound/soc/intel/skylake/skl-sst-ipc.h
+++ b/sound/soc/intel/skylake/skl-sst-ipc.h
@@ -55,6 +55,11 @@ struct skl_sst {
 
 	/* IPC messaging */
 	struct sst_generic_ipc ipc;
+
+	/* callback for miscbdge */
+	void (*enable_miscbdcge)(struct device *dev, bool enable);
+	/*Is CGCTL.MISCBDCGE disabled*/
+	bool miscbdcg_disabled;
 };
 
 struct skl_ipc_init_instance_msg {
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index 2c16325d1ce1..85d47cedd125 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -28,6 +28,8 @@
 #include <sound/pcm.h>
 #include "../common/sst-acpi.h"
 #include "skl.h"
+#include "skl-sst-dsp.h"
+#include "skl-sst-ipc.h"
 
 /*
  * initialize the PCI registers
@@ -58,6 +60,49 @@ static void skl_init_pci(struct skl *skl)
 	skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 }
 
+static void update_pci_dword(struct pci_dev *pci,
+			unsigned int reg, u32 mask, u32 val)
+{
+	u32 data = 0;
+
+	pci_read_config_dword(pci, reg, &data);
+	data &= ~mask;
+	data |= (val & mask);
+	pci_write_config_dword(pci, reg, data);
+}
+
+/*
+ * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
+ *
+ * @dev: device pointer
+ * @enable: enable/disable flag
+ */
+static void skl_enable_miscbdcge(struct device *dev, bool enable)
+{
+	struct pci_dev *pci = to_pci_dev(dev);
+	u32 val;
+
+	val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
+
+	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
+}
+
+/*
+ * While performing reset, controller may not come back properly causing
+ * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
+ * (init chip) and then again set CGCTL.MISCBDCGE to 1
+ */
+static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
+{
+	int ret;
+
+	skl_enable_miscbdcge(bus->dev, false);
+	ret = snd_hdac_bus_init_chip(bus, full_reset);
+	skl_enable_miscbdcge(bus->dev, true);
+
+	return ret;
+}
+
 /* called from IRQ */
 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
 {
@@ -144,7 +189,9 @@ static int _skl_suspend(struct hdac_ext_bus *ebus)
 		return ret;
 
 	snd_hdac_bus_stop_chip(bus);
+	skl_enable_miscbdcge(bus->dev, false);
 	snd_hdac_bus_enter_link_reset(bus);
+	skl_enable_miscbdcge(bus->dev, true);
 
 	return 0;
 }
@@ -155,7 +202,7 @@ static int _skl_resume(struct hdac_ext_bus *ebus)
 	struct hdac_bus *bus = ebus_to_hbus(ebus);
 
 	skl_init_pci(skl);
-	snd_hdac_bus_init_chip(bus, true);
+	skl_init_chip(bus, true);
 
 	return skl_resume_dsp(skl);
 }
@@ -379,7 +426,7 @@ static int skl_codec_create(struct hdac_ext_bus *ebus)
 				 * back to the sanity state.
 				 */
 				snd_hdac_bus_stop_chip(bus);
-				snd_hdac_bus_init_chip(bus, true);
+				skl_init_chip(bus, true);
 			}
 		}
 	}
@@ -489,7 +536,7 @@ static int skl_first_init(struct hdac_ext_bus *ebus)
 	/* initialize chip */
 	skl_init_pci(skl);
 
-	snd_hdac_bus_init_chip(bus, true);
+	skl_init_chip(bus, true);
 
 	/* codec detection */
 	if (!bus->codec_mask) {
@@ -538,6 +585,8 @@ static int skl_probe(struct pci_dev *pci,
 			dev_dbg(bus->dev, "error failed to register dsp\n");
 			goto out_mach_free;
 		}
+		skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge;
+
 	}
 	if (ebus->mlcap)
 		snd_hdac_ext_bus_get_ml_capabilities(ebus);
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h
index 3d167eed0f59..7610808102f9 100644
--- a/sound/soc/intel/skylake/skl.h
+++ b/sound/soc/intel/skylake/skl.h
@@ -48,6 +48,9 @@
 #define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20
 
+#define AZX_PCIREG_CGCTL		0x48
+#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)
+
 struct skl_dsp_resource {
 	u32 max_mcps;
 	u32 max_mem;
-- 
1.9.1

[PATCH v4 08/13] ASoC: Intel: Skylake: Use CGCTL.MISCBDCGE for Phrase detection notification

[Vinod Koul]

From: "Dharageswari.R" <dharageswari.r@intel.com>

Per HW recommendation, SW shall clear the CGCTL.MISCBDCGE and set
it back once data is transferred. So clear this when we get the
IPC and track using a driver flag, and set back on closure

Signed-off-by: Dharageswari.R <dharageswari.r@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c     | 13 +++++++++++++
 sound/soc/intel/skylake/skl-sst-ipc.c | 15 +++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index b89ae6f7c096..8039a0479053 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -25,6 +25,8 @@
 #include <sound/soc.h>
 #include "skl.h"
 #include "skl-topology.h"
+#include "skl-sst-dsp.h"
+#include "skl-sst-ipc.h"
 
 #define HDA_MONO 1
 #define HDA_STEREO 2
@@ -272,6 +274,7 @@ static void skl_pcm_close(struct snd_pcm_substream *substream,
 	struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 	struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 	struct skl_dma_params *dma_params = NULL;
+	struct skl *skl = ebus_to_skl(ebus);
 
 	dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 
@@ -285,6 +288,16 @@ static void skl_pcm_close(struct snd_pcm_substream *substream,
 	snd_soc_dai_set_dma_data(dai, substream, NULL);
 	skl_set_suspend_active(substream, dai, false);
 
+	/*
+	 * check if close is for "Reference Pin" and set back the
+	 * CGCTL.MISCBDCGE if disabled by driver
+	 */
+	if (!strncmp(dai->name, "Reference Pin", 13) &&
+			skl->skl_sst->miscbdcg_disabled) {
+		skl->skl_sst->enable_miscbdcge(dai->dev, true);
+		skl->skl_sst->miscbdcg_disabled = false;
+	}
+
 	kfree(dma_params);
 }
 
diff --git a/sound/soc/intel/skylake/skl-sst-ipc.c b/sound/soc/intel/skylake/skl-sst-ipc.c
index 62e665a3b8f7..543460293b00 100644
--- a/sound/soc/intel/skylake/skl-sst-ipc.c
+++ b/sound/soc/intel/skylake/skl-sst-ipc.c
@@ -16,8 +16,10 @@
 
 #include "../common/sst-dsp.h"
 #include "../common/sst-dsp-priv.h"
+#include "skl.h"
 #include "skl-sst-dsp.h"
 #include "skl-sst-ipc.h"
+#include "sound/hdaudio_ext.h"
 
 
 #define IPC_IXC_STATUS_BITS		24
@@ -322,6 +324,19 @@ static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
 			wake_up(&skl->boot_wait);
 			break;
 
+		case IPC_GLB_NOTIFY_PHRASE_DETECTED:
+			dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
+
+			/*
+			 * Per HW recomendation, After phrase detection,
+			 * clear the CGCTL.MISCBDCGE.
+			 *
+			 * This will be set back on stream closure
+			 */
+			skl->enable_miscbdcge(ipc->dev, false);
+			skl->miscbdcg_disabled = true;
+			break;
+
 		default:
 			dev_err(ipc->dev, "ipc: Unhandled error msg=%x",
 						header.primary);
-- 
1.9.1

[PATCH v4 09/13] ASoC: Intel: Skylake: manage link power in active suspend

[Vinod Koul]

When device enters active suspend, we should turn off the links
as they are not in use. Similarly we need to bring back links
when we exit active suspend.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index 85d47cedd125..5987509507ba 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -223,6 +223,7 @@ static int skl_suspend(struct device *dev)
 	 * running, we need to save the state for these and continue
 	 */
 	if (skl->supend_active) {
+		snd_hdac_ext_bus_link_power_down_all(ebus);
 		pci_save_state(pci);
 		pci_disable_device(pci);
 		return 0;
@@ -245,6 +246,7 @@ static int skl_resume(struct device *dev)
 	if (skl->supend_active) {
 		pci_restore_state(pci);
 		ret = pci_enable_device(pci);
+		snd_hdac_ext_bus_link_power_up_all(ebus);
 	} else {
 		ret = _skl_resume(ebus);
 	}
-- 
1.9.1

[PATCH v4 10/13] ASoC: Intel: Skylake: enable interrupt as wake source in active suspend

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

In active suspend, any HDA interrupt should wake the system. When device
enters active suspend, we need to enable HDA controller interrupt as wake
source. Similarly disable HDA controller interrupt as wake source when
exiting active suspend.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index 5987509507ba..275d00334b53 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -217,6 +217,7 @@ static int skl_suspend(struct device *dev)
 	struct pci_dev *pci = to_pci_dev(dev);
 	struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
 	struct skl *skl  = ebus_to_skl(ebus);
+	struct hdac_bus *bus = ebus_to_hbus(ebus);
 
 	/*
 	 * Do not suspend if streams which are marked ignore suspend are
@@ -224,6 +225,7 @@ static int skl_suspend(struct device *dev)
 	 */
 	if (skl->supend_active) {
 		snd_hdac_ext_bus_link_power_down_all(ebus);
+		enable_irq_wake(bus->irq);
 		pci_save_state(pci);
 		pci_disable_device(pci);
 		return 0;
@@ -237,6 +239,7 @@ static int skl_resume(struct device *dev)
 	struct pci_dev *pci = to_pci_dev(dev);
 	struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
 	struct skl *skl  = ebus_to_skl(ebus);
+	struct hdac_bus *bus = ebus_to_hbus(ebus);
 	int ret;
 
 	/*
@@ -247,6 +250,7 @@ static int skl_resume(struct device *dev)
 		pci_restore_state(pci);
 		ret = pci_enable_device(pci);
 		snd_hdac_ext_bus_link_power_up_all(ebus);
+		disable_irq_wake(bus->irq);
 	} else {
 		ret = _skl_resume(ebus);
 	}
-- 
1.9.1

[PATCH v4 11/13] ASoC: Intel: Skylake: Add DMA resume position in Trigger resume/suspend

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

Use the DMA resume capability to resume the DMA position when
stream is suspended/resumed.

In suspend we save the position and when stream is resumed the stream needs
to be started from the position when the stream was suspended using the new
DMA resume capabilities

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 8039a0479053..5a532224cb47 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -393,6 +393,15 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 	switch (cmd) {
 	case SNDRV_PCM_TRIGGER_RESUME:
 		skl_pcm_prepare(substream, dai);
+		/*
+		 * enable DMA Resume enable bit for the stream, set the dpib
+		 * & lpib position to resune before starting the DMA
+		 */
+		snd_hdac_ext_stream_drsm_enable(ebus, true,
+					hdac_stream(stream)->index);
+		snd_hdac_ext_stream_set_dpibr(ebus, stream, stream->dpib);
+		snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
+
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		/*
@@ -421,8 +430,17 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 			return ret;
 
 		ret = skl_decoupled_trigger(substream, cmd);
-		if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
+		if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) {
+			/* save the dpib and lpib positions */
+			stream->dpib = readl(ebus->bus.remap_addr +
+					AZX_REG_VS_SDXDPIB_XBASE +
+					(AZX_REG_VS_SDXDPIB_XINTERVAL *
+					hdac_stream(stream)->index));
+
+			stream->lpib = snd_hdac_stream_get_pos_lpib(
+							hdac_stream(stream));
 			snd_hdac_ext_stream_decouple(ebus, stream, false);
+		}
 		break;
 
 	default:
-- 
1.9.1

[PATCH v4 12/13] ASoC: Intel: Skylake: Reconfigure Link stream on suspend/resume

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

On suspend the link register are lost so we need to reconfigure
them in resume. This patch adds the reconfiguration of the link
register in trigger resume.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 5a532224cb47..17a64362b283 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -496,11 +496,6 @@ static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
 	struct hdac_ext_link *link;
 
-	if (link_dev->link_prepared) {
-		dev_dbg(dai->dev, "already stream is prepared - returning\n");
-		return 0;
-	}
-
 	dma_params  = (struct skl_dma_params *)
 			snd_soc_dai_get_dma_data(codec_dai, substream);
 	if (dma_params)
@@ -508,14 +503,15 @@ static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 	dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
 			hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
 
-	snd_hdac_ext_link_stream_reset(link_dev);
-
-	snd_hdac_ext_link_stream_setup(link_dev, format_val);
-
 	link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
 	if (!link)
 		return -EINVAL;
 
+	snd_hdac_ext_bus_link_power_up(link);
+	snd_hdac_ext_link_stream_reset(link_dev);
+
+	snd_hdac_ext_link_stream_setup(link_dev, format_val);
+
 	snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
 	link_dev->link_prepared = 1;
 
@@ -527,12 +523,16 @@ static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 {
 	struct hdac_ext_stream *link_dev =
 				snd_soc_dai_get_dma_data(dai, substream);
+	struct hdac_ext_bus *ebus = get_bus_ctx(substream);
+	struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 
 	dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_RESUME:
+		skl_link_pcm_prepare(substream, dai);
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-	case SNDRV_PCM_TRIGGER_RESUME:
+		snd_hdac_ext_stream_decouple(ebus, stream, true);
 		snd_hdac_ext_link_stream_start(link_dev);
 		break;
 
@@ -540,6 +540,8 @@ static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 	case SNDRV_PCM_TRIGGER_SUSPEND:
 	case SNDRV_PCM_TRIGGER_STOP:
 		snd_hdac_ext_link_stream_clear(link_dev);
+		if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
+			snd_hdac_ext_stream_decouple(ebus, stream, false);
 		break;
 
 	default:
-- 
1.9.1

[PATCH v4 13/13] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds pcm capability to support Resume.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 17a64362b283..f3553258091a 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -38,6 +38,7 @@ static struct snd_pcm_hardware azx_pcm_hw = {
 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 				 SNDRV_PCM_INFO_MMAP_VALID |
 				 SNDRV_PCM_INFO_PAUSE |
+				 SNDRV_PCM_INFO_RESUME |
 				 SNDRV_PCM_INFO_SYNC_START |
 				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
-- 
1.9.1

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Vinod Koul]

On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:
> From: Jeeja KP <jeeja.kp@intel.com>
> 
> Skylake sports new capability of DMA resume, DRSM where we can
> resume the DMA. This capability is defined by presence of
> AZX_DRSM_CAP_ID.

Hi Takashi,

Can you please ACK this and path 4, 5 and 6 of this series, as they are
on sound/hda/. I think Mark is waiting on that..

> 
> If this capability is present, we use this capability.
> So we add:
> 
> snd_hdac_ext_stream_drsm_enable() - DMA resume caps
> snd_hdac_ext_stream_set_dpibr() - set the DMA position
> snd_hdac_ext_stream_set_lpib() - set the lpib
> 
> Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
> ---
>  include/sound/hda_register.h        |  9 +++++
>  include/sound/hdaudio_ext.h         | 14 ++++++++
>  sound/hda/ext/hdac_ext_controller.c |  6 ++++
>  sound/hda/ext/hdac_ext_stream.c     | 71 +++++++++++++++++++++++++++++++++++++
>  4 files changed, 100 insertions(+)
> 
> diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
> index 2ae8812d7b1a..28ac1f9a18ac 100644
> --- a/include/sound/hda_register.h
> +++ b/include/sound/hda_register.h
> @@ -230,6 +230,15 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
>  #define AZX_MLCTL_SPA			(1<<16)
>  #define AZX_MLCTL_CPA			23
>  
> +
> +/* registers for DMA Resume Capability Structure */
> +#define AZX_DRSM_CAP_ID			0x5
> +#define AZX_REG_DRSM_CTL		0x4
> +/* Base used to calculate the iterating register offset */
> +#define AZX_DRSM_BASE			0x08
> +/* Interval used to calculate the iterating register offset */
> +#define AZX_DRSM_INTERVAL		0x08
> +
>  /*
>   * helpers to read the stream position
>   */
> diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
> index 425af0674557..f3454950ee0b 100644
> --- a/include/sound/hdaudio_ext.h
> +++ b/include/sound/hdaudio_ext.h
> @@ -12,6 +12,7 @@
>   * @spbcap: SPIB capabilities pointer
>   * @mlcap: MultiLink capabilities pointer
>   * @gtscap: gts capabilities pointer
> + * @drsmcap: dma resume capabilities pointer
>   * @hlink_list: link list of HDA links
>   */
>  struct hdac_ext_bus {
> @@ -23,6 +24,7 @@ struct hdac_ext_bus {
>  	void __iomem *spbcap;
>  	void __iomem *mlcap;
>  	void __iomem *gtscap;
> +	void __iomem *drsmcap;
>  
>  	struct list_head hlink_list;
>  };
> @@ -72,6 +74,9 @@ enum hdac_ext_stream_type {
>   * @pplc_addr: processing pipe link stream pointer
>   * @spib_addr: software position in buffers stream pointer
>   * @fifo_addr: software position Max fifos stream pointer
> + * @dpibr_addr: DMA position in buffer resume pointer
> + * @dpib: DMA position in buffer
> + * @lpib: Linear position in buffer
>   * @decoupled: stream host and link is decoupled
>   * @link_locked: link is locked
>   * @link_prepared: link is prepared
> @@ -86,6 +91,10 @@ struct hdac_ext_stream {
>  	void __iomem *spib_addr;
>  	void __iomem *fifo_addr;
>  
> +	void __iomem *dpibr_addr;
> +
> +	u32 dpib;
> +	u32 lpib;
>  	bool decoupled:1;
>  	bool link_locked:1;
>  	bool link_prepared;
> @@ -116,6 +125,11 @@ int snd_hdac_ext_stream_set_spib(struct hdac_ext_bus *ebus,
>  				 struct hdac_ext_stream *stream, u32 value);
>  int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_ext_bus *ebus,
>  				 struct hdac_ext_stream *stream);
> +void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
> +				bool enable, int index);
> +int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
> +				struct hdac_ext_stream *stream, u32 value);
> +int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value);
>  
>  void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hstream);
>  void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hstream);
> diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
> index 63215b17247c..556267e75591 100644
> --- a/sound/hda/ext/hdac_ext_controller.c
> +++ b/sound/hda/ext/hdac_ext_controller.c
> @@ -77,6 +77,12 @@ int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *ebus)
>  			ebus->spbcap = bus->remap_addr + offset;
>  			break;
>  
> +		case AZX_DRSM_CAP_ID:
> +			/* DMA resume  capability found, handler function */
> +			dev_dbg(bus->dev, "Found DRSM capability\n");
> +			ebus->drsmcap = bus->remap_addr + offset;
> +			break;
> +
>  		default:
>  			dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
>  			break;
> diff --git a/sound/hda/ext/hdac_ext_stream.c b/sound/hda/ext/hdac_ext_stream.c
> index cb89ec7c8147..8f30e8836818 100644
> --- a/sound/hda/ext/hdac_ext_stream.c
> +++ b/sound/hda/ext/hdac_ext_stream.c
> @@ -59,6 +59,10 @@ void snd_hdac_ext_stream_init(struct hdac_ext_bus *ebus,
>  					AZX_SPB_MAXFIFO;
>  	}
>  
> +	if (ebus->drsmcap)
> +		stream->dpibr_addr = ebus->drsmcap + AZX_DRSM_BASE +
> +					AZX_DRSM_INTERVAL * idx;
> +
>  	stream->decoupled = false;
>  	snd_hdac_stream_init(bus, &stream->hstream, idx, direction, tag);
>  }
> @@ -497,3 +501,70 @@ void snd_hdac_ext_stop_streams(struct hdac_ext_bus *ebus)
>  	}
>  }
>  EXPORT_SYMBOL_GPL(snd_hdac_ext_stop_streams);
> +
> +/**
> + * snd_hdac_ext_stream_drsm_enable - enable DMA resume for a stream
> + * @ebus: HD-audio ext core bus
> + * @enable: flag to enable/disable DRSM
> + * @index: stream index for which DRSM need to be enabled
> + */
> +void snd_hdac_ext_stream_drsm_enable(struct hdac_ext_bus *ebus,
> +				bool enable, int index)
> +{
> +	u32 mask = 0;
> +	u32 register_mask = 0;
> +	struct hdac_bus *bus = &ebus->bus;
> +
> +	if (!ebus->drsmcap) {
> +		dev_err(bus->dev, "Address of DRSM capability is NULL");
> +		return;
> +	}
> +
> +	mask |= (1 << index);
> +
> +	register_mask = readl(ebus->drsmcap + AZX_REG_SPB_SPBFCCTL);
> +
> +	mask |= register_mask;
> +
> +	if (enable)
> +		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, 0, mask);
> +	else
> +		snd_hdac_updatel(ebus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
> +}
> +EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_drsm_enable);
> +
> +/**
> + * snd_hdac_ext_stream_set_dpibr - sets the dpibr value of a stream
> + * @ebus: HD-audio ext core bus
> + * @stream: hdac_ext_stream
> + * @value: dpib value to set
> + */
> +int snd_hdac_ext_stream_set_dpibr(struct hdac_ext_bus *ebus,
> +				 struct hdac_ext_stream *stream, u32 value)
> +{
> +	struct hdac_bus *bus = &ebus->bus;
> +
> +	if (!ebus->drsmcap) {
> +		dev_err(bus->dev, "Address of DRSM capability is NULL");
> +		return -EINVAL;
> +	}
> +
> +	writel(value, stream->dpibr_addr);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_dpibr);
> +
> +/**
> + * snd_hdac_ext_stream_set_lpib - sets the lpib value of a stream
> + * @ebus: HD-audio ext core bus
> + * @stream: hdac_ext_stream
> + * @value: lpib value to set
> + */
> +int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *stream, u32 value)
> +{
> +	snd_hdac_stream_writel(&stream->hstream, SD_LPIB, value);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_set_lpib);
> -- 
> 1.9.1
> 

-- 
~Vinod

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 405 bytes --]

On Mon, Jan 04, 2016 at 11:27:15AM +0530, Vinod Koul wrote:
> On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:

> > Skylake sports new capability of DMA resume, DRSM where we can
> > resume the DMA. This capability is defined by presence of
> > AZX_DRSM_CAP_ID.

> Can you please ACK this and path 4, 5 and 6 of this series, as they are
> on sound/hda/. I think Mark is waiting on that..

Yes.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

[-- Attachment #2: Type: text/plain, Size: 0 bytes --]

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Takashi Iwai]

On Tue, 05 Jan 2016 16:51:08 +0100,
Mark Brown wrote:
> 
> On Mon, Jan 04, 2016 at 11:27:15AM +0530, Vinod Koul wrote:
> > On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:
> 
> > > Skylake sports new capability of DMA resume, DRSM where we can
> > > resume the DMA. This capability is defined by presence of
> > > AZX_DRSM_CAP_ID.
> 
> > Can you please ACK this and path 4, 5 and 6 of this series, as they are
> > on sound/hda/. I think Mark is waiting on that..
> 
> Yes.

Sorry for the late reply, as I've been on vacation.
Feel free to take my ack:

Reviewed-by: Takashi Iwai <tiwai@suse.de>


thanks,

Takashi

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Takashi Iwai]

On Wed, 06 Jan 2016 10:18:21 +0100,
Vinod Koul wrote:
> 
> On Wed, Jan 06, 2016 at 10:03:24AM +0100, Takashi Iwai wrote:
> > On Tue, 05 Jan 2016 16:51:08 +0100,
> > Mark Brown wrote:
> > > 
> > > On Mon, Jan 04, 2016 at 11:27:15AM +0530, Vinod Koul wrote:
> > > > On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:
> > > 
> > > > > Skylake sports new capability of DMA resume, DRSM where we can
> > > > > resume the DMA. This capability is defined by presence of
> > > > > AZX_DRSM_CAP_ID.
> > > 
> > > > Can you please ACK this and path 4, 5 and 6 of this series, as they are
> > > > on sound/hda/. I think Mark is waiting on that..
> > > 
> > > Yes.
> > 
> > Sorry for the late reply, as I've been on vacation.
> > Feel free to take my ack:
> > 
> > Reviewed-by: Takashi Iwai <tiwai@suse.de>
> 
> Thanks Takashi
> 
> Can you please ACK the next three patches as well, they are
> on HDA too

Oh I meant for the series.


Takashi

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Vinod Koul]

On Wed, Jan 06, 2016 at 10:03:24AM +0100, Takashi Iwai wrote:
> On Tue, 05 Jan 2016 16:51:08 +0100,
> Mark Brown wrote:
> > 
> > On Mon, Jan 04, 2016 at 11:27:15AM +0530, Vinod Koul wrote:
> > > On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:
> > 
> > > > Skylake sports new capability of DMA resume, DRSM where we can
> > > > resume the DMA. This capability is defined by presence of
> > > > AZX_DRSM_CAP_ID.
> > 
> > > Can you please ACK this and path 4, 5 and 6 of this series, as they are
> > > on sound/hda/. I think Mark is waiting on that..
> > 
> > Yes.
> 
> Sorry for the late reply, as I've been on vacation.
> Feel free to take my ack:
> 
> Reviewed-by: Takashi Iwai <tiwai@suse.de>

Thanks Takashi

Can you please ACK the next three patches as well, they are
on HDA too

-- 
~Vinod

Re: [PATCH v4 03/13] ALSA: hdac: Add support for hda DMA Resume capability

[Vinod Koul]

On Wed, Jan 06, 2016 at 10:16:31AM +0100, Takashi Iwai wrote:
> On Wed, 06 Jan 2016 10:18:21 +0100,
> Vinod Koul wrote:
> > 
> > On Wed, Jan 06, 2016 at 10:03:24AM +0100, Takashi Iwai wrote:
> > > On Tue, 05 Jan 2016 16:51:08 +0100,
> > > Mark Brown wrote:
> > > > 
> > > > On Mon, Jan 04, 2016 at 11:27:15AM +0530, Vinod Koul wrote:
> > > > > On Fri, Dec 18, 2015 at 03:11:59PM +0530, Vinod Koul wrote:
> > > > 
> > > > > > Skylake sports new capability of DMA resume, DRSM where we can
> > > > > > resume the DMA. This capability is defined by presence of
> > > > > > AZX_DRSM_CAP_ID.
> > > > 
> > > > > Can you please ACK this and path 4, 5 and 6 of this series, as they are
> > > > > on sound/hda/. I think Mark is waiting on that..
> > > > 
> > > > Yes.
> > > 
> > > Sorry for the late reply, as I've been on vacation.
> > > Feel free to take my ack:
> > > 
> > > Reviewed-by: Takashi Iwai <tiwai@suse.de>
> > 
> > Thanks Takashi
> > 
> > Can you please ACK the next three patches as well, they are
> > on HDA too
> 
> Oh I meant for the series.

Much better then, Thanks :)

-- 
~Vinod

Applied "ASoC: Intel: Skylake: Use CGCTL.MISCBDCGE for Phrase detection notification" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Use CGCTL.MISCBDCGE for Phrase detection notification

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 721c3e36f774150f453216efcf5e1895577ac68c Mon Sep 17 00:00:00 2001
From: "Dharageswari.R" <dharageswari.r@intel.com>
Date: Fri, 18 Dec 2015 15:12:04 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Use CGCTL.MISCBDCGE for Phrase
 detection notification

Per HW recommendation, SW shall clear the CGCTL.MISCBDCGE and set
it back once data is transferred. So clear this when we get the
IPC and track using a driver flag, and set back on closure

Signed-off-by: Dharageswari.R <dharageswari.r@intel.com>
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-pcm.c     | 13 +++++++++++++
 sound/soc/intel/skylake/skl-sst-ipc.c | 15 +++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index b89ae6f7c096..8039a0479053 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -25,6 +25,8 @@
 #include <sound/soc.h>
 #include "skl.h"
 #include "skl-topology.h"
+#include "skl-sst-dsp.h"
+#include "skl-sst-ipc.h"
 
 #define HDA_MONO 1
 #define HDA_STEREO 2
@@ -272,6 +274,7 @@ static void skl_pcm_close(struct snd_pcm_substream *substream,
 	struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 	struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
 	struct skl_dma_params *dma_params = NULL;
+	struct skl *skl = ebus_to_skl(ebus);
 
 	dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 
@@ -285,6 +288,16 @@ static void skl_pcm_close(struct snd_pcm_substream *substream,
 	snd_soc_dai_set_dma_data(dai, substream, NULL);
 	skl_set_suspend_active(substream, dai, false);
 
+	/*
+	 * check if close is for "Reference Pin" and set back the
+	 * CGCTL.MISCBDCGE if disabled by driver
+	 */
+	if (!strncmp(dai->name, "Reference Pin", 13) &&
+			skl->skl_sst->miscbdcg_disabled) {
+		skl->skl_sst->enable_miscbdcge(dai->dev, true);
+		skl->skl_sst->miscbdcg_disabled = false;
+	}
+
 	kfree(dma_params);
 }
 
diff --git a/sound/soc/intel/skylake/skl-sst-ipc.c b/sound/soc/intel/skylake/skl-sst-ipc.c
index 62e665a3b8f7..543460293b00 100644
--- a/sound/soc/intel/skylake/skl-sst-ipc.c
+++ b/sound/soc/intel/skylake/skl-sst-ipc.c
@@ -16,8 +16,10 @@
 
 #include "../common/sst-dsp.h"
 #include "../common/sst-dsp-priv.h"
+#include "skl.h"
 #include "skl-sst-dsp.h"
 #include "skl-sst-ipc.h"
+#include "sound/hdaudio_ext.h"
 
 
 #define IPC_IXC_STATUS_BITS		24
@@ -322,6 +324,19 @@ static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
 			wake_up(&skl->boot_wait);
 			break;
 
+		case IPC_GLB_NOTIFY_PHRASE_DETECTED:
+			dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
+
+			/*
+			 * Per HW recomendation, After phrase detection,
+			 * clear the CGCTL.MISCBDCGE.
+			 *
+			 * This will be set back on stream closure
+			 */
+			skl->enable_miscbdcge(ipc->dev, false);
+			skl->miscbdcg_disabled = true;
+			break;
+
 		default:
 			dev_err(ipc->dev, "ipc: Unhandled error msg=%x",
 						header.primary);
-- 
2.7.0.rc3

Applied "ASoC: Intel: Skylake: fix reset controller sequencing" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: fix reset controller sequencing

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 0c8ba9d28518822d612de23fc9020b2a66a0228c Mon Sep 17 00:00:00 2001
From: Jayachandran B <jayachandran.b@intel.com>
Date: Fri, 18 Dec 2015 15:12:03 +0530
Subject: [PATCH] ASoC: Intel: Skylake: fix reset controller sequencing

MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-sst-ipc.h |  5 ++++
 sound/soc/intel/skylake/skl.c         | 55 +++++++++++++++++++++++++++++++++--
 sound/soc/intel/skylake/skl.h         |  3 ++
 3 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-ipc.h b/sound/soc/intel/skylake/skl-sst-ipc.h
index 1bbcdb471cf2..d59d1ba62a43 100644
--- a/sound/soc/intel/skylake/skl-sst-ipc.h
+++ b/sound/soc/intel/skylake/skl-sst-ipc.h
@@ -55,6 +55,11 @@ struct skl_sst {
 
 	/* IPC messaging */
 	struct sst_generic_ipc ipc;
+
+	/* callback for miscbdge */
+	void (*enable_miscbdcge)(struct device *dev, bool enable);
+	/*Is CGCTL.MISCBDCGE disabled*/
+	bool miscbdcg_disabled;
 };
 
 struct skl_ipc_init_instance_msg {
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index b69649aa7809..dd38f5feb7c0 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -29,6 +29,8 @@
 #include <sound/pcm.h>
 #include "../common/sst-acpi.h"
 #include "skl.h"
+#include "skl-sst-dsp.h"
+#include "skl-sst-ipc.h"
 
 /*
  * initialize the PCI registers
@@ -59,6 +61,49 @@ static void skl_init_pci(struct skl *skl)
 	skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 }
 
+static void update_pci_dword(struct pci_dev *pci,
+			unsigned int reg, u32 mask, u32 val)
+{
+	u32 data = 0;
+
+	pci_read_config_dword(pci, reg, &data);
+	data &= ~mask;
+	data |= (val & mask);
+	pci_write_config_dword(pci, reg, data);
+}
+
+/*
+ * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
+ *
+ * @dev: device pointer
+ * @enable: enable/disable flag
+ */
+static void skl_enable_miscbdcge(struct device *dev, bool enable)
+{
+	struct pci_dev *pci = to_pci_dev(dev);
+	u32 val;
+
+	val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
+
+	update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
+}
+
+/*
+ * While performing reset, controller may not come back properly causing
+ * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
+ * (init chip) and then again set CGCTL.MISCBDCGE to 1
+ */
+static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
+{
+	int ret;
+
+	skl_enable_miscbdcge(bus->dev, false);
+	ret = snd_hdac_bus_init_chip(bus, full_reset);
+	skl_enable_miscbdcge(bus->dev, true);
+
+	return ret;
+}
+
 /* called from IRQ */
 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
 {
@@ -145,7 +190,9 @@ static int _skl_suspend(struct hdac_ext_bus *ebus)
 		return ret;
 
 	snd_hdac_bus_stop_chip(bus);
+	skl_enable_miscbdcge(bus->dev, false);
 	snd_hdac_bus_enter_link_reset(bus);
+	skl_enable_miscbdcge(bus->dev, true);
 
 	return 0;
 }
@@ -156,7 +203,7 @@ static int _skl_resume(struct hdac_ext_bus *ebus)
 	struct hdac_bus *bus = ebus_to_hbus(ebus);
 
 	skl_init_pci(skl);
-	snd_hdac_bus_init_chip(bus, true);
+	skl_init_chip(bus, true);
 
 	return skl_resume_dsp(skl);
 }
@@ -380,7 +427,7 @@ static int skl_codec_create(struct hdac_ext_bus *ebus)
 				 * back to the sanity state.
 				 */
 				snd_hdac_bus_stop_chip(bus);
-				snd_hdac_bus_init_chip(bus, true);
+				skl_init_chip(bus, true);
 			}
 		}
 	}
@@ -490,7 +537,7 @@ static int skl_first_init(struct hdac_ext_bus *ebus)
 	/* initialize chip */
 	skl_init_pci(skl);
 
-	snd_hdac_bus_init_chip(bus, true);
+	skl_init_chip(bus, true);
 
 	/* codec detection */
 	if (!bus->codec_mask) {
@@ -539,6 +586,8 @@ static int skl_probe(struct pci_dev *pci,
 			dev_dbg(bus->dev, "error failed to register dsp\n");
 			goto out_mach_free;
 		}
+		skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge;
+
 	}
 	if (ebus->mlcap)
 		snd_hdac_ext_bus_get_ml_capabilities(ebus);
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h
index 36a1b8c5f6d0..8a08bb727991 100644
--- a/sound/soc/intel/skylake/skl.h
+++ b/sound/soc/intel/skylake/skl.h
@@ -48,6 +48,9 @@
 #define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20
 
+#define AZX_PCIREG_CGCTL		0x48
+#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)
+
 struct skl_dsp_resource {
 	u32 max_mcps;
 	u32 max_mem;
-- 
2.7.0.rc3