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* [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page
@ 2016-01-11 11:39 Michel Thierry
  2016-01-11 11:51 ` Chris Wilson
  2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Michel Thierry @ 2016-01-11 11:39 UTC (permalink / raw)
  To: intel-gfx; +Cc: artur.harasimiuk

Kernel and userspace are able to handle 4GB (1<<32) address space range,
but "A32 Stateless Model" is not. According to documentation, A32 accesses
are based on General State Base Address and bound checking is in place.
Because size field (instruction State Base Address) limitation, it is not
possible to address full 4GB memory region.

A32 Stateless Model is used by some libraries and without this patch, the
last page of 4GB address space is not accessible in 32bit processes.

Reported-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6c60e04..ddc21d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3488,7 +3488,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
 	if (flags & PIN_MAPPABLE)
 		end = min_t(u64, end, dev_priv->gtt.mappable_end);
 	if (flags & PIN_ZONE_4G)
-		end = min_t(u64, end, (1ULL << 32));
+		end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
 
 	if (alignment == 0)
 		alignment = flags & PIN_MAPPABLE ? fence_alignment :
-- 
2.7.0

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page
  2016-01-11 11:39 [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page Michel Thierry
@ 2016-01-11 11:51 ` Chris Wilson
  2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
  1 sibling, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2016-01-11 11:51 UTC (permalink / raw)
  To: Michel Thierry; +Cc: intel-gfx, artur.harasimiuk

On Mon, Jan 11, 2016 at 11:39:27AM +0000, Michel Thierry wrote:
> Kernel and userspace are able to handle 4GB (1<<32) address space range,
> but "A32 Stateless Model" is not. According to documentation, A32 accesses
> are based on General State Base Address and bound checking is in place.
> Because size field (instruction State Base Address) limitation, it is not
> possible to address full 4GB memory region.
> 
> A32 Stateless Model is used by some libraries and without this patch, the
> last page of 4GB address space is not accessible in 32bit processes.
> 
> Reported-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>

That seems reasonably in line with the flag, and a caveat I think we
live with (GGTT which is already 4G max can't use the last page, even if
we hadn't already given it away).

> ---
>  drivers/gpu/drm/i915/i915_gem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6c60e04..ddc21d4 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3488,7 +3488,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
>  	if (flags & PIN_MAPPABLE)
>  		end = min_t(u64, end, dev_priv->gtt.mappable_end);
>  	if (flags & PIN_ZONE_4G)
> -		end = min_t(u64, end, (1ULL << 32));
> +		end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);

Bah, I came here expecting to find a mistake with brackets and u64
promotion. Spoilsport.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* ✓ success: Fi.CI.BAT
  2016-01-11 11:39 [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page Michel Thierry
  2016-01-11 11:51 ` Chris Wilson
@ 2016-01-11 11:53 ` Patchwork
  2016-01-12 16:50   ` Daniel Vetter
  1 sibling, 1 reply; 4+ messages in thread
From: Patchwork @ 2016-01-11 11:53 UTC (permalink / raw)
  To: Michel Thierry; +Cc: intel-gfx

== Summary ==

Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest

Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (bdw-ultra)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b:
                dmesg-warn -> PASS       (byt-nuc)

bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:138  pass:132  dwarn:0   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
hsw-gt2          total:141  pass:136  dwarn:0   dfail:0   fail:1   skip:4  
hsw-xps12        total:138  pass:133  dwarn:1   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:141  pass:101  dwarn:3   dfail:0   fail:0   skip:37 
ivb-t430s        total:135  pass:122  dwarn:3   dfail:4   fail:0   skip:6  
skl-i5k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 

Results at /archive/results/CI_IGT_test/Patchwork_1125/

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: ✓ success:  Fi.CI.BAT
  2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
@ 2016-01-12 16:50   ` Daniel Vetter
  0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2016-01-12 16:50 UTC (permalink / raw)
  To: Patchwork; +Cc: intel-gfx

On Mon, Jan 11, 2016 at 11:53:53AM -0000, Patchwork wrote:
> == Summary ==
> 
> Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC integration manifest
> 
> Test gem_storedw_loop:
>         Subgroup basic-render:
>                 dmesg-warn -> PASS       (bdw-ultra)
> Test kms_flip:
>         Subgroup basic-flip-vs-dpms:
>                 dmesg-warn -> PASS       (ilk-hp8440p)
> Test kms_pipe_crc_basic:
>         Subgroup read-crc-pipe-b:
>                 dmesg-warn -> PASS       (byt-nuc)
> 
> bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
> bdw-ultra        total:138  pass:132  dwarn:0   dfail:0   fail:0   skip:6  
> bsw-nuc-2        total:141  pass:114  dwarn:3   dfail:0   fail:0   skip:24 
> byt-nuc          total:141  pass:119  dwarn:7   dfail:0   fail:0   skip:15 
> hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
> hsw-gt2          total:141  pass:136  dwarn:0   dfail:0   fail:1   skip:4  
> hsw-xps12        total:138  pass:133  dwarn:1   dfail:0   fail:0   skip:4  
> ilk-hp8440p      total:141  pass:101  dwarn:3   dfail:0   fail:0   skip:37 
> ivb-t430s        total:135  pass:122  dwarn:3   dfail:4   fail:0   skip:6  
> skl-i5k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
> skl-i7k-2        total:141  pass:131  dwarn:2   dfail:0   fail:0   skip:8  
> snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
> snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1125/

Yay, a lucky patch that passed bat, so merged it to dinq!
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-01-12 16:50 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-11 11:39 [PATCH] drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page Michel Thierry
2016-01-11 11:51 ` Chris Wilson
2016-01-11 11:53 ` ✓ success: Fi.CI.BAT Patchwork
2016-01-12 16:50   ` Daniel Vetter

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