* [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock
@ 2015-12-21 12:56 ` Jon Hunter
0 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2015-12-21 12:56 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out1
------------[ cut here ]------------
WARNING: at drivers/clk/tegra/clk.c:269
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
PC is at tegra_init_from_table+0x140/0x164
LR is at tegra_init_from_table+0x140/0x164
pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
sp : ffffffc0bc0abd50
x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
x27: ffffffc000a06000 x26: ffffffc0bc019780
x25: ffffffc00086a708 x24: ffffffc00086a790
x23: ffffffc0006d7188 x22: ffffffc0bc010000
x21: 000000000000016e x20: ffffffc0bc00d100
x19: ffffffc000944178 x18: 0000000000000007
x17: 000000000000000e x16: 0000000000000001
x15: 0000000000000007 x14: 000000000000000e
x13: 0000000000000013 x12: 000000000000001a
x11: 000000000000004d x10: 0000000000000750
x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
x7 : 0000000000000001 x6 : 0000000002d5f0f8
x5 : 0000000000000000 x4 : 0000000000000000
x3 : 0000000000000002 x2 : ffffffc000996724
x1 : 0000000000000000 x0 : 0000000000000032
---[ end trace cbd20ae519e92ced ]---
Call trace:
[<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
[<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
[<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
[<ffffffc00008291c>] do_one_initcall+0x90/0x194
[<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
[<ffffffc000636bb0>] kernel_init+0x10/0xdc
[<ffffffc000085cd0>] ret_from_fork+0x10/0x40
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out2
------------[ cut here ]------------
pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 849be30b52bf..791215747863 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2739,8 +2739,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
- { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
- { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock
@ 2015-12-21 12:56 ` Jon Hunter
0 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2015-12-21 12:56 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out1
------------[ cut here ]------------
WARNING: at drivers/clk/tegra/clk.c:269
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
PC is at tegra_init_from_table+0x140/0x164
LR is at tegra_init_from_table+0x140/0x164
pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
sp : ffffffc0bc0abd50
x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
x27: ffffffc000a06000 x26: ffffffc0bc019780
x25: ffffffc00086a708 x24: ffffffc00086a790
x23: ffffffc0006d7188 x22: ffffffc0bc010000
x21: 000000000000016e x20: ffffffc0bc00d100
x19: ffffffc000944178 x18: 0000000000000007
x17: 000000000000000e x16: 0000000000000001
x15: 0000000000000007 x14: 000000000000000e
x13: 0000000000000013 x12: 000000000000001a
x11: 000000000000004d x10: 0000000000000750
x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
x7 : 0000000000000001 x6 : 0000000002d5f0f8
x5 : 0000000000000000 x4 : 0000000000000000
x3 : 0000000000000002 x2 : ffffffc000996724
x1 : 0000000000000000 x0 : 0000000000000032
---[ end trace cbd20ae519e92ced ]---
Call trace:
[<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
[<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
[<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
[<ffffffc00008291c>] do_one_initcall+0x90/0x194
[<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
[<ffffffc000636bb0>] kernel_init+0x10/0xdc
[<ffffffc000085cd0>] ret_from_fork+0x10/0x40
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out2
------------[ cut here ]------------
pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 849be30b52bf..791215747863 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2739,8 +2739,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
- { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
- { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2015-12-21 12:56 ` Jon Hunter
@ 2015-12-21 12:56 ` Jon Hunter
-1 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2015-12-21 12:56 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 791215747863..6f043c5e2394 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
/* PLLU_VCO */
val = readl(clk_base + pll_u_vco_params.base_reg);
- val &= ~BIT(24); /* disable PLLU_OVERRIDE */
+ val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
writel(val, clk_base + pll_u_vco_params.base_reg);
clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2015-12-21 12:56 ` Jon Hunter
0 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2015-12-21 12:56 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: Rhyland Klein, linux-clk, linux-tegra, linux-kernel, Jon Hunter
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 791215747863..6f043c5e2394 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
/* PLLU_VCO */
val = readl(clk_base + pll_u_vco_params.base_reg);
- val &= ~BIT(24); /* disable PLLU_OVERRIDE */
+ val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
writel(val, clk_base + pll_u_vco_params.base_reg);
clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
--
2.1.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock
2015-12-21 12:56 ` Jon Hunter
@ 2015-12-21 16:37 ` Rhyland Klein
-1 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2015-12-21 16:37 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 12/21/2015 7:56 AM, Jon Hunter wrote:
> If the pll_u is not configured by the bootloader, then on kernel boot the
> following warning is seen:
>
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out1
> ------------[ cut here ]------------
> WARNING: at drivers/clk/tegra/clk.c:269
> Modules linked in:
>
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
> Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
> task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
> PC is at tegra_init_from_table+0x140/0x164
> LR is at tegra_init_from_table+0x140/0x164
> pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
> sp : ffffffc0bc0abd50
> x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
> x27: ffffffc000a06000 x26: ffffffc0bc019780
> x25: ffffffc00086a708 x24: ffffffc00086a790
> x23: ffffffc0006d7188 x22: ffffffc0bc010000
> x21: 000000000000016e x20: ffffffc0bc00d100
> x19: ffffffc000944178 x18: 0000000000000007
> x17: 000000000000000e x16: 0000000000000001
> x15: 0000000000000007 x14: 000000000000000e
> x13: 0000000000000013 x12: 000000000000001a
> x11: 000000000000004d x10: 0000000000000750
> x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
> x7 : 0000000000000001 x6 : 0000000002d5f0f8
> x5 : 0000000000000000 x4 : 0000000000000000
> x3 : 0000000000000002 x2 : ffffffc000996724
> x1 : 0000000000000000 x0 : 0000000000000032
>
> ---[ end trace cbd20ae519e92ced ]---
> Call trace:
> [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
> [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
> [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
> [<ffffffc00008291c>] do_one_initcall+0x90/0x194
> [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
> [<ffffffc000636bb0>] kernel_init+0x10/0xdc
> [<ffffffc000085cd0>] ret_from_fork+0x10/0x40
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out2
> ------------[ cut here ]------------
>
> pll_u can be either controlled by software or hardware and this is
> selected via the OVERRIDE bit in the pll_u base register. In the function
> tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
> hardware control of the pll. However, at the same time the pll_u clocks
> are populated in the init_table for tegra210 and so software will try to
> configure the pll_u if it is not already configured and hence, the above
> warning is seen when the pll fails to lock. Remove the pll_u clocks from
> the init_table so that software does not try to configure this pll on
> boot.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 849be30b52bf..791215747863 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2739,8 +2739,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
> { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
> { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
> { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
> - { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
> - { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
> { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
> { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
> { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
>
Acked-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock
@ 2015-12-21 16:37 ` Rhyland Klein
0 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2015-12-21 16:37 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk, linux-tegra, linux-kernel
On 12/21/2015 7:56 AM, Jon Hunter wrote:
> If the pll_u is not configured by the bootloader, then on kernel boot the
> following warning is seen:
>
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out1
> ------------[ cut here ]------------
> WARNING: at drivers/clk/tegra/clk.c:269
> Modules linked in:
>
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
> Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
> task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
> PC is at tegra_init_from_table+0x140/0x164
> LR is at tegra_init_from_table+0x140/0x164
> pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
> sp : ffffffc0bc0abd50
> x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
> x27: ffffffc000a06000 x26: ffffffc0bc019780
> x25: ffffffc00086a708 x24: ffffffc00086a790
> x23: ffffffc0006d7188 x22: ffffffc0bc010000
> x21: 000000000000016e x20: ffffffc0bc00d100
> x19: ffffffc000944178 x18: 0000000000000007
> x17: 000000000000000e x16: 0000000000000001
> x15: 0000000000000007 x14: 000000000000000e
> x13: 0000000000000013 x12: 000000000000001a
> x11: 000000000000004d x10: 0000000000000750
> x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
> x7 : 0000000000000001 x6 : 0000000002d5f0f8
> x5 : 0000000000000000 x4 : 0000000000000000
> x3 : 0000000000000002 x2 : ffffffc000996724
> x1 : 0000000000000000 x0 : 0000000000000032
>
> ---[ end trace cbd20ae519e92ced ]---
> Call trace:
> [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
> [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
> [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
> [<ffffffc00008291c>] do_one_initcall+0x90/0x194
> [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
> [<ffffffc000636bb0>] kernel_init+0x10/0xdc
> [<ffffffc000085cd0>] ret_from_fork+0x10/0x40
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out2
> ------------[ cut here ]------------
>
> pll_u can be either controlled by software or hardware and this is
> selected via the OVERRIDE bit in the pll_u base register. In the function
> tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
> hardware control of the pll. However, at the same time the pll_u clocks
> are populated in the init_table for tegra210 and so software will try to
> configure the pll_u if it is not already configured and hence, the above
> warning is seen when the pll fails to lock. Remove the pll_u clocks from
> the init_table so that software does not try to configure this pll on
> boot.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 849be30b52bf..791215747863 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2739,8 +2739,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
> { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
> { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
> { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
> - { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
> - { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
> { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
> { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
> { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2015-12-21 12:56 ` Jon Hunter
@ 2015-12-21 16:38 ` Rhyland Klein
-1 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2015-12-21 16:38 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk, linux-tegra, linux-kernel
On 12/21/2015 7:56 AM, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 791215747863..6f043c5e2394 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>
> /* PLLU_VCO */
> val = readl(clk_base + pll_u_vco_params.base_reg);
> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2015-12-21 16:38 ` Rhyland Klein
0 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2015-12-21 16:38 UTC (permalink / raw)
To: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-clk, linux-tegra, linux-kernel
On 12/21/2015 7:56 AM, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 791215747863..6f043c5e2394 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>
> /* PLLU_VCO */
> val = readl(clk_base + pll_u_vco_params.base_reg);
> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2015-12-21 12:56 ` Jon Hunter
@ 2016-01-13 16:08 ` Thierry Reding
-1 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2016-01-13 16:08 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 1406 bytes --]
On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>
> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 791215747863..6f043c5e2394 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>
> /* PLLU_VCO */
> val = readl(clk_base + pll_u_vco_params.base_reg);
> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
I think the comment is now redundant, given that the code says pretty
much the same thing. No need to respin for that, I can remove the
comment when I apply the patch. That is, unless anyone feels strongly
about keeping the comment.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2016-01-13 16:08 ` Thierry Reding
0 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2016-01-13 16:08 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1377 bytes --]
On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 791215747863..6f043c5e2394 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>
> /* PLLU_VCO */
> val = readl(clk_base + pll_u_vco_params.base_reg);
> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> writel(val, clk_base + pll_u_vco_params.base_reg);
>
> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
I think the comment is now redundant, given that the code says pretty
much the same thing. No need to respin for that, I can remove the
comment when I apply the patch. That is, unless anyone feels strongly
about keeping the comment.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2016-01-13 16:08 ` Thierry Reding
@ 2016-01-13 16:10 ` Rhyland Klein
-1 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2016-01-13 16:10 UTC (permalink / raw)
To: Thierry Reding, Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
On 1/13/2016 11:08 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>
>> /* PLLU_VCO */
>> val = readl(clk_base + pll_u_vco_params.base_reg);
>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>
>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.
I agree its redundant. If I am going to post a new version to address
other concerns, I can just roll this in while doing so.
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2016-01-13 16:10 ` Rhyland Klein
0 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2016-01-13 16:10 UTC (permalink / raw)
To: Thierry Reding, Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, linux-clk,
linux-tegra, linux-kernel
On 1/13/2016 11:08 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>
>> /* PLLU_VCO */
>> val = readl(clk_base + pll_u_vco_params.base_reg);
>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>
>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.
I agree its redundant. If I am going to post a new version to address
other concerns, I can just roll this in while doing so.
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2016-01-13 16:10 ` Rhyland Klein
(?)
@ 2016-01-13 16:19 ` Thierry Reding
2016-01-13 16:28 ` Rhyland Klein
-1 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2016-01-13 16:19 UTC (permalink / raw)
To: Rhyland Klein
Cc: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren,
Alexandre Courbot, linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1907 bytes --]
On Wed, Jan 13, 2016 at 11:10:53AM -0500, Rhyland Klein wrote:
> On 1/13/2016 11:08 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> >
> > On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> >> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> >> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> >> the code directly uses the bit number. Therefore, use the definition,
> >> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
> >>
> >> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> >> ---
> >> drivers/clk/tegra/clk-tegra210.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> >> index 791215747863..6f043c5e2394 100644
> >> --- a/drivers/clk/tegra/clk-tegra210.c
> >> +++ b/drivers/clk/tegra/clk-tegra210.c
> >> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
> >>
> >> /* PLLU_VCO */
> >> val = readl(clk_base + pll_u_vco_params.base_reg);
> >> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> >> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> >> writel(val, clk_base + pll_u_vco_params.base_reg);
> >>
> >> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
> >
> > I think the comment is now redundant, given that the code says pretty
> > much the same thing. No need to respin for that, I can remove the
> > comment when I apply the patch. That is, unless anyone feels strongly
> > about keeping the comment.
>
> I agree its redundant. If I am going to post a new version to address
> other concerns, I can just roll this in while doing so.
This looks like a good fix, or cleanup, on its own. So no need for
anyone to carry this forward, I can pick it up into a fixes branch
for v4.5.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2016-01-13 16:08 ` Thierry Reding
@ 2016-01-13 16:26 ` Jon Hunter
-1 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2016-01-13 16:26 UTC (permalink / raw)
To: Thierry Reding
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 13/01/16 16:08, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>
>> /* PLLU_VCO */
>> val = readl(clk_base + pll_u_vco_params.base_reg);
>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>
>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.
Fine with me. Thanks.
Jon
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2016-01-13 16:26 ` Jon Hunter
0 siblings, 0 replies; 19+ messages in thread
From: Jon Hunter @ 2016-01-13 16:26 UTC (permalink / raw)
To: Thierry Reding
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk, linux-tegra, linux-kernel
On 13/01/16 16:08, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>
>> /* PLLU_VCO */
>> val = readl(clk_base + pll_u_vco_params.base_reg);
>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>
>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.
Fine with me. Thanks.
Jon
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2016-01-13 16:19 ` Thierry Reding
@ 2016-01-13 16:28 ` Rhyland Klein
0 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2016-01-13 16:28 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren,
Alexandre Courbot, linux-clk, linux-tegra, linux-kernel
On 1/13/2016 11:19 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Wed, Jan 13, 2016 at 11:10:53AM -0500, Rhyland Klein wrote:
>> On 1/13/2016 11:08 AM, Thierry Reding wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>>>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>>>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>>>> the code directly uses the bit number. Therefore, use the definition,
>>>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>>>
>>>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>> index 791215747863..6f043c5e2394 100644
>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>>>
>>>> /* PLLU_VCO */
>>>> val = readl(clk_base + pll_u_vco_params.base_reg);
>>>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>>>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>>>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>>>
>>>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>>>
>>> I think the comment is now redundant, given that the code says pretty
>>> much the same thing. No need to respin for that, I can remove the
>>> comment when I apply the patch. That is, unless anyone feels strongly
>>> about keeping the comment.
>>
>> I agree its redundant. If I am going to post a new version to address
>> other concerns, I can just roll this in while doing so.
>
> This looks like a good fix, or cleanup, on its own. So no need for
> anyone to carry this forward, I can pick it up into a fixes branch
> for v4.5.
>
Sure thing.
Thanks,
Rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
@ 2016-01-13 16:28 ` Rhyland Klein
0 siblings, 0 replies; 19+ messages in thread
From: Rhyland Klein @ 2016-01-13 16:28 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Peter De Schrijver, Prashant Gaikwad,
Michael Turquette, Stephen Boyd, Stephen Warren,
Alexandre Courbot, linux-clk, linux-tegra, linux-kernel
On 1/13/2016 11:19 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Wed, Jan 13, 2016 at 11:10:53AM -0500, Rhyland Klein wrote:
>> On 1/13/2016 11:08 AM, Thierry Reding wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>>>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>>>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>>>> the code directly uses the bit number. Therefore, use the definition,
>>>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>>>
>>>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-tegra210.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>> index 791215747863..6f043c5e2394 100644
>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>>>
>>>> /* PLLU_VCO */
>>>> val = readl(clk_base + pll_u_vco_params.base_reg);
>>>> - val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>>>> + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>>>> writel(val, clk_base + pll_u_vco_params.base_reg);
>>>>
>>>> clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>>>
>>> I think the comment is now redundant, given that the code says pretty
>>> much the same thing. No need to respin for that, I can remove the
>>> comment when I apply the patch. That is, unless anyone feels strongly
>>> about keeping the comment.
>>
>> I agree its redundant. If I am going to post a new version to address
>> other concerns, I can just roll this in while doing so.
>
> This looks like a good fix, or cleanup, on its own. So no need for
> anyone to carry this forward, I can pick it up into a fixes branch
> for v4.5.
>
Sure thing.
Thanks,
Rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock
2015-12-21 12:56 ` Jon Hunter
` (2 preceding siblings ...)
(?)
@ 2016-01-13 17:10 ` Thierry Reding
-1 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2016-01-13 17:10 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2942 bytes --]
On Mon, Dec 21, 2015 at 12:56:31PM +0000, Jon Hunter wrote:
> If the pll_u is not configured by the bootloader, then on kernel boot the
> following warning is seen:
>
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out1
> ------------[ cut here ]------------
> WARNING: at drivers/clk/tegra/clk.c:269
> Modules linked in:
>
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
> Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
> task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
> PC is at tegra_init_from_table+0x140/0x164
> LR is at tegra_init_from_table+0x140/0x164
> pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
> sp : ffffffc0bc0abd50
> x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
> x27: ffffffc000a06000 x26: ffffffc0bc019780
> x25: ffffffc00086a708 x24: ffffffc00086a790
> x23: ffffffc0006d7188 x22: ffffffc0bc010000
> x21: 000000000000016e x20: ffffffc0bc00d100
> x19: ffffffc000944178 x18: 0000000000000007
> x17: 000000000000000e x16: 0000000000000001
> x15: 0000000000000007 x14: 000000000000000e
> x13: 0000000000000013 x12: 000000000000001a
> x11: 000000000000004d x10: 0000000000000750
> x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
> x7 : 0000000000000001 x6 : 0000000002d5f0f8
> x5 : 0000000000000000 x4 : 0000000000000000
> x3 : 0000000000000002 x2 : ffffffc000996724
> x1 : 0000000000000000 x0 : 0000000000000032
>
> ---[ end trace cbd20ae519e92ced ]---
> Call trace:
> [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
> [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
> [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
> [<ffffffc00008291c>] do_one_initcall+0x90/0x194
> [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
> [<ffffffc000636bb0>] kernel_init+0x10/0xdc
> [<ffffffc000085cd0>] ret_from_fork+0x10/0x40
> clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
> tegra_init_from_table: Failed to enable pll_u_out2
> ------------[ cut here ]------------
>
> pll_u can be either controlled by software or hardware and this is
> selected via the OVERRIDE bit in the pll_u base register. In the function
> tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
> hardware control of the pll. However, at the same time the pll_u clocks
> are populated in the init_table for tegra210 and so software will try to
> configure the pll_u if it is not already configured and hence, the above
> warning is seen when the pll fails to lock. Remove the pll_u clocks from
> the init_table so that software does not try to configure this pll on
> boot.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 --
> 1 file changed, 2 deletions(-)
Applied, thanks.
Thierry
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
2015-12-21 12:56 ` Jon Hunter
` (2 preceding siblings ...)
(?)
@ 2016-01-13 17:10 ` Thierry Reding
-1 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2016-01-13 17:10 UTC (permalink / raw)
To: Jon Hunter
Cc: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Stephen Warren, Alexandre Courbot, Rhyland Klein,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 569 bytes --]
On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied with the now redundant comment removed.
Thanks,
Thierry
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^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2016-01-13 17:10 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-21 12:56 [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock Jon Hunter
2015-12-21 12:56 ` Jon Hunter
2015-12-21 12:56 ` [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Jon Hunter
2015-12-21 12:56 ` Jon Hunter
2015-12-21 16:38 ` Rhyland Klein
2015-12-21 16:38 ` Rhyland Klein
[not found] ` <1450702592-7755-2-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-13 16:08 ` Thierry Reding
2016-01-13 16:08 ` Thierry Reding
2016-01-13 16:10 ` Rhyland Klein
2016-01-13 16:10 ` Rhyland Klein
2016-01-13 16:19 ` Thierry Reding
2016-01-13 16:28 ` Rhyland Klein
2016-01-13 16:28 ` Rhyland Klein
2016-01-13 16:26 ` Jon Hunter
2016-01-13 16:26 ` Jon Hunter
2016-01-13 17:10 ` Thierry Reding
[not found] ` <1450702592-7755-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-21 16:37 ` [PATCH 1/2] clk: tegra: Fix warning caused by pll_u failing to lock Rhyland Klein
2015-12-21 16:37 ` Rhyland Klein
2016-01-13 17:10 ` Thierry Reding
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