* [rtc-linux] [PATCH V3 0/5] Add support for MAXIM MAX77620/MAX20024 PMIC
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan
Add SW support for MAXIM Semiconductor's Power Management
IC (PMIC) MAX77620/MAX20024. This PMIC supports DC-DC/LDOS, GPIOs,
RTC, watchdog, clocks etc.
This series add respective driver for each of sub-modules.
---
Changes from V1:
DT DOC:
- Added units in some of properties.
- Change the boolean property to tristate type and detail some of
properties.
RTC:
- Rename the file to rtc-max77xxx.c and make the generic implementation.
- Direct regmap apis are used for the register access.
- Decouped from max77620 driver.
- Taken care of cleanup comments form V1 version.
MFD:
- Code cleanups per review from V1.
- Move register acccess APIs from header to c file.
- Remove some of non required variable, remove duplication in error message
and simplify some of function implementation.
GPIO:
- Use the gpiochip_add_data and get the chip data from core APIs.
- Cleanups based on comment received on mfd/rtc.
- Avoid duplication on error message.
Pinctrl:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Regulators:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
- Taken care of review comment from Mark.
Changes from V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Drop RTC driver and its i2c client registartion.
- Refactor Regulator driver to use core API for DT parsing.
Laxman Dewangan (5):
DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
mfd: max77620: add core driver for MAX77620/MAX20024
pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
gpio: max77620: add gpio driver for MAX77620/MAX20024
regulator: max77620: add regulator driver for max77620/max20024
Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-max77620.c | 302 +++++++
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/max77620.c | 898 +++++++++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-max77620.c | 703 ++++++++++++++++
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77620-regulator.c | 892 ++++++++++++++++++++
include/dt-bindings/mfd/max77620.h | 38 +
include/linux/mfd/max77620.h | 402 +++++++++
15 files changed, 3679 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 drivers/gpio/gpio-max77620.c
create mode 100644 drivers/mfd/max77620.c
create mode 100644 drivers/pinctrl/pinctrl-max77620.c
create mode 100644 drivers/regulator/max77620-regulator.c
create mode 100644 include/dt-bindings/mfd/max77620.h
create mode 100644 include/linux/mfd/max77620.h
--
2.1.4
--
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH V3 0/5] Add support for MAXIM MAX77620/MAX20024 PMIC
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan
Add SW support for MAXIM Semiconductor's Power Management
IC (PMIC) MAX77620/MAX20024. This PMIC supports DC-DC/LDOS, GPIOs,
RTC, watchdog, clocks etc.
This series add respective driver for each of sub-modules.
---
Changes from V1:
DT DOC:
- Added units in some of properties.
- Change the boolean property to tristate type and detail some of
properties.
RTC:
- Rename the file to rtc-max77xxx.c and make the generic implementation.
- Direct regmap apis are used for the register access.
- Decouped from max77620 driver.
- Taken care of cleanup comments form V1 version.
MFD:
- Code cleanups per review from V1.
- Move register acccess APIs from header to c file.
- Remove some of non required variable, remove duplication in error message
and simplify some of function implementation.
GPIO:
- Use the gpiochip_add_data and get the chip data from core APIs.
- Cleanups based on comment received on mfd/rtc.
- Avoid duplication on error message.
Pinctrl:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Regulators:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
- Taken care of review comment from Mark.
Changes from V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Drop RTC driver and its i2c client registartion.
- Refactor Regulator driver to use core API for DT parsing.
Laxman Dewangan (5):
DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
mfd: max77620: add core driver for MAX77620/MAX20024
pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
gpio: max77620: add gpio driver for MAX77620/MAX20024
regulator: max77620: add regulator driver for max77620/max20024
Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-max77620.c | 302 +++++++
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/max77620.c | 898 +++++++++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-max77620.c | 703 ++++++++++++++++
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77620-regulator.c | 892 ++++++++++++++++++++
include/dt-bindings/mfd/max77620.h | 38 +
include/linux/mfd/max77620.h | 402 +++++++++
15 files changed, 3679 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 drivers/gpio/gpio-max77620.c
create mode 100644 drivers/mfd/max77620.c
create mode 100644 drivers/pinctrl/pinctrl-max77620.c
create mode 100644 drivers/regulator/max77620-regulator.c
create mode 100644 include/dt-bindings/mfd/max77620.h
create mode 100644 include/linux/mfd/max77620.h
--
2.1.4
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-14 11:32 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan
The MAXIM PMIC MAX77620 and MAX20024 are power management IC
which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
watchdog etc.
Add DT binding document for the different functionality of
this device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Added units in some of properties.
- Change the boolean property to tristate type and detail some of
properties.
Change from V2:
- added unit in period related dt property.
Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++++++++++++++
include/dt-bindings/mfd/max77620.h | 38 ++
2 files changed, 435 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 include/dt-bindings/mfd/max77620.h
diff --git a/Documentation/devicetree/bindings/mfd/max77620.txt b/Documentation/devicetree/bindings/mfd/max77620.txt
new file mode 100644
index 0000000..46f6aac
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77620.txt
@@ -0,0 +1,397 @@
+* MAX77620 Power management IC from Maxim Semiconductor.
+
+Required properties:
+-------------------
+- compatible: Must be one of
+ "maxim,max77620" or
+ "maxim,max20024".
+- reg: I2C device address.
+- interrupt-controller: MAX77620 has internal interrupt controller which
+ takes the interrupt request from internal sub-blocks like RTC,
+ regulators, GPIOs as well as external input.
+- #interrupt-cells: Should be set to 2 for IRQ number and flags.
+ The first cell is the IRQ number. IRQ numbers for different interrupt
+ source of MAX77620 are defined at dt-bindings/mfd/max77620.h
+ The second cell is the flags, encoded as the trigger masks from binding
+ document interrupts.txt, using dt-bindings/irq.
+
+Optional properties:
+-------------------
+This device also supports the power OFF of system.
+Following properties are used for this purpose:
+- system-power-controller: Boolean, This device will be use as
+ system power controller and used for power OFF of system.
+ Host issue necessary command to PMIC.
+
+
+Optional submodule and their properties:
+=======================================
+
+Flexible power sequence configuration
+====================================
+This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
+power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
+FPS1 and FPS2. The details of FPS configuration is provided through
+subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
+child node under this subnodes. The FPS number is provided via reg property.
+
+The property for fps child nodes as:
+Required properties:
+ -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
+Optinal properties:
+ -maxim,active-fps-time-period-us: Active state FPS time period in
+ microseconds.
+ -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
+ microseconds.
+ -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
+ macros are defined on dt-bindings/mfd/max77620.h for
+ different enable source.
+ FPS_EN_SRC_EN0 for EN0 enable source.
+ FPS_EN_SRC_EN1 for En1 enable source.
+ FPS_EN_SRC_SW for SW based control.
+ -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
+ If this property present then enable the FPS else
+ disable FPS.
+ -maxim,enable-sleep: Boolean, enable sleep when the external control
+ goes from HIGH to LOW.
+ -maxim,enable-global-lpm: Boolean, enable global LPM when the external
+ control goes from HIGH to LOW.
+
+Here supported time periods by device in microseconds are as follows:
+MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
+MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
+
+Pinmux and GPIO:
+===============
+Device has 8 GPIO pins which can be configured as GPIO as well as the
+special IO functions.
+
+Please refer to pinctrl-bindings.txt for details of the common pinctrl
+bindings used by client devices, including the meaning of the phrase
+"pin configuration node".
+
+Following are properties which is needed if GPIO and pinmux functionality
+is required:
+ Required properties:
+ -------------------
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Number of GPIO cells. Refer to binding document
+ gpio/gpio.txt
+
+ Optional properties:
+ --------------------
+ Following properties are require if pin control setting is required
+ at boot.
+ - pinctrl-names: A pinctrl state named "default" be defined, using
+ the bindings in pinctrl/pinctrl-binding.txt.
+ - pinctrl[0...n]: Properties to contain the phandle that refer to
+ different nodes of pin control settings. These nodes
+ represents the pin control setting of state 0 to state n.
+ Each of these nodes contains different subnodes to
+ represents some desired configuration for a list of pins.
+ This configuration can include the mux function to select
+ on those pin(s), and various pin configuration parameters,
+ such as pull-up, open drain.
+
+ Each subnode have following properties:
+ Required properties:
+ - pins: List of pins. Valid values of pins properties
+ are: gpio0, gpio1, gpio2, gpio3, gpio4,
+ gpio5, gpio6, gpio7
+
+ Optional properties:
+ function, drive-push-pull, drive-open-drain,
+ bias-pull-up, bias-pull-down.
+ Definitions are in the pinmux dt binding
+ devicetree/bindings/pinctrl/pinctrl-bindings.txt
+ Absence of properties will leave the configuration
+ on default.
+
+ Valid values for function properties are:
+ gpio, lpm-control-in, fps-out, 32k-out,
+ sd0-dvs-in, sd1-dvs-in, reference-out
+ Theres is also customised property for the GPIO1,
+ GPIO2 and GPIO3.
+ - maxim,active-fps-source: FPS source for the gpios in
+ active state of the GPIO. Valid values are
+ FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
+ FPS_SRC_NONE. Absence of this property will
+ leave the pin on default.
+ - maxim,active-fps-power-up-slot: Power up slot on
+ given FPS for acive state.Valid values are 0
+ to 7.
+ - maxim,active-fps-power-down-slot: Power down slot
+ on given FPS for active state. Valid values
+ are 0 t 7.
+ - maxim,suspend-fps-source: Suspend state FPS source.
+ - maxim,suspend-fps-power-down-slot: Suspend state
+ power down slot.
+ - maxim,suspend-fps-power-up-slot: Suspend state power
+ up slot.
+
+Regulators:
+===========
+Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The node "regulators"
+is require if regulator functionality is needed.
+
+Following are properties of regulator subnode.
+
+ Optional properties:
+ -------------------
+ The input supply of regulators are the optional properties on the
+ regulator node. The input supply of these regulators are provided
+ through following properties:
+ in-sd0-supply: Input supply for SD0, INA-SD0 or INB-SD0 pins.
+ in-sd1-supply: Input supply for SD1.
+ in-sd2-supply: Input supply for SD2.
+ in-sd3-supply: Input supply for SD3.
+ in-ldo0-1-supply: Input supply for LDO0 and LDO1.
+ in-ldo2-supply: Input supply for LDO2.
+ in-ldo3-5-supply: Input supply for LDO3 and LDO5
+ in-ldo4-6-supply: Input supply for LDO4 and LDO6.
+ in-ldo7-8-supply: Input supply for LDO7 and LDO8.
+
+
+ Optional sub nodes for regulators:
+ ---------------------------------
+ The subnodes name is the name of regulator and it must be one of:
+ sd[0-3], ldo[0-8]
+
+ Each sub-node should contain the constraints and initialization
+ information for that regulator. See regulator.txt for a description
+ of standard properties for these sub-nodes.
+ Additional optional custom properties are listed below.
+ maxim,active-fps-source: FPS source. The macros are defined at
+ dt-bindings/mfd/max77620.h
+ maxim,shutdown-fps-source: Same as maxim,fps-source, but it
+ will apply during shutdown of system.
+ maxim,active-fps-power-up-slot: Active state Power up slot for
+ rail on given FPS.
+ maxim,active-fps-power-down-slot: Active state Power down slot
+ for rail on given FPS.
+ maxim,suspend-fps-source: Suspend state FPS source of rail.
+ maxim,suspend-fps-power-up-slot: Suspend state FPS power
+ up slot.
+ maxim,suspend-fps-power-down-slot: Suspend state FPS power
+ down slot.
+ maxim,enable-group-low-power: Enable Group low power mode.
+ maxim,enable-sd0-en2-control: Enable EN2 pincontrol for SD0.
+ This property is only applicable for SD0.
+ maxim,disable-remote-sense-on-suspend: Boolean, disable
+ remote sense on suspend and re-enable on resume.
+ If this property is not there then no change on
+ configuration.
+
+Backup Battery:
+==============
+This sub-node configure charging backup battery of the device. Device
+has support of charging the backup battery. The subnode name is
+"backup-battery".
+
+The property for backup-battery child nodes as:
+Presense of this child node will enable the backup battery charging.
+
+Optinal properties:
+ -maxim,bb-charging-current-microamp: Charging current
+ setting.
+ The device supports 50/100/200/400/600/800uA.
+ If this property is unavailable then it will
+ charge with 50uA.
+ -maxim,bb-charging-voltage-microvolt: Charging Voltage Limit Setting.
+ Device supports 2500000/3000000/3300000/350000uV.
+ Default will be set to 2500mV. The voltage will be roundoff
+ to nearest lower side if other than above is configured.
+ -maxim,bb-output-resister-ohm: Output resistor on Ohm.
+ Device supports 100/1000/3000/6000 Ohms.
+
+Low-Battery Monitor:
+==================
+This sub-node configure low battery monitor configuration registers.
+Device has support for low-battery monitor configuration through
+child DT node "low-battery-monitor".
+
+Optinal properties:
+ - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-shutdown: Tristate, enable/disable low battery
+ shutdown.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ backup-battery {
+ maxim,bb-charging-current-microamp = <100>;
+ maxim,bb-charging-voltage-microvolt = <3000000>;
+ maxim,bb-output-resister-ohm = <100>;
+ };
+
+ fps {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fps@0 {
+ reg = <0>;
+ maxim,fps-time-period-us = <1280>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN0>;
+ };
+
+ fps@1 {
+ reg = <1>;
+ maxim,fps-time-period-us = <2560>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN1>;
+ };
+
+ fps@2 {
+ reg = <2>;
+ maxim,fps-time-period-us = <640>;
+ maxim,fps-enable-input = <FPS_EN_SRC_SW>;
+ };
+ };
+
+ regulators {
+ in-ldo0-1-supply = <&max77620_sd2>;
+ in-ldo7-8-supply = <&max77620_sd2>;
+
+ max77620_sd0: sd0 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_sd1: sd1 {
+ regulator-name = "vddio-ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_sd2: sd2 {
+ regulator-name = "vdd-pre-reg";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_sd3: sd3 {
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_ldo0: ldo0 {
+ regulator-name = "avdd-sys";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo1: ldo1 {
+ regulator-name = "vdd-pex";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo2: ldo2 {
+ regulator-name = "vddio-sdmmc3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo3: ldo3 {
+ regulator-name = "vdd-cam-hv";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo4: ldo4 {
+ regulator-name = "vdd-rtc";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_ldo5: ldo5 {
+ regulator-name = "avdd-ts-hv";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo6: ldo6 {
+ regulator-name = "vdd-ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo7: ldo7 {
+ regulator-name = "vdd-gen-pll-edp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_ldo8: ldo8 {
+ regulator-name = "vdd-hdmi-dp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+ };
+};
diff --git a/include/dt-bindings/mfd/max77620.h b/include/dt-bindings/mfd/max77620.h
new file mode 100644
index 0000000..8423d1d
--- /dev/null
+++ b/include/dt-bindings/mfd/max77620.h
@@ -0,0 +1,38 @@
+/*
+ * This header provides macros for MAXIM MAX77620 device bindings.
+ *
+ * Copyright (c) 2016, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_MFD_MAX77620_H
+#define _DT_BINDINGS_MFD_MAX77620_H
+
+/* MAX77620 interrupts */
+#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */
+#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */
+#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */
+#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */
+#define MAX77620_IRQ_TOP_RTC 4 /* RTC */
+#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */
+#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */
+#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */
+
+/* FPS enable -inputs */
+#define FPS_EN_SRC_EN0 0
+#define FPS_EN_SRC_EN1 1
+#define FPS_EN_SRC_SW 2
+#define FPS_EN_SRC_RSVD 3
+
+/* FPS source */
+#define FPS_SRC_0 0
+#define FPS_SRC_1 1
+#define FPS_SRC_2 2
+#define FPS_SRC_NONE 3
+#define FPS_SRC_DEF 4
+
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [rtc-linux] [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan
The MAXIM PMIC MAX77620 and MAX20024 are power management IC
which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
watchdog etc.
Add DT binding document for the different functionality of
this device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Added units in some of properties.
- Change the boolean property to tristate type and detail some of
properties.
Change from V2:
- added unit in period related dt property.
Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++++++++++++++
include/dt-bindings/mfd/max77620.h | 38 ++
2 files changed, 435 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 include/dt-bindings/mfd/max77620.h
diff --git a/Documentation/devicetree/bindings/mfd/max77620.txt b/Documentation/devicetree/bindings/mfd/max77620.txt
new file mode 100644
index 0000000..46f6aac
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77620.txt
@@ -0,0 +1,397 @@
+* MAX77620 Power management IC from Maxim Semiconductor.
+
+Required properties:
+-------------------
+- compatible: Must be one of
+ "maxim,max77620" or
+ "maxim,max20024".
+- reg: I2C device address.
+- interrupt-controller: MAX77620 has internal interrupt controller which
+ takes the interrupt request from internal sub-blocks like RTC,
+ regulators, GPIOs as well as external input.
+- #interrupt-cells: Should be set to 2 for IRQ number and flags.
+ The first cell is the IRQ number. IRQ numbers for different interrupt
+ source of MAX77620 are defined at dt-bindings/mfd/max77620.h
+ The second cell is the flags, encoded as the trigger masks from binding
+ document interrupts.txt, using dt-bindings/irq.
+
+Optional properties:
+-------------------
+This device also supports the power OFF of system.
+Following properties are used for this purpose:
+- system-power-controller: Boolean, This device will be use as
+ system power controller and used for power OFF of system.
+ Host issue necessary command to PMIC.
+
+
+Optional submodule and their properties:
+=======================================
+
+Flexible power sequence configuration
+====================================
+This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
+power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
+FPS1 and FPS2. The details of FPS configuration is provided through
+subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
+child node under this subnodes. The FPS number is provided via reg property.
+
+The property for fps child nodes as:
+Required properties:
+ -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
+Optinal properties:
+ -maxim,active-fps-time-period-us: Active state FPS time period in
+ microseconds.
+ -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
+ microseconds.
+ -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
+ macros are defined on dt-bindings/mfd/max77620.h for
+ different enable source.
+ FPS_EN_SRC_EN0 for EN0 enable source.
+ FPS_EN_SRC_EN1 for En1 enable source.
+ FPS_EN_SRC_SW for SW based control.
+ -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
+ If this property present then enable the FPS else
+ disable FPS.
+ -maxim,enable-sleep: Boolean, enable sleep when the external control
+ goes from HIGH to LOW.
+ -maxim,enable-global-lpm: Boolean, enable global LPM when the external
+ control goes from HIGH to LOW.
+
+Here supported time periods by device in microseconds are as follows:
+MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
+MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
+
+Pinmux and GPIO:
+===============
+Device has 8 GPIO pins which can be configured as GPIO as well as the
+special IO functions.
+
+Please refer to pinctrl-bindings.txt for details of the common pinctrl
+bindings used by client devices, including the meaning of the phrase
+"pin configuration node".
+
+Following are properties which is needed if GPIO and pinmux functionality
+is required:
+ Required properties:
+ -------------------
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Number of GPIO cells. Refer to binding document
+ gpio/gpio.txt
+
+ Optional properties:
+ --------------------
+ Following properties are require if pin control setting is required
+ at boot.
+ - pinctrl-names: A pinctrl state named "default" be defined, using
+ the bindings in pinctrl/pinctrl-binding.txt.
+ - pinctrl[0...n]: Properties to contain the phandle that refer to
+ different nodes of pin control settings. These nodes
+ represents the pin control setting of state 0 to state n.
+ Each of these nodes contains different subnodes to
+ represents some desired configuration for a list of pins.
+ This configuration can include the mux function to select
+ on those pin(s), and various pin configuration parameters,
+ such as pull-up, open drain.
+
+ Each subnode have following properties:
+ Required properties:
+ - pins: List of pins. Valid values of pins properties
+ are: gpio0, gpio1, gpio2, gpio3, gpio4,
+ gpio5, gpio6, gpio7
+
+ Optional properties:
+ function, drive-push-pull, drive-open-drain,
+ bias-pull-up, bias-pull-down.
+ Definitions are in the pinmux dt binding
+ devicetree/bindings/pinctrl/pinctrl-bindings.txt
+ Absence of properties will leave the configuration
+ on default.
+
+ Valid values for function properties are:
+ gpio, lpm-control-in, fps-out, 32k-out,
+ sd0-dvs-in, sd1-dvs-in, reference-out
+ Theres is also customised property for the GPIO1,
+ GPIO2 and GPIO3.
+ - maxim,active-fps-source: FPS source for the gpios in
+ active state of the GPIO. Valid values are
+ FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
+ FPS_SRC_NONE. Absence of this property will
+ leave the pin on default.
+ - maxim,active-fps-power-up-slot: Power up slot on
+ given FPS for acive state.Valid values are 0
+ to 7.
+ - maxim,active-fps-power-down-slot: Power down slot
+ on given FPS for active state. Valid values
+ are 0 t 7.
+ - maxim,suspend-fps-source: Suspend state FPS source.
+ - maxim,suspend-fps-power-down-slot: Suspend state
+ power down slot.
+ - maxim,suspend-fps-power-up-slot: Suspend state power
+ up slot.
+
+Regulators:
+===========
+Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The node "regulators"
+is require if regulator functionality is needed.
+
+Following are properties of regulator subnode.
+
+ Optional properties:
+ -------------------
+ The input supply of regulators are the optional properties on the
+ regulator node. The input supply of these regulators are provided
+ through following properties:
+ in-sd0-supply: Input supply for SD0, INA-SD0 or INB-SD0 pins.
+ in-sd1-supply: Input supply for SD1.
+ in-sd2-supply: Input supply for SD2.
+ in-sd3-supply: Input supply for SD3.
+ in-ldo0-1-supply: Input supply for LDO0 and LDO1.
+ in-ldo2-supply: Input supply for LDO2.
+ in-ldo3-5-supply: Input supply for LDO3 and LDO5
+ in-ldo4-6-supply: Input supply for LDO4 and LDO6.
+ in-ldo7-8-supply: Input supply for LDO7 and LDO8.
+
+
+ Optional sub nodes for regulators:
+ ---------------------------------
+ The subnodes name is the name of regulator and it must be one of:
+ sd[0-3], ldo[0-8]
+
+ Each sub-node should contain the constraints and initialization
+ information for that regulator. See regulator.txt for a description
+ of standard properties for these sub-nodes.
+ Additional optional custom properties are listed below.
+ maxim,active-fps-source: FPS source. The macros are defined at
+ dt-bindings/mfd/max77620.h
+ maxim,shutdown-fps-source: Same as maxim,fps-source, but it
+ will apply during shutdown of system.
+ maxim,active-fps-power-up-slot: Active state Power up slot for
+ rail on given FPS.
+ maxim,active-fps-power-down-slot: Active state Power down slot
+ for rail on given FPS.
+ maxim,suspend-fps-source: Suspend state FPS source of rail.
+ maxim,suspend-fps-power-up-slot: Suspend state FPS power
+ up slot.
+ maxim,suspend-fps-power-down-slot: Suspend state FPS power
+ down slot.
+ maxim,enable-group-low-power: Enable Group low power mode.
+ maxim,enable-sd0-en2-control: Enable EN2 pincontrol for SD0.
+ This property is only applicable for SD0.
+ maxim,disable-remote-sense-on-suspend: Boolean, disable
+ remote sense on suspend and re-enable on resume.
+ If this property is not there then no change on
+ configuration.
+
+Backup Battery:
+==============
+This sub-node configure charging backup battery of the device. Device
+has support of charging the backup battery. The subnode name is
+"backup-battery".
+
+The property for backup-battery child nodes as:
+Presense of this child node will enable the backup battery charging.
+
+Optinal properties:
+ -maxim,bb-charging-current-microamp: Charging current
+ setting.
+ The device supports 50/100/200/400/600/800uA.
+ If this property is unavailable then it will
+ charge with 50uA.
+ -maxim,bb-charging-voltage-microvolt: Charging Voltage Limit Setting.
+ Device supports 2500000/3000000/3300000/350000uV.
+ Default will be set to 2500mV. The voltage will be roundoff
+ to nearest lower side if other than above is configured.
+ -maxim,bb-output-resister-ohm: Output resistor on Ohm.
+ Device supports 100/1000/3000/6000 Ohms.
+
+Low-Battery Monitor:
+==================
+This sub-node configure low battery monitor configuration registers.
+Device has support for low-battery monitor configuration through
+child DT node "low-battery-monitor".
+
+Optinal properties:
+ - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-shutdown: Tristate, enable/disable low battery
+ shutdown.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ backup-battery {
+ maxim,bb-charging-current-microamp = <100>;
+ maxim,bb-charging-voltage-microvolt = <3000000>;
+ maxim,bb-output-resister-ohm = <100>;
+ };
+
+ fps {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fps@0 {
+ reg = <0>;
+ maxim,fps-time-period-us = <1280>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN0>;
+ };
+
+ fps@1 {
+ reg = <1>;
+ maxim,fps-time-period-us = <2560>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN1>;
+ };
+
+ fps@2 {
+ reg = <2>;
+ maxim,fps-time-period-us = <640>;
+ maxim,fps-enable-input = <FPS_EN_SRC_SW>;
+ };
+ };
+
+ regulators {
+ in-ldo0-1-supply = <&max77620_sd2>;
+ in-ldo7-8-supply = <&max77620_sd2>;
+
+ max77620_sd0: sd0 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_sd1: sd1 {
+ regulator-name = "vddio-ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_sd2: sd2 {
+ regulator-name = "vdd-pre-reg";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_sd3: sd3 {
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_ldo0: ldo0 {
+ regulator-name = "avdd-sys";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo1: ldo1 {
+ regulator-name = "vdd-pex";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo2: ldo2 {
+ regulator-name = "vddio-sdmmc3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo3: ldo3 {
+ regulator-name = "vdd-cam-hv";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo4: ldo4 {
+ regulator-name = "vdd-rtc";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_ldo5: ldo5 {
+ regulator-name = "avdd-ts-hv";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo6: ldo6 {
+ regulator-name = "vdd-ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo7: ldo7 {
+ regulator-name = "vdd-gen-pll-edp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_ldo8: ldo8 {
+ regulator-name = "vdd-hdmi-dp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+ };
+};
diff --git a/include/dt-bindings/mfd/max77620.h b/include/dt-bindings/mfd/max77620.h
new file mode 100644
index 0000000..8423d1d
--- /dev/null
+++ b/include/dt-bindings/mfd/max77620.h
@@ -0,0 +1,38 @@
+/*
+ * This header provides macros for MAXIM MAX77620 device bindings.
+ *
+ * Copyright (c) 2016, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_MFD_MAX77620_H
+#define _DT_BINDINGS_MFD_MAX77620_H
+
+/* MAX77620 interrupts */
+#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */
+#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */
+#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */
+#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */
+#define MAX77620_IRQ_TOP_RTC 4 /* RTC */
+#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */
+#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */
+#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */
+
+/* FPS enable -inputs */
+#define FPS_EN_SRC_EN0 0
+#define FPS_EN_SRC_EN1 1
+#define FPS_EN_SRC_SW 2
+#define FPS_EN_SRC_RSVD 3
+
+/* FPS source */
+#define FPS_SRC_0 0
+#define FPS_SRC_1 1
+#define FPS_SRC_2 2
+#define FPS_SRC_NONE 3
+#define FPS_SRC_DEF 4
+
+#endif
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan
The MAXIM PMIC MAX77620 and MAX20024 are power management IC
which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
watchdog etc.
Add DT binding document for the different functionality of
this device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Added units in some of properties.
- Change the boolean property to tristate type and detail some of
properties.
Change from V2:
- added unit in period related dt property.
Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++++++++++++++
include/dt-bindings/mfd/max77620.h | 38 ++
2 files changed, 435 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
create mode 100644 include/dt-bindings/mfd/max77620.h
diff --git a/Documentation/devicetree/bindings/mfd/max77620.txt b/Documentation/devicetree/bindings/mfd/max77620.txt
new file mode 100644
index 0000000..46f6aac
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77620.txt
@@ -0,0 +1,397 @@
+* MAX77620 Power management IC from Maxim Semiconductor.
+
+Required properties:
+-------------------
+- compatible: Must be one of
+ "maxim,max77620" or
+ "maxim,max20024".
+- reg: I2C device address.
+- interrupt-controller: MAX77620 has internal interrupt controller which
+ takes the interrupt request from internal sub-blocks like RTC,
+ regulators, GPIOs as well as external input.
+- #interrupt-cells: Should be set to 2 for IRQ number and flags.
+ The first cell is the IRQ number. IRQ numbers for different interrupt
+ source of MAX77620 are defined at dt-bindings/mfd/max77620.h
+ The second cell is the flags, encoded as the trigger masks from binding
+ document interrupts.txt, using dt-bindings/irq.
+
+Optional properties:
+-------------------
+This device also supports the power OFF of system.
+Following properties are used for this purpose:
+- system-power-controller: Boolean, This device will be use as
+ system power controller and used for power OFF of system.
+ Host issue necessary command to PMIC.
+
+
+Optional submodule and their properties:
+=======================================
+
+Flexible power sequence configuration
+====================================
+This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
+power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
+FPS1 and FPS2. The details of FPS configuration is provided through
+subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
+child node under this subnodes. The FPS number is provided via reg property.
+
+The property for fps child nodes as:
+Required properties:
+ -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
+Optinal properties:
+ -maxim,active-fps-time-period-us: Active state FPS time period in
+ microseconds.
+ -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
+ microseconds.
+ -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
+ macros are defined on dt-bindings/mfd/max77620.h for
+ different enable source.
+ FPS_EN_SRC_EN0 for EN0 enable source.
+ FPS_EN_SRC_EN1 for En1 enable source.
+ FPS_EN_SRC_SW for SW based control.
+ -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
+ If this property present then enable the FPS else
+ disable FPS.
+ -maxim,enable-sleep: Boolean, enable sleep when the external control
+ goes from HIGH to LOW.
+ -maxim,enable-global-lpm: Boolean, enable global LPM when the external
+ control goes from HIGH to LOW.
+
+Here supported time periods by device in microseconds are as follows:
+MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
+MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
+
+Pinmux and GPIO:
+===============
+Device has 8 GPIO pins which can be configured as GPIO as well as the
+special IO functions.
+
+Please refer to pinctrl-bindings.txt for details of the common pinctrl
+bindings used by client devices, including the meaning of the phrase
+"pin configuration node".
+
+Following are properties which is needed if GPIO and pinmux functionality
+is required:
+ Required properties:
+ -------------------
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Number of GPIO cells. Refer to binding document
+ gpio/gpio.txt
+
+ Optional properties:
+ --------------------
+ Following properties are require if pin control setting is required
+ at boot.
+ - pinctrl-names: A pinctrl state named "default" be defined, using
+ the bindings in pinctrl/pinctrl-binding.txt.
+ - pinctrl[0...n]: Properties to contain the phandle that refer to
+ different nodes of pin control settings. These nodes
+ represents the pin control setting of state 0 to state n.
+ Each of these nodes contains different subnodes to
+ represents some desired configuration for a list of pins.
+ This configuration can include the mux function to select
+ on those pin(s), and various pin configuration parameters,
+ such as pull-up, open drain.
+
+ Each subnode have following properties:
+ Required properties:
+ - pins: List of pins. Valid values of pins properties
+ are: gpio0, gpio1, gpio2, gpio3, gpio4,
+ gpio5, gpio6, gpio7
+
+ Optional properties:
+ function, drive-push-pull, drive-open-drain,
+ bias-pull-up, bias-pull-down.
+ Definitions are in the pinmux dt binding
+ devicetree/bindings/pinctrl/pinctrl-bindings.txt
+ Absence of properties will leave the configuration
+ on default.
+
+ Valid values for function properties are:
+ gpio, lpm-control-in, fps-out, 32k-out,
+ sd0-dvs-in, sd1-dvs-in, reference-out
+ Theres is also customised property for the GPIO1,
+ GPIO2 and GPIO3.
+ - maxim,active-fps-source: FPS source for the gpios in
+ active state of the GPIO. Valid values are
+ FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
+ FPS_SRC_NONE. Absence of this property will
+ leave the pin on default.
+ - maxim,active-fps-power-up-slot: Power up slot on
+ given FPS for acive state.Valid values are 0
+ to 7.
+ - maxim,active-fps-power-down-slot: Power down slot
+ on given FPS for active state. Valid values
+ are 0 t 7.
+ - maxim,suspend-fps-source: Suspend state FPS source.
+ - maxim,suspend-fps-power-down-slot: Suspend state
+ power down slot.
+ - maxim,suspend-fps-power-up-slot: Suspend state power
+ up slot.
+
+Regulators:
+===========
+Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The node "regulators"
+is require if regulator functionality is needed.
+
+Following are properties of regulator subnode.
+
+ Optional properties:
+ -------------------
+ The input supply of regulators are the optional properties on the
+ regulator node. The input supply of these regulators are provided
+ through following properties:
+ in-sd0-supply: Input supply for SD0, INA-SD0 or INB-SD0 pins.
+ in-sd1-supply: Input supply for SD1.
+ in-sd2-supply: Input supply for SD2.
+ in-sd3-supply: Input supply for SD3.
+ in-ldo0-1-supply: Input supply for LDO0 and LDO1.
+ in-ldo2-supply: Input supply for LDO2.
+ in-ldo3-5-supply: Input supply for LDO3 and LDO5
+ in-ldo4-6-supply: Input supply for LDO4 and LDO6.
+ in-ldo7-8-supply: Input supply for LDO7 and LDO8.
+
+
+ Optional sub nodes for regulators:
+ ---------------------------------
+ The subnodes name is the name of regulator and it must be one of:
+ sd[0-3], ldo[0-8]
+
+ Each sub-node should contain the constraints and initialization
+ information for that regulator. See regulator.txt for a description
+ of standard properties for these sub-nodes.
+ Additional optional custom properties are listed below.
+ maxim,active-fps-source: FPS source. The macros are defined at
+ dt-bindings/mfd/max77620.h
+ maxim,shutdown-fps-source: Same as maxim,fps-source, but it
+ will apply during shutdown of system.
+ maxim,active-fps-power-up-slot: Active state Power up slot for
+ rail on given FPS.
+ maxim,active-fps-power-down-slot: Active state Power down slot
+ for rail on given FPS.
+ maxim,suspend-fps-source: Suspend state FPS source of rail.
+ maxim,suspend-fps-power-up-slot: Suspend state FPS power
+ up slot.
+ maxim,suspend-fps-power-down-slot: Suspend state FPS power
+ down slot.
+ maxim,enable-group-low-power: Enable Group low power mode.
+ maxim,enable-sd0-en2-control: Enable EN2 pincontrol for SD0.
+ This property is only applicable for SD0.
+ maxim,disable-remote-sense-on-suspend: Boolean, disable
+ remote sense on suspend and re-enable on resume.
+ If this property is not there then no change on
+ configuration.
+
+Backup Battery:
+==============
+This sub-node configure charging backup battery of the device. Device
+has support of charging the backup battery. The subnode name is
+"backup-battery".
+
+The property for backup-battery child nodes as:
+Presense of this child node will enable the backup battery charging.
+
+Optinal properties:
+ -maxim,bb-charging-current-microamp: Charging current
+ setting.
+ The device supports 50/100/200/400/600/800uA.
+ If this property is unavailable then it will
+ charge with 50uA.
+ -maxim,bb-charging-voltage-microvolt: Charging Voltage Limit Setting.
+ Device supports 2500000/3000000/3300000/350000uV.
+ Default will be set to 2500mV. The voltage will be roundoff
+ to nearest lower side if other than above is configured.
+ -maxim,bb-output-resister-ohm: Output resistor on Ohm.
+ Device supports 100/1000/3000/6000 Ohms.
+
+Low-Battery Monitor:
+==================
+This sub-node configure low battery monitor configuration registers.
+Device has support for low-battery monitor configuration through
+child DT node "low-battery-monitor".
+
+Optinal properties:
+ - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-shutdown: Tristate, enable/disable low battery
+ shutdown.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+ - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
+ 0 for disable,
+ 1 for enable,
+ absence will left configuration to default.
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+
+Example:
+--------
+#include <dt-bindings/mfd/max77620.h>
+...
+max77620@3c {
+ compatible = "maxim,max77620";
+ reg = <0x3c>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 86 IRQ_TYPE_NONE>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ backup-battery {
+ maxim,bb-charging-current-microamp = <100>;
+ maxim,bb-charging-voltage-microvolt = <3000000>;
+ maxim,bb-output-resister-ohm = <100>;
+ };
+
+ fps {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fps@0 {
+ reg = <0>;
+ maxim,fps-time-period-us = <1280>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN0>;
+ };
+
+ fps@1 {
+ reg = <1>;
+ maxim,fps-time-period-us = <2560>;
+ maxim,fps-enable-input = <FPS_EN_SRC_EN1>;
+ };
+
+ fps@2 {
+ reg = <2>;
+ maxim,fps-time-period-us = <640>;
+ maxim,fps-enable-input = <FPS_EN_SRC_SW>;
+ };
+ };
+
+ regulators {
+ in-ldo0-1-supply = <&max77620_sd2>;
+ in-ldo7-8-supply = <&max77620_sd2>;
+
+ max77620_sd0: sd0 {
+ regulator-name = "vdd-core";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_sd1: sd1 {
+ regulator-name = "vddio-ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_sd2: sd2 {
+ regulator-name = "vdd-pre-reg";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_sd3: sd3 {
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+ };
+
+ max77620_ldo0: ldo0 {
+ regulator-name = "avdd-sys";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo1: ldo1 {
+ regulator-name = "vdd-pex";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo2: ldo2 {
+ regulator-name = "vddio-sdmmc3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo3: ldo3 {
+ regulator-name = "vdd-cam-hv";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo4: ldo4 {
+ regulator-name = "vdd-rtc";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_0>;
+ };
+
+ max77620_ldo5: ldo5 {
+ regulator-name = "avdd-ts-hv";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo6: ldo6 {
+ regulator-name = "vdd-ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+
+ max77620_ldo7: ldo7 {
+ regulator-name = "vdd-gen-pll-edp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ maxim,fps-source = <FPS_SRC_1>;
+ };
+
+ max77620_ldo8: ldo8 {
+ regulator-name = "vdd-hdmi-dp";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ maxim,fps-source = <FPS_SRC_NONE>;
+ };
+ };
+};
diff --git a/include/dt-bindings/mfd/max77620.h b/include/dt-bindings/mfd/max77620.h
new file mode 100644
index 0000000..8423d1d
--- /dev/null
+++ b/include/dt-bindings/mfd/max77620.h
@@ -0,0 +1,38 @@
+/*
+ * This header provides macros for MAXIM MAX77620 device bindings.
+ *
+ * Copyright (c) 2016, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_MFD_MAX77620_H
+#define _DT_BINDINGS_MFD_MAX77620_H
+
+/* MAX77620 interrupts */
+#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */
+#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */
+#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */
+#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */
+#define MAX77620_IRQ_TOP_RTC 4 /* RTC */
+#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */
+#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */
+#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */
+
+/* FPS enable -inputs */
+#define FPS_EN_SRC_EN0 0
+#define FPS_EN_SRC_EN1 1
+#define FPS_EN_SRC_SW 2
+#define FPS_EN_SRC_RSVD 3
+
+/* FPS source */
+#define FPS_SRC_0 0
+#define FPS_SRC_1 1
+#define FPS_SRC_2 2
+#define FPS_SRC_NONE 3
+#define FPS_SRC_DEF 4
+
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
2016-01-14 11:32 ` Laxman Dewangan
@ 2016-01-15 2:55 ` Rob Herring
-1 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2016-01-15 2:55 UTC (permalink / raw)
To: Laxman Dewangan
Cc: pawel.moll, mark.rutland, ijc+devicetree, galak, linus.walleij,
gnurou, lee.jones, broonie, a.zummo, alexandre.belloni,
lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski
On Thu, Jan 14, 2016 at 05:02:42PM +0530, Laxman Dewangan wrote:
> The MAXIM PMIC MAX77620 and MAX20024 are power management IC
> which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
> watchdog etc.
>
> Add DT binding document for the different functionality of
> this device.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> - Added units in some of properties.
> - Change the boolean property to tristate type and detail some of
> properties.
>
> Change from V2:
> - added unit in period related dt property.
>
> Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++++++++++++++
> include/dt-bindings/mfd/max77620.h | 38 ++
> 2 files changed, 435 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
> create mode 100644 include/dt-bindings/mfd/max77620.h
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [rtc-linux] Re: [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
@ 2016-01-15 2:55 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2016-01-15 2:55 UTC (permalink / raw)
To: Laxman Dewangan
Cc: pawel.moll, mark.rutland, ijc+devicetree, galak, linus.walleij,
gnurou, lee.jones, broonie, a.zummo, alexandre.belloni,
lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski
On Thu, Jan 14, 2016 at 05:02:42PM +0530, Laxman Dewangan wrote:
> The MAXIM PMIC MAX77620 and MAX20024 are power management IC
> which supports RTC, GPIO, DCDC/LDO regulators, interrupt,
> watchdog etc.
>
> Add DT binding document for the different functionality of
> this device.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> - Added units in some of properties.
> - Change the boolean property to tristate type and detail some of
> properties.
>
> Change from V2:
> - added unit in period related dt property.
>
> Documentation/devicetree/bindings/mfd/max77620.txt | 397 +++++++++++++++++++++
> include/dt-bindings/mfd/max77620.h | 38 ++
> 2 files changed, 435 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/max77620.txt
> create mode 100644 include/dt-bindings/mfd/max77620.h
Acked-by: Rob Herring <robh@kernel.org>
--
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^ permalink raw reply [flat|nested] 32+ messages in thread
[parent not found: <1452771166-13694-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-27 9:42 ` Linus Walleij
-1 siblings, 0 replies; 32+ messages in thread
From: Linus Walleij @ 2016-01-27 9:42 UTC (permalink / raw)
To: Laxman Dewangan, Sebastian Reichel, Dmitry Eremin-Solenikov,
David Woodhouse
Cc: Rob Herring, Paweł Moll, Mark Rutland,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg, Kumar Gala,
Alexandre Courbot, Lee Jones, Mark Brown, Alessandro Zummo,
Alexandre Belloni, Liam Girdwood,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
rtc-linux-/JYPxA39Uh5TLH3MbocFFw, Stephen Warren, Thierry Reding,
Krzysztof Kozłowski, Ulf Hansson
On Thu, Jan 14, 2016 at 12:32 PM, Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> +Flexible power sequence configuration
> +====================================
> +This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
> +power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
> +FPS1 and FPS2. The details of FPS configuration is provided through
> +subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
> +child node under this subnodes. The FPS number is provided via reg property.
> +
> +The property for fps child nodes as:
> +Required properties:
> + -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
This is ambitiously custom. Isn't power sequencing a generic problem?
The MMC subsystem has some power sequencing for example.
> +Optinal properties:
> + -maxim,active-fps-time-period-us: Active state FPS time period in
> + microseconds.
> + -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
> + microseconds.
Define the "active state" and "suspend state" in the initial paragraph
under FPS so we can understand what these things are.
> + -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
> + macros are defined on dt-bindings/mfd/max77620.h for
> + different enable source.
> + FPS_EN_SRC_EN0 for EN0 enable source.
> + FPS_EN_SRC_EN1 for En1 enable source.
> + FPS_EN_SRC_SW for SW based control.
Is SW software? And EN0 and EN1 two different lines into the PMIC?
In that case describe that somewhere.
> + -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
> + If this property present then enable the FPS else
> + disable FPS.
> + -maxim,enable-sleep: Boolean, enable sleep when the external control
> + goes from HIGH to LOW.
> + -maxim,enable-global-lpm: Boolean, enable global LPM when the external
> + control goes from HIGH to LOW.
First *what* is it that will sleep? The PMIC? The whole system? Or
does this simply mean that this will start the state machine? Elaborate.
This is confusing since for example there is a generic "wakeup-enable;"
property you can set on any device, therfore these things must be very
precisely defined.
What is "external control"? Is that a line into the PMIC?
> + Optional properties:
> + --------------------
> + Following properties are require if pin control setting is required
> + at boot.
> + - pinctrl-names: A pinctrl state named "default" be defined, using
> + the bindings in pinctrl/pinctrl-binding.txt.
> + - pinctrl[0...n]: Properties to contain the phandle that refer to
> + different nodes of pin control settings. These nodes
> + represents the pin control setting of state 0 to state n.
> + Each of these nodes contains different subnodes to
> + represents some desired configuration for a list of pins.
> + This configuration can include the mux function to select
> + on those pin(s), and various pin configuration parameters,
> + such as pull-up, open drain.
> +
> + Each subnode have following properties:
> + Required properties:
> + - pins: List of pins. Valid values of pins properties
> + are: gpio0, gpio1, gpio2, gpio3, gpio4,
> + gpio5, gpio6, gpio7
> +
> + Optional properties:
Optional properties under optional properties?
This is getting confusing.
Write "Optional pin configurations"
> + function, drive-push-pull, drive-open-drain,
> + bias-pull-up, bias-pull-down.
> + Definitions are in the pinmux dt binding
> + devicetree/bindings/pinctrl/pinctrl-bindings.txt
> + Absence of properties will leave the configuration
> + on default.
Thanks for using standardized bindings.
> + Valid values for function properties are:
> + gpio, lpm-control-in, fps-out, 32k-out,
> + sd0-dvs-in, sd1-dvs-in, reference-out
> + Theres is also customised property for the GPIO1,
> + GPIO2 and GPIO3.
> + - maxim,active-fps-source: FPS source for the gpios in
> + active state of the GPIO. Valid values are
> + FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
> + FPS_SRC_NONE. Absence of this property will
> + leave the pin on default.
Define closer what an FPS source is. What is the effect on the pin?
> + - maxim,active-fps-power-up-slot: Power up slot on
> + given FPS for acive state.Valid values are 0
> + to 7.
> + - maxim,active-fps-power-down-slot: Power down slot
> + on given FPS for active state. Valid values
> + are 0 t 7.
> + - maxim,suspend-fps-source: Suspend state FPS source.
> + - maxim,suspend-fps-power-down-slot: Suspend state
> + power down slot.
> + - maxim,suspend-fps-power-up-slot: Suspend state power
> + up slot.
These two also have to be explained and connected back under the FPS
heading and explained. I guess it is impossible to understand this
without an accurate understanding of the FPS state machine, so provide
such a description in the document.
> +Low-Battery Monitor:
> +==================
> +This sub-node configure low battery monitor configuration registers.
> +Device has support for low-battery monitor configuration through
> +child DT node "low-battery-monitor".
> +
> +Optinal properties:
> + - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-shutdown: Tristate, enable/disable low battery
> + shutdown.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
I guess this should be reviewed by the drivers/power maintainers?
Added on the To: line.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [rtc-linux] Re: [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
@ 2016-01-27 9:42 ` Linus Walleij
0 siblings, 0 replies; 32+ messages in thread
From: Linus Walleij @ 2016-01-27 9:42 UTC (permalink / raw)
To: Laxman Dewangan, Sebastian Reichel, Dmitry Eremin-Solenikov,
David Woodhouse
Cc: Rob Herring, Paweł Moll, Mark Rutland, ijc+devicetree,
Kumar Gala, Alexandre Courbot, Lee Jones, Mark Brown,
Alessandro Zummo, Alexandre Belloni, Liam Girdwood, devicetree,
linux-kernel, linux-gpio, rtc-linux, Stephen Warren,
Thierry Reding, Krzysztof Kozłowski, Ulf Hansson
On Thu, Jan 14, 2016 at 12:32 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> +Flexible power sequence configuration
> +====================================
> +This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
> +power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
> +FPS1 and FPS2. The details of FPS configuration is provided through
> +subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
> +child node under this subnodes. The FPS number is provided via reg property.
> +
> +The property for fps child nodes as:
> +Required properties:
> + -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
This is ambitiously custom. Isn't power sequencing a generic problem?
The MMC subsystem has some power sequencing for example.
> +Optinal properties:
> + -maxim,active-fps-time-period-us: Active state FPS time period in
> + microseconds.
> + -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
> + microseconds.
Define the "active state" and "suspend state" in the initial paragraph
under FPS so we can understand what these things are.
> + -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
> + macros are defined on dt-bindings/mfd/max77620.h for
> + different enable source.
> + FPS_EN_SRC_EN0 for EN0 enable source.
> + FPS_EN_SRC_EN1 for En1 enable source.
> + FPS_EN_SRC_SW for SW based control.
Is SW software? And EN0 and EN1 two different lines into the PMIC?
In that case describe that somewhere.
> + -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
> + If this property present then enable the FPS else
> + disable FPS.
> + -maxim,enable-sleep: Boolean, enable sleep when the external control
> + goes from HIGH to LOW.
> + -maxim,enable-global-lpm: Boolean, enable global LPM when the external
> + control goes from HIGH to LOW.
First *what* is it that will sleep? The PMIC? The whole system? Or
does this simply mean that this will start the state machine? Elaborate.
This is confusing since for example there is a generic "wakeup-enable;"
property you can set on any device, therfore these things must be very
precisely defined.
What is "external control"? Is that a line into the PMIC?
> + Optional properties:
> + --------------------
> + Following properties are require if pin control setting is required
> + at boot.
> + - pinctrl-names: A pinctrl state named "default" be defined, using
> + the bindings in pinctrl/pinctrl-binding.txt.
> + - pinctrl[0...n]: Properties to contain the phandle that refer to
> + different nodes of pin control settings. These nodes
> + represents the pin control setting of state 0 to state n.
> + Each of these nodes contains different subnodes to
> + represents some desired configuration for a list of pins.
> + This configuration can include the mux function to select
> + on those pin(s), and various pin configuration parameters,
> + such as pull-up, open drain.
> +
> + Each subnode have following properties:
> + Required properties:
> + - pins: List of pins. Valid values of pins properties
> + are: gpio0, gpio1, gpio2, gpio3, gpio4,
> + gpio5, gpio6, gpio7
> +
> + Optional properties:
Optional properties under optional properties?
This is getting confusing.
Write "Optional pin configurations"
> + function, drive-push-pull, drive-open-drain,
> + bias-pull-up, bias-pull-down.
> + Definitions are in the pinmux dt binding
> + devicetree/bindings/pinctrl/pinctrl-bindings.txt
> + Absence of properties will leave the configuration
> + on default.
Thanks for using standardized bindings.
> + Valid values for function properties are:
> + gpio, lpm-control-in, fps-out, 32k-out,
> + sd0-dvs-in, sd1-dvs-in, reference-out
> + Theres is also customised property for the GPIO1,
> + GPIO2 and GPIO3.
> + - maxim,active-fps-source: FPS source for the gpios in
> + active state of the GPIO. Valid values are
> + FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
> + FPS_SRC_NONE. Absence of this property will
> + leave the pin on default.
Define closer what an FPS source is. What is the effect on the pin?
> + - maxim,active-fps-power-up-slot: Power up slot on
> + given FPS for acive state.Valid values are 0
> + to 7.
> + - maxim,active-fps-power-down-slot: Power down slot
> + on given FPS for active state. Valid values
> + are 0 t 7.
> + - maxim,suspend-fps-source: Suspend state FPS source.
> + - maxim,suspend-fps-power-down-slot: Suspend state
> + power down slot.
> + - maxim,suspend-fps-power-up-slot: Suspend state power
> + up slot.
These two also have to be explained and connected back under the FPS
heading and explained. I guess it is impossible to understand this
without an accurate understanding of the FPS state machine, so provide
such a description in the document.
> +Low-Battery Monitor:
> +==================
> +This sub-node configure low battery monitor configuration registers.
> +Device has support for low-battery monitor configuration through
> +child DT node "low-battery-monitor".
> +
> +Optinal properties:
> + - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-shutdown: Tristate, enable/disable low battery
> + shutdown.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
I guess this should be reviewed by the drivers/power maintainers?
Added on the To: line.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH V3 1/5] DT: mfd: add device-tree binding doc fro PMIC max77620/max20024
@ 2016-01-27 9:42 ` Linus Walleij
0 siblings, 0 replies; 32+ messages in thread
From: Linus Walleij @ 2016-01-27 9:42 UTC (permalink / raw)
To: Laxman Dewangan, Sebastian Reichel, Dmitry Eremin-Solenikov,
David Woodhouse
Cc: Rob Herring, Paweł Moll, Mark Rutland, ijc+devicetree,
Kumar Gala, Alexandre Courbot, Lee Jones, Mark Brown,
Alessandro Zummo, Alexandre Belloni, Liam Girdwood, devicetree,
linux-kernel, linux-gpio, rtc-linux, Stephen Warren,
Thierry Reding, Krzysztof Kozłowski, Ulf Hansson
On Thu, Jan 14, 2016 at 12:32 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> +Flexible power sequence configuration
> +====================================
> +This sub-node configures the Flexible Power Sequnece(FPS) for power ON slot,
> +power OFF slot and slot period of the device. Device has 3 FPS as FPS0,
> +FPS1 and FPS2. The details of FPS configuration is provided through
> +subnode "fps". The details of FPS0, FPS1, FPS2 are provided through the
> +child node under this subnodes. The FPS number is provided via reg property.
> +
> +The property for fps child nodes as:
> +Required properties:
> + -reg: FPS number like 0, 1, 2 for FPS0, FPS1 and FPS2 respectively.
This is ambitiously custom. Isn't power sequencing a generic problem?
The MMC subsystem has some power sequencing for example.
> +Optinal properties:
> + -maxim,active-fps-time-period-us: Active state FPS time period in
> + microseconds.
> + -maxim,suspend-fps-time-period-us: Suspend state FPS time period in
> + microseconds.
Define the "active state" and "suspend state" in the initial paragraph
under FPS so we can understand what these things are.
> + -maxim,fps-enable-input: FPS enable source like EN0, EN1 or SW. The
> + macros are defined on dt-bindings/mfd/max77620.h for
> + different enable source.
> + FPS_EN_SRC_EN0 for EN0 enable source.
> + FPS_EN_SRC_EN1 for En1 enable source.
> + FPS_EN_SRC_SW for SW based control.
Is SW software? And EN0 and EN1 two different lines into the PMIC?
In that case describe that somewhere.
> + -maxim,fps-sw-enable: Boolean, applicable if enable input is SW.
> + If this property present then enable the FPS else
> + disable FPS.
> + -maxim,enable-sleep: Boolean, enable sleep when the external control
> + goes from HIGH to LOW.
> + -maxim,enable-global-lpm: Boolean, enable global LPM when the external
> + control goes from HIGH to LOW.
First *what* is it that will sleep? The PMIC? The whole system? Or
does this simply mean that this will start the state machine? Elaborate.
This is confusing since for example there is a generic "wakeup-enable;"
property you can set on any device, therfore these things must be very
precisely defined.
What is "external control"? Is that a line into the PMIC?
> + Optional properties:
> + --------------------
> + Following properties are require if pin control setting is required
> + at boot.
> + - pinctrl-names: A pinctrl state named "default" be defined, using
> + the bindings in pinctrl/pinctrl-binding.txt.
> + - pinctrl[0...n]: Properties to contain the phandle that refer to
> + different nodes of pin control settings. These nodes
> + represents the pin control setting of state 0 to state n.
> + Each of these nodes contains different subnodes to
> + represents some desired configuration for a list of pins.
> + This configuration can include the mux function to select
> + on those pin(s), and various pin configuration parameters,
> + such as pull-up, open drain.
> +
> + Each subnode have following properties:
> + Required properties:
> + - pins: List of pins. Valid values of pins properties
> + are: gpio0, gpio1, gpio2, gpio3, gpio4,
> + gpio5, gpio6, gpio7
> +
> + Optional properties:
Optional properties under optional properties?
This is getting confusing.
Write "Optional pin configurations"
> + function, drive-push-pull, drive-open-drain,
> + bias-pull-up, bias-pull-down.
> + Definitions are in the pinmux dt binding
> + devicetree/bindings/pinctrl/pinctrl-bindings.txt
> + Absence of properties will leave the configuration
> + on default.
Thanks for using standardized bindings.
> + Valid values for function properties are:
> + gpio, lpm-control-in, fps-out, 32k-out,
> + sd0-dvs-in, sd1-dvs-in, reference-out
> + Theres is also customised property for the GPIO1,
> + GPIO2 and GPIO3.
> + - maxim,active-fps-source: FPS source for the gpios in
> + active state of the GPIO. Valid values are
> + FPS_SRC_0, FPS_SRC_1, FPS_SRC_2 and
> + FPS_SRC_NONE. Absence of this property will
> + leave the pin on default.
Define closer what an FPS source is. What is the effect on the pin?
> + - maxim,active-fps-power-up-slot: Power up slot on
> + given FPS for acive state.Valid values are 0
> + to 7.
> + - maxim,active-fps-power-down-slot: Power down slot
> + on given FPS for active state. Valid values
> + are 0 t 7.
> + - maxim,suspend-fps-source: Suspend state FPS source.
> + - maxim,suspend-fps-power-down-slot: Suspend state
> + power down slot.
> + - maxim,suspend-fps-power-up-slot: Suspend state power
> + up slot.
These two also have to be explained and connected back under the FPS
heading and explained. I guess it is impossible to understand this
without an accurate understanding of the FPS state machine, so provide
such a description in the document.
> +Low-Battery Monitor:
> +==================
> +This sub-node configure low battery monitor configuration registers.
> +Device has support for low-battery monitor configuration through
> +child DT node "low-battery-monitor".
> +
> +Optinal properties:
> + - maxim,low-battery-dac: Tristate, enable/disable low battery DAC.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-shutdown: Tristate, enable/disable low battery
> + shutdown.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
> + - maxim,low-battery-reset: Tristate, enable/disable low battery reset.
> + 0 for disable,
> + 1 for enable,
> + absence will left configuration to default.
I guess this should be reviewed by the drivers/power maintainers?
Added on the To: line.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH V3 2/5] mfd: max77620: add core driver for MAX77620/MAX20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-14 11:32 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi,
Mallikarjun Kasoju
MAX77620/MAX20024 are Power Management IC from the MAXIM.
It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
watchdog, clock etc.
Add MFD drier to provides common support for accessing the
device; additional drivers is developed on respected subsystem
in order to use the functionality of the device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Code cleanups per review from V1.
- Move register acccess APIs from header to c file.
- Remove some of non required variable, remove duplication in error message
and simplify some of function implementation.
- Register RTC driver such that it can get the regmap handle form parent device
Changes from V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Drop RTC driver and its i2c client registration.
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/max77620.c | 898 +++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/max77620.h | 402 +++++++++++++++++++
4 files changed, 1316 insertions(+)
create mode 100644 drivers/mfd/max77620.c
create mode 100644 include/linux/mfd/max77620.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9581ebb..edeb85c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -492,6 +492,21 @@ config MFD_MAX14577
additional drivers must be enabled in order to use the functionality
of the device.
+config MFD_MAX77620
+ bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
+ depends on I2C=y
+ depends on OF
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for Maxim Semiconductor MAX77620 and
+ MAX20024 which are Power Management IC with General purpose pins,
+ RTC, regulators, clock generator, watchdog etc. This driver
+ provides common support for accessing the device; additional drivers
+ must be enabled in order to use the functionality of the device.
+
config MFD_MAX77686
bool "Maxim Semiconductor MAX77686/802 PMIC Support"
depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0f230a6..97910ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
obj-$(CONFIG_MFD_DA9150) += da9150-core.o
obj-$(CONFIG_MFD_MAX14577) += max14577.o
+obj-$(CONFIG_MFD_MAX77620) += max77620.o
obj-$(CONFIG_MFD_MAX77686) += max77686.o
obj-$(CONFIG_MFD_MAX77693) += max77693.o
obj-$(CONFIG_MFD_MAX77843) += max77843.o
diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
new file mode 100644
index 0000000..e965261
--- /dev/null
+++ b/drivers/mfd/max77620.c
@@ -0,0 +1,898 @@
+/*
+ * Maxim MAX77620 MFD Driver
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Mallikarjun Kasoju <mkasoju@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/mfd/core.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/mfd/max77620.h>
+
+static struct resource gpio_resources[] = {
+ {
+ .start = MAX77620_IRQ_TOP_GPIO,
+ .end = MAX77620_IRQ_TOP_GPIO,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource thermal_resources[] = {
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM1,
+ .end = MAX77620_IRQ_LBT_TJALRM1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM2,
+ .end = MAX77620_IRQ_LBT_TJALRM2,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static const struct regmap_irq max77620_top_irqs[] = {
+ [MAX77620_IRQ_TOP_GLBL] = {
+ .mask = MAX77620_IRQ_TOP_GLBL_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_SD] = {
+ .mask = MAX77620_IRQ_TOP_SD_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_LDO] = {
+ .mask = MAX77620_IRQ_TOP_LDO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_GPIO] = {
+ .mask = MAX77620_IRQ_TOP_GPIO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_RTC] = {
+ .mask = MAX77620_IRQ_TOP_RTC_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_32K] = {
+ .mask = MAX77620_IRQ_TOP_32K_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_ONOFF] = {
+ .mask = MAX77620_IRQ_TOP_ONOFF_MASK,
+ .reg_offset = 0,
+ },
+
+ [MAX77620_IRQ_LBT_MBATLOW] = {
+ .mask = MAX77620_IRQ_LBM_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM1] = {
+ .mask = MAX77620_IRQ_TJALRM1_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM2] = {
+ .mask = MAX77620_IRQ_TJALRM2_MASK,
+ .reg_offset = 1,
+ },
+
+};
+
+static const char * const max77620_nverc[] = {
+ "Shutdown-pin",
+ "System WatchDog Timer",
+ "Hard Reset",
+ "Junction Temp Overload",
+ "Main-Battery Low",
+ "Main-Battery overvoltage Lockout",
+ "Main-Battery undervoltage Lockout",
+ "Reset input",
+};
+
+enum max77660_ids {
+ MAX77620_PMIC_ID,
+ MAX77620_GPIO_ID,
+ MAX77620_PINCTRL_ID,
+ MAX77620_CLK_ID,
+ MAX77620_POWER_OFF_ID,
+ MAX77620_WDT_ID,
+ MAX77620_THERMAL_ID,
+ MAX77620_RTC_ID,
+};
+
+#define MAX77620_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX77620_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+static struct mfd_cell max77620_children[] = {
+ MAX77620_SUB_MODULE_RES(gpio, GPIO),
+ MAX77620_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX77620_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX77620_SUB_MODULE_NO_RES(clk, CLK),
+ MAX77620_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX77620_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX77620_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+static struct mfd_cell max20024_children[] = {
+ MAX20024_SUB_MODULE_RES(gpio, GPIO),
+ MAX20024_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX20024_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX20024_SUB_MODULE_NO_RES(clk, CLK),
+ MAX20024_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX20024_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX20024_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+struct max77620_sub_modules {
+ struct mfd_cell *cells;
+ int ncells;
+ u32 id;
+};
+
+static const struct max77620_sub_modules max77620_cells = {
+ .cells = max77620_children,
+ .ncells = ARRAY_SIZE(max77620_children),
+ .id = MAX77620,
+};
+
+static const struct max77620_sub_modules max20024_cells = {
+ .cells = max20024_children,
+ .ncells = ARRAY_SIZE(max20024_children),
+ .id = MAX20024,
+};
+
+static struct regmap_irq_chip max77620_top_irq_chip = {
+ .name = "max77620-top",
+ .irqs = max77620_top_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_top_irqs),
+ .num_regs = 2,
+ .status_base = MAX77620_REG_IRQTOP,
+ .mask_base = MAX77620_REG_IRQTOPM,
+};
+
+static const struct regmap_range max77620_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_readable_table = {
+ .yes_ranges = max77620_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
+};
+
+static const struct regmap_range max20024_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+ regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
+};
+
+static const struct regmap_access_table max20024_readable_table = {
+ .yes_ranges = max20024_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
+};
+
+static const struct regmap_range max77620_writable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_writable_table = {
+ .yes_ranges = max77620_writable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
+};
+
+static const struct regmap_range max77620_cacheable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
+ regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
+};
+
+static const struct regmap_access_table max77620_volatile_table = {
+ .no_ranges = max77620_cacheable_ranges,
+ .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
+};
+
+static const struct regmap_config max77620_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX77620_REG_DVSSD4 + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max77620_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+static const struct regmap_config max20024_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX20024_REG_MAX_ADD + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max20024_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+int max77620_irq_get_virq(struct device *dev, int irq)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_irq_get_virq(chip->top_irq_data, irq);
+}
+EXPORT_SYMBOL_GPL(max77620_irq_get_virq);
+
+int max77620_reg_write(struct device *dev, unsigned int reg, u8 val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_write(chip->rmap, reg, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_write);
+
+int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int ival;
+ int ret;
+
+ ret = regmap_read(chip->rmap, reg, &ival);
+ if (ret < 0)
+ return ret;
+ *val = ival;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(max77620_reg_read);
+
+int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_update_bits(chip->rmap, reg, mask, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_update);
+
+static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
+ int tperiod)
+{
+ int base_fps_time = (chip->id == MAX20024) ? 20 : 40;
+ int x, i;
+
+ for (i = 0; i < 0x7; ++i) {
+ x = base_fps_time * BIT(i);
+ if (x >= tperiod)
+ return i;
+ }
+
+ return i;
+}
+
+static int max77620_config_fps(struct max77620_chip *chip,
+ struct device_node *fps_np)
+{
+ struct device *dev = chip->dev;
+ unsigned int mask = 0, config = 0;
+ int input_enable = 2;
+ u32 pval;
+ int tperiod, fps_id;
+ int ret;
+
+ ret = of_property_read_u32(fps_np, "reg", &pval);
+ if (ret < 0) {
+ dev_err(dev, "reg prop missing from node %s\n", fps_np->name);
+ return 0;
+ }
+ if (pval > 2) {
+ dev_err(dev, "FPS%u is not supported\n", pval);
+ return 0;
+ }
+ fps_id = pval;
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,active-fps-time-period-us", &pval);
+ if (!ret) {
+ mask |= MAX77620_FPS_TIME_PERIOD_MASK;
+ chip->active_fps_period[fps_id] = min(pval, 5120U);
+ tperiod = max77620_get_fps_period_reg_value(
+ chip, chip->active_fps_period[fps_id]);
+ config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
+ }
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,suspend-fps-time-period-us", &pval);
+ if (!ret)
+ chip->suspend_fps_period[fps_id] = min(pval, 5120U);
+
+ ret = of_property_read_u32(fps_np, "maxim,fps-enable-input", &pval);
+ if (!ret) {
+ if (pval > 2) {
+ dev_err(dev, "FPS %d enable-input invalid\n", fps_id);
+ } else {
+ input_enable = pval;
+ mask |= MAX77620_FPS_EN_SRC_MASK;
+ }
+ }
+ config |= (input_enable & 0x3) << MAX77620_FPS_EN_SRC_SHIFT;
+
+ if (input_enable == 2) {
+ bool enable_fps = of_property_read_bool(fps_np,
+ "maxim,fps-sw-enable");
+ mask |= MAX77620_FPS_ENFPS_MASK;
+ if (enable_fps)
+ config |= 1;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(fps_np,
+ "maxim,enable-sleep");
+ if (!chip->enable_global_lpm)
+ chip->enable_global_lpm = of_property_read_bool(fps_np,
+ "maxim,enable-global-lpm");
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ mask, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_fps(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *fps_np, *fps_child;
+ u8 config;
+ int fps_id;
+ int ret;
+
+ for (fps_id = 0; fps_id < 3; ++fps_id) {
+ chip->active_fps_period[fps_id] = -1;
+ chip->suspend_fps_period[fps_id] = -1;
+ }
+
+ fps_np = of_get_child_by_name(dev->of_node, "fps");
+ if (!fps_np)
+ goto skip_fps;
+
+ for_each_child_of_node(fps_np, fps_child) {
+ ret = max77620_config_fps(chip, fps_child);
+ if (ret < 0)
+ return ret;
+ }
+
+ config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+skip_fps:
+ /* Enable wake on EN0 pin */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(dev->of_node,
+ "maxim,enable-sleep");
+
+ /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
+ if ((chip->id == MAX20024) && chip->sleep_enable) {
+ config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ config, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int max77620_init_backup_battery_charging(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *bb_node;
+ u32 pval;
+ u8 config;
+ int ret;
+
+ bb_node = of_get_child_by_name(dev->of_node, "backup-battery");
+ if (!bb_node) {
+ dev_dbg(dev, "Backup battery charging support disabled\n");
+ max77620_reg_update(chip->dev, MAX77620_REG_CNFGBBC,
+ MAX77620_CNFGBBC_ENABLE, 0);
+ return 0;
+ }
+
+ config = MAX77620_CNFGBBC_ENABLE;
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-current-microamp", &pval);
+ if (ret < 0)
+ pval = 50;
+ if (pval <= 50)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 100)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 200)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 400)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 600)
+ config |= 1 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else
+ config |= 2 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+
+ if (pval > 100)
+ config |= MAX77620_CNFGBBC_LOW_CURRENT_DISABLE;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-voltage-microvolt",
+ &pval);
+ if (ret < 0)
+ pval = 2500000;
+ pval /= 1000;
+ if (pval <= 2500)
+ config |= 0 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3000)
+ config |= 1 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3300)
+ config |= 2 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else
+ config |= 3 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-output-resister-ohm", &pval);
+ if (ret < 0)
+ pval = 1000;
+
+ if (pval <= 100)
+ config |= 0 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 1000)
+ config |= 1 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 3000)
+ config |= 2 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 6000)
+ config |= 3 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+
+ ret = max77620_reg_write(dev, MAX77620_REG_CNFGBBC, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_CNFGBBC, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_init_low_battery_monitor(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np;
+ u8 mask = 0, val = 0;
+ u32 pval;
+ int ret;
+
+ np = of_get_child_by_name(dev->of_node, "low-battery-monitor");
+ if (!np)
+ return 0;
+
+ ret = of_property_read_u32(np, "maxim,low-battery-dac", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-shutdown", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_MPPLD;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_MPPLD;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-reset", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBRSTEN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBRSTEN;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(dev, MAX77620_REG_CNFGGLBL1,
+ mask, val);
+ if (ret < 0)
+ dev_err(dev, "Reg CNFGGLBL1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_chip(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ u32 mrt_time = 0;
+ u8 reg_val;
+ int ret;
+
+ ret = of_property_read_u32(np, "maxim,hard-power-off-time", &mrt_time);
+ if (ret < 0)
+ return 0;
+
+ mrt_time = (mrt_time > 12) ? 12 : mrt_time;
+ if (mrt_time <= 6)
+ reg_val = mrt_time - 2;
+ else
+ reg_val = (mrt_time - 6) / 2 + 4;
+
+ reg_val <<= MAX77620_ONOFFCNFG1_MRT_SHIFT;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_MRT_MASK, reg_val);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable alarm wake to enable sleep from EN input signal */
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_ALARM1, 0);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int max77620_read_es_version(struct max77620_chip *chip)
+{
+ u8 val, cid_val[6];
+ int i;
+ int ret;
+
+ for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; ++i) {
+ ret = max77620_reg_read(chip->dev, i, &val);
+ if (ret < 0) {
+ dev_err(chip->dev, "CID%d register read failed: %d\n",
+ i - MAX77620_REG_CID0, ret);
+ return ret;
+ }
+ dev_dbg(chip->dev, "CID%d: 0x%02x\n",
+ i - MAX77620_REG_CID0, val);
+ cid_val[i - MAX77620_REG_CID0] = val;
+ }
+
+ /* CID4 is OTP Version and CID5 is ES version */
+ dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%02X\n",
+ cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
+
+ return ret;
+}
+
+static irqreturn_t max77620_mbattlow_irq(int irq, void *data)
+{
+ struct max77620_chip *max77620 = data;
+
+ dev_dbg(max77620->dev, "MBATTLOW interrupt occurred\n");
+
+ return IRQ_HANDLED;
+}
+
+static int max77620_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device_node *node = client->dev.of_node;
+ const struct max77620_sub_modules *children;
+ const struct regmap_config *rmap_config = &max77620_regmap_config;
+ struct max77620_chip *chip;
+ int ret = 0;
+
+ if (!node) {
+ dev_err(&client->dev, "Device is not from DT\n");
+ return -ENODEV;
+ }
+
+ children = of_device_get_match_data(&client->dev);
+ if (!children)
+ return -ENODEV;
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, chip);
+ chip->dev = &client->dev;
+ chip->irq_base = -1;
+ chip->chip_irq = client->irq;
+ chip->id = children->id;
+ chip->base_client = client;
+
+ if (chip->id == MAX20024)
+ rmap_config = &max20024_regmap_config;
+
+ chip->rmap = devm_regmap_init_i2c(chip->base_client, rmap_config);
+ if (IS_ERR(chip->rmap)) {
+ ret = PTR_ERR(chip->rmap);
+ dev_err(&client->dev, "regmap init failed %d\n", ret);
+ return ret;
+ }
+
+ mutex_init(&chip->mutex_config);
+
+ ret = max77620_read_es_version(chip);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_initialise_chip(chip, &client->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_add_irq_chip(chip->rmap, chip->chip_irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ chip->irq_base, &max77620_top_irq_chip,
+ &chip->top_irq_data);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to add top irq_chip %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_initialise_fps(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_backup_battery_charging(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_low_battery_monitor(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = mfd_add_devices(&client->dev, -1, children->cells,
+ children->ncells, NULL, 0,
+ regmap_irq_get_domain(chip->top_irq_data));
+ if (ret < 0) {
+ dev_err(&client->dev, "mfd add dev fail %d\n", ret);
+ goto fail_free_irq;
+ }
+
+ chip->irq_mbattlow = max77620_irq_get_virq(chip->dev,
+ MAX77620_IRQ_LBT_MBATLOW);
+ if (chip->irq_mbattlow) {
+ ret = devm_request_threaded_irq(chip->dev, chip->irq_mbattlow,
+ NULL, max77620_mbattlow_irq,
+ IRQF_ONESHOT,
+ dev_name(chip->dev), chip);
+ if (ret < 0)
+ dev_err(&client->dev, "request irq %d failed: %d\n",
+ chip->irq_mbattlow, ret);
+ }
+
+ return 0;
+
+fail_free_irq:
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return ret;
+}
+
+static int max77620_remove(struct i2c_client *client)
+{
+ struct max77620_chip *chip = i2c_get_clientdata(client);
+
+ mfd_remove_devices(chip->dev);
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_set_fps_period(struct max77620_chip *chip,
+ int fps_id, int time_period)
+{
+ struct device *dev = chip->dev;
+ int period = max77620_get_fps_period_reg_value(chip, time_period);
+ int ret;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ MAX77620_FPS_TIME_PERIOD_MASK,
+ period << MAX77620_FPS_TIME_PERIOD_SHIFT);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_i2c_suspend(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int config;
+ int fps;
+ int ret;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->suspend_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->suspend_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure SLPEN on suspend as
+ * it will be configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_SLPEN,
+ config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0, 0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ disable_irq(chip->chip_irq);
+
+ return 0;
+}
+
+static int max77620_i2c_resume(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ int ret;
+ int fps;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->active_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->active_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure WKEN0 on resume as
+ * it is configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ /* Enable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ enable_irq(chip->chip_irq);
+
+ return 0;
+}
+#endif
+
+static const struct i2c_device_id max77620_id[] = {
+ {"max77620", MAX77620},
+ {"max20024", MAX20024},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, max77620_id);
+
+static const struct of_device_id max77620_of_match[] = {
+ {
+ .compatible = "maxim,max77620",
+ .data = &max77620_cells,
+ }, {
+ .compatible = "maxim,max20024",
+ .data = &max20024_cells,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, max77620_of_match);
+
+static const struct dev_pm_ops max77620_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
+};
+
+static struct i2c_driver max77620_driver = {
+ .driver = {
+ .name = "max77620",
+ .pm = &max77620_pm_ops,
+ .of_match_table = max77620_of_match,
+ },
+ .probe = max77620_probe,
+ .remove = max77620_remove,
+ .id_table = max77620_id,
+};
+
+static int __init max77620_init(void)
+{
+ return i2c_add_driver(&max77620_driver);
+}
+subsys_initcall(max77620_init);
+
+static void __exit max77620_exit(void)
+{
+ i2c_del_driver(&max77620_driver);
+}
+module_exit(max77620_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_ALIAS("i2c:max77620");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
new file mode 100644
index 0000000..2bb4829
--- /dev/null
+++ b/include/linux/mfd/max77620.h
@@ -0,0 +1,402 @@
+/*
+ * max77620.h: Defining registers address and its bit definitions
+ * of MAX77620 and MAX20024
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _LINUX_MFD_MAX77620_H_
+#define _LINUX_MFD_MAX77620_H_
+
+/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
+#define MAX77620_REG_CNFGGLBL1 0x00
+#define MAX77620_REG_CNFGGLBL2 0x01
+#define MAX77620_REG_CNFGGLBL3 0x02
+#define MAX77620_REG_CNFG1_32K 0x03
+#define MAX77620_REG_CNFGBBC 0x04
+#define MAX77620_REG_IRQTOP 0x05
+#define MAX77620_REG_INTLBT 0x06
+#define MAX77620_REG_IRQSD 0x07
+#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
+#define MAX77620_REG_IRQ_LVL2_L8 0x09
+#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
+#define MAX77620_REG_ONOFFIRQ 0x0B
+#define MAX77620_REG_NVERC 0x0C
+#define MAX77620_REG_IRQTOPM 0x0D
+#define MAX77620_REG_INTENLBT 0x0E
+#define MAX77620_REG_IRQMASKSD 0x0F
+#define MAX77620_REG_IRQ_MSK_L0_7 0x10
+#define MAX77620_REG_IRQ_MSK_L8 0x11
+#define MAX77620_REG_ONOFFIRQM 0x12
+#define MAX77620_REG_STATLBT 0x13
+#define MAX77620_REG_STATSD 0x14
+#define MAX77620_REG_ONOFFSTAT 0x15
+
+/* SD and LDO Registers */
+#define MAX77620_REG_SD0 0x16
+#define MAX77620_REG_SD1 0x17
+#define MAX77620_REG_SD2 0x18
+#define MAX77620_REG_SD3 0x19
+#define MAX77620_REG_SD4 0x1A
+#define MAX77620_REG_DVSSD0 0x1B
+#define MAX77620_REG_DVSSD1 0x1C
+#define MAX77620_REG_SD0_CFG 0x1D
+#define MAX77620_REG_SD1_CFG 0x1E
+#define MAX77620_REG_SD2_CFG 0x1F
+#define MAX77620_REG_SD3_CFG 0x20
+#define MAX77620_REG_SD4_CFG 0x21
+#define MAX77620_REG_SD_CFG2 0x22
+#define MAX77620_REG_LDO0_CFG 0x23
+#define MAX77620_REG_LDO0_CFG2 0x24
+#define MAX77620_REG_LDO1_CFG 0x25
+#define MAX77620_REG_LDO1_CFG2 0x26
+#define MAX77620_REG_LDO2_CFG 0x27
+#define MAX77620_REG_LDO2_CFG2 0x28
+#define MAX77620_REG_LDO3_CFG 0x29
+#define MAX77620_REG_LDO3_CFG2 0x2A
+#define MAX77620_REG_LDO4_CFG 0x2B
+#define MAX77620_REG_LDO4_CFG2 0x2C
+#define MAX77620_REG_LDO5_CFG 0x2D
+#define MAX77620_REG_LDO5_CFG2 0x2E
+#define MAX77620_REG_LDO6_CFG 0x2F
+#define MAX77620_REG_LDO6_CFG2 0x30
+#define MAX77620_REG_LDO7_CFG 0x31
+#define MAX77620_REG_LDO7_CFG2 0x32
+#define MAX77620_REG_LDO8_CFG 0x33
+#define MAX77620_REG_LDO8_CFG2 0x34
+#define MAX77620_REG_LDO_CFG3 0x35
+
+#define MAX77620_LDO_SLEW_RATE_MASK 0x1
+
+/* LDO Configuration 3 */
+#define MAX77620_TRACK4_MASK BIT(5)
+#define MAX77620_TRACK4_SHIFT 5
+
+/* Voltage */
+#define MAX77620_SDX_VOLT_MASK 0xFF
+#define MAX77620_SD0_VOLT_MASK 0x3F
+#define MAX77620_SD1_VOLT_MASK 0x7F
+#define MAX77620_LDO_VOLT_MASK 0x3F
+
+#define MAX77620_REG_GPIO0 0x36
+#define MAX77620_REG_GPIO1 0x37
+#define MAX77620_REG_GPIO2 0x38
+#define MAX77620_REG_GPIO3 0x39
+#define MAX77620_REG_GPIO4 0x3A
+#define MAX77620_REG_GPIO5 0x3B
+#define MAX77620_REG_GPIO6 0x3C
+#define MAX77620_REG_GPIO7 0x3D
+#define MAX77620_REG_PUE_GPIO 0x3E
+#define MAX77620_REG_PDE_GPIO 0x3F
+#define MAX77620_REG_AME_GPIO 0x40
+#define MAX77620_REG_ONOFFCNFG1 0x41
+#define MAX77620_REG_ONOFFCNFG2 0x42
+
+/* FPS Registers */
+#define MAX77620_REG_FPS_CFG0 0x43
+#define MAX77620_REG_FPS_CFG1 0x44
+#define MAX77620_REG_FPS_CFG2 0x45
+#define MAX77620_REG_FPS_LDO0 0x46
+#define MAX77620_REG_FPS_LDO1 0x47
+#define MAX77620_REG_FPS_LDO2 0x48
+#define MAX77620_REG_FPS_LDO3 0x49
+#define MAX77620_REG_FPS_LDO4 0x4A
+#define MAX77620_REG_FPS_LDO5 0x4B
+#define MAX77620_REG_FPS_LDO6 0x4C
+#define MAX77620_REG_FPS_LDO7 0x4D
+#define MAX77620_REG_FPS_LDO8 0x4E
+#define MAX77620_REG_FPS_SD0 0x4F
+#define MAX77620_REG_FPS_SD1 0x50
+#define MAX77620_REG_FPS_SD2 0x51
+#define MAX77620_REG_FPS_SD3 0x52
+#define MAX77620_REG_FPS_SD4 0x53
+#define MAX77620_REG_FPS_NONE 0
+
+#define MAX77620_FPS_SRC_MASK 0xC0
+#define MAX77620_FPS_SRC_SHIFT 6
+#define MAX77620_FPS_PU_PERIOD_MASK 0x38
+#define MAX77620_FPS_PU_PERIOD_SHIFT 3
+#define MAX77620_FPS_PD_PERIOD_MASK 0x07
+#define MAX77620_FPS_PD_PERIOD_SHIFT 0
+#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
+#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
+#define MAX77620_FPS_EN_SRC_MASK 0x06
+#define MAX77620_FPS_EN_SRC_SHIFT 1
+#define MAX77620_FPS_ENFPS_MASK 0x01
+
+#define MAX77620_REG_FPS_GPIO1 0x54
+#define MAX77620_REG_FPS_GPIO2 0x55
+#define MAX77620_REG_FPS_GPIO3 0x56
+#define MAX77620_REG_FPS_RSO 0x57
+#define MAX77620_REG_CID0 0x58
+#define MAX77620_REG_CID1 0x59
+#define MAX77620_REG_CID2 0x5A
+#define MAX77620_REG_CID3 0x5B
+#define MAX77620_REG_CID4 0x5C
+#define MAX77620_REG_CID5 0x5D
+
+#define MAX77620_REG_DVSSD4 0x5E
+#define MAX20024_REG_MAX_ADD 0x70
+
+#define MAX77620_CID_DIDM_MASK 0xF0
+#define MAX77620_CID_DIDM_SHIFT 4
+
+/* CNCG2SD */
+#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
+#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
+
+/* Device Identification Metal */
+#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
+/* Device Indentification OTP */
+#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
+
+/* SD CNFG1 */
+#define MAX77620_SD_SR_MASK 0xC0
+#define MAX77620_SD_SR_SHIFT 6
+#define MAX77620_SD_POWER_MODE_MASK 0x30
+#define MAX77620_SD_POWER_MODE_SHIFT 4
+#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
+#define MAX77620_SD_CFG1_ADE_DISABLE 0
+#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
+#define MAX77620_SD_FPWM_MASK 0x04
+#define MAX77620_SD_FPWM_SHIFT 2
+#define MAX77620_SD_FSRADE_MASK 0x01
+#define MAX77620_SD_FSRADE_SHIFT 0
+#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
+#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
+#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
+#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
+#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
+#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
+
+/* LDO_CNFG2 */
+#define MAX77620_LDO_POWER_MODE_MASK 0xC0
+#define MAX77620_LDO_POWER_MODE_SHIFT 6
+#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
+#define MAX77620_LDO_CFG2_ADE_DISABLE 0
+#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
+#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
+#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
+#define MAX77620_LDO_CFG2_SS_SLOW 0
+
+#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
+#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
+#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
+#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
+#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
+#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
+#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
+
+#define MAX77620_IRQ_LBM_MASK BIT(3)
+#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
+#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
+
+#define MAX77620_PWR_I2C_ADDR 0x3c
+#define MAX77620_RTC_I2C_ADDR 0x68
+
+#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
+#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
+#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
+#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
+#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
+#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
+#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
+
+#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
+
+#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
+
+#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
+#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
+#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
+#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
+#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
+#define MAX20024_ONOFFCNFG1_CLRSE 0x18
+
+#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
+#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
+#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
+#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
+#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
+
+#define MAX77620_GLBLM_MASK BIT(0)
+
+#define MAX77620_WDTC_MASK 0x3
+#define MAX77620_WDTOFFC BIT(4)
+#define MAX77620_WDTSLPC BIT(3)
+#define MAX77620_WDTEN BIT(2)
+
+#define MAX77620_TWD_MASK 0x3
+#define MAX77620_TWD_2s 0x0
+#define MAX77620_TWD_16s 0x1
+#define MAX77620_TWD_64s 0x2
+#define MAX77620_TWD_128s 0x3
+
+#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
+#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
+#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
+#define MAX77620_CNFGGLBL1_LBDAC 0x0E
+#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
+
+/* CNFG BBC registers */
+#define MAX77620_CNFGBBC_ENABLE BIT(0)
+#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
+#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
+#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
+#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
+#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
+#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
+#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
+
+/* I2c Slave Id */
+enum {
+ MAX77620_PWR_SLAVE,
+ MAX77620_RTC_SLAVE,
+ MAX77620_NUM_SLAVES,
+};
+
+/* GPIOs */
+enum {
+ MAX77620_GPIO0,
+ MAX77620_GPIO1,
+ MAX77620_GPIO2,
+ MAX77620_GPIO3,
+ MAX77620_GPIO4,
+ MAX77620_GPIO5,
+ MAX77620_GPIO6,
+ MAX77620_GPIO7,
+
+ MAX77620_GPIO_NR,
+};
+
+/* Interrupts */
+enum {
+ MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
+ MAX77620_IRQ_TOP_SD, /* SD power fail */
+ MAX77620_IRQ_TOP_LDO, /* LDO power fail */
+ MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
+ MAX77620_IRQ_TOP_RTC, /* RTC */
+ MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
+ MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
+
+ MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
+
+ MAX77620_IRQ_GPIO0, /* GPIO0 edge detection */
+ MAX77620_IRQ_GPIO1, /* GPIO1 edge detection */
+ MAX77620_IRQ_GPIO2, /* GPIO2 edge detection */
+ MAX77620_IRQ_GPIO3, /* GPIO3 edge detection */
+ MAX77620_IRQ_GPIO4, /* GPIO4 edge detection */
+ MAX77620_IRQ_GPIO5, /* GPIO5 edge detection */
+ MAX77620_IRQ_GPIO6, /* GPIO6 edge detection */
+ MAX77620_IRQ_GPIO7, /* GPIO7 edge detection */
+
+ MAX77620_IRQ_ONOFF_MRWRN, /* Hard power off warnning */
+ MAX77620_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */
+ MAX77620_IRQ_ONOFF_EN0_F, /* EN0 falling */
+ MAX77620_IRQ_ONOFF_EN0_R, /* EN0 rising */
+ MAX77620_IRQ_ONOFF_LID_F, /* LID falling */
+ MAX77620_IRQ_ONOFF_LID_R, /* LID rising */
+ MAX77620_IRQ_ONOFF_ACOK_F, /* ACOK falling */
+ MAX77620_IRQ_ONOFF_ACOK_R, /* ACOK rising */
+
+ MAX77620_IRQ_NVER, /* Non-Volatile Event Recorder */
+ MAX77620_IRQ_NR,
+};
+
+enum max77620_regulators {
+ MAX77620_REGULATOR_ID_SD0,
+ MAX77620_REGULATOR_ID_SD1,
+ MAX77620_REGULATOR_ID_SD2,
+ MAX77620_REGULATOR_ID_SD3,
+ MAX77620_REGULATOR_ID_SD4,
+ MAX77620_REGULATOR_ID_LDO0,
+ MAX77620_REGULATOR_ID_LDO1,
+ MAX77620_REGULATOR_ID_LDO2,
+ MAX77620_REGULATOR_ID_LDO3,
+ MAX77620_REGULATOR_ID_LDO4,
+ MAX77620_REGULATOR_ID_LDO5,
+ MAX77620_REGULATOR_ID_LDO6,
+ MAX77620_REGULATOR_ID_LDO7,
+ MAX77620_REGULATOR_ID_LDO8,
+ MAX77620_NUM_REGS,
+};
+
+/* FPS Source */
+enum max77620_regulator_fps_src {
+ FPS_SRC_0,
+ FPS_SRC_1,
+ FPS_SRC_2,
+ FPS_SRC_NONE,
+ FPS_SRC_DEF,
+};
+
+/* Regulator types */
+enum max77620_regulator_type {
+ MAX77620_REGULATOR_TYPE_SD,
+ MAX77620_REGULATOR_TYPE_LDO_N,
+ MAX77620_REGULATOR_TYPE_LDO_P,
+};
+
+enum max77620_chip_id {
+ MAX77620,
+ MAX20024,
+};
+
+struct max77620_chip {
+ struct device *dev;
+
+ struct i2c_client *base_client;
+ struct regmap *rmap;
+
+ int chip_irq;
+ int irq_base;
+ int irq_mbattlow;
+
+ struct mutex mutex_config;
+ bool sleep_enable;
+ bool enable_global_lpm;
+ int active_fps_period[3];
+ int suspend_fps_period[3];
+
+ struct regmap_irq_chip_data *top_irq_data;
+ struct regmap_irq_chip_data *gpio_irq_data;
+
+ /* chip id */
+ u32 id;
+};
+
+extern int max77620_irq_get_virq(struct device *dev, int irq);
+extern int max77620_reg_write(struct device *dev, unsigned int reg, u8 val);
+extern int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val);
+extern int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val);
+#endif /* _LINUX_MFD_MAX77620_H_ */
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [rtc-linux] [PATCH V3 2/5] mfd: max77620: add core driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi,
Mallikarjun Kasoju
MAX77620/MAX20024 are Power Management IC from the MAXIM.
It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
watchdog, clock etc.
Add MFD drier to provides common support for accessing the
device; additional drivers is developed on respected subsystem
in order to use the functionality of the device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Code cleanups per review from V1.
- Move register acccess APIs from header to c file.
- Remove some of non required variable, remove duplication in error message
and simplify some of function implementation.
- Register RTC driver such that it can get the regmap handle form parent device
Changes from V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Drop RTC driver and its i2c client registration.
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/max77620.c | 898 +++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/max77620.h | 402 +++++++++++++++++++
4 files changed, 1316 insertions(+)
create mode 100644 drivers/mfd/max77620.c
create mode 100644 include/linux/mfd/max77620.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9581ebb..edeb85c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -492,6 +492,21 @@ config MFD_MAX14577
additional drivers must be enabled in order to use the functionality
of the device.
+config MFD_MAX77620
+ bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
+ depends on I2C=y
+ depends on OF
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for Maxim Semiconductor MAX77620 and
+ MAX20024 which are Power Management IC with General purpose pins,
+ RTC, regulators, clock generator, watchdog etc. This driver
+ provides common support for accessing the device; additional drivers
+ must be enabled in order to use the functionality of the device.
+
config MFD_MAX77686
bool "Maxim Semiconductor MAX77686/802 PMIC Support"
depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0f230a6..97910ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
obj-$(CONFIG_MFD_DA9150) += da9150-core.o
obj-$(CONFIG_MFD_MAX14577) += max14577.o
+obj-$(CONFIG_MFD_MAX77620) += max77620.o
obj-$(CONFIG_MFD_MAX77686) += max77686.o
obj-$(CONFIG_MFD_MAX77693) += max77693.o
obj-$(CONFIG_MFD_MAX77843) += max77843.o
diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
new file mode 100644
index 0000000..e965261
--- /dev/null
+++ b/drivers/mfd/max77620.c
@@ -0,0 +1,898 @@
+/*
+ * Maxim MAX77620 MFD Driver
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Mallikarjun Kasoju <mkasoju@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/mfd/core.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/mfd/max77620.h>
+
+static struct resource gpio_resources[] = {
+ {
+ .start = MAX77620_IRQ_TOP_GPIO,
+ .end = MAX77620_IRQ_TOP_GPIO,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource thermal_resources[] = {
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM1,
+ .end = MAX77620_IRQ_LBT_TJALRM1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM2,
+ .end = MAX77620_IRQ_LBT_TJALRM2,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static const struct regmap_irq max77620_top_irqs[] = {
+ [MAX77620_IRQ_TOP_GLBL] = {
+ .mask = MAX77620_IRQ_TOP_GLBL_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_SD] = {
+ .mask = MAX77620_IRQ_TOP_SD_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_LDO] = {
+ .mask = MAX77620_IRQ_TOP_LDO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_GPIO] = {
+ .mask = MAX77620_IRQ_TOP_GPIO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_RTC] = {
+ .mask = MAX77620_IRQ_TOP_RTC_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_32K] = {
+ .mask = MAX77620_IRQ_TOP_32K_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_ONOFF] = {
+ .mask = MAX77620_IRQ_TOP_ONOFF_MASK,
+ .reg_offset = 0,
+ },
+
+ [MAX77620_IRQ_LBT_MBATLOW] = {
+ .mask = MAX77620_IRQ_LBM_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM1] = {
+ .mask = MAX77620_IRQ_TJALRM1_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM2] = {
+ .mask = MAX77620_IRQ_TJALRM2_MASK,
+ .reg_offset = 1,
+ },
+
+};
+
+static const char * const max77620_nverc[] = {
+ "Shutdown-pin",
+ "System WatchDog Timer",
+ "Hard Reset",
+ "Junction Temp Overload",
+ "Main-Battery Low",
+ "Main-Battery overvoltage Lockout",
+ "Main-Battery undervoltage Lockout",
+ "Reset input",
+};
+
+enum max77660_ids {
+ MAX77620_PMIC_ID,
+ MAX77620_GPIO_ID,
+ MAX77620_PINCTRL_ID,
+ MAX77620_CLK_ID,
+ MAX77620_POWER_OFF_ID,
+ MAX77620_WDT_ID,
+ MAX77620_THERMAL_ID,
+ MAX77620_RTC_ID,
+};
+
+#define MAX77620_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX77620_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+static struct mfd_cell max77620_children[] = {
+ MAX77620_SUB_MODULE_RES(gpio, GPIO),
+ MAX77620_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX77620_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX77620_SUB_MODULE_NO_RES(clk, CLK),
+ MAX77620_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX77620_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX77620_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+static struct mfd_cell max20024_children[] = {
+ MAX20024_SUB_MODULE_RES(gpio, GPIO),
+ MAX20024_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX20024_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX20024_SUB_MODULE_NO_RES(clk, CLK),
+ MAX20024_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX20024_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX20024_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+struct max77620_sub_modules {
+ struct mfd_cell *cells;
+ int ncells;
+ u32 id;
+};
+
+static const struct max77620_sub_modules max77620_cells = {
+ .cells = max77620_children,
+ .ncells = ARRAY_SIZE(max77620_children),
+ .id = MAX77620,
+};
+
+static const struct max77620_sub_modules max20024_cells = {
+ .cells = max20024_children,
+ .ncells = ARRAY_SIZE(max20024_children),
+ .id = MAX20024,
+};
+
+static struct regmap_irq_chip max77620_top_irq_chip = {
+ .name = "max77620-top",
+ .irqs = max77620_top_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_top_irqs),
+ .num_regs = 2,
+ .status_base = MAX77620_REG_IRQTOP,
+ .mask_base = MAX77620_REG_IRQTOPM,
+};
+
+static const struct regmap_range max77620_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_readable_table = {
+ .yes_ranges = max77620_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
+};
+
+static const struct regmap_range max20024_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+ regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
+};
+
+static const struct regmap_access_table max20024_readable_table = {
+ .yes_ranges = max20024_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
+};
+
+static const struct regmap_range max77620_writable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_writable_table = {
+ .yes_ranges = max77620_writable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
+};
+
+static const struct regmap_range max77620_cacheable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
+ regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
+};
+
+static const struct regmap_access_table max77620_volatile_table = {
+ .no_ranges = max77620_cacheable_ranges,
+ .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
+};
+
+static const struct regmap_config max77620_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX77620_REG_DVSSD4 + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max77620_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+static const struct regmap_config max20024_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX20024_REG_MAX_ADD + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max20024_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+int max77620_irq_get_virq(struct device *dev, int irq)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_irq_get_virq(chip->top_irq_data, irq);
+}
+EXPORT_SYMBOL_GPL(max77620_irq_get_virq);
+
+int max77620_reg_write(struct device *dev, unsigned int reg, u8 val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_write(chip->rmap, reg, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_write);
+
+int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int ival;
+ int ret;
+
+ ret = regmap_read(chip->rmap, reg, &ival);
+ if (ret < 0)
+ return ret;
+ *val = ival;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(max77620_reg_read);
+
+int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_update_bits(chip->rmap, reg, mask, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_update);
+
+static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
+ int tperiod)
+{
+ int base_fps_time = (chip->id == MAX20024) ? 20 : 40;
+ int x, i;
+
+ for (i = 0; i < 0x7; ++i) {
+ x = base_fps_time * BIT(i);
+ if (x >= tperiod)
+ return i;
+ }
+
+ return i;
+}
+
+static int max77620_config_fps(struct max77620_chip *chip,
+ struct device_node *fps_np)
+{
+ struct device *dev = chip->dev;
+ unsigned int mask = 0, config = 0;
+ int input_enable = 2;
+ u32 pval;
+ int tperiod, fps_id;
+ int ret;
+
+ ret = of_property_read_u32(fps_np, "reg", &pval);
+ if (ret < 0) {
+ dev_err(dev, "reg prop missing from node %s\n", fps_np->name);
+ return 0;
+ }
+ if (pval > 2) {
+ dev_err(dev, "FPS%u is not supported\n", pval);
+ return 0;
+ }
+ fps_id = pval;
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,active-fps-time-period-us", &pval);
+ if (!ret) {
+ mask |= MAX77620_FPS_TIME_PERIOD_MASK;
+ chip->active_fps_period[fps_id] = min(pval, 5120U);
+ tperiod = max77620_get_fps_period_reg_value(
+ chip, chip->active_fps_period[fps_id]);
+ config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
+ }
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,suspend-fps-time-period-us", &pval);
+ if (!ret)
+ chip->suspend_fps_period[fps_id] = min(pval, 5120U);
+
+ ret = of_property_read_u32(fps_np, "maxim,fps-enable-input", &pval);
+ if (!ret) {
+ if (pval > 2) {
+ dev_err(dev, "FPS %d enable-input invalid\n", fps_id);
+ } else {
+ input_enable = pval;
+ mask |= MAX77620_FPS_EN_SRC_MASK;
+ }
+ }
+ config |= (input_enable & 0x3) << MAX77620_FPS_EN_SRC_SHIFT;
+
+ if (input_enable == 2) {
+ bool enable_fps = of_property_read_bool(fps_np,
+ "maxim,fps-sw-enable");
+ mask |= MAX77620_FPS_ENFPS_MASK;
+ if (enable_fps)
+ config |= 1;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(fps_np,
+ "maxim,enable-sleep");
+ if (!chip->enable_global_lpm)
+ chip->enable_global_lpm = of_property_read_bool(fps_np,
+ "maxim,enable-global-lpm");
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ mask, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_fps(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *fps_np, *fps_child;
+ u8 config;
+ int fps_id;
+ int ret;
+
+ for (fps_id = 0; fps_id < 3; ++fps_id) {
+ chip->active_fps_period[fps_id] = -1;
+ chip->suspend_fps_period[fps_id] = -1;
+ }
+
+ fps_np = of_get_child_by_name(dev->of_node, "fps");
+ if (!fps_np)
+ goto skip_fps;
+
+ for_each_child_of_node(fps_np, fps_child) {
+ ret = max77620_config_fps(chip, fps_child);
+ if (ret < 0)
+ return ret;
+ }
+
+ config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+skip_fps:
+ /* Enable wake on EN0 pin */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(dev->of_node,
+ "maxim,enable-sleep");
+
+ /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
+ if ((chip->id == MAX20024) && chip->sleep_enable) {
+ config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ config, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int max77620_init_backup_battery_charging(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *bb_node;
+ u32 pval;
+ u8 config;
+ int ret;
+
+ bb_node = of_get_child_by_name(dev->of_node, "backup-battery");
+ if (!bb_node) {
+ dev_dbg(dev, "Backup battery charging support disabled\n");
+ max77620_reg_update(chip->dev, MAX77620_REG_CNFGBBC,
+ MAX77620_CNFGBBC_ENABLE, 0);
+ return 0;
+ }
+
+ config = MAX77620_CNFGBBC_ENABLE;
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-current-microamp", &pval);
+ if (ret < 0)
+ pval = 50;
+ if (pval <= 50)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 100)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 200)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 400)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 600)
+ config |= 1 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else
+ config |= 2 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+
+ if (pval > 100)
+ config |= MAX77620_CNFGBBC_LOW_CURRENT_DISABLE;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-voltage-microvolt",
+ &pval);
+ if (ret < 0)
+ pval = 2500000;
+ pval /= 1000;
+ if (pval <= 2500)
+ config |= 0 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3000)
+ config |= 1 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3300)
+ config |= 2 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else
+ config |= 3 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-output-resister-ohm", &pval);
+ if (ret < 0)
+ pval = 1000;
+
+ if (pval <= 100)
+ config |= 0 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 1000)
+ config |= 1 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 3000)
+ config |= 2 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 6000)
+ config |= 3 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+
+ ret = max77620_reg_write(dev, MAX77620_REG_CNFGBBC, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_CNFGBBC, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_init_low_battery_monitor(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np;
+ u8 mask = 0, val = 0;
+ u32 pval;
+ int ret;
+
+ np = of_get_child_by_name(dev->of_node, "low-battery-monitor");
+ if (!np)
+ return 0;
+
+ ret = of_property_read_u32(np, "maxim,low-battery-dac", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-shutdown", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_MPPLD;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_MPPLD;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-reset", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBRSTEN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBRSTEN;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(dev, MAX77620_REG_CNFGGLBL1,
+ mask, val);
+ if (ret < 0)
+ dev_err(dev, "Reg CNFGGLBL1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_chip(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ u32 mrt_time = 0;
+ u8 reg_val;
+ int ret;
+
+ ret = of_property_read_u32(np, "maxim,hard-power-off-time", &mrt_time);
+ if (ret < 0)
+ return 0;
+
+ mrt_time = (mrt_time > 12) ? 12 : mrt_time;
+ if (mrt_time <= 6)
+ reg_val = mrt_time - 2;
+ else
+ reg_val = (mrt_time - 6) / 2 + 4;
+
+ reg_val <<= MAX77620_ONOFFCNFG1_MRT_SHIFT;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_MRT_MASK, reg_val);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable alarm wake to enable sleep from EN input signal */
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_ALARM1, 0);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int max77620_read_es_version(struct max77620_chip *chip)
+{
+ u8 val, cid_val[6];
+ int i;
+ int ret;
+
+ for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; ++i) {
+ ret = max77620_reg_read(chip->dev, i, &val);
+ if (ret < 0) {
+ dev_err(chip->dev, "CID%d register read failed: %d\n",
+ i - MAX77620_REG_CID0, ret);
+ return ret;
+ }
+ dev_dbg(chip->dev, "CID%d: 0x%02x\n",
+ i - MAX77620_REG_CID0, val);
+ cid_val[i - MAX77620_REG_CID0] = val;
+ }
+
+ /* CID4 is OTP Version and CID5 is ES version */
+ dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%02X\n",
+ cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
+
+ return ret;
+}
+
+static irqreturn_t max77620_mbattlow_irq(int irq, void *data)
+{
+ struct max77620_chip *max77620 = data;
+
+ dev_dbg(max77620->dev, "MBATTLOW interrupt occurred\n");
+
+ return IRQ_HANDLED;
+}
+
+static int max77620_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device_node *node = client->dev.of_node;
+ const struct max77620_sub_modules *children;
+ const struct regmap_config *rmap_config = &max77620_regmap_config;
+ struct max77620_chip *chip;
+ int ret = 0;
+
+ if (!node) {
+ dev_err(&client->dev, "Device is not from DT\n");
+ return -ENODEV;
+ }
+
+ children = of_device_get_match_data(&client->dev);
+ if (!children)
+ return -ENODEV;
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, chip);
+ chip->dev = &client->dev;
+ chip->irq_base = -1;
+ chip->chip_irq = client->irq;
+ chip->id = children->id;
+ chip->base_client = client;
+
+ if (chip->id == MAX20024)
+ rmap_config = &max20024_regmap_config;
+
+ chip->rmap = devm_regmap_init_i2c(chip->base_client, rmap_config);
+ if (IS_ERR(chip->rmap)) {
+ ret = PTR_ERR(chip->rmap);
+ dev_err(&client->dev, "regmap init failed %d\n", ret);
+ return ret;
+ }
+
+ mutex_init(&chip->mutex_config);
+
+ ret = max77620_read_es_version(chip);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_initialise_chip(chip, &client->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_add_irq_chip(chip->rmap, chip->chip_irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ chip->irq_base, &max77620_top_irq_chip,
+ &chip->top_irq_data);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to add top irq_chip %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_initialise_fps(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_backup_battery_charging(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_low_battery_monitor(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = mfd_add_devices(&client->dev, -1, children->cells,
+ children->ncells, NULL, 0,
+ regmap_irq_get_domain(chip->top_irq_data));
+ if (ret < 0) {
+ dev_err(&client->dev, "mfd add dev fail %d\n", ret);
+ goto fail_free_irq;
+ }
+
+ chip->irq_mbattlow = max77620_irq_get_virq(chip->dev,
+ MAX77620_IRQ_LBT_MBATLOW);
+ if (chip->irq_mbattlow) {
+ ret = devm_request_threaded_irq(chip->dev, chip->irq_mbattlow,
+ NULL, max77620_mbattlow_irq,
+ IRQF_ONESHOT,
+ dev_name(chip->dev), chip);
+ if (ret < 0)
+ dev_err(&client->dev, "request irq %d failed: %d\n",
+ chip->irq_mbattlow, ret);
+ }
+
+ return 0;
+
+fail_free_irq:
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return ret;
+}
+
+static int max77620_remove(struct i2c_client *client)
+{
+ struct max77620_chip *chip = i2c_get_clientdata(client);
+
+ mfd_remove_devices(chip->dev);
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_set_fps_period(struct max77620_chip *chip,
+ int fps_id, int time_period)
+{
+ struct device *dev = chip->dev;
+ int period = max77620_get_fps_period_reg_value(chip, time_period);
+ int ret;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ MAX77620_FPS_TIME_PERIOD_MASK,
+ period << MAX77620_FPS_TIME_PERIOD_SHIFT);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_i2c_suspend(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int config;
+ int fps;
+ int ret;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->suspend_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->suspend_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure SLPEN on suspend as
+ * it will be configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_SLPEN,
+ config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0, 0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ disable_irq(chip->chip_irq);
+
+ return 0;
+}
+
+static int max77620_i2c_resume(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ int ret;
+ int fps;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->active_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->active_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure WKEN0 on resume as
+ * it is configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ /* Enable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ enable_irq(chip->chip_irq);
+
+ return 0;
+}
+#endif
+
+static const struct i2c_device_id max77620_id[] = {
+ {"max77620", MAX77620},
+ {"max20024", MAX20024},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, max77620_id);
+
+static const struct of_device_id max77620_of_match[] = {
+ {
+ .compatible = "maxim,max77620",
+ .data = &max77620_cells,
+ }, {
+ .compatible = "maxim,max20024",
+ .data = &max20024_cells,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, max77620_of_match);
+
+static const struct dev_pm_ops max77620_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
+};
+
+static struct i2c_driver max77620_driver = {
+ .driver = {
+ .name = "max77620",
+ .pm = &max77620_pm_ops,
+ .of_match_table = max77620_of_match,
+ },
+ .probe = max77620_probe,
+ .remove = max77620_remove,
+ .id_table = max77620_id,
+};
+
+static int __init max77620_init(void)
+{
+ return i2c_add_driver(&max77620_driver);
+}
+subsys_initcall(max77620_init);
+
+static void __exit max77620_exit(void)
+{
+ i2c_del_driver(&max77620_driver);
+}
+module_exit(max77620_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_ALIAS("i2c:max77620");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
new file mode 100644
index 0000000..2bb4829
--- /dev/null
+++ b/include/linux/mfd/max77620.h
@@ -0,0 +1,402 @@
+/*
+ * max77620.h: Defining registers address and its bit definitions
+ * of MAX77620 and MAX20024
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _LINUX_MFD_MAX77620_H_
+#define _LINUX_MFD_MAX77620_H_
+
+/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
+#define MAX77620_REG_CNFGGLBL1 0x00
+#define MAX77620_REG_CNFGGLBL2 0x01
+#define MAX77620_REG_CNFGGLBL3 0x02
+#define MAX77620_REG_CNFG1_32K 0x03
+#define MAX77620_REG_CNFGBBC 0x04
+#define MAX77620_REG_IRQTOP 0x05
+#define MAX77620_REG_INTLBT 0x06
+#define MAX77620_REG_IRQSD 0x07
+#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
+#define MAX77620_REG_IRQ_LVL2_L8 0x09
+#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
+#define MAX77620_REG_ONOFFIRQ 0x0B
+#define MAX77620_REG_NVERC 0x0C
+#define MAX77620_REG_IRQTOPM 0x0D
+#define MAX77620_REG_INTENLBT 0x0E
+#define MAX77620_REG_IRQMASKSD 0x0F
+#define MAX77620_REG_IRQ_MSK_L0_7 0x10
+#define MAX77620_REG_IRQ_MSK_L8 0x11
+#define MAX77620_REG_ONOFFIRQM 0x12
+#define MAX77620_REG_STATLBT 0x13
+#define MAX77620_REG_STATSD 0x14
+#define MAX77620_REG_ONOFFSTAT 0x15
+
+/* SD and LDO Registers */
+#define MAX77620_REG_SD0 0x16
+#define MAX77620_REG_SD1 0x17
+#define MAX77620_REG_SD2 0x18
+#define MAX77620_REG_SD3 0x19
+#define MAX77620_REG_SD4 0x1A
+#define MAX77620_REG_DVSSD0 0x1B
+#define MAX77620_REG_DVSSD1 0x1C
+#define MAX77620_REG_SD0_CFG 0x1D
+#define MAX77620_REG_SD1_CFG 0x1E
+#define MAX77620_REG_SD2_CFG 0x1F
+#define MAX77620_REG_SD3_CFG 0x20
+#define MAX77620_REG_SD4_CFG 0x21
+#define MAX77620_REG_SD_CFG2 0x22
+#define MAX77620_REG_LDO0_CFG 0x23
+#define MAX77620_REG_LDO0_CFG2 0x24
+#define MAX77620_REG_LDO1_CFG 0x25
+#define MAX77620_REG_LDO1_CFG2 0x26
+#define MAX77620_REG_LDO2_CFG 0x27
+#define MAX77620_REG_LDO2_CFG2 0x28
+#define MAX77620_REG_LDO3_CFG 0x29
+#define MAX77620_REG_LDO3_CFG2 0x2A
+#define MAX77620_REG_LDO4_CFG 0x2B
+#define MAX77620_REG_LDO4_CFG2 0x2C
+#define MAX77620_REG_LDO5_CFG 0x2D
+#define MAX77620_REG_LDO5_CFG2 0x2E
+#define MAX77620_REG_LDO6_CFG 0x2F
+#define MAX77620_REG_LDO6_CFG2 0x30
+#define MAX77620_REG_LDO7_CFG 0x31
+#define MAX77620_REG_LDO7_CFG2 0x32
+#define MAX77620_REG_LDO8_CFG 0x33
+#define MAX77620_REG_LDO8_CFG2 0x34
+#define MAX77620_REG_LDO_CFG3 0x35
+
+#define MAX77620_LDO_SLEW_RATE_MASK 0x1
+
+/* LDO Configuration 3 */
+#define MAX77620_TRACK4_MASK BIT(5)
+#define MAX77620_TRACK4_SHIFT 5
+
+/* Voltage */
+#define MAX77620_SDX_VOLT_MASK 0xFF
+#define MAX77620_SD0_VOLT_MASK 0x3F
+#define MAX77620_SD1_VOLT_MASK 0x7F
+#define MAX77620_LDO_VOLT_MASK 0x3F
+
+#define MAX77620_REG_GPIO0 0x36
+#define MAX77620_REG_GPIO1 0x37
+#define MAX77620_REG_GPIO2 0x38
+#define MAX77620_REG_GPIO3 0x39
+#define MAX77620_REG_GPIO4 0x3A
+#define MAX77620_REG_GPIO5 0x3B
+#define MAX77620_REG_GPIO6 0x3C
+#define MAX77620_REG_GPIO7 0x3D
+#define MAX77620_REG_PUE_GPIO 0x3E
+#define MAX77620_REG_PDE_GPIO 0x3F
+#define MAX77620_REG_AME_GPIO 0x40
+#define MAX77620_REG_ONOFFCNFG1 0x41
+#define MAX77620_REG_ONOFFCNFG2 0x42
+
+/* FPS Registers */
+#define MAX77620_REG_FPS_CFG0 0x43
+#define MAX77620_REG_FPS_CFG1 0x44
+#define MAX77620_REG_FPS_CFG2 0x45
+#define MAX77620_REG_FPS_LDO0 0x46
+#define MAX77620_REG_FPS_LDO1 0x47
+#define MAX77620_REG_FPS_LDO2 0x48
+#define MAX77620_REG_FPS_LDO3 0x49
+#define MAX77620_REG_FPS_LDO4 0x4A
+#define MAX77620_REG_FPS_LDO5 0x4B
+#define MAX77620_REG_FPS_LDO6 0x4C
+#define MAX77620_REG_FPS_LDO7 0x4D
+#define MAX77620_REG_FPS_LDO8 0x4E
+#define MAX77620_REG_FPS_SD0 0x4F
+#define MAX77620_REG_FPS_SD1 0x50
+#define MAX77620_REG_FPS_SD2 0x51
+#define MAX77620_REG_FPS_SD3 0x52
+#define MAX77620_REG_FPS_SD4 0x53
+#define MAX77620_REG_FPS_NONE 0
+
+#define MAX77620_FPS_SRC_MASK 0xC0
+#define MAX77620_FPS_SRC_SHIFT 6
+#define MAX77620_FPS_PU_PERIOD_MASK 0x38
+#define MAX77620_FPS_PU_PERIOD_SHIFT 3
+#define MAX77620_FPS_PD_PERIOD_MASK 0x07
+#define MAX77620_FPS_PD_PERIOD_SHIFT 0
+#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
+#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
+#define MAX77620_FPS_EN_SRC_MASK 0x06
+#define MAX77620_FPS_EN_SRC_SHIFT 1
+#define MAX77620_FPS_ENFPS_MASK 0x01
+
+#define MAX77620_REG_FPS_GPIO1 0x54
+#define MAX77620_REG_FPS_GPIO2 0x55
+#define MAX77620_REG_FPS_GPIO3 0x56
+#define MAX77620_REG_FPS_RSO 0x57
+#define MAX77620_REG_CID0 0x58
+#define MAX77620_REG_CID1 0x59
+#define MAX77620_REG_CID2 0x5A
+#define MAX77620_REG_CID3 0x5B
+#define MAX77620_REG_CID4 0x5C
+#define MAX77620_REG_CID5 0x5D
+
+#define MAX77620_REG_DVSSD4 0x5E
+#define MAX20024_REG_MAX_ADD 0x70
+
+#define MAX77620_CID_DIDM_MASK 0xF0
+#define MAX77620_CID_DIDM_SHIFT 4
+
+/* CNCG2SD */
+#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
+#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
+
+/* Device Identification Metal */
+#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
+/* Device Indentification OTP */
+#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
+
+/* SD CNFG1 */
+#define MAX77620_SD_SR_MASK 0xC0
+#define MAX77620_SD_SR_SHIFT 6
+#define MAX77620_SD_POWER_MODE_MASK 0x30
+#define MAX77620_SD_POWER_MODE_SHIFT 4
+#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
+#define MAX77620_SD_CFG1_ADE_DISABLE 0
+#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
+#define MAX77620_SD_FPWM_MASK 0x04
+#define MAX77620_SD_FPWM_SHIFT 2
+#define MAX77620_SD_FSRADE_MASK 0x01
+#define MAX77620_SD_FSRADE_SHIFT 0
+#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
+#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
+#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
+#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
+#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
+#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
+
+/* LDO_CNFG2 */
+#define MAX77620_LDO_POWER_MODE_MASK 0xC0
+#define MAX77620_LDO_POWER_MODE_SHIFT 6
+#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
+#define MAX77620_LDO_CFG2_ADE_DISABLE 0
+#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
+#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
+#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
+#define MAX77620_LDO_CFG2_SS_SLOW 0
+
+#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
+#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
+#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
+#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
+#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
+#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
+#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
+
+#define MAX77620_IRQ_LBM_MASK BIT(3)
+#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
+#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
+
+#define MAX77620_PWR_I2C_ADDR 0x3c
+#define MAX77620_RTC_I2C_ADDR 0x68
+
+#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
+#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
+#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
+#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
+#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
+#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
+#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
+
+#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
+
+#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
+
+#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
+#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
+#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
+#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
+#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
+#define MAX20024_ONOFFCNFG1_CLRSE 0x18
+
+#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
+#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
+#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
+#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
+#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
+
+#define MAX77620_GLBLM_MASK BIT(0)
+
+#define MAX77620_WDTC_MASK 0x3
+#define MAX77620_WDTOFFC BIT(4)
+#define MAX77620_WDTSLPC BIT(3)
+#define MAX77620_WDTEN BIT(2)
+
+#define MAX77620_TWD_MASK 0x3
+#define MAX77620_TWD_2s 0x0
+#define MAX77620_TWD_16s 0x1
+#define MAX77620_TWD_64s 0x2
+#define MAX77620_TWD_128s 0x3
+
+#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
+#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
+#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
+#define MAX77620_CNFGGLBL1_LBDAC 0x0E
+#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
+
+/* CNFG BBC registers */
+#define MAX77620_CNFGBBC_ENABLE BIT(0)
+#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
+#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
+#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
+#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
+#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
+#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
+#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
+
+/* I2c Slave Id */
+enum {
+ MAX77620_PWR_SLAVE,
+ MAX77620_RTC_SLAVE,
+ MAX77620_NUM_SLAVES,
+};
+
+/* GPIOs */
+enum {
+ MAX77620_GPIO0,
+ MAX77620_GPIO1,
+ MAX77620_GPIO2,
+ MAX77620_GPIO3,
+ MAX77620_GPIO4,
+ MAX77620_GPIO5,
+ MAX77620_GPIO6,
+ MAX77620_GPIO7,
+
+ MAX77620_GPIO_NR,
+};
+
+/* Interrupts */
+enum {
+ MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
+ MAX77620_IRQ_TOP_SD, /* SD power fail */
+ MAX77620_IRQ_TOP_LDO, /* LDO power fail */
+ MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
+ MAX77620_IRQ_TOP_RTC, /* RTC */
+ MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
+ MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
+
+ MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
+
+ MAX77620_IRQ_GPIO0, /* GPIO0 edge detection */
+ MAX77620_IRQ_GPIO1, /* GPIO1 edge detection */
+ MAX77620_IRQ_GPIO2, /* GPIO2 edge detection */
+ MAX77620_IRQ_GPIO3, /* GPIO3 edge detection */
+ MAX77620_IRQ_GPIO4, /* GPIO4 edge detection */
+ MAX77620_IRQ_GPIO5, /* GPIO5 edge detection */
+ MAX77620_IRQ_GPIO6, /* GPIO6 edge detection */
+ MAX77620_IRQ_GPIO7, /* GPIO7 edge detection */
+
+ MAX77620_IRQ_ONOFF_MRWRN, /* Hard power off warnning */
+ MAX77620_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */
+ MAX77620_IRQ_ONOFF_EN0_F, /* EN0 falling */
+ MAX77620_IRQ_ONOFF_EN0_R, /* EN0 rising */
+ MAX77620_IRQ_ONOFF_LID_F, /* LID falling */
+ MAX77620_IRQ_ONOFF_LID_R, /* LID rising */
+ MAX77620_IRQ_ONOFF_ACOK_F, /* ACOK falling */
+ MAX77620_IRQ_ONOFF_ACOK_R, /* ACOK rising */
+
+ MAX77620_IRQ_NVER, /* Non-Volatile Event Recorder */
+ MAX77620_IRQ_NR,
+};
+
+enum max77620_regulators {
+ MAX77620_REGULATOR_ID_SD0,
+ MAX77620_REGULATOR_ID_SD1,
+ MAX77620_REGULATOR_ID_SD2,
+ MAX77620_REGULATOR_ID_SD3,
+ MAX77620_REGULATOR_ID_SD4,
+ MAX77620_REGULATOR_ID_LDO0,
+ MAX77620_REGULATOR_ID_LDO1,
+ MAX77620_REGULATOR_ID_LDO2,
+ MAX77620_REGULATOR_ID_LDO3,
+ MAX77620_REGULATOR_ID_LDO4,
+ MAX77620_REGULATOR_ID_LDO5,
+ MAX77620_REGULATOR_ID_LDO6,
+ MAX77620_REGULATOR_ID_LDO7,
+ MAX77620_REGULATOR_ID_LDO8,
+ MAX77620_NUM_REGS,
+};
+
+/* FPS Source */
+enum max77620_regulator_fps_src {
+ FPS_SRC_0,
+ FPS_SRC_1,
+ FPS_SRC_2,
+ FPS_SRC_NONE,
+ FPS_SRC_DEF,
+};
+
+/* Regulator types */
+enum max77620_regulator_type {
+ MAX77620_REGULATOR_TYPE_SD,
+ MAX77620_REGULATOR_TYPE_LDO_N,
+ MAX77620_REGULATOR_TYPE_LDO_P,
+};
+
+enum max77620_chip_id {
+ MAX77620,
+ MAX20024,
+};
+
+struct max77620_chip {
+ struct device *dev;
+
+ struct i2c_client *base_client;
+ struct regmap *rmap;
+
+ int chip_irq;
+ int irq_base;
+ int irq_mbattlow;
+
+ struct mutex mutex_config;
+ bool sleep_enable;
+ bool enable_global_lpm;
+ int active_fps_period[3];
+ int suspend_fps_period[3];
+
+ struct regmap_irq_chip_data *top_irq_data;
+ struct regmap_irq_chip_data *gpio_irq_data;
+
+ /* chip id */
+ u32 id;
+};
+
+extern int max77620_irq_get_virq(struct device *dev, int irq);
+extern int max77620_reg_write(struct device *dev, unsigned int reg, u8 val);
+extern int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val);
+extern int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val);
+#endif /* _LINUX_MFD_MAX77620_H_ */
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH V3 2/5] mfd: max77620: add core driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi,
Mallikarjun Kasoju
MAX77620/MAX20024 are Power Management IC from the MAXIM.
It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
watchdog, clock etc.
Add MFD drier to provides common support for accessing the
device; additional drivers is developed on respected subsystem
in order to use the functionality of the device.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Code cleanups per review from V1.
- Move register acccess APIs from header to c file.
- Remove some of non required variable, remove duplication in error message
and simplify some of function implementation.
- Register RTC driver such that it can get the regmap handle form parent device
Changes from V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Drop RTC driver and its i2c client registration.
drivers/mfd/Kconfig | 15 +
drivers/mfd/Makefile | 1 +
drivers/mfd/max77620.c | 898 +++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/max77620.h | 402 +++++++++++++++++++
4 files changed, 1316 insertions(+)
create mode 100644 drivers/mfd/max77620.c
create mode 100644 include/linux/mfd/max77620.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9581ebb..edeb85c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -492,6 +492,21 @@ config MFD_MAX14577
additional drivers must be enabled in order to use the functionality
of the device.
+config MFD_MAX77620
+ bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
+ depends on I2C=y
+ depends on OF
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for Maxim Semiconductor MAX77620 and
+ MAX20024 which are Power Management IC with General purpose pins,
+ RTC, regulators, clock generator, watchdog etc. This driver
+ provides common support for accessing the device; additional drivers
+ must be enabled in order to use the functionality of the device.
+
config MFD_MAX77686
bool "Maxim Semiconductor MAX77686/802 PMIC Support"
depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0f230a6..97910ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
obj-$(CONFIG_MFD_DA9150) += da9150-core.o
obj-$(CONFIG_MFD_MAX14577) += max14577.o
+obj-$(CONFIG_MFD_MAX77620) += max77620.o
obj-$(CONFIG_MFD_MAX77686) += max77686.o
obj-$(CONFIG_MFD_MAX77693) += max77693.o
obj-$(CONFIG_MFD_MAX77843) += max77843.o
diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
new file mode 100644
index 0000000..e965261
--- /dev/null
+++ b/drivers/mfd/max77620.c
@@ -0,0 +1,898 @@
+/*
+ * Maxim MAX77620 MFD Driver
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Mallikarjun Kasoju <mkasoju@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/mfd/core.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/mfd/max77620.h>
+
+static struct resource gpio_resources[] = {
+ {
+ .start = MAX77620_IRQ_TOP_GPIO,
+ .end = MAX77620_IRQ_TOP_GPIO,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource thermal_resources[] = {
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM1,
+ .end = MAX77620_IRQ_LBT_TJALRM1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MAX77620_IRQ_LBT_TJALRM2,
+ .end = MAX77620_IRQ_LBT_TJALRM2,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static const struct regmap_irq max77620_top_irqs[] = {
+ [MAX77620_IRQ_TOP_GLBL] = {
+ .mask = MAX77620_IRQ_TOP_GLBL_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_SD] = {
+ .mask = MAX77620_IRQ_TOP_SD_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_LDO] = {
+ .mask = MAX77620_IRQ_TOP_LDO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_GPIO] = {
+ .mask = MAX77620_IRQ_TOP_GPIO_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_RTC] = {
+ .mask = MAX77620_IRQ_TOP_RTC_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_32K] = {
+ .mask = MAX77620_IRQ_TOP_32K_MASK,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_TOP_ONOFF] = {
+ .mask = MAX77620_IRQ_TOP_ONOFF_MASK,
+ .reg_offset = 0,
+ },
+
+ [MAX77620_IRQ_LBT_MBATLOW] = {
+ .mask = MAX77620_IRQ_LBM_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM1] = {
+ .mask = MAX77620_IRQ_TJALRM1_MASK,
+ .reg_offset = 1,
+ },
+ [MAX77620_IRQ_LBT_TJALRM2] = {
+ .mask = MAX77620_IRQ_TJALRM2_MASK,
+ .reg_offset = 1,
+ },
+
+};
+
+static const char * const max77620_nverc[] = {
+ "Shutdown-pin",
+ "System WatchDog Timer",
+ "Hard Reset",
+ "Junction Temp Overload",
+ "Main-Battery Low",
+ "Main-Battery overvoltage Lockout",
+ "Main-Battery undervoltage Lockout",
+ "Reset input",
+};
+
+enum max77660_ids {
+ MAX77620_PMIC_ID,
+ MAX77620_GPIO_ID,
+ MAX77620_PINCTRL_ID,
+ MAX77620_CLK_ID,
+ MAX77620_POWER_OFF_ID,
+ MAX77620_WDT_ID,
+ MAX77620_THERMAL_ID,
+ MAX77620_RTC_ID,
+};
+
+#define MAX77620_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .num_resources = ARRAY_SIZE(_name##_resources), \
+ .resources = &_name##_resources[0], \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX77620_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max77620-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+#define MAX20024_SUB_MODULE_NO_RES(_name, _id) \
+ [MAX77620_##_id##_ID] = { \
+ .name = "max20024-"#_name, \
+ .id = MAX77620_##_id##_ID, \
+ }
+
+static struct mfd_cell max77620_children[] = {
+ MAX77620_SUB_MODULE_RES(gpio, GPIO),
+ MAX77620_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX77620_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX77620_SUB_MODULE_NO_RES(clk, CLK),
+ MAX77620_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX77620_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX77620_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+static struct mfd_cell max20024_children[] = {
+ MAX20024_SUB_MODULE_RES(gpio, GPIO),
+ MAX20024_SUB_MODULE_NO_RES(pmic, PMIC),
+ MAX20024_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
+ MAX20024_SUB_MODULE_NO_RES(clk, CLK),
+ MAX20024_SUB_MODULE_NO_RES(power-off, POWER_OFF),
+ MAX20024_SUB_MODULE_NO_RES(wdt, WDT),
+ MAX20024_SUB_MODULE_RES(thermal, THERMAL),
+};
+
+struct max77620_sub_modules {
+ struct mfd_cell *cells;
+ int ncells;
+ u32 id;
+};
+
+static const struct max77620_sub_modules max77620_cells = {
+ .cells = max77620_children,
+ .ncells = ARRAY_SIZE(max77620_children),
+ .id = MAX77620,
+};
+
+static const struct max77620_sub_modules max20024_cells = {
+ .cells = max20024_children,
+ .ncells = ARRAY_SIZE(max20024_children),
+ .id = MAX20024,
+};
+
+static struct regmap_irq_chip max77620_top_irq_chip = {
+ .name = "max77620-top",
+ .irqs = max77620_top_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_top_irqs),
+ .num_regs = 2,
+ .status_base = MAX77620_REG_IRQTOP,
+ .mask_base = MAX77620_REG_IRQTOPM,
+};
+
+static const struct regmap_range max77620_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_readable_table = {
+ .yes_ranges = max77620_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
+};
+
+static const struct regmap_range max20024_readable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+ regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
+};
+
+static const struct regmap_access_table max20024_readable_table = {
+ .yes_ranges = max20024_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
+};
+
+static const struct regmap_range max77620_writable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
+};
+
+static const struct regmap_access_table max77620_writable_table = {
+ .yes_ranges = max77620_writable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
+};
+
+static const struct regmap_range max77620_cacheable_ranges[] = {
+ regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
+ regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
+};
+
+static const struct regmap_access_table max77620_volatile_table = {
+ .no_ranges = max77620_cacheable_ranges,
+ .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
+};
+
+static const struct regmap_config max77620_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX77620_REG_DVSSD4 + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max77620_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+static const struct regmap_config max20024_regmap_config = {
+ .name = "power-slave",
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = MAX20024_REG_MAX_ADD + 1,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &max20024_readable_table,
+ .wr_table = &max77620_writable_table,
+ .volatile_table = &max77620_volatile_table,
+};
+
+int max77620_irq_get_virq(struct device *dev, int irq)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_irq_get_virq(chip->top_irq_data, irq);
+}
+EXPORT_SYMBOL_GPL(max77620_irq_get_virq);
+
+int max77620_reg_write(struct device *dev, unsigned int reg, u8 val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_write(chip->rmap, reg, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_write);
+
+int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int ival;
+ int ret;
+
+ ret = regmap_read(chip->rmap, reg, &ival);
+ if (ret < 0)
+ return ret;
+ *val = ival;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(max77620_reg_read);
+
+int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+
+ return regmap_update_bits(chip->rmap, reg, mask, val);
+}
+EXPORT_SYMBOL_GPL(max77620_reg_update);
+
+static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
+ int tperiod)
+{
+ int base_fps_time = (chip->id == MAX20024) ? 20 : 40;
+ int x, i;
+
+ for (i = 0; i < 0x7; ++i) {
+ x = base_fps_time * BIT(i);
+ if (x >= tperiod)
+ return i;
+ }
+
+ return i;
+}
+
+static int max77620_config_fps(struct max77620_chip *chip,
+ struct device_node *fps_np)
+{
+ struct device *dev = chip->dev;
+ unsigned int mask = 0, config = 0;
+ int input_enable = 2;
+ u32 pval;
+ int tperiod, fps_id;
+ int ret;
+
+ ret = of_property_read_u32(fps_np, "reg", &pval);
+ if (ret < 0) {
+ dev_err(dev, "reg prop missing from node %s\n", fps_np->name);
+ return 0;
+ }
+ if (pval > 2) {
+ dev_err(dev, "FPS%u is not supported\n", pval);
+ return 0;
+ }
+ fps_id = pval;
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,active-fps-time-period-us", &pval);
+ if (!ret) {
+ mask |= MAX77620_FPS_TIME_PERIOD_MASK;
+ chip->active_fps_period[fps_id] = min(pval, 5120U);
+ tperiod = max77620_get_fps_period_reg_value(
+ chip, chip->active_fps_period[fps_id]);
+ config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
+ }
+
+ ret = of_property_read_u32(fps_np,
+ "maxim,suspend-fps-time-period-us", &pval);
+ if (!ret)
+ chip->suspend_fps_period[fps_id] = min(pval, 5120U);
+
+ ret = of_property_read_u32(fps_np, "maxim,fps-enable-input", &pval);
+ if (!ret) {
+ if (pval > 2) {
+ dev_err(dev, "FPS %d enable-input invalid\n", fps_id);
+ } else {
+ input_enable = pval;
+ mask |= MAX77620_FPS_EN_SRC_MASK;
+ }
+ }
+ config |= (input_enable & 0x3) << MAX77620_FPS_EN_SRC_SHIFT;
+
+ if (input_enable == 2) {
+ bool enable_fps = of_property_read_bool(fps_np,
+ "maxim,fps-sw-enable");
+ mask |= MAX77620_FPS_ENFPS_MASK;
+ if (enable_fps)
+ config |= 1;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(fps_np,
+ "maxim,enable-sleep");
+ if (!chip->enable_global_lpm)
+ chip->enable_global_lpm = of_property_read_bool(fps_np,
+ "maxim,enable-global-lpm");
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ mask, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_fps(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *fps_np, *fps_child;
+ u8 config;
+ int fps_id;
+ int ret;
+
+ for (fps_id = 0; fps_id < 3; ++fps_id) {
+ chip->active_fps_period[fps_id] = -1;
+ chip->suspend_fps_period[fps_id] = -1;
+ }
+
+ fps_np = of_get_child_by_name(dev->of_node, "fps");
+ if (!fps_np)
+ goto skip_fps;
+
+ for_each_child_of_node(fps_np, fps_child) {
+ ret = max77620_config_fps(chip, fps_child);
+ if (ret < 0)
+ return ret;
+ }
+
+ config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+skip_fps:
+ /* Enable wake on EN0 pin */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+ if (!chip->sleep_enable)
+ chip->sleep_enable = of_property_read_bool(dev->of_node,
+ "maxim,enable-sleep");
+
+ /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
+ if ((chip->id == MAX20024) && chip->sleep_enable) {
+ config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ config, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int max77620_init_backup_battery_charging(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *bb_node;
+ u32 pval;
+ u8 config;
+ int ret;
+
+ bb_node = of_get_child_by_name(dev->of_node, "backup-battery");
+ if (!bb_node) {
+ dev_dbg(dev, "Backup battery charging support disabled\n");
+ max77620_reg_update(chip->dev, MAX77620_REG_CNFGBBC,
+ MAX77620_CNFGBBC_ENABLE, 0);
+ return 0;
+ }
+
+ config = MAX77620_CNFGBBC_ENABLE;
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-current-microamp", &pval);
+ if (ret < 0)
+ pval = 50;
+ if (pval <= 50)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 100)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 200)
+ config |= 0 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 400)
+ config |= 3 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else if (pval <= 600)
+ config |= 1 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+ else
+ config |= 2 << MAX77620_CNFGBBC_CURRENT_SHIFT;
+
+ if (pval > 100)
+ config |= MAX77620_CNFGBBC_LOW_CURRENT_DISABLE;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-charging-voltage-microvolt",
+ &pval);
+ if (ret < 0)
+ pval = 2500000;
+ pval /= 1000;
+ if (pval <= 2500)
+ config |= 0 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3000)
+ config |= 1 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else if (pval <= 3300)
+ config |= 2 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+ else
+ config |= 3 << MAX77620_CNFGBBC_VOLTAGE_SHIFT;
+
+ ret = of_property_read_u32(bb_node,
+ "maxim,bb-output-resister-ohm", &pval);
+ if (ret < 0)
+ pval = 1000;
+
+ if (pval <= 100)
+ config |= 0 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 1000)
+ config |= 1 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 3000)
+ config |= 2 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+ else if (pval <= 6000)
+ config |= 3 << MAX77620_CNFGBBC_RESISTOR_SHIFT;
+
+ ret = max77620_reg_write(dev, MAX77620_REG_CNFGBBC, config);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_CNFGBBC, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_init_low_battery_monitor(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np;
+ u8 mask = 0, val = 0;
+ u32 pval;
+ int ret;
+
+ np = of_get_child_by_name(dev->of_node, "low-battery-monitor");
+ if (!np)
+ return 0;
+
+ ret = of_property_read_u32(np, "maxim,low-battery-dac", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBDAC_EN;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-shutdown", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_MPPLD;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_MPPLD;
+ }
+
+ ret = of_property_read_u32(np, "maxim,low-battery-reset", &pval);
+ if (!ret) {
+ mask |= MAX77620_CNFGGLBL1_LBRSTEN;
+ if (pval)
+ val |= MAX77620_CNFGGLBL1_LBRSTEN;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(dev, MAX77620_REG_CNFGGLBL1,
+ mask, val);
+ if (ret < 0)
+ dev_err(dev, "Reg CNFGGLBL1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_initialise_chip(struct max77620_chip *chip,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ u32 mrt_time = 0;
+ u8 reg_val;
+ int ret;
+
+ ret = of_property_read_u32(np, "maxim,hard-power-off-time", &mrt_time);
+ if (ret < 0)
+ return 0;
+
+ mrt_time = (mrt_time > 12) ? 12 : mrt_time;
+ if (mrt_time <= 6)
+ reg_val = mrt_time - 2;
+ else
+ reg_val = (mrt_time - 6) / 2 + 4;
+
+ reg_val <<= MAX77620_ONOFFCNFG1_MRT_SHIFT;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_MRT_MASK, reg_val);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable alarm wake to enable sleep from EN input signal */
+ ret = max77620_reg_update(dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_ALARM1, 0);
+ if (ret < 0) {
+ dev_err(dev, "REG ONOFFCNFG2 update failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int max77620_read_es_version(struct max77620_chip *chip)
+{
+ u8 val, cid_val[6];
+ int i;
+ int ret;
+
+ for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; ++i) {
+ ret = max77620_reg_read(chip->dev, i, &val);
+ if (ret < 0) {
+ dev_err(chip->dev, "CID%d register read failed: %d\n",
+ i - MAX77620_REG_CID0, ret);
+ return ret;
+ }
+ dev_dbg(chip->dev, "CID%d: 0x%02x\n",
+ i - MAX77620_REG_CID0, val);
+ cid_val[i - MAX77620_REG_CID0] = val;
+ }
+
+ /* CID4 is OTP Version and CID5 is ES version */
+ dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%02X\n",
+ cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
+
+ return ret;
+}
+
+static irqreturn_t max77620_mbattlow_irq(int irq, void *data)
+{
+ struct max77620_chip *max77620 = data;
+
+ dev_dbg(max77620->dev, "MBATTLOW interrupt occurred\n");
+
+ return IRQ_HANDLED;
+}
+
+static int max77620_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device_node *node = client->dev.of_node;
+ const struct max77620_sub_modules *children;
+ const struct regmap_config *rmap_config = &max77620_regmap_config;
+ struct max77620_chip *chip;
+ int ret = 0;
+
+ if (!node) {
+ dev_err(&client->dev, "Device is not from DT\n");
+ return -ENODEV;
+ }
+
+ children = of_device_get_match_data(&client->dev);
+ if (!children)
+ return -ENODEV;
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, chip);
+ chip->dev = &client->dev;
+ chip->irq_base = -1;
+ chip->chip_irq = client->irq;
+ chip->id = children->id;
+ chip->base_client = client;
+
+ if (chip->id == MAX20024)
+ rmap_config = &max20024_regmap_config;
+
+ chip->rmap = devm_regmap_init_i2c(chip->base_client, rmap_config);
+ if (IS_ERR(chip->rmap)) {
+ ret = PTR_ERR(chip->rmap);
+ dev_err(&client->dev, "regmap init failed %d\n", ret);
+ return ret;
+ }
+
+ mutex_init(&chip->mutex_config);
+
+ ret = max77620_read_es_version(chip);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_initialise_chip(chip, &client->dev);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_add_irq_chip(chip->rmap, chip->chip_irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ chip->irq_base, &max77620_top_irq_chip,
+ &chip->top_irq_data);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to add top irq_chip %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_initialise_fps(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_backup_battery_charging(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = max77620_init_low_battery_monitor(chip, &client->dev);
+ if (ret < 0)
+ goto fail_free_irq;
+
+ ret = mfd_add_devices(&client->dev, -1, children->cells,
+ children->ncells, NULL, 0,
+ regmap_irq_get_domain(chip->top_irq_data));
+ if (ret < 0) {
+ dev_err(&client->dev, "mfd add dev fail %d\n", ret);
+ goto fail_free_irq;
+ }
+
+ chip->irq_mbattlow = max77620_irq_get_virq(chip->dev,
+ MAX77620_IRQ_LBT_MBATLOW);
+ if (chip->irq_mbattlow) {
+ ret = devm_request_threaded_irq(chip->dev, chip->irq_mbattlow,
+ NULL, max77620_mbattlow_irq,
+ IRQF_ONESHOT,
+ dev_name(chip->dev), chip);
+ if (ret < 0)
+ dev_err(&client->dev, "request irq %d failed: %d\n",
+ chip->irq_mbattlow, ret);
+ }
+
+ return 0;
+
+fail_free_irq:
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return ret;
+}
+
+static int max77620_remove(struct i2c_client *client)
+{
+ struct max77620_chip *chip = i2c_get_clientdata(client);
+
+ mfd_remove_devices(chip->dev);
+ regmap_del_irq_chip(chip->chip_irq, chip->top_irq_data);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_set_fps_period(struct max77620_chip *chip,
+ int fps_id, int time_period)
+{
+ struct device *dev = chip->dev;
+ int period = max77620_get_fps_period_reg_value(chip, time_period);
+ int ret;
+
+ ret = max77620_reg_update(dev, MAX77620_REG_FPS_CFG0 + fps_id,
+ MAX77620_FPS_TIME_PERIOD_MASK,
+ period << MAX77620_FPS_TIME_PERIOD_SHIFT);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x write failed: %d\n",
+ MAX77620_REG_FPS_CFG0 + fps_id, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int max77620_i2c_suspend(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ unsigned int config;
+ int fps;
+ int ret;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->suspend_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->suspend_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure SLPEN on suspend as
+ * it will be configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG1,
+ MAX77620_ONOFFCNFG1_SLPEN,
+ config);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG1 update failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Disable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0, 0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ disable_irq(chip->chip_irq);
+
+ return 0;
+}
+
+static int max77620_i2c_resume(struct device *dev)
+{
+ struct max77620_chip *chip = dev_get_drvdata(dev);
+ int ret;
+ int fps;
+
+ for (fps = 0; fps < 2; ++fps) {
+ if (chip->active_fps_period[fps] < 0)
+ continue;
+
+ ret = max77620_set_fps_period(chip, fps,
+ chip->active_fps_period[fps]);
+ if (ret < 0)
+ dev_err(dev, "FPS%d config failed: %d\n", fps, ret);
+ }
+
+ /*
+ * For MAX20024: No need to configure WKEN0 on resume as
+ * it is configured on Init.
+ */
+ if (chip->id == MAX20024)
+ goto out;
+
+ /* Enable WK_EN0 */
+ ret = max77620_reg_update(chip->dev, MAX77620_REG_ONOFFCNFG2,
+ MAX77620_ONOFFCNFG2_WK_EN0,
+ MAX77620_ONOFFCNFG2_WK_EN0);
+ if (ret < 0) {
+ dev_err(dev, "Reg ONOFFCNFG2 WK_EN0 update failed: %d\n", ret);
+ return ret;
+ }
+
+out:
+ enable_irq(chip->chip_irq);
+
+ return 0;
+}
+#endif
+
+static const struct i2c_device_id max77620_id[] = {
+ {"max77620", MAX77620},
+ {"max20024", MAX20024},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, max77620_id);
+
+static const struct of_device_id max77620_of_match[] = {
+ {
+ .compatible = "maxim,max77620",
+ .data = &max77620_cells,
+ }, {
+ .compatible = "maxim,max20024",
+ .data = &max20024_cells,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, max77620_of_match);
+
+static const struct dev_pm_ops max77620_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
+};
+
+static struct i2c_driver max77620_driver = {
+ .driver = {
+ .name = "max77620",
+ .pm = &max77620_pm_ops,
+ .of_match_table = max77620_of_match,
+ },
+ .probe = max77620_probe,
+ .remove = max77620_remove,
+ .id_table = max77620_id,
+};
+
+static int __init max77620_init(void)
+{
+ return i2c_add_driver(&max77620_driver);
+}
+subsys_initcall(max77620_init);
+
+static void __exit max77620_exit(void)
+{
+ i2c_del_driver(&max77620_driver);
+}
+module_exit(max77620_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_ALIAS("i2c:max77620");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
new file mode 100644
index 0000000..2bb4829
--- /dev/null
+++ b/include/linux/mfd/max77620.h
@@ -0,0 +1,402 @@
+/*
+ * max77620.h: Defining registers address and its bit definitions
+ * of MAX77620 and MAX20024
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _LINUX_MFD_MAX77620_H_
+#define _LINUX_MFD_MAX77620_H_
+
+/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
+#define MAX77620_REG_CNFGGLBL1 0x00
+#define MAX77620_REG_CNFGGLBL2 0x01
+#define MAX77620_REG_CNFGGLBL3 0x02
+#define MAX77620_REG_CNFG1_32K 0x03
+#define MAX77620_REG_CNFGBBC 0x04
+#define MAX77620_REG_IRQTOP 0x05
+#define MAX77620_REG_INTLBT 0x06
+#define MAX77620_REG_IRQSD 0x07
+#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
+#define MAX77620_REG_IRQ_LVL2_L8 0x09
+#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
+#define MAX77620_REG_ONOFFIRQ 0x0B
+#define MAX77620_REG_NVERC 0x0C
+#define MAX77620_REG_IRQTOPM 0x0D
+#define MAX77620_REG_INTENLBT 0x0E
+#define MAX77620_REG_IRQMASKSD 0x0F
+#define MAX77620_REG_IRQ_MSK_L0_7 0x10
+#define MAX77620_REG_IRQ_MSK_L8 0x11
+#define MAX77620_REG_ONOFFIRQM 0x12
+#define MAX77620_REG_STATLBT 0x13
+#define MAX77620_REG_STATSD 0x14
+#define MAX77620_REG_ONOFFSTAT 0x15
+
+/* SD and LDO Registers */
+#define MAX77620_REG_SD0 0x16
+#define MAX77620_REG_SD1 0x17
+#define MAX77620_REG_SD2 0x18
+#define MAX77620_REG_SD3 0x19
+#define MAX77620_REG_SD4 0x1A
+#define MAX77620_REG_DVSSD0 0x1B
+#define MAX77620_REG_DVSSD1 0x1C
+#define MAX77620_REG_SD0_CFG 0x1D
+#define MAX77620_REG_SD1_CFG 0x1E
+#define MAX77620_REG_SD2_CFG 0x1F
+#define MAX77620_REG_SD3_CFG 0x20
+#define MAX77620_REG_SD4_CFG 0x21
+#define MAX77620_REG_SD_CFG2 0x22
+#define MAX77620_REG_LDO0_CFG 0x23
+#define MAX77620_REG_LDO0_CFG2 0x24
+#define MAX77620_REG_LDO1_CFG 0x25
+#define MAX77620_REG_LDO1_CFG2 0x26
+#define MAX77620_REG_LDO2_CFG 0x27
+#define MAX77620_REG_LDO2_CFG2 0x28
+#define MAX77620_REG_LDO3_CFG 0x29
+#define MAX77620_REG_LDO3_CFG2 0x2A
+#define MAX77620_REG_LDO4_CFG 0x2B
+#define MAX77620_REG_LDO4_CFG2 0x2C
+#define MAX77620_REG_LDO5_CFG 0x2D
+#define MAX77620_REG_LDO5_CFG2 0x2E
+#define MAX77620_REG_LDO6_CFG 0x2F
+#define MAX77620_REG_LDO6_CFG2 0x30
+#define MAX77620_REG_LDO7_CFG 0x31
+#define MAX77620_REG_LDO7_CFG2 0x32
+#define MAX77620_REG_LDO8_CFG 0x33
+#define MAX77620_REG_LDO8_CFG2 0x34
+#define MAX77620_REG_LDO_CFG3 0x35
+
+#define MAX77620_LDO_SLEW_RATE_MASK 0x1
+
+/* LDO Configuration 3 */
+#define MAX77620_TRACK4_MASK BIT(5)
+#define MAX77620_TRACK4_SHIFT 5
+
+/* Voltage */
+#define MAX77620_SDX_VOLT_MASK 0xFF
+#define MAX77620_SD0_VOLT_MASK 0x3F
+#define MAX77620_SD1_VOLT_MASK 0x7F
+#define MAX77620_LDO_VOLT_MASK 0x3F
+
+#define MAX77620_REG_GPIO0 0x36
+#define MAX77620_REG_GPIO1 0x37
+#define MAX77620_REG_GPIO2 0x38
+#define MAX77620_REG_GPIO3 0x39
+#define MAX77620_REG_GPIO4 0x3A
+#define MAX77620_REG_GPIO5 0x3B
+#define MAX77620_REG_GPIO6 0x3C
+#define MAX77620_REG_GPIO7 0x3D
+#define MAX77620_REG_PUE_GPIO 0x3E
+#define MAX77620_REG_PDE_GPIO 0x3F
+#define MAX77620_REG_AME_GPIO 0x40
+#define MAX77620_REG_ONOFFCNFG1 0x41
+#define MAX77620_REG_ONOFFCNFG2 0x42
+
+/* FPS Registers */
+#define MAX77620_REG_FPS_CFG0 0x43
+#define MAX77620_REG_FPS_CFG1 0x44
+#define MAX77620_REG_FPS_CFG2 0x45
+#define MAX77620_REG_FPS_LDO0 0x46
+#define MAX77620_REG_FPS_LDO1 0x47
+#define MAX77620_REG_FPS_LDO2 0x48
+#define MAX77620_REG_FPS_LDO3 0x49
+#define MAX77620_REG_FPS_LDO4 0x4A
+#define MAX77620_REG_FPS_LDO5 0x4B
+#define MAX77620_REG_FPS_LDO6 0x4C
+#define MAX77620_REG_FPS_LDO7 0x4D
+#define MAX77620_REG_FPS_LDO8 0x4E
+#define MAX77620_REG_FPS_SD0 0x4F
+#define MAX77620_REG_FPS_SD1 0x50
+#define MAX77620_REG_FPS_SD2 0x51
+#define MAX77620_REG_FPS_SD3 0x52
+#define MAX77620_REG_FPS_SD4 0x53
+#define MAX77620_REG_FPS_NONE 0
+
+#define MAX77620_FPS_SRC_MASK 0xC0
+#define MAX77620_FPS_SRC_SHIFT 6
+#define MAX77620_FPS_PU_PERIOD_MASK 0x38
+#define MAX77620_FPS_PU_PERIOD_SHIFT 3
+#define MAX77620_FPS_PD_PERIOD_MASK 0x07
+#define MAX77620_FPS_PD_PERIOD_SHIFT 0
+#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
+#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
+#define MAX77620_FPS_EN_SRC_MASK 0x06
+#define MAX77620_FPS_EN_SRC_SHIFT 1
+#define MAX77620_FPS_ENFPS_MASK 0x01
+
+#define MAX77620_REG_FPS_GPIO1 0x54
+#define MAX77620_REG_FPS_GPIO2 0x55
+#define MAX77620_REG_FPS_GPIO3 0x56
+#define MAX77620_REG_FPS_RSO 0x57
+#define MAX77620_REG_CID0 0x58
+#define MAX77620_REG_CID1 0x59
+#define MAX77620_REG_CID2 0x5A
+#define MAX77620_REG_CID3 0x5B
+#define MAX77620_REG_CID4 0x5C
+#define MAX77620_REG_CID5 0x5D
+
+#define MAX77620_REG_DVSSD4 0x5E
+#define MAX20024_REG_MAX_ADD 0x70
+
+#define MAX77620_CID_DIDM_MASK 0xF0
+#define MAX77620_CID_DIDM_SHIFT 4
+
+/* CNCG2SD */
+#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
+#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
+
+/* Device Identification Metal */
+#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
+/* Device Indentification OTP */
+#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
+
+/* SD CNFG1 */
+#define MAX77620_SD_SR_MASK 0xC0
+#define MAX77620_SD_SR_SHIFT 6
+#define MAX77620_SD_POWER_MODE_MASK 0x30
+#define MAX77620_SD_POWER_MODE_SHIFT 4
+#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
+#define MAX77620_SD_CFG1_ADE_DISABLE 0
+#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
+#define MAX77620_SD_FPWM_MASK 0x04
+#define MAX77620_SD_FPWM_SHIFT 2
+#define MAX77620_SD_FSRADE_MASK 0x01
+#define MAX77620_SD_FSRADE_SHIFT 0
+#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
+#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
+#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
+#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
+#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
+#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
+
+/* LDO_CNFG2 */
+#define MAX77620_LDO_POWER_MODE_MASK 0xC0
+#define MAX77620_LDO_POWER_MODE_SHIFT 6
+#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
+#define MAX77620_LDO_CFG2_ADE_DISABLE 0
+#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
+#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
+#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
+#define MAX77620_LDO_CFG2_SS_SLOW 0
+
+#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
+#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
+#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
+#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
+#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
+#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
+#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
+
+#define MAX77620_IRQ_LBM_MASK BIT(3)
+#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
+#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
+
+#define MAX77620_PWR_I2C_ADDR 0x3c
+#define MAX77620_RTC_I2C_ADDR 0x68
+
+#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
+#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
+#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
+#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
+#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
+#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
+#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
+#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
+#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
+#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
+#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
+
+#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
+
+#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
+
+#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
+#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
+#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
+#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
+#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
+#define MAX20024_ONOFFCNFG1_CLRSE 0x18
+
+#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
+#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
+#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
+#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
+#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
+
+#define MAX77620_GLBLM_MASK BIT(0)
+
+#define MAX77620_WDTC_MASK 0x3
+#define MAX77620_WDTOFFC BIT(4)
+#define MAX77620_WDTSLPC BIT(3)
+#define MAX77620_WDTEN BIT(2)
+
+#define MAX77620_TWD_MASK 0x3
+#define MAX77620_TWD_2s 0x0
+#define MAX77620_TWD_16s 0x1
+#define MAX77620_TWD_64s 0x2
+#define MAX77620_TWD_128s 0x3
+
+#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
+#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
+#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
+#define MAX77620_CNFGGLBL1_LBDAC 0x0E
+#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
+
+/* CNFG BBC registers */
+#define MAX77620_CNFGBBC_ENABLE BIT(0)
+#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
+#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
+#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
+#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
+#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
+#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
+#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
+
+/* I2c Slave Id */
+enum {
+ MAX77620_PWR_SLAVE,
+ MAX77620_RTC_SLAVE,
+ MAX77620_NUM_SLAVES,
+};
+
+/* GPIOs */
+enum {
+ MAX77620_GPIO0,
+ MAX77620_GPIO1,
+ MAX77620_GPIO2,
+ MAX77620_GPIO3,
+ MAX77620_GPIO4,
+ MAX77620_GPIO5,
+ MAX77620_GPIO6,
+ MAX77620_GPIO7,
+
+ MAX77620_GPIO_NR,
+};
+
+/* Interrupts */
+enum {
+ MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
+ MAX77620_IRQ_TOP_SD, /* SD power fail */
+ MAX77620_IRQ_TOP_LDO, /* LDO power fail */
+ MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
+ MAX77620_IRQ_TOP_RTC, /* RTC */
+ MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
+ MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
+
+ MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
+ MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
+
+ MAX77620_IRQ_GPIO0, /* GPIO0 edge detection */
+ MAX77620_IRQ_GPIO1, /* GPIO1 edge detection */
+ MAX77620_IRQ_GPIO2, /* GPIO2 edge detection */
+ MAX77620_IRQ_GPIO3, /* GPIO3 edge detection */
+ MAX77620_IRQ_GPIO4, /* GPIO4 edge detection */
+ MAX77620_IRQ_GPIO5, /* GPIO5 edge detection */
+ MAX77620_IRQ_GPIO6, /* GPIO6 edge detection */
+ MAX77620_IRQ_GPIO7, /* GPIO7 edge detection */
+
+ MAX77620_IRQ_ONOFF_MRWRN, /* Hard power off warnning */
+ MAX77620_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */
+ MAX77620_IRQ_ONOFF_EN0_F, /* EN0 falling */
+ MAX77620_IRQ_ONOFF_EN0_R, /* EN0 rising */
+ MAX77620_IRQ_ONOFF_LID_F, /* LID falling */
+ MAX77620_IRQ_ONOFF_LID_R, /* LID rising */
+ MAX77620_IRQ_ONOFF_ACOK_F, /* ACOK falling */
+ MAX77620_IRQ_ONOFF_ACOK_R, /* ACOK rising */
+
+ MAX77620_IRQ_NVER, /* Non-Volatile Event Recorder */
+ MAX77620_IRQ_NR,
+};
+
+enum max77620_regulators {
+ MAX77620_REGULATOR_ID_SD0,
+ MAX77620_REGULATOR_ID_SD1,
+ MAX77620_REGULATOR_ID_SD2,
+ MAX77620_REGULATOR_ID_SD3,
+ MAX77620_REGULATOR_ID_SD4,
+ MAX77620_REGULATOR_ID_LDO0,
+ MAX77620_REGULATOR_ID_LDO1,
+ MAX77620_REGULATOR_ID_LDO2,
+ MAX77620_REGULATOR_ID_LDO3,
+ MAX77620_REGULATOR_ID_LDO4,
+ MAX77620_REGULATOR_ID_LDO5,
+ MAX77620_REGULATOR_ID_LDO6,
+ MAX77620_REGULATOR_ID_LDO7,
+ MAX77620_REGULATOR_ID_LDO8,
+ MAX77620_NUM_REGS,
+};
+
+/* FPS Source */
+enum max77620_regulator_fps_src {
+ FPS_SRC_0,
+ FPS_SRC_1,
+ FPS_SRC_2,
+ FPS_SRC_NONE,
+ FPS_SRC_DEF,
+};
+
+/* Regulator types */
+enum max77620_regulator_type {
+ MAX77620_REGULATOR_TYPE_SD,
+ MAX77620_REGULATOR_TYPE_LDO_N,
+ MAX77620_REGULATOR_TYPE_LDO_P,
+};
+
+enum max77620_chip_id {
+ MAX77620,
+ MAX20024,
+};
+
+struct max77620_chip {
+ struct device *dev;
+
+ struct i2c_client *base_client;
+ struct regmap *rmap;
+
+ int chip_irq;
+ int irq_base;
+ int irq_mbattlow;
+
+ struct mutex mutex_config;
+ bool sleep_enable;
+ bool enable_global_lpm;
+ int active_fps_period[3];
+ int suspend_fps_period[3];
+
+ struct regmap_irq_chip_data *top_irq_data;
+ struct regmap_irq_chip_data *gpio_irq_data;
+
+ /* chip id */
+ u32 id;
+};
+
+extern int max77620_irq_get_virq(struct device *dev, int irq);
+extern int max77620_reg_write(struct device *dev, unsigned int reg, u8 val);
+extern int max77620_reg_read(struct device *dev, unsigned int reg, u8 *val);
+extern int max77620_reg_update(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val);
+#endif /* _LINUX_MFD_MAX77620_H_ */
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH V3 2/5] mfd: max77620: add core driver for MAX77620/MAX20024
2016-01-14 11:32 ` Laxman Dewangan
@ 2016-01-19 5:13 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 5:13 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Chaitanya Bandi, Mallikarjun Kasoju
On 14.01.2016 20:32, Laxman Dewangan wrote:
> MAX77620/MAX20024 are Power Management IC from the MAXIM.
> It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
> watchdog, clock etc.
>
> Add MFD drier to provides common support for accessing the
> device; additional drivers is developed on respected subsystem
> in order to use the functionality of the device.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
> ---
> Changes from V1:
> - Code cleanups per review from V1.
> - Move register acccess APIs from header to c file.
> - Remove some of non required variable, remove duplication in error message
> and simplify some of function implementation.
> - Register RTC driver such that it can get the regmap handle form parent device
> Changes from V2:
> - Run coccicheck and checkpatch in strict mode for the alignment.
> - Drop RTC driver and its i2c client registration.
>
> drivers/mfd/Kconfig | 15 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/max77620.c | 898 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/max77620.h | 402 +++++++++++++++++++
> 4 files changed, 1316 insertions(+)
> create mode 100644 drivers/mfd/max77620.c
> create mode 100644 include/linux/mfd/max77620.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 9581ebb..edeb85c 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -492,6 +492,21 @@ config MFD_MAX14577
> additional drivers must be enabled in order to use the functionality
> of the device.
>
> +config MFD_MAX77620
> + bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
> + depends on I2C=y
> + depends on OF
> + select MFD_CORE
> + select REGMAP_I2C
> + select REGMAP_IRQ
> + select IRQ_DOMAIN
> + help
> + Say yes here to add support for Maxim Semiconductor MAX77620 and
> + MAX20024 which are Power Management IC with General purpose pins,
> + RTC, regulators, clock generator, watchdog etc. This driver
> + provides common support for accessing the device; additional drivers
> + must be enabled in order to use the functionality of the device.
> +
> config MFD_MAX77686
> bool "Maxim Semiconductor MAX77686/802 PMIC Support"
> depends on I2C=y
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 0f230a6..97910ed 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -123,6 +123,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
> obj-$(CONFIG_MFD_DA9150) += da9150-core.o
>
> obj-$(CONFIG_MFD_MAX14577) += max14577.o
> +obj-$(CONFIG_MFD_MAX77620) += max77620.o
> obj-$(CONFIG_MFD_MAX77686) += max77686.o
> obj-$(CONFIG_MFD_MAX77693) += max77693.o
> obj-$(CONFIG_MFD_MAX77843) += max77843.o
> diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
> new file mode 100644
> index 0000000..e965261
> --- /dev/null
> +++ b/drivers/mfd/max77620.c
> @@ -0,0 +1,898 @@
> +/*
> + * Maxim MAX77620 MFD Driver
> + *
> + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
> + *
> + * Author:
> + * Laxman Dewangan <ldewangan@nvidia.com>
> + * Chaitanya Bandi <bandik@nvidia.com>
> + * Mallikarjun Kasoju <mkasoju@nvidia.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/i2c.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/core.h>
> +#include <linux/interrupt.h>
> +#include <linux/regmap.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/mfd/max77620.h>
> +
> +static struct resource gpio_resources[] = {
> + {
> + .start = MAX77620_IRQ_TOP_GPIO,
> + .end = MAX77620_IRQ_TOP_GPIO,
> + .flags = IORESOURCE_IRQ,
> + }
> +};
> +
> +static struct resource thermal_resources[] = {
> + {
> + .start = MAX77620_IRQ_LBT_TJALRM1,
> + .end = MAX77620_IRQ_LBT_TJALRM1,
> + .flags = IORESOURCE_IRQ,
> + },
> + {
> + .start = MAX77620_IRQ_LBT_TJALRM2,
> + .end = MAX77620_IRQ_LBT_TJALRM2,
> + .flags = IORESOURCE_IRQ,
> + }
> +};
> +
> +static const struct regmap_irq max77620_top_irqs[] = {
> + [MAX77620_IRQ_TOP_GLBL] = {
> + .mask = MAX77620_IRQ_TOP_GLBL_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_SD] = {
> + .mask = MAX77620_IRQ_TOP_SD_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_LDO] = {
> + .mask = MAX77620_IRQ_TOP_LDO_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_GPIO] = {
> + .mask = MAX77620_IRQ_TOP_GPIO_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_RTC] = {
> + .mask = MAX77620_IRQ_TOP_RTC_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_32K] = {
> + .mask = MAX77620_IRQ_TOP_32K_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_ONOFF] = {
> + .mask = MAX77620_IRQ_TOP_ONOFF_MASK,
> + .reg_offset = 0,
> + },
> +
> + [MAX77620_IRQ_LBT_MBATLOW] = {
> + .mask = MAX77620_IRQ_LBM_MASK,
> + .reg_offset = 1,
> + },
> + [MAX77620_IRQ_LBT_TJALRM1] = {
> + .mask = MAX77620_IRQ_TJALRM1_MASK,
> + .reg_offset = 1,
> + },
> + [MAX77620_IRQ_LBT_TJALRM2] = {
> + .mask = MAX77620_IRQ_TJALRM2_MASK,
> + .reg_offset = 1,
> + },
> +
> +};
> +
> +static const char * const max77620_nverc[] = {
> + "Shutdown-pin",
> + "System WatchDog Timer",
> + "Hard Reset",
> + "Junction Temp Overload",
> + "Main-Battery Low",
> + "Main-Battery overvoltage Lockout",
> + "Main-Battery undervoltage Lockout",
> + "Reset input",
> +};
This looks unused.
> +
> +enum max77660_ids {
> + MAX77620_PMIC_ID,
> + MAX77620_GPIO_ID,
> + MAX77620_PINCTRL_ID,
> + MAX77620_CLK_ID,
> + MAX77620_POWER_OFF_ID,
> + MAX77620_WDT_ID,
> + MAX77620_THERMAL_ID,
> + MAX77620_RTC_ID,
> +};
> +
> +#define MAX77620_SUB_MODULE_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max77620-"#_name, \
> + .num_resources = ARRAY_SIZE(_name##_resources), \
> + .resources = &_name##_resources[0], \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX20024_SUB_MODULE_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max20024-"#_name, \
> + .num_resources = ARRAY_SIZE(_name##_resources), \
> + .resources = &_name##_resources[0], \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX77620_SUB_MODULE_NO_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max77620-"#_name, \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX20024_SUB_MODULE_NO_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max20024-"#_name, \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +static struct mfd_cell max77620_children[] = {
> + MAX77620_SUB_MODULE_RES(gpio, GPIO),
> + MAX77620_SUB_MODULE_NO_RES(pmic, PMIC),
> + MAX77620_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
> + MAX77620_SUB_MODULE_NO_RES(clk, CLK),
> + MAX77620_SUB_MODULE_NO_RES(power-off, POWER_OFF),
> + MAX77620_SUB_MODULE_NO_RES(wdt, WDT),
> + MAX77620_SUB_MODULE_RES(thermal, THERMAL),
> +};
> +
> +static struct mfd_cell max20024_children[] = {
> + MAX20024_SUB_MODULE_RES(gpio, GPIO),
> + MAX20024_SUB_MODULE_NO_RES(pmic, PMIC),
> + MAX20024_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
> + MAX20024_SUB_MODULE_NO_RES(clk, CLK),
> + MAX20024_SUB_MODULE_NO_RES(power-off, POWER_OFF),
> + MAX20024_SUB_MODULE_NO_RES(wdt, WDT),
> + MAX20024_SUB_MODULE_RES(thermal, THERMAL),
> +};
> +
> +struct max77620_sub_modules {
> + struct mfd_cell *cells;
> + int ncells;
> + u32 id;
> +};
> +
> +static const struct max77620_sub_modules max77620_cells = {
> + .cells = max77620_children,
> + .ncells = ARRAY_SIZE(max77620_children),
> + .id = MAX77620,
> +};
> +
> +static const struct max77620_sub_modules max20024_cells = {
> + .cells = max20024_children,
> + .ncells = ARRAY_SIZE(max20024_children),
> + .id = MAX20024,
> +};
> +
> +static struct regmap_irq_chip max77620_top_irq_chip = {
> + .name = "max77620-top",
> + .irqs = max77620_top_irqs,
> + .num_irqs = ARRAY_SIZE(max77620_top_irqs),
> + .num_regs = 2,
> + .status_base = MAX77620_REG_IRQTOP,
> + .mask_base = MAX77620_REG_IRQTOPM,
> +};
> +
> +static const struct regmap_range max77620_readable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> +};
> +
> +static const struct regmap_access_table max77620_readable_table = {
> + .yes_ranges = max77620_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
> +};
> +
> +static const struct regmap_range max20024_readable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> + regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
> +};
> +
> +static const struct regmap_access_table max20024_readable_table = {
> + .yes_ranges = max20024_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
> +};
> +
> +static const struct regmap_range max77620_writable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> +};
> +
> +static const struct regmap_access_table max77620_writable_table = {
> + .yes_ranges = max77620_writable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
> +};
> +
> +static const struct regmap_range max77620_cacheable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
> + regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
> +};
> +
> +static const struct regmap_access_table max77620_volatile_table = {
> + .no_ranges = max77620_cacheable_ranges,
> + .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
> +};
> +
> +static const struct regmap_config max77620_regmap_config = {
> + .name = "power-slave",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = MAX77620_REG_DVSSD4 + 1,
> + .cache_type = REGCACHE_RBTREE,
> + .rd_table = &max77620_readable_table,
> + .wr_table = &max77620_writable_table,
> + .volatile_table = &max77620_volatile_table,
> +};
> +
> +static const struct regmap_config max20024_regmap_config = {
> + .name = "power-slave",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = MAX20024_REG_MAX_ADD + 1,
> + .cache_type = REGCACHE_RBTREE,
> + .rd_table = &max20024_readable_table,
> + .wr_table = &max77620_writable_table,
> + .volatile_table = &max77620_volatile_table,
> +};
> +
> +int max77620_irq_get_virq(struct device *dev, int irq)
> +{
> + struct max77620_chip *chip = dev_get_drvdata(dev);
> +
> + return regmap_irq_get_virq(chip->top_irq_data, irq);
> +}
> +EXPORT_SYMBOL_GPL(max77620_irq_get_virq);
> +
> +int max77620_reg_write(struct device *dev, unsigned int reg, u8 val)
Any special need why val is u8 (here and in max77620_reg_read())? The
regmap API and max77620_reg_update() use unsigned int.
Operate on unsigned ints, if it is possible. It makes everything more
consistent and easier to spot eventual wrong casts.
[...]
> diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
> new file mode 100644
> index 0000000..2bb4829
> --- /dev/null
> +++ b/include/linux/mfd/max77620.h
> @@ -0,0 +1,402 @@
> +/*
> + * max77620.h: Defining registers address and its bit definitions
> + * of MAX77620 and MAX20024
> + *
> + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#ifndef _LINUX_MFD_MAX77620_H_
> +#define _LINUX_MFD_MAX77620_H_
> +
> +/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
> +#define MAX77620_REG_CNFGGLBL1 0x00
> +#define MAX77620_REG_CNFGGLBL2 0x01
> +#define MAX77620_REG_CNFGGLBL3 0x02
> +#define MAX77620_REG_CNFG1_32K 0x03
> +#define MAX77620_REG_CNFGBBC 0x04
> +#define MAX77620_REG_IRQTOP 0x05
> +#define MAX77620_REG_INTLBT 0x06
> +#define MAX77620_REG_IRQSD 0x07
> +#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
> +#define MAX77620_REG_IRQ_LVL2_L8 0x09
> +#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
> +#define MAX77620_REG_ONOFFIRQ 0x0B
> +#define MAX77620_REG_NVERC 0x0C
> +#define MAX77620_REG_IRQTOPM 0x0D
> +#define MAX77620_REG_INTENLBT 0x0E
> +#define MAX77620_REG_IRQMASKSD 0x0F
> +#define MAX77620_REG_IRQ_MSK_L0_7 0x10
> +#define MAX77620_REG_IRQ_MSK_L8 0x11
> +#define MAX77620_REG_ONOFFIRQM 0x12
> +#define MAX77620_REG_STATLBT 0x13
> +#define MAX77620_REG_STATSD 0x14
> +#define MAX77620_REG_ONOFFSTAT 0x15
> +
> +/* SD and LDO Registers */
> +#define MAX77620_REG_SD0 0x16
> +#define MAX77620_REG_SD1 0x17
> +#define MAX77620_REG_SD2 0x18
> +#define MAX77620_REG_SD3 0x19
> +#define MAX77620_REG_SD4 0x1A
> +#define MAX77620_REG_DVSSD0 0x1B
> +#define MAX77620_REG_DVSSD1 0x1C
> +#define MAX77620_REG_SD0_CFG 0x1D
> +#define MAX77620_REG_SD1_CFG 0x1E
> +#define MAX77620_REG_SD2_CFG 0x1F
> +#define MAX77620_REG_SD3_CFG 0x20
> +#define MAX77620_REG_SD4_CFG 0x21
> +#define MAX77620_REG_SD_CFG2 0x22
> +#define MAX77620_REG_LDO0_CFG 0x23
> +#define MAX77620_REG_LDO0_CFG2 0x24
> +#define MAX77620_REG_LDO1_CFG 0x25
> +#define MAX77620_REG_LDO1_CFG2 0x26
> +#define MAX77620_REG_LDO2_CFG 0x27
> +#define MAX77620_REG_LDO2_CFG2 0x28
> +#define MAX77620_REG_LDO3_CFG 0x29
> +#define MAX77620_REG_LDO3_CFG2 0x2A
> +#define MAX77620_REG_LDO4_CFG 0x2B
> +#define MAX77620_REG_LDO4_CFG2 0x2C
> +#define MAX77620_REG_LDO5_CFG 0x2D
> +#define MAX77620_REG_LDO5_CFG2 0x2E
> +#define MAX77620_REG_LDO6_CFG 0x2F
> +#define MAX77620_REG_LDO6_CFG2 0x30
> +#define MAX77620_REG_LDO7_CFG 0x31
> +#define MAX77620_REG_LDO7_CFG2 0x32
> +#define MAX77620_REG_LDO8_CFG 0x33
> +#define MAX77620_REG_LDO8_CFG2 0x34
> +#define MAX77620_REG_LDO_CFG3 0x35
> +
> +#define MAX77620_LDO_SLEW_RATE_MASK 0x1
> +
> +/* LDO Configuration 3 */
> +#define MAX77620_TRACK4_MASK BIT(5)
> +#define MAX77620_TRACK4_SHIFT 5
> +
> +/* Voltage */
> +#define MAX77620_SDX_VOLT_MASK 0xFF
> +#define MAX77620_SD0_VOLT_MASK 0x3F
> +#define MAX77620_SD1_VOLT_MASK 0x7F
Duplicated space after #define
> +#define MAX77620_LDO_VOLT_MASK 0x3F
> +
> +#define MAX77620_REG_GPIO0 0x36
> +#define MAX77620_REG_GPIO1 0x37
> +#define MAX77620_REG_GPIO2 0x38
> +#define MAX77620_REG_GPIO3 0x39
> +#define MAX77620_REG_GPIO4 0x3A
> +#define MAX77620_REG_GPIO5 0x3B
> +#define MAX77620_REG_GPIO6 0x3C
> +#define MAX77620_REG_GPIO7 0x3D
> +#define MAX77620_REG_PUE_GPIO 0x3E
> +#define MAX77620_REG_PDE_GPIO 0x3F
> +#define MAX77620_REG_AME_GPIO 0x40
> +#define MAX77620_REG_ONOFFCNFG1 0x41
> +#define MAX77620_REG_ONOFFCNFG2 0x42
> +
> +/* FPS Registers */
> +#define MAX77620_REG_FPS_CFG0 0x43
> +#define MAX77620_REG_FPS_CFG1 0x44
> +#define MAX77620_REG_FPS_CFG2 0x45
> +#define MAX77620_REG_FPS_LDO0 0x46
> +#define MAX77620_REG_FPS_LDO1 0x47
> +#define MAX77620_REG_FPS_LDO2 0x48
> +#define MAX77620_REG_FPS_LDO3 0x49
> +#define MAX77620_REG_FPS_LDO4 0x4A
> +#define MAX77620_REG_FPS_LDO5 0x4B
> +#define MAX77620_REG_FPS_LDO6 0x4C
> +#define MAX77620_REG_FPS_LDO7 0x4D
> +#define MAX77620_REG_FPS_LDO8 0x4E
> +#define MAX77620_REG_FPS_SD0 0x4F
> +#define MAX77620_REG_FPS_SD1 0x50
> +#define MAX77620_REG_FPS_SD2 0x51
> +#define MAX77620_REG_FPS_SD3 0x52
> +#define MAX77620_REG_FPS_SD4 0x53
> +#define MAX77620_REG_FPS_NONE 0
> +
> +#define MAX77620_FPS_SRC_MASK 0xC0
> +#define MAX77620_FPS_SRC_SHIFT 6
> +#define MAX77620_FPS_PU_PERIOD_MASK 0x38
> +#define MAX77620_FPS_PU_PERIOD_SHIFT 3
> +#define MAX77620_FPS_PD_PERIOD_MASK 0x07
> +#define MAX77620_FPS_PD_PERIOD_SHIFT 0
> +#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
> +#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
> +#define MAX77620_FPS_EN_SRC_MASK 0x06
> +#define MAX77620_FPS_EN_SRC_SHIFT 1
> +#define MAX77620_FPS_ENFPS_MASK 0x01
> +
> +#define MAX77620_REG_FPS_GPIO1 0x54
> +#define MAX77620_REG_FPS_GPIO2 0x55
> +#define MAX77620_REG_FPS_GPIO3 0x56
> +#define MAX77620_REG_FPS_RSO 0x57
> +#define MAX77620_REG_CID0 0x58
> +#define MAX77620_REG_CID1 0x59
> +#define MAX77620_REG_CID2 0x5A
> +#define MAX77620_REG_CID3 0x5B
> +#define MAX77620_REG_CID4 0x5C
> +#define MAX77620_REG_CID5 0x5D
> +
> +#define MAX77620_REG_DVSSD4 0x5E
> +#define MAX20024_REG_MAX_ADD 0x70
> +
> +#define MAX77620_CID_DIDM_MASK 0xF0
> +#define MAX77620_CID_DIDM_SHIFT 4
> +
> +/* CNCG2SD */
> +#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
> +#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
> +
> +/* Device Identification Metal */
> +#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
> +/* Device Indentification OTP */
> +#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
> +
> +/* SD CNFG1 */
> +#define MAX77620_SD_SR_MASK 0xC0
> +#define MAX77620_SD_SR_SHIFT 6
> +#define MAX77620_SD_POWER_MODE_MASK 0x30
> +#define MAX77620_SD_POWER_MODE_SHIFT 4
> +#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
> +#define MAX77620_SD_CFG1_ADE_DISABLE 0
> +#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
> +#define MAX77620_SD_FPWM_MASK 0x04
> +#define MAX77620_SD_FPWM_SHIFT 2
> +#define MAX77620_SD_FSRADE_MASK 0x01
> +#define MAX77620_SD_FSRADE_SHIFT 0
> +#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
> +#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
> +#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
> +#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
> +#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
> +#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
> +
> +/* LDO_CNFG2 */
> +#define MAX77620_LDO_POWER_MODE_MASK 0xC0
> +#define MAX77620_LDO_POWER_MODE_SHIFT 6
> +#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
> +#define MAX77620_LDO_CFG2_ADE_DISABLE 0
> +#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
> +#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
> +#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
> +#define MAX77620_LDO_CFG2_SS_SLOW 0
> +
> +#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
> +#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
> +#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
> +#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
> +#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
> +#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
> +#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
> +
> +#define MAX77620_IRQ_LBM_MASK BIT(3)
> +#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
> +#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
> +
> +#define MAX77620_PWR_I2C_ADDR 0x3c
> +#define MAX77620_RTC_I2C_ADDR 0x68
> +
> +#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
> +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
> +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
> +#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
> +#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
> +#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
> +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
> +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
> +#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
> +#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
> +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
> +
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
> +
> +#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
> +
> +#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
> +#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
> +#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
> +#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
> +#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
> +#define MAX20024_ONOFFCNFG1_CLRSE 0x18
> +
> +#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
> +#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
> +#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
> +#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
> +#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
> +
> +#define MAX77620_GLBLM_MASK BIT(0)
Use one space after #define.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* [rtc-linux] Re: [PATCH V3 2/5] mfd: max77620: add core driver for MAX77620/MAX20024
@ 2016-01-19 5:13 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 5:13 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Chaitanya Bandi, Mallikarjun Kasoju
On 14.01.2016 20:32, Laxman Dewangan wrote:
> MAX77620/MAX20024 are Power Management IC from the MAXIM.
> It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
> watchdog, clock etc.
>
> Add MFD drier to provides common support for accessing the
> device; additional drivers is developed on respected subsystem
> in order to use the functionality of the device.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
> ---
> Changes from V1:
> - Code cleanups per review from V1.
> - Move register acccess APIs from header to c file.
> - Remove some of non required variable, remove duplication in error message
> and simplify some of function implementation.
> - Register RTC driver such that it can get the regmap handle form parent device
> Changes from V2:
> - Run coccicheck and checkpatch in strict mode for the alignment.
> - Drop RTC driver and its i2c client registration.
>
> drivers/mfd/Kconfig | 15 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/max77620.c | 898 +++++++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/max77620.h | 402 +++++++++++++++++++
> 4 files changed, 1316 insertions(+)
> create mode 100644 drivers/mfd/max77620.c
> create mode 100644 include/linux/mfd/max77620.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 9581ebb..edeb85c 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -492,6 +492,21 @@ config MFD_MAX14577
> additional drivers must be enabled in order to use the functionality
> of the device.
>
> +config MFD_MAX77620
> + bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
> + depends on I2C=y
> + depends on OF
> + select MFD_CORE
> + select REGMAP_I2C
> + select REGMAP_IRQ
> + select IRQ_DOMAIN
> + help
> + Say yes here to add support for Maxim Semiconductor MAX77620 and
> + MAX20024 which are Power Management IC with General purpose pins,
> + RTC, regulators, clock generator, watchdog etc. This driver
> + provides common support for accessing the device; additional drivers
> + must be enabled in order to use the functionality of the device.
> +
> config MFD_MAX77686
> bool "Maxim Semiconductor MAX77686/802 PMIC Support"
> depends on I2C=y
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 0f230a6..97910ed 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -123,6 +123,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
> obj-$(CONFIG_MFD_DA9150) += da9150-core.o
>
> obj-$(CONFIG_MFD_MAX14577) += max14577.o
> +obj-$(CONFIG_MFD_MAX77620) += max77620.o
> obj-$(CONFIG_MFD_MAX77686) += max77686.o
> obj-$(CONFIG_MFD_MAX77693) += max77693.o
> obj-$(CONFIG_MFD_MAX77843) += max77843.o
> diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
> new file mode 100644
> index 0000000..e965261
> --- /dev/null
> +++ b/drivers/mfd/max77620.c
> @@ -0,0 +1,898 @@
> +/*
> + * Maxim MAX77620 MFD Driver
> + *
> + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
> + *
> + * Author:
> + * Laxman Dewangan <ldewangan@nvidia.com>
> + * Chaitanya Bandi <bandik@nvidia.com>
> + * Mallikarjun Kasoju <mkasoju@nvidia.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/i2c.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/core.h>
> +#include <linux/interrupt.h>
> +#include <linux/regmap.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/mfd/max77620.h>
> +
> +static struct resource gpio_resources[] = {
> + {
> + .start = MAX77620_IRQ_TOP_GPIO,
> + .end = MAX77620_IRQ_TOP_GPIO,
> + .flags = IORESOURCE_IRQ,
> + }
> +};
> +
> +static struct resource thermal_resources[] = {
> + {
> + .start = MAX77620_IRQ_LBT_TJALRM1,
> + .end = MAX77620_IRQ_LBT_TJALRM1,
> + .flags = IORESOURCE_IRQ,
> + },
> + {
> + .start = MAX77620_IRQ_LBT_TJALRM2,
> + .end = MAX77620_IRQ_LBT_TJALRM2,
> + .flags = IORESOURCE_IRQ,
> + }
> +};
> +
> +static const struct regmap_irq max77620_top_irqs[] = {
> + [MAX77620_IRQ_TOP_GLBL] = {
> + .mask = MAX77620_IRQ_TOP_GLBL_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_SD] = {
> + .mask = MAX77620_IRQ_TOP_SD_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_LDO] = {
> + .mask = MAX77620_IRQ_TOP_LDO_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_GPIO] = {
> + .mask = MAX77620_IRQ_TOP_GPIO_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_RTC] = {
> + .mask = MAX77620_IRQ_TOP_RTC_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_32K] = {
> + .mask = MAX77620_IRQ_TOP_32K_MASK,
> + .reg_offset = 0,
> + },
> + [MAX77620_IRQ_TOP_ONOFF] = {
> + .mask = MAX77620_IRQ_TOP_ONOFF_MASK,
> + .reg_offset = 0,
> + },
> +
> + [MAX77620_IRQ_LBT_MBATLOW] = {
> + .mask = MAX77620_IRQ_LBM_MASK,
> + .reg_offset = 1,
> + },
> + [MAX77620_IRQ_LBT_TJALRM1] = {
> + .mask = MAX77620_IRQ_TJALRM1_MASK,
> + .reg_offset = 1,
> + },
> + [MAX77620_IRQ_LBT_TJALRM2] = {
> + .mask = MAX77620_IRQ_TJALRM2_MASK,
> + .reg_offset = 1,
> + },
> +
> +};
> +
> +static const char * const max77620_nverc[] = {
> + "Shutdown-pin",
> + "System WatchDog Timer",
> + "Hard Reset",
> + "Junction Temp Overload",
> + "Main-Battery Low",
> + "Main-Battery overvoltage Lockout",
> + "Main-Battery undervoltage Lockout",
> + "Reset input",
> +};
This looks unused.
> +
> +enum max77660_ids {
> + MAX77620_PMIC_ID,
> + MAX77620_GPIO_ID,
> + MAX77620_PINCTRL_ID,
> + MAX77620_CLK_ID,
> + MAX77620_POWER_OFF_ID,
> + MAX77620_WDT_ID,
> + MAX77620_THERMAL_ID,
> + MAX77620_RTC_ID,
> +};
> +
> +#define MAX77620_SUB_MODULE_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max77620-"#_name, \
> + .num_resources = ARRAY_SIZE(_name##_resources), \
> + .resources = &_name##_resources[0], \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX20024_SUB_MODULE_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max20024-"#_name, \
> + .num_resources = ARRAY_SIZE(_name##_resources), \
> + .resources = &_name##_resources[0], \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX77620_SUB_MODULE_NO_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max77620-"#_name, \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +#define MAX20024_SUB_MODULE_NO_RES(_name, _id) \
> + [MAX77620_##_id##_ID] = { \
> + .name = "max20024-"#_name, \
> + .id = MAX77620_##_id##_ID, \
> + }
> +
> +static struct mfd_cell max77620_children[] = {
> + MAX77620_SUB_MODULE_RES(gpio, GPIO),
> + MAX77620_SUB_MODULE_NO_RES(pmic, PMIC),
> + MAX77620_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
> + MAX77620_SUB_MODULE_NO_RES(clk, CLK),
> + MAX77620_SUB_MODULE_NO_RES(power-off, POWER_OFF),
> + MAX77620_SUB_MODULE_NO_RES(wdt, WDT),
> + MAX77620_SUB_MODULE_RES(thermal, THERMAL),
> +};
> +
> +static struct mfd_cell max20024_children[] = {
> + MAX20024_SUB_MODULE_RES(gpio, GPIO),
> + MAX20024_SUB_MODULE_NO_RES(pmic, PMIC),
> + MAX20024_SUB_MODULE_NO_RES(pinctrl, PINCTRL),
> + MAX20024_SUB_MODULE_NO_RES(clk, CLK),
> + MAX20024_SUB_MODULE_NO_RES(power-off, POWER_OFF),
> + MAX20024_SUB_MODULE_NO_RES(wdt, WDT),
> + MAX20024_SUB_MODULE_RES(thermal, THERMAL),
> +};
> +
> +struct max77620_sub_modules {
> + struct mfd_cell *cells;
> + int ncells;
> + u32 id;
> +};
> +
> +static const struct max77620_sub_modules max77620_cells = {
> + .cells = max77620_children,
> + .ncells = ARRAY_SIZE(max77620_children),
> + .id = MAX77620,
> +};
> +
> +static const struct max77620_sub_modules max20024_cells = {
> + .cells = max20024_children,
> + .ncells = ARRAY_SIZE(max20024_children),
> + .id = MAX20024,
> +};
> +
> +static struct regmap_irq_chip max77620_top_irq_chip = {
> + .name = "max77620-top",
> + .irqs = max77620_top_irqs,
> + .num_irqs = ARRAY_SIZE(max77620_top_irqs),
> + .num_regs = 2,
> + .status_base = MAX77620_REG_IRQTOP,
> + .mask_base = MAX77620_REG_IRQTOPM,
> +};
> +
> +static const struct regmap_range max77620_readable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> +};
> +
> +static const struct regmap_access_table max77620_readable_table = {
> + .yes_ranges = max77620_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
> +};
> +
> +static const struct regmap_range max20024_readable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> + regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
> +};
> +
> +static const struct regmap_access_table max20024_readable_table = {
> + .yes_ranges = max20024_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
> +};
> +
> +static const struct regmap_range max77620_writable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
> +};
> +
> +static const struct regmap_access_table max77620_writable_table = {
> + .yes_ranges = max77620_writable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
> +};
> +
> +static const struct regmap_range max77620_cacheable_ranges[] = {
> + regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
> + regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
> +};
> +
> +static const struct regmap_access_table max77620_volatile_table = {
> + .no_ranges = max77620_cacheable_ranges,
> + .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
> +};
> +
> +static const struct regmap_config max77620_regmap_config = {
> + .name = "power-slave",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = MAX77620_REG_DVSSD4 + 1,
> + .cache_type = REGCACHE_RBTREE,
> + .rd_table = &max77620_readable_table,
> + .wr_table = &max77620_writable_table,
> + .volatile_table = &max77620_volatile_table,
> +};
> +
> +static const struct regmap_config max20024_regmap_config = {
> + .name = "power-slave",
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = MAX20024_REG_MAX_ADD + 1,
> + .cache_type = REGCACHE_RBTREE,
> + .rd_table = &max20024_readable_table,
> + .wr_table = &max77620_writable_table,
> + .volatile_table = &max77620_volatile_table,
> +};
> +
> +int max77620_irq_get_virq(struct device *dev, int irq)
> +{
> + struct max77620_chip *chip = dev_get_drvdata(dev);
> +
> + return regmap_irq_get_virq(chip->top_irq_data, irq);
> +}
> +EXPORT_SYMBOL_GPL(max77620_irq_get_virq);
> +
> +int max77620_reg_write(struct device *dev, unsigned int reg, u8 val)
Any special need why val is u8 (here and in max77620_reg_read())? The
regmap API and max77620_reg_update() use unsigned int.
Operate on unsigned ints, if it is possible. It makes everything more
consistent and easier to spot eventual wrong casts.
[...]
> diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
> new file mode 100644
> index 0000000..2bb4829
> --- /dev/null
> +++ b/include/linux/mfd/max77620.h
> @@ -0,0 +1,402 @@
> +/*
> + * max77620.h: Defining registers address and its bit definitions
> + * of MAX77620 and MAX20024
> + *
> + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#ifndef _LINUX_MFD_MAX77620_H_
> +#define _LINUX_MFD_MAX77620_H_
> +
> +/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
> +#define MAX77620_REG_CNFGGLBL1 0x00
> +#define MAX77620_REG_CNFGGLBL2 0x01
> +#define MAX77620_REG_CNFGGLBL3 0x02
> +#define MAX77620_REG_CNFG1_32K 0x03
> +#define MAX77620_REG_CNFGBBC 0x04
> +#define MAX77620_REG_IRQTOP 0x05
> +#define MAX77620_REG_INTLBT 0x06
> +#define MAX77620_REG_IRQSD 0x07
> +#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
> +#define MAX77620_REG_IRQ_LVL2_L8 0x09
> +#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
> +#define MAX77620_REG_ONOFFIRQ 0x0B
> +#define MAX77620_REG_NVERC 0x0C
> +#define MAX77620_REG_IRQTOPM 0x0D
> +#define MAX77620_REG_INTENLBT 0x0E
> +#define MAX77620_REG_IRQMASKSD 0x0F
> +#define MAX77620_REG_IRQ_MSK_L0_7 0x10
> +#define MAX77620_REG_IRQ_MSK_L8 0x11
> +#define MAX77620_REG_ONOFFIRQM 0x12
> +#define MAX77620_REG_STATLBT 0x13
> +#define MAX77620_REG_STATSD 0x14
> +#define MAX77620_REG_ONOFFSTAT 0x15
> +
> +/* SD and LDO Registers */
> +#define MAX77620_REG_SD0 0x16
> +#define MAX77620_REG_SD1 0x17
> +#define MAX77620_REG_SD2 0x18
> +#define MAX77620_REG_SD3 0x19
> +#define MAX77620_REG_SD4 0x1A
> +#define MAX77620_REG_DVSSD0 0x1B
> +#define MAX77620_REG_DVSSD1 0x1C
> +#define MAX77620_REG_SD0_CFG 0x1D
> +#define MAX77620_REG_SD1_CFG 0x1E
> +#define MAX77620_REG_SD2_CFG 0x1F
> +#define MAX77620_REG_SD3_CFG 0x20
> +#define MAX77620_REG_SD4_CFG 0x21
> +#define MAX77620_REG_SD_CFG2 0x22
> +#define MAX77620_REG_LDO0_CFG 0x23
> +#define MAX77620_REG_LDO0_CFG2 0x24
> +#define MAX77620_REG_LDO1_CFG 0x25
> +#define MAX77620_REG_LDO1_CFG2 0x26
> +#define MAX77620_REG_LDO2_CFG 0x27
> +#define MAX77620_REG_LDO2_CFG2 0x28
> +#define MAX77620_REG_LDO3_CFG 0x29
> +#define MAX77620_REG_LDO3_CFG2 0x2A
> +#define MAX77620_REG_LDO4_CFG 0x2B
> +#define MAX77620_REG_LDO4_CFG2 0x2C
> +#define MAX77620_REG_LDO5_CFG 0x2D
> +#define MAX77620_REG_LDO5_CFG2 0x2E
> +#define MAX77620_REG_LDO6_CFG 0x2F
> +#define MAX77620_REG_LDO6_CFG2 0x30
> +#define MAX77620_REG_LDO7_CFG 0x31
> +#define MAX77620_REG_LDO7_CFG2 0x32
> +#define MAX77620_REG_LDO8_CFG 0x33
> +#define MAX77620_REG_LDO8_CFG2 0x34
> +#define MAX77620_REG_LDO_CFG3 0x35
> +
> +#define MAX77620_LDO_SLEW_RATE_MASK 0x1
> +
> +/* LDO Configuration 3 */
> +#define MAX77620_TRACK4_MASK BIT(5)
> +#define MAX77620_TRACK4_SHIFT 5
> +
> +/* Voltage */
> +#define MAX77620_SDX_VOLT_MASK 0xFF
> +#define MAX77620_SD0_VOLT_MASK 0x3F
> +#define MAX77620_SD1_VOLT_MASK 0x7F
Duplicated space after #define
> +#define MAX77620_LDO_VOLT_MASK 0x3F
> +
> +#define MAX77620_REG_GPIO0 0x36
> +#define MAX77620_REG_GPIO1 0x37
> +#define MAX77620_REG_GPIO2 0x38
> +#define MAX77620_REG_GPIO3 0x39
> +#define MAX77620_REG_GPIO4 0x3A
> +#define MAX77620_REG_GPIO5 0x3B
> +#define MAX77620_REG_GPIO6 0x3C
> +#define MAX77620_REG_GPIO7 0x3D
> +#define MAX77620_REG_PUE_GPIO 0x3E
> +#define MAX77620_REG_PDE_GPIO 0x3F
> +#define MAX77620_REG_AME_GPIO 0x40
> +#define MAX77620_REG_ONOFFCNFG1 0x41
> +#define MAX77620_REG_ONOFFCNFG2 0x42
> +
> +/* FPS Registers */
> +#define MAX77620_REG_FPS_CFG0 0x43
> +#define MAX77620_REG_FPS_CFG1 0x44
> +#define MAX77620_REG_FPS_CFG2 0x45
> +#define MAX77620_REG_FPS_LDO0 0x46
> +#define MAX77620_REG_FPS_LDO1 0x47
> +#define MAX77620_REG_FPS_LDO2 0x48
> +#define MAX77620_REG_FPS_LDO3 0x49
> +#define MAX77620_REG_FPS_LDO4 0x4A
> +#define MAX77620_REG_FPS_LDO5 0x4B
> +#define MAX77620_REG_FPS_LDO6 0x4C
> +#define MAX77620_REG_FPS_LDO7 0x4D
> +#define MAX77620_REG_FPS_LDO8 0x4E
> +#define MAX77620_REG_FPS_SD0 0x4F
> +#define MAX77620_REG_FPS_SD1 0x50
> +#define MAX77620_REG_FPS_SD2 0x51
> +#define MAX77620_REG_FPS_SD3 0x52
> +#define MAX77620_REG_FPS_SD4 0x53
> +#define MAX77620_REG_FPS_NONE 0
> +
> +#define MAX77620_FPS_SRC_MASK 0xC0
> +#define MAX77620_FPS_SRC_SHIFT 6
> +#define MAX77620_FPS_PU_PERIOD_MASK 0x38
> +#define MAX77620_FPS_PU_PERIOD_SHIFT 3
> +#define MAX77620_FPS_PD_PERIOD_MASK 0x07
> +#define MAX77620_FPS_PD_PERIOD_SHIFT 0
> +#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
> +#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
> +#define MAX77620_FPS_EN_SRC_MASK 0x06
> +#define MAX77620_FPS_EN_SRC_SHIFT 1
> +#define MAX77620_FPS_ENFPS_MASK 0x01
> +
> +#define MAX77620_REG_FPS_GPIO1 0x54
> +#define MAX77620_REG_FPS_GPIO2 0x55
> +#define MAX77620_REG_FPS_GPIO3 0x56
> +#define MAX77620_REG_FPS_RSO 0x57
> +#define MAX77620_REG_CID0 0x58
> +#define MAX77620_REG_CID1 0x59
> +#define MAX77620_REG_CID2 0x5A
> +#define MAX77620_REG_CID3 0x5B
> +#define MAX77620_REG_CID4 0x5C
> +#define MAX77620_REG_CID5 0x5D
> +
> +#define MAX77620_REG_DVSSD4 0x5E
> +#define MAX20024_REG_MAX_ADD 0x70
> +
> +#define MAX77620_CID_DIDM_MASK 0xF0
> +#define MAX77620_CID_DIDM_SHIFT 4
> +
> +/* CNCG2SD */
> +#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
> +#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
> +
> +/* Device Identification Metal */
> +#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
> +/* Device Indentification OTP */
> +#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
> +
> +/* SD CNFG1 */
> +#define MAX77620_SD_SR_MASK 0xC0
> +#define MAX77620_SD_SR_SHIFT 6
> +#define MAX77620_SD_POWER_MODE_MASK 0x30
> +#define MAX77620_SD_POWER_MODE_SHIFT 4
> +#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
> +#define MAX77620_SD_CFG1_ADE_DISABLE 0
> +#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
> +#define MAX77620_SD_FPWM_MASK 0x04
> +#define MAX77620_SD_FPWM_SHIFT 2
> +#define MAX77620_SD_FSRADE_MASK 0x01
> +#define MAX77620_SD_FSRADE_SHIFT 0
> +#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
> +#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
> +#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
> +#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
> +#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
> +#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
> +
> +/* LDO_CNFG2 */
> +#define MAX77620_LDO_POWER_MODE_MASK 0xC0
> +#define MAX77620_LDO_POWER_MODE_SHIFT 6
> +#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
> +#define MAX77620_LDO_CFG2_ADE_DISABLE 0
> +#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
> +#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
> +#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
> +#define MAX77620_LDO_CFG2_SS_SLOW 0
> +
> +#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
> +#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
> +#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
> +#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
> +#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
> +#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
> +#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
> +
> +#define MAX77620_IRQ_LBM_MASK BIT(3)
> +#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
> +#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
> +
> +#define MAX77620_PWR_I2C_ADDR 0x3c
> +#define MAX77620_RTC_I2C_ADDR 0x68
> +
> +#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
> +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
> +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
> +#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
> +#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
> +#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
> +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
> +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
> +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
> +#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
> +#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
> +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
> +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
> +
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
> +#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
> +
> +#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
> +
> +#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
> +#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
> +#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
> +#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
> +#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
> +#define MAX20024_ONOFFCNFG1_CLRSE 0x18
> +
> +#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
> +#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
> +#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
> +#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
> +#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
> +
> +#define MAX77620_GLBLM_MASK BIT(0)
Use one space after #define.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH V3 3/5] pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-14 11:32 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.
Add pincontrol driver to configure these parameters through
pincontrol APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-max77620.c | 703 +++++++++++++++++++++++++++++++++++++
3 files changed, 714 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-max77620.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 99a4c10..b6d2d23 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -227,6 +227,16 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MAX77620
+ bool "MAX77620/MAX20024 Pincontrol support"
+ depends on MFD_MAX77620
+ select GENERIC_PINCONF
+ help
+ Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
+ This PMIC has 8 GPIO pins that work as GPIO as well as special
+ function in alternate mode. This driver also configure push-pull,
+ open drain, FPS slots etc.
+
config PINCTRL_PALMAS
bool "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index bf1b5ca..72833e3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
new file mode 100644
index 0000000..440d700
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -0,0 +1,703 @@
+/*
+ * MAX77620 pin control driver.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max77620.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define MAX77620_PIN_NUM 8
+
+enum max77620_pin_ppdrv {
+ MAX77620_PIN_UNCONFIG_DRV,
+ MAX77620_PIN_OD_DRV,
+ MAX77620_PIN_PP_DRV,
+};
+
+enum max77620_pinconf_param {
+ MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+struct max77620_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned ngroups;
+ int mux_option;
+};
+
+struct max77620_cfg_param {
+ const char *property;
+ enum max77620_pinconf_param param;
+};
+
+static const struct pinconf_generic_params max77620_cfg_params[] = {
+ {
+ .property = "maxim,active-fps-source",
+ .param = MAX77620_ACTIVE_FPS_SOURCE,
+ }, {
+ .property = "maxim,active-fps-power-up-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,active-fps-power-down-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-source",
+ .param = MAX77620_SUSPEND_FPS_SOURCE,
+ }, {
+ .property = "maxim,suspend-fps-power-up-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-power-down-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+ },
+};
+
+enum max77620_alternate_pinmux_option {
+ MAX77620_PINMUX_GPIO = 0,
+ MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
+ MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
+ MAX77620_PINMUX_32K_OUT1 = 3,
+ MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
+ MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
+ MAX77620_PINMUX_REFERENCE_OUT = 6,
+};
+
+struct max77620_pingroup {
+ const char *name;
+ const unsigned pins[1];
+ unsigned npins;
+ enum max77620_alternate_pinmux_option alt_option;
+};
+
+struct max77620_pin_info {
+ enum max77620_pin_ppdrv drv_type;
+ int pull_config;
+};
+
+struct max77620_fps_config {
+ int active_fps_src;
+ int active_power_up_slots;
+ int active_power_down_slots;
+ int suspend_fps_src;
+ int suspend_power_up_slots;
+ int suspend_power_down_slots;
+};
+
+struct max77620_pctrl_info {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct max77620_chip *max77620;
+ int pins_current_opt[MAX77620_GPIO_NR];
+ const struct max77620_pin_function *functions;
+ unsigned num_functions;
+ const struct max77620_pingroup *pin_groups;
+ int num_pin_groups;
+ const struct pinctrl_pin_desc *pins;
+ unsigned num_pins;
+ struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
+ struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
+};
+
+static const struct pinctrl_pin_desc max77620_pins_desc[] = {
+ PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
+ PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
+ PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
+ PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
+ PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
+ PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
+ PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
+ PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+#define FUNCTION_GROUP(fname, mux) \
+ { \
+ .name = fname, \
+ .groups = gpio_groups, \
+ .ngroups = ARRAY_SIZE(gpio_groups), \
+ .mux_option = MAX77620_PINMUX_##mux, \
+ }
+
+static const struct max77620_pin_function max77620_pin_function[] = {
+ FUNCTION_GROUP("gpio", GPIO),
+ FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
+ FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
+ FUNCTION_GROUP("32k-out1", 32K_OUT1),
+ FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("reference-out", REFERENCE_OUT),
+};
+
+#define MAX77620_PINGROUP(pg_name, pin_id, option) \
+ { \
+ .name = #pg_name, \
+ .pins = {MAX77620_##pin_id}, \
+ .npins = 1, \
+ .alt_option = MAX77620_PINMUX_##option, \
+ }
+
+static const struct max77620_pingroup max77620_pingroups[] = {
+ MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
+ MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
+ MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
+};
+
+static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_pin_groups;
+}
+
+static const char *max77620_pinctrl_get_group_name(
+ struct pinctrl_dev *pctldev, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->pin_groups[group].name;
+}
+
+static int max77620_pinctrl_get_group_pins(
+ struct pinctrl_dev *pctldev, unsigned group,
+ const unsigned **pins, unsigned *num_pins)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = mpci->pin_groups[group].pins;
+ *num_pins = mpci->pin_groups[group].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops max77620_pinctrl_ops = {
+ .get_groups_count = max77620_pinctrl_get_groups_count,
+ .get_group_name = max77620_pinctrl_get_group_name,
+ .get_group_pins = max77620_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_functions;
+}
+
+static const char *max77620_pinctrl_get_func_name(
+ struct pinctrl_dev *pctldev, unsigned function)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->functions[function].name;
+}
+
+static int max77620_pinctrl_get_func_groups(
+ struct pinctrl_dev *pctldev, unsigned function,
+ const char * const **groups, unsigned * const num_groups)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = mpci->functions[function].groups;
+ *num_groups = mpci->functions[function].ngroups;
+
+ return 0;
+}
+
+static int max77620_pinctrl_enable(
+ struct pinctrl_dev *pctldev, unsigned function, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ u8 val;
+ int ret;
+
+ if (function == MAX77620_PINMUX_GPIO) {
+ val = 0;
+ } else if (function == mpci->pin_groups[group].alt_option) {
+ val = 1 << group;
+ } else {
+ dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
+ group, function);
+ return -EINVAL;
+ }
+ ret = max77620_reg_update(mpci->max77620->dev, MAX77620_REG_AME_GPIO,
+ 1 << group, val);
+ if (ret < 0)
+ dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
+
+ return ret;
+}
+
+static const struct pinmux_ops max77620_pinmux_ops = {
+ .get_functions_count = max77620_pinctrl_get_funcs_count,
+ .get_function_name = max77620_pinctrl_get_func_name,
+ .get_function_groups = max77620_pinctrl_get_func_groups,
+ .set_mux = max77620_pinctrl_enable,
+};
+
+static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u8 val;
+ int arg = 0;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, (u16)arg);
+
+ return 0;
+}
+
+static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
+ int addr, int *fps)
+{
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mpci->max77620->dev, addr, &val);
+ if (ret < 0) {
+ dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+
+ return 0;
+}
+
+static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
+ int pin, int param)
+{
+ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
+ int addr, ret;
+ int param_val;
+ int mask, shift;
+
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return 0;
+
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ switch (param) {
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ mask = MAX77620_FPS_SRC_MASK;
+ shift = MAX77620_FPS_SRC_SHIFT;
+ param_val = fps_config->active_fps_src;
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ param_val = fps_config->suspend_fps_src;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ mask = MAX77620_FPS_PU_PERIOD_MASK;
+ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
+ param_val = fps_config->active_power_up_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ param_val = fps_config->suspend_power_up_slots;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ mask = MAX77620_FPS_PD_PERIOD_MASK;
+ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
+ param_val = fps_config->active_power_down_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
+ param_val = fps_config->suspend_power_down_slots;
+ break;
+
+ default:
+ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
+ param, pin);
+ return -EINVAL;
+ }
+
+ if (param_val < 0)
+ return 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev, addr, mask,
+ param_val << shift);
+ if (ret < 0)
+ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
+
+ return ret;
+}
+
+static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ struct device *parent = mpci->max77620->dev;
+ struct max77620_fps_config *fps_config;
+ int param;
+ u16 param_val;
+ unsigned int val;
+ unsigned int pu_val;
+ unsigned int pd_val;
+ int addr, ret;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ param_val = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ val = param_val ? 0 : 1;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ val = param_val ? 1 : 0;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->active_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_ACTIVE_FPS_SOURCE)
+ fps_config->active_fps_src = param_val;
+ else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
+ fps_config->active_power_up_slots = param_val;
+ else
+ fps_config->active_power_down_slots = param_val;
+
+ ret = max77620_set_fps_param(mpci, pin, param);
+ if (ret < 0)
+ return ret;
+ break;
+
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->suspend_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ fps_config->suspend_fps_src = param_val;
+ else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ fps_config->suspend_power_up_slots = param_val;
+ else
+ fps_config->suspend_power_down_slots =
+ param_val;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
+ BIT(pin) : 0;
+ pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
+ BIT(pin) : 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO,
+ BIT(pin), pu_val);
+ if (ret < 0) {
+ dev_err(dev, "PUE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO,
+ BIT(pin), pd_val);
+ if (ret < 0) {
+ dev_err(dev, "PDE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops max77620_pinconf_ops = {
+ .pin_config_get = max77620_pinconf_get,
+ .pin_config_set = max77620_pinconf_set,
+};
+
+static struct pinctrl_desc max77620_pinctrl_desc = {
+ .pctlops = &max77620_pinctrl_ops,
+ .pmxops = &max77620_pinmux_ops,
+ .confops = &max77620_pinconf_ops,
+};
+
+static int max77620_pinctrl_probe(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci;
+ struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
+ int i;
+
+ mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
+ if (!mpci)
+ return -ENOMEM;
+
+ mpci->dev = &pdev->dev;
+ mpci->dev->of_node = pdev->dev.parent->of_node;
+ mpci->max77620 = max77620;
+
+ mpci->pins = max77620_pins_desc;
+ mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
+ mpci->functions = max77620_pin_function;
+ mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
+ mpci->pin_groups = max77620_pingroups;
+ mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
+ platform_set_drvdata(pdev, mpci);
+
+ max77620_pinctrl_desc.name = dev_name(&pdev->dev);
+ max77620_pinctrl_desc.pins = max77620_pins_desc;
+ max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
+ max77620_pinctrl_desc.num_custom_params =
+ ARRAY_SIZE(max77620_cfg_params);
+ max77620_pinctrl_desc.custom_params = max77620_cfg_params;
+
+ for (i = 0; i < MAX77620_PIN_NUM; ++i) {
+ mpci->fps_config[i].active_fps_src = -1;
+ mpci->fps_config[i].active_power_up_slots = -1;
+ mpci->fps_config[i].active_power_down_slots = -1;
+ mpci->fps_config[i].suspend_fps_src = -1;
+ mpci->fps_config[i].suspend_power_up_slots = -1;
+ mpci->fps_config[i].suspend_power_down_slots = -1;
+ }
+
+ mpci->pctl = pinctrl_register(&max77620_pinctrl_desc,
+ &pdev->dev, mpci);
+ if (IS_ERR(mpci->pctl)) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return PTR_ERR(mpci->pctl);
+ }
+
+ return 0;
+}
+
+static int max77620_pinctrl_remove(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(mpci->pctl);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_suspend_fps_param[] = {
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_active_fps_param[] = {
+ MAX77620_ACTIVE_FPS_SOURCE,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_pinctrl_suspend(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_suspend_fps_param[p]);
+ }
+
+ return 0;
+};
+
+static int max77620_pinctrl_resume(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_active_fps_param[p]);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(
+ max77620_pinctrl_suspend, max77620_pinctrl_resume)
+};
+
+static const struct platform_device_id max77620_pinctrl_devtype[] = {
+ { .name = "max77620-pinctrl", },
+ { .name = "max20024-pinctrl", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
+
+static struct platform_driver max77620_pinctrl_driver = {
+ .driver = {
+ .name = "max77620-pinctrl",
+ .pm = &max77620_pinctrl_pm_ops,
+ },
+ .probe = max77620_pinctrl_probe,
+ .remove = max77620_pinctrl_remove,
+ .id_table = max77620_pinctrl_devtype,
+};
+
+static int __init max77620_pinctrl_init(void)
+{
+ return platform_driver_register(&max77620_pinctrl_driver);
+}
+subsys_initcall(max77620_pinctrl_init);
+
+static void __exit max77620_pinctrl_exit(void)
+{
+ platform_driver_unregister(&max77620_pinctrl_driver);
+}
+module_exit(max77620_pinctrl_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
+MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pinctrl");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [rtc-linux] [PATCH V3 3/5] pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.
Add pincontrol driver to configure these parameters through
pincontrol APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-max77620.c | 703 +++++++++++++++++++++++++++++++++++++
3 files changed, 714 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-max77620.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 99a4c10..b6d2d23 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -227,6 +227,16 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MAX77620
+ bool "MAX77620/MAX20024 Pincontrol support"
+ depends on MFD_MAX77620
+ select GENERIC_PINCONF
+ help
+ Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
+ This PMIC has 8 GPIO pins that work as GPIO as well as special
+ function in alternate mode. This driver also configure push-pull,
+ open drain, FPS slots etc.
+
config PINCTRL_PALMAS
bool "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index bf1b5ca..72833e3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
new file mode 100644
index 0000000..440d700
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -0,0 +1,703 @@
+/*
+ * MAX77620 pin control driver.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max77620.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define MAX77620_PIN_NUM 8
+
+enum max77620_pin_ppdrv {
+ MAX77620_PIN_UNCONFIG_DRV,
+ MAX77620_PIN_OD_DRV,
+ MAX77620_PIN_PP_DRV,
+};
+
+enum max77620_pinconf_param {
+ MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+struct max77620_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned ngroups;
+ int mux_option;
+};
+
+struct max77620_cfg_param {
+ const char *property;
+ enum max77620_pinconf_param param;
+};
+
+static const struct pinconf_generic_params max77620_cfg_params[] = {
+ {
+ .property = "maxim,active-fps-source",
+ .param = MAX77620_ACTIVE_FPS_SOURCE,
+ }, {
+ .property = "maxim,active-fps-power-up-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,active-fps-power-down-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-source",
+ .param = MAX77620_SUSPEND_FPS_SOURCE,
+ }, {
+ .property = "maxim,suspend-fps-power-up-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-power-down-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+ },
+};
+
+enum max77620_alternate_pinmux_option {
+ MAX77620_PINMUX_GPIO = 0,
+ MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
+ MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
+ MAX77620_PINMUX_32K_OUT1 = 3,
+ MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
+ MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
+ MAX77620_PINMUX_REFERENCE_OUT = 6,
+};
+
+struct max77620_pingroup {
+ const char *name;
+ const unsigned pins[1];
+ unsigned npins;
+ enum max77620_alternate_pinmux_option alt_option;
+};
+
+struct max77620_pin_info {
+ enum max77620_pin_ppdrv drv_type;
+ int pull_config;
+};
+
+struct max77620_fps_config {
+ int active_fps_src;
+ int active_power_up_slots;
+ int active_power_down_slots;
+ int suspend_fps_src;
+ int suspend_power_up_slots;
+ int suspend_power_down_slots;
+};
+
+struct max77620_pctrl_info {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct max77620_chip *max77620;
+ int pins_current_opt[MAX77620_GPIO_NR];
+ const struct max77620_pin_function *functions;
+ unsigned num_functions;
+ const struct max77620_pingroup *pin_groups;
+ int num_pin_groups;
+ const struct pinctrl_pin_desc *pins;
+ unsigned num_pins;
+ struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
+ struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
+};
+
+static const struct pinctrl_pin_desc max77620_pins_desc[] = {
+ PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
+ PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
+ PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
+ PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
+ PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
+ PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
+ PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
+ PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+#define FUNCTION_GROUP(fname, mux) \
+ { \
+ .name = fname, \
+ .groups = gpio_groups, \
+ .ngroups = ARRAY_SIZE(gpio_groups), \
+ .mux_option = MAX77620_PINMUX_##mux, \
+ }
+
+static const struct max77620_pin_function max77620_pin_function[] = {
+ FUNCTION_GROUP("gpio", GPIO),
+ FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
+ FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
+ FUNCTION_GROUP("32k-out1", 32K_OUT1),
+ FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("reference-out", REFERENCE_OUT),
+};
+
+#define MAX77620_PINGROUP(pg_name, pin_id, option) \
+ { \
+ .name = #pg_name, \
+ .pins = {MAX77620_##pin_id}, \
+ .npins = 1, \
+ .alt_option = MAX77620_PINMUX_##option, \
+ }
+
+static const struct max77620_pingroup max77620_pingroups[] = {
+ MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
+ MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
+ MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
+};
+
+static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_pin_groups;
+}
+
+static const char *max77620_pinctrl_get_group_name(
+ struct pinctrl_dev *pctldev, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->pin_groups[group].name;
+}
+
+static int max77620_pinctrl_get_group_pins(
+ struct pinctrl_dev *pctldev, unsigned group,
+ const unsigned **pins, unsigned *num_pins)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = mpci->pin_groups[group].pins;
+ *num_pins = mpci->pin_groups[group].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops max77620_pinctrl_ops = {
+ .get_groups_count = max77620_pinctrl_get_groups_count,
+ .get_group_name = max77620_pinctrl_get_group_name,
+ .get_group_pins = max77620_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_functions;
+}
+
+static const char *max77620_pinctrl_get_func_name(
+ struct pinctrl_dev *pctldev, unsigned function)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->functions[function].name;
+}
+
+static int max77620_pinctrl_get_func_groups(
+ struct pinctrl_dev *pctldev, unsigned function,
+ const char * const **groups, unsigned * const num_groups)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = mpci->functions[function].groups;
+ *num_groups = mpci->functions[function].ngroups;
+
+ return 0;
+}
+
+static int max77620_pinctrl_enable(
+ struct pinctrl_dev *pctldev, unsigned function, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ u8 val;
+ int ret;
+
+ if (function == MAX77620_PINMUX_GPIO) {
+ val = 0;
+ } else if (function == mpci->pin_groups[group].alt_option) {
+ val = 1 << group;
+ } else {
+ dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
+ group, function);
+ return -EINVAL;
+ }
+ ret = max77620_reg_update(mpci->max77620->dev, MAX77620_REG_AME_GPIO,
+ 1 << group, val);
+ if (ret < 0)
+ dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
+
+ return ret;
+}
+
+static const struct pinmux_ops max77620_pinmux_ops = {
+ .get_functions_count = max77620_pinctrl_get_funcs_count,
+ .get_function_name = max77620_pinctrl_get_func_name,
+ .get_function_groups = max77620_pinctrl_get_func_groups,
+ .set_mux = max77620_pinctrl_enable,
+};
+
+static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u8 val;
+ int arg = 0;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, (u16)arg);
+
+ return 0;
+}
+
+static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
+ int addr, int *fps)
+{
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mpci->max77620->dev, addr, &val);
+ if (ret < 0) {
+ dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+
+ return 0;
+}
+
+static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
+ int pin, int param)
+{
+ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
+ int addr, ret;
+ int param_val;
+ int mask, shift;
+
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return 0;
+
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ switch (param) {
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ mask = MAX77620_FPS_SRC_MASK;
+ shift = MAX77620_FPS_SRC_SHIFT;
+ param_val = fps_config->active_fps_src;
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ param_val = fps_config->suspend_fps_src;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ mask = MAX77620_FPS_PU_PERIOD_MASK;
+ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
+ param_val = fps_config->active_power_up_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ param_val = fps_config->suspend_power_up_slots;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ mask = MAX77620_FPS_PD_PERIOD_MASK;
+ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
+ param_val = fps_config->active_power_down_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
+ param_val = fps_config->suspend_power_down_slots;
+ break;
+
+ default:
+ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
+ param, pin);
+ return -EINVAL;
+ }
+
+ if (param_val < 0)
+ return 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev, addr, mask,
+ param_val << shift);
+ if (ret < 0)
+ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
+
+ return ret;
+}
+
+static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ struct device *parent = mpci->max77620->dev;
+ struct max77620_fps_config *fps_config;
+ int param;
+ u16 param_val;
+ unsigned int val;
+ unsigned int pu_val;
+ unsigned int pd_val;
+ int addr, ret;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ param_val = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ val = param_val ? 0 : 1;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ val = param_val ? 1 : 0;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->active_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_ACTIVE_FPS_SOURCE)
+ fps_config->active_fps_src = param_val;
+ else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
+ fps_config->active_power_up_slots = param_val;
+ else
+ fps_config->active_power_down_slots = param_val;
+
+ ret = max77620_set_fps_param(mpci, pin, param);
+ if (ret < 0)
+ return ret;
+ break;
+
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->suspend_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ fps_config->suspend_fps_src = param_val;
+ else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ fps_config->suspend_power_up_slots = param_val;
+ else
+ fps_config->suspend_power_down_slots =
+ param_val;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
+ BIT(pin) : 0;
+ pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
+ BIT(pin) : 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO,
+ BIT(pin), pu_val);
+ if (ret < 0) {
+ dev_err(dev, "PUE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO,
+ BIT(pin), pd_val);
+ if (ret < 0) {
+ dev_err(dev, "PDE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops max77620_pinconf_ops = {
+ .pin_config_get = max77620_pinconf_get,
+ .pin_config_set = max77620_pinconf_set,
+};
+
+static struct pinctrl_desc max77620_pinctrl_desc = {
+ .pctlops = &max77620_pinctrl_ops,
+ .pmxops = &max77620_pinmux_ops,
+ .confops = &max77620_pinconf_ops,
+};
+
+static int max77620_pinctrl_probe(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci;
+ struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
+ int i;
+
+ mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
+ if (!mpci)
+ return -ENOMEM;
+
+ mpci->dev = &pdev->dev;
+ mpci->dev->of_node = pdev->dev.parent->of_node;
+ mpci->max77620 = max77620;
+
+ mpci->pins = max77620_pins_desc;
+ mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
+ mpci->functions = max77620_pin_function;
+ mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
+ mpci->pin_groups = max77620_pingroups;
+ mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
+ platform_set_drvdata(pdev, mpci);
+
+ max77620_pinctrl_desc.name = dev_name(&pdev->dev);
+ max77620_pinctrl_desc.pins = max77620_pins_desc;
+ max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
+ max77620_pinctrl_desc.num_custom_params =
+ ARRAY_SIZE(max77620_cfg_params);
+ max77620_pinctrl_desc.custom_params = max77620_cfg_params;
+
+ for (i = 0; i < MAX77620_PIN_NUM; ++i) {
+ mpci->fps_config[i].active_fps_src = -1;
+ mpci->fps_config[i].active_power_up_slots = -1;
+ mpci->fps_config[i].active_power_down_slots = -1;
+ mpci->fps_config[i].suspend_fps_src = -1;
+ mpci->fps_config[i].suspend_power_up_slots = -1;
+ mpci->fps_config[i].suspend_power_down_slots = -1;
+ }
+
+ mpci->pctl = pinctrl_register(&max77620_pinctrl_desc,
+ &pdev->dev, mpci);
+ if (IS_ERR(mpci->pctl)) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return PTR_ERR(mpci->pctl);
+ }
+
+ return 0;
+}
+
+static int max77620_pinctrl_remove(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(mpci->pctl);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_suspend_fps_param[] = {
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_active_fps_param[] = {
+ MAX77620_ACTIVE_FPS_SOURCE,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_pinctrl_suspend(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_suspend_fps_param[p]);
+ }
+
+ return 0;
+};
+
+static int max77620_pinctrl_resume(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_active_fps_param[p]);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(
+ max77620_pinctrl_suspend, max77620_pinctrl_resume)
+};
+
+static const struct platform_device_id max77620_pinctrl_devtype[] = {
+ { .name = "max77620-pinctrl", },
+ { .name = "max20024-pinctrl", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
+
+static struct platform_driver max77620_pinctrl_driver = {
+ .driver = {
+ .name = "max77620-pinctrl",
+ .pm = &max77620_pinctrl_pm_ops,
+ },
+ .probe = max77620_pinctrl_probe,
+ .remove = max77620_pinctrl_remove,
+ .id_table = max77620_pinctrl_devtype,
+};
+
+static int __init max77620_pinctrl_init(void)
+{
+ return platform_driver_register(&max77620_pinctrl_driver);
+}
+subsys_initcall(max77620_pinctrl_init);
+
+static void __exit max77620_pinctrl_exit(void)
+{
+ platform_driver_unregister(&max77620_pinctrl_driver);
+}
+module_exit(max77620_pinctrl_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
+MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pinctrl");
+MODULE_LICENSE("GPL v2");
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH V3 3/5] pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.
Add pincontrol driver to configure these parameters through
pincontrol APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-max77620.c | 703 +++++++++++++++++++++++++++++++++++++
3 files changed, 714 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-max77620.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 99a4c10..b6d2d23 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -227,6 +227,16 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MAX77620
+ bool "MAX77620/MAX20024 Pincontrol support"
+ depends on MFD_MAX77620
+ select GENERIC_PINCONF
+ help
+ Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
+ This PMIC has 8 GPIO pins that work as GPIO as well as special
+ function in alternate mode. This driver also configure push-pull,
+ open drain, FPS slots etc.
+
config PINCTRL_PALMAS
bool "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index bf1b5ca..72833e3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
new file mode 100644
index 0000000..440d700
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -0,0 +1,703 @@
+/*
+ * MAX77620 pin control driver.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max77620.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define MAX77620_PIN_NUM 8
+
+enum max77620_pin_ppdrv {
+ MAX77620_PIN_UNCONFIG_DRV,
+ MAX77620_PIN_OD_DRV,
+ MAX77620_PIN_PP_DRV,
+};
+
+enum max77620_pinconf_param {
+ MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+struct max77620_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned ngroups;
+ int mux_option;
+};
+
+struct max77620_cfg_param {
+ const char *property;
+ enum max77620_pinconf_param param;
+};
+
+static const struct pinconf_generic_params max77620_cfg_params[] = {
+ {
+ .property = "maxim,active-fps-source",
+ .param = MAX77620_ACTIVE_FPS_SOURCE,
+ }, {
+ .property = "maxim,active-fps-power-up-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,active-fps-power-down-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-source",
+ .param = MAX77620_SUSPEND_FPS_SOURCE,
+ }, {
+ .property = "maxim,suspend-fps-power-up-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-power-down-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+ },
+};
+
+enum max77620_alternate_pinmux_option {
+ MAX77620_PINMUX_GPIO = 0,
+ MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
+ MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
+ MAX77620_PINMUX_32K_OUT1 = 3,
+ MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
+ MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
+ MAX77620_PINMUX_REFERENCE_OUT = 6,
+};
+
+struct max77620_pingroup {
+ const char *name;
+ const unsigned pins[1];
+ unsigned npins;
+ enum max77620_alternate_pinmux_option alt_option;
+};
+
+struct max77620_pin_info {
+ enum max77620_pin_ppdrv drv_type;
+ int pull_config;
+};
+
+struct max77620_fps_config {
+ int active_fps_src;
+ int active_power_up_slots;
+ int active_power_down_slots;
+ int suspend_fps_src;
+ int suspend_power_up_slots;
+ int suspend_power_down_slots;
+};
+
+struct max77620_pctrl_info {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct max77620_chip *max77620;
+ int pins_current_opt[MAX77620_GPIO_NR];
+ const struct max77620_pin_function *functions;
+ unsigned num_functions;
+ const struct max77620_pingroup *pin_groups;
+ int num_pin_groups;
+ const struct pinctrl_pin_desc *pins;
+ unsigned num_pins;
+ struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
+ struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
+};
+
+static const struct pinctrl_pin_desc max77620_pins_desc[] = {
+ PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
+ PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
+ PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
+ PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
+ PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
+ PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
+ PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
+ PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+#define FUNCTION_GROUP(fname, mux) \
+ { \
+ .name = fname, \
+ .groups = gpio_groups, \
+ .ngroups = ARRAY_SIZE(gpio_groups), \
+ .mux_option = MAX77620_PINMUX_##mux, \
+ }
+
+static const struct max77620_pin_function max77620_pin_function[] = {
+ FUNCTION_GROUP("gpio", GPIO),
+ FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
+ FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
+ FUNCTION_GROUP("32k-out1", 32K_OUT1),
+ FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("reference-out", REFERENCE_OUT),
+};
+
+#define MAX77620_PINGROUP(pg_name, pin_id, option) \
+ { \
+ .name = #pg_name, \
+ .pins = {MAX77620_##pin_id}, \
+ .npins = 1, \
+ .alt_option = MAX77620_PINMUX_##option, \
+ }
+
+static const struct max77620_pingroup max77620_pingroups[] = {
+ MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
+ MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
+ MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
+};
+
+static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_pin_groups;
+}
+
+static const char *max77620_pinctrl_get_group_name(
+ struct pinctrl_dev *pctldev, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->pin_groups[group].name;
+}
+
+static int max77620_pinctrl_get_group_pins(
+ struct pinctrl_dev *pctldev, unsigned group,
+ const unsigned **pins, unsigned *num_pins)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = mpci->pin_groups[group].pins;
+ *num_pins = mpci->pin_groups[group].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops max77620_pinctrl_ops = {
+ .get_groups_count = max77620_pinctrl_get_groups_count,
+ .get_group_name = max77620_pinctrl_get_group_name,
+ .get_group_pins = max77620_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_functions;
+}
+
+static const char *max77620_pinctrl_get_func_name(
+ struct pinctrl_dev *pctldev, unsigned function)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->functions[function].name;
+}
+
+static int max77620_pinctrl_get_func_groups(
+ struct pinctrl_dev *pctldev, unsigned function,
+ const char * const **groups, unsigned * const num_groups)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = mpci->functions[function].groups;
+ *num_groups = mpci->functions[function].ngroups;
+
+ return 0;
+}
+
+static int max77620_pinctrl_enable(
+ struct pinctrl_dev *pctldev, unsigned function, unsigned group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ u8 val;
+ int ret;
+
+ if (function == MAX77620_PINMUX_GPIO) {
+ val = 0;
+ } else if (function == mpci->pin_groups[group].alt_option) {
+ val = 1 << group;
+ } else {
+ dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
+ group, function);
+ return -EINVAL;
+ }
+ ret = max77620_reg_update(mpci->max77620->dev, MAX77620_REG_AME_GPIO,
+ 1 << group, val);
+ if (ret < 0)
+ dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
+
+ return ret;
+}
+
+static const struct pinmux_ops max77620_pinmux_ops = {
+ .get_functions_count = max77620_pinctrl_get_funcs_count,
+ .get_function_name = max77620_pinctrl_get_func_name,
+ .get_function_groups = max77620_pinctrl_get_func_groups,
+ .set_mux = max77620_pinctrl_enable,
+};
+
+static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u8 val;
+ int arg = 0;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = max77620_reg_read(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, (u16)arg);
+
+ return 0;
+}
+
+static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
+ int addr, int *fps)
+{
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mpci->max77620->dev, addr, &val);
+ if (ret < 0) {
+ dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+
+ return 0;
+}
+
+static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
+ int pin, int param)
+{
+ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
+ int addr, ret;
+ int param_val;
+ int mask, shift;
+
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return 0;
+
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ switch (param) {
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ mask = MAX77620_FPS_SRC_MASK;
+ shift = MAX77620_FPS_SRC_SHIFT;
+ param_val = fps_config->active_fps_src;
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ param_val = fps_config->suspend_fps_src;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ mask = MAX77620_FPS_PU_PERIOD_MASK;
+ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
+ param_val = fps_config->active_power_up_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ param_val = fps_config->suspend_power_up_slots;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ mask = MAX77620_FPS_PD_PERIOD_MASK;
+ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
+ param_val = fps_config->active_power_down_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
+ param_val = fps_config->suspend_power_down_slots;
+ break;
+
+ default:
+ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
+ param, pin);
+ return -EINVAL;
+ }
+
+ if (param_val < 0)
+ return 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev, addr, mask,
+ param_val << shift);
+ if (ret < 0)
+ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
+
+ return ret;
+}
+
+static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ struct device *parent = mpci->max77620->dev;
+ struct max77620_fps_config *fps_config;
+ int param;
+ u16 param_val;
+ unsigned int val;
+ unsigned int pu_val;
+ unsigned int pd_val;
+ int addr, ret;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ param_val = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ val = param_val ? 0 : 1;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ val = param_val ? 1 : 0;
+ ret = max77620_reg_update(
+ parent, MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK, val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->active_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_ACTIVE_FPS_SOURCE)
+ fps_config->active_fps_src = param_val;
+ else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
+ fps_config->active_power_up_slots = param_val;
+ else
+ fps_config->active_power_down_slots = param_val;
+
+ ret = max77620_set_fps_param(mpci, pin, param);
+ if (ret < 0)
+ return ret;
+ break;
+
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
+ (param_val == FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->suspend_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ fps_config->suspend_fps_src = param_val;
+ else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ fps_config->suspend_power_up_slots = param_val;
+ else
+ fps_config->suspend_power_down_slots =
+ param_val;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
+ BIT(pin) : 0;
+ pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
+ BIT(pin) : 0;
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PUE_GPIO,
+ BIT(pin), pu_val);
+ if (ret < 0) {
+ dev_err(dev, "PUE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mpci->max77620->dev,
+ MAX77620_REG_PDE_GPIO,
+ BIT(pin), pd_val);
+ if (ret < 0) {
+ dev_err(dev, "PDE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops max77620_pinconf_ops = {
+ .pin_config_get = max77620_pinconf_get,
+ .pin_config_set = max77620_pinconf_set,
+};
+
+static struct pinctrl_desc max77620_pinctrl_desc = {
+ .pctlops = &max77620_pinctrl_ops,
+ .pmxops = &max77620_pinmux_ops,
+ .confops = &max77620_pinconf_ops,
+};
+
+static int max77620_pinctrl_probe(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci;
+ struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
+ int i;
+
+ mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
+ if (!mpci)
+ return -ENOMEM;
+
+ mpci->dev = &pdev->dev;
+ mpci->dev->of_node = pdev->dev.parent->of_node;
+ mpci->max77620 = max77620;
+
+ mpci->pins = max77620_pins_desc;
+ mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
+ mpci->functions = max77620_pin_function;
+ mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
+ mpci->pin_groups = max77620_pingroups;
+ mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
+ platform_set_drvdata(pdev, mpci);
+
+ max77620_pinctrl_desc.name = dev_name(&pdev->dev);
+ max77620_pinctrl_desc.pins = max77620_pins_desc;
+ max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
+ max77620_pinctrl_desc.num_custom_params =
+ ARRAY_SIZE(max77620_cfg_params);
+ max77620_pinctrl_desc.custom_params = max77620_cfg_params;
+
+ for (i = 0; i < MAX77620_PIN_NUM; ++i) {
+ mpci->fps_config[i].active_fps_src = -1;
+ mpci->fps_config[i].active_power_up_slots = -1;
+ mpci->fps_config[i].active_power_down_slots = -1;
+ mpci->fps_config[i].suspend_fps_src = -1;
+ mpci->fps_config[i].suspend_power_up_slots = -1;
+ mpci->fps_config[i].suspend_power_down_slots = -1;
+ }
+
+ mpci->pctl = pinctrl_register(&max77620_pinctrl_desc,
+ &pdev->dev, mpci);
+ if (IS_ERR(mpci->pctl)) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return PTR_ERR(mpci->pctl);
+ }
+
+ return 0;
+}
+
+static int max77620_pinctrl_remove(struct platform_device *pdev)
+{
+ struct max77620_pctrl_info *mpci = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(mpci->pctl);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_suspend_fps_param[] = {
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_active_fps_param[] = {
+ MAX77620_ACTIVE_FPS_SOURCE,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_pinctrl_suspend(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_suspend_fps_param[p]);
+ }
+
+ return 0;
+};
+
+static int max77620_pinctrl_resume(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_active_fps_param[p]);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(
+ max77620_pinctrl_suspend, max77620_pinctrl_resume)
+};
+
+static const struct platform_device_id max77620_pinctrl_devtype[] = {
+ { .name = "max77620-pinctrl", },
+ { .name = "max20024-pinctrl", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
+
+static struct platform_driver max77620_pinctrl_driver = {
+ .driver = {
+ .name = "max77620-pinctrl",
+ .pm = &max77620_pinctrl_pm_ops,
+ },
+ .probe = max77620_pinctrl_probe,
+ .remove = max77620_pinctrl_remove,
+ .id_table = max77620_pinctrl_devtype,
+};
+
+static int __init max77620_pinctrl_init(void)
+{
+ return platform_driver_register(&max77620_pinctrl_driver);
+}
+subsys_initcall(max77620_pinctrl_init);
+
+static void __exit max77620_pinctrl_exit(void)
+{
+ platform_driver_unregister(&max77620_pinctrl_driver);
+}
+module_exit(max77620_pinctrl_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
+MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pinctrl");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH V3 4/5] gpio: max77620: add gpio driver for MAX77620/MAX20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-14 11:32 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Use the gpiochip_add_data and get the chip data from core APIs.
- Cleanups based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-max77620.c | 302 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 312 insertions(+)
create mode 100644 drivers/gpio/gpio-max77620.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f2b7160..b96a80c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -797,6 +797,15 @@ config GPIO_LP3943
LP3943 can be used as a GPIO expander which provides up to 16 GPIOs.
Open drain outputs are required for this usage.
+config GPIO_MAX77620
+ bool "GPIO support for PMIC MAX77620 and MAX20024"
+ depends on MFD_MAX77620
+ help
+ GPIO driver for MAX77620 and MAX20024 PMIC from Maxim Semiconductor.
+ MAX77620 PMIC has 8 pins that can be configured as GPIOs. The
+ driver also provides interrupt support for each of the gpios.
+ Say yes here to enable the max77620 to be used as gpio controller.
+
config GPIO_MSIC
bool "Intel MSIC mixed signal gpio support"
depends on MFD_INTEL_MSIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ece7d7c..f676a2d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
+obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o
obj-$(CONFIG_GPIO_MB86S7X) += gpio-mb86s7x.o
obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
new file mode 100644
index 0000000..dcf6099
--- /dev/null
+++ b/drivers/gpio/gpio-max77620.c
@@ -0,0 +1,302 @@
+/*
+ * MAXIM MAX77620 GPIO driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/max77620.h>
+
+#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
+
+struct max77620_gpio {
+ struct gpio_chip gpio_chip;
+ struct device *parent;
+ struct device *dev;
+ int gpio_irq;
+ int irq_base;
+ int gpio_base;
+};
+
+static const struct regmap_irq max77620_gpio_irqs[] = {
+ [MAX77620_IRQ_GPIO0 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO1 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO2 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO3 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO4 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO5 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO6 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO7 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
+ .reg_offset = 0,
+ },
+};
+
+static struct regmap_irq_chip max77620_gpio_irq_chip = {
+ .name = "max77620-gpio",
+ .irqs = max77620_gpio_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
+ .num_regs = 1,
+ .irq_reg_stride = 1,
+ .status_base = MAX77620_REG_IRQ_LVL2_GPIO,
+};
+
+static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ int ret;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_INPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mgpio->parent, GPIO_REG_ADDR(offset), &val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
+ return ret;
+ }
+
+ return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
+}
+
+static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_OUTPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_set_debounce(struct gpio_chip *gc,
+ unsigned offset, unsigned debounce)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ switch (debounce) {
+ case 0:
+ val = MAX77620_CNFG_GPIO_DBNC_None;
+ break;
+ case 1 ... 8:
+ val = MAX77620_CNFG_GPIO_DBNC_8ms;
+ break;
+ case 9 ... 16:
+ val = MAX77620_CNFG_GPIO_DBNC_16ms;
+ break;
+ case 17 ... 32:
+ val = MAX77620_CNFG_GPIO_DBNC_32ms;
+ break;
+ default:
+ dev_err(mgpio->dev, "Illegal value %u\n", debounce);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DBNC_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
+
+ return ret;
+}
+
+static void max77620_gpio_set(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
+}
+
+static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ return regmap_irq_get_virq(chip->gpio_irq_data, offset);
+}
+
+static void max77620_gpio_irq_remove(struct max77620_gpio *mgpio)
+{
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ regmap_del_irq_chip(mgpio->gpio_irq, chip->gpio_irq_data);
+ chip->gpio_irq_data = NULL;
+}
+
+static int max77620_gpio_probe(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio;
+ struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
+ int ret;
+ int gpio_irq;
+
+ gpio_irq = platform_get_irq(pdev, 0);
+ if (gpio_irq <= 0) {
+ dev_err(&pdev->dev, "Gpio irq not available %d\n", gpio_irq);
+ return -ENODEV;
+ }
+
+ mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
+ if (!mgpio)
+ return -ENOMEM;
+
+ mgpio->parent = pdev->dev.parent;
+ mgpio->dev = &pdev->dev;
+ mgpio->gpio_irq = gpio_irq;
+
+ mgpio->gpio_chip.label = pdev->name;
+ mgpio->gpio_chip.parent = &pdev->dev;
+ mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
+ mgpio->gpio_chip.get = max77620_gpio_get;
+ mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
+ mgpio->gpio_chip.set = max77620_gpio_set;
+ mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
+ mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
+ mgpio->gpio_chip.can_sleep = 1;
+ mgpio->gpio_chip.base = -1;
+ mgpio->irq_base = -1;
+#ifdef CONFIG_OF_GPIO
+ mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
+#endif
+
+ platform_set_drvdata(pdev, mgpio);
+
+ ret = gpiochip_add_data(&mgpio->gpio_chip, mgpio);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
+ return ret;
+ }
+ mgpio->gpio_base = mgpio->gpio_chip.base;
+
+ ret = regmap_add_irq_chip(chip->rmap, mgpio->gpio_irq, IRQF_ONESHOT,
+ mgpio->irq_base,
+ &max77620_gpio_irq_chip,
+ &chip->gpio_irq_data);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return ret;
+}
+
+static int max77620_gpio_remove(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio = platform_get_drvdata(pdev);
+
+ max77620_gpio_irq_remove(mgpio);
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return 0;
+}
+
+static const struct platform_device_id max77620_gpio_devtype[] = {
+ { .name = "max77620-gpio", },
+ { .name = "max20024-gpio", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
+
+static struct platform_driver max77620_gpio_driver = {
+ .driver.name = "max77620-gpio",
+ .driver.owner = THIS_MODULE,
+ .probe = max77620_gpio_probe,
+ .remove = max77620_gpio_remove,
+ .id_table = max77620_gpio_devtype,
+};
+
+static int __init max77620_gpio_init(void)
+{
+ return platform_driver_register(&max77620_gpio_driver);
+}
+subsys_initcall(max77620_gpio_init);
+
+static void __exit max77620_gpio_exit(void)
+{
+ platform_driver_unregister(&max77620_gpio_driver);
+}
+module_exit(max77620_gpio_exit);
+
+MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_ALIAS("platform:max77620-gpio");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [rtc-linux] [PATCH V3 4/5] gpio: max77620: add gpio driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Use the gpiochip_add_data and get the chip data from core APIs.
- Cleanups based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-max77620.c | 302 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 312 insertions(+)
create mode 100644 drivers/gpio/gpio-max77620.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f2b7160..b96a80c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -797,6 +797,15 @@ config GPIO_LP3943
LP3943 can be used as a GPIO expander which provides up to 16 GPIOs.
Open drain outputs are required for this usage.
+config GPIO_MAX77620
+ bool "GPIO support for PMIC MAX77620 and MAX20024"
+ depends on MFD_MAX77620
+ help
+ GPIO driver for MAX77620 and MAX20024 PMIC from Maxim Semiconductor.
+ MAX77620 PMIC has 8 pins that can be configured as GPIOs. The
+ driver also provides interrupt support for each of the gpios.
+ Say yes here to enable the max77620 to be used as gpio controller.
+
config GPIO_MSIC
bool "Intel MSIC mixed signal gpio support"
depends on MFD_INTEL_MSIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ece7d7c..f676a2d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
+obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o
obj-$(CONFIG_GPIO_MB86S7X) += gpio-mb86s7x.o
obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
new file mode 100644
index 0000000..dcf6099
--- /dev/null
+++ b/drivers/gpio/gpio-max77620.c
@@ -0,0 +1,302 @@
+/*
+ * MAXIM MAX77620 GPIO driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/max77620.h>
+
+#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
+
+struct max77620_gpio {
+ struct gpio_chip gpio_chip;
+ struct device *parent;
+ struct device *dev;
+ int gpio_irq;
+ int irq_base;
+ int gpio_base;
+};
+
+static const struct regmap_irq max77620_gpio_irqs[] = {
+ [MAX77620_IRQ_GPIO0 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO1 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO2 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO3 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO4 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO5 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO6 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO7 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
+ .reg_offset = 0,
+ },
+};
+
+static struct regmap_irq_chip max77620_gpio_irq_chip = {
+ .name = "max77620-gpio",
+ .irqs = max77620_gpio_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
+ .num_regs = 1,
+ .irq_reg_stride = 1,
+ .status_base = MAX77620_REG_IRQ_LVL2_GPIO,
+};
+
+static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ int ret;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_INPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mgpio->parent, GPIO_REG_ADDR(offset), &val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
+ return ret;
+ }
+
+ return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
+}
+
+static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_OUTPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_set_debounce(struct gpio_chip *gc,
+ unsigned offset, unsigned debounce)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ switch (debounce) {
+ case 0:
+ val = MAX77620_CNFG_GPIO_DBNC_None;
+ break;
+ case 1 ... 8:
+ val = MAX77620_CNFG_GPIO_DBNC_8ms;
+ break;
+ case 9 ... 16:
+ val = MAX77620_CNFG_GPIO_DBNC_16ms;
+ break;
+ case 17 ... 32:
+ val = MAX77620_CNFG_GPIO_DBNC_32ms;
+ break;
+ default:
+ dev_err(mgpio->dev, "Illegal value %u\n", debounce);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DBNC_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
+
+ return ret;
+}
+
+static void max77620_gpio_set(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
+}
+
+static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ return regmap_irq_get_virq(chip->gpio_irq_data, offset);
+}
+
+static void max77620_gpio_irq_remove(struct max77620_gpio *mgpio)
+{
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ regmap_del_irq_chip(mgpio->gpio_irq, chip->gpio_irq_data);
+ chip->gpio_irq_data = NULL;
+}
+
+static int max77620_gpio_probe(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio;
+ struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
+ int ret;
+ int gpio_irq;
+
+ gpio_irq = platform_get_irq(pdev, 0);
+ if (gpio_irq <= 0) {
+ dev_err(&pdev->dev, "Gpio irq not available %d\n", gpio_irq);
+ return -ENODEV;
+ }
+
+ mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
+ if (!mgpio)
+ return -ENOMEM;
+
+ mgpio->parent = pdev->dev.parent;
+ mgpio->dev = &pdev->dev;
+ mgpio->gpio_irq = gpio_irq;
+
+ mgpio->gpio_chip.label = pdev->name;
+ mgpio->gpio_chip.parent = &pdev->dev;
+ mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
+ mgpio->gpio_chip.get = max77620_gpio_get;
+ mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
+ mgpio->gpio_chip.set = max77620_gpio_set;
+ mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
+ mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
+ mgpio->gpio_chip.can_sleep = 1;
+ mgpio->gpio_chip.base = -1;
+ mgpio->irq_base = -1;
+#ifdef CONFIG_OF_GPIO
+ mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
+#endif
+
+ platform_set_drvdata(pdev, mgpio);
+
+ ret = gpiochip_add_data(&mgpio->gpio_chip, mgpio);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
+ return ret;
+ }
+ mgpio->gpio_base = mgpio->gpio_chip.base;
+
+ ret = regmap_add_irq_chip(chip->rmap, mgpio->gpio_irq, IRQF_ONESHOT,
+ mgpio->irq_base,
+ &max77620_gpio_irq_chip,
+ &chip->gpio_irq_data);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return ret;
+}
+
+static int max77620_gpio_remove(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio = platform_get_drvdata(pdev);
+
+ max77620_gpio_irq_remove(mgpio);
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return 0;
+}
+
+static const struct platform_device_id max77620_gpio_devtype[] = {
+ { .name = "max77620-gpio", },
+ { .name = "max20024-gpio", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
+
+static struct platform_driver max77620_gpio_driver = {
+ .driver.name = "max77620-gpio",
+ .driver.owner = THIS_MODULE,
+ .probe = max77620_gpio_probe,
+ .remove = max77620_gpio_remove,
+ .id_table = max77620_gpio_devtype,
+};
+
+static int __init max77620_gpio_init(void)
+{
+ return platform_driver_register(&max77620_gpio_driver);
+}
+subsys_initcall(max77620_gpio_init);
+
+static void __exit max77620_gpio_exit(void)
+{
+ platform_driver_unregister(&max77620_gpio_driver);
+}
+module_exit(max77620_gpio_exit);
+
+MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_ALIAS("platform:max77620-gpio");
+MODULE_LICENSE("GPL v2");
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH V3 4/5] gpio: max77620: add gpio driver for MAX77620/MAX20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan, Chaitanya Bandi
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO
pins. It also supports interrupts from these pins.
Add GPIO driver for these pins to control via GPIO APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
---
Changes from V1:
- Use the gpiochip_add_data and get the chip data from core APIs.
- Cleanups based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- update based on api changes from core.
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-max77620.c | 302 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 312 insertions(+)
create mode 100644 drivers/gpio/gpio-max77620.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f2b7160..b96a80c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -797,6 +797,15 @@ config GPIO_LP3943
LP3943 can be used as a GPIO expander which provides up to 16 GPIOs.
Open drain outputs are required for this usage.
+config GPIO_MAX77620
+ bool "GPIO support for PMIC MAX77620 and MAX20024"
+ depends on MFD_MAX77620
+ help
+ GPIO driver for MAX77620 and MAX20024 PMIC from Maxim Semiconductor.
+ MAX77620 PMIC has 8 pins that can be configured as GPIOs. The
+ driver also provides interrupt support for each of the gpios.
+ Say yes here to enable the max77620 to be used as gpio controller.
+
config GPIO_MSIC
bool "Intel MSIC mixed signal gpio support"
depends on MFD_INTEL_MSIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ece7d7c..f676a2d 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
+obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o
obj-$(CONFIG_GPIO_MB86S7X) += gpio-mb86s7x.o
obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
new file mode 100644
index 0000000..dcf6099
--- /dev/null
+++ b/drivers/gpio/gpio-max77620.c
@@ -0,0 +1,302 @@
+/*
+ * MAXIM MAX77620 GPIO driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/max77620.h>
+
+#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
+
+struct max77620_gpio {
+ struct gpio_chip gpio_chip;
+ struct device *parent;
+ struct device *dev;
+ int gpio_irq;
+ int irq_base;
+ int gpio_base;
+};
+
+static const struct regmap_irq max77620_gpio_irqs[] = {
+ [MAX77620_IRQ_GPIO0 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO1 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO2 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO3 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO4 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO5 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO6 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
+ .reg_offset = 0,
+ },
+ [MAX77620_IRQ_GPIO7 - MAX77620_IRQ_GPIO0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
+ .reg_offset = 0,
+ },
+};
+
+static struct regmap_irq_chip max77620_gpio_irq_chip = {
+ .name = "max77620-gpio",
+ .irqs = max77620_gpio_irqs,
+ .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
+ .num_regs = 1,
+ .irq_reg_stride = 1,
+ .status_base = MAX77620_REG_IRQ_LVL2_GPIO,
+};
+
+static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ int ret;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_INPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(mgpio->parent, GPIO_REG_ADDR(offset), &val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
+ return ret;
+ }
+
+ return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
+}
+
+static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DIR_MASK,
+ MAX77620_CNFG_GPIO_DIR_OUTPUT);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
+
+ return ret;
+}
+
+static int max77620_gpio_set_debounce(struct gpio_chip *gc,
+ unsigned offset, unsigned debounce)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ switch (debounce) {
+ case 0:
+ val = MAX77620_CNFG_GPIO_DBNC_None;
+ break;
+ case 1 ... 8:
+ val = MAX77620_CNFG_GPIO_DBNC_8ms;
+ break;
+ case 9 ... 16:
+ val = MAX77620_CNFG_GPIO_DBNC_16ms;
+ break;
+ case 17 ... 32:
+ val = MAX77620_CNFG_GPIO_DBNC_32ms;
+ break;
+ default:
+ dev_err(mgpio->dev, "Illegal value %u\n", debounce);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_DBNC_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
+
+ return ret;
+}
+
+static void max77620_gpio_set(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ u8 val;
+ int ret;
+
+ val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
+
+ ret = max77620_reg_update(mgpio->parent, GPIO_REG_ADDR(offset),
+ MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
+ if (ret < 0)
+ dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
+}
+
+static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ return regmap_irq_get_virq(chip->gpio_irq_data, offset);
+}
+
+static void max77620_gpio_irq_remove(struct max77620_gpio *mgpio)
+{
+ struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
+
+ regmap_del_irq_chip(mgpio->gpio_irq, chip->gpio_irq_data);
+ chip->gpio_irq_data = NULL;
+}
+
+static int max77620_gpio_probe(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio;
+ struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
+ int ret;
+ int gpio_irq;
+
+ gpio_irq = platform_get_irq(pdev, 0);
+ if (gpio_irq <= 0) {
+ dev_err(&pdev->dev, "Gpio irq not available %d\n", gpio_irq);
+ return -ENODEV;
+ }
+
+ mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
+ if (!mgpio)
+ return -ENOMEM;
+
+ mgpio->parent = pdev->dev.parent;
+ mgpio->dev = &pdev->dev;
+ mgpio->gpio_irq = gpio_irq;
+
+ mgpio->gpio_chip.label = pdev->name;
+ mgpio->gpio_chip.parent = &pdev->dev;
+ mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
+ mgpio->gpio_chip.get = max77620_gpio_get;
+ mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
+ mgpio->gpio_chip.set = max77620_gpio_set;
+ mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
+ mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
+ mgpio->gpio_chip.can_sleep = 1;
+ mgpio->gpio_chip.base = -1;
+ mgpio->irq_base = -1;
+#ifdef CONFIG_OF_GPIO
+ mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
+#endif
+
+ platform_set_drvdata(pdev, mgpio);
+
+ ret = gpiochip_add_data(&mgpio->gpio_chip, mgpio);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
+ return ret;
+ }
+ mgpio->gpio_base = mgpio->gpio_chip.base;
+
+ ret = regmap_add_irq_chip(chip->rmap, mgpio->gpio_irq, IRQF_ONESHOT,
+ mgpio->irq_base,
+ &max77620_gpio_irq_chip,
+ &chip->gpio_irq_data);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return ret;
+}
+
+static int max77620_gpio_remove(struct platform_device *pdev)
+{
+ struct max77620_gpio *mgpio = platform_get_drvdata(pdev);
+
+ max77620_gpio_irq_remove(mgpio);
+ gpiochip_remove(&mgpio->gpio_chip);
+
+ return 0;
+}
+
+static const struct platform_device_id max77620_gpio_devtype[] = {
+ { .name = "max77620-gpio", },
+ { .name = "max20024-gpio", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
+
+static struct platform_driver max77620_gpio_driver = {
+ .driver.name = "max77620-gpio",
+ .driver.owner = THIS_MODULE,
+ .probe = max77620_gpio_probe,
+ .remove = max77620_gpio_remove,
+ .id_table = max77620_gpio_devtype,
+};
+
+static int __init max77620_gpio_init(void)
+{
+ return platform_driver_register(&max77620_gpio_driver);
+}
+subsys_initcall(max77620_gpio_init);
+
+static void __exit max77620_gpio_exit(void)
+{
+ platform_driver_unregister(&max77620_gpio_driver);
+}
+module_exit(max77620_gpio_exit);
+
+MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
+MODULE_ALIAS("platform:max77620-gpio");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
2016-01-14 11:32 ` Laxman Dewangan
(?)
@ 2016-01-14 11:32 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan,
Mallikarjun Kasoju
MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
multiple DCDC and LDOs. This supplies the power to different
components of the system.
Also these rails has configuration for ramp time, flexible
power sequence, slew rate etc.
Add regulator driver to access these rails via regulator APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Refactor Regulator driver to use core API for DT parsing.
- Update based on API changes.
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77620-regulator.c | 892 +++++++++++++++++++++++++++++++++
3 files changed, 902 insertions(+)
create mode 100644 drivers/regulator/max77620-regulator.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8155e80..b92214b 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -343,6 +343,15 @@ config REGULATOR_MAX1586
regulator via I2C bus. The provided regulator is suitable
for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
+config REGULATOR_MAX77620
+ tristate "Maxim 77620/MAX20024 voltage regulator"
+ depends on MFD_MAX77620
+ help
+ This driver controls Maxim MAX77620 voltage output regulator
+ via I2C bus. The provided regulator is suitable for Tegra
+ chip to control Step-Down DC-DC and LDOs. Say Y here to
+ enable the regulator driver.
+
config REGULATOR_MAX8649
tristate "Maxim 8649 voltage regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 980b194..2564c00 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o
obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
+obj-$(CONFIG_REGULATOR_MAX77620) += max77620-regulator.o
obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c
new file mode 100644
index 0000000..97e7572
--- /dev/null
+++ b/drivers/regulator/max77620-regulator.c
@@ -0,0 +1,892 @@
+/*
+ * Maxim MAX77620 Regulator driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/mfd/max77620.h>
+
+#define max77620_rails(_name) "max77620-"#_name
+
+/* Power Mode */
+#define MAX77620_POWER_MODE_NORMAL 3
+#define MAX77620_POWER_MODE_LPM 2
+#define MAX77620_POWER_MODE_GLPM 1
+#define MAX77620_POWER_MODE_DISABLE 0
+
+/* SD Slew Rate */
+#define MAX77620_SD_SR_13_75 0
+#define MAX77620_SD_SR_27_5 1
+#define MAX77620_SD_SR_55 2
+#define MAX77620_SD_SR_100 3
+
+#define MAX77620_FPS_SRC_NUM 3
+
+struct max77620_regulator_info {
+ u8 type;
+ u32 min_uV;
+ u32 max_uV;
+ u32 step_uV;
+ u8 fps_addr;
+ u8 volt_addr;
+ u8 cfg_addr;
+ u8 volt_mask;
+ u8 power_mode_mask;
+ u8 power_mode_shift;
+ u8 remote_sense_addr;
+ u8 remote_sense_mask;
+ struct regulator_desc desc;
+};
+
+struct max77620_regulator_pdata {
+ bool glpm_enable;
+ bool sd_fsrade_disable;
+ bool disable_remote_sense_on_suspend;
+ struct regulator_init_data *reg_idata;
+ int active_fps_src;
+ int active_fps_pd_slot;
+ int active_fps_pu_slot;
+ int suspend_fps_src;
+ int suspend_fps_pd_slot;
+ int suspend_fps_pu_slot;
+ int current_mode;
+};
+
+struct max77620_regulator {
+ struct device *dev;
+ struct max77620_chip *max77620_chip;
+ struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
+ struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
+ struct regulator_desc *rdesc[MAX77620_NUM_REGS];
+ int enable_power_mode[MAX77620_NUM_REGS];
+ int current_power_mode[MAX77620_NUM_REGS];
+ int active_fps_src[MAX77620_NUM_REGS];
+};
+
+#define fps_src_name(fps_src) \
+ (fps_src == FPS_SRC_0 ? "FPS_SRC_0" : \
+ fps_src == FPS_SRC_1 ? "FPS_SRC_1" : \
+ fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
+
+static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+
+ return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+}
+
+static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
+ int fps_src, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ switch (fps_src) {
+ case FPS_SRC_0:
+ case FPS_SRC_1:
+ case FPS_SRC_2:
+ case FPS_SRC_NONE:
+ break;
+
+ case FPS_SRC_DEF:
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+ pmic->active_fps_src[id] = ret;
+ return 0;
+
+ default:
+ dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
+ fps_src, id);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->fps_addr,
+ MAX77620_FPS_SRC_MASK,
+ fps_src << MAX77620_FPS_SRC_SHIFT);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ pmic->active_fps_src[id] = fps_src;
+
+ return 0;
+}
+
+static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
+ int id, bool is_suspend)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ unsigned int val = 0;
+ unsigned int mask = 0;
+ int pu = rpdata->active_fps_pu_slot;
+ int pd = rpdata->active_fps_pd_slot;
+ int ret = 0;
+
+ if (is_suspend) {
+ pu = rpdata->suspend_fps_pu_slot;
+ pd = rpdata->suspend_fps_pd_slot;
+ }
+
+ /* FPS power up period setting */
+ if (pu >= 0) {
+ val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PU_PERIOD_MASK;
+ }
+
+ /* FPS power down period setting */
+ if (pd >= 0) {
+ val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PD_PERIOD_MASK;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(parent, rinfo->fps_addr, mask, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
+ int power_mode, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_update(parent, addr, mask, power_mode << shift);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
+ id, ret);
+ return ret;
+ }
+ pmic->current_power_mode[id] = power_mode;
+
+ return ret;
+}
+
+static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 val, addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_read(parent, addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
+ id, addr, ret);
+ return ret;
+ }
+
+ return (val & mask) >> shift;
+}
+
+static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 rval;
+ int slew_rate;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+
+ slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 13750;
+ break;
+ case 1:
+ slew_rate = 27500;
+ break;
+ case 2:
+ slew_rate = 55000;
+ break;
+ case 3:
+ slew_rate = 100000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ default:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ slew_rate = rval & 0x1;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 100000;
+ break;
+ case 1:
+ slew_rate = 5000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ }
+
+ return 0;
+}
+
+static int max77620_init_sd_fs_trade(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ val = (rpdata->sd_fsrade_disable) ? MAX77620_SD_FSRADE_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FSRADE_MASK, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int ret;
+
+ /* Initialise sd_fstrade */
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_init_sd_fs_trade(pmic, id);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Update power mode */
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->current_power_mode[id] = ret;
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+
+ if (rpdata->active_fps_src == FPS_SRC_DEF) {
+ ret = max77620_regulator_get_fps_src(pmic, id);
+ if (ret < 0)
+ return ret;
+ rpdata->active_fps_src = ret;
+ }
+
+ /* If rails are externally control of FPS then enable it always. */
+ if (rpdata->active_fps_src == FPS_SRC_NONE) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ } else {
+ if (pmic->current_power_mode[id] !=
+ pmic->enable_power_mode[id]) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_regulator_set_fps_slots(pmic, id, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int max77620_regulator_enable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ pmic->enable_power_mode[id], id);
+}
+
+static int max77620_regulator_disable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ MAX77620_POWER_MODE_DISABLE, id);
+}
+
+static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ int ret = 1;
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 1;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ if (ret != MAX77620_POWER_MODE_DISABLE)
+ return 1;
+
+ return 0;
+}
+
+static int max77620_regulator_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ bool fpwm = false;
+ int power_mode;
+ int ret;
+ u8 val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ fpwm = true;
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ if (rpdata->glpm_enable)
+ power_mode = MAX77620_POWER_MODE_GLPM;
+ else
+ power_mode = MAX77620_POWER_MODE_LPM;
+ break;
+
+ default:
+ dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
+ id, mode);
+ return -EINVAL;
+ }
+
+ if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
+ goto skip_fpwm;
+
+ val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FPWM_MASK, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ rpdata->current_mode = mode;
+
+skip_fpwm:
+ ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->enable_power_mode[id] = power_mode;
+
+ return 0;
+}
+
+static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ struct device *parent = pmic->max77620_chip->dev;
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int fpwm = 0;
+ int ret;
+ int pm_mode, reg_mode;
+ u8 val;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return 0;
+
+ pm_mode = ret;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ fpwm = !!(val & MAX77620_SD_FPWM_MASK);
+ }
+
+ switch (pm_mode) {
+ case MAX77620_POWER_MODE_NORMAL:
+ case MAX77620_POWER_MODE_DISABLE:
+ if (fpwm)
+ reg_mode = REGULATOR_MODE_FAST;
+ else
+ reg_mode = REGULATOR_MODE_NORMAL;
+ break;
+ case MAX77620_POWER_MODE_LPM:
+ case MAX77620_POWER_MODE_GLPM:
+ reg_mode = REGULATOR_MODE_IDLE;
+ break;
+ default:
+ return 0;
+ }
+
+ return reg_mode;
+}
+
+static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
+ int ramp_delay)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ int ret, val;
+ u8 mask;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ if (ramp_delay <= 13750)
+ val = 0;
+ else if (ramp_delay <= 27500)
+ val = 1;
+ else if (ramp_delay <= 55000)
+ val = 2;
+ else
+ val = 3;
+ val <<= MAX77620_SD_SR_SHIFT;
+ mask = MAX77620_SD_SR_MASK;
+ } else {
+ if (ramp_delay <= 5000)
+ val = 1;
+ else
+ val = 0;
+ mask = MAX77620_LDO_SLEW_RATE_MASK;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->cfg_addr, mask, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_of_parse_cb(struct device_node *np,
+ const struct regulator_desc *desc,
+ struct regulator_config *config)
+{
+ struct max77620_regulator *pmic = config->driver_data;
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
+ u32 pval;
+ int ret;
+
+ rpdata->glpm_enable = of_property_read_bool(np,
+ "maxim,enable-group-low-power");
+
+ rpdata->sd_fsrade_disable = of_property_read_bool(np,
+ "maxim,disable-active-discharge");
+
+ rpdata->disable_remote_sense_on_suspend = of_property_read_bool(
+ np, "maxim,disable-remote-sense-on-suspend");
+
+ ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
+ rpdata->active_fps_src = (!ret) ? pval : FPS_SRC_DEF;
+
+ ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
+ rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,active-fps-power-down-slot", &pval);
+ rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
+ rpdata->suspend_fps_src = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-up-slot", &pval);
+ rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-down-slot", &pval);
+ rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
+
+ return max77620_init_pmic(pmic, desc->id);
+}
+
+static struct regulator_ops max77620_regulator_ops = {
+ .is_enabled = max77620_regulator_is_enabled,
+ .enable = max77620_regulator_enable,
+ .disable = max77620_regulator_disable,
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .set_mode = max77620_regulator_set_mode,
+ .get_mode = max77620_regulator_get_mode,
+ .set_ramp_delay = max77620_regulator_set_ramp_delay,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+};
+
+#define MAX77620_SD_CNF2_ROVS_EN_NONE 0
+#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
+ _step_uV, _rs_add, _rs_mask) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_SD, \
+ .volt_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = _rs_add, \
+ .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
+ .volt_mask = MAX77620_LDO_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id##_CFG, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG2, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = 0xFF, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_LDO_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id##_CFG, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static int max77620_regulator_probe(struct platform_device *pdev)
+{
+ struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
+ struct max77620_regulator_info *regulator_info;
+ struct device *dev = &pdev->dev;
+ struct regulator_config config = { };
+ struct max77620_regulator *pmic;
+ int ret = 0;
+ int id;
+
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pmic);
+ pmic->max77620_chip = max77620_chip;
+ pmic->dev = dev;
+ if (!dev->of_node)
+ dev->of_node = pdev->dev.parent->of_node;
+
+ regulator_info = (max77620_chip->id == MAX77620) ? max77620_regs_info :
+ max20024_regs_info;
+
+ config.regmap = max77620_chip->rmap;
+ config.dev = dev;
+ config.driver_data = pmic;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ struct regulator_dev *rdev;
+ struct regulator_desc *rdesc;
+
+ if ((max77620_chip->id == MAX77620) &&
+ (id == MAX77620_REGULATOR_ID_SD4))
+ continue;
+
+ rdesc = ®ulator_info[id].desc;
+ pmic->rinfo[id] = &max77620_regs_info[id];
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+ pmic->rdesc[id] = rdesc;
+
+ ret = max77620_read_slew_rate(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+ ret = PTR_ERR(rdev);
+ dev_err(dev, "Regulator registration %s failed: %d\n",
+ rdesc->name, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_regulator_suspend(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask, 0);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, true);
+ if (reg_pdata->suspend_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
+ id);
+ }
+
+ return 0;
+}
+
+static int max77620_regulator_resume(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask,
+ rinfo->remote_sense_mask);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, false);
+ if (reg_pdata->active_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
+ id);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_regulator_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
+ max77620_regulator_resume)
+};
+
+static const struct platform_device_id max77620_regulator_devtype[] = {
+ { .name = "max77620-pmic", },
+ { .name = "max20024-pmic", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
+
+static struct platform_driver max77620_regulator_driver = {
+ .probe = max77620_regulator_probe,
+ .id_table = max77620_regulator_devtype,
+ .driver = {
+ .name = "max77620-pmic",
+ .pm = &max77620_regulator_pm_ops,
+ },
+};
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
+static void __exit max77620_reg_exit(void)
+{
+ platform_driver_unregister(&max77620_regulator_driver);
+}
+module_exit(max77620_reg_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pmic");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [rtc-linux] [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan,
Mallikarjun Kasoju
MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
multiple DCDC and LDOs. This supplies the power to different
components of the system.
Also these rails has configuration for ramp time, flexible
power sequence, slew rate etc.
Add regulator driver to access these rails via regulator APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Refactor Regulator driver to use core API for DT parsing.
- Update based on API changes.
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77620-regulator.c | 892 +++++++++++++++++++++++++++++++++
3 files changed, 902 insertions(+)
create mode 100644 drivers/regulator/max77620-regulator.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8155e80..b92214b 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -343,6 +343,15 @@ config REGULATOR_MAX1586
regulator via I2C bus. The provided regulator is suitable
for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
+config REGULATOR_MAX77620
+ tristate "Maxim 77620/MAX20024 voltage regulator"
+ depends on MFD_MAX77620
+ help
+ This driver controls Maxim MAX77620 voltage output regulator
+ via I2C bus. The provided regulator is suitable for Tegra
+ chip to control Step-Down DC-DC and LDOs. Say Y here to
+ enable the regulator driver.
+
config REGULATOR_MAX8649
tristate "Maxim 8649 voltage regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 980b194..2564c00 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o
obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
+obj-$(CONFIG_REGULATOR_MAX77620) += max77620-regulator.o
obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c
new file mode 100644
index 0000000..97e7572
--- /dev/null
+++ b/drivers/regulator/max77620-regulator.c
@@ -0,0 +1,892 @@
+/*
+ * Maxim MAX77620 Regulator driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/mfd/max77620.h>
+
+#define max77620_rails(_name) "max77620-"#_name
+
+/* Power Mode */
+#define MAX77620_POWER_MODE_NORMAL 3
+#define MAX77620_POWER_MODE_LPM 2
+#define MAX77620_POWER_MODE_GLPM 1
+#define MAX77620_POWER_MODE_DISABLE 0
+
+/* SD Slew Rate */
+#define MAX77620_SD_SR_13_75 0
+#define MAX77620_SD_SR_27_5 1
+#define MAX77620_SD_SR_55 2
+#define MAX77620_SD_SR_100 3
+
+#define MAX77620_FPS_SRC_NUM 3
+
+struct max77620_regulator_info {
+ u8 type;
+ u32 min_uV;
+ u32 max_uV;
+ u32 step_uV;
+ u8 fps_addr;
+ u8 volt_addr;
+ u8 cfg_addr;
+ u8 volt_mask;
+ u8 power_mode_mask;
+ u8 power_mode_shift;
+ u8 remote_sense_addr;
+ u8 remote_sense_mask;
+ struct regulator_desc desc;
+};
+
+struct max77620_regulator_pdata {
+ bool glpm_enable;
+ bool sd_fsrade_disable;
+ bool disable_remote_sense_on_suspend;
+ struct regulator_init_data *reg_idata;
+ int active_fps_src;
+ int active_fps_pd_slot;
+ int active_fps_pu_slot;
+ int suspend_fps_src;
+ int suspend_fps_pd_slot;
+ int suspend_fps_pu_slot;
+ int current_mode;
+};
+
+struct max77620_regulator {
+ struct device *dev;
+ struct max77620_chip *max77620_chip;
+ struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
+ struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
+ struct regulator_desc *rdesc[MAX77620_NUM_REGS];
+ int enable_power_mode[MAX77620_NUM_REGS];
+ int current_power_mode[MAX77620_NUM_REGS];
+ int active_fps_src[MAX77620_NUM_REGS];
+};
+
+#define fps_src_name(fps_src) \
+ (fps_src == FPS_SRC_0 ? "FPS_SRC_0" : \
+ fps_src == FPS_SRC_1 ? "FPS_SRC_1" : \
+ fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
+
+static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+
+ return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+}
+
+static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
+ int fps_src, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ switch (fps_src) {
+ case FPS_SRC_0:
+ case FPS_SRC_1:
+ case FPS_SRC_2:
+ case FPS_SRC_NONE:
+ break;
+
+ case FPS_SRC_DEF:
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+ pmic->active_fps_src[id] = ret;
+ return 0;
+
+ default:
+ dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
+ fps_src, id);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->fps_addr,
+ MAX77620_FPS_SRC_MASK,
+ fps_src << MAX77620_FPS_SRC_SHIFT);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ pmic->active_fps_src[id] = fps_src;
+
+ return 0;
+}
+
+static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
+ int id, bool is_suspend)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ unsigned int val = 0;
+ unsigned int mask = 0;
+ int pu = rpdata->active_fps_pu_slot;
+ int pd = rpdata->active_fps_pd_slot;
+ int ret = 0;
+
+ if (is_suspend) {
+ pu = rpdata->suspend_fps_pu_slot;
+ pd = rpdata->suspend_fps_pd_slot;
+ }
+
+ /* FPS power up period setting */
+ if (pu >= 0) {
+ val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PU_PERIOD_MASK;
+ }
+
+ /* FPS power down period setting */
+ if (pd >= 0) {
+ val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PD_PERIOD_MASK;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(parent, rinfo->fps_addr, mask, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
+ int power_mode, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_update(parent, addr, mask, power_mode << shift);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
+ id, ret);
+ return ret;
+ }
+ pmic->current_power_mode[id] = power_mode;
+
+ return ret;
+}
+
+static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 val, addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_read(parent, addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
+ id, addr, ret);
+ return ret;
+ }
+
+ return (val & mask) >> shift;
+}
+
+static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 rval;
+ int slew_rate;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+
+ slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 13750;
+ break;
+ case 1:
+ slew_rate = 27500;
+ break;
+ case 2:
+ slew_rate = 55000;
+ break;
+ case 3:
+ slew_rate = 100000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ default:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ slew_rate = rval & 0x1;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 100000;
+ break;
+ case 1:
+ slew_rate = 5000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ }
+
+ return 0;
+}
+
+static int max77620_init_sd_fs_trade(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ val = (rpdata->sd_fsrade_disable) ? MAX77620_SD_FSRADE_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FSRADE_MASK, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int ret;
+
+ /* Initialise sd_fstrade */
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_init_sd_fs_trade(pmic, id);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Update power mode */
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->current_power_mode[id] = ret;
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+
+ if (rpdata->active_fps_src == FPS_SRC_DEF) {
+ ret = max77620_regulator_get_fps_src(pmic, id);
+ if (ret < 0)
+ return ret;
+ rpdata->active_fps_src = ret;
+ }
+
+ /* If rails are externally control of FPS then enable it always. */
+ if (rpdata->active_fps_src == FPS_SRC_NONE) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ } else {
+ if (pmic->current_power_mode[id] !=
+ pmic->enable_power_mode[id]) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_regulator_set_fps_slots(pmic, id, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int max77620_regulator_enable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ pmic->enable_power_mode[id], id);
+}
+
+static int max77620_regulator_disable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ MAX77620_POWER_MODE_DISABLE, id);
+}
+
+static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ int ret = 1;
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 1;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ if (ret != MAX77620_POWER_MODE_DISABLE)
+ return 1;
+
+ return 0;
+}
+
+static int max77620_regulator_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ bool fpwm = false;
+ int power_mode;
+ int ret;
+ u8 val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ fpwm = true;
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ if (rpdata->glpm_enable)
+ power_mode = MAX77620_POWER_MODE_GLPM;
+ else
+ power_mode = MAX77620_POWER_MODE_LPM;
+ break;
+
+ default:
+ dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
+ id, mode);
+ return -EINVAL;
+ }
+
+ if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
+ goto skip_fpwm;
+
+ val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FPWM_MASK, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ rpdata->current_mode = mode;
+
+skip_fpwm:
+ ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->enable_power_mode[id] = power_mode;
+
+ return 0;
+}
+
+static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ struct device *parent = pmic->max77620_chip->dev;
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int fpwm = 0;
+ int ret;
+ int pm_mode, reg_mode;
+ u8 val;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return 0;
+
+ pm_mode = ret;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ fpwm = !!(val & MAX77620_SD_FPWM_MASK);
+ }
+
+ switch (pm_mode) {
+ case MAX77620_POWER_MODE_NORMAL:
+ case MAX77620_POWER_MODE_DISABLE:
+ if (fpwm)
+ reg_mode = REGULATOR_MODE_FAST;
+ else
+ reg_mode = REGULATOR_MODE_NORMAL;
+ break;
+ case MAX77620_POWER_MODE_LPM:
+ case MAX77620_POWER_MODE_GLPM:
+ reg_mode = REGULATOR_MODE_IDLE;
+ break;
+ default:
+ return 0;
+ }
+
+ return reg_mode;
+}
+
+static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
+ int ramp_delay)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ int ret, val;
+ u8 mask;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ if (ramp_delay <= 13750)
+ val = 0;
+ else if (ramp_delay <= 27500)
+ val = 1;
+ else if (ramp_delay <= 55000)
+ val = 2;
+ else
+ val = 3;
+ val <<= MAX77620_SD_SR_SHIFT;
+ mask = MAX77620_SD_SR_MASK;
+ } else {
+ if (ramp_delay <= 5000)
+ val = 1;
+ else
+ val = 0;
+ mask = MAX77620_LDO_SLEW_RATE_MASK;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->cfg_addr, mask, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_of_parse_cb(struct device_node *np,
+ const struct regulator_desc *desc,
+ struct regulator_config *config)
+{
+ struct max77620_regulator *pmic = config->driver_data;
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
+ u32 pval;
+ int ret;
+
+ rpdata->glpm_enable = of_property_read_bool(np,
+ "maxim,enable-group-low-power");
+
+ rpdata->sd_fsrade_disable = of_property_read_bool(np,
+ "maxim,disable-active-discharge");
+
+ rpdata->disable_remote_sense_on_suspend = of_property_read_bool(
+ np, "maxim,disable-remote-sense-on-suspend");
+
+ ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
+ rpdata->active_fps_src = (!ret) ? pval : FPS_SRC_DEF;
+
+ ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
+ rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,active-fps-power-down-slot", &pval);
+ rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
+ rpdata->suspend_fps_src = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-up-slot", &pval);
+ rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-down-slot", &pval);
+ rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
+
+ return max77620_init_pmic(pmic, desc->id);
+}
+
+static struct regulator_ops max77620_regulator_ops = {
+ .is_enabled = max77620_regulator_is_enabled,
+ .enable = max77620_regulator_enable,
+ .disable = max77620_regulator_disable,
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .set_mode = max77620_regulator_set_mode,
+ .get_mode = max77620_regulator_get_mode,
+ .set_ramp_delay = max77620_regulator_set_ramp_delay,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+};
+
+#define MAX77620_SD_CNF2_ROVS_EN_NONE 0
+#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
+ _step_uV, _rs_add, _rs_mask) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_SD, \
+ .volt_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = _rs_add, \
+ .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
+ .volt_mask = MAX77620_LDO_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id##_CFG, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG2, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = 0xFF, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_LDO_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id##_CFG, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static int max77620_regulator_probe(struct platform_device *pdev)
+{
+ struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
+ struct max77620_regulator_info *regulator_info;
+ struct device *dev = &pdev->dev;
+ struct regulator_config config = { };
+ struct max77620_regulator *pmic;
+ int ret = 0;
+ int id;
+
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pmic);
+ pmic->max77620_chip = max77620_chip;
+ pmic->dev = dev;
+ if (!dev->of_node)
+ dev->of_node = pdev->dev.parent->of_node;
+
+ regulator_info = (max77620_chip->id == MAX77620) ? max77620_regs_info :
+ max20024_regs_info;
+
+ config.regmap = max77620_chip->rmap;
+ config.dev = dev;
+ config.driver_data = pmic;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ struct regulator_dev *rdev;
+ struct regulator_desc *rdesc;
+
+ if ((max77620_chip->id == MAX77620) &&
+ (id == MAX77620_REGULATOR_ID_SD4))
+ continue;
+
+ rdesc = ®ulator_info[id].desc;
+ pmic->rinfo[id] = &max77620_regs_info[id];
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+ pmic->rdesc[id] = rdesc;
+
+ ret = max77620_read_slew_rate(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+ ret = PTR_ERR(rdev);
+ dev_err(dev, "Regulator registration %s failed: %d\n",
+ rdesc->name, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_regulator_suspend(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask, 0);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, true);
+ if (reg_pdata->suspend_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
+ id);
+ }
+
+ return 0;
+}
+
+static int max77620_regulator_resume(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask,
+ rinfo->remote_sense_mask);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, false);
+ if (reg_pdata->active_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
+ id);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_regulator_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
+ max77620_regulator_resume)
+};
+
+static const struct platform_device_id max77620_regulator_devtype[] = {
+ { .name = "max77620-pmic", },
+ { .name = "max20024-pmic", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
+
+static struct platform_driver max77620_regulator_driver = {
+ .probe = max77620_regulator_probe,
+ .id_table = max77620_regulator_devtype,
+ .driver = {
+ .name = "max77620-pmic",
+ .pm = &max77620_regulator_pm_ops,
+ },
+};
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
+static void __exit max77620_reg_exit(void)
+{
+ platform_driver_unregister(&max77620_regulator_driver);
+}
+module_exit(max77620_reg_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pmic");
+MODULE_LICENSE("GPL v2");
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-14 11:32 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-14 11:32 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linus.walleij, gnurou, lee.jones, broonie, a.zummo,
alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, k.kozlowski, Laxman Dewangan,
Mallikarjun Kasoju
MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
multiple DCDC and LDOs. This supplies the power to different
components of the system.
Also these rails has configuration for ramp time, flexible
power sequence, slew rate etc.
Add regulator driver to access these rails via regulator APIs.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
---
Changes from V1:
- Cleanup code based on comment received on mfd/rtc.
- Avoid duplication on error message.
Changes form V2:
- Run coccicheck and checkpatch in strict mode for the alignment.
- Refactor Regulator driver to use core API for DT parsing.
- Update based on API changes.
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77620-regulator.c | 892 +++++++++++++++++++++++++++++++++
3 files changed, 902 insertions(+)
create mode 100644 drivers/regulator/max77620-regulator.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 8155e80..b92214b 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -343,6 +343,15 @@ config REGULATOR_MAX1586
regulator via I2C bus. The provided regulator is suitable
for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
+config REGULATOR_MAX77620
+ tristate "Maxim 77620/MAX20024 voltage regulator"
+ depends on MFD_MAX77620
+ help
+ This driver controls Maxim MAX77620 voltage output regulator
+ via I2C bus. The provided regulator is suitable for Tegra
+ chip to control Step-Down DC-DC and LDOs. Say Y here to
+ enable the regulator driver.
+
config REGULATOR_MAX8649
tristate "Maxim 8649 voltage regulator"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 980b194..2564c00 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o
obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
+obj-$(CONFIG_REGULATOR_MAX77620) += max77620-regulator.o
obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c
new file mode 100644
index 0000000..97e7572
--- /dev/null
+++ b/drivers/regulator/max77620-regulator.c
@@ -0,0 +1,892 @@
+/*
+ * Maxim MAX77620 Regulator driver
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/mfd/max77620.h>
+
+#define max77620_rails(_name) "max77620-"#_name
+
+/* Power Mode */
+#define MAX77620_POWER_MODE_NORMAL 3
+#define MAX77620_POWER_MODE_LPM 2
+#define MAX77620_POWER_MODE_GLPM 1
+#define MAX77620_POWER_MODE_DISABLE 0
+
+/* SD Slew Rate */
+#define MAX77620_SD_SR_13_75 0
+#define MAX77620_SD_SR_27_5 1
+#define MAX77620_SD_SR_55 2
+#define MAX77620_SD_SR_100 3
+
+#define MAX77620_FPS_SRC_NUM 3
+
+struct max77620_regulator_info {
+ u8 type;
+ u32 min_uV;
+ u32 max_uV;
+ u32 step_uV;
+ u8 fps_addr;
+ u8 volt_addr;
+ u8 cfg_addr;
+ u8 volt_mask;
+ u8 power_mode_mask;
+ u8 power_mode_shift;
+ u8 remote_sense_addr;
+ u8 remote_sense_mask;
+ struct regulator_desc desc;
+};
+
+struct max77620_regulator_pdata {
+ bool glpm_enable;
+ bool sd_fsrade_disable;
+ bool disable_remote_sense_on_suspend;
+ struct regulator_init_data *reg_idata;
+ int active_fps_src;
+ int active_fps_pd_slot;
+ int active_fps_pu_slot;
+ int suspend_fps_src;
+ int suspend_fps_pd_slot;
+ int suspend_fps_pu_slot;
+ int current_mode;
+};
+
+struct max77620_regulator {
+ struct device *dev;
+ struct max77620_chip *max77620_chip;
+ struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
+ struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
+ struct regulator_desc *rdesc[MAX77620_NUM_REGS];
+ int enable_power_mode[MAX77620_NUM_REGS];
+ int current_power_mode[MAX77620_NUM_REGS];
+ int active_fps_src[MAX77620_NUM_REGS];
+};
+
+#define fps_src_name(fps_src) \
+ (fps_src == FPS_SRC_0 ? "FPS_SRC_0" : \
+ fps_src == FPS_SRC_1 ? "FPS_SRC_1" : \
+ fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
+
+static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+
+ return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+}
+
+static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
+ int fps_src, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ switch (fps_src) {
+ case FPS_SRC_0:
+ case FPS_SRC_1:
+ case FPS_SRC_2:
+ case FPS_SRC_NONE:
+ break;
+
+ case FPS_SRC_DEF:
+ ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+ pmic->active_fps_src[id] = ret;
+ return 0;
+
+ default:
+ dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
+ fps_src, id);
+ return -EINVAL;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->fps_addr,
+ MAX77620_FPS_SRC_MASK,
+ fps_src << MAX77620_FPS_SRC_SHIFT);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ pmic->active_fps_src[id] = fps_src;
+
+ return 0;
+}
+
+static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
+ int id, bool is_suspend)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ unsigned int val = 0;
+ unsigned int mask = 0;
+ int pu = rpdata->active_fps_pu_slot;
+ int pd = rpdata->active_fps_pd_slot;
+ int ret = 0;
+
+ if (is_suspend) {
+ pu = rpdata->suspend_fps_pu_slot;
+ pd = rpdata->suspend_fps_pd_slot;
+ }
+
+ /* FPS power up period setting */
+ if (pu >= 0) {
+ val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PU_PERIOD_MASK;
+ }
+
+ /* FPS power down period setting */
+ if (pd >= 0) {
+ val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
+ mask |= MAX77620_FPS_PD_PERIOD_MASK;
+ }
+
+ if (mask) {
+ ret = max77620_reg_update(parent, rinfo->fps_addr, mask, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->fps_addr, ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
+ int power_mode, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_update(parent, addr, mask, power_mode << shift);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
+ id, ret);
+ return ret;
+ }
+ pmic->current_power_mode[id] = power_mode;
+
+ return ret;
+}
+
+static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
+ int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 mask = rinfo->power_mode_mask;
+ u8 shift = rinfo->power_mode_shift;
+ u8 val, addr;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ addr = rinfo->cfg_addr;
+ break;
+ default:
+ addr = rinfo->volt_addr;
+ break;
+ }
+
+ ret = max77620_reg_read(parent, addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
+ id, addr, ret);
+ return ret;
+ }
+
+ return (val & mask) >> shift;
+}
+
+static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 rval;
+ int slew_rate;
+ int ret;
+
+ switch (rinfo->type) {
+ case MAX77620_REGULATOR_TYPE_SD:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+
+ slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 13750;
+ break;
+ case 1:
+ slew_rate = 27500;
+ break;
+ case 2:
+ slew_rate = 55000;
+ break;
+ case 3:
+ slew_rate = 100000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ default:
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ slew_rate = rval & 0x1;
+ switch (slew_rate) {
+ case 0:
+ slew_rate = 100000;
+ break;
+ case 1:
+ slew_rate = 5000;
+ break;
+ }
+ rinfo->desc.ramp_delay = slew_rate;
+ break;
+ }
+
+ return 0;
+}
+
+static int max77620_init_sd_fs_trade(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ u8 val;
+ int ret;
+
+ val = (rpdata->sd_fsrade_disable) ? MAX77620_SD_FSRADE_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FSRADE_MASK, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
+{
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int ret;
+
+ /* Initialise sd_fstrade */
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_init_sd_fs_trade(pmic, id);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Update power mode */
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->current_power_mode[id] = ret;
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+
+ if (rpdata->active_fps_src == FPS_SRC_DEF) {
+ ret = max77620_regulator_get_fps_src(pmic, id);
+ if (ret < 0)
+ return ret;
+ rpdata->active_fps_src = ret;
+ }
+
+ /* If rails are externally control of FPS then enable it always. */
+ if (rpdata->active_fps_src == FPS_SRC_NONE) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ } else {
+ if (pmic->current_power_mode[id] !=
+ pmic->enable_power_mode[id]) {
+ ret = max77620_regulator_set_power_mode(
+ pmic, pmic->enable_power_mode[id], id);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
+ if (ret < 0)
+ return ret;
+
+ ret = max77620_regulator_set_fps_slots(pmic, id, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int max77620_regulator_enable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ pmic->enable_power_mode[id], id);
+}
+
+static int max77620_regulator_disable(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 0;
+
+ return max77620_regulator_set_power_mode(pmic,
+ MAX77620_POWER_MODE_DISABLE, id);
+}
+
+static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ int ret = 1;
+
+ if (pmic->active_fps_src[id] != FPS_SRC_NONE)
+ return 1;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ if (ret != MAX77620_POWER_MODE_DISABLE)
+ return 1;
+
+ return 0;
+}
+
+static int max77620_regulator_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ bool fpwm = false;
+ int power_mode;
+ int ret;
+ u8 val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ fpwm = true;
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ power_mode = MAX77620_POWER_MODE_NORMAL;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ if (rpdata->glpm_enable)
+ power_mode = MAX77620_POWER_MODE_GLPM;
+ else
+ power_mode = MAX77620_POWER_MODE_LPM;
+ break;
+
+ default:
+ dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
+ id, mode);
+ return -EINVAL;
+ }
+
+ if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
+ goto skip_fpwm;
+
+ val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
+ ret = max77620_reg_update(parent, rinfo->cfg_addr,
+ MAX77620_SD_FPWM_MASK, val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ rpdata->current_mode = mode;
+
+skip_fpwm:
+ ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
+ if (ret < 0)
+ return ret;
+
+ pmic->enable_power_mode[id] = power_mode;
+
+ return 0;
+}
+
+static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ struct device *parent = pmic->max77620_chip->dev;
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ int fpwm = 0;
+ int ret;
+ int pm_mode, reg_mode;
+ u8 val;
+
+ ret = max77620_regulator_get_power_mode(pmic, id);
+ if (ret < 0)
+ return 0;
+
+ pm_mode = ret;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ ret = max77620_reg_read(parent, rinfo->cfg_addr, &val);
+ if (ret < 0) {
+ dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
+ rinfo->cfg_addr, ret);
+ return ret;
+ }
+ fpwm = !!(val & MAX77620_SD_FPWM_MASK);
+ }
+
+ switch (pm_mode) {
+ case MAX77620_POWER_MODE_NORMAL:
+ case MAX77620_POWER_MODE_DISABLE:
+ if (fpwm)
+ reg_mode = REGULATOR_MODE_FAST;
+ else
+ reg_mode = REGULATOR_MODE_NORMAL;
+ break;
+ case MAX77620_POWER_MODE_LPM:
+ case MAX77620_POWER_MODE_GLPM:
+ reg_mode = REGULATOR_MODE_IDLE;
+ break;
+ default:
+ return 0;
+ }
+
+ return reg_mode;
+}
+
+static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
+ int ramp_delay)
+{
+ struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
+ int id = rdev_get_id(rdev);
+ struct max77620_regulator_info *rinfo = pmic->rinfo[id];
+ struct device *parent = pmic->max77620_chip->dev;
+ int ret, val;
+ u8 mask;
+
+ if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+ if (ramp_delay <= 13750)
+ val = 0;
+ else if (ramp_delay <= 27500)
+ val = 1;
+ else if (ramp_delay <= 55000)
+ val = 2;
+ else
+ val = 3;
+ val <<= MAX77620_SD_SR_SHIFT;
+ mask = MAX77620_SD_SR_MASK;
+ } else {
+ if (ramp_delay <= 5000)
+ val = 1;
+ else
+ val = 0;
+ mask = MAX77620_LDO_SLEW_RATE_MASK;
+ }
+
+ ret = max77620_reg_update(parent, rinfo->cfg_addr, mask, val);
+ if (ret < 0)
+ dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->cfg_addr, ret);
+
+ return ret;
+}
+
+static int max77620_of_parse_cb(struct device_node *np,
+ const struct regulator_desc *desc,
+ struct regulator_config *config)
+{
+ struct max77620_regulator *pmic = config->driver_data;
+ struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
+ u32 pval;
+ int ret;
+
+ rpdata->glpm_enable = of_property_read_bool(np,
+ "maxim,enable-group-low-power");
+
+ rpdata->sd_fsrade_disable = of_property_read_bool(np,
+ "maxim,disable-active-discharge");
+
+ rpdata->disable_remote_sense_on_suspend = of_property_read_bool(
+ np, "maxim,disable-remote-sense-on-suspend");
+
+ ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
+ rpdata->active_fps_src = (!ret) ? pval : FPS_SRC_DEF;
+
+ ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
+ rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,active-fps-power-down-slot", &pval);
+ rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
+ rpdata->suspend_fps_src = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-up-slot", &pval);
+ rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
+
+ ret = of_property_read_u32(
+ np, "maxim,suspend-fps-power-down-slot", &pval);
+ rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
+
+ return max77620_init_pmic(pmic, desc->id);
+}
+
+static struct regulator_ops max77620_regulator_ops = {
+ .is_enabled = max77620_regulator_is_enabled,
+ .enable = max77620_regulator_enable,
+ .disable = max77620_regulator_disable,
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .set_mode = max77620_regulator_set_mode,
+ .get_mode = max77620_regulator_get_mode,
+ .set_ramp_delay = max77620_regulator_set_ramp_delay,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+};
+
+#define MAX77620_SD_CNF2_ROVS_EN_NONE 0
+#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
+ _step_uV, _rs_add, _rs_mask) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_SD, \
+ .volt_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = _rs_add, \
+ .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
+ [MAX77620_REGULATOR_ID_##_id] = { \
+ .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
+ .volt_mask = MAX77620_LDO_VOLT_MASK, \
+ .volt_addr = MAX77620_REG_##_id##_CFG, \
+ .cfg_addr = MAX77620_REG_##_id##_CFG2, \
+ .fps_addr = MAX77620_REG_FPS_##_id, \
+ .remote_sense_addr = 0xFF, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
+ .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
+ .desc = { \
+ .name = max77620_rails(_name), \
+ .of_match = of_match_ptr(#_name), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .of_parse_cb = max77620_of_parse_cb, \
+ .supply_name = _sname, \
+ .id = MAX77620_REGULATOR_ID_##_id, \
+ .ops = &max77620_regulator_ops, \
+ .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
+ .min_uV = _min_uV, \
+ .uV_step = _step_uV, \
+ .enable_time = 500, \
+ .vsel_mask = MAX77620_LDO_VOLT_MASK, \
+ .vsel_reg = MAX77620_REG_##_id##_CFG, \
+ .type = REGULATOR_VOLTAGE, \
+ }, \
+ }
+
+static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
+ RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
+ RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
+ RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+ RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
+
+ RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
+ RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
+ RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
+ RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
+ RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
+};
+
+static int max77620_regulator_probe(struct platform_device *pdev)
+{
+ struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
+ struct max77620_regulator_info *regulator_info;
+ struct device *dev = &pdev->dev;
+ struct regulator_config config = { };
+ struct max77620_regulator *pmic;
+ int ret = 0;
+ int id;
+
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pmic);
+ pmic->max77620_chip = max77620_chip;
+ pmic->dev = dev;
+ if (!dev->of_node)
+ dev->of_node = pdev->dev.parent->of_node;
+
+ regulator_info = (max77620_chip->id == MAX77620) ? max77620_regs_info :
+ max20024_regs_info;
+
+ config.regmap = max77620_chip->rmap;
+ config.dev = dev;
+ config.driver_data = pmic;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ struct regulator_dev *rdev;
+ struct regulator_desc *rdesc;
+
+ if ((max77620_chip->id == MAX77620) &&
+ (id == MAX77620_REGULATOR_ID_SD4))
+ continue;
+
+ rdesc = ®ulator_info[id].desc;
+ pmic->rinfo[id] = &max77620_regs_info[id];
+ pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
+ pmic->rdesc[id] = rdesc;
+
+ ret = max77620_read_slew_rate(pmic, id);
+ if (ret < 0)
+ return ret;
+
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+ ret = PTR_ERR(rdev);
+ dev_err(dev, "Regulator registration %s failed: %d\n",
+ rdesc->name, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_regulator_suspend(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask, 0);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, true);
+ if (reg_pdata->suspend_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
+ id);
+ }
+
+ return 0;
+}
+
+static int max77620_regulator_resume(struct device *dev)
+{
+ struct max77620_regulator *pmic = dev_get_drvdata(dev);
+ struct max77620_regulator_pdata *reg_pdata;
+ struct max77620_regulator_info *rinfo;
+ struct device *parent = pmic->dev->parent;
+ int id;
+ int ret;
+
+ for (id = 0; id < MAX77620_NUM_REGS; ++id) {
+ reg_pdata = &pmic->reg_pdata[id];
+ rinfo = pmic->rinfo[id];
+ if (!reg_pdata || !rinfo)
+ continue;
+
+ if (reg_pdata->disable_remote_sense_on_suspend &&
+ (rinfo->remote_sense_addr != 0xFF)) {
+ ret = max77620_reg_update(parent,
+ rinfo->remote_sense_addr,
+ rinfo->remote_sense_mask,
+ rinfo->remote_sense_mask);
+ if (ret < 0)
+ dev_err(dev, "Reg 0x%02x update failed: %d\n",
+ rinfo->remote_sense_addr, ret);
+ }
+
+ max77620_regulator_set_fps_slots(pmic, id, false);
+ if (reg_pdata->active_fps_src < 0)
+ continue;
+ max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
+ id);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_regulator_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
+ max77620_regulator_resume)
+};
+
+static const struct platform_device_id max77620_regulator_devtype[] = {
+ { .name = "max77620-pmic", },
+ { .name = "max20024-pmic", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
+
+static struct platform_driver max77620_regulator_driver = {
+ .probe = max77620_regulator_probe,
+ .id_table = max77620_regulator_devtype,
+ .driver = {
+ .name = "max77620-pmic",
+ .pm = &max77620_regulator_pm_ops,
+ },
+};
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
+static void __exit max77620_reg_exit(void)
+{
+ platform_driver_unregister(&max77620_regulator_driver);
+}
+module_exit(max77620_reg_exit);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver");
+MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pmic");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
2016-01-14 11:32 ` Laxman Dewangan
@ 2016-01-19 5:29 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 5:29 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
On 14.01.2016 20:32, Laxman Dewangan wrote:
> MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
> multiple DCDC and LDOs. This supplies the power to different
> components of the system.
> Also these rails has configuration for ramp time, flexible
> power sequence, slew rate etc.
>
> Add regulator driver to access these rails via regulator APIs.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
> ---
> Changes from V1:
> - Cleanup code based on comment received on mfd/rtc.
> - Avoid duplication on error message.
>
> Changes form V2:
> - Run coccicheck and checkpatch in strict mode for the alignment.
> - Refactor Regulator driver to use core API for DT parsing.
> - Update based on API changes.
>
> drivers/regulator/Kconfig | 9 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/max77620-regulator.c | 892 +++++++++++++++++++++++++++++++++
> 3 files changed, 902 insertions(+)
> create mode 100644 drivers/regulator/max77620-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 8155e80..b92214b 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -343,6 +343,15 @@ config REGULATOR_MAX1586
> regulator via I2C bus. The provided regulator is suitable
> for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
>
> +config REGULATOR_MAX77620
> + tristate "Maxim 77620/MAX20024 voltage regulator"
> + depends on MFD_MAX77620
> + help
> + This driver controls Maxim MAX77620 voltage output regulator
> + via I2C bus. The provided regulator is suitable for Tegra
> + chip to control Step-Down DC-DC and LDOs. Say Y here to
> + enable the regulator driver.
> +
> config REGULATOR_MAX8649
> tristate "Maxim 8649 voltage regulator"
> depends on I2C
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 980b194..2564c00 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
> obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o
> obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
> obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
> +obj-$(CONFIG_REGULATOR_MAX77620) += max77620-regulator.o
> obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
> obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
> obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
> diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c
> new file mode 100644
> index 0000000..97e7572
> --- /dev/null
> +++ b/drivers/regulator/max77620-regulator.c
> @@ -0,0 +1,892 @@
> +/*
> + * Maxim MAX77620 Regulator driver
> + *
> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
> + *
> + * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
> + * Laxman Dewangan <ldewangan@nvidia.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/machine.h>
> +#include <linux/regulator/of_regulator.h>
> +#include <linux/regulator/of_regulator.h>
This duplicated header was not present before... something weird is
happening with your patch. :)
> +#include <linux/mfd/max77620.h>
> +
> +#define max77620_rails(_name) "max77620-"#_name
> +
> +/* Power Mode */
> +#define MAX77620_POWER_MODE_NORMAL 3
> +#define MAX77620_POWER_MODE_LPM 2
> +#define MAX77620_POWER_MODE_GLPM 1
> +#define MAX77620_POWER_MODE_DISABLE 0
> +
> +/* SD Slew Rate */
> +#define MAX77620_SD_SR_13_75 0
> +#define MAX77620_SD_SR_27_5 1
> +#define MAX77620_SD_SR_55 2
> +#define MAX77620_SD_SR_100 3
> +
> +#define MAX77620_FPS_SRC_NUM 3
> +
> +struct max77620_regulator_info {
> + u8 type;
> + u32 min_uV;
> + u32 max_uV;
> + u32 step_uV;
> + u8 fps_addr;
> + u8 volt_addr;
> + u8 cfg_addr;
> + u8 volt_mask;
> + u8 power_mode_mask;
> + u8 power_mode_shift;
> + u8 remote_sense_addr;
> + u8 remote_sense_mask;
> + struct regulator_desc desc;
> +};
> +
> +struct max77620_regulator_pdata {
> + bool glpm_enable;
> + bool sd_fsrade_disable;
> + bool disable_remote_sense_on_suspend;
> + struct regulator_init_data *reg_idata;
> + int active_fps_src;
> + int active_fps_pd_slot;
> + int active_fps_pu_slot;
> + int suspend_fps_src;
> + int suspend_fps_pd_slot;
> + int suspend_fps_pu_slot;
> + int current_mode;
> +};
> +
> +struct max77620_regulator {
> + struct device *dev;
> + struct max77620_chip *max77620_chip;
> + struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
> + struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
> + struct regulator_desc *rdesc[MAX77620_NUM_REGS];
> + int enable_power_mode[MAX77620_NUM_REGS];
> + int current_power_mode[MAX77620_NUM_REGS];
> + int active_fps_src[MAX77620_NUM_REGS];
> +};
> +
> +#define fps_src_name(fps_src) \
> + (fps_src == FPS_SRC_0 ? "FPS_SRC_0" : \
> + fps_src == FPS_SRC_1 ? "FPS_SRC_1" : \
> + fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
> +
> +static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
> + int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> +
> + return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
> +}
> +
> +static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
> + int fps_src, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + switch (fps_src) {
> + case FPS_SRC_0:
> + case FPS_SRC_1:
> + case FPS_SRC_2:
> + case FPS_SRC_NONE:
> + break;
> +
> + case FPS_SRC_DEF:
> + ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
> + pmic->active_fps_src[id] = ret;
> + return 0;
> +
> + default:
> + dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
> + fps_src, id);
> + return -EINVAL;
> + }
> +
> + ret = max77620_reg_update(parent, rinfo->fps_addr,
> + MAX77620_FPS_SRC_MASK,
> + fps_src << MAX77620_FPS_SRC_SHIFT);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + pmic->active_fps_src[id] = fps_src;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
> + int id, bool is_suspend)
> +{
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + unsigned int val = 0;
> + unsigned int mask = 0;
> + int pu = rpdata->active_fps_pu_slot;
> + int pd = rpdata->active_fps_pd_slot;
> + int ret = 0;
> +
> + if (is_suspend) {
> + pu = rpdata->suspend_fps_pu_slot;
> + pd = rpdata->suspend_fps_pd_slot;
> + }
> +
> + /* FPS power up period setting */
> + if (pu >= 0) {
> + val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
> + mask |= MAX77620_FPS_PU_PERIOD_MASK;
> + }
> +
> + /* FPS power down period setting */
> + if (pd >= 0) {
> + val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
> + mask |= MAX77620_FPS_PD_PERIOD_MASK;
> + }
> +
> + if (mask) {
> + ret = max77620_reg_update(parent, rinfo->fps_addr, mask, val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
> + int power_mode, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 mask = rinfo->power_mode_mask;
> + u8 shift = rinfo->power_mode_shift;
> + u8 addr;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + addr = rinfo->cfg_addr;
> + break;
> + default:
> + addr = rinfo->volt_addr;
> + break;
> + }
> +
> + ret = max77620_reg_update(parent, addr, mask, power_mode << shift);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
> + id, ret);
> + return ret;
> + }
> + pmic->current_power_mode[id] = power_mode;
> +
> + return ret;
> +}
> +
> +static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
> + int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 mask = rinfo->power_mode_mask;
> + u8 shift = rinfo->power_mode_shift;
> + u8 val, addr;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + addr = rinfo->cfg_addr;
> + break;
> + default:
> + addr = rinfo->volt_addr;
> + break;
> + }
> +
> + ret = max77620_reg_read(parent, addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
> + id, addr, ret);
> + return ret;
> + }
> +
> + return (val & mask) >> shift;
> +}
> +
> +static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 rval;
> + int slew_rate;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> +
> + slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
> + switch (slew_rate) {
> + case 0:
> + slew_rate = 13750;
> + break;
> + case 1:
> + slew_rate = 27500;
> + break;
> + case 2:
> + slew_rate = 55000;
> + break;
> + case 3:
> + slew_rate = 100000;
> + break;
> + }
> + rinfo->desc.ramp_delay = slew_rate;
> + break;
> + default:
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + slew_rate = rval & 0x1;
> + switch (slew_rate) {
> + case 0:
> + slew_rate = 100000;
> + break;
> + case 1:
> + slew_rate = 5000;
> + break;
> + }
> + rinfo->desc.ramp_delay = slew_rate;
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int max77620_init_sd_fs_trade(struct max77620_regulator *pmic, int id)
> +{
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + val = (rpdata->sd_fsrade_disable) ? MAX77620_SD_FSRADE_MASK : 0;
> + ret = max77620_reg_update(parent, rinfo->cfg_addr,
> + MAX77620_SD_FSRADE_MASK, val);
> + if (ret < 0)
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> +
> + return ret;
> +}
> +
> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
> +{
This function seems to be used only from max77620_of_parse_cb(). I would
find easier to read if this was located before definition of
max77620_of_parse_cb(). Can you move it (or you had other idea of
placing algorithm)?
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + int ret;
> +
> + /* Initialise sd_fstrade */
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + ret = max77620_init_sd_fs_trade(pmic, id);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Update power mode */
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + pmic->current_power_mode[id] = ret;
> + pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
> +
> + if (rpdata->active_fps_src == FPS_SRC_DEF) {
> + ret = max77620_regulator_get_fps_src(pmic, id);
> + if (ret < 0)
> + return ret;
> + rpdata->active_fps_src = ret;
> + }
> +
> + /* If rails are externally control of FPS then enable it always. */
> + if (rpdata->active_fps_src == FPS_SRC_NONE) {
> + ret = max77620_regulator_set_power_mode(
> + pmic, pmic->enable_power_mode[id], id);
> + if (ret < 0)
> + return ret;
> + } else {
> + if (pmic->current_power_mode[id] !=
> + pmic->enable_power_mode[id]) {
> + ret = max77620_regulator_set_power_mode(
> + pmic, pmic->enable_power_mode[id], id);
The 'pmic' argument should be after opening parenthesis, not at new line.
> + if (ret < 0)
> + return ret;
> + }
> + }
> +
> + ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
> + if (ret < 0)
> + return ret;
> +
> + ret = max77620_regulator_set_fps_slots(pmic, id, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_enable(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 0;
> +
> + return max77620_regulator_set_power_mode(pmic,
> + pmic->enable_power_mode[id], id);
> +}
> +
> +static int max77620_regulator_disable(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 0;
> +
> + return max77620_regulator_set_power_mode(pmic,
> + MAX77620_POWER_MODE_DISABLE, id);
> +}
> +
> +static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + int ret = 1;
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 1;
> +
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + if (ret != MAX77620_POWER_MODE_DISABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_set_mode(struct regulator_dev *rdev,
> + unsigned int mode)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + bool fpwm = false;
> + int power_mode;
> + int ret;
> + u8 val;
> +
> + switch (mode) {
> + case REGULATOR_MODE_FAST:
> + fpwm = true;
> + power_mode = MAX77620_POWER_MODE_NORMAL;
> + break;
> +
> + case REGULATOR_MODE_NORMAL:
> + power_mode = MAX77620_POWER_MODE_NORMAL;
> + break;
> +
> + case REGULATOR_MODE_IDLE:
> + if (rpdata->glpm_enable)
> + power_mode = MAX77620_POWER_MODE_GLPM;
> + else
> + power_mode = MAX77620_POWER_MODE_LPM;
> + break;
> +
> + default:
> + dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
> + id, mode);
> + return -EINVAL;
> + }
> +
> + if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
> + goto skip_fpwm;
> +
> + val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
> + ret = max77620_reg_update(parent, rinfo->cfg_addr,
> + MAX77620_SD_FPWM_MASK, val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + rpdata->current_mode = mode;
> +
> +skip_fpwm:
> + ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
> + if (ret < 0)
> + return ret;
> +
> + pmic->enable_power_mode[id] = power_mode;
> +
> + return 0;
> +}
> +
> +static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + struct device *parent = pmic->max77620_chip->dev;
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + int fpwm = 0;
> + int ret;
> + int pm_mode, reg_mode;
> + u8 val;
> +
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return 0;
> +
> + pm_mode = ret;
> +
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + fpwm = !!(val & MAX77620_SD_FPWM_MASK);
> + }
> +
> + switch (pm_mode) {
> + case MAX77620_POWER_MODE_NORMAL:
> + case MAX77620_POWER_MODE_DISABLE:
> + if (fpwm)
> + reg_mode = REGULATOR_MODE_FAST;
> + else
> + reg_mode = REGULATOR_MODE_NORMAL;
> + break;
> + case MAX77620_POWER_MODE_LPM:
> + case MAX77620_POWER_MODE_GLPM:
> + reg_mode = REGULATOR_MODE_IDLE;
> + break;
> + default:
> + return 0;
> + }
> +
> + return reg_mode;
> +}
> +
> +static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
> + int ramp_delay)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + int ret, val;
> + u8 mask;
> +
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + if (ramp_delay <= 13750)
> + val = 0;
> + else if (ramp_delay <= 27500)
> + val = 1;
> + else if (ramp_delay <= 55000)
> + val = 2;
> + else
> + val = 3;
> + val <<= MAX77620_SD_SR_SHIFT;
> + mask = MAX77620_SD_SR_MASK;
> + } else {
> + if (ramp_delay <= 5000)
> + val = 1;
> + else
> + val = 0;
> + mask = MAX77620_LDO_SLEW_RATE_MASK;
> + }
> +
> + ret = max77620_reg_update(parent, rinfo->cfg_addr, mask, val);
> + if (ret < 0)
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> +
> + return ret;
> +}
> +
> +static int max77620_of_parse_cb(struct device_node *np,
> + const struct regulator_desc *desc,
> + struct regulator_config *config)
> +{
> + struct max77620_regulator *pmic = config->driver_data;
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
> + u32 pval;
> + int ret;
> +
> + rpdata->glpm_enable = of_property_read_bool(np,
> + "maxim,enable-group-low-power");
> +
> + rpdata->sd_fsrade_disable = of_property_read_bool(np,
> + "maxim,disable-active-discharge");
> +
> + rpdata->disable_remote_sense_on_suspend = of_property_read_bool(
> + np, "maxim,disable-remote-sense-on-suspend");
> +
> + ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
> + rpdata->active_fps_src = (!ret) ? pval : FPS_SRC_DEF;
> +
> + ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
> + rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,active-fps-power-down-slot", &pval);
> + rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
> + rpdata->suspend_fps_src = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,suspend-fps-power-up-slot", &pval);
> + rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,suspend-fps-power-down-slot", &pval);
> + rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
> +
> + return max77620_init_pmic(pmic, desc->id);
> +}
> +
> +static struct regulator_ops max77620_regulator_ops = {
> + .is_enabled = max77620_regulator_is_enabled,
> + .enable = max77620_regulator_enable,
> + .disable = max77620_regulator_disable,
> + .list_voltage = regulator_list_voltage_linear,
> + .map_voltage = regulator_map_voltage_linear,
> + .get_voltage_sel = regulator_get_voltage_sel_regmap,
> + .set_voltage_sel = regulator_set_voltage_sel_regmap,
> + .set_mode = max77620_regulator_set_mode,
> + .get_mode = max77620_regulator_get_mode,
> + .set_ramp_delay = max77620_regulator_set_ramp_delay,
> + .set_voltage_time_sel = regulator_set_voltage_time_sel,
> +};
> +
> +#define MAX77620_SD_CNF2_ROVS_EN_NONE 0
> +#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
> + _step_uV, _rs_add, _rs_mask) \
> + [MAX77620_REGULATOR_ID_##_id] = { \
> + .type = MAX77620_REGULATOR_TYPE_SD, \
> + .volt_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
> + .volt_addr = MAX77620_REG_##_id, \
> + .cfg_addr = MAX77620_REG_##_id##_CFG, \
> + .fps_addr = MAX77620_REG_FPS_##_id, \
> + .remote_sense_addr = _rs_add, \
> + .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
> + .min_uV = _min_uV, \
> + .max_uV = _max_uV, \
> + .step_uV = _step_uV, \
> + .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
> + .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
> + .desc = { \
> + .name = max77620_rails(_name), \
> + .of_match = of_match_ptr(#_name), \
> + .regulators_node = of_match_ptr("regulators"), \
> + .of_parse_cb = max77620_of_parse_cb, \
> + .supply_name = _sname, \
> + .id = MAX77620_REGULATOR_ID_##_id, \
> + .ops = &max77620_regulator_ops, \
> + .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
> + .min_uV = _min_uV, \
> + .uV_step = _step_uV, \
> + .enable_time = 500, \
> + .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
> + .vsel_reg = MAX77620_REG_##_id, \
> + .type = REGULATOR_VOLTAGE, \
> + }, \
> + }
> +
> +#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
> + [MAX77620_REGULATOR_ID_##_id] = { \
> + .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
> + .volt_mask = MAX77620_LDO_VOLT_MASK, \
> + .volt_addr = MAX77620_REG_##_id##_CFG, \
> + .cfg_addr = MAX77620_REG_##_id##_CFG2, \
> + .fps_addr = MAX77620_REG_FPS_##_id, \
> + .remote_sense_addr = 0xFF, \
> + .min_uV = _min_uV, \
> + .max_uV = _max_uV, \
> + .step_uV = _step_uV, \
> + .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
> + .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
> + .desc = { \
> + .name = max77620_rails(_name), \
> + .of_match = of_match_ptr(#_name), \
> + .regulators_node = of_match_ptr("regulators"), \
> + .of_parse_cb = max77620_of_parse_cb, \
> + .supply_name = _sname, \
> + .id = MAX77620_REGULATOR_ID_##_id, \
> + .ops = &max77620_regulator_ops, \
> + .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
> + .min_uV = _min_uV, \
> + .uV_step = _step_uV, \
> + .enable_time = 500, \
> + .vsel_mask = MAX77620_LDO_VOLT_MASK, \
> + .vsel_reg = MAX77620_REG_##_id##_CFG, \
> + .type = REGULATOR_VOLTAGE, \
> + }, \
> + }
> +
> +static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
> + RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
> + RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
> + RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> +
> + RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
> + RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
> + RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
> +};
> +
> +static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
> + RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
> + RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
> + RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> +
> + RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
> + RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
> + RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
> +};
> +
> +static int max77620_regulator_probe(struct platform_device *pdev)
> +{
> + struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
> + struct max77620_regulator_info *regulator_info;
> + struct device *dev = &pdev->dev;
> + struct regulator_config config = { };
> + struct max77620_regulator *pmic;
> + int ret = 0;
> + int id;
> +
> + pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
> + if (!pmic)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, pmic);
> + pmic->max77620_chip = max77620_chip;
> + pmic->dev = dev;
> + if (!dev->of_node)
> + dev->of_node = pdev->dev.parent->of_node;
> +
> + regulator_info = (max77620_chip->id == MAX77620) ? max77620_regs_info :
> + max20024_regs_info;
> +
> + config.regmap = max77620_chip->rmap;
> + config.dev = dev;
> + config.driver_data = pmic;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + struct regulator_dev *rdev;
> + struct regulator_desc *rdesc;
> +
> + if ((max77620_chip->id == MAX77620) &&
> + (id == MAX77620_REGULATOR_ID_SD4))
> + continue;
> +
> + rdesc = ®ulator_info[id].desc;
> + pmic->rinfo[id] = &max77620_regs_info[id];
> + pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
> + pmic->rdesc[id] = rdesc;
> +
> + ret = max77620_read_slew_rate(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + rdev = devm_regulator_register(dev, rdesc, &config);
> + if (IS_ERR(rdev)) {
> + ret = PTR_ERR(rdev);
> + dev_err(dev, "Regulator registration %s failed: %d\n",
> + rdesc->name, ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int max77620_regulator_suspend(struct device *dev)
> +{
> + struct max77620_regulator *pmic = dev_get_drvdata(dev);
> + struct max77620_regulator_pdata *reg_pdata;
> + struct max77620_regulator_info *rinfo;
> + struct device *parent = pmic->dev->parent;
> + int id;
> + int ret;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + reg_pdata = &pmic->reg_pdata[id];
> + rinfo = pmic->rinfo[id];
> + if (!reg_pdata || !rinfo)
> + continue;
> +
> + if (reg_pdata->disable_remote_sense_on_suspend &&
> + (rinfo->remote_sense_addr != 0xFF)) {
> + ret = max77620_reg_update(parent,
> + rinfo->remote_sense_addr,
> + rinfo->remote_sense_mask, 0);
> + if (ret < 0)
> + dev_err(dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->remote_sense_addr, ret);
> + }
> +
> + max77620_regulator_set_fps_slots(pmic, id, true);
> + if (reg_pdata->suspend_fps_src < 0)
> + continue;
> + max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
> + id);
> + }
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_resume(struct device *dev)
> +{
> + struct max77620_regulator *pmic = dev_get_drvdata(dev);
> + struct max77620_regulator_pdata *reg_pdata;
> + struct max77620_regulator_info *rinfo;
> + struct device *parent = pmic->dev->parent;
> + int id;
> + int ret;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + reg_pdata = &pmic->reg_pdata[id];
> + rinfo = pmic->rinfo[id];
> + if (!reg_pdata || !rinfo)
> + continue;
> +
> + if (reg_pdata->disable_remote_sense_on_suspend &&
> + (rinfo->remote_sense_addr != 0xFF)) {
> + ret = max77620_reg_update(parent,
> + rinfo->remote_sense_addr,
> + rinfo->remote_sense_mask,
> + rinfo->remote_sense_mask);
> + if (ret < 0)
> + dev_err(dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->remote_sense_addr, ret);
> + }
> +
> + max77620_regulator_set_fps_slots(pmic, id, false);
> + if (reg_pdata->active_fps_src < 0)
> + continue;
> + max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
> + id);
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops max77620_regulator_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
> + max77620_regulator_resume)
> +};
> +
> +static const struct platform_device_id max77620_regulator_devtype[] = {
> + { .name = "max77620-pmic", },
> + { .name = "max20024-pmic", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
> +
> +static struct platform_driver max77620_regulator_driver = {
> + .probe = max77620_regulator_probe,
> + .id_table = max77620_regulator_devtype,
> + .driver = {
> + .name = "max77620-pmic",
> + .pm = &max77620_regulator_pm_ops,
> + },
> +};
> +
> +static int __init max77620_regulator_init(void)
> +{
> + return platform_driver_register(&max77620_regulator_driver);
> +}
> +subsys_initcall(max77620_regulator_init);
> +
Does it have to be subsys_initcall? Any special requirements for
ordering the drivers? Probe deferring is encouraged instead.
Best Regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* [rtc-linux] Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-19 5:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 5:29 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
On 14.01.2016 20:32, Laxman Dewangan wrote:
> MAXIM Semiconductor's PMIC, MAX77620 and MAX20024 have the
> multiple DCDC and LDOs. This supplies the power to different
> components of the system.
> Also these rails has configuration for ramp time, flexible
> power sequence, slew rate etc.
>
> Add regulator driver to access these rails via regulator APIs.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
> ---
> Changes from V1:
> - Cleanup code based on comment received on mfd/rtc.
> - Avoid duplication on error message.
>
> Changes form V2:
> - Run coccicheck and checkpatch in strict mode for the alignment.
> - Refactor Regulator driver to use core API for DT parsing.
> - Update based on API changes.
>
> drivers/regulator/Kconfig | 9 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/max77620-regulator.c | 892 +++++++++++++++++++++++++++++++++
> 3 files changed, 902 insertions(+)
> create mode 100644 drivers/regulator/max77620-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 8155e80..b92214b 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -343,6 +343,15 @@ config REGULATOR_MAX1586
> regulator via I2C bus. The provided regulator is suitable
> for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
>
> +config REGULATOR_MAX77620
> + tristate "Maxim 77620/MAX20024 voltage regulator"
> + depends on MFD_MAX77620
> + help
> + This driver controls Maxim MAX77620 voltage output regulator
> + via I2C bus. The provided regulator is suitable for Tegra
> + chip to control Step-Down DC-DC and LDOs. Say Y here to
> + enable the regulator driver.
> +
> config REGULATOR_MAX8649
> tristate "Maxim 8649 voltage regulator"
> depends on I2C
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 980b194..2564c00 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
> obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o
> obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
> obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
> +obj-$(CONFIG_REGULATOR_MAX77620) += max77620-regulator.o
> obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
> obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
> obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
> diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c
> new file mode 100644
> index 0000000..97e7572
> --- /dev/null
> +++ b/drivers/regulator/max77620-regulator.c
> @@ -0,0 +1,892 @@
> +/*
> + * Maxim MAX77620 Regulator driver
> + *
> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
> + *
> + * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
> + * Laxman Dewangan <ldewangan@nvidia.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/machine.h>
> +#include <linux/regulator/of_regulator.h>
> +#include <linux/regulator/of_regulator.h>
This duplicated header was not present before... something weird is
happening with your patch. :)
> +#include <linux/mfd/max77620.h>
> +
> +#define max77620_rails(_name) "max77620-"#_name
> +
> +/* Power Mode */
> +#define MAX77620_POWER_MODE_NORMAL 3
> +#define MAX77620_POWER_MODE_LPM 2
> +#define MAX77620_POWER_MODE_GLPM 1
> +#define MAX77620_POWER_MODE_DISABLE 0
> +
> +/* SD Slew Rate */
> +#define MAX77620_SD_SR_13_75 0
> +#define MAX77620_SD_SR_27_5 1
> +#define MAX77620_SD_SR_55 2
> +#define MAX77620_SD_SR_100 3
> +
> +#define MAX77620_FPS_SRC_NUM 3
> +
> +struct max77620_regulator_info {
> + u8 type;
> + u32 min_uV;
> + u32 max_uV;
> + u32 step_uV;
> + u8 fps_addr;
> + u8 volt_addr;
> + u8 cfg_addr;
> + u8 volt_mask;
> + u8 power_mode_mask;
> + u8 power_mode_shift;
> + u8 remote_sense_addr;
> + u8 remote_sense_mask;
> + struct regulator_desc desc;
> +};
> +
> +struct max77620_regulator_pdata {
> + bool glpm_enable;
> + bool sd_fsrade_disable;
> + bool disable_remote_sense_on_suspend;
> + struct regulator_init_data *reg_idata;
> + int active_fps_src;
> + int active_fps_pd_slot;
> + int active_fps_pu_slot;
> + int suspend_fps_src;
> + int suspend_fps_pd_slot;
> + int suspend_fps_pu_slot;
> + int current_mode;
> +};
> +
> +struct max77620_regulator {
> + struct device *dev;
> + struct max77620_chip *max77620_chip;
> + struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
> + struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
> + struct regulator_desc *rdesc[MAX77620_NUM_REGS];
> + int enable_power_mode[MAX77620_NUM_REGS];
> + int current_power_mode[MAX77620_NUM_REGS];
> + int active_fps_src[MAX77620_NUM_REGS];
> +};
> +
> +#define fps_src_name(fps_src) \
> + (fps_src == FPS_SRC_0 ? "FPS_SRC_0" : \
> + fps_src == FPS_SRC_1 ? "FPS_SRC_1" : \
> + fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
> +
> +static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
> + int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> +
> + return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
> +}
> +
> +static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
> + int fps_src, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + switch (fps_src) {
> + case FPS_SRC_0:
> + case FPS_SRC_1:
> + case FPS_SRC_2:
> + case FPS_SRC_NONE:
> + break;
> +
> + case FPS_SRC_DEF:
> + ret = max77620_reg_read(parent, rinfo->fps_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
> + pmic->active_fps_src[id] = ret;
> + return 0;
> +
> + default:
> + dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
> + fps_src, id);
> + return -EINVAL;
> + }
> +
> + ret = max77620_reg_update(parent, rinfo->fps_addr,
> + MAX77620_FPS_SRC_MASK,
> + fps_src << MAX77620_FPS_SRC_SHIFT);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + pmic->active_fps_src[id] = fps_src;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
> + int id, bool is_suspend)
> +{
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + unsigned int val = 0;
> + unsigned int mask = 0;
> + int pu = rpdata->active_fps_pu_slot;
> + int pd = rpdata->active_fps_pd_slot;
> + int ret = 0;
> +
> + if (is_suspend) {
> + pu = rpdata->suspend_fps_pu_slot;
> + pd = rpdata->suspend_fps_pd_slot;
> + }
> +
> + /* FPS power up period setting */
> + if (pu >= 0) {
> + val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
> + mask |= MAX77620_FPS_PU_PERIOD_MASK;
> + }
> +
> + /* FPS power down period setting */
> + if (pd >= 0) {
> + val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
> + mask |= MAX77620_FPS_PD_PERIOD_MASK;
> + }
> +
> + if (mask) {
> + ret = max77620_reg_update(parent, rinfo->fps_addr, mask, val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->fps_addr, ret);
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
> + int power_mode, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 mask = rinfo->power_mode_mask;
> + u8 shift = rinfo->power_mode_shift;
> + u8 addr;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + addr = rinfo->cfg_addr;
> + break;
> + default:
> + addr = rinfo->volt_addr;
> + break;
> + }
> +
> + ret = max77620_reg_update(parent, addr, mask, power_mode << shift);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
> + id, ret);
> + return ret;
> + }
> + pmic->current_power_mode[id] = power_mode;
> +
> + return ret;
> +}
> +
> +static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
> + int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 mask = rinfo->power_mode_mask;
> + u8 shift = rinfo->power_mode_shift;
> + u8 val, addr;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + addr = rinfo->cfg_addr;
> + break;
> + default:
> + addr = rinfo->volt_addr;
> + break;
> + }
> +
> + ret = max77620_reg_read(parent, addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
> + id, addr, ret);
> + return ret;
> + }
> +
> + return (val & mask) >> shift;
> +}
> +
> +static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
> +{
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 rval;
> + int slew_rate;
> + int ret;
> +
> + switch (rinfo->type) {
> + case MAX77620_REGULATOR_TYPE_SD:
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> +
> + slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
> + switch (slew_rate) {
> + case 0:
> + slew_rate = 13750;
> + break;
> + case 1:
> + slew_rate = 27500;
> + break;
> + case 2:
> + slew_rate = 55000;
> + break;
> + case 3:
> + slew_rate = 100000;
> + break;
> + }
> + rinfo->desc.ramp_delay = slew_rate;
> + break;
> + default:
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &rval);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + slew_rate = rval & 0x1;
> + switch (slew_rate) {
> + case 0:
> + slew_rate = 100000;
> + break;
> + case 1:
> + slew_rate = 5000;
> + break;
> + }
> + rinfo->desc.ramp_delay = slew_rate;
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int max77620_init_sd_fs_trade(struct max77620_regulator *pmic, int id)
> +{
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + u8 val;
> + int ret;
> +
> + val = (rpdata->sd_fsrade_disable) ? MAX77620_SD_FSRADE_MASK : 0;
> + ret = max77620_reg_update(parent, rinfo->cfg_addr,
> + MAX77620_SD_FSRADE_MASK, val);
> + if (ret < 0)
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> +
> + return ret;
> +}
> +
> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
> +{
This function seems to be used only from max77620_of_parse_cb(). I would
find easier to read if this was located before definition of
max77620_of_parse_cb(). Can you move it (or you had other idea of
placing algorithm)?
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + int ret;
> +
> + /* Initialise sd_fstrade */
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + ret = max77620_init_sd_fs_trade(pmic, id);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Update power mode */
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + pmic->current_power_mode[id] = ret;
> + pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
> +
> + if (rpdata->active_fps_src == FPS_SRC_DEF) {
> + ret = max77620_regulator_get_fps_src(pmic, id);
> + if (ret < 0)
> + return ret;
> + rpdata->active_fps_src = ret;
> + }
> +
> + /* If rails are externally control of FPS then enable it always. */
> + if (rpdata->active_fps_src == FPS_SRC_NONE) {
> + ret = max77620_regulator_set_power_mode(
> + pmic, pmic->enable_power_mode[id], id);
> + if (ret < 0)
> + return ret;
> + } else {
> + if (pmic->current_power_mode[id] !=
> + pmic->enable_power_mode[id]) {
> + ret = max77620_regulator_set_power_mode(
> + pmic, pmic->enable_power_mode[id], id);
The 'pmic' argument should be after opening parenthesis, not at new line.
> + if (ret < 0)
> + return ret;
> + }
> + }
> +
> + ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
> + if (ret < 0)
> + return ret;
> +
> + ret = max77620_regulator_set_fps_slots(pmic, id, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_enable(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 0;
> +
> + return max77620_regulator_set_power_mode(pmic,
> + pmic->enable_power_mode[id], id);
> +}
> +
> +static int max77620_regulator_disable(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 0;
> +
> + return max77620_regulator_set_power_mode(pmic,
> + MAX77620_POWER_MODE_DISABLE, id);
> +}
> +
> +static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + int ret = 1;
> +
> + if (pmic->active_fps_src[id] != FPS_SRC_NONE)
> + return 1;
> +
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + if (ret != MAX77620_POWER_MODE_DISABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_set_mode(struct regulator_dev *rdev,
> + unsigned int mode)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + bool fpwm = false;
> + int power_mode;
> + int ret;
> + u8 val;
> +
> + switch (mode) {
> + case REGULATOR_MODE_FAST:
> + fpwm = true;
> + power_mode = MAX77620_POWER_MODE_NORMAL;
> + break;
> +
> + case REGULATOR_MODE_NORMAL:
> + power_mode = MAX77620_POWER_MODE_NORMAL;
> + break;
> +
> + case REGULATOR_MODE_IDLE:
> + if (rpdata->glpm_enable)
> + power_mode = MAX77620_POWER_MODE_GLPM;
> + else
> + power_mode = MAX77620_POWER_MODE_LPM;
> + break;
> +
> + default:
> + dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
> + id, mode);
> + return -EINVAL;
> + }
> +
> + if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
> + goto skip_fpwm;
> +
> + val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
> + ret = max77620_reg_update(parent, rinfo->cfg_addr,
> + MAX77620_SD_FPWM_MASK, val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + rpdata->current_mode = mode;
> +
> +skip_fpwm:
> + ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
> + if (ret < 0)
> + return ret;
> +
> + pmic->enable_power_mode[id] = power_mode;
> +
> + return 0;
> +}
> +
> +static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + struct device *parent = pmic->max77620_chip->dev;
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + int fpwm = 0;
> + int ret;
> + int pm_mode, reg_mode;
> + u8 val;
> +
> + ret = max77620_regulator_get_power_mode(pmic, id);
> + if (ret < 0)
> + return 0;
> +
> + pm_mode = ret;
> +
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + ret = max77620_reg_read(parent, rinfo->cfg_addr, &val);
> + if (ret < 0) {
> + dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
> + rinfo->cfg_addr, ret);
> + return ret;
> + }
> + fpwm = !!(val & MAX77620_SD_FPWM_MASK);
> + }
> +
> + switch (pm_mode) {
> + case MAX77620_POWER_MODE_NORMAL:
> + case MAX77620_POWER_MODE_DISABLE:
> + if (fpwm)
> + reg_mode = REGULATOR_MODE_FAST;
> + else
> + reg_mode = REGULATOR_MODE_NORMAL;
> + break;
> + case MAX77620_POWER_MODE_LPM:
> + case MAX77620_POWER_MODE_GLPM:
> + reg_mode = REGULATOR_MODE_IDLE;
> + break;
> + default:
> + return 0;
> + }
> +
> + return reg_mode;
> +}
> +
> +static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
> + int ramp_delay)
> +{
> + struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> + struct max77620_regulator_info *rinfo = pmic->rinfo[id];
> + struct device *parent = pmic->max77620_chip->dev;
> + int ret, val;
> + u8 mask;
> +
> + if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
> + if (ramp_delay <= 13750)
> + val = 0;
> + else if (ramp_delay <= 27500)
> + val = 1;
> + else if (ramp_delay <= 55000)
> + val = 2;
> + else
> + val = 3;
> + val <<= MAX77620_SD_SR_SHIFT;
> + mask = MAX77620_SD_SR_MASK;
> + } else {
> + if (ramp_delay <= 5000)
> + val = 1;
> + else
> + val = 0;
> + mask = MAX77620_LDO_SLEW_RATE_MASK;
> + }
> +
> + ret = max77620_reg_update(parent, rinfo->cfg_addr, mask, val);
> + if (ret < 0)
> + dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->cfg_addr, ret);
> +
> + return ret;
> +}
> +
> +static int max77620_of_parse_cb(struct device_node *np,
> + const struct regulator_desc *desc,
> + struct regulator_config *config)
> +{
> + struct max77620_regulator *pmic = config->driver_data;
> + struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
> + u32 pval;
> + int ret;
> +
> + rpdata->glpm_enable = of_property_read_bool(np,
> + "maxim,enable-group-low-power");
> +
> + rpdata->sd_fsrade_disable = of_property_read_bool(np,
> + "maxim,disable-active-discharge");
> +
> + rpdata->disable_remote_sense_on_suspend = of_property_read_bool(
> + np, "maxim,disable-remote-sense-on-suspend");
> +
> + ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
> + rpdata->active_fps_src = (!ret) ? pval : FPS_SRC_DEF;
> +
> + ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
> + rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,active-fps-power-down-slot", &pval);
> + rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
> + rpdata->suspend_fps_src = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,suspend-fps-power-up-slot", &pval);
> + rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
> +
> + ret = of_property_read_u32(
> + np, "maxim,suspend-fps-power-down-slot", &pval);
> + rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
> +
> + return max77620_init_pmic(pmic, desc->id);
> +}
> +
> +static struct regulator_ops max77620_regulator_ops = {
> + .is_enabled = max77620_regulator_is_enabled,
> + .enable = max77620_regulator_enable,
> + .disable = max77620_regulator_disable,
> + .list_voltage = regulator_list_voltage_linear,
> + .map_voltage = regulator_map_voltage_linear,
> + .get_voltage_sel = regulator_get_voltage_sel_regmap,
> + .set_voltage_sel = regulator_set_voltage_sel_regmap,
> + .set_mode = max77620_regulator_set_mode,
> + .get_mode = max77620_regulator_get_mode,
> + .set_ramp_delay = max77620_regulator_set_ramp_delay,
> + .set_voltage_time_sel = regulator_set_voltage_time_sel,
> +};
> +
> +#define MAX77620_SD_CNF2_ROVS_EN_NONE 0
> +#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
> + _step_uV, _rs_add, _rs_mask) \
> + [MAX77620_REGULATOR_ID_##_id] = { \
> + .type = MAX77620_REGULATOR_TYPE_SD, \
> + .volt_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
> + .volt_addr = MAX77620_REG_##_id, \
> + .cfg_addr = MAX77620_REG_##_id##_CFG, \
> + .fps_addr = MAX77620_REG_FPS_##_id, \
> + .remote_sense_addr = _rs_add, \
> + .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
> + .min_uV = _min_uV, \
> + .max_uV = _max_uV, \
> + .step_uV = _step_uV, \
> + .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
> + .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
> + .desc = { \
> + .name = max77620_rails(_name), \
> + .of_match = of_match_ptr(#_name), \
> + .regulators_node = of_match_ptr("regulators"), \
> + .of_parse_cb = max77620_of_parse_cb, \
> + .supply_name = _sname, \
> + .id = MAX77620_REGULATOR_ID_##_id, \
> + .ops = &max77620_regulator_ops, \
> + .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
> + .min_uV = _min_uV, \
> + .uV_step = _step_uV, \
> + .enable_time = 500, \
> + .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
> + .vsel_reg = MAX77620_REG_##_id, \
> + .type = REGULATOR_VOLTAGE, \
> + }, \
> + }
> +
> +#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
> + [MAX77620_REGULATOR_ID_##_id] = { \
> + .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
> + .volt_mask = MAX77620_LDO_VOLT_MASK, \
> + .volt_addr = MAX77620_REG_##_id##_CFG, \
> + .cfg_addr = MAX77620_REG_##_id##_CFG2, \
> + .fps_addr = MAX77620_REG_FPS_##_id, \
> + .remote_sense_addr = 0xFF, \
> + .min_uV = _min_uV, \
> + .max_uV = _max_uV, \
> + .step_uV = _step_uV, \
> + .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
> + .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
> + .desc = { \
> + .name = max77620_rails(_name), \
> + .of_match = of_match_ptr(#_name), \
> + .regulators_node = of_match_ptr("regulators"), \
> + .of_parse_cb = max77620_of_parse_cb, \
> + .supply_name = _sname, \
> + .id = MAX77620_REGULATOR_ID_##_id, \
> + .ops = &max77620_regulator_ops, \
> + .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
> + .min_uV = _min_uV, \
> + .uV_step = _step_uV, \
> + .enable_time = 500, \
> + .vsel_mask = MAX77620_LDO_VOLT_MASK, \
> + .vsel_reg = MAX77620_REG_##_id##_CFG, \
> + .type = REGULATOR_VOLTAGE, \
> + }, \
> + }
> +
> +static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
> + RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
> + RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
> + RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> +
> + RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
> + RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
> + RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
> +};
> +
> +static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
> + RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
> + RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
> + RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> + RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
> +
> + RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
> + RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
> + RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
> + RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
> + RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
> +};
> +
> +static int max77620_regulator_probe(struct platform_device *pdev)
> +{
> + struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
> + struct max77620_regulator_info *regulator_info;
> + struct device *dev = &pdev->dev;
> + struct regulator_config config = { };
> + struct max77620_regulator *pmic;
> + int ret = 0;
> + int id;
> +
> + pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
> + if (!pmic)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, pmic);
> + pmic->max77620_chip = max77620_chip;
> + pmic->dev = dev;
> + if (!dev->of_node)
> + dev->of_node = pdev->dev.parent->of_node;
> +
> + regulator_info = (max77620_chip->id == MAX77620) ? max77620_regs_info :
> + max20024_regs_info;
> +
> + config.regmap = max77620_chip->rmap;
> + config.dev = dev;
> + config.driver_data = pmic;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + struct regulator_dev *rdev;
> + struct regulator_desc *rdesc;
> +
> + if ((max77620_chip->id == MAX77620) &&
> + (id == MAX77620_REGULATOR_ID_SD4))
> + continue;
> +
> + rdesc = ®ulator_info[id].desc;
> + pmic->rinfo[id] = &max77620_regs_info[id];
> + pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
> + pmic->rdesc[id] = rdesc;
> +
> + ret = max77620_read_slew_rate(pmic, id);
> + if (ret < 0)
> + return ret;
> +
> + rdev = devm_regulator_register(dev, rdesc, &config);
> + if (IS_ERR(rdev)) {
> + ret = PTR_ERR(rdev);
> + dev_err(dev, "Regulator registration %s failed: %d\n",
> + rdesc->name, ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int max77620_regulator_suspend(struct device *dev)
> +{
> + struct max77620_regulator *pmic = dev_get_drvdata(dev);
> + struct max77620_regulator_pdata *reg_pdata;
> + struct max77620_regulator_info *rinfo;
> + struct device *parent = pmic->dev->parent;
> + int id;
> + int ret;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + reg_pdata = &pmic->reg_pdata[id];
> + rinfo = pmic->rinfo[id];
> + if (!reg_pdata || !rinfo)
> + continue;
> +
> + if (reg_pdata->disable_remote_sense_on_suspend &&
> + (rinfo->remote_sense_addr != 0xFF)) {
> + ret = max77620_reg_update(parent,
> + rinfo->remote_sense_addr,
> + rinfo->remote_sense_mask, 0);
> + if (ret < 0)
> + dev_err(dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->remote_sense_addr, ret);
> + }
> +
> + max77620_regulator_set_fps_slots(pmic, id, true);
> + if (reg_pdata->suspend_fps_src < 0)
> + continue;
> + max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
> + id);
> + }
> +
> + return 0;
> +}
> +
> +static int max77620_regulator_resume(struct device *dev)
> +{
> + struct max77620_regulator *pmic = dev_get_drvdata(dev);
> + struct max77620_regulator_pdata *reg_pdata;
> + struct max77620_regulator_info *rinfo;
> + struct device *parent = pmic->dev->parent;
> + int id;
> + int ret;
> +
> + for (id = 0; id < MAX77620_NUM_REGS; ++id) {
> + reg_pdata = &pmic->reg_pdata[id];
> + rinfo = pmic->rinfo[id];
> + if (!reg_pdata || !rinfo)
> + continue;
> +
> + if (reg_pdata->disable_remote_sense_on_suspend &&
> + (rinfo->remote_sense_addr != 0xFF)) {
> + ret = max77620_reg_update(parent,
> + rinfo->remote_sense_addr,
> + rinfo->remote_sense_mask,
> + rinfo->remote_sense_mask);
> + if (ret < 0)
> + dev_err(dev, "Reg 0x%02x update failed: %d\n",
> + rinfo->remote_sense_addr, ret);
> + }
> +
> + max77620_regulator_set_fps_slots(pmic, id, false);
> + if (reg_pdata->active_fps_src < 0)
> + continue;
> + max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
> + id);
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops max77620_regulator_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
> + max77620_regulator_resume)
> +};
> +
> +static const struct platform_device_id max77620_regulator_devtype[] = {
> + { .name = "max77620-pmic", },
> + { .name = "max20024-pmic", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
> +
> +static struct platform_driver max77620_regulator_driver = {
> + .probe = max77620_regulator_probe,
> + .id_table = max77620_regulator_devtype,
> + .driver = {
> + .name = "max77620-pmic",
> + .pm = &max77620_regulator_pm_ops,
> + },
> +};
> +
> +static int __init max77620_regulator_init(void)
> +{
> + return platform_driver_register(&max77620_regulator_driver);
> +}
> +subsys_initcall(max77620_regulator_init);
> +
Does it have to be subsys_initcall? Any special requirements for
ordering the drivers? Probe deferring is encouraged instead.
Best Regards,
Krzysztof
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^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
2016-01-19 5:29 ` [rtc-linux] " Krzysztof Kozlowski
(?)
@ 2016-01-19 7:04 ` Laxman Dewangan
-1 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-19 7:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
Thanks for review.
Here is my view on the some of the review comment.
On Tuesday 19 January 2016 10:59 AM, Krzysztof Kozlowski wrote:
> On 14.01.2016 20:32, Laxman Dewangan wrote:
> + return ret;
> +}
> +
> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
> +{
> This function seems to be used only from max77620_of_parse_cb(). I would
> find easier to read if this was located before definition of
> max77620_of_parse_cb(). Can you move it (or you had other idea of
> placing algorithm)?
I wanted to keep all local function on top which is used on this file
and not the regulator ops.
Then implement regulator ops and then probe.
Let me see if I can do anything here.
>
>> + pmic->enable_power_mode[id]) {
>> + ret = max77620_regulator_set_power_mode(
>> + pmic, pmic->enable_power_mode[id], id);
> The 'pmic' argument should be after opening parenthesis, not at new line.
This is done for indenting alignment. I am using checkpatch --strict
option and for this the next line should be on same column of first
charcter after opening parenthesis.
To avoid this error, if we want to re-align the indenting for next line
then left the line empty after "(".
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
> Does it have to be subsys_initcall? Any special requirements for
> ordering the drivers? Probe deferring is encouraged instead.
>
>
This is to make sure th regulators are ready before other driver get
probed. This is basic need of some of driver and hence subsys_initcall.
I will move to module_init() as some of other PMIC driver (as3722) is in
the module init and used in tegra platform so not seeing much issue on this.
^ permalink raw reply [flat|nested] 32+ messages in thread* [rtc-linux] Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-19 7:04 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-19 7:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
Thanks for review.
Here is my view on the some of the review comment.
On Tuesday 19 January 2016 10:59 AM, Krzysztof Kozlowski wrote:
> On 14.01.2016 20:32, Laxman Dewangan wrote:
> + return ret;
> +}
> +
> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
> +{
> This function seems to be used only from max77620_of_parse_cb(). I would
> find easier to read if this was located before definition of
> max77620_of_parse_cb(). Can you move it (or you had other idea of
> placing algorithm)?
I wanted to keep all local function on top which is used on this file
and not the regulator ops.
Then implement regulator ops and then probe.
Let me see if I can do anything here.
>
>> + pmic->enable_power_mode[id]) {
>> + ret = max77620_regulator_set_power_mode(
>> + pmic, pmic->enable_power_mode[id], id);
> The 'pmic' argument should be after opening parenthesis, not at new line.
This is done for indenting alignment. I am using checkpatch --strict
option and for this the next line should be on same column of first
charcter after opening parenthesis.
To avoid this error, if we want to re-align the indenting for next line
then left the line empty after "(".
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
> Does it have to be subsys_initcall? Any special requirements for
> ordering the drivers? Probe deferring is encouraged instead.
>
>
This is to make sure th regulators are ready before other driver get
probed. This is basic need of some of driver and hence subsys_initcall.
I will move to module_init() as some of other PMIC driver (as3722) is in
the module init and used in tegra platform so not seeing much issue on this.
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^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-19 7:04 ` Laxman Dewangan
0 siblings, 0 replies; 32+ messages in thread
From: Laxman Dewangan @ 2016-01-19 7:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
Thanks for review.
Here is my view on the some of the review comment.
On Tuesday 19 January 2016 10:59 AM, Krzysztof Kozlowski wrote:
> On 14.01.2016 20:32, Laxman Dewangan wrote:
> + return ret;
> +}
> +
> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
> +{
> This function seems to be used only from max77620_of_parse_cb(). I would
> find easier to read if this was located before definition of
> max77620_of_parse_cb(). Can you move it (or you had other idea of
> placing algorithm)?
I wanted to keep all local function on top which is used on this file
and not the regulator ops.
Then implement regulator ops and then probe.
Let me see if I can do anything here.
>
>> + pmic->enable_power_mode[id]) {
>> + ret = max77620_regulator_set_power_mode(
>> + pmic, pmic->enable_power_mode[id], id);
> The 'pmic' argument should be after opening parenthesis, not at new line.
This is done for indenting alignment. I am using checkpatch --strict
option and for this the next line should be on same column of first
charcter after opening parenthesis.
To avoid this error, if we want to re-align the indenting for next line
then left the line empty after "(".
+
+static int __init max77620_regulator_init(void)
+{
+ return platform_driver_register(&max77620_regulator_driver);
+}
+subsys_initcall(max77620_regulator_init);
+
> Does it have to be subsys_initcall? Any special requirements for
> ordering the drivers? Probe deferring is encouraged instead.
>
>
This is to make sure th regulators are ready before other driver get
probed. This is basic need of some of driver and hence subsys_initcall.
I will move to module_init() as some of other PMIC driver (as3722) is in
the module init and used in tegra platform so not seeing much issue on this.
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
2016-01-19 7:04 ` Laxman Dewangan
@ 2016-01-19 7:26 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 7:26 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
On 19.01.2016 16:04, Laxman Dewangan wrote:
> Thanks for review.
> Here is my view on the some of the review comment.
>
> On Tuesday 19 January 2016 10:59 AM, Krzysztof Kozlowski wrote:
>> On 14.01.2016 20:32, Laxman Dewangan wrote:
>
>> + return ret;
>> +}
>> +
>> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
>> +{
>> This function seems to be used only from max77620_of_parse_cb(). I would
>> find easier to read if this was located before definition of
>> max77620_of_parse_cb(). Can you move it (or you had other idea of
>> placing algorithm)?
>
> I wanted to keep all local function on top which is used on this file
> and not the regulator ops.
> Then implement regulator ops and then probe.
> Let me see if I can do anything here.
Ah, OK then. That kind of order makes sense as well.
>
>>
>>> + pmic->enable_power_mode[id]) {
>>> + ret = max77620_regulator_set_power_mode(
>>> + pmic, pmic->enable_power_mode[id], id);
>> The 'pmic' argument should be after opening parenthesis, not at new line.
>
> This is done for indenting alignment. I am using checkpatch --strict
> option and for this the next line should be on same column of first
> charcter after opening parenthesis.
> To avoid this error, if we want to re-align the indenting for next line
> then left the line empty after "(".
But the next line is not aligned with the function call. So the 'strict'
is not followed and the code is less readable. Instead this should be
something like:
+ ret = max77620_regulator_set_power_mode(pmic
+ pmic->enable_power_mode[id],
id);
You cannot align it with function call anyway (to many indentations and
too long name of function).
>
> +
> +static int __init max77620_regulator_init(void)
> +{
> + return platform_driver_register(&max77620_regulator_driver);
> +}
> +subsys_initcall(max77620_regulator_init);
> +
>
>> Does it have to be subsys_initcall? Any special requirements for
>> ordering the drivers? Probe deferring is encouraged instead.
>>
>>
>
>
> This is to make sure th regulators are ready before other driver get
> probed. This is basic need of some of driver and hence subsys_initcall.
> I will move to module_init() as some of other PMIC driver (as3722) is in
> the module init and used in tegra platform so not seeing much issue on
> this.
The other driver should support deferred probe and then the problem is
somehow solved. There are some rare cases when this does not work yet
but then please describe exactly which driver cannot work with it.
For example max77802 regulator works well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* [rtc-linux] Re: [PATCH V3 5/5] regulator: max77620: add regulator driver for max77620/max20024
@ 2016-01-19 7:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-19 7:26 UTC (permalink / raw)
To: Laxman Dewangan, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linus.walleij, gnurou, lee.jones, broonie,
a.zummo, alexandre.belloni
Cc: lgirdwood, devicetree, linux-kernel, linux-gpio, rtc-linux,
swarren, treding, Mallikarjun Kasoju
On 19.01.2016 16:04, Laxman Dewangan wrote:
> Thanks for review.
> Here is my view on the some of the review comment.
>
> On Tuesday 19 January 2016 10:59 AM, Krzysztof Kozlowski wrote:
>> On 14.01.2016 20:32, Laxman Dewangan wrote:
>
>> + return ret;
>> +}
>> +
>> +static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
>> +{
>> This function seems to be used only from max77620_of_parse_cb(). I would
>> find easier to read if this was located before definition of
>> max77620_of_parse_cb(). Can you move it (or you had other idea of
>> placing algorithm)?
>
> I wanted to keep all local function on top which is used on this file
> and not the regulator ops.
> Then implement regulator ops and then probe.
> Let me see if I can do anything here.
Ah, OK then. That kind of order makes sense as well.
>
>>
>>> + pmic->enable_power_mode[id]) {
>>> + ret = max77620_regulator_set_power_mode(
>>> + pmic, pmic->enable_power_mode[id], id);
>> The 'pmic' argument should be after opening parenthesis, not at new line.
>
> This is done for indenting alignment. I am using checkpatch --strict
> option and for this the next line should be on same column of first
> charcter after opening parenthesis.
> To avoid this error, if we want to re-align the indenting for next line
> then left the line empty after "(".
But the next line is not aligned with the function call. So the 'strict'
is not followed and the code is less readable. Instead this should be
something like:
+ ret = max77620_regulator_set_power_mode(pmic
+ pmic->enable_power_mode[id],
id);
You cannot align it with function call anyway (to many indentations and
too long name of function).
>
> +
> +static int __init max77620_regulator_init(void)
> +{
> + return platform_driver_register(&max77620_regulator_driver);
> +}
> +subsys_initcall(max77620_regulator_init);
> +
>
>> Does it have to be subsys_initcall? Any special requirements for
>> ordering the drivers? Probe deferring is encouraged instead.
>>
>>
>
>
> This is to make sure th regulators are ready before other driver get
> probed. This is basic need of some of driver and hence subsys_initcall.
> I will move to module_init() as some of other PMIC driver (as3722) is in
> the module init and used in tegra platform so not seeing much issue on
> this.
The other driver should support deferred probe and then the problem is
somehow solved. There are some rare cases when this does not work yet
but then please describe exactly which driver cannot work with it.
For example max77802 regulator works well.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 32+ messages in thread