[PATCH 0/2] crypto: caam - performance fixes/improvements

[PATCH 0/2] crypto: caam - performance fixes/improvements

[Horia Geantă]

The following patches increase/fix CAAM performance by modifying
the configuration of MCFGR (Master Configuration Register):
-1st patch fixes a ~ 5% performance drop on PPC platforms
-2nd patch improves performance in some use cases, since CAAM DMA
transfers are optimized


Note: AWCACHE[0] (AXI3 "bufferable") and AWCACHE[1] (AXI3 "cacheable")
are set irrespective of platform, since:
-for ARM-based SoCs: the interconnect IP ignores AWCACHE[0]
-for PPC-based SoCs: PAMU handles coherency control, not AWCACHE[1]

Horia Geantă (2):
  crypto: caam - make write transactions bufferable on PPC platforms
  crypto: caam - enable LARGE_BURST for enhancing DMA transactions size

 drivers/crypto/caam/ctrl.c | 4 ++--
 drivers/crypto/caam/regs.h | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

-- 
2.4.4

[PATCH 1/2] crypto: caam - make write transactions bufferable on PPC platforms

[Horia Geantă]

Previous change (see "Fixes" tag) to the MCFGR register
clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).

This makes all writes non-bufferable, causing a ~ 5% performance drop
for PPC-based platforms.

Rework previous change such that MCFGR[AWCACHE]=4'b0011
(bufferable + cacheable) for all platforms.
Note: For ARM-based platforms, AWCACHE[0] is ignored
by the interconnect IP.

Fixes: f10967495144 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
 drivers/crypto/caam/ctrl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 8abb4bc548cc..69d4a1326fee 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev)
 	 * long pointers in master configuration register
 	 */
 	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
-		      MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
-					MCFGR_LONG_PTR : 0));
+		      MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
+		      (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 
 	/*
 	 *  Read the Compile Time paramters and SCFGR to determine
-- 
2.4.4

[PATCH v2 1/2] crypto: caam - make write transactions bufferable on PPC platforms

[Horia Geantă]

Previous change (see "Fixes" tag) to the MCFGR register
clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).

This makes all writes non-bufferable, causing a ~ 5% performance drop
for PPC-based platforms.

Rework previous change such that MCFGR[AWCACHE]=4'b0011
(bufferable + cacheable) for all platforms.
Note: For ARM-based platforms, AWCACHE[0] is ignored
by the interconnect IP.

Cc: <stable@vger.kernel.org> # 4.3+
Fixes: f10967495144 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---

v2: Cc-ed stable.

 drivers/crypto/caam/ctrl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 8abb4bc548cc..69d4a1326fee 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev)
 	 * long pointers in master configuration register
 	 */
 	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
-		      MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
-					MCFGR_LONG_PTR : 0));
+		      MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
+		      (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 
 	/*
 	 *  Read the Compile Time paramters and SCFGR to determine
-- 
2.4.4

Re: [PATCH v2 1/2] crypto: caam - make write transactions bufferable on PPC platforms

[Herbert Xu]

On Tue, Jan 12, 2016 at 05:59:29PM +0200, Horia Geantă wrote:
> Previous change (see "Fixes" tag) to the MCFGR register
> clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).
> 
> This makes all writes non-bufferable, causing a ~ 5% performance drop
> for PPC-based platforms.
> 
> Rework previous change such that MCFGR[AWCACHE]=4'b0011
> (bufferable + cacheable) for all platforms.
> Note: For ARM-based platforms, AWCACHE[0] is ignored
> by the interconnect IP.
> 
> Cc: <stable@vger.kernel.org> # 4.3+
> Fixes: f10967495144 ("crypto: caam - fix snooping for write transactions")
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

Patch applied.  Thanks!
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

[PATCH 2/2] crypto: caam - enable LARGE_BURST for enhancing DMA transactions size

[Horia Geantă]

Increasing CAAM DMA engine transaction size either
-reduces the number of required transactions or
-adds the ability to transfer more data with same transaction count

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
 drivers/crypto/caam/ctrl.c | 2 +-
 drivers/crypto/caam/regs.h | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 69d4a1326fee..44d30b45f3cc 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -534,7 +534,7 @@ static int caam_probe(struct platform_device *pdev)
 	 * long pointers in master configuration register
 	 */
 	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
-		      MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
+		      MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 		      (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 
 	/*
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index a8a79975682f..0ba9c40597dc 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -455,7 +455,8 @@ struct caam_ctrl {
 #define MCFGR_AXIPIPE_MASK	(0xf << MCFGR_AXIPIPE_SHIFT)
 
 #define MCFGR_AXIPRI		0x00000008 /* Assert AXI priority sideband */
-#define MCFGR_BURST_64		0x00000001 /* Max burst size */
+#define MCFGR_LARGE_BURST	0x00000004 /* 128/256-byte burst size */
+#define MCFGR_BURST_64		0x00000001 /* 64-byte burst size */
 
 /* JRSTART register offsets */
 #define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
-- 
2.4.4

Re: [PATCH 2/2] crypto: caam - enable LARGE_BURST for enhancing DMA transactions size

[Herbert Xu]

On Tue, Jan 12, 2016 at 05:14:10PM +0200, Horia Geantă wrote:
> Increasing CAAM DMA engine transaction size either
> -reduces the number of required transactions or
> -adds the ability to transfer more data with same transaction count
> 
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

Applied.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH 0/2] crypto: caam - performance fixes/improvements

[Horia Ioan Geanta Neag]

On 1/12/2016 5:14 PM, Horia Geantă wrote:
> The following patches increase/fix CAAM performance by modifying
> the configuration of MCFGR (Master Configuration Register):
> -1st patch fixes a ~ 5% performance drop on PPC platforms
> -2nd patch improves performance in some use cases, since CAAM DMA
> transfers are optimized
> 
> 
> Note: AWCACHE[0] (AXI3 "bufferable") and AWCACHE[1] (AXI3 "cacheable")
> are set irrespective of platform, since:
> -for ARM-based SoCs: the interconnect IP ignores AWCACHE[0]
> -for PPC-based SoCs: PAMU handles coherency control, not AWCACHE[1]
> 
> Horia Geantă (2):
>   crypto: caam - make write transactions bufferable on PPC platforms
>   crypto: caam - enable LARGE_BURST for enhancing DMA transactions size

Herbert, I see that you've sent the crypto fixes for 4.5 pull request.
Any reason why these patches were not included?
I was expecting at least the first one to get it, it's even Cc-ing stable.

Thanks,
Horia

Re: [PATCH 0/2] crypto: caam - performance fixes/improvements

[Herbert Xu]

On Fri, Jan 22, 2016 at 04:52:36PM +0000, Horia Ioan Geanta Neag wrote:
> Herbert, I see that you've sent the crypto fixes for 4.5 pull request.
> Any reason why these patches were not included?
> I was expecting at least the first one to get it, it's even Cc-ing stable.

Well the second patch is definitely too late for 4.5. In future
please don't bundle patches together unless they are all obviously
critical bug fixes or they may all be postponed to the next merge
window.

I'll look at the first patch again.

Cheers,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt