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* [PATCH v4 0/6] Check pixel clock when setting mode
@ 2016-02-02 13:16 Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check Mika Kahola
                   ` (8 more replies)
  0 siblings, 9 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview

'cvt 2560 1600 60' gives

# 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync

where pixel clock 348.50 MHz is higher than the supported 304 MHz.

The missing mode validity checks for DisplayPort, HDMI, DP-MST, SDVO, CRT, and TV.

V2:
- The maximum DOT clock frequency is added to debugfs i915_frequency_info.
- max dotclock cached in dev_priv structure
- moved computation of max dotclock to 'intel_display.c'

V3:
- intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
- for GEN9 and above the max dotclock frequency is equal to CD clock
  frequency
- for older generations the dot clock frequency is limited to 90% of the
  CD clock frequency
- For Cherryview the dot clock is limited to 95% of CD clock frequency
- for GEN2/3 the maximum dot clock frequency is limited to 90% of the
  2X CD clock frequency as we have on option to use double wide mode
- cleanup

V4:
- renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
  caused changes to all patches in my series even though some of them has
  been r-b'd by Ville
- for consistency the max_pixclk variable is renamed as max_dotclk throughout
  the whole series

Mika Kahola (6):
  drm/i915: DisplayPort pixel clock check
  drm/i915: HDMI pixel clock check
  drm/i915: DisplayPort-MST pixel clock check
  drm/i915: SDVO pixel clock check
  drm/i915: CRT pixel clock check
  drm/i915: TV pixel clock check

 drivers/gpu/drm/i915/intel_crt.c    | 4 ++++
 drivers/gpu/drm/i915/intel_dp.c     | 3 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
 drivers/gpu/drm/i915/intel_hdmi.c   | 8 ++++++++
 drivers/gpu/drm/i915/intel_sdvo.c   | 4 ++++
 drivers/gpu/drm/i915/intel_tv.c     | 4 ++++
 6 files changed, 27 insertions(+), 1 deletion(-)

-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 2/6] drm/i915: HDMI " Mika Kahola
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort.

V2:
- removed computation for max DOT clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f44aba1..396d1a1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -203,6 +203,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
@@ -220,7 +221,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
 
-	if (mode_rate > max_rate)
+	if (mode_rate > max_rate || target_clock > max_dotclk)
 		return MODE_CLOCK_HIGH;
 
 	if (mode->clock < 10000)
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 2/6] drm/i915: HDMI pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 3/6] drm/i915: DisplayPort-MST " Mika Kahola
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to HDMI.

V2:
- removed computation for max dot clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk
- check for stereo mode added

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8698a64..edb7e90 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1202,11 +1202,19 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 	enum drm_mode_status status;
 	int clock;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
 	clock = mode->clock;
+
+	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
+		clock *= 2;
+
+	if (clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock *= 2;
 
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 3/6] drm/i915: DisplayPort-MST pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 2/6] drm/i915: HDMI " Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 4/6] drm/i915: SDVO " Mika Kahola
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort MST.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 2a2ab30..a2bd698 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -371,6 +371,8 @@ static enum drm_mode_status
 intel_dp_mst_mode_valid(struct drm_connector *connector,
 			struct drm_display_mode *mode)
 {
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
 	/* TODO - validate mode against available PBN for link */
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
@@ -378,6 +380,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return MODE_H_ILLEGAL;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 4/6] drm/i915: SDVO pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (2 preceding siblings ...)
  2016-02-02 13:16 ` [PATCH v4 3/6] drm/i915: DisplayPort-MST " Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 5/6] drm/i915: CRT " Mika Kahola
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to SDVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 2e1da06..4ecc076 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1527,6 +1527,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
 {
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -1537,6 +1538,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 	if (intel_sdvo->pixel_clock_max < mode->clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	if (intel_sdvo->is_lvds) {
 		if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
 			return MODE_PANEL;
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 5/6] drm/i915: CRT pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (3 preceding siblings ...)
  2016-02-02 13:16 ` [PATCH v4 4/6] drm/i915: SDVO " Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:16 ` [PATCH v4 6/6] drm/i915: TV " Mika Kahola
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to CRT.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9c89df1..ad5dfab 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -216,6 +216,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = connector->dev;
+	int max_dotclk = to_i915(dev)->max_dotclk_freq;
 
 	int max_clock = 0;
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -231,6 +232,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
 	if (mode->clock > max_clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 	if (HAS_PCH_LPT(dev) &&
 	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v4 6/6] drm/i915: TV pixel clock check
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (4 preceding siblings ...)
  2016-02-02 13:16 ` [PATCH v4 5/6] drm/i915: CRT " Mika Kahola
@ 2016-02-02 13:16 ` Mika Kahola
  2016-02-02 13:44 ` ✓ Fi.CI.BAT: success for Check pixel clock when setting mode Patchwork
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Mika Kahola @ 2016-02-02 13:16 UTC (permalink / raw)
  To: intel-gfx

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to TV.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_tv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 948cbff..eeb4e3c 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -897,6 +897,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
 {
 	struct intel_tv *intel_tv = intel_attached_tv(connector);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
 
 	/* Ensure TV refresh is close to desired refresh */
 	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
-- 
1.9.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* ✓ Fi.CI.BAT: success for Check pixel clock when setting mode
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (5 preceding siblings ...)
  2016-02-02 13:16 ` [PATCH v4 6/6] drm/i915: TV " Mika Kahola
@ 2016-02-02 13:44 ` Patchwork
  2016-02-02 16:25 ` [PATCH v4 0/6] " Ville Syrjälä
  2016-02-11  9:20 ` Daniel Vetter
  8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2016-02-02 13:44 UTC (permalink / raw)
  To: Mika Kahola; +Cc: intel-gfx

== Summary ==

Series 3009v1 Check pixel clock when setting mode
http://patchwork.freedesktop.org/api/1.0/series/3009/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b-frame-sequence:
                dmesg-warn -> PASS       (skl-i5k-2)
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> PASS       (byt-nuc)

bdw-nuci7        total:156  pass:147  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:159  pass:147  dwarn:0   dfail:0   fail:0   skip:12 
bsw-nuc-2        total:159  pass:129  dwarn:0   dfail:0   fail:0   skip:30 
byt-nuc          total:159  pass:136  dwarn:0   dfail:0   fail:0   skip:23 
hsw-brixbox      total:159  pass:146  dwarn:0   dfail:0   fail:0   skip:13 
hsw-gt2          total:159  pass:149  dwarn:0   dfail:0   fail:0   skip:10 
hsw-xps12        total:156  pass:146  dwarn:0   dfail:0   fail:0   skip:10 
ilk-hp8440p      total:159  pass:111  dwarn:0   dfail:0   fail:0   skip:48 
ivb-t430s        total:159  pass:145  dwarn:0   dfail:0   fail:0   skip:14 
skl-i5k-2        total:159  pass:144  dwarn:1   dfail:0   fail:0   skip:14 
snb-dellxps      total:159  pass:137  dwarn:0   dfail:0   fail:0   skip:22 
snb-x220t        total:159  pass:137  dwarn:0   dfail:0   fail:1   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1342/

5d3deb0902a962218ad9b0e583e4d1bbdec29f9a drm-intel-nightly: 2016y-02m-01d-20h-05m-03s UTC integration manifest
a20919f8e17f365c8bc956fa0080f85ec2fc8613 drm/i915: TV pixel clock check
4ffb8a33501e94e3019b7823f6b607d2b4673755 drm/i915: CRT pixel clock check
1171c10d097e10362eb0c317c8c1f01d3d6da7d8 drm/i915: SDVO pixel clock check
aa4c8b657b332610ba2a0599aecf93353f73d8ab drm/i915: DisplayPort-MST pixel clock check
22bee8570e2ab9bd5db75d87a8f2bd6ea66c56f6 drm/i915: HDMI pixel clock check
5c53160f762743864cad2770e86f29185decb074 drm/i915: DisplayPort pixel clock check

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 0/6] Check pixel clock when setting mode
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (6 preceding siblings ...)
  2016-02-02 13:44 ` ✓ Fi.CI.BAT: success for Check pixel clock when setting mode Patchwork
@ 2016-02-02 16:25 ` Ville Syrjälä
  2016-02-11  9:16   ` Daniel Vetter
  2016-02-11  9:20 ` Daniel Vetter
  8 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2016-02-02 16:25 UTC (permalink / raw)
  To: Mika Kahola; +Cc: intel-gfx

On Tue, Feb 02, 2016 at 03:16:37PM +0200, Mika Kahola wrote:
> From EDID we can read and request higher pixel clock than
> our HW can support. This set of patches add checks if
> requested pixel clock is lower than the one supported by the HW.
> The requested mode is discarded if we cannot support the requested
> pixel clock. For example for Cherryview
> 
> 'cvt 2560 1600 60' gives
> 
> # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> 
> where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> 
> The missing mode validity checks for DisplayPort, HDMI, DP-MST, SDVO, CRT, and TV.
> 
> V2:
> - The maximum DOT clock frequency is added to debugfs i915_frequency_info.
> - max dotclock cached in dev_priv structure
> - moved computation of max dotclock to 'intel_display.c'
> 
> V3:
> - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> - for GEN9 and above the max dotclock frequency is equal to CD clock
>   frequency
> - for older generations the dot clock frequency is limited to 90% of the
>   CD clock frequency
> - For Cherryview the dot clock is limited to 95% of CD clock frequency
> - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
>   2X CD clock frequency as we have on option to use double wide mode
> - cleanup
> 
> V4:
> - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
>   caused changes to all patches in my series even though some of them has
>   been r-b'd by Ville
> - for consistency the max_pixclk variable is renamed as max_dotclk throughout
>   the whole series
> 
> Mika Kahola (6):
>   drm/i915: DisplayPort pixel clock check
>   drm/i915: HDMI pixel clock check
>   drm/i915: DisplayPort-MST pixel clock check
>   drm/i915: SDVO pixel clock check
>   drm/i915: CRT pixel clock check
>   drm/i915: TV pixel clock check

I think I've r-b'd these in the past, but just in case I had another
look and it still looks OK to me. So, for the series:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now, apparently there are some actual bugs out there that could be
fixed by this. Eg:
https://bugzilla.redhat.com/show_bug.cgi?id=1279797

We had one bug in fdo too, but somehow that got closed before we added
any of the relevant checks. I think it was this one:
https://bugs.freedesktop.org/show_bug.cgi?id=85621

I'd be tempted to put cc:stable on this stuff actually, to get those
bugs fixed. Looks max_dotclock_freq got merged in 4.4 so we can't
backport beyond that.

> 
>  drivers/gpu/drm/i915/intel_crt.c    | 4 ++++
>  drivers/gpu/drm/i915/intel_dp.c     | 3 ++-
>  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
>  drivers/gpu/drm/i915/intel_hdmi.c   | 8 ++++++++
>  drivers/gpu/drm/i915/intel_sdvo.c   | 4 ++++
>  drivers/gpu/drm/i915/intel_tv.c     | 4 ++++
>  6 files changed, 27 insertions(+), 1 deletion(-)
> 
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 0/6] Check pixel clock when setting mode
  2016-02-02 16:25 ` [PATCH v4 0/6] " Ville Syrjälä
@ 2016-02-11  9:16   ` Daniel Vetter
  0 siblings, 0 replies; 12+ messages in thread
From: Daniel Vetter @ 2016-02-11  9:16 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Tue, Feb 02, 2016 at 06:25:39PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 02, 2016 at 03:16:37PM +0200, Mika Kahola wrote:
> > From EDID we can read and request higher pixel clock than
> > our HW can support. This set of patches add checks if
> > requested pixel clock is lower than the one supported by the HW.
> > The requested mode is discarded if we cannot support the requested
> > pixel clock. For example for Cherryview
> > 
> > 'cvt 2560 1600 60' gives
> > 
> > # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> > Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> > 
> > where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> > 
> > The missing mode validity checks for DisplayPort, HDMI, DP-MST, SDVO, CRT, and TV.
> > 
> > V2:
> > - The maximum DOT clock frequency is added to debugfs i915_frequency_info.
> > - max dotclock cached in dev_priv structure
> > - moved computation of max dotclock to 'intel_display.c'
> > 
> > V3:
> > - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> > - for GEN9 and above the max dotclock frequency is equal to CD clock
> >   frequency
> > - for older generations the dot clock frequency is limited to 90% of the
> >   CD clock frequency
> > - For Cherryview the dot clock is limited to 95% of CD clock frequency
> > - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
> >   2X CD clock frequency as we have on option to use double wide mode
> > - cleanup
> > 
> > V4:
> > - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
> >   caused changes to all patches in my series even though some of them has
> >   been r-b'd by Ville
> > - for consistency the max_pixclk variable is renamed as max_dotclk throughout
> >   the whole series
> > 
> > Mika Kahola (6):
> >   drm/i915: DisplayPort pixel clock check
> >   drm/i915: HDMI pixel clock check
> >   drm/i915: DisplayPort-MST pixel clock check
> >   drm/i915: SDVO pixel clock check
> >   drm/i915: CRT pixel clock check
> >   drm/i915: TV pixel clock check
> 
> I think I've r-b'd these in the past, but just in case I had another
> look and it still looks OK to me. So, for the series:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now, apparently there are some actual bugs out there that could be
> fixed by this. Eg:
> https://bugzilla.redhat.com/show_bug.cgi?id=1279797
> 
> We had one bug in fdo too, but somehow that got closed before we added
> any of the relevant checks. I think it was this one:
> https://bugs.freedesktop.org/show_bug.cgi?id=85621
> 
> I'd be tempted to put cc:stable on this stuff actually, to get those
> bugs fixed. Looks max_dotclock_freq got merged in 4.4 so we can't
> backport beyond that.

Hm, I was less risky, so pushed them all to dinq without cc: something.
We'll see how it goes, and can cherry-pick later on.
-Daniel

> 
> > 
> >  drivers/gpu/drm/i915/intel_crt.c    | 4 ++++
> >  drivers/gpu/drm/i915/intel_dp.c     | 3 ++-
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
> >  drivers/gpu/drm/i915/intel_hdmi.c   | 8 ++++++++
> >  drivers/gpu/drm/i915/intel_sdvo.c   | 4 ++++
> >  drivers/gpu/drm/i915/intel_tv.c     | 4 ++++
> >  6 files changed, 27 insertions(+), 1 deletion(-)
> > 
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 0/6] Check pixel clock when setting mode
  2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
                   ` (7 preceding siblings ...)
  2016-02-02 16:25 ` [PATCH v4 0/6] " Ville Syrjälä
@ 2016-02-11  9:20 ` Daniel Vetter
  2016-02-11 12:36   ` Kahola, Mika
  8 siblings, 1 reply; 12+ messages in thread
From: Daniel Vetter @ 2016-02-11  9:20 UTC (permalink / raw)
  To: Mika Kahola; +Cc: intel-gfx

On Tue, Feb 02, 2016 at 03:16:37PM +0200, Mika Kahola wrote:
> From EDID we can read and request higher pixel clock than
> our HW can support. This set of patches add checks if
> requested pixel clock is lower than the one supported by the HW.
> The requested mode is discarded if we cannot support the requested
> pixel clock. For example for Cherryview
> 
> 'cvt 2560 1600 60' gives
> 
> # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> 
> where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> 
> The missing mode validity checks for DisplayPort, HDMI, DP-MST, SDVO, CRT, and TV.
> 
> V2:
> - The maximum DOT clock frequency is added to debugfs i915_frequency_info.
> - max dotclock cached in dev_priv structure
> - moved computation of max dotclock to 'intel_display.c'
> 
> V3:
> - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> - for GEN9 and above the max dotclock frequency is equal to CD clock
>   frequency
> - for older generations the dot clock frequency is limited to 90% of the
>   CD clock frequency
> - For Cherryview the dot clock is limited to 95% of CD clock frequency
> - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
>   2X CD clock frequency as we have on option to use double wide mode
> - cleanup
> 
> V4:
> - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
>   caused changes to all patches in my series even though some of them has
>   been r-b'd by Ville
> - for consistency the max_pixclk variable is renamed as max_dotclk throughout
>   the whole series
> 
> Mika Kahola (6):
>   drm/i915: DisplayPort pixel clock check
>   drm/i915: HDMI pixel clock check
>   drm/i915: DisplayPort-MST pixel clock check
>   drm/i915: SDVO pixel clock check
>   drm/i915: CRT pixel clock check
>   drm/i915: TV pixel clock check

Note that the title of your series is wrong I think - mode_valid is _only_
called at probe time, to filter the list of modes userspace can see.
Userspace can still try to set a mode not in that list which would be
above that dotclk. From a quick look around I don't see that addressed
anywhere.

If that's true then I think we also need an igt which exercises this code
by trying to set a dotclock that's way too high (but for a resolution that
the display actually supports).
-Daniel


> 
>  drivers/gpu/drm/i915/intel_crt.c    | 4 ++++
>  drivers/gpu/drm/i915/intel_dp.c     | 3 ++-
>  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
>  drivers/gpu/drm/i915/intel_hdmi.c   | 8 ++++++++
>  drivers/gpu/drm/i915/intel_sdvo.c   | 4 ++++
>  drivers/gpu/drm/i915/intel_tv.c     | 4 ++++
>  6 files changed, 27 insertions(+), 1 deletion(-)
> 
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v4 0/6] Check pixel clock when setting mode
  2016-02-11  9:20 ` Daniel Vetter
@ 2016-02-11 12:36   ` Kahola, Mika
  0 siblings, 0 replies; 12+ messages in thread
From: Kahola, Mika @ 2016-02-11 12:36 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: intel-gfx

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Thursday, February 11, 2016 11:21 AM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 0/6] Check pixel clock when setting mode
> 
> On Tue, Feb 02, 2016 at 03:16:37PM +0200, Mika Kahola wrote:
> > From EDID we can read and request higher pixel clock than our HW can
> > support. This set of patches add checks if requested pixel clock is
> > lower than the one supported by the HW.
> > The requested mode is discarded if we cannot support the requested
> > pixel clock. For example for Cherryview
> >
> > 'cvt 2560 1600 60' gives
> >
> > # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> > Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603
> > 1609 1658 -hsync +vsync
> >
> > where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> >
> > The missing mode validity checks for DisplayPort, HDMI, DP-MST, SDVO,
> CRT, and TV.
> >
> > V2:
> > - The maximum DOT clock frequency is added to debugfs
> i915_frequency_info.
> > - max dotclock cached in dev_priv structure
> > - moved computation of max dotclock to 'intel_display.c'
> >
> > V3:
> > - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> > - for GEN9 and above the max dotclock frequency is equal to CD clock
> >   frequency
> > - for older generations the dot clock frequency is limited to 90% of the
> >   CD clock frequency
> > - For Cherryview the dot clock is limited to 95% of CD clock frequency
> > - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
> >   2X CD clock frequency as we have on option to use double wide mode
> > - cleanup
> >
> > V4:
> > - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
> >   caused changes to all patches in my series even though some of them has
> >   been r-b'd by Ville
> > - for consistency the max_pixclk variable is renamed as max_dotclk
> throughout
> >   the whole series
> >
> > Mika Kahola (6):
> >   drm/i915: DisplayPort pixel clock check
> >   drm/i915: HDMI pixel clock check
> >   drm/i915: DisplayPort-MST pixel clock check
> >   drm/i915: SDVO pixel clock check
> >   drm/i915: CRT pixel clock check
> >   drm/i915: TV pixel clock check
> 
> Note that the title of your series is wrong I think - mode_valid is _only_ called
> at probe time, to filter the list of modes userspace can see.
> Userspace can still try to set a mode not in that list which would be above
> that dotclk. From a quick look around I don't see that addressed anywhere.
> 
Indeed, the title is a bit misleading as the mode is checked at probe time. 

> If that's true then I think we also need an igt which exercises this code by
> trying to set a dotclock that's way too high (but for a resolution that the
> display actually supports).
Let's put this on my to-do list

Cheers,
Mika

> -Daniel
> 
> 
> >
> >  drivers/gpu/drm/i915/intel_crt.c    | 4 ++++
> >  drivers/gpu/drm/i915/intel_dp.c     | 3 ++-
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
> >  drivers/gpu/drm/i915/intel_hdmi.c   | 8 ++++++++
> >  drivers/gpu/drm/i915/intel_sdvo.c   | 4 ++++
> >  drivers/gpu/drm/i915/intel_tv.c     | 4 ++++
> >  6 files changed, 27 insertions(+), 1 deletion(-)
> >
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2016-02-11 12:36 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-02 13:16 [PATCH v4 0/6] Check pixel clock when setting mode Mika Kahola
2016-02-02 13:16 ` [PATCH v4 1/6] drm/i915: DisplayPort pixel clock check Mika Kahola
2016-02-02 13:16 ` [PATCH v4 2/6] drm/i915: HDMI " Mika Kahola
2016-02-02 13:16 ` [PATCH v4 3/6] drm/i915: DisplayPort-MST " Mika Kahola
2016-02-02 13:16 ` [PATCH v4 4/6] drm/i915: SDVO " Mika Kahola
2016-02-02 13:16 ` [PATCH v4 5/6] drm/i915: CRT " Mika Kahola
2016-02-02 13:16 ` [PATCH v4 6/6] drm/i915: TV " Mika Kahola
2016-02-02 13:44 ` ✓ Fi.CI.BAT: success for Check pixel clock when setting mode Patchwork
2016-02-02 16:25 ` [PATCH v4 0/6] " Ville Syrjälä
2016-02-11  9:16   ` Daniel Vetter
2016-02-11  9:20 ` Daniel Vetter
2016-02-11 12:36   ` Kahola, Mika

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