[RFC v5 00/15] MIPS: ath79: AR9331: add devicetree support

[RFC v5 00/15] MIPS: ath79: AR9331: add devicetree support

[Antony Pavlov]

This patchseries relies on additonal USB support and appended DTB handling
patches by Alban Bedel:

  * https://patchwork.linux-mips.org/patch/11497/
  * https://patchwork.linux-mips.org/patch/11495/

  * MIPS: OF: Rework the appended DTB handling to keep the PROM arguments
    https://github.com/AlbanBedel/linux/commit/3e1bb5db49a9da1d5d9c90d345fd114f00596c19

  * MIPS: ath79: Add support for DTB passed using the UHI boot protocol
    https://github.com/AlbanBedel/linux/commit/b0229b82f84c3e054308eb481d0f4a782fc8ac41

  * MIPS: ath79: Remove the builtin DTB support
    https://github.com/AlbanBedel/linux/commit/0b8843b069e525db690c253e03b7a15bc1d1f0df

Changes since RFC v4:

  * AR3132-related patches are postponed;
  * drivers/clk/clk-ath79.c is rewritten;
  * DPTechnics DPT-Module board support is added;
  * TP-LINK MR3020 USB support is added;
  * gpio polled keys support is added for all boards;
  * appended DTB is used, so now we can use single vmlinux.bin
    image for all boards.

Changes since RFC v3:

  * clk: get pll registers base address from devicetree node
  * MIPS: dts: qca: ar9132: use short references for usb too
  * MIPS: dts: qca: ar9331: add usb support
  * MIPS: ath79: Dragino MS14: enable usb support

Changes since RFC v2:

  * add Onion Omega board support;
  * add AR9132 SoC clock driver;
  * add AR9132 devicetree fixes.

Changes since RFC v1:

  * add Dragino MS14 board support;
  * add "ref" oscillator input clock for pll-controller;
    add necessary nodes to board dts files.


Antony Pavlov (15):
  WIP: clk: add Atheros AR933X SoCs clock driver
  dt-bindings: clock: qca,ath79-pll: fix copy-paste typos
  MIPS: ath79: use clk-ath79.c driver for AR933X
  WIP: MIPS: ath79: setup.c: disable platform code for OF boards
  MIPS: dts: qca: introduce AR9331 devicetree
  MIPS: ath79: add initial support for TP-LINK MR3020
  usb: ehci: add vbus-gpio parameter
  MIPS: tl_mr3020: enable usb support
  devicetree: add Dragino vendor id
  MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)
  devicetree: add Onion Corporation vendor id
  MIPS: ath79: add initial support for Onion Omega
  devicetree: add DPTechnics vendor id
  MIPS: ath79: add DPT-Module support
  WIP: MIPS: ath79: add AR9331 devicetree defconfig

 .../devicetree/bindings/clock/qca,ath79-pll.txt    |   4 +-
 .../devicetree/bindings/vendor-prefixes.txt        |   3 +
 arch/mips/ath79/clock.c                            |   6 +-
 arch/mips/ath79/setup.c                            |  17 +-
 arch/mips/boot/dts/qca/Makefile                    |   4 +
 arch/mips/boot/dts/qca/ar9331.dtsi                 | 157 +++++++++
 arch/mips/boot/dts/qca/dpt_module.dts              |  77 +++++
 arch/mips/boot/dts/qca/dragino_ms14.dts            | 101 ++++++
 arch/mips/boot/dts/qca/omega.dts                   |  77 +++++
 arch/mips/boot/dts/qca/tl_mr3020.dts               | 108 +++++++
 arch/mips/configs/ar9331-dt-raw_defconfig          | 100 ++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-ath79.c                            | 354 +++++++++++++++++++++
 drivers/usb/host/ehci-platform.c                   |  22 ++
 include/dt-bindings/clock/ath79-clk.h              |  22 ++
 15 files changed, 1041 insertions(+), 12 deletions(-)
 create mode 100644 arch/mips/boot/dts/qca/ar9331.dtsi
 create mode 100644 arch/mips/boot/dts/qca/dpt_module.dts
 create mode 100644 arch/mips/boot/dts/qca/dragino_ms14.dts
 create mode 100644 arch/mips/boot/dts/qca/omega.dts
 create mode 100644 arch/mips/boot/dts/qca/tl_mr3020.dts
 create mode 100644 arch/mips/configs/ar9331-dt-raw_defconfig
 create mode 100644 drivers/clk/clk-ath79.c
 create mode 100644 include/dt-bindings/clock/ath79-clk.h

-- 
2.7.0

[RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Antony Pavlov]

This driver can be easely upgraded for other Atheros
SoCs (e.g. AR724X/AR913X) support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 drivers/clk/Makefile                  |   1 +
 drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/ath79-clk.h |  22 +++
 3 files changed, 377 insertions(+)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..d7ad50e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ endif
 # hardware specific clock types
 # please keep this section sorted lexicographically by file/directory path name
 obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
+obj-$(CONFIG_ATH79)			+= clk-ath79.o
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
 obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
 obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
new file mode 100644
index 0000000..e899d31
--- /dev/null
+++ b/drivers/clk/clk-ath79.c
@@ -0,0 +1,354 @@
+/*
+ * Clock driver for Atheros AR933X SoCs
+ *
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This driver is based on Ingenic CGU linux driver by Paul Burton
+ * and AR9331 barebox driver by Antony Pavlov.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/ath79-clk.h>
+
+#include "asm/mach-ath79/ar71xx_regs.h"
+
+struct ath79_pll_info {
+	u32 div_shift;
+	u32 div_mask;
+};
+
+struct ath79_cblk;
+
+/**
+ * struct ath79_clk_info - information about a clock
+ * @name: name of the clock
+ * @type: a bitmask formed from ATH79_CLK_* values
+ * @parents: an index of parent of this clock
+ *           within the clock_info array, or -1
+ *           which correspond to no valid parent
+ * @pll: information valid if type includes ATH79_CLK_PLL
+ */
+struct ath79_clk_info {
+	const char *name;
+
+	enum {
+		ATH79_CLK_NONE		= 0,
+		ATH79_CLK_EXT		= 1,
+		ATH79_CLK_PLL		= 2,
+		ATH79_CLK_ALIAS		= 3,
+	} type;
+
+	struct ath79_cblk *cblk;
+	int parent;
+
+	struct ath79_pll_info pll;
+};
+
+struct ath79_cblk {
+	struct device_node *np;
+	void __iomem *base;
+
+	const struct ath79_clk_info *clock_info;
+	struct clk_onecell_data clocks;
+};
+
+/**
+ * struct ath79_clk - private data for a clock
+ * @hw: see Documentation/clk.txt
+ * @cblk: a pointer to the cblk data
+ * @idx: the index of this clock cblk->clock_info
+ * @pll: information valid if type includes ATH79_CLK_PLL
+ */
+struct ath79_clk {
+	struct clk_hw hw;
+	struct ath79_cblk *cblk;
+	unsigned idx;
+};
+
+#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
+
+static const struct ath79_clk_info ar9331_clocks[] = {
+
+	/* External clock */
+	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
+
+	[ATH79_CLK_CPU] = {
+		"cpu", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_DDR] = {
+		"ddr", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_AHB] = {
+		"ahb", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_WDT] = {
+		"wdt", ATH79_CLK_ALIAS,
+		.parent = ATH79_CLK_AHB,
+	},
+
+	[ATH79_CLK_UART] = {
+		"uart", ATH79_CLK_ALIAS,
+		.parent = ATH79_CLK_REF,
+	},
+};
+
+struct ath79_cblk *
+ath79_cblk_new(const struct ath79_clk_info *clock_info,
+		unsigned num_clocks, struct device_node *np)
+{
+	struct ath79_cblk *cblk;
+
+	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
+	if (!cblk)
+		goto err_out;
+
+	cblk->base = of_iomap(np, 0);
+	if (!cblk->base) {
+		pr_err("%s: failed to map clock block registers\n", __func__);
+		goto err_out_free;
+	}
+
+	cblk->np = np;
+	cblk->clock_info = clock_info;
+	cblk->clocks.clk_num = num_clocks;
+
+	return cblk;
+
+err_out_free:
+	kfree(cblk);
+
+err_out:
+	return NULL;
+}
+
+static unsigned long
+ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
+	struct ath79_cblk *cblk = ath79_clk->cblk;
+	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
+	const struct ath79_pll_info *pll_info;
+	unsigned long rate;
+	unsigned long freq;
+	u32 clock_ctrl;
+	u32 cpu_config;
+	u32 t;
+
+	BUG_ON(clk_info->type != ATH79_CLK_PLL);
+
+	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
+
+	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+		return parent_rate;
+	}
+
+	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	freq = parent_rate / t;
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
+	freq *= t;
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (t == 0)
+		t = 1;
+
+	freq >>= t;
+
+	pll_info = &clk_info->pll;
+
+	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
+	rate = freq / t;
+
+	return rate;
+}
+
+static const struct clk_ops ath79_pll_clk_ops = {
+	.recalc_rate = ath79_pll_recalc_rate,
+};
+
+static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
+{
+	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
+	const struct ath79_clk_info *parent_clk_info;
+	struct clk_init_data clk_init;
+	struct ath79_clk *ath79_clk = NULL;
+	struct clk *clk;
+	int err = -EINVAL;
+
+	if (clk_info->type == ATH79_CLK_EXT) {
+		clk = of_clk_get_by_name(cblk->np, clk_info->name);
+		if (IS_ERR(clk)) {
+			pr_err("%s: no external clock '%s' provided\n",
+			       __func__, clk_info->name);
+			err = -ENODEV;
+			goto out;
+		}
+
+		err = clk_register_clkdev(clk, clk_info->name, NULL);
+		if (err) {
+			clk_put(clk);
+			goto out;
+		}
+
+		cblk->clocks.clks[idx] = clk;
+
+		return 0;
+	}
+
+	parent_clk_info = &cblk->clock_info[clk_info->parent];
+
+	if (clk_info->type == ATH79_CLK_ALIAS) {
+		clk = clk_register_fixed_factor(NULL, clk_info->name,
+						parent_clk_info->name, 0, 1, 1);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock '%s'\n", __func__,
+			       clk_info->name);
+			err = PTR_ERR(clk);
+			goto out;
+		}
+
+		cblk->clocks.clks[idx] = clk;
+
+		return 0;
+	}
+
+	if (!clk_info->type) {
+		pr_err("%s: no clock type specified for '%s'\n", __func__,
+		       clk_info->name);
+		goto out;
+	}
+
+	ath79_clk = kzalloc(sizeof(*ath79_clk), GFP_KERNEL);
+	if (!ath79_clk) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	ath79_clk->hw.init = &clk_init;
+	ath79_clk->cblk = cblk;
+	ath79_clk->idx = idx;
+
+	clk_init.name = clk_info->name;
+	clk_init.flags = 0;
+	clk_init.parent_names = &parent_clk_info->name;
+	clk_init.num_parents = 1;
+
+	if (clk_info->type == ATH79_CLK_PLL) {
+		clk_init.ops = &ath79_pll_clk_ops;
+	}
+
+	clk = clk_register(NULL, &ath79_clk->hw);
+	if (IS_ERR(clk)) {
+		pr_err("%s: failed to register clock '%s'\n", __func__,
+		       clk_info->name);
+		err = PTR_ERR(clk);
+		goto out;
+	}
+
+	err = clk_register_clkdev(clk, clk_info->name, NULL);
+	if (err)
+		goto out;
+
+	cblk->clocks.clks[idx] = clk;
+out:
+	if (err)
+		kfree(ath79_clk);
+
+	return err;
+}
+
+static int ath79_cblk_register_clocks(struct ath79_cblk *cblk)
+{
+	unsigned i;
+	int err;
+
+	cblk->clocks.clks = kcalloc(cblk->clocks.clk_num, sizeof(struct clk *),
+				   GFP_KERNEL);
+	if (!cblk->clocks.clks) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	for (i = 0; i < cblk->clocks.clk_num; i++) {
+		err = ath79_register_clock(cblk, i);
+		if (err)
+			goto err_out_unregister;
+	}
+
+	err = of_clk_add_provider(cblk->np, of_clk_src_onecell_get,
+				  &cblk->clocks);
+	if (err)
+		goto err_out_unregister;
+
+	return 0;
+
+err_out_unregister:
+	for (i = 0; i < cblk->clocks.clk_num; i++) {
+		if (!cblk->clocks.clks[i])
+			continue;
+		if (cblk->clock_info[i].type == ATH79_CLK_EXT)
+			clk_put(cblk->clocks.clks[i]);
+		else
+			clk_unregister(cblk->clocks.clks[i]);
+	}
+
+	kfree(cblk->clocks.clks);
+
+err_out:
+	return err;
+}
+
+static void __init ar9130_init(struct device_node *np)
+{
+	int retval;
+	struct ath79_cblk *cblk;
+
+	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
+	if (!cblk) {
+		pr_err("%s: failed to initialise clk block\n", __func__);
+		return;
+	}
+
+	retval = ath79_cblk_register_clocks(cblk);
+	if (retval)
+		pr_err("%s: failed to register clocks\n", __func__);
+}
+CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 0000000..1c6fb04
--- /dev/null
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_REF		0
+#define ATH79_CLK_CPU		1
+#define ATH79_CLK_DDR		2
+#define ATH79_CLK_AHB		3
+#define ATH79_CLK_WDT		4
+#define ATH79_CLK_UART		5
+
+#define ATH79_CLK_END		6
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
-- 
2.7.0

[RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
index e0fc2c1..ae99f22 100644
--- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+- compatible: has to be "qca,<soctype>-pll" and one of the following
   fallbacks:
   - "qca,ar7100-pll"
   - "qca,ar7240-pll"
@@ -21,7 +21,7 @@ Optional properties:
 
 Example:
 
-	memory-controller@18050000 {
+	pll-controller@18050000 {
 		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
 		reg = <0x18050000 0x20>;
 
-- 
2.7.0

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[RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
index e0fc2c1..ae99f22 100644
--- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+- compatible: has to be "qca,<soctype>-pll" and one of the following
   fallbacks:
   - "qca,ar7100-pll"
   - "qca,ar7240-pll"
@@ -21,7 +21,7 @@ Optional properties:
 
 Example:
 
-	memory-controller@18050000 {
+	pll-controller@18050000 {
 		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
 		reg = <0x18050000 0x20>;
 
-- 
2.7.0

[RFC v5 03/15] MIPS: ath79: use clk-ath79.c driver for AR933X

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
---
 arch/mips/ath79/clock.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117c..3c98eba 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -24,6 +24,7 @@
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
+#include "machtypes.h"
 
 #define AR71XX_BASE_FREQ	40000000
 #define AR724X_BASE_FREQ	5000000
@@ -441,7 +442,9 @@ static void __init qca955x_clocks_init(void)
 
 void __init ath79_clocks_init(void)
 {
-	if (soc_is_ar71xx())
+	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
+		/* pass */
+	} else if (soc_is_ar71xx())
 		ar71xx_clocks_init();
 	else if (soc_is_ar724x())
 		ar724x_clocks_init();
@@ -484,7 +487,6 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
 #endif
-- 
2.7.0

[RFC v5 04/15] WIP: MIPS: ath79: setup.c: disable platform code for OF boards

[Antony Pavlov]

For OF boards we have to skip platform initialization code
so we can prove that OF code do all necessary initialization.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
---
 arch/mips/ath79/setup.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 99ab4bb..d65d161 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -206,15 +206,16 @@ void __init plat_mem_setup(void)
 	else if (fw_arg0 == -2)
 		__dt_setup_arch((void *)fw_arg1);
 
-	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
-					   AR71XX_RESET_SIZE);
-	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
-					 AR71XX_PLL_SIZE);
-	ath79_detect_sys_type();
-	ath79_ddr_ctrl_init();
-
-	if (mips_machtype != ATH79_MACH_GENERIC_OF)
+	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
+		ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
+						   AR71XX_RESET_SIZE);
+		ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
+						 AR71XX_PLL_SIZE);
+		ath79_detect_sys_type();
+		ath79_ddr_ctrl_init();
+
 		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+	}
 
 	_machine_restart = ath79_restart;
 	_machine_halt = ath79_halt;
-- 
2.7.0

[RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Antony Pavlov]

This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/ar9331.dtsi | 157 +++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)

diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..333c7ff
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,157 @@
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+	compatible = "qca,ar9331";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+	};
+
+	ref: ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll ATH79_CLK_UART>;
+				clock-names = "uart";
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x100>;
+
+				clocks = <&ref>;
+				clock-names = "ref";
+
+				#clock-cells = <1>;
+			};
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			rst: reset-controller@1806001c {
+				compatible = "qca,ar7100-reset";
+				reg = <0x1806001c 0x4>;
+
+				#reset-cells = <1>;
+			};
+
+			usb: usb@1b000100 {
+				compatible = "qca,ar7100-ehci", "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <3>;
+				resets = <&rst 5>;
+
+				has-transaction-translator;
+
+				phy-names = "usb";
+				phys = <&usb_phy>;
+
+				status = "disabled";
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi";
+				reg = <0x1f000000 0x10>;
+
+				clocks = <&pll ATH79_CLK_AHB>;
+				clock-names = "ahb";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+	};
+
+	usb_phy: usb-phy {
+		compatible = "qca,ar7100-usb-phy";
+
+		reset-names = "usb-phy", "usb-suspend-override";
+		resets = <&rst 4>, <&rst 3>;
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+};
-- 
2.7.0

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[RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Antony Pavlov]

This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/ar9331.dtsi | 157 +++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)

diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..333c7ff
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,157 @@
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+	compatible = "qca,ar9331";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+	};
+
+	ref: ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll ATH79_CLK_UART>;
+				clock-names = "uart";
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x100>;
+
+				clocks = <&ref>;
+				clock-names = "ref";
+
+				#clock-cells = <1>;
+			};
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			rst: reset-controller@1806001c {
+				compatible = "qca,ar7100-reset";
+				reg = <0x1806001c 0x4>;
+
+				#reset-cells = <1>;
+			};
+
+			usb: usb@1b000100 {
+				compatible = "qca,ar7100-ehci", "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <3>;
+				resets = <&rst 5>;
+
+				has-transaction-translator;
+
+				phy-names = "usb";
+				phys = <&usb_phy>;
+
+				status = "disabled";
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi";
+				reg = <0x1f000000 0x10>;
+
+				clocks = <&pll ATH79_CLK_AHB>;
+				clock-names = "ahb";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+	};
+
+	usb_phy: usb-phy {
+		compatible = "qca,ar7100-usb-phy";
+
+		reset-names = "usb-phy", "usb-suspend-override";
+		resets = <&rst 4>, <&rst 3>;
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+};
-- 
2.7.0

[RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * GPIO keys and LEDs.

Links:

  * http://www.tp-link.com/en/products/details/?model=TL-MR3020
  * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
  * https://wikidevi.com/wiki/TP-LINK_TL-MR3020

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile      |  1 +
 arch/mips/boot/dts/qca/tl_mr3020.dts | 99 ++++++++++++++++++++++++++++++++++++
 2 files changed, 100 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 14bd225..504c4b1 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
 obj-				+= dummy.o
diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
new file mode 100644
index 0000000..2a1b296
--- /dev/null
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "TP-Link TL-MR3020";
+	compatible = "tplink,tl-mr3020";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "tp-link:green:lan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wps {
+			label = "tp-link:green:wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led3g {
+			label = "tp-link:green:3g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@1 {
+			label = "sw1";
+			linux,code = <BTN_0>;
+			gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@2 {
+			label = "sw2";
+			linux,code = <BTN_1>;
+			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Spansion S25FL032PIF SPI flash */
+	spiflash: s25sl032p@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25sl032p", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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[RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * GPIO keys and LEDs.

Links:

  * http://www.tp-link.com/en/products/details/?model=TL-MR3020
  * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
  * https://wikidevi.com/wiki/TP-LINK_TL-MR3020

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/Makefile      |  1 +
 arch/mips/boot/dts/qca/tl_mr3020.dts | 99 ++++++++++++++++++++++++++++++++++++
 2 files changed, 100 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 14bd225..504c4b1 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
 obj-				+= dummy.o
diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
new file mode 100644
index 0000000..2a1b296
--- /dev/null
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "TP-Link TL-MR3020";
+	compatible = "tplink,tl-mr3020";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "tp-link:green:lan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wps {
+			label = "tp-link:green:wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led3g {
+			label = "tp-link:green:3g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@1 {
+			label = "sw1";
+			linux,code = <BTN_0>;
+			gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@2 {
+			label = "sw2";
+			linux,code = <BTN_1>;
+			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Spansion S25FL032PIF SPI flash */
+	spiflash: s25sl032p@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25sl032p", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

[RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Antony Pavlov]

This patch retrieves and configures the vbus control gpio via
the device tree.

This patch is based on a ehci-s5p.c commit fd81d59c90d38661
("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-usb@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index bd7082f2..0d95ced 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_gpio.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/reset.h>
@@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
 	.power_off =		ehci_platform_power_off,
 };
 
+static void setup_vbus_gpio(struct device *dev)
+{
+	int err;
+	int gpio;
+
+	if (!dev->of_node)
+		return;
+
+	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
+	if (!gpio_is_valid(gpio))
+		return;
+
+	err = devm_gpio_request_one(dev, gpio,
+				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
+				"ehci_vbus_gpio");
+	if (err)
+		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
+}
+
 static int ehci_platform_probe(struct platform_device *dev)
 {
 	struct usb_hcd *hcd;
@@ -174,6 +194,8 @@ static int ehci_platform_probe(struct platform_device *dev)
 		return irq;
 	}
 
+	setup_vbus_gpio(&dev->dev);
+
 	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
 			     dev_name(&dev->dev));
 	if (!hcd)
-- 
2.7.0

[RFC v5 08/15] MIPS: tl_mr3020: enable usb support

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/boot/dts/qca/tl_mr3020.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
index 2a1b296..45c27ed 100644
--- a/arch/mips/boot/dts/qca/tl_mr3020.dts
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -84,6 +84,15 @@
 	status = "okay";
 };
 
+&usb {
+	status = "okay";
+	vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_phy {
+	status = "okay";
+};
+
 &spi {
 	num-chipselects = <1>;
 	status = "okay";
-- 
2.7.0

[RFC v5 09/15] devicetree: add Dragino vendor id

[Antony Pavlov]

Please see http://www.dragino.com/about/about.html for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 72e2c5a..49d07bf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
 edt	Emerging Display Technologies
-- 
2.7.0

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[RFC v5 09/15] devicetree: add Dragino vendor id

[Antony Pavlov]

Please see http://www.dragino.com/about/about.html for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 72e2c5a..49d07bf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
 edt	Emerging Display Technologies
-- 
2.7.0

[RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

    * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
    * https://wiki.openwrt.org/toh/dragino/ms14

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile         |   1 +
 arch/mips/boot/dts/qca/dragino_ms14.dts | 101 ++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 504c4b1..e949cff 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/dragino_ms14.dts b/arch/mips/boot/dts/qca/dragino_ms14.dts
new file mode 100644
index 0000000..44abb77
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dragino_ms14.dts
@@ -0,0 +1,101 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Dragino MS14 (Dragino 2)";
+	compatible = "dragino,ms14";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "dragino2:red:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "dragino2:red:lan";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wan {
+			label = "dragino2:red:wan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		system {
+			label = "dragino2:red:system";
+			gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "jumpstart";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		button@1 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128BVFG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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[RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

    * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
    * https://wiki.openwrt.org/toh/dragino/ms14

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/Makefile         |   1 +
 arch/mips/boot/dts/qca/dragino_ms14.dts | 101 ++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 504c4b1..e949cff 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/dragino_ms14.dts b/arch/mips/boot/dts/qca/dragino_ms14.dts
new file mode 100644
index 0000000..44abb77
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dragino_ms14.dts
@@ -0,0 +1,101 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Dragino MS14 (Dragino 2)";
+	compatible = "dragino,ms14";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "dragino2:red:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "dragino2:red:lan";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wan {
+			label = "dragino2:red:wan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		system {
+			label = "dragino2:red:system";
+			gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "jumpstart";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		button@1 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128BVFG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

[RFC v5 11/15] devicetree: add Onion Corporation vendor id

[Antony Pavlov]

Please see https://onion.io/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 49d07bf..afb96f7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -166,6 +166,7 @@ nvidia	NVIDIA
 nxp	NXP Semiconductors
 okaya	Okaya Electric America, Inc.
 olimex	OLIMEX Ltd.
+onion	Onion Corporation
 onnn	ON Semiconductor Corp.
 opencores	OpenCores.org
 option	Option NV
-- 
2.7.0

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[RFC v5 11/15] devicetree: add Onion Corporation vendor id

[Antony Pavlov]

Please see https://onion.io/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 49d07bf..afb96f7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -166,6 +166,7 @@ nvidia	NVIDIA
 nxp	NXP Semiconductors
 okaya	Okaya Electric America, Inc.
 olimex	OLIMEX Ltd.
+onion	Onion Corporation
 onnn	ON Semiconductor Corp.
 opencores	OpenCores.org
 option	Option NV
-- 
2.7.0

[RFC v5 12/15] MIPS: ath79: add initial support for Onion Omega

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Please see https://onion.io/omega for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: L. D. Pinney <ldpinney-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Boken Lin <bl-Jj7zZGp/71Y@public.gmane.org>
Cc: Jacky Huang <huangfangcheng-9Onoh4P/yGk@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile  |  1 +
 arch/mips/boot/dts/qca/omega.dts | 77 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index e949cff..ca2ecb8 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,6 +1,7 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
+dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/omega.dts b/arch/mips/boot/dts/qca/omega.dts
new file mode 100644
index 0000000..f4a7ed0
--- /dev/null
+++ b/arch/mips/boot/dts/qca/omega.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Onion Omega";
+	compatible = "onion,omega";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "onion:amber:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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[RFC v5 12/15] MIPS: ath79: add initial support for Onion Omega

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Please see https://onion.io/omega for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: L. D. Pinney <ldpinney@gmail.com>
Cc: Boken Lin <bl@onion.io>
Cc: Jacky Huang <huangfangcheng@163.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/Makefile  |  1 +
 arch/mips/boot/dts/qca/omega.dts | 77 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index e949cff..ca2ecb8 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,6 +1,7 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
+dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/omega.dts b/arch/mips/boot/dts/qca/omega.dts
new file mode 100644
index 0000000..f4a7ed0
--- /dev/null
+++ b/arch/mips/boot/dts/qca/omega.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Onion Omega";
+	compatible = "onion,omega";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "onion:amber:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

[RFC v5 13/15] devicetree: add DPTechnics vendor id

[Antony Pavlov]

Please see https://www.dptechnics.com/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index afb96f7..8cb96f2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dptechnics	DPTechnics
 dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
-- 
2.7.0

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[RFC v5 13/15] devicetree: add DPTechnics vendor id

[Antony Pavlov]

Please see https://www.dptechnics.com/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Daan Pape <daan@dptechnics.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index afb96f7..8cb96f2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dptechnics	DPTechnics
 dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
-- 
2.7.0

[RFC v5 14/15] MIPS: ath79: add DPT-Module support

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=50
  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=63

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile       |  1 +
 arch/mips/boot/dts/qca/dpt_module.dts | 77 +++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index ca2ecb8..7d4bf43 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dpt_module.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
diff --git a/arch/mips/boot/dts/qca/dpt_module.dts b/arch/mips/boot/dts/qca/dpt_module.dts
new file mode 100644
index 0000000..f4ccb74
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dpt_module.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "DPTechnics DPT-Module";
+	compatible = "dptechnics,dpt-module";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "dpt-module:green:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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[RFC v5 14/15] MIPS: ath79: add DPT-Module support

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=50
  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=63

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Daan Pape <daan@dptechnics.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/boot/dts/qca/Makefile       |  1 +
 arch/mips/boot/dts/qca/dpt_module.dts | 77 +++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index ca2ecb8..7d4bf43 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dpt_module.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
diff --git a/arch/mips/boot/dts/qca/dpt_module.dts b/arch/mips/boot/dts/qca/dpt_module.dts
new file mode 100644
index 0000000..f4ccb74
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dpt_module.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "DPTechnics DPT-Module";
+	compatible = "dptechnics,dpt-module";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "dpt-module:green:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

[RFC v5 15/15] WIP: MIPS: ath79: add AR9331 devicetree defconfig

[Antony Pavlov]

This commit adds defconfig file for AR9331 kernel
with device tree support.

The boards with u-boot_mod-like bootloader are supported:

  * TP-LINK MR3020;
  * Dragino 2;
  * Onion Omega;
  * DPTechnics DPT-Module.

Here is a small instruction:

1. download rootfs.mipsI.cpio image into your linux kernel
   source root dir.

    $ wget https://github.com/frantony/linux/raw/c95a5953e3dd96ad304de515f79acb555e0bc24e/rootfs.mipsI.cpio

2. you have to disable fw_getenv() function because
devicetree-enabled kernel will hangs if started
from u-boot_mod:

    > --- a/arch/mips/fw/lib/cmdline.c
    > +++ b/arch/mips/fw/lib/cmdline.c
    > @@ -51,6 +51,8 @@ char *fw_getenv(char *envname)
    >  {
    >         char *result = NULL;
    >
    > +       return result;
    > +

3. configure linux kernel and build vmlinux.bin linux kernel image

    $ make ARCH=mips ar9331-dt-raw_defconfig
    $ make ARCH=mips CROSS_COMPILE=<your cross compiler> vmlinux.bin

4. prepare vmlinux_dtb.bin image for your board

  4.1 for TP-LINK TL-MR3020

    $ make ARCH=mips qca/tl_mr3020.dtb
    $ cat arch/mips/boot/vmlinux.bin arch/mips/boot/dts/qca/tl_mr3020.dtb > vmlinux_dtb.bin

  4.2 for Dragino 2

    $ make ARCH=mips qca/dragino_ms14.dtb
    $ cat arch/mips/boot/vmlinux.bin arch/mips/boot/dts/qca/dragino_ms14.dtb > vmlinux_dtb.bin

  4.3 for Onion Omega

    $ make ARCH=mips qca/omega.dtb
    $ cat arch/mips/boot/vmlinux.bin arch/mips/boot/dts/qca/omega.dtb > vmlinux_dtb.bin

  4.4 DPTechnics DPT-Module

    $ make ARCH=mips qca/dpt_module.dtb
    $ cat arch/mips/boot/vmlinux.bin arch/mips/boot/dts/qca/dpt_module.dtb > vmlinux_dtb.bin

5. put the vmlinux_dtb.bin into the root directory of your tftp-server

6. connect to u-boot_mod console

7. use u-boot_mod to download vmlinux_dtb.bin into RAM of your board and run it:

   uboot> setenv serverip 192.168.1.2; setenv ipaddr 192.168.1.22
   uboot> tftpboot 0x80060000 vmlinux_dtb.bin; go 0x80060000

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: linux-mips@linux-mips.org
---
 arch/mips/configs/ar9331-dt-raw_defconfig | 100 ++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

diff --git a/arch/mips/configs/ar9331-dt-raw_defconfig b/arch/mips/configs/ar9331-dt-raw_defconfig
new file mode 100644
index 0000000..5d81969
--- /dev/null
+++ b/arch/mips/configs/ar9331-dt-raw_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ATH79=y
+CONFIG_ATH79_MACH_AP121=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="rootfs.mipsI.cpio"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_ATH79=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_ATH79 is not set
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PHY_SIMPLE_PDEV=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="init=/bin/sh machtype=DTB console=ttyATH0 root=/dev/ram"
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_CRC_ITU_T=y
-- 
2.7.0

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:47 AM, Antony Pavlov wrote:
> This driver can be easely upgraded for other Atheros
> SoCs (e.g. AR724X/AR913X) support.
> 

Hi!

[...]

> +static unsigned long
> +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> +	struct ath79_cblk *cblk = ath79_clk->cblk;
> +	const struct ath79_clk_info *clk_info =
> &cblk->clock_info[ath79_clk->idx]; +	const struct ath79_pll_info
> *pll_info;
> +	unsigned long rate;
> +	unsigned long freq;
> +	u32 clock_ctrl;
> +	u32 cpu_config;
> +	u32 t;
> +
> +	BUG_ON(clk_info->type != ATH79_CLK_PLL);
> +
> +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> +
> +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> +		return parent_rate;
> +	}

You can drop the {} here.

> +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> +	freq = parent_rate / t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> +	freq *= t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> +	if (t == 0)
> +		t = 1;
> +
> +	freq >>= t;
> +
> +	pll_info = &clk_info->pll;
> +
> +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> +	rate = freq / t;
> +
> +	return rate;
> +}

[...]

> +static void __init ar9130_init(struct device_node *np)
> +{
> +	int retval;
> +	struct ath79_cblk *cblk;
> +
> +	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +	if (!cblk) {
> +		pr_err("%s: failed to initialise clk block\n", __func__);
> +		return;
> +	}
> +
> +	retval = ath79_cblk_register_clocks(cblk);
> +	if (retval)
> +		pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);

Is that ar9130_init name correct? Shouldn't it be ar9330_init ?

Looks good otherwise, thanks!

Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:48 AM, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

Acked-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>

Best regards,
Marek Vasut
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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:48 AM, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

Re: [RFC v5 03/15] MIPS: ath79: use clk-ath79.c driver for AR933X

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:49 AM, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Gabor Juhos <juhosg@openwrt.org>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

Re: [RFC v5 04/15] WIP: MIPS: ath79: setup.c: disable platform code for OF boards

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:50 AM, Antony Pavlov wrote:
> For OF boards we have to skip platform initialization code
> so we can prove that OF code do all necessary initialization.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org

Why is this WIP ? It looks fine.

Reviewed-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

Re: [RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:51 AM, Antony Pavlov wrote:
> This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
> The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
> typically used in very cheap Access Points and Routers.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---

[...]

> +			usb: usb@1b000100 {
> +				compatible = "qca,ar7100-ehci", "generic-ehci";
> +				reg = <0x1b000100 0x100>;

It's actually chipidea HDRC , you should bind that driver with it instead.
See for example this:
http://patchwork.linux-mips.org/patch/4968/

> +				interrupt-parent = <&cpuintc>;
> +				interrupts = <3>;
> +				resets = <&rst 5>;
> +
> +				has-transaction-translator;
> +
> +				phy-names = "usb";
> +				phys = <&usb_phy>;
> +
> +				status = "disabled";
> +			};

[...]

Best regards,
Marek Vasut
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Re: [RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:51 AM, Antony Pavlov wrote:
> This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
> The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
> typically used in very cheap Access Points and Routers.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Gabor Juhos <juhosg@openwrt.org>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---

[...]

> +			usb: usb@1b000100 {
> +				compatible = "qca,ar7100-ehci", "generic-ehci";
> +				reg = <0x1b000100 0x100>;

It's actually chipidea HDRC , you should bind that driver with it instead.
See for example this:
http://patchwork.linux-mips.org/patch/4968/

> +				interrupt-parent = <&cpuintc>;
> +				interrupts = <3>;
> +				resets = <&rst 5>;
> +
> +				has-transaction-translator;
> +
> +				phy-names = "usb";
> +				phys = <&usb_phy>;
> +
> +				status = "disabled";
> +			};

[...]

Best regards,
Marek Vasut

Re: [RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:52 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>   * http://www.tp-link.com/en/products/details/?model=TL-MR3020
>   * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
>   * https://wikidevi.com/wiki/TP-LINK_TL-MR3020
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/mips/boot/dts/qca/Makefile      |  1 +
>  arch/mips/boot/dts/qca/tl_mr3020.dts | 99
> ++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 14bd225..504c4b1 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb

You might want to stay consistent and call it ar9331_tl_mr3020.dtb .

[...]

Best regards,
Marek Vasut
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Re: [RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:52 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>   * http://www.tp-link.com/en/products/details/?model=TL-MR3020
>   * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
>   * https://wikidevi.com/wiki/TP-LINK_TL-MR3020
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Gabor Juhos <juhosg@openwrt.org>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
>  arch/mips/boot/dts/qca/Makefile      |  1 +
>  arch/mips/boot/dts/qca/tl_mr3020.dts | 99
> ++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 14bd225..504c4b1 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb

You might want to stay consistent and call it ar9331_tl_mr3020.dtb .

[...]

Best regards,
Marek Vasut

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:53 AM, Antony Pavlov wrote:
> This patch retrieves and configures the vbus control gpio via
> the device tree.
> 
> This patch is based on a ehci-s5p.c commit fd81d59c90d38661
> ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-usb@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)

I think this patch will not be needed if you switch the ar9331 to chipidea hdrc
driver. There is CI HDRC in the ar9331.

Best regards,
Marek Vasut

Re: [RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:56 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * USB host;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>     * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
>     * https://wiki.openwrt.org/toh/dragino/ms14
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/mips/boot/dts/qca/Makefile         |   1 +
>  arch/mips/boot/dts/qca/dragino_ms14.dts | 101
> ++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 504c4b1..e949cff 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb

ar9331_dragino_ms14.dtb ?

>  dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
> 

You should re-order the board additions at the end of the patchset, so you
can then squash the USB DT patch for the mr3020 board into it.

Best regards,
Marek Vasut
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Re: [RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:56 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * USB host;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>     * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
>     * https://wiki.openwrt.org/toh/dragino/ms14
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Gabor Juhos <juhosg@openwrt.org>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
>  arch/mips/boot/dts/qca/Makefile         |   1 +
>  arch/mips/boot/dts/qca/dragino_ms14.dts | 101
> ++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 504c4b1..e949cff 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb

ar9331_dragino_ms14.dtb ?

>  dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
> 

You should re-order the board additions at the end of the patchset, so you
can then squash the USB DT patch for the mr3020 board into it.

Best regards,
Marek Vasut

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Alban]

On Tue,  9 Feb 2016 11:13:47 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> This driver can be easely upgraded for other Atheros
> SoCs (e.g. AR724X/AR913X) support.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Cc: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  drivers/clk/Makefile                  |   1 +
>  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/ath79-clk.h |  22 +++
>  3 files changed, 377 insertions(+)
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index b038e36..d7ad50e 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -18,6 +18,7 @@ endif
>  # hardware specific clock types
>  # please keep this section sorted lexicographically by file/directory path name
>  obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
> +obj-$(CONFIG_ATH79)			+= clk-ath79.o
>  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
>  obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
>  obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
> diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> new file mode 100644
> index 0000000..e899d31
> --- /dev/null
> +++ b/drivers/clk/clk-ath79.c
> @@ -0,0 +1,354 @@
> +/*
> + * Clock driver for Atheros AR933X SoCs
> + *
> + * Copyright (C) 2016 Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This driver is based on Ingenic CGU linux driver by Paul Burton
> + * and AR9331 barebox driver by Antony Pavlov.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include <dt-bindings/clock/ath79-clk.h>
> +
> +#include "asm/mach-ath79/ar71xx_regs.h"

This header shouldn't be used in new code, just defines the few
registers needed here. Not using this header allow the driver
to be built in compile test which increase test coverage.

> +struct ath79_pll_info {
> +	u32 div_shift;
> +	u32 div_mask;
> +};
> +
> +struct ath79_cblk;
> +
> +/**
> + * struct ath79_clk_info - information about a clock
> + * @name: name of the clock
> + * @type: a bitmask formed from ATH79_CLK_* values
> + * @parents: an index of parent of this clock
> + *           within the clock_info array, or -1
> + *           which correspond to no valid parent
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk_info {
> +	const char *name;
> +
> +	enum {
> +		ATH79_CLK_NONE		= 0,
> +		ATH79_CLK_EXT		= 1,
> +		ATH79_CLK_PLL		= 2,
> +		ATH79_CLK_ALIAS		= 3,
> +	} type;
> +
> +	struct ath79_cblk *cblk;
> +	int parent;
> +
> +	struct ath79_pll_info pll;
> +};
> +
> +struct ath79_cblk {
> +	struct device_node *np;
> +	void __iomem *base;
> +
> +	const struct ath79_clk_info *clock_info;
> +	struct clk_onecell_data clocks;
> +};
> +
> +/**
> + * struct ath79_clk - private data for a clock
> + * @hw: see Documentation/clk.txt
> + * @cblk: a pointer to the cblk data
> + * @idx: the index of this clock cblk->clock_info
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk {
> +	struct clk_hw hw;
> +	struct ath79_cblk *cblk;
> +	unsigned idx;
> +};
> +
> +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> +
> +static const struct ath79_clk_info ar9331_clocks[] = {
> +
> +	/* External clock */
> +	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
> +
> +	[ATH79_CLK_CPU] = {
> +		"cpu", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_DDR] = {
> +		"ddr", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_AHB] = {
> +		"ahb", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_WDT] = {
> +		"wdt", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_AHB,
> +	},
> +
> +	[ATH79_CLK_UART] = {
> +		"uart", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_REF,
> +	},
> +};
> +
> +struct ath79_cblk *
> +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> +		unsigned num_clocks, struct device_node *np)
> +{
> +	struct ath79_cblk *cblk;
> +
> +	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
> +	if (!cblk)
> +		goto err_out;
> +
> +	cblk->base = of_iomap(np, 0);
> +	if (!cblk->base) {
> +		pr_err("%s: failed to map clock block registers\n", __func__);
> +		goto err_out_free;
> +	}
> +
> +	cblk->np = np;
> +	cblk->clock_info = clock_info;
> +	cblk->clocks.clk_num = num_clocks;
> +
> +	return cblk;
> +
> +err_out_free:
> +	kfree(cblk);
> +
> +err_out:
> +	return NULL;
> +}
> +
> +static unsigned long
> +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> +	struct ath79_cblk *cblk = ath79_clk->cblk;
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
> +	const struct ath79_pll_info *pll_info;
> +	unsigned long rate;
> +	unsigned long freq;
> +	u32 clock_ctrl;
> +	u32 cpu_config;
> +	u32 t;
> +
> +	BUG_ON(clk_info->type != ATH79_CLK_PLL);

It's probably debatable if such a BUG_ON() is really needed.

> +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> +
> +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> +		return parent_rate;
> +	}

Those brace should goes away.

> +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> +	freq = parent_rate / t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> +	freq *= t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> +	if (t == 0)
> +		t = 1;
> +
> +	freq >>= t;
> +
> +	pll_info = &clk_info->pll;
> +
> +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> +	rate = freq / t;

If we just compute a fixed rate we could as well use
clk_register_fixed_factor() and drop 80% of the code of this driver.

> +	return rate;
> +}
> +
> +static const struct clk_ops ath79_pll_clk_ops = {
> +	.recalc_rate = ath79_pll_recalc_rate,
> +};
> +
> +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> +{
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
> +	const struct ath79_clk_info *parent_clk_info;
> +	struct clk_init_data clk_init;
> +	struct ath79_clk *ath79_clk = NULL;
> +	struct clk *clk;
> +	int err = -EINVAL;
> +
> +	if (clk_info->type == ATH79_CLK_EXT) {
> +		clk = of_clk_get_by_name(cblk->np, clk_info->name);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: no external clock '%s' provided\n",
> +			       __func__, clk_info->name);
> +			err = -ENODEV;
> +			goto out;
> +		}
> +
> +		err = clk_register_clkdev(clk, clk_info->name, NULL);
> +		if (err) {
> +			clk_put(clk);
> +			goto out;
> +		}

clk_register_clkdev() and naming providers is not needed on OF
platforms. This should only be used on legacy platforms.

> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}
> +
> +	parent_clk_info = &cblk->clock_info[clk_info->parent];
> +
> +	if (clk_info->type == ATH79_CLK_ALIAS) {
> +		clk = clk_register_fixed_factor(NULL, clk_info->name,
> +						parent_clk_info->name, 0, 1, 1);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: failed to register clock '%s'\n", __func__,
> +			       clk_info->name);
> +			err = PTR_ERR(clk);
> +			goto out;
> +		}
> +
> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}

I really don't get why you keep insisting on having those useless alias
clocks. Alias are only needed on legacy platforms to form connections
between clock providers and consumers. On OF platforms these
connections are nicely represented in the DT, so it is just not
needed at all.

> +	if (!clk_info->type) {
> +		pr_err("%s: no clock type specified for '%s'\n", __func__,
> +		       clk_info->name);
> +		goto out;
> +	}
> +
> +	ath79_clk = kzalloc(sizeof(*ath79_clk), GFP_KERNEL);
> +	if (!ath79_clk) {
> +		err = -ENOMEM;
> +		goto out;
> +	}
> +
> +	ath79_clk->hw.init = &clk_init;
> +	ath79_clk->cblk = cblk;
> +	ath79_clk->idx = idx;
> +
> +	clk_init.name = clk_info->name;
> +	clk_init.flags = 0;
> +	clk_init.parent_names = &parent_clk_info->name;
> +	clk_init.num_parents = 1;
> +
> +	if (clk_info->type == ATH79_CLK_PLL) {
> +		clk_init.ops = &ath79_pll_clk_ops;
> +	}
> +
> +	clk = clk_register(NULL, &ath79_clk->hw);
> +	if (IS_ERR(clk)) {
> +		pr_err("%s: failed to register clock '%s'\n", __func__,
> +		       clk_info->name);
> +		err = PTR_ERR(clk);
> +		goto out;
> +	}
> +
> +	err = clk_register_clkdev(clk, clk_info->name, NULL);
> +	if (err)
> +		goto out;

clk_register_clkdev() shouldn't be needed here either.

> +	cblk->clocks.clks[idx] = clk;
> +out:
> +	if (err)
> +		kfree(ath79_clk);
> +
> +	return err;
> +}
> +
> +static int ath79_cblk_register_clocks(struct ath79_cblk *cblk)
> +{
> +	unsigned i;
> +	int err;
> +
> +	cblk->clocks.clks = kcalloc(cblk->clocks.clk_num, sizeof(struct clk *),
> +				   GFP_KERNEL);
> +	if (!cblk->clocks.clks) {
> +		err = -ENOMEM;
> +		goto err_out;
> +	}
> +
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		err = ath79_register_clock(cblk, i);
> +		if (err)
> +			goto err_out_unregister;
> +	}
> +
> +	err = of_clk_add_provider(cblk->np, of_clk_src_onecell_get,
> +				  &cblk->clocks);
> +	if (err)
> +		goto err_out_unregister;
> +
> +	return 0;
> +
> +err_out_unregister:
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		if (!cblk->clocks.clks[i])
> +			continue;
> +		if (cblk->clock_info[i].type == ATH79_CLK_EXT)
> +			clk_put(cblk->clocks.clks[i]);
> +		else
> +			clk_unregister(cblk->clocks.clks[i]);
> +	}
> +
> +	kfree(cblk->clocks.clks);
> +
> +err_out:
> +	return err;
> +}
> +
> +static void __init ar9130_init(struct device_node *np)
> +{
> +	int retval;
> +	struct ath79_cblk *cblk;
> +
> +	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +	if (!cblk) {
> +		pr_err("%s: failed to initialise clk block\n", __func__);
> +		return;
> +	}
> +
> +	retval = ath79_cblk_register_clocks(cblk);
> +	if (retval)
> +		pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);
> diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
> new file mode 100644
> index 0000000..1c6fb04
> --- /dev/null
> +++ b/include/dt-bindings/clock/ath79-clk.h
> @@ -0,0 +1,22 @@
> +/*
> + * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_ATH79_CLK_H
> +#define __DT_BINDINGS_ATH79_CLK_H
> +
> +#define ATH79_CLK_REF		0
> +#define ATH79_CLK_CPU		1
> +#define ATH79_CLK_DDR		2
> +#define ATH79_CLK_AHB		3
> +#define ATH79_CLK_WDT		4
> +#define ATH79_CLK_UART		5
> +
> +#define ATH79_CLK_END		6
> +
> +#endif /* __DT_BINDINGS_ATH79_CLK_H */

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Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Alban]

On Tue,  9 Feb 2016 11:13:47 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> This driver can be easely upgraded for other Atheros
> SoCs (e.g. AR724X/AR913X) support.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Paul Burton <paul.burton@imgtec.com>
> Cc: linux-clk@vger.kernel.org
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
>  drivers/clk/Makefile                  |   1 +
>  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/ath79-clk.h |  22 +++
>  3 files changed, 377 insertions(+)
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index b038e36..d7ad50e 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -18,6 +18,7 @@ endif
>  # hardware specific clock types
>  # please keep this section sorted lexicographically by file/directory path name
>  obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
> +obj-$(CONFIG_ATH79)			+= clk-ath79.o
>  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
>  obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
>  obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
> diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> new file mode 100644
> index 0000000..e899d31
> --- /dev/null
> +++ b/drivers/clk/clk-ath79.c
> @@ -0,0 +1,354 @@
> +/*
> + * Clock driver for Atheros AR933X SoCs
> + *
> + * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
> + *
> + * This driver is based on Ingenic CGU linux driver by Paul Burton
> + * and AR9331 barebox driver by Antony Pavlov.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include <dt-bindings/clock/ath79-clk.h>
> +
> +#include "asm/mach-ath79/ar71xx_regs.h"

This header shouldn't be used in new code, just defines the few
registers needed here. Not using this header allow the driver
to be built in compile test which increase test coverage.

> +struct ath79_pll_info {
> +	u32 div_shift;
> +	u32 div_mask;
> +};
> +
> +struct ath79_cblk;
> +
> +/**
> + * struct ath79_clk_info - information about a clock
> + * @name: name of the clock
> + * @type: a bitmask formed from ATH79_CLK_* values
> + * @parents: an index of parent of this clock
> + *           within the clock_info array, or -1
> + *           which correspond to no valid parent
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk_info {
> +	const char *name;
> +
> +	enum {
> +		ATH79_CLK_NONE		= 0,
> +		ATH79_CLK_EXT		= 1,
> +		ATH79_CLK_PLL		= 2,
> +		ATH79_CLK_ALIAS		= 3,
> +	} type;
> +
> +	struct ath79_cblk *cblk;
> +	int parent;
> +
> +	struct ath79_pll_info pll;
> +};
> +
> +struct ath79_cblk {
> +	struct device_node *np;
> +	void __iomem *base;
> +
> +	const struct ath79_clk_info *clock_info;
> +	struct clk_onecell_data clocks;
> +};
> +
> +/**
> + * struct ath79_clk - private data for a clock
> + * @hw: see Documentation/clk.txt
> + * @cblk: a pointer to the cblk data
> + * @idx: the index of this clock cblk->clock_info
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk {
> +	struct clk_hw hw;
> +	struct ath79_cblk *cblk;
> +	unsigned idx;
> +};
> +
> +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> +
> +static const struct ath79_clk_info ar9331_clocks[] = {
> +
> +	/* External clock */
> +	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
> +
> +	[ATH79_CLK_CPU] = {
> +		"cpu", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_DDR] = {
> +		"ddr", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_AHB] = {
> +		"ahb", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_WDT] = {
> +		"wdt", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_AHB,
> +	},
> +
> +	[ATH79_CLK_UART] = {
> +		"uart", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_REF,
> +	},
> +};
> +
> +struct ath79_cblk *
> +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> +		unsigned num_clocks, struct device_node *np)
> +{
> +	struct ath79_cblk *cblk;
> +
> +	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
> +	if (!cblk)
> +		goto err_out;
> +
> +	cblk->base = of_iomap(np, 0);
> +	if (!cblk->base) {
> +		pr_err("%s: failed to map clock block registers\n", __func__);
> +		goto err_out_free;
> +	}
> +
> +	cblk->np = np;
> +	cblk->clock_info = clock_info;
> +	cblk->clocks.clk_num = num_clocks;
> +
> +	return cblk;
> +
> +err_out_free:
> +	kfree(cblk);
> +
> +err_out:
> +	return NULL;
> +}
> +
> +static unsigned long
> +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> +	struct ath79_cblk *cblk = ath79_clk->cblk;
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
> +	const struct ath79_pll_info *pll_info;
> +	unsigned long rate;
> +	unsigned long freq;
> +	u32 clock_ctrl;
> +	u32 cpu_config;
> +	u32 t;
> +
> +	BUG_ON(clk_info->type != ATH79_CLK_PLL);

It's probably debatable if such a BUG_ON() is really needed.

> +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> +
> +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> +		return parent_rate;
> +	}

Those brace should goes away.

> +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> +	freq = parent_rate / t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> +	freq *= t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> +	if (t == 0)
> +		t = 1;
> +
> +	freq >>= t;
> +
> +	pll_info = &clk_info->pll;
> +
> +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> +	rate = freq / t;

If we just compute a fixed rate we could as well use
clk_register_fixed_factor() and drop 80% of the code of this driver.

> +	return rate;
> +}
> +
> +static const struct clk_ops ath79_pll_clk_ops = {
> +	.recalc_rate = ath79_pll_recalc_rate,
> +};
> +
> +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> +{
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
> +	const struct ath79_clk_info *parent_clk_info;
> +	struct clk_init_data clk_init;
> +	struct ath79_clk *ath79_clk = NULL;
> +	struct clk *clk;
> +	int err = -EINVAL;
> +
> +	if (clk_info->type == ATH79_CLK_EXT) {
> +		clk = of_clk_get_by_name(cblk->np, clk_info->name);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: no external clock '%s' provided\n",
> +			       __func__, clk_info->name);
> +			err = -ENODEV;
> +			goto out;
> +		}
> +
> +		err = clk_register_clkdev(clk, clk_info->name, NULL);
> +		if (err) {
> +			clk_put(clk);
> +			goto out;
> +		}

clk_register_clkdev() and naming providers is not needed on OF
platforms. This should only be used on legacy platforms.

> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}
> +
> +	parent_clk_info = &cblk->clock_info[clk_info->parent];
> +
> +	if (clk_info->type == ATH79_CLK_ALIAS) {
> +		clk = clk_register_fixed_factor(NULL, clk_info->name,
> +						parent_clk_info->name, 0, 1, 1);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: failed to register clock '%s'\n", __func__,
> +			       clk_info->name);
> +			err = PTR_ERR(clk);
> +			goto out;
> +		}
> +
> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}

I really don't get why you keep insisting on having those useless alias
clocks. Alias are only needed on legacy platforms to form connections
between clock providers and consumers. On OF platforms these
connections are nicely represented in the DT, so it is just not
needed at all.

> +	if (!clk_info->type) {
> +		pr_err("%s: no clock type specified for '%s'\n", __func__,
> +		       clk_info->name);
> +		goto out;
> +	}
> +
> +	ath79_clk = kzalloc(sizeof(*ath79_clk), GFP_KERNEL);
> +	if (!ath79_clk) {
> +		err = -ENOMEM;
> +		goto out;
> +	}
> +
> +	ath79_clk->hw.init = &clk_init;
> +	ath79_clk->cblk = cblk;
> +	ath79_clk->idx = idx;
> +
> +	clk_init.name = clk_info->name;
> +	clk_init.flags = 0;
> +	clk_init.parent_names = &parent_clk_info->name;
> +	clk_init.num_parents = 1;
> +
> +	if (clk_info->type == ATH79_CLK_PLL) {
> +		clk_init.ops = &ath79_pll_clk_ops;
> +	}
> +
> +	clk = clk_register(NULL, &ath79_clk->hw);
> +	if (IS_ERR(clk)) {
> +		pr_err("%s: failed to register clock '%s'\n", __func__,
> +		       clk_info->name);
> +		err = PTR_ERR(clk);
> +		goto out;
> +	}
> +
> +	err = clk_register_clkdev(clk, clk_info->name, NULL);
> +	if (err)
> +		goto out;

clk_register_clkdev() shouldn't be needed here either.

> +	cblk->clocks.clks[idx] = clk;
> +out:
> +	if (err)
> +		kfree(ath79_clk);
> +
> +	return err;
> +}
> +
> +static int ath79_cblk_register_clocks(struct ath79_cblk *cblk)
> +{
> +	unsigned i;
> +	int err;
> +
> +	cblk->clocks.clks = kcalloc(cblk->clocks.clk_num, sizeof(struct clk *),
> +				   GFP_KERNEL);
> +	if (!cblk->clocks.clks) {
> +		err = -ENOMEM;
> +		goto err_out;
> +	}
> +
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		err = ath79_register_clock(cblk, i);
> +		if (err)
> +			goto err_out_unregister;
> +	}
> +
> +	err = of_clk_add_provider(cblk->np, of_clk_src_onecell_get,
> +				  &cblk->clocks);
> +	if (err)
> +		goto err_out_unregister;
> +
> +	return 0;
> +
> +err_out_unregister:
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		if (!cblk->clocks.clks[i])
> +			continue;
> +		if (cblk->clock_info[i].type == ATH79_CLK_EXT)
> +			clk_put(cblk->clocks.clks[i]);
> +		else
> +			clk_unregister(cblk->clocks.clks[i]);
> +	}
> +
> +	kfree(cblk->clocks.clks);
> +
> +err_out:
> +	return err;
> +}
> +
> +static void __init ar9130_init(struct device_node *np)
> +{
> +	int retval;
> +	struct ath79_cblk *cblk;
> +
> +	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +	if (!cblk) {
> +		pr_err("%s: failed to initialise clk block\n", __func__);
> +		return;
> +	}
> +
> +	retval = ath79_cblk_register_clocks(cblk);
> +	if (retval)
> +		pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);
> diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
> new file mode 100644
> index 0000000..1c6fb04
> --- /dev/null
> +++ b/include/dt-bindings/clock/ath79-clk.h
> @@ -0,0 +1,22 @@
> +/*
> + * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_ATH79_CLK_H
> +#define __DT_BINDINGS_ATH79_CLK_H
> +
> +#define ATH79_CLK_REF		0
> +#define ATH79_CLK_CPU		1
> +#define ATH79_CLK_DDR		2
> +#define ATH79_CLK_AHB		3
> +#define ATH79_CLK_WDT		4
> +#define ATH79_CLK_UART		5
> +
> +#define ATH79_CLK_END		6
> +
> +#endif /* __DT_BINDINGS_ATH79_CLK_H */

Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Alban]

On Tue,  9 Feb 2016 11:13:48 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> index e0fc2c1..ae99f22 100644
> --- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
>  The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
>  
>  Required Properties:
> -- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
> +- compatible: has to be "qca,<soctype>-pll" and one of the following
>    fallbacks:
>    - "qca,ar7100-pll"
>    - "qca,ar7240-pll"
> @@ -21,7 +21,7 @@ Optional properties:
>  
>  Example:
>  
> -	memory-controller@18050000 {
> +	pll-controller@18050000 {
>  		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
>  		reg = <0x18050000 0x20>;
>  

Acked-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>

Alban
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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Alban]

On Tue,  9 Feb 2016 11:13:48 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> index e0fc2c1..ae99f22 100644
> --- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
>  The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
>  
>  Required Properties:
> -- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
> +- compatible: has to be "qca,<soctype>-pll" and one of the following
>    fallbacks:
>    - "qca,ar7100-pll"
>    - "qca,ar7240-pll"
> @@ -21,7 +21,7 @@ Optional properties:
>  
>  Example:
>  
> -	memory-controller@18050000 {
> +	pll-controller@18050000 {
>  		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
>  		reg = <0x18050000 0x20>;
>  

Acked-by: Alban Bedel <albeu@free.fr>

Alban

Re: [RFC v5 03/15] MIPS: ath79: use clk-ath79.c driver for AR933X

[Alban]

On Tue,  9 Feb 2016 11:13:49 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Gabor Juhos <juhosg@openwrt.org>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: linux-mips@linux-mips.org
> ---
>  arch/mips/ath79/clock.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
> index eb5117c..3c98eba 100644
> --- a/arch/mips/ath79/clock.c
> +++ b/arch/mips/ath79/clock.c
> @@ -24,6 +24,7 @@
>  #include <asm/mach-ath79/ath79.h>
>  #include <asm/mach-ath79/ar71xx_regs.h>
>  #include "common.h"
> +#include "machtypes.h"
>  
>  #define AR71XX_BASE_FREQ	40000000
>  #define AR724X_BASE_FREQ	5000000
> @@ -441,7 +442,9 @@ static void __init qca955x_clocks_init(void)
>  
>  void __init ath79_clocks_init(void)
>  {
> -	if (soc_is_ar71xx())
> +	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
> +		/* pass */
> +	} else if (soc_is_ar71xx())

This will break all non AR9330 SoC as their clock won't be properly
initialized, so this is not acceptable.

I would also really prefer if we can avoid having two completely
different implementation for legacy and OF platforms. Ideally both
legacy and OF should use the same core code, just with 2 different
wrappers. The OF wrapper would just need to get the parent clock from
DT and call the core setup. The legacy code path would need to create
the fixed rate parent clock with the current hard coded value, call the
core setup, then register the clkdev and alias mapping.

I find it important to avoid code duplication because that mean double
the amount of testing work. But in practice that generally mean that
only one half get tested as no one wants to do double the work.

> @@ -484,7 +487,6 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
>  CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
>  CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
>  CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
> -CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
>  CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
>  CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
>  #endif

This should have been part of the new driver, otherwise this will break
bisecting as there would be a version with 2 CLK_OF_DECLARE for ar9330.

Alban

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Alban]

On Tue,  9 Feb 2016 11:13:53 +0300
Antony Pavlov <antonynpavlov@gmail.com> wrote:

> This patch retrieves and configures the vbus control gpio via
> the device tree.

Wouldn't using a regulator be better than hard coding the GPIO case?

Alban

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Antony Pavlov]

On Tue, 9 Feb 2016 23:15:20 +0100
Alban <albeu@free.fr> wrote:

> On Tue,  9 Feb 2016 11:13:53 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > This patch retrieves and configures the vbus control gpio via
> > the device tree.
> 
> Wouldn't using a regulator be better than hard coding the GPIO case?
> 

Marek Vasut has noted that it is possible to use compatible = "chipidea,usb2",
which makes it possible to connect fixed vbus regulator via "vbus-supply" property.

I'll try to use fixed-regulator in RFC v6.

-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 03/15] MIPS: ath79: use clk-ath79.c driver for AR933X

[Antony Pavlov]

On Tue, 9 Feb 2016 23:07:21 +0100
Alban <albeu@free.fr> wrote:

> On Tue,  9 Feb 2016 11:13:49 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Gabor Juhos <juhosg@openwrt.org>
> > Cc: Alban Bedel <albeu@free.fr>
> > Cc: linux-mips@linux-mips.org
> > ---
> >  arch/mips/ath79/clock.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
> > index eb5117c..3c98eba 100644
> > --- a/arch/mips/ath79/clock.c
> > +++ b/arch/mips/ath79/clock.c
> > @@ -24,6 +24,7 @@
> >  #include <asm/mach-ath79/ath79.h>
> >  #include <asm/mach-ath79/ar71xx_regs.h>
> >  #include "common.h"
> > +#include "machtypes.h"
> >  
> >  #define AR71XX_BASE_FREQ	40000000
> >  #define AR724X_BASE_FREQ	5000000
> > @@ -441,7 +442,9 @@ static void __init qca955x_clocks_init(void)
> >  
> >  void __init ath79_clocks_init(void)
> >  {
> > -	if (soc_is_ar71xx())
> > +	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
> > +		/* pass */
> > +	} else if (soc_is_ar71xx())
> 
> This will break all non AR9330 SoC as their clock won't be properly
> initialized, so this is not acceptable.

Actually this can't broke non-OF board.
This breaks only OF AR9132-based board WR1043DN just because I have not
included AR9132-related patches into RFC v5 patcheseries.

But after adding these patches the problem will disappear.

> I would also really prefer if we can avoid having two completely
> different implementation for legacy and OF platforms. Ideally both
> legacy and OF should use the same core code, just with 2 different
> wrappers. The OF wrapper would just need to get the parent clock from
> DT and call the core setup. The legacy code path would need to create
> the fixed rate parent clock with the current hard coded value, call the
> core setup, then register the clkdev and alias mapping.
> 
> I find it important to avoid code duplication because that mean double
> the amount of testing work. But in practice that generally mean that
> only one half get tested as no one wants to do double the work.

I'm completely agreed your plan. The RFC v5 patchseries was intended
to proof of-clk driver implementation. Please not that it's a RFC series.

> > @@ -484,7 +487,6 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
> >  CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
> >  CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
> >  CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
> > -CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
> >  CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
> >  CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
> >  #endif
> 
> This should have been part of the new driver, otherwise this will break
> bisecting as there would be a version with 2 CLK_OF_DECLARE for ar9330.

No, it can't break a bisection because there is no defconfig that enables both simultaneously.
Of cause you always prepare special configuration by hand :) if you wish intentionally
break your bisection.
If I have missed something then please explain exactly the situation then a bisection
can be broken.
 
-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Antony Pavlov]

On Tue, 9 Feb 2016 22:51:34 +0100
Alban <albeu@free.fr> wrote:

> On Tue,  9 Feb 2016 11:13:47 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > This driver can be easely upgraded for other Atheros
> > SoCs (e.g. AR724X/AR913X) support.
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Alban Bedel <albeu@free.fr>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Stephen Boyd <sboyd@codeaurora.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Paul Burton <paul.burton@imgtec.com>
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-mips@linux-mips.org
> > Cc: devicetree@vger.kernel.org
> > ---
> >  drivers/clk/Makefile                  |   1 +
> >  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
> >  include/dt-bindings/clock/ath79-clk.h |  22 +++
> >  3 files changed, 377 insertions(+)
> > 
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index b038e36..d7ad50e 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -18,6 +18,7 @@ endif
> >  # hardware specific clock types
> >  # please keep this section sorted lexicographically by file/directory path name
> >  obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
> > +obj-$(CONFIG_ATH79)			+= clk-ath79.o
> >  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
> >  obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
> >  obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
> > diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> > new file mode 100644
> > index 0000000..e899d31
> > --- /dev/null
> > +++ b/drivers/clk/clk-ath79.c
> > @@ -0,0 +1,354 @@
> > +/*
> > + * Clock driver for Atheros AR933X SoCs
> > + *
> > + * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
> > + *
> > + * This driver is based on Ingenic CGU linux driver by Paul Burton
> > + * and AR9331 barebox driver by Antony Pavlov.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +
> > +#include <dt-bindings/clock/ath79-clk.h>
> > +
> > +#include "asm/mach-ath79/ar71xx_regs.h"
> 
> This header shouldn't be used in new code, just defines the few
> registers needed here. Not using this header allow the driver
> to be built in compile test which increase test coverage.

ok.

> > +struct ath79_pll_info {
> > +	u32 div_shift;
> > +	u32 div_mask;
> > +};
> > +
> > +struct ath79_cblk;
> > +
> > +/**
> > + * struct ath79_clk_info - information about a clock
> > + * @name: name of the clock
> > + * @type: a bitmask formed from ATH79_CLK_* values
> > + * @parents: an index of parent of this clock
> > + *           within the clock_info array, or -1
> > + *           which correspond to no valid parent
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk_info {
> > +	const char *name;
> > +
> > +	enum {
> > +		ATH79_CLK_NONE		= 0,
> > +		ATH79_CLK_EXT		= 1,
> > +		ATH79_CLK_PLL		= 2,
> > +		ATH79_CLK_ALIAS		= 3,
> > +	} type;
> > +
> > +	struct ath79_cblk *cblk;
> > +	int parent;
> > +
> > +	struct ath79_pll_info pll;
> > +};
> > +
> > +struct ath79_cblk {
> > +	struct device_node *np;
> > +	void __iomem *base;
> > +
> > +	const struct ath79_clk_info *clock_info;
> > +	struct clk_onecell_data clocks;
> > +};
> > +
> > +/**
> > + * struct ath79_clk - private data for a clock
> > + * @hw: see Documentation/clk.txt
> > + * @cblk: a pointer to the cblk data
> > + * @idx: the index of this clock cblk->clock_info
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk {
> > +	struct clk_hw hw;
> > +	struct ath79_cblk *cblk;
> > +	unsigned idx;
> > +};
> > +
> > +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> > +
> > +static const struct ath79_clk_info ar9331_clocks[] = {
> > +
> > +	/* External clock */
> > +	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
> > +
> > +	[ATH79_CLK_CPU] = {
> > +		"cpu", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_DDR] = {
> > +		"ddr", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_AHB] = {
> > +		"ahb", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_WDT] = {
> > +		"wdt", ATH79_CLK_ALIAS,
> > +		.parent = ATH79_CLK_AHB,
> > +	},
> > +
> > +	[ATH79_CLK_UART] = {
> > +		"uart", ATH79_CLK_ALIAS,
> > +		.parent = ATH79_CLK_REF,
> > +	},
> > +};
> > +
> > +struct ath79_cblk *
> > +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> > +		unsigned num_clocks, struct device_node *np)
> > +{
> > +	struct ath79_cblk *cblk;
> > +
> > +	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
> > +	if (!cblk)
> > +		goto err_out;
> > +
> > +	cblk->base = of_iomap(np, 0);
> > +	if (!cblk->base) {
> > +		pr_err("%s: failed to map clock block registers\n", __func__);
> > +		goto err_out_free;
> > +	}
> > +
> > +	cblk->np = np;
> > +	cblk->clock_info = clock_info;
> > +	cblk->clocks.clk_num = num_clocks;
> > +
> > +	return cblk;
> > +
> > +err_out_free:
> > +	kfree(cblk);
> > +
> > +err_out:
> > +	return NULL;
> > +}
> > +
> > +static unsigned long
> > +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > +{
> > +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> > +	struct ath79_cblk *cblk = ath79_clk->cblk;
> > +	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
> > +	const struct ath79_pll_info *pll_info;
> > +	unsigned long rate;
> > +	unsigned long freq;
> > +	u32 clock_ctrl;
> > +	u32 cpu_config;
> > +	u32 t;
> > +
> > +	BUG_ON(clk_info->type != ATH79_CLK_PLL);
> 
> It's probably debatable if such a BUG_ON() is really needed.

In simple RFC v5 driver version this check is redundant.
I suppose it's reasonable for more advanced version of the driver.
 
> > +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> > +
> > +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> > +		return parent_rate;
> > +	}
> 
> Those brace should goes away.

Ok.

> > +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> > +	freq = parent_rate / t;
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> > +	freq *= t;
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> > +	if (t == 0)
> > +		t = 1;
> > +
> > +	freq >>= t;
> > +
> > +	pll_info = &clk_info->pll;
> > +
> > +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> > +	rate = freq / t;
> 
> If we just compute a fixed rate we could as well use
> clk_register_fixed_factor() and drop 80% of the code of this driver.

80% is an overstatement.

> > +	return rate;
> > +}
> > +
> > +static const struct clk_ops ath79_pll_clk_ops = {
> > +	.recalc_rate = ath79_pll_recalc_rate,
> > +};
> > +
> > +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> > +{
> > +	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
> > +	const struct ath79_clk_info *parent_clk_info;
> > +	struct clk_init_data clk_init;
> > +	struct ath79_clk *ath79_clk = NULL;
> > +	struct clk *clk;
> > +	int err = -EINVAL;
> > +
> > +	if (clk_info->type == ATH79_CLK_EXT) {
> > +		clk = of_clk_get_by_name(cblk->np, clk_info->name);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: no external clock '%s' provided\n",
> > +			       __func__, clk_info->name);
> > +			err = -ENODEV;
> > +			goto out;
> > +		}
> > +
> > +		err = clk_register_clkdev(clk, clk_info->name, NULL);
> > +		if (err) {
> > +			clk_put(clk);
> > +			goto out;
> > +		}
> 
> clk_register_clkdev() and naming providers is not needed on OF
> platforms. This should only be used on legacy platforms.

I can't drop these clk_register_clkdev() just now without patching legacy code.

If I just drop clk_register_clkdev() then I get

    Kernel panic - not syncing: unable to get cpu clock, err=-2

on start.


> > +		cblk->clocks.clks[idx] = clk;
> > +
> > +		return 0;
> > +	}
> > +
> > +	parent_clk_info = &cblk->clock_info[clk_info->parent];
> > +
> > +	if (clk_info->type == ATH79_CLK_ALIAS) {
> > +		clk = clk_register_fixed_factor(NULL, clk_info->name,
> > +						parent_clk_info->name, 0, 1, 1);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: failed to register clock '%s'\n", __func__,
> > +			       clk_info->name);
> > +			err = PTR_ERR(clk);
> > +			goto out;
> > +		}
> > +
> > +		cblk->clocks.clks[idx] = clk;
> > +
> > +		return 0;
> > +	}
> 
> I really don't get why you keep insisting on having those useless alias
> clocks. Alias are only needed on legacy platforms to form connections
> between clock providers and consumers. On OF platforms these
> connections are nicely represented in the DT, so it is just not
> needed at all.

I have droppped these aliases in RFC v6 series.

-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Antony Pavlov]

On Tue, 9 Feb 2016 22:51:34 +0100
Alban <albeu@free.fr> wrote:

> On Tue,  9 Feb 2016 11:13:47 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
>=20
> > This driver can be easely upgraded for other Atheros
> > SoCs (e.g. AR724X/AR913X) support.
> >=20
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Alban Bedel <albeu@free.fr>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Stephen Boyd <sboyd@codeaurora.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Paul Burton <paul.burton@imgtec.com>
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-mips@linux-mips.org
> > Cc: devicetree@vger.kernel.org
> > ---
> >  drivers/clk/Makefile                  |   1 +
> >  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++=
++++++++
> >  include/dt-bindings/clock/ath79-clk.h |  22 +++
> >  3 files changed, 377 insertions(+)
> >=20
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index b038e36..d7ad50e 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -18,6 +18,7 @@ endif
> >  # hardware specific clock types
> >  # please keep this section sorted lexicographically by file/directory =
path name
> >  obj-$(CONFIG_MACH_ASM9260)		+=3D clk-asm9260.o
> > +obj-$(CONFIG_ATH79)			+=3D clk-ath79.o
> >  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+=3D clk-axi-clkgen.o
> >  obj-$(CONFIG_ARCH_AXXIA)		+=3D clk-axm5516.o
> >  obj-$(CONFIG_COMMON_CLK_CDCE706)	+=3D clk-cdce706.o
> > diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> > new file mode 100644
> > index 0000000..e899d31
> > --- /dev/null
> > +++ b/drivers/clk/clk-ath79.c
> > @@ -0,0 +1,354 @@
> > +/*
> > + * Clock driver for Atheros AR933X SoCs
> > + *
> > + * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
> > + *
> > + * This driver is based on Ingenic CGU linux driver by Paul Burton
> > + * and AR9331 barebox driver by Antony Pavlov.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +
> > +#include <dt-bindings/clock/ath79-clk.h>
> > +
> > +#include "asm/mach-ath79/ar71xx_regs.h"
>=20
> This header shouldn't be used in new code, just defines the few
> registers needed here. Not using this header allow the driver
> to be built in compile test which increase test coverage.

ok.

> > +struct ath79_pll_info {
> > +	u32 div_shift;
> > +	u32 div_mask;
> > +};
> > +
> > +struct ath79_cblk;
> > +
> > +/**
> > + * struct ath79_clk_info - information about a clock
> > + * @name: name of the clock
> > + * @type: a bitmask formed from ATH79_CLK_* values
> > + * @parents: an index of parent of this clock
> > + *           within the clock_info array, or -1
> > + *           which correspond to no valid parent
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk_info {
> > +	const char *name;
> > +
> > +	enum {
> > +		ATH79_CLK_NONE		=3D 0,
> > +		ATH79_CLK_EXT		=3D 1,
> > +		ATH79_CLK_PLL		=3D 2,
> > +		ATH79_CLK_ALIAS		=3D 3,
> > +	} type;
> > +
> > +	struct ath79_cblk *cblk;
> > +	int parent;
> > +
> > +	struct ath79_pll_info pll;
> > +};
> > +
> > +struct ath79_cblk {
> > +	struct device_node *np;
> > +	void __iomem *base;
> > +
> > +	const struct ath79_clk_info *clock_info;
> > +	struct clk_onecell_data clocks;
> > +};
> > +
> > +/**
> > + * struct ath79_clk - private data for a clock
> > + * @hw: see Documentation/clk.txt
> > + * @cblk: a pointer to the cblk data
> > + * @idx: the index of this clock cblk->clock_info
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk {
> > +	struct clk_hw hw;
> > +	struct ath79_cblk *cblk;
> > +	unsigned idx;
> > +};
> > +
> > +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> > +
> > +static const struct ath79_clk_info ar9331_clocks[] =3D {
> > +
> > +	/* External clock */
> > +	[ATH79_CLK_REF] =3D { "ref", ATH79_CLK_EXT },
> > +
> > +	[ATH79_CLK_CPU] =3D {
> > +		"cpu", ATH79_CLK_PLL,
> > +		.parent =3D ATH79_CLK_REF,
> > +		.pll =3D {
> > +			.div_shift =3D AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> > +			.div_mask =3D AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_DDR] =3D {
> > +		"ddr", ATH79_CLK_PLL,
> > +		.parent =3D ATH79_CLK_REF,
> > +		.pll =3D {
> > +			.div_shift =3D AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> > +			.div_mask =3D AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_AHB] =3D {
> > +		"ahb", ATH79_CLK_PLL,
> > +		.parent =3D ATH79_CLK_REF,
> > +		.pll =3D {
> > +			.div_shift =3D AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> > +			.div_mask =3D AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_WDT] =3D {
> > +		"wdt", ATH79_CLK_ALIAS,
> > +		.parent =3D ATH79_CLK_AHB,
> > +	},
> > +
> > +	[ATH79_CLK_UART] =3D {
> > +		"uart", ATH79_CLK_ALIAS,
> > +		.parent =3D ATH79_CLK_REF,
> > +	},
> > +};
> > +
> > +struct ath79_cblk *
> > +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> > +		unsigned num_clocks, struct device_node *np)
> > +{
> > +	struct ath79_cblk *cblk;
> > +
> > +	cblk =3D kzalloc(sizeof(*cblk), GFP_KERNEL);
> > +	if (!cblk)
> > +		goto err_out;
> > +
> > +	cblk->base =3D of_iomap(np, 0);
> > +	if (!cblk->base) {
> > +		pr_err("%s: failed to map clock block registers\n", __func__);
> > +		goto err_out_free;
> > +	}
> > +
> > +	cblk->np =3D np;
> > +	cblk->clock_info =3D clock_info;
> > +	cblk->clocks.clk_num =3D num_clocks;
> > +
> > +	return cblk;
> > +
> > +err_out_free:
> > +	kfree(cblk);
> > +
> > +err_out:
> > +	return NULL;
> > +}
> > +
> > +static unsigned long
> > +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > +{
> > +	struct ath79_clk *ath79_clk =3D to_ath79_clk(hw);
> > +	struct ath79_cblk *cblk =3D ath79_clk->cblk;
> > +	const struct ath79_clk_info *clk_info =3D &cblk->clock_info[ath79_clk=
->idx];
> > +	const struct ath79_pll_info *pll_info;
> > +	unsigned long rate;
> > +	unsigned long freq;
> > +	u32 clock_ctrl;
> > +	u32 cpu_config;
> > +	u32 t;
> > +
> > +	BUG_ON(clk_info->type !=3D ATH79_CLK_PLL);
>=20
> It's probably debatable if such a BUG_ON() is really needed.

In simple RFC v5 driver version this check is redundant.
I suppose it's reasonable for more advanced version of the driver.
=20
> > +	clock_ctrl =3D __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> > +
> > +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> > +		return parent_rate;
> > +	}
>=20
> Those brace should goes away.

Ok.

> > +	cpu_config =3D __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> > +
> > +	t =3D (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> > +	freq =3D parent_rate / t;
> > +
> > +	t =3D (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> > +	freq *=3D t;
> > +
> > +	t =3D (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> > +	if (t =3D=3D 0)
> > +		t =3D 1;
> > +
> > +	freq >>=3D t;
> > +
> > +	pll_info =3D &clk_info->pll;
> > +
> > +	t =3D ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> > +	rate =3D freq / t;
>=20
> If we just compute a fixed rate we could as well use
> clk_register_fixed_factor() and drop 80% of the code of this driver.

80% is an overstatement.

> > +	return rate;
> > +}
> > +
> > +static const struct clk_ops ath79_pll_clk_ops =3D {
> > +	.recalc_rate =3D ath79_pll_recalc_rate,
> > +};
> > +
> > +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> > +{
> > +	const struct ath79_clk_info *clk_info =3D &cblk->clock_info[idx];
> > +	const struct ath79_clk_info *parent_clk_info;
> > +	struct clk_init_data clk_init;
> > +	struct ath79_clk *ath79_clk =3D NULL;
> > +	struct clk *clk;
> > +	int err =3D -EINVAL;
> > +
> > +	if (clk_info->type =3D=3D ATH79_CLK_EXT) {
> > +		clk =3D of_clk_get_by_name(cblk->np, clk_info->name);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: no external clock '%s' provided\n",
> > +			       __func__, clk_info->name);
> > +			err =3D -ENODEV;
> > +			goto out;
> > +		}
> > +
> > +		err =3D clk_register_clkdev(clk, clk_info->name, NULL);
> > +		if (err) {
> > +			clk_put(clk);
> > +			goto out;
> > +		}
>=20
> clk_register_clkdev() and naming providers is not needed on OF
> platforms. This should only be used on legacy platforms.

I can't drop these clk_register_clkdev() just now without patching legacy c=
ode.

If I just drop clk_register_clkdev() then I get

    Kernel panic - not syncing: unable to get cpu clock, err=3D-2

on start.


> > +		cblk->clocks.clks[idx] =3D clk;
> > +
> > +		return 0;
> > +	}
> > +
> > +	parent_clk_info =3D &cblk->clock_info[clk_info->parent];
> > +
> > +	if (clk_info->type =3D=3D ATH79_CLK_ALIAS) {
> > +		clk =3D clk_register_fixed_factor(NULL, clk_info->name,
> > +						parent_clk_info->name, 0, 1, 1);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: failed to register clock '%s'\n", __func__,
> > +			       clk_info->name);
> > +			err =3D PTR_ERR(clk);
> > +			goto out;
> > +		}
> > +
> > +		cblk->clocks.clks[idx] =3D clk;
> > +
> > +		return 0;
> > +	}
>=20
> I really don't get why you keep insisting on having those useless alias
> clocks. Alias are only needed on legacy platforms to form connections
> between clock providers and consumers. On OF platforms these
> connections are nicely represented in the DT, so it is just not
> needed at all.

I have droppped these aliases in RFC v6 series.

--=A0
Best regards,
=A0 Antony Pavlov

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Michael Turquette]

Quoting Antony Pavlov (2016-02-09 00:13:47)
> +static void __init ar9130_init(struct device_node *np)
> +{
> +       int retval;
> +       struct ath79_cblk *cblk;
> +
> +       cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +       if (!cblk) {
> +               pr_err("%s: failed to initialise clk block\n", __func__);
> +               return;
> +       }
> +
> +       retval = ath79_cblk_register_clocks(cblk);
> +       if (retval)
> +               pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);

Is there any reason this isn't a platform_driver?

Thanks,
Mike

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Michael Turquette]

Quoting Antony Pavlov (2016-02-09 00:13:47)
> +static void __init ar9130_init(struct device_node *np)
> +{
> +       int retval;
> +       struct ath79_cblk *cblk;
> +
> +       cblk =3D ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks),=
 np);
> +       if (!cblk) {
> +               pr_err("%s: failed to initialise clk block\n", __func__);
> +               return;
> +       }
> +
> +       retval =3D ath79_cblk_register_clocks(cblk);
> +       if (retval)
> +               pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);

Is there any reason this isn't a platform_driver?

Thanks,
Mike

Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:48AM +0300, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:48AM +0300, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alban Bedel <albeu@free.fr>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: devicetree@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [RFC v5 13/15] devicetree: add DPTechnics vendor id

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:59AM +0300, Antony Pavlov wrote:
> Please see https://www.dptechnics.com/contact for details.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [RFC v5 13/15] devicetree: add DPTechnics vendor id

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:59AM +0300, Antony Pavlov wrote:
> Please see https://www.dptechnics.com/contact for details.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Daan Pape <daan@dptechnics.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Alan Stern]

On Tue, 9 Feb 2016, Antony Pavlov wrote:

> This patch retrieves and configures the vbus control gpio via
> the device tree.
> 
> This patch is based on a ehci-s5p.c commit fd81d59c90d38661
> ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-usb@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index bd7082f2..0d95ced 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -28,6 +28,7 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/of_gpio.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/reset.h>
> @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
>  	.power_off =		ehci_platform_power_off,
>  };
>  
> +static void setup_vbus_gpio(struct device *dev)
> +{
> +	int err;
> +	int gpio;
> +
> +	if (!dev->of_node)
> +		return;
> +
> +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
> +	if (!gpio_is_valid(gpio))
> +		return;
> +
> +	err = devm_gpio_request_one(dev, gpio,
> +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
> +				"ehci_vbus_gpio");
> +	if (err)
> +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);

I don't understand this.  If you get an error here, what's the point of 
allowing the probe to continue?  Shouldn't you return an error code so 
the probe will fail?

Alan Stern

> +}
> +
>  static int ehci_platform_probe(struct platform_device *dev)
>  {
>  	struct usb_hcd *hcd;
> @@ -174,6 +194,8 @@ static int ehci_platform_probe(struct platform_device *dev)
>  		return irq;
>  	}
>  
> +	setup_vbus_gpio(&dev->dev);
> +
>  	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>  			     dev_name(&dev->dev));
>  	if (!hcd)
> 

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Alan Stern]

On Tue, 9 Feb 2016, Antony Pavlov wrote:

> This patch retrieves and configures the vbus control gpio via
> the device tree.
> 
> This patch is based on a ehci-s5p.c commit fd81d59c90d38661
> ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-usb@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index bd7082f2..0d95ced 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -28,6 +28,7 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/of_gpio.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/reset.h>
> @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
>  	.power_off =		ehci_platform_power_off,
>  };
>  
> +static void setup_vbus_gpio(struct device *dev)
> +{
> +	int err;
> +	int gpio;
> +
> +	if (!dev->of_node)
> +		return;
> +
> +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
> +	if (!gpio_is_valid(gpio))
> +		return;
> +
> +	err = devm_gpio_request_one(dev, gpio,
> +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
> +				"ehci_vbus_gpio");
> +	if (err)
> +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);

I don't understand this.  If you get an error here, what's the point of 
allowing the probe to continue?  Shouldn't you return an error code so 
the probe will fail?

Alan Stern

> +}
> +
>  static int ehci_platform_probe(struct platform_device *dev)
>  {
>  	struct usb_hcd *hcd;
> @@ -174,6 +194,8 @@ static int ehci_platform_probe(struct platform_device *dev)
>  		return irq;
>  	}
>  
> +	setup_vbus_gpio(&dev->dev);
> +
>  	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
>  			     dev_name(&dev->dev));
>  	if (!hcd)
> 

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Marek Vasut]

On 02/18/2016 05:12 PM, Alan Stern wrote:
> On Tue, 9 Feb 2016, Antony Pavlov wrote:
> 
>> This patch retrieves and configures the vbus control gpio via
>> the device tree.
>>
>> This patch is based on a ehci-s5p.c commit fd81d59c90d38661
>> ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
>>
>> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
>> Cc: Alan Stern <stern@rowland.harvard.edu>
>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> Cc: linux-usb@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> ---
>>  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
>> index bd7082f2..0d95ced 100644
>> --- a/drivers/usb/host/ehci-platform.c
>> +++ b/drivers/usb/host/ehci-platform.c
>> @@ -28,6 +28,7 @@
>>  #include <linux/io.h>
>>  #include <linux/module.h>
>>  #include <linux/of.h>
>> +#include <linux/of_gpio.h>
>>  #include <linux/phy/phy.h>
>>  #include <linux/platform_device.h>
>>  #include <linux/reset.h>
>> @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
>>  	.power_off =		ehci_platform_power_off,
>>  };
>>  
>> +static void setup_vbus_gpio(struct device *dev)
>> +{
>> +	int err;
>> +	int gpio;
>> +
>> +	if (!dev->of_node)
>> +		return;
>> +
>> +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
>> +	if (!gpio_is_valid(gpio))
>> +		return;
>> +
>> +	err = devm_gpio_request_one(dev, gpio,
>> +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
>> +				"ehci_vbus_gpio");
>> +	if (err)
>> +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
> 
> I don't understand this.  If you get an error here, what's the point of 
> allowing the probe to continue?  Shouldn't you return an error code so 
> the probe will fail?

The idea is I believe that if there is no vbus gpio specified, the port
might just not have vbus control, so the probe can continue. But this
patch is irrelevant anyway, since Alexey will switch to CI HDRC driver
and use standard regulator, as it should be done.

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Antony Pavlov]

On Thu, 18 Feb 2016 11:12:43 -0500 (EST)
Alan Stern <stern@rowland.harvard.edu> wrote:

> On Tue, 9 Feb 2016, Antony Pavlov wrote:
> 
> > This patch retrieves and configures the vbus control gpio via
> > the device tree.
> > 
> > This patch is based on a ehci-s5p.c commit fd81d59c90d38661
> > ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Alan Stern <stern@rowland.harvard.edu>
> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Cc: linux-usb@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> > index bd7082f2..0d95ced 100644
> > --- a/drivers/usb/host/ehci-platform.c
> > +++ b/drivers/usb/host/ehci-platform.c
> > @@ -28,6 +28,7 @@
> >  #include <linux/io.h>
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> > +#include <linux/of_gpio.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/reset.h>
> > @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
> >  	.power_off =		ehci_platform_power_off,
> >  };
> >  
> > +static void setup_vbus_gpio(struct device *dev)
> > +{
> > +	int err;
> > +	int gpio;
> > +
> > +	if (!dev->of_node)
> > +		return;
> > +
> > +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
> > +	if (!gpio_is_valid(gpio))
> > +		return;
> > +
> > +	err = devm_gpio_request_one(dev, gpio,
> > +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
> > +				"ehci_vbus_gpio");
> > +	if (err)
> > +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
>
>
> I don't understand this.  If you get an error here, what's the point of 
> allowing the probe to continue?  Shouldn't you return an error code so 
> the probe will fail?

Please ignore the 'usb: ehci: add vbus-gpio parameter' patch!

In the new AR9331 patchseries I use chipidea USB driver (thanks to Marek for the suggestion)
in the AR9331 dtsi-file:

        usb: usb@1b000100 {
                compatible = "chipidea,usb2";
                reg = <0x1b000000 0x200>;

                interrupt-parent = <&cpuintc>;
                interrupts = <3>;
                resets = <&rst 5>;

                phy-names = "usb-phy";
                phys = <&usb_phy>;

                status = "disabled";
        };


so I use regulator in the TL-MR3020 board dts file:

        reg_usb_vbus: reg_usb_vbus {
                compatible = "regulator-fixed";
                regulator-name = "usb_vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };

&usb {
        dr_mode = "host";
        vbus-supply = <&reg_usb_vbus>;
        status = "okay";
};

As a result there is no need in adding vbus-gpio parameter to ehci anymore!

> > +}
> > +
> >  static int ehci_platform_probe(struct platform_device *dev)
> >  {
> >  	struct usb_hcd *hcd;
> > @@ -174,6 +194,8 @@ static int ehci_platform_probe(struct platform_device *dev)
> >  		return irq;
> >  	}
> >  
> > +	setup_vbus_gpio(&dev->dev);
> > +
> >  	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
> >  			     dev_name(&dev->dev));
> >  	if (!hcd)
> > 
> 


-- 
-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Antony Pavlov]

On Thu, 18 Feb 2016 11:12:43 -0500 (EST)
Alan Stern <stern@rowland.harvard.edu> wrote:

> On Tue, 9 Feb 2016, Antony Pavlov wrote:
> 
> > This patch retrieves and configures the vbus control gpio via
> > the device tree.
> > 
> > This patch is based on a ehci-s5p.c commit fd81d59c90d38661
> > ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Alan Stern <stern@rowland.harvard.edu>
> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Cc: linux-usb@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >  drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> > index bd7082f2..0d95ced 100644
> > --- a/drivers/usb/host/ehci-platform.c
> > +++ b/drivers/usb/host/ehci-platform.c
> > @@ -28,6 +28,7 @@
> >  #include <linux/io.h>
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> > +#include <linux/of_gpio.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/reset.h>
> > @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
> >  	.power_off =		ehci_platform_power_off,
> >  };
> >  
> > +static void setup_vbus_gpio(struct device *dev)
> > +{
> > +	int err;
> > +	int gpio;
> > +
> > +	if (!dev->of_node)
> > +		return;
> > +
> > +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
> > +	if (!gpio_is_valid(gpio))
> > +		return;
> > +
> > +	err = devm_gpio_request_one(dev, gpio,
> > +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
> > +				"ehci_vbus_gpio");
> > +	if (err)
> > +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
>
>
> I don't understand this.  If you get an error here, what's the point of 
> allowing the probe to continue?  Shouldn't you return an error code so 
> the probe will fail?

Please ignore the 'usb: ehci: add vbus-gpio parameter' patch!

In the new AR9331 patchseries I use chipidea USB driver (thanks to Marek for the suggestion)
in the AR9331 dtsi-file:

        usb: usb@1b000100 {
                compatible = "chipidea,usb2";
                reg = <0x1b000000 0x200>;

                interrupt-parent = <&cpuintc>;
                interrupts = <3>;
                resets = <&rst 5>;

                phy-names = "usb-phy";
                phys = <&usb_phy>;

                status = "disabled";
        };


so I use regulator in the TL-MR3020 board dts file:

        reg_usb_vbus: reg_usb_vbus {
                compatible = "regulator-fixed";
                regulator-name = "usb_vbus";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };

&usb {
        dr_mode = "host";
        vbus-supply = <&reg_usb_vbus>;
        status = "okay";
};

As a result there is no need in adding vbus-gpio parameter to ehci anymore!

> > +}
> > +
> >  static int ehci_platform_probe(struct platform_device *dev)
> >  {
> >  	struct usb_hcd *hcd;
> > @@ -174,6 +194,8 @@ static int ehci_platform_probe(struct platform_device *dev)
> >  		return irq;
> >  	}
> >  
> > +	setup_vbus_gpio(&dev->dev);
> > +
> >  	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
> >  			     dev_name(&dev->dev));
> >  	if (!hcd)
> > 
> 


-- 
-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Sergei Shtylyov]

On 02/18/2016 09:06 PM, Antony Pavlov wrote:

>>> This patch retrieves and configures the vbus control gpio via
>>> the device tree.
>>>
>>> This patch is based on a ehci-s5p.c commit fd81d59c90d38661
>>> ("USB: ehci-s5p: Add vbus setup function to the s5p ehci glue layer").
>>>
>>> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
>>> Cc: Alan Stern <stern@rowland.harvard.edu>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> Cc: linux-usb@vger.kernel.org
>>> Cc: linux-kernel@vger.kernel.org
>>> ---
>>>   drivers/usb/host/ehci-platform.c | 22 ++++++++++++++++++++++
>>>   1 file changed, 22 insertions(+)
>>>
>>> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
>>> index bd7082f2..0d95ced 100644
>>> --- a/drivers/usb/host/ehci-platform.c
>>> +++ b/drivers/usb/host/ehci-platform.c
>>> @@ -28,6 +28,7 @@
>>>   #include <linux/io.h>
>>>   #include <linux/module.h>
>>>   #include <linux/of.h>
>>> +#include <linux/of_gpio.h>
>>>   #include <linux/phy/phy.h>
>>>   #include <linux/platform_device.h>
>>>   #include <linux/reset.h>
>>> @@ -142,6 +143,25 @@ static struct usb_ehci_pdata ehci_platform_defaults = {
>>>   	.power_off =		ehci_platform_power_off,
>>>   };
>>>
>>> +static void setup_vbus_gpio(struct device *dev)
>>> +{
>>> +	int err;
>>> +	int gpio;
>>> +
>>> +	if (!dev->of_node)
>>> +		return;
>>> +
>>> +	gpio = of_get_named_gpio(dev->of_node, "vbus-gpio", 0);
>>> +	if (!gpio_is_valid(gpio))
>>> +		return;
>>> +
>>> +	err = devm_gpio_request_one(dev, gpio,
>>> +				GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
>>> +				"ehci_vbus_gpio");
>>> +	if (err)
>>> +		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
>>
>>
>> I don't understand this.  If you get an error here, what's the point of
>> allowing the probe to continue?  Shouldn't you return an error code so
>> the probe will fail?
>
> Please ignore the 'usb: ehci: add vbus-gpio parameter' patch!
>
> In the new AR9331 patchseries I use chipidea USB driver (thanks to Marek for the suggestion)
> in the AR9331 dtsi-file:
>
>          usb: usb@1b000100 {
>                  compatible = "chipidea,usb2";
>                  reg = <0x1b000000 0x200>;
>
>                  interrupt-parent = <&cpuintc>;
>                  interrupts = <3>;
>                  resets = <&rst 5>;
>
>                  phy-names = "usb-phy";
>                  phys = <&usb_phy>;
>
>                  status = "disabled";
>          };
>
>
> so I use regulator in the TL-MR3020 board dts file:
>
>          reg_usb_vbus: reg_usb_vbus {
>                  compatible = "regulator-fixed";
>                  regulator-name = "usb_vbus";
>                  regulator-min-microvolt = <5000000>;

    Not 0?

>                  regulator-max-microvolt = <5000000>;
>                  gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;

    Where's the switch if both voltages are equal?

>                  enable-active-high;
>          };
>
> &usb {
>          dr_mode = "host";
>          vbus-supply = <&reg_usb_vbus>;
>          status = "okay";
> };
>
> As a result there is no need in adding vbus-gpio parameter to ehci anymore!
[...]

MBR, Sergei

Re: [RFC v5 07/15] usb: ehci: add vbus-gpio parameter

[Antony Pavlov]

On Thu, 18 Feb 2016 21:31:20 +0300
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote:

> On 02/18/2016 09:06 PM, Antony Pavlov wrote:
[...]
> > so I use regulator in the TL-MR3020 board dts file:
> >
> >          reg_usb_vbus: reg_usb_vbus {
> >                  compatible = "regulator-fixed";
> >                  regulator-name = "usb_vbus";
> >                  regulator-min-microvolt = <5000000>;
> 
>     Not 0?
> 
> >                  regulator-max-microvolt = <5000000>;
> >                  gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
> 
>     Where's the switch if both voltages are equal?

Here is a quote from linux/Documentation/devicetree/bindings/regulator/fixed-regulator.txt

        Any property defined as part of the core regulator
        binding, defined in regulator.txt, can also be used.
        However a fixed voltage regulator is expected to have the
        regulator-min-microvolt and regulator-max-microvolt
        to be the same.

Moreover please see this of_get_fixed_voltage_config() code fragment
(please see linux/drivers/regulator/fixed.c for details):

	if (init_data->constraints.min_uV == init_data->constraints.max_uV) {
		config->microvolts = init_data->constraints.min_uV;
	} else {
		dev_err(dev,
			 "Fixed regulator specified with variable voltages\n");
		return ERR_PTR(-EINVAL);
	}

-- 
Best regards,
  Antony Pavlov