* [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
@ 2016-02-19 11:23 Deepak M
2016-02-19 11:23 ` [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI Deepak M
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Deepak M @ 2016-02-19 11:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, Jani Nikula
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
v3 by Jani
- rebase on previous patches
- don't return null on errors
v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606 ++++++++++++++++++++++++++---
2 files changed, 559 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870..606dc71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_FLISDSI 0x1b
#define IOSF_PORT_GPIO_SC 0x48
#define IOSF_PORT_GPIO_SUS 0xa8
+#define IOSF_MAX_GPIO_NUM_NC 26
+#define IOSF_MAX_GPIO_NUM_SC 128
+#define IOSF_MAX_GPIO_NUM 172
#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
+#define VLV_GPIO_CFG 0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c..e02e5e0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
#define NS_KHZ_RATIO 1000000
-#define GPI0_NC_0_HV_DDI0_HPD 0x4130
-#define GPIO_NC_0_HV_DDI0_PAD 0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
-#define GPIO_NC_3_PANEL0_VDDEN 0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
-#define GPIO_NC_4_PANEL0_BLKEN 0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF0 0x4180
-#define GPIO_NC_6_PAD 0x4188
-#define GPIO_NC_7_PCONF0 0x4190
-#define GPIO_NC_7_PAD 0x4198
-#define GPIO_NC_8_PCONF0 0x4170
-#define GPIO_NC_8_PAD 0x4178
-#define GPIO_NC_9_PCONF0 0x4100
-#define GPIO_NC_9_PAD 0x4108
-#define GPIO_NC_10_PCONF0 0x40E0
-#define GPIO_NC_10_PAD 0x40E8
-#define GPIO_NC_11_PCONF0 0x40F0
-#define GPIO_NC_11_PAD 0x40F8
+#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
+#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
+#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
+#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
+#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
+#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
+#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
+#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
+#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
+#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
+#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
+#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
+#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
+#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
+#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
+#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
+#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
+#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
+#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
+#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
+#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
+#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
+#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
+#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
+#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
+#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
+#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
+#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
+#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
+#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
+#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
+
+#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
+#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
+#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
+#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
+#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
+#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
+#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
+#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
+#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
+#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
+#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
+#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
+#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
+#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
+#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
+#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
+#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
+#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
+#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
+#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
+#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
+#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
+#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
+#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
+#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
+#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
+#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
+#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
+#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
+#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
+#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
+#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
+#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
+#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
+#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
+#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
+#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
+#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
+#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
+#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
+#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
+#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
+#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
+#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
+#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
+#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
+#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
+#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
+#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
+#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
+#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
+#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
+#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
+#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
+#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
+#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
+#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
+#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
+#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
+#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
+#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
+#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
+#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
+#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
+#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
+#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
+#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
+#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
+#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
+#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
+#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
+#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
+#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
+#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
+#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
+#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
+#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
+#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
+#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
+#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
+#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
+#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
+#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
+#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
+#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
+#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
+#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
+#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
+#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
+#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
+#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
+#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
+#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
+#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
+#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
+#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
+#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
+#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
+#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
+#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
+#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
+#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
+#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
+#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
+#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
+#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
+#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
+#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
+#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
+#define VLV_SPKR_GPIOC_54_PAD 0x4678
+#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
+#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
+#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
+#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
+#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
+#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
+#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
+#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
+#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
+#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
+#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
+#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
+#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
+#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
+#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
+#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
+#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
+#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
+#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
+#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
+#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
+#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
+#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
+#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
+#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
+#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
+#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
+#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
+#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
+#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
+#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
+#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
+#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
+#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
+#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
+#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
+#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
+#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
+#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
+#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
+#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
+#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
+#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
+#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
+#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
+#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
+#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
+#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
+#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
+#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
+#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
+#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
+#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
+#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
+#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
+#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
+#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
+#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
+#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
+#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
+#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
+#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
+#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
+#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
+#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
+#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
+#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
+#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
+#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
+#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
+#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
+#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
+#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
+#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
+#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
+#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
+#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
+#define VLV_PWM0_GPIOC_94_PAD 0x40A8
+#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
+#define VLV_PWM1_GPIOC_95_PAD 0x40B8
+#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
+#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
+#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
+#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
+#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
+#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
+#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
+#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
+#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
+#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
+#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
+#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
+
+#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
+#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
+#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
+#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
+#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
+#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
+#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
+#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
+#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
+#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
+#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
+#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
+#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
+#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
+#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
+#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
+#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
+#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
+#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
+#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
+#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
+#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
+#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
+#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
+#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
+#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
+#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
+#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
+#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
+#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
+#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
+#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
+#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
+#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
+#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
+#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
+#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
+#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
+#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
+#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
+#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
+#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
+#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
+#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
+#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
+#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
+#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
+#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
+#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
+#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
+#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
+#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
+#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
+#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
+#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
+#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
+#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
+#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
+#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
+#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
+#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
+#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
+#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
+#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
+#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
+#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
+#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
+#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
+#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
+#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
+#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
+#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
+#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
+#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
+#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
+#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
+#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
+#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
+#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
+#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
+#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
+#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
+#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
+#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
+#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
+#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
+#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
+#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
struct gpio_table {
u16 function_reg;
@@ -90,18 +416,181 @@ struct gpio_table {
};
static struct gpio_table gtable[] = {
- { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
- { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
- { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
- { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
- { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
- { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
- { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
- { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
- { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
- { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
- { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
- { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
+ { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0, VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
+ { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
+ { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
+ { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0, VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
+ { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0, VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
+ { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0, VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
+ { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0, VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
+ { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
+ { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
+ { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0, VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
+ { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0, VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
+ { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0, VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
+ { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0, VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
+ { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
+ { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
+ { VLV_GP_CAMERASB00_GPIONC_15_PCONF0, VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
+ { VLV_GP_CAMERASB01_GPIONC_16_PCONF0, VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
+ { VLV_GP_CAMERASB02_GPIONC_17_PCONF0, VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
+ { VLV_GP_CAMERASB03_GPIONC_18_PCONF0, VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
+ { VLV_GP_CAMERASB04_GPIONC_19_PCONF0, VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
+ { VLV_GP_CAMERASB05_GPIONC_20_PCONF0, VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
+ { VLV_GP_CAMERASB06_GPIONC_21_PCONF0, VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
+ { VLV_GP_CAMERASB07_GPIONC_22_PCONF0, VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
+ { VLV_GP_CAMERASB08_GPIONC_23_PCONF0, VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
+ { VLV_GP_CAMERASB09_GPIONC_24_PCONF0, VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
+ { VLV_GP_CAMERASB10_GPIONC_25_PCONF0, VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
+ { VLV_GP_CAMERASB11_GPIONC_26_PCONF0, VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
+
+ { VLV_SATA_GP0_GPIOC_0_PCONF0, VLV_SATA_GP0_GPIOC_0_PAD, 0},
+ { VLV_SATA_GP1_GPIOC_1_PCONF0, VLV_SATA_GP1_GPIOC_1_PAD, 0},
+ { VLV_SATA_LEDN_GPIOC_2_PCONF0, VLV_SATA_LEDN_GPIOC_2_PAD, 0},
+ { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0, VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
+ { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0, VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
+ { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0, VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
+ { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0, VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
+ { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0, VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
+ { VLV_HDA_RSTB_GPIOC_8_PCONF0, VLV_HDA_RSTB_GPIOC_8_PAD, 0},
+ { VLV_HDA_SYNC_GPIOC_9_PCONF0, VLV_HDA_SYNC_GPIOC_9_PAD, 0},
+ { VLV_HDA_CLK_GPIOC_10_PCONF0, VLV_HDA_CLK_GPIOC_10_PAD, 0},
+ { VLV_HDA_SDO_GPIOC_11_PCONF0, VLV_HDA_SDO_GPIOC_11_PAD, 0},
+ { VLV_HDA_SDI0_GPIOC_12_PCONF0, VLV_HDA_SDI0_GPIOC_12_PAD, 0},
+ { VLV_HDA_SDI1_GPIOC_13_PCONF0, VLV_HDA_SDI1_GPIOC_13_PAD, 0},
+ { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0, VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
+ { VLV_HDA_DOCKENB_GPIOC_15_PCONF0, VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
+ { VLV_SDMMC1_CLK_GPIOC_16_PCONF0, VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
+ { VLV_SDMMC1_D0_GPIOC_17_PCONF0, VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
+ { VLV_SDMMC1_D1_GPIOC_18_PCONF0, VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
+ { VLV_SDMMC1_D2_GPIOC_19_PCONF0, VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
+ { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0, VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
+ { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0, VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
+ { VLV_MMC1_D5_GPIOC_22_PCONF0, VLV_MMC1_D5_GPIOC_22_PAD, 0},
+ { VLV_MMC1_D6_GPIOC_23_PCONF0, VLV_MMC1_D6_GPIOC_23_PAD, 0},
+ { VLV_MMC1_D7_GPIOC_24_PCONF0, VLV_MMC1_D7_GPIOC_24_PAD, 0},
+ { VLV_SDMMC1_CMD_GPIOC_25_PCONF0, VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
+ { VLV_MMC1_RESET_B_GPIOC_26_PCONF0, VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
+ { VLV_SDMMC2_CLK_GPIOC_27_PCONF0, VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
+ { VLV_SDMMC2_D0_GPIOC_28_PCONF0, VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
+ { VLV_SDMMC2_D1_GPIOC_29_PCONF0, VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
+ { VLV_SDMMC2_D2_GPIOC_30_PCONF0, VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
+ { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0, VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
+ { VLV_SDMMC2_CMD_GPIOC_32_PCONF0, VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
+ { VLV_SDMMC3_CLK_GPIOC_33_PCONF0, VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
+ { VLV_SDMMC3_D0_GPIOC_34_PCONF0, VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
+ { VLV_SDMMC3_D1_GPIOC_35_PCONF0, VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
+ { VLV_SDMMC3_D2_GPIOC_36_PCONF0, VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
+ { VLV_SDMMC3_D3_GPIOC_37_PCONF0, VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
+ { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0, VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
+ { VLV_SDMMC3_CMD_GPIOC_39_PCONF0, VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
+ { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0, VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
+ { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
+ { VLV_LPC_AD0_GPIOC_42_PCONF0, VLV_LPC_AD0_GPIOC_42_PAD, 0},
+ { VLV_LPC_AD1_GPIOC_43_PCONF0, VLV_LPC_AD1_GPIOC_43_PAD, 0},
+ { VLV_LPC_AD2_GPIOC_44_PCONF0, VLV_LPC_AD2_GPIOC_44_PAD, 0},
+ { VLV_LPC_AD3_GPIOC_45_PCONF0, VLV_LPC_AD3_GPIOC_45_PAD, 0},
+ { VLV_LPC_FRAMEB_GPIOC_46_PCONF0, VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
+ { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0, VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
+ { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0, VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
+ { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0, VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
+ { VLV_ILB_SERIRQ_GPIOC_50_PCONF0, VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
+ { VLV_SMB_DATA_GPIOC_51_PCONF0, VLV_SMB_DATA_GPIOC_51_PAD, 0},
+ { VLV_SMB_CLK_GPIOC_52_PCONF0, VLV_SMB_CLK_GPIOC_52_PAD, 0},
+ { VLV_SMB_ALERTB_GPIOC_53_PCONF0, VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
+ { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
+ { VLV_MHSI_ACDATA_GPIOC_55_PCONF0, VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
+ { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0, VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
+ { VLV_MHSI_ACREADY_GPIOC_57_PCONF0, VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
+ { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0, VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
+ { VLV_MHSI_CADATA_GPIOC_59_PCONF0, VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
+ { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0, VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
+ { VLV_MHSI_CAREADY_GPIOC_61_PCONF0, VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
+ { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0, VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
+ { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0, VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
+ { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0, VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
+ { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0, VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
+ { VLV_SPI1_CS0_B_GPIOC_66_PCONF0, VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
+ { VLV_SPI1_MISO_GPIOC_67_PCONF0, VLV_SPI1_MISO_GPIOC_67_PAD, 0},
+ { VLV_SPI1_MOSI_GPIOC_68_PCONF0, VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
+ { VLV_SPI1_CLK_GPIOC_69_PCONF0, VLV_SPI1_CLK_GPIOC_69_PAD, 0},
+ { VLV_UART1_RXD_GPIOC_70_PCONF0, VLV_UART1_RXD_GPIOC_70_PAD, 0},
+ { VLV_UART1_TXD_GPIOC_71_PCONF0, VLV_UART1_TXD_GPIOC_71_PAD, 0},
+ { VLV_UART1_RTS_B_GPIOC_72_PCONF0, VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
+ { VLV_UART1_CTS_B_GPIOC_73_PCONF0, VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
+ { VLV_UART2_RXD_GPIOC_74_PCONF0, VLV_UART2_RXD_GPIOC_74_PAD, 0},
+ { VLV_UART2_TXD_GPIOC_75_PCONF0, VLV_UART2_TXD_GPIOC_75_PAD, 0},
+ { VLV_UART2_RTS_B_GPIOC_76_PCONF0, VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
+ { VLV_UART2_CTS_B_GPIOC_77_PCONF0, VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
+ { VLV_I2C0_SDA_GPIOC_78_PCONF0, VLV_I2C0_SDA_GPIOC_78_PAD, 0},
+ { VLV_I2C0_SCL_GPIOC_79_PCONF0, VLV_I2C0_SCL_GPIOC_79_PAD, 0},
+ { VLV_I2C1_SDA_GPIOC_80_PCONF0, VLV_I2C1_SDA_GPIOC_80_PAD, 0},
+ { VLV_I2C1_SCL_GPIOC_81_PCONF0, VLV_I2C1_SCL_GPIOC_81_PAD, 0},
+ { VLV_I2C2_SDA_GPIOC_82_PCONF0, VLV_I2C2_SDA_GPIOC_82_PAD, 0},
+ { VLV_I2C2_SCL_GPIOC_83_PCONF0, VLV_I2C2_SCL_GPIOC_83_PAD, 0},
+ { VLV_I2C3_SDA_GPIOC_84_PCONF0, VLV_I2C3_SDA_GPIOC_84_PAD, 0},
+ { VLV_I2C3_SCL_GPIOC_85_PCONF0, VLV_I2C3_SCL_GPIOC_85_PAD, 0},
+ { VLV_I2C4_SDA_GPIOC_86_PCONF0, VLV_I2C4_SDA_GPIOC_86_PAD, 0},
+ { VLV_I2C4_SCL_GPIOC_87_PCONF0, VLV_I2C4_SCL_GPIOC_87_PAD, 0},
+ { VLV_I2C5_SDA_GPIOC_88_PCONF0, VLV_I2C5_SDA_GPIOC_88_PAD, 0},
+ { VLV_I2C5_SCL_GPIOC_89_PCONF0, VLV_I2C5_SCL_GPIOC_89_PAD, 0},
+ { VLV_I2C6_SDA_GPIOC_90_PCONF0, VLV_I2C6_SDA_GPIOC_90_PAD, 0},
+ { VLV_I2C6_SCL_GPIOC_91_PCONF0, VLV_I2C6_SCL_GPIOC_91_PAD, 0},
+ { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0, VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
+ { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0, VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
+ { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
+ { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
+ { VLV_PLT_CLK0_GPIOC_96_PCONF0, VLV_PLT_CLK0_GPIOC_96_PAD, 0},
+ { VLV_PLT_CLK1_GPIOC_97_PCONF0, VLV_PLT_CLK1_GPIOC_97_PAD, 0},
+ { VLV_PLT_CLK2_GPIOC_98_PCONF0, VLV_PLT_CLK2_GPIOC_98_PAD, 0},
+ { VLV_PLT_CLK3_GPIOC_99_PCONF0, VLV_PLT_CLK3_GPIOC_99_PAD, 0},
+ { VLV_PLT_CLK4_GPIOC_100_PCONF0, VLV_PLT_CLK4_GPIOC_100_PAD, 0},
+ { VLV_PLT_CLK5_GPIOC_101_PCONF0, VLV_PLT_CLK5_GPIOC_101_PAD, 0},
+
+ { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0, VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
+ { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0, VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
+ { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0, VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
+ { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0, VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
+ { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0, VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
+ { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0, VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
+ { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0, VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
+ { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0, VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
+ { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
+ { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
+ { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
+ { VLV_SUSPWRDNACK_GPIOS_11_PCONF0, VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
+ { VLV_PMU_SUSCLK_GPIOS_12_PCONF0, VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
+ { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0, VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
+ { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0, VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
+ { VLV_PMU_WAKE_B_GPIOS_15_PCONF0, VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
+ { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0, VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
+ { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0, VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
+ { VLV_SUS_STAT_B_GPIOS_18_PCONF0, VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
+ { VLV_USB_OC0_B_GPIOS_19_PCONF0, VLV_USB_OC0_B_GPIOS_19_PAD, 0},
+ { VLV_USB_OC1_B_GPIOS_20_PCONF0, VLV_USB_OC1_B_GPIOS_20_PAD, 0},
+ { VLV_SPI_CS1_B_GPIOS_21_PCONF0, VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
+ { VLV_GPIO_DFX0_GPIOS_22_PCONF0, VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
+ { VLV_GPIO_DFX1_GPIOS_23_PCONF0, VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
+ { VLV_GPIO_DFX2_GPIOS_24_PCONF0, VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
+ { VLV_GPIO_DFX3_GPIOS_25_PCONF0, VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
+ { VLV_GPIO_DFX4_GPIOS_26_PCONF0, VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
+ { VLV_GPIO_DFX5_GPIOS_27_PCONF0, VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
+ { VLV_GPIO_DFX6_GPIOS_28_PCONF0, VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
+ { VLV_GPIO_DFX7_GPIOS_29_PCONF0, VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
+ { VLV_GPIO_DFX8_GPIOS_30_PCONF0, VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
+ { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0, VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
+ { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0, VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
+ { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0, VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
+ { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0, VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
+ { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0, VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
+ { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0, VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
+ { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0, VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
+ { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0, VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
+ { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0, VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
+ { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0, VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
+ { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0, VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
+ { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0, VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
+ { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
};
static inline enum port intel_dsi_seq_port_to_port(u8 port)
@@ -201,9 +690,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
u8 gpio, action;
u16 function, pad;
u32 val;
+ u8 port;
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
+ /*
+ * Skipping the first byte as it is of no
+ * interest for android in new version
+ */
if (dev_priv->vbt.dsi.seq_version >= 3)
data++;
@@ -212,19 +708,24 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */
action = *data++ & 1;
- if (gpio >= ARRAY_SIZE(gtable)) {
- DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
- goto out;
- }
-
- if (!IS_VALLEYVIEW(dev_priv)) {
- DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
- goto out;
- }
-
if (dev_priv->vbt.dsi.seq_version >= 3) {
- DRM_DEBUG_KMS("GPIO element v3 not supported\n");
- goto out;
+ if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
+ DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+ port = IOSF_PORT_GPIO_NC;
+ } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
+ gpio <= IOSF_MAX_GPIO_NUM_SC) {
+ DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
+ port = IOSF_PORT_GPIO_SC;
+ } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
+ gpio <= IOSF_MAX_GPIO_NUM) {
+ DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
+ port = IOSF_PORT_GPIO_SUS;
+ } else {
+ DRM_ERROR("GPIO number is not present in the table\n");
+ goto out;
+ }
+ } else {
+ port = IOSF_PORT_GPIO_NC;
}
function = gtable[gpio].function_reg;
@@ -233,16 +734,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
mutex_lock(&dev_priv->sb_lock);
if (!gtable[gpio].init) {
/* program the function */
- /* FIXME: remove constant below */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
- 0x2000CC00);
+ vlv_iosf_sb_write(dev_priv, port, function,
+ VLV_GPIO_CFG);
gtable[gpio].init = 1;
}
- val = 0x4 | action;
+ val = VLV_GPIO_INPUT_DIS | action;
/* pull up/down */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
+ vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(&dev_priv->sb_lock);
out:
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
@ 2016-02-19 11:23 ` Deepak M
2016-02-19 13:25 ` Jani Nikula
2016-02-19 11:23 ` [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control Deepak M
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Deepak M @ 2016-02-19 11:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Deepak M
From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 87 +++++++++++++++++++++++++++++-
2 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 606dc71..fc57477 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
#define IOSF_PORT_GPIO_NC 0x13
+#define CHV_IOSF_PORT_GPIO_N 0x13
+#define CHV_IOSF_PORT_GPIO_SE 0x48
+#define CHV_IOSF_PORT_GPIO_SW 0xB2
+#define CHV_IOSF_PORT_GPIO_E 0xA8
+#define CHV_MAX_GPIO_NUM_N 72
+#define CHV_MAX_GPIO_NUM_SE 99
+#define CHV_MAX_GPIO_NUM_SW 197
+#define CHV_MIN_GPIO_NUM_SE 73
+#define CHV_MIN_GPIO_NUM_SW 100
+#define CHV_MIN_GPIO_NUM_E 198
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_FLISDSI 0x1b
@@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_GPIO_CFG 0x2000CC00
#define VLV_GPIO_INPUT_DIS 0x04
+#define CHV_PAD_FMLY_BASE 0x4400
+#define CHV_PAD_FMLY_SIZE 0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
+#define CHV_PAD_CFG_REG_SIZE 0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY 15
+
+#define CHV_GPIO_CFG_UNLOCK 0x00000000
+#define CHV_GPIO_CFG_HIZ 0x00008100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT 1
+
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index e02e5e0..7fd1fae 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -685,7 +685,68 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
return data;
}
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+static int chv_program_gpio(struct intel_dsi *intel_dsi,
+ const u8 *data, const u8 **cur_data)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u8 gpio, action;
+ u16 family_num;
+ u16 function, pad;
+ u8 block;
+
+ /*
+ * Skipping the first byte as it is of no
+ * interest for linux kernel in new VBT version
+ */
+ if (dev_priv->vbt.dsi.seq_version >= 3)
+ data++;
+
+ gpio = *data++;
+
+ /* pull up/down */
+ action = *data++;
+
+ if (dev_priv->vbt.dsi.seq_version >= 3) {
+ if (gpio <= CHV_MAX_GPIO_NUM_N) {
+ block = CHV_IOSF_PORT_GPIO_N;
+ DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+ } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+ block = CHV_IOSF_PORT_GPIO_SE;
+ gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+ DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+ } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+ block = CHV_IOSF_PORT_GPIO_SW;
+ gpio = gpio - CHV_MIN_GPIO_NUM_SW;
+ DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
+ } else {
+ block = CHV_IOSF_PORT_GPIO_E;
+ gpio = gpio - CHV_MIN_GPIO_NUM_E;
+ DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
+ }
+ } else
+ block = IOSF_PORT_GPIO_NC;
+
+ family_num = gpio / CHV_VBT_MAX_PINS_PER_FMLY;
+ gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+ pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+ (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
+ function = pad + CHV_PAD_CFG_REG_SIZE;
+
+ mutex_lock(&dev_priv->sb_lock);
+ vlv_iosf_sb_write(dev_priv, block, function,
+ CHV_GPIO_CFG_UNLOCK);
+ vlv_iosf_sb_write(dev_priv, block, pad, CHV_GPIO_CFG_HIZ |
+ (action << CHV_GPIO_CFG_TX_STATE_SHIFT));
+ mutex_unlock(&dev_priv->sb_lock);
+
+ *cur_data = data;
+
+ return 0;
+}
+
+static int vlv_program_gpio(struct intel_dsi *intel_dsi,
+ const u8 *data, const u8 **cur_data)
{
u8 gpio, action;
u16 function, pad;
@@ -746,6 +807,30 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
mutex_unlock(&dev_priv->sb_lock);
out:
+ *cur_data = data;
+
+ return 0;
+}
+
+static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ int ret;
+
+ DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
+ ret = -EINVAL;
+
+ if (IS_CHERRYVIEW(dev))
+ ret = chv_program_gpio(intel_dsi, data, &data);
+ else if (IS_VALLEYVIEW(dev))
+ ret = vlv_program_gpio(intel_dsi, data, &data);
+ else
+ DRM_ERROR("GPIO programming missing for this platform.\n");
+
+ if (ret)
+ return NULL;
+
return data;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
2016-02-19 11:23 ` [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI Deepak M
@ 2016-02-19 11:23 ` Deepak M
2016-02-19 13:34 ` Jani Nikula
2016-02-19 12:14 ` ✓ Fi.CI.BAT: success for series starting with [Generic,GPIO,1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Deepak M @ 2016-02-19 11:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Uma Shankar <uma.shankar@intel.com>
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46 ++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7fd1fae..c6e18fe 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -32,6 +32,7 @@
#include <linux/slab.h>
#include <video/mipi_display.h>
#include <asm/intel-mid.h>
+#include <linux/gpio.h>
#include <video/mipi_display.h>
#include "i915_drv.h"
#include "intel_drv.h"
@@ -593,6 +594,16 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
};
+struct bxt_gpio_table {
+ u16 gpio_pin;
+ u16 offset;
+};
+
+static struct bxt_gpio_table bxt_gtable[] = {
+ {0xC1, 270},
+ {0x1B, 456}
+};
+
static inline enum port intel_dsi_seq_port_to_port(u8 port)
{
return port ? PORT_C : PORT_A;
@@ -812,6 +823,39 @@ out:
return 0;
}
+static int bxt_program_gpio(struct intel_dsi *intel_dsi,
+ const u8 *data, const u8 **cur_data)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u8 gpio, action;
+ u16 function;
+
+ /*
+ * Skipping the first byte as it is of no
+ * interest for android in new version
+ */
+ if (dev_priv->vbt.dsi.seq_version >= 3)
+ data++;
+
+ gpio = *data++;
+
+ /* pull up/down */
+ action = *data++;
+ function = (bxt_gtable[0].gpio_pin == gpio) ?
+ bxt_gtable[0].offset :
+ (bxt_gtable[1].gpio_pin == gpio) ?
+ bxt_gtable[1].offset : 0;
+ if (!function)
+ return -1;
+
+ gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
+ gpio_set_value(function, action);
+
+ *cur_data = data;
+ return 0;
+}
+
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -825,6 +869,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
ret = chv_program_gpio(intel_dsi, data, &data);
else if (IS_VALLEYVIEW(dev))
ret = vlv_program_gpio(intel_dsi, data, &data);
+ else if (IS_BROXTON(dev))
+ ret = bxt_program_gpio(intel_dsi, data, &data);
else
DRM_ERROR("GPIO programming missing for this platform.\n");
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [Generic,GPIO,1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
2016-02-19 11:23 ` [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI Deepak M
2016-02-19 11:23 ` [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control Deepak M
@ 2016-02-19 12:14 ` Patchwork
2016-02-19 13:21 ` [Generic GPIO patch 1/3] " Jani Nikula
` (2 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-02-19 12:14 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Summary ==
Series 3623v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3623/revisions/1/mbox/
Test gem_ctx_param_basic:
Subgroup basic-default:
incomplete -> PASS (snb-x220t)
Subgroup invalid-ctx-get:
incomplete -> PASS (snb-x220t)
Subgroup non-root-set-no-zeromap:
incomplete -> PASS (snb-x220t)
Subgroup root-set:
incomplete -> PASS (snb-x220t)
Subgroup root-set-no-zeromap-disabled:
incomplete -> PASS (snb-x220t)
Subgroup root-set-no-zeromap-enabled:
incomplete -> PASS (snb-x220t)
Test gem_exec_basic:
Subgroup basic-blt:
incomplete -> PASS (snb-x220t)
Test gem_flink_basic:
Subgroup bad-flink:
incomplete -> PASS (snb-x220t)
Test gem_linear_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_mmap:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Subgroup basic-small-bo:
incomplete -> PASS (snb-x220t)
Test gem_mmap_gtt:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Subgroup basic-copy:
incomplete -> PASS (snb-x220t)
Subgroup basic-read-no-prefault:
incomplete -> PASS (snb-x220t)
Subgroup basic-read-write-distinct:
incomplete -> PASS (snb-x220t)
Subgroup basic-write-cpu-read-gtt:
incomplete -> PASS (snb-x220t)
Subgroup basic-write-read-distinct:
incomplete -> PASS (snb-x220t)
Test gem_pread:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_render_linear_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_render_tiled_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_ringfill:
Subgroup basic-default:
incomplete -> PASS (snb-x220t)
Subgroup basic-default-bomb:
incomplete -> PASS (ivb-t430s)
Subgroup basic-default-forked:
incomplete -> PASS (snb-x220t)
Subgroup basic-default-hang:
incomplete -> PASS (snb-x220t)
Test gem_storedw_loop:
Subgroup basic-bsd1:
incomplete -> SKIP (snb-x220t)
Subgroup basic-render:
incomplete -> PASS (snb-x220t)
Subgroup basic-vebox:
incomplete -> SKIP (snb-x220t)
Test gem_sync:
Subgroup basic-blt:
incomplete -> PASS (snb-x220t)
Test gem_tiled_pread_basic:
incomplete -> PASS (snb-x220t)
Test kms_addfb_basic:
Subgroup addfb25-modifier-no-flag:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-0:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-1024:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-128:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-256:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-999:
incomplete -> PASS (snb-x220t)
Subgroup basic-x-tiled:
incomplete -> PASS (snb-x220t)
Subgroup framebuffer-vs-set-tiling:
incomplete -> PASS (snb-x220t)
Subgroup no-handle:
incomplete -> PASS (snb-x220t)
Subgroup size-max:
incomplete -> PASS (snb-x220t)
Subgroup too-wide:
incomplete -> PASS (snb-x220t)
Subgroup unused-handle:
incomplete -> PASS (snb-x220t)
Subgroup unused-modifier:
incomplete -> PASS (snb-x220t)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
incomplete -> PASS (snb-x220t)
Test kms_force_connector_basic:
Subgroup force-load-detect:
dmesg-fail -> FAIL (snb-dellxps)
fail -> DMESG-FAIL (ivb-t430s)
Subgroup prune-stale-modes:
skip -> PASS (snb-x220t)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-c-frame-sequence:
incomplete -> SKIP (snb-x220t)
Subgroup read-crc-pipe-a-frame-sequence:
incomplete -> PASS (snb-x220t)
Subgroup read-crc-pipe-b:
incomplete -> PASS (snb-x220t)
Subgroup read-crc-pipe-c-frame-sequence:
incomplete -> SKIP (snb-x220t)
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (snb-x220t)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-pci-d3-state:
incomplete -> FAIL (snb-x220t)
Subgroup basic-rte:
dmesg-warn -> PASS (byt-nuc) UNSTABLE
Test prime_self_import:
Subgroup basic-with_two_bos:
incomplete -> PASS (snb-x220t)
bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip:14
bsw-nuc-2 total:167 pass:136 dwarn:1 dfail:0 fail:0 skip:30
byt-nuc total:167 pass:142 dwarn:0 dfail:0 fail:0 skip:25
ivb-t430s total:167 pass:152 dwarn:0 dfail:1 fail:0 skip:14
skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
snb-dellxps total:167 pass:144 dwarn:0 dfail:0 fail:1 skip:22
snb-x220t total:167 pass:144 dwarn:0 dfail:0 fail:2 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1443/
e4599905334de9349501a383afb8503a1dde5728 drm-intel-nightly: 2016y-02m-18d-17h-13m-22s UTC integration manifest
d5e09008c6199940b5e81cee17591095a3e2d10b drm/i915: BXT GPIO support for backlight and panel control
eaa99cb0836c1b52711da3d8a534afc2cacb8733 drm/i915: GPIO for CHT generic MIPI
ba7400b32c3e4e81b563181fc40736bdf3d6f582 drm/i915/dsi: Added the generic gpio sequence support and gpio table
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
` (2 preceding siblings ...)
2016-02-19 12:14 ` ✓ Fi.CI.BAT: success for series starting with [Generic,GPIO,1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Patchwork
@ 2016-02-19 13:21 ` Jani Nikula
2016-02-19 13:31 ` Deepak, M
2016-02-19 15:15 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev2) Patchwork
2016-02-22 13:47 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev4) Patchwork
5 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2016-02-19 13:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Fri, 19 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> The generic gpio is sequence is parsed from the VBT and the
> GPIO table is updated with the North core, South core and
> SUS core elements.
>
> v2: Move changes in sideband.c file to new patch(Jani), rebase
> v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
>
> v3 by Jani
> - rebase on previous patches
> - don't return null on errors
>
> v4 by Deepak
> - rebase
> - prefixed the VLV_ to all the GPIO macros
There were also versions 4, 5 and 6 by me also. v6 is at
http://patchwork.freedesktop.org/patch/msgid/f684304ca297fd3dd325c29a541b8960fe468b96.1454582914.git.jani.nikula@intel.com
You should take that as the basis.
Also see comments inline.
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 +
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606 ++++++++++++++++++++++++++---
> 2 files changed, 559 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3774870..606dc71 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_FLISDSI 0x1b
> #define IOSF_PORT_GPIO_SC 0x48
> #define IOSF_PORT_GPIO_SUS 0xa8
> +#define IOSF_MAX_GPIO_NUM_NC 26
> +#define IOSF_MAX_GPIO_NUM_SC 128
> +#define IOSF_MAX_GPIO_NUM 172
> #define IOSF_PORT_CCU 0xa9
> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
>
> +#define VLV_GPIO_CFG 0x2000CC00
> +#define VLV_GPIO_INPUT_DIS 0x04
> +
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 787f01c..e02e5e0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
>
> #define NS_KHZ_RATIO 1000000
>
> -#define GPI0_NC_0_HV_DDI0_HPD 0x4130
> -#define GPIO_NC_0_HV_DDI0_PAD 0x4138
> -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
> -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
> -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
> -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
> -#define GPIO_NC_3_PANEL0_VDDEN 0x4140
> -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
> -#define GPIO_NC_4_PANEL0_BLKEN 0x4150
> -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
> -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
> -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
> -#define GPIO_NC_6_PCONF0 0x4180
> -#define GPIO_NC_6_PAD 0x4188
> -#define GPIO_NC_7_PCONF0 0x4190
> -#define GPIO_NC_7_PAD 0x4198
> -#define GPIO_NC_8_PCONF0 0x4170
> -#define GPIO_NC_8_PAD 0x4178
> -#define GPIO_NC_9_PCONF0 0x4100
> -#define GPIO_NC_9_PAD 0x4108
> -#define GPIO_NC_10_PCONF0 0x40E0
> -#define GPIO_NC_10_PAD 0x40E8
> -#define GPIO_NC_11_PCONF0 0x40F0
> -#define GPIO_NC_11_PAD 0x40F8
> +#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
> +#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
> +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
> +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
> +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
> +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
> +#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
> +#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
> +#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
> +#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
> +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
> +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
> +#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
> +#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
> +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
> +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
> +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
> +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
> +#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
> +#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
> +#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
> +#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
> +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
> +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
> +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
> +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
> +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
> +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
> +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
> +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
> +#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
> +#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
> +#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
> +#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
> +#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
> +#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
> +#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
> +#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
> +#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
> +#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
> +#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
> +#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
> +#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
> +#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
> +#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
> +#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
> +#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
> +#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
> +#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
> +#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
> +#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
> +#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
> +#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
> +#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
> +
> +#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
> +#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
> +#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
> +#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
> +#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
> +#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
> +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
> +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
> +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
> +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
> +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
> +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
> +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
> +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
> +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
> +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
> +#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
> +#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
> +#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
> +#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
> +#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
> +#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
> +#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
> +#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
> +#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
> +#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
> +#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
> +#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
> +#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
> +#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
> +#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
> +#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
> +#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
> +#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
> +#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
> +#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
> +#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
> +#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
> +#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
> +#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
> +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
> +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
> +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
> +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
> +#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
> +#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
> +#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
> +#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
> +#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
> +#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
> +#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
> +#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
> +#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
> +#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
> +#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
> +#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
> +#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
> +#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
> +#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
> +#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
> +#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
> +#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
> +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
> +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
> +#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
> +#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
> +#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
> +#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
> +#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
> +#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
> +#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
> +#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
> +#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
> +#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
> +#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
> +#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
> +#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
> +#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
> +#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
> +#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
> +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
> +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
> +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
> +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
> +#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
> +#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
> +#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
> +#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
> +#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
> +#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
> +#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
> +#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
> +#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
> +#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
> +#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
> +#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
> +#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
> +#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
> +#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
> +#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
> +#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
> +#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
> +#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
> +#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
> +#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
> +#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
> +#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
> +#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
> +#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
> +#define VLV_SPKR_GPIOC_54_PAD 0x4678
> +#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
> +#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
> +#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
> +#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
> +#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
> +#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
> +#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
> +#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
> +#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
> +#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
> +#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
> +#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
> +#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
> +#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
> +#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
> +#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
> +#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
> +#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
> +#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
> +#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
> +#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
> +#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
> +#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
> +#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
> +#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
> +#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
> +#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
> +#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
> +#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
> +#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
> +#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
> +#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
> +#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
> +#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
> +#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
> +#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
> +#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
> +#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
> +#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
> +#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
> +#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
> +#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
> +#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
> +#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
> +#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
> +#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
> +#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
> +#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
> +#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
> +#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
> +#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
> +#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
> +#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
> +#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
> +#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
> +#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
> +#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
> +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
> +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
> +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
> +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
> +#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
> +#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
> +#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
> +#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
> +#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
> +#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
> +#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
> +#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
> +#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
> +#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
> +#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
> +#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
> +#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
> +#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
> +#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
> +#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
> +#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
> +#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
> +#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
> +#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
> +#define VLV_PWM0_GPIOC_94_PAD 0x40A8
> +#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
> +#define VLV_PWM1_GPIOC_95_PAD 0x40B8
> +#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
> +#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
> +#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
> +#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
> +#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
> +#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
> +#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
> +#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
> +#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
> +#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
> +#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
> +#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
> +
> +#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
> +#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
> +#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
> +#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
> +#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
> +#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
> +#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
> +#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
> +#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
> +#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
> +#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
> +#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
> +#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
> +#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
> +#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
> +#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
> +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
> +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
> +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
> +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
> +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
> +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
> +#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
> +#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
> +#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
> +#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
> +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
> +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
> +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
> +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
> +#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
> +#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
> +#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
> +#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
> +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
> +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
> +#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
> +#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
> +#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
> +#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
> +#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
> +#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
> +#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
> +#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
> +#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
> +#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
> +#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
> +#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
> +#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
> +#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
> +#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
> +#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
> +#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
> +#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
> +#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
> +#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
> +#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
> +#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
> +#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
> +#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
> +#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
> +#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
> +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
> +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
> +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
> +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
> +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
> +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
> +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
> +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
> +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
> +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
> +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
> +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
> +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
> +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
> +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
> +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
> +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
> +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
> +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
> +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
> +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
> +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
> +#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
> +#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
> +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
> +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
>
> struct gpio_table {
> u16 function_reg;
> @@ -90,18 +416,181 @@ struct gpio_table {
> };
>
> static struct gpio_table gtable[] = {
> - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
> - { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
> - { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
> - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
> - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
> - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
> - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
> - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
> - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
> - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
> - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
> - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
> + { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0, VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
> + { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
> + { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
> + { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0, VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
> + { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0, VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
> + { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0, VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
> + { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0, VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
> + { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
> + { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
> + { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0, VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
> + { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0, VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
> + { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0, VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
> + { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0, VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
> + { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
> + { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
> + { VLV_GP_CAMERASB00_GPIONC_15_PCONF0, VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
> + { VLV_GP_CAMERASB01_GPIONC_16_PCONF0, VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
> + { VLV_GP_CAMERASB02_GPIONC_17_PCONF0, VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
> + { VLV_GP_CAMERASB03_GPIONC_18_PCONF0, VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
> + { VLV_GP_CAMERASB04_GPIONC_19_PCONF0, VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
> + { VLV_GP_CAMERASB05_GPIONC_20_PCONF0, VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
> + { VLV_GP_CAMERASB06_GPIONC_21_PCONF0, VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
> + { VLV_GP_CAMERASB07_GPIONC_22_PCONF0, VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
> + { VLV_GP_CAMERASB08_GPIONC_23_PCONF0, VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
> + { VLV_GP_CAMERASB09_GPIONC_24_PCONF0, VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
> + { VLV_GP_CAMERASB10_GPIONC_25_PCONF0, VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
> + { VLV_GP_CAMERASB11_GPIONC_26_PCONF0, VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
> +
> + { VLV_SATA_GP0_GPIOC_0_PCONF0, VLV_SATA_GP0_GPIOC_0_PAD, 0},
> + { VLV_SATA_GP1_GPIOC_1_PCONF0, VLV_SATA_GP1_GPIOC_1_PAD, 0},
> + { VLV_SATA_LEDN_GPIOC_2_PCONF0, VLV_SATA_LEDN_GPIOC_2_PAD, 0},
> + { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0, VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
> + { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0, VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
> + { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0, VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
> + { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0, VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
> + { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0, VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
> + { VLV_HDA_RSTB_GPIOC_8_PCONF0, VLV_HDA_RSTB_GPIOC_8_PAD, 0},
> + { VLV_HDA_SYNC_GPIOC_9_PCONF0, VLV_HDA_SYNC_GPIOC_9_PAD, 0},
> + { VLV_HDA_CLK_GPIOC_10_PCONF0, VLV_HDA_CLK_GPIOC_10_PAD, 0},
> + { VLV_HDA_SDO_GPIOC_11_PCONF0, VLV_HDA_SDO_GPIOC_11_PAD, 0},
> + { VLV_HDA_SDI0_GPIOC_12_PCONF0, VLV_HDA_SDI0_GPIOC_12_PAD, 0},
> + { VLV_HDA_SDI1_GPIOC_13_PCONF0, VLV_HDA_SDI1_GPIOC_13_PAD, 0},
> + { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0, VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
> + { VLV_HDA_DOCKENB_GPIOC_15_PCONF0, VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
> + { VLV_SDMMC1_CLK_GPIOC_16_PCONF0, VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
> + { VLV_SDMMC1_D0_GPIOC_17_PCONF0, VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
> + { VLV_SDMMC1_D1_GPIOC_18_PCONF0, VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
> + { VLV_SDMMC1_D2_GPIOC_19_PCONF0, VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
> + { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0, VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
> + { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0, VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
> + { VLV_MMC1_D5_GPIOC_22_PCONF0, VLV_MMC1_D5_GPIOC_22_PAD, 0},
> + { VLV_MMC1_D6_GPIOC_23_PCONF0, VLV_MMC1_D6_GPIOC_23_PAD, 0},
> + { VLV_MMC1_D7_GPIOC_24_PCONF0, VLV_MMC1_D7_GPIOC_24_PAD, 0},
> + { VLV_SDMMC1_CMD_GPIOC_25_PCONF0, VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
> + { VLV_MMC1_RESET_B_GPIOC_26_PCONF0, VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
> + { VLV_SDMMC2_CLK_GPIOC_27_PCONF0, VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
> + { VLV_SDMMC2_D0_GPIOC_28_PCONF0, VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
> + { VLV_SDMMC2_D1_GPIOC_29_PCONF0, VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
> + { VLV_SDMMC2_D2_GPIOC_30_PCONF0, VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
> + { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0, VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
> + { VLV_SDMMC2_CMD_GPIOC_32_PCONF0, VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
> + { VLV_SDMMC3_CLK_GPIOC_33_PCONF0, VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
> + { VLV_SDMMC3_D0_GPIOC_34_PCONF0, VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
> + { VLV_SDMMC3_D1_GPIOC_35_PCONF0, VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
> + { VLV_SDMMC3_D2_GPIOC_36_PCONF0, VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
> + { VLV_SDMMC3_D3_GPIOC_37_PCONF0, VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
> + { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0, VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
> + { VLV_SDMMC3_CMD_GPIOC_39_PCONF0, VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
> + { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0, VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
> + { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
> + { VLV_LPC_AD0_GPIOC_42_PCONF0, VLV_LPC_AD0_GPIOC_42_PAD, 0},
> + { VLV_LPC_AD1_GPIOC_43_PCONF0, VLV_LPC_AD1_GPIOC_43_PAD, 0},
> + { VLV_LPC_AD2_GPIOC_44_PCONF0, VLV_LPC_AD2_GPIOC_44_PAD, 0},
> + { VLV_LPC_AD3_GPIOC_45_PCONF0, VLV_LPC_AD3_GPIOC_45_PAD, 0},
> + { VLV_LPC_FRAMEB_GPIOC_46_PCONF0, VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
> + { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0, VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
> + { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0, VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
> + { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0, VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
> + { VLV_ILB_SERIRQ_GPIOC_50_PCONF0, VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
> + { VLV_SMB_DATA_GPIOC_51_PCONF0, VLV_SMB_DATA_GPIOC_51_PAD, 0},
> + { VLV_SMB_CLK_GPIOC_52_PCONF0, VLV_SMB_CLK_GPIOC_52_PAD, 0},
> + { VLV_SMB_ALERTB_GPIOC_53_PCONF0, VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
> + { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
> + { VLV_MHSI_ACDATA_GPIOC_55_PCONF0, VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
> + { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0, VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
> + { VLV_MHSI_ACREADY_GPIOC_57_PCONF0, VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
> + { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0, VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
> + { VLV_MHSI_CADATA_GPIOC_59_PCONF0, VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
> + { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0, VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
> + { VLV_MHSI_CAREADY_GPIOC_61_PCONF0, VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
> + { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0, VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
> + { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0, VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
> + { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0, VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
> + { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0, VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
> + { VLV_SPI1_CS0_B_GPIOC_66_PCONF0, VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
> + { VLV_SPI1_MISO_GPIOC_67_PCONF0, VLV_SPI1_MISO_GPIOC_67_PAD, 0},
> + { VLV_SPI1_MOSI_GPIOC_68_PCONF0, VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
> + { VLV_SPI1_CLK_GPIOC_69_PCONF0, VLV_SPI1_CLK_GPIOC_69_PAD, 0},
> + { VLV_UART1_RXD_GPIOC_70_PCONF0, VLV_UART1_RXD_GPIOC_70_PAD, 0},
> + { VLV_UART1_TXD_GPIOC_71_PCONF0, VLV_UART1_TXD_GPIOC_71_PAD, 0},
> + { VLV_UART1_RTS_B_GPIOC_72_PCONF0, VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
> + { VLV_UART1_CTS_B_GPIOC_73_PCONF0, VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
> + { VLV_UART2_RXD_GPIOC_74_PCONF0, VLV_UART2_RXD_GPIOC_74_PAD, 0},
> + { VLV_UART2_TXD_GPIOC_75_PCONF0, VLV_UART2_TXD_GPIOC_75_PAD, 0},
> + { VLV_UART2_RTS_B_GPIOC_76_PCONF0, VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
> + { VLV_UART2_CTS_B_GPIOC_77_PCONF0, VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
> + { VLV_I2C0_SDA_GPIOC_78_PCONF0, VLV_I2C0_SDA_GPIOC_78_PAD, 0},
> + { VLV_I2C0_SCL_GPIOC_79_PCONF0, VLV_I2C0_SCL_GPIOC_79_PAD, 0},
> + { VLV_I2C1_SDA_GPIOC_80_PCONF0, VLV_I2C1_SDA_GPIOC_80_PAD, 0},
> + { VLV_I2C1_SCL_GPIOC_81_PCONF0, VLV_I2C1_SCL_GPIOC_81_PAD, 0},
> + { VLV_I2C2_SDA_GPIOC_82_PCONF0, VLV_I2C2_SDA_GPIOC_82_PAD, 0},
> + { VLV_I2C2_SCL_GPIOC_83_PCONF0, VLV_I2C2_SCL_GPIOC_83_PAD, 0},
> + { VLV_I2C3_SDA_GPIOC_84_PCONF0, VLV_I2C3_SDA_GPIOC_84_PAD, 0},
> + { VLV_I2C3_SCL_GPIOC_85_PCONF0, VLV_I2C3_SCL_GPIOC_85_PAD, 0},
> + { VLV_I2C4_SDA_GPIOC_86_PCONF0, VLV_I2C4_SDA_GPIOC_86_PAD, 0},
> + { VLV_I2C4_SCL_GPIOC_87_PCONF0, VLV_I2C4_SCL_GPIOC_87_PAD, 0},
> + { VLV_I2C5_SDA_GPIOC_88_PCONF0, VLV_I2C5_SDA_GPIOC_88_PAD, 0},
> + { VLV_I2C5_SCL_GPIOC_89_PCONF0, VLV_I2C5_SCL_GPIOC_89_PAD, 0},
> + { VLV_I2C6_SDA_GPIOC_90_PCONF0, VLV_I2C6_SDA_GPIOC_90_PAD, 0},
> + { VLV_I2C6_SCL_GPIOC_91_PCONF0, VLV_I2C6_SCL_GPIOC_91_PAD, 0},
> + { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0, VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
> + { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0, VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
> + { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
> + { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
> + { VLV_PLT_CLK0_GPIOC_96_PCONF0, VLV_PLT_CLK0_GPIOC_96_PAD, 0},
> + { VLV_PLT_CLK1_GPIOC_97_PCONF0, VLV_PLT_CLK1_GPIOC_97_PAD, 0},
> + { VLV_PLT_CLK2_GPIOC_98_PCONF0, VLV_PLT_CLK2_GPIOC_98_PAD, 0},
> + { VLV_PLT_CLK3_GPIOC_99_PCONF0, VLV_PLT_CLK3_GPIOC_99_PAD, 0},
> + { VLV_PLT_CLK4_GPIOC_100_PCONF0, VLV_PLT_CLK4_GPIOC_100_PAD, 0},
> + { VLV_PLT_CLK5_GPIOC_101_PCONF0, VLV_PLT_CLK5_GPIOC_101_PAD, 0},
> +
> + { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0, VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
> + { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0, VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
> + { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0, VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
> + { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0, VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
> + { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0, VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
> + { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0, VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
> + { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0, VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
> + { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0, VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
> + { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
> + { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
> + { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
> + { VLV_SUSPWRDNACK_GPIOS_11_PCONF0, VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
> + { VLV_PMU_SUSCLK_GPIOS_12_PCONF0, VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
> + { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0, VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
> + { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0, VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
> + { VLV_PMU_WAKE_B_GPIOS_15_PCONF0, VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
> + { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0, VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
> + { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0, VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
> + { VLV_SUS_STAT_B_GPIOS_18_PCONF0, VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
> + { VLV_USB_OC0_B_GPIOS_19_PCONF0, VLV_USB_OC0_B_GPIOS_19_PAD, 0},
> + { VLV_USB_OC1_B_GPIOS_20_PCONF0, VLV_USB_OC1_B_GPIOS_20_PAD, 0},
> + { VLV_SPI_CS1_B_GPIOS_21_PCONF0, VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
> + { VLV_GPIO_DFX0_GPIOS_22_PCONF0, VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
> + { VLV_GPIO_DFX1_GPIOS_23_PCONF0, VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
> + { VLV_GPIO_DFX2_GPIOS_24_PCONF0, VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
> + { VLV_GPIO_DFX3_GPIOS_25_PCONF0, VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
> + { VLV_GPIO_DFX4_GPIOS_26_PCONF0, VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
> + { VLV_GPIO_DFX5_GPIOS_27_PCONF0, VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
> + { VLV_GPIO_DFX6_GPIOS_28_PCONF0, VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
> + { VLV_GPIO_DFX7_GPIOS_29_PCONF0, VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
> + { VLV_GPIO_DFX8_GPIOS_30_PCONF0, VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
> + { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0, VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
> + { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0, VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
> + { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0, VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
> + { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0, VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
> + { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0, VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
> + { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0, VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
> + { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0, VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
> + { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0, VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
> + { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0, VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
> + { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0, VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
> + { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0, VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
> + { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0, VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
> + { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
> };
>
> static inline enum port intel_dsi_seq_port_to_port(u8 port)
> @@ -201,9 +690,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> u8 gpio, action;
> u16 function, pad;
> u32 val;
> + u8 port;
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> +
> + /*
> + * Skipping the first byte as it is of no
> + * interest for android in new version
> + */
That comment is unnecessary and misleading.
> if (dev_priv->vbt.dsi.seq_version >= 3)
> data++;
>
> @@ -212,19 +708,24 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> /* pull up/down */
> action = *data++ & 1;
>
> - if (gpio >= ARRAY_SIZE(gtable)) {
> - DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> - goto out;
> - }
> -
> - if (!IS_VALLEYVIEW(dev_priv)) {
> - DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> - goto out;
> - }
Both of these checks are needed and added for a reason.
> -
> if (dev_priv->vbt.dsi.seq_version >= 3) {
> - DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> - goto out;
> + if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
> + DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
> + port = IOSF_PORT_GPIO_NC;
> + } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
> + gpio <= IOSF_MAX_GPIO_NUM_SC) {
> + DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
> + port = IOSF_PORT_GPIO_SC;
> + } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
> + gpio <= IOSF_MAX_GPIO_NUM) {
> + DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
> + port = IOSF_PORT_GPIO_SUS;
> + } else {
> + DRM_ERROR("GPIO number is not present in the table\n");
> + goto out;
> + }
> + } else {
> + port = IOSF_PORT_GPIO_NC;
> }
>
> function = gtable[gpio].function_reg;
> @@ -233,16 +734,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> mutex_lock(&dev_priv->sb_lock);
> if (!gtable[gpio].init) {
> /* program the function */
> - /* FIXME: remove constant below */
> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> - 0x2000CC00);
> + vlv_iosf_sb_write(dev_priv, port, function,
> + VLV_GPIO_CFG);
> gtable[gpio].init = 1;
> }
>
> - val = 0x4 | action;
> + val = VLV_GPIO_INPUT_DIS | action;
>
> /* pull up/down */
> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> + vlv_iosf_sb_write(dev_priv, port, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI
2016-02-19 11:23 ` [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI Deepak M
@ 2016-02-19 13:25 ` Jani Nikula
2016-02-22 13:25 ` [GPIO PATCH 1/2] " Deepak M
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2016-02-19 13:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Fri, 19 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
>
> The GPIO configuration and register offsets are different from
> baytrail for cherrytrail. Port the gpio programming accordingly
> for cherrytrail in this patch.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 87 +++++++++++++++++++++++++++++-
> 2 files changed, 106 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 606dc71..fc57477 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_NC 0x11
> #define IOSF_PORT_DPIO 0x12
> #define IOSF_PORT_GPIO_NC 0x13
> +#define CHV_IOSF_PORT_GPIO_N 0x13
> +#define CHV_IOSF_PORT_GPIO_SE 0x48
> +#define CHV_IOSF_PORT_GPIO_SW 0xB2
> +#define CHV_IOSF_PORT_GPIO_E 0xA8
> +#define CHV_MAX_GPIO_NUM_N 72
> +#define CHV_MAX_GPIO_NUM_SE 99
> +#define CHV_MAX_GPIO_NUM_SW 197
> +#define CHV_MIN_GPIO_NUM_SE 73
> +#define CHV_MIN_GPIO_NUM_SW 100
> +#define CHV_MIN_GPIO_NUM_E 198
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> @@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_GPIO_CFG 0x2000CC00
> #define VLV_GPIO_INPUT_DIS 0x04
>
> +#define CHV_PAD_FMLY_BASE 0x4400
> +#define CHV_PAD_FMLY_SIZE 0x400
> +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
> +#define CHV_PAD_CFG_REG_SIZE 0x4
> +#define CHV_VBT_MAX_PINS_PER_FMLY 15
> +
> +#define CHV_GPIO_CFG_UNLOCK 0x00000000
> +#define CHV_GPIO_CFG_HIZ 0x00008100
> +#define CHV_GPIO_CFG_TX_STATE_SHIFT 1
> +
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index e02e5e0..7fd1fae 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -685,7 +685,68 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
> return data;
> }
>
> -static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> +static int chv_program_gpio(struct intel_dsi *intel_dsi,
> + const u8 *data, const u8 **cur_data)
> +{
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u8 gpio, action;
> + u16 family_num;
> + u16 function, pad;
> + u8 block;
> +
> + /*
> + * Skipping the first byte as it is of no
> + * interest for linux kernel in new VBT version
> + */
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
> + gpio = *data++;
> +
> + /* pull up/down */
> + action = *data++;
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> + if (gpio <= CHV_MAX_GPIO_NUM_N) {
> + block = CHV_IOSF_PORT_GPIO_N;
> + DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
> + } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
> + block = CHV_IOSF_PORT_GPIO_SE;
> + gpio = gpio - CHV_MIN_GPIO_NUM_SE;
> + DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
> + } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
> + block = CHV_IOSF_PORT_GPIO_SW;
> + gpio = gpio - CHV_MIN_GPIO_NUM_SW;
> + DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
> + } else {
> + block = CHV_IOSF_PORT_GPIO_E;
> + gpio = gpio - CHV_MIN_GPIO_NUM_E;
> + DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
> + }
> + } else
> + block = IOSF_PORT_GPIO_NC;
> +
> + family_num = gpio / CHV_VBT_MAX_PINS_PER_FMLY;
> + gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
> + pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
> + (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
> + function = pad + CHV_PAD_CFG_REG_SIZE;
> +
> + mutex_lock(&dev_priv->sb_lock);
> + vlv_iosf_sb_write(dev_priv, block, function,
> + CHV_GPIO_CFG_UNLOCK);
> + vlv_iosf_sb_write(dev_priv, block, pad, CHV_GPIO_CFG_HIZ |
> + (action << CHV_GPIO_CFG_TX_STATE_SHIFT));
> + mutex_unlock(&dev_priv->sb_lock);
> +
> + *cur_data = data;
> +
> + return 0;
> +}
> +
> +static int vlv_program_gpio(struct intel_dsi *intel_dsi,
> + const u8 *data, const u8 **cur_data)
> {
> u8 gpio, action;
> u16 function, pad;
> @@ -746,6 +807,30 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> mutex_unlock(&dev_priv->sb_lock);
>
> out:
> + *cur_data = data;
> +
> + return 0;
> +}
> +
> +static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> +{
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + int ret;
> +
> + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> +
> + ret = -EINVAL;
> +
> + if (IS_CHERRYVIEW(dev))
> + ret = chv_program_gpio(intel_dsi, data, &data);
> + else if (IS_VALLEYVIEW(dev))
> + ret = vlv_program_gpio(intel_dsi, data, &data);
This is the wrong level of abstraction for vlv vs. chv. The input data
is the same for all of them, please don't duplicate the parsing of it
all over the place.
> + else
> + DRM_ERROR("GPIO programming missing for this platform.\n");
Even if you don't know the platform, you can parse the data and skip.
> +
> + if (ret)
> + return NULL;
Even if there are errors, you can parse the data and skip.
> +
> return data;
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-19 13:21 ` [Generic GPIO patch 1/3] " Jani Nikula
@ 2016-02-19 13:31 ` Deepak, M
2016-02-19 13:36 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Deepak, M @ 2016-02-19 13:31 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Nikula, Jani
> Sent: Friday, February 19, 2016 6:51 PM
> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.deepak@intel.com>
> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
> sequence support and gpio table
>
> On Fri, 19 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> > The generic gpio is sequence is parsed from the VBT and the GPIO table
> > is updated with the North core, South core and SUS core elements.
> >
> > v2: Move changes in sideband.c file to new patch(Jani), rebase
> > v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
> >
> > v3 by Jani
> > - rebase on previous patches
> > - don't return null on errors
> >
> > v4 by Deepak
> > - rebase
> > - prefixed the VLV_ to all the GPIO macros
>
> There were also versions 4, 5 and 6 by me also. v6 is at
>
> http://patchwork.freedesktop.org/patch/msgid/f684304ca297fd3dd325c29a
> 541b8960fe468b96.1454582914.git.jani.nikula@intel.com
>
> You should take that as the basis.
[Deepak, M] The link points me to the i2c patch not the gpio one.
>
> Also see comments inline.
>
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 6 +
> > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606
> > ++++++++++++++++++++++++++---
> > 2 files changed, 559 insertions(+), 53 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 3774870..606dc71 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
> reg)
> > #define IOSF_PORT_FLISDSI 0x1b
> > #define IOSF_PORT_GPIO_SC 0x48
> > #define IOSF_PORT_GPIO_SUS 0xa8
> > +#define IOSF_MAX_GPIO_NUM_NC 26
> > +#define IOSF_MAX_GPIO_NUM_SC 128
> > +#define IOSF_MAX_GPIO_NUM 172
> > #define IOSF_PORT_CCU 0xa9
> > #define VLV_IOSF_DATA
> _MMIO(VLV_DISPLAY_BASE + 0x2104)
> > #define VLV_IOSF_ADDR
> _MMIO(VLV_DISPLAY_BASE + 0x2108)
> >
> > +#define VLV_GPIO_CFG 0x2000CC00
> > +#define VLV_GPIO_INPUT_DIS 0x04
> > +
> > /* See configdb bunit SB addr map */
> > #define BUNIT_REG_BISOC 0x11
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 787f01c..e02e5e0 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -58,30 +58,356 @@ static inline struct vbt_panel
> > *to_vbt_panel(struct drm_panel *panel)
> >
> > #define NS_KHZ_RATIO 1000000
> >
> > -#define GPI0_NC_0_HV_DDI0_HPD 0x4130
> > -#define GPIO_NC_0_HV_DDI0_PAD 0x4138
> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
> > -#define GPIO_NC_3_PANEL0_VDDEN 0x4140
> > -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
> > -#define GPIO_NC_4_PANEL0_BLKEN 0x4150
> > -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
> > -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
> > -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
> > -#define GPIO_NC_6_PCONF0 0x4180
> > -#define GPIO_NC_6_PAD 0x4188
> > -#define GPIO_NC_7_PCONF0 0x4190
> > -#define GPIO_NC_7_PAD 0x4198
> > -#define GPIO_NC_8_PCONF0 0x4170
> > -#define GPIO_NC_8_PAD 0x4178
> > -#define GPIO_NC_9_PCONF0 0x4100
> > -#define GPIO_NC_9_PAD 0x4108
> > -#define GPIO_NC_10_PCONF0 0x40E0
> > -#define GPIO_NC_10_PAD 0x40E8
> > -#define GPIO_NC_11_PCONF0 0x40F0
> > -#define GPIO_NC_11_PAD 0x40F8
> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
> > +#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
> > +#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
> > +#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
> > +#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
> > +#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
> > +#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
> > +#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
> > +#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
> > +#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
> > +#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
> > +#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
> > +#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
> > +#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
> > +#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
> > +#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
> > +#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
> > +#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
> > +#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
> > +#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
> > +#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
> > +#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
> > +#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
> > +#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
> > +#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
> > +
> > +#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
> > +#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
> > +#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
> > +#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
> > +#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
> > +#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
> > +#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
> > +#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
> > +#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
> > +#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
> > +#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
> > +#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
> > +#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
> > +#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
> > +#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
> > +#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
> > +#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
> > +#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
> > +#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
> > +#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
> > +#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
> > +#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
> > +#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
> > +#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
> > +#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
> > +#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
> > +#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
> > +#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
> > +#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
> > +#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
> > +#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
> > +#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
> > +#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
> > +#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
> > +#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
> > +#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
> > +#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
> > +#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
> > +#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
> > +#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
> > +#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
> > +#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
> > +#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
> > +#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
> > +#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
> > +#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
> > +#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
> > +#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
> > +#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
> > +#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
> > +#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
> > +#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
> > +#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
> > +#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
> > +#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
> > +#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
> > +#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
> > +#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
> > +#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
> > +#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
> > +#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
> > +#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
> > +#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
> > +#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
> > +#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
> > +#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
> > +#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
> > +#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
> > +#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
> > +#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
> > +#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
> > +#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
> > +#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
> > +#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
> > +#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
> > +#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
> > +#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
> > +#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
> > +#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
> > +#define VLV_SPKR_GPIOC_54_PAD 0x4678
> > +#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
> > +#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
> > +#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
> > +#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
> > +#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
> > +#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
> > +#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
> > +#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
> > +#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
> > +#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
> > +#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
> > +#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
> > +#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
> > +#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
> > +#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
> > +#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
> > +#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
> > +#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
> > +#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
> > +#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
> > +#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
> > +#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
> > +#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
> > +#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
> > +#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
> > +#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
> > +#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
> > +#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
> > +#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
> > +#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
> > +#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
> > +#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
> > +#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
> > +#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
> > +#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
> > +#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
> > +#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
> > +#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
> > +#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
> > +#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
> > +#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
> > +#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
> > +#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
> > +#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
> > +#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
> > +#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
> > +#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
> > +#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
> > +#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
> > +#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
> > +#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
> > +#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
> > +#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
> > +#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
> > +#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
> > +#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
> > +#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
> > +#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
> > +#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
> > +#define VLV_PWM0_GPIOC_94_PAD 0x40A8
> > +#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
> > +#define VLV_PWM1_GPIOC_95_PAD 0x40B8
> > +#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
> > +#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
> > +#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
> > +#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
> > +#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
> > +#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
> > +#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
> > +#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
> > +#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
> > +#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
> > +#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
> > +#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
> > +
> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
> > +#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
> > +#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
> > +#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
> > +#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
> > +#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
> > +#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
> > +#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
> > +#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
> > +#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
> > +#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
> > +#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
> > +#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
> > +#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
> > +#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
> > +#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
> > +#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
> > +#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
> > +#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
> > +#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
> > +#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
> > +#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
> > +#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
> > +#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
> > +#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
> > +#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
> > +#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
> > +#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
> > +#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
> > +#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
> > +#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
> > +#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
> > +#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
> >
> > struct gpio_table {
> > u16 function_reg;
> > @@ -90,18 +416,181 @@ struct gpio_table { };
> >
> > static struct gpio_table gtable[] = {
> > - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
> > - { GPIO_NC_1_HV_DDI0_DDC_SDA,
> GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
> > - { GPIO_NC_2_HV_DDI0_DDC_SCL,
> GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
> > - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD,
> 0 },
> > - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0
> },
> > - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0
> },
> > - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
> > - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
> > - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
> > - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
> > - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
> > - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
> > + { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0,
> VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
> > + { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0,
> VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
> > + { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0,
> VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
> > + { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0,
> VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
> > + { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0,
> VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
> > + { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0,
> VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
> > + { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0,
> VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
> > + { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0,
> VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
> > + { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0,
> VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
> > + { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0,
> VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
> > + { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0,
> VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
> > + { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0,
> VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
> > + { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0,
> VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
> > + { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0,
> VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
> > + { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0,
> VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
> > + { VLV_GP_CAMERASB00_GPIONC_15_PCONF0,
> VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
> > + { VLV_GP_CAMERASB01_GPIONC_16_PCONF0,
> VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
> > + { VLV_GP_CAMERASB02_GPIONC_17_PCONF0,
> VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
> > + { VLV_GP_CAMERASB03_GPIONC_18_PCONF0,
> VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
> > + { VLV_GP_CAMERASB04_GPIONC_19_PCONF0,
> VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
> > + { VLV_GP_CAMERASB05_GPIONC_20_PCONF0,
> VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
> > + { VLV_GP_CAMERASB06_GPIONC_21_PCONF0,
> VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
> > + { VLV_GP_CAMERASB07_GPIONC_22_PCONF0,
> VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
> > + { VLV_GP_CAMERASB08_GPIONC_23_PCONF0,
> VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
> > + { VLV_GP_CAMERASB09_GPIONC_24_PCONF0,
> VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
> > + { VLV_GP_CAMERASB10_GPIONC_25_PCONF0,
> VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
> > + { VLV_GP_CAMERASB11_GPIONC_26_PCONF0,
> > +VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
> > +
> > + { VLV_SATA_GP0_GPIOC_0_PCONF0,
> VLV_SATA_GP0_GPIOC_0_PAD, 0},
> > + { VLV_SATA_GP1_GPIOC_1_PCONF0,
> VLV_SATA_GP1_GPIOC_1_PAD, 0},
> > + { VLV_SATA_LEDN_GPIOC_2_PCONF0,
> VLV_SATA_LEDN_GPIOC_2_PAD, 0},
> > + { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0,
> VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
> > + { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0,
> VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
> > + { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0,
> VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
> > + { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0,
> VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
> > + { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0,
> VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
> > + { VLV_HDA_RSTB_GPIOC_8_PCONF0,
> VLV_HDA_RSTB_GPIOC_8_PAD, 0},
> > + { VLV_HDA_SYNC_GPIOC_9_PCONF0,
> VLV_HDA_SYNC_GPIOC_9_PAD, 0},
> > + { VLV_HDA_CLK_GPIOC_10_PCONF0,
> VLV_HDA_CLK_GPIOC_10_PAD, 0},
> > + { VLV_HDA_SDO_GPIOC_11_PCONF0,
> VLV_HDA_SDO_GPIOC_11_PAD, 0},
> > + { VLV_HDA_SDI0_GPIOC_12_PCONF0,
> VLV_HDA_SDI0_GPIOC_12_PAD, 0},
> > + { VLV_HDA_SDI1_GPIOC_13_PCONF0,
> VLV_HDA_SDI1_GPIOC_13_PAD, 0},
> > + { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0,
> VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
> > + { VLV_HDA_DOCKENB_GPIOC_15_PCONF0,
> VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
> > + { VLV_SDMMC1_CLK_GPIOC_16_PCONF0,
> VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
> > + { VLV_SDMMC1_D0_GPIOC_17_PCONF0,
> VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
> > + { VLV_SDMMC1_D1_GPIOC_18_PCONF0,
> VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
> > + { VLV_SDMMC1_D2_GPIOC_19_PCONF0,
> VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
> > + { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0,
> VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
> > + { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0,
> VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
> > + { VLV_MMC1_D5_GPIOC_22_PCONF0,
> VLV_MMC1_D5_GPIOC_22_PAD, 0},
> > + { VLV_MMC1_D6_GPIOC_23_PCONF0,
> VLV_MMC1_D6_GPIOC_23_PAD, 0},
> > + { VLV_MMC1_D7_GPIOC_24_PCONF0,
> VLV_MMC1_D7_GPIOC_24_PAD, 0},
> > + { VLV_SDMMC1_CMD_GPIOC_25_PCONF0,
> VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
> > + { VLV_MMC1_RESET_B_GPIOC_26_PCONF0,
> VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
> > + { VLV_SDMMC2_CLK_GPIOC_27_PCONF0,
> VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
> > + { VLV_SDMMC2_D0_GPIOC_28_PCONF0,
> VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
> > + { VLV_SDMMC2_D1_GPIOC_29_PCONF0,
> VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
> > + { VLV_SDMMC2_D2_GPIOC_30_PCONF0,
> VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
> > + { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0,
> VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
> > + { VLV_SDMMC2_CMD_GPIOC_32_PCONF0,
> VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
> > + { VLV_SDMMC3_CLK_GPIOC_33_PCONF0,
> VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
> > + { VLV_SDMMC3_D0_GPIOC_34_PCONF0,
> VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
> > + { VLV_SDMMC3_D1_GPIOC_35_PCONF0,
> VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
> > + { VLV_SDMMC3_D2_GPIOC_36_PCONF0,
> VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
> > + { VLV_SDMMC3_D3_GPIOC_37_PCONF0,
> VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
> > + { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0,
> VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
> > + { VLV_SDMMC3_CMD_GPIOC_39_PCONF0,
> VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
> > + { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0,
> VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
> > + { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0,
> VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
> > + { VLV_LPC_AD0_GPIOC_42_PCONF0,
> VLV_LPC_AD0_GPIOC_42_PAD, 0},
> > + { VLV_LPC_AD1_GPIOC_43_PCONF0,
> VLV_LPC_AD1_GPIOC_43_PAD, 0},
> > + { VLV_LPC_AD2_GPIOC_44_PCONF0,
> VLV_LPC_AD2_GPIOC_44_PAD, 0},
> > + { VLV_LPC_AD3_GPIOC_45_PCONF0,
> VLV_LPC_AD3_GPIOC_45_PAD, 0},
> > + { VLV_LPC_FRAMEB_GPIOC_46_PCONF0,
> VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
> > + { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0,
> VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
> > + { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0,
> VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
> > + { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0,
> VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
> > + { VLV_ILB_SERIRQ_GPIOC_50_PCONF0,
> VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
> > + { VLV_SMB_DATA_GPIOC_51_PCONF0,
> VLV_SMB_DATA_GPIOC_51_PAD, 0},
> > + { VLV_SMB_CLK_GPIOC_52_PCONF0,
> VLV_SMB_CLK_GPIOC_52_PAD, 0},
> > + { VLV_SMB_ALERTB_GPIOC_53_PCONF0,
> VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
> > + { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
> > + { VLV_MHSI_ACDATA_GPIOC_55_PCONF0,
> VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
> > + { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0,
> VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
> > + { VLV_MHSI_ACREADY_GPIOC_57_PCONF0,
> VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
> > + { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0,
> VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
> > + { VLV_MHSI_CADATA_GPIOC_59_PCONF0,
> VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
> > + { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0,
> VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
> > + { VLV_MHSI_CAREADY_GPIOC_61_PCONF0,
> VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
> > + { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0,
> VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
> > + { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0,
> VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
> > + { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0,
> VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
> > + { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0,
> VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
> > + { VLV_SPI1_CS0_B_GPIOC_66_PCONF0,
> VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
> > + { VLV_SPI1_MISO_GPIOC_67_PCONF0,
> VLV_SPI1_MISO_GPIOC_67_PAD, 0},
> > + { VLV_SPI1_MOSI_GPIOC_68_PCONF0,
> VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
> > + { VLV_SPI1_CLK_GPIOC_69_PCONF0,
> VLV_SPI1_CLK_GPIOC_69_PAD, 0},
> > + { VLV_UART1_RXD_GPIOC_70_PCONF0,
> VLV_UART1_RXD_GPIOC_70_PAD, 0},
> > + { VLV_UART1_TXD_GPIOC_71_PCONF0,
> VLV_UART1_TXD_GPIOC_71_PAD, 0},
> > + { VLV_UART1_RTS_B_GPIOC_72_PCONF0,
> VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
> > + { VLV_UART1_CTS_B_GPIOC_73_PCONF0,
> VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
> > + { VLV_UART2_RXD_GPIOC_74_PCONF0,
> VLV_UART2_RXD_GPIOC_74_PAD, 0},
> > + { VLV_UART2_TXD_GPIOC_75_PCONF0,
> VLV_UART2_TXD_GPIOC_75_PAD, 0},
> > + { VLV_UART2_RTS_B_GPIOC_76_PCONF0,
> VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
> > + { VLV_UART2_CTS_B_GPIOC_77_PCONF0,
> VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
> > + { VLV_I2C0_SDA_GPIOC_78_PCONF0,
> VLV_I2C0_SDA_GPIOC_78_PAD, 0},
> > + { VLV_I2C0_SCL_GPIOC_79_PCONF0,
> VLV_I2C0_SCL_GPIOC_79_PAD, 0},
> > + { VLV_I2C1_SDA_GPIOC_80_PCONF0,
> VLV_I2C1_SDA_GPIOC_80_PAD, 0},
> > + { VLV_I2C1_SCL_GPIOC_81_PCONF0,
> VLV_I2C1_SCL_GPIOC_81_PAD, 0},
> > + { VLV_I2C2_SDA_GPIOC_82_PCONF0,
> VLV_I2C2_SDA_GPIOC_82_PAD, 0},
> > + { VLV_I2C2_SCL_GPIOC_83_PCONF0,
> VLV_I2C2_SCL_GPIOC_83_PAD, 0},
> > + { VLV_I2C3_SDA_GPIOC_84_PCONF0,
> VLV_I2C3_SDA_GPIOC_84_PAD, 0},
> > + { VLV_I2C3_SCL_GPIOC_85_PCONF0,
> VLV_I2C3_SCL_GPIOC_85_PAD, 0},
> > + { VLV_I2C4_SDA_GPIOC_86_PCONF0,
> VLV_I2C4_SDA_GPIOC_86_PAD, 0},
> > + { VLV_I2C4_SCL_GPIOC_87_PCONF0,
> VLV_I2C4_SCL_GPIOC_87_PAD, 0},
> > + { VLV_I2C5_SDA_GPIOC_88_PCONF0,
> VLV_I2C5_SDA_GPIOC_88_PAD, 0},
> > + { VLV_I2C5_SCL_GPIOC_89_PCONF0,
> VLV_I2C5_SCL_GPIOC_89_PAD, 0},
> > + { VLV_I2C6_SDA_GPIOC_90_PCONF0,
> VLV_I2C6_SDA_GPIOC_90_PAD, 0},
> > + { VLV_I2C6_SCL_GPIOC_91_PCONF0,
> VLV_I2C6_SCL_GPIOC_91_PAD, 0},
> > + { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0,
> VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
> > + { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0,
> VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
> > + { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
> > + { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
> > + { VLV_PLT_CLK0_GPIOC_96_PCONF0,
> VLV_PLT_CLK0_GPIOC_96_PAD, 0},
> > + { VLV_PLT_CLK1_GPIOC_97_PCONF0,
> VLV_PLT_CLK1_GPIOC_97_PAD, 0},
> > + { VLV_PLT_CLK2_GPIOC_98_PCONF0,
> VLV_PLT_CLK2_GPIOC_98_PAD, 0},
> > + { VLV_PLT_CLK3_GPIOC_99_PCONF0,
> VLV_PLT_CLK3_GPIOC_99_PAD, 0},
> > + { VLV_PLT_CLK4_GPIOC_100_PCONF0,
> VLV_PLT_CLK4_GPIOC_100_PAD, 0},
> > + { VLV_PLT_CLK5_GPIOC_101_PCONF0,
> VLV_PLT_CLK5_GPIOC_101_PAD, 0},
> > +
> > + { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0,
> VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
> > + { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0,
> VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
> > + { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0,
> VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
> > + { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0,
> VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
> > + { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0,
> VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
> > + { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0,
> VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
> > + { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0,
> VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
> > + { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0,
> VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
> > + { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0,
> VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
> > + { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0,
> VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
> > + { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0,
> VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
> > + { VLV_SUSPWRDNACK_GPIOS_11_PCONF0,
> VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
> > + { VLV_PMU_SUSCLK_GPIOS_12_PCONF0,
> VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
> > + { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0,
> VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
> > + { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0,
> VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
> > + { VLV_PMU_WAKE_B_GPIOS_15_PCONF0,
> VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
> > + { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0,
> VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
> > + { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0,
> VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
> > + { VLV_SUS_STAT_B_GPIOS_18_PCONF0,
> VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
> > + { VLV_USB_OC0_B_GPIOS_19_PCONF0,
> VLV_USB_OC0_B_GPIOS_19_PAD, 0},
> > + { VLV_USB_OC1_B_GPIOS_20_PCONF0,
> VLV_USB_OC1_B_GPIOS_20_PAD, 0},
> > + { VLV_SPI_CS1_B_GPIOS_21_PCONF0,
> VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
> > + { VLV_GPIO_DFX0_GPIOS_22_PCONF0,
> VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
> > + { VLV_GPIO_DFX1_GPIOS_23_PCONF0,
> VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
> > + { VLV_GPIO_DFX2_GPIOS_24_PCONF0,
> VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
> > + { VLV_GPIO_DFX3_GPIOS_25_PCONF0,
> VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
> > + { VLV_GPIO_DFX4_GPIOS_26_PCONF0,
> VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
> > + { VLV_GPIO_DFX5_GPIOS_27_PCONF0,
> VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
> > + { VLV_GPIO_DFX6_GPIOS_28_PCONF0,
> VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
> > + { VLV_GPIO_DFX7_GPIOS_29_PCONF0,
> VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
> > + { VLV_GPIO_DFX8_GPIOS_30_PCONF0,
> VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
> > + { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0,
> VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0,
> VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0,
> VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0,
> VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0,
> VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0,
> VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0,
> VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0,
> VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
> > + { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0,
> VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
> > + { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0,
> VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
> > + { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0,
> VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
> > + { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0,
> VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
> > + { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0,
> > +VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
> > };
> >
> > static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -201,9
> > +690,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi,
> const u8 *data)
> > u8 gpio, action;
> > u16 function, pad;
> > u32 val;
> > + u8 port;
> > struct drm_device *dev = intel_dsi->base.base.dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> > +
> > + /*
> > + * Skipping the first byte as it is of no
> > + * interest for android in new version
> > + */
>
[Deepak, M] Okay, will remove this comment.
> That comment is unnecessary and misleading.
>
> > if (dev_priv->vbt.dsi.seq_version >= 3)
> > data++;
> >
> > @@ -212,19 +708,24 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
> *intel_dsi, const u8 *data)
> > /* pull up/down */
> > action = *data++ & 1;
> >
> > - if (gpio >= ARRAY_SIZE(gtable)) {
> > - DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> > - goto out;
> > - }
> > -
> > - if (!IS_VALLEYVIEW(dev_priv)) {
> > - DRM_DEBUG_KMS("GPIO element not supported on this
> platform\n");
> > - goto out;
> > - }
>
> Both of these checks are needed and added for a reason.
[Deepak, M] Okay will add these checks back.
>
> > -
> > if (dev_priv->vbt.dsi.seq_version >= 3) {
> > - DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> > - goto out;
> > + if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
> > + DRM_DEBUG_DRIVER("GPIO is in the north
> Block\n");
> > + port = IOSF_PORT_GPIO_NC;
> > + } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
> > + gpio <= IOSF_MAX_GPIO_NUM_SC)
> {
> > + DRM_DEBUG_DRIVER("GPIO is in the south
> Block\n");
> > + port = IOSF_PORT_GPIO_SC;
> > + } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
> > + gpio <= IOSF_MAX_GPIO_NUM) {
> > + DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
> > + port = IOSF_PORT_GPIO_SUS;
> > + } else {
> > + DRM_ERROR("GPIO number is not present in the
> table\n");
> > + goto out;
> > + }
> > + } else {
> > + port = IOSF_PORT_GPIO_NC;
> > }
> >
> > function = gtable[gpio].function_reg; @@ -233,16 +734,15 @@ static
> > const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> > mutex_lock(&dev_priv->sb_lock);
> > if (!gtable[gpio].init) {
> > /* program the function */
> > - /* FIXME: remove constant below */
> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
> > - 0x2000CC00);
> > + vlv_iosf_sb_write(dev_priv, port, function,
> > + VLV_GPIO_CFG);
> > gtable[gpio].init = 1;
> > }
> >
> > - val = 0x4 | action;
> > + val = VLV_GPIO_INPUT_DIS | action;
> >
> > /* pull up/down */
> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
> > + vlv_iosf_sb_write(dev_priv, port, pad, val);
> > mutex_unlock(&dev_priv->sb_lock);
> >
> > out:
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control
2016-02-19 11:23 ` [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control Deepak M
@ 2016-02-19 13:34 ` Jani Nikula
2016-02-22 13:26 ` [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI Deepak M
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2016-02-19 13:34 UTC (permalink / raw)
To: Deepak M, intel-gfx
On Fri, 19 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> From: Uma Shankar <uma.shankar@intel.com>
>
> Added the BXT GPIO pin configuration and programming logic for
> backlight and panel control.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46 ++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 7fd1fae..c6e18fe 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -32,6 +32,7 @@
> #include <linux/slab.h>
> #include <video/mipi_display.h>
> #include <asm/intel-mid.h>
> +#include <linux/gpio.h>
> #include <video/mipi_display.h>
> #include "i915_drv.h"
> #include "intel_drv.h"
> @@ -593,6 +594,16 @@ static struct gpio_table gtable[] = {
> { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
> };
>
> +struct bxt_gpio_table {
> + u16 gpio_pin;
> + u16 offset;
> +};
> +
> +static struct bxt_gpio_table bxt_gtable[] = {
> + {0xC1, 270},
> + {0x1B, 456}
Where's this magic from?
> +};
> +
> static inline enum port intel_dsi_seq_port_to_port(u8 port)
> {
> return port ? PORT_C : PORT_A;
> @@ -812,6 +823,39 @@ out:
> return 0;
> }
>
> +static int bxt_program_gpio(struct intel_dsi *intel_dsi,
> + const u8 *data, const u8 **cur_data)
> +{
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u8 gpio, action;
> + u16 function;
> +
> + /*
> + * Skipping the first byte as it is of no
> + * interest for android in new version
> + */
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
> + gpio = *data++;
> +
> + /* pull up/down */
> + action = *data++;
> + function = (bxt_gtable[0].gpio_pin == gpio) ?
> + bxt_gtable[0].offset :
> + (bxt_gtable[1].gpio_pin == gpio) ?
> + bxt_gtable[1].offset : 0;
Don't be lazy, please turn this into a for loop looking at the
table. This is just making it painful for the poor developer who needs
to add one more thing into the table later on.
The smart thing to do would be to abstract this part between vlv/chv/bxt
anyway. There's really no reason to have this duplicated.
> + if (!function)
> + return -1;
> +
> + gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
This might succeed the first time, but subsequent calls will fail. This
is like allocation. You also need to gpio_free afterwards, but you're
not supposed to do request/free every time you want to set the value.
> + gpio_set_value(function, action);
> +
> + *cur_data = data;
> + return 0;
> +}
> +
> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> {
> struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -825,6 +869,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> ret = chv_program_gpio(intel_dsi, data, &data);
> else if (IS_VALLEYVIEW(dev))
> ret = vlv_program_gpio(intel_dsi, data, &data);
> + else if (IS_BROXTON(dev))
> + ret = bxt_program_gpio(intel_dsi, data, &data);
> else
> DRM_ERROR("GPIO programming missing for this platform.\n");
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-19 13:31 ` Deepak, M
@ 2016-02-19 13:36 ` Jani Nikula
2016-02-19 13:46 ` [PATCH] " Deepak M
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2016-02-19 13:36 UTC (permalink / raw)
To: Deepak, M, intel-gfx
On Fri, 19 Feb 2016, "Deepak, M" <m.deepak@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Friday, February 19, 2016 6:51 PM
>> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Deepak, M <m.deepak@intel.com>
>> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
>> sequence support and gpio table
>>
>> On Fri, 19 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
>> > The generic gpio is sequence is parsed from the VBT and the GPIO table
>> > is updated with the North core, South core and SUS core elements.
>> >
>> > v2: Move changes in sideband.c file to new patch(Jani), rebase
>> > v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
>> >
>> > v3 by Jani
>> > - rebase on previous patches
>> > - don't return null on errors
>> >
>> > v4 by Deepak
>> > - rebase
>> > - prefixed the VLV_ to all the GPIO macros
>>
>> There were also versions 4, 5 and 6 by me also. v6 is at
>>
>> http://patchwork.freedesktop.org/patch/msgid/f684304ca297fd3dd325c29a
>> 541b8960fe468b96.1454582914.git.jani.nikula@intel.com
>>
>> You should take that as the basis.
> [Deepak, M] The link points me to the i2c patch not the gpio one.
Doh! Sorry, please disregard that. I'll go grab some more coffee.
BR,
Jani.
>>
>> Also see comments inline.
>>
>> > Signed-off-by: Deepak M <m.deepak@intel.com>
>> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 6 +
>> > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606
>> > ++++++++++++++++++++++++++---
>> > 2 files changed, 559 insertions(+), 53 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 3774870..606dc71 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
>> reg)
>> > #define IOSF_PORT_FLISDSI 0x1b
>> > #define IOSF_PORT_GPIO_SC 0x48
>> > #define IOSF_PORT_GPIO_SUS 0xa8
>> > +#define IOSF_MAX_GPIO_NUM_NC 26
>> > +#define IOSF_MAX_GPIO_NUM_SC 128
>> > +#define IOSF_MAX_GPIO_NUM 172
>> > #define IOSF_PORT_CCU 0xa9
>> > #define VLV_IOSF_DATA
>> _MMIO(VLV_DISPLAY_BASE + 0x2104)
>> > #define VLV_IOSF_ADDR
>> _MMIO(VLV_DISPLAY_BASE + 0x2108)
>> >
>> > +#define VLV_GPIO_CFG 0x2000CC00
>> > +#define VLV_GPIO_INPUT_DIS 0x04
>> > +
>> > /* See configdb bunit SB addr map */
>> > #define BUNIT_REG_BISOC 0x11
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > index 787f01c..e02e5e0 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > @@ -58,30 +58,356 @@ static inline struct vbt_panel
>> > *to_vbt_panel(struct drm_panel *panel)
>> >
>> > #define NS_KHZ_RATIO 1000000
>> >
>> > -#define GPI0_NC_0_HV_DDI0_HPD 0x4130
>> > -#define GPIO_NC_0_HV_DDI0_PAD 0x4138
>> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
>> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
>> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
>> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
>> > -#define GPIO_NC_3_PANEL0_VDDEN 0x4140
>> > -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
>> > -#define GPIO_NC_4_PANEL0_BLKEN 0x4150
>> > -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
>> > -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
>> > -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
>> > -#define GPIO_NC_6_PCONF0 0x4180
>> > -#define GPIO_NC_6_PAD 0x4188
>> > -#define GPIO_NC_7_PCONF0 0x4190
>> > -#define GPIO_NC_7_PAD 0x4198
>> > -#define GPIO_NC_8_PCONF0 0x4170
>> > -#define GPIO_NC_8_PAD 0x4178
>> > -#define GPIO_NC_9_PCONF0 0x4100
>> > -#define GPIO_NC_9_PAD 0x4108
>> > -#define GPIO_NC_10_PCONF0 0x40E0
>> > -#define GPIO_NC_10_PAD 0x40E8
>> > -#define GPIO_NC_11_PCONF0 0x40F0
>> > -#define GPIO_NC_11_PAD 0x40F8
>> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
>> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
>> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
>> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
>> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
>> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
>> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
>> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
>> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
>> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
>> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
>> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
>> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
>> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
>> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
>> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
>> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
>> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
>> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
>> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
>> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
>> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
>> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
>> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
>> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
>> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
>> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
>> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
>> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
>> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
>> > +#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
>> > +#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
>> > +#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
>> > +#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
>> > +#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
>> > +#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
>> > +#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
>> > +#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
>> > +#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
>> > +#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
>> > +#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
>> > +#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
>> > +#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
>> > +#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
>> > +#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
>> > +#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
>> > +#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
>> > +#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
>> > +#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
>> > +#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
>> > +#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
>> > +#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
>> > +#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
>> > +#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
>> > +
>> > +#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
>> > +#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
>> > +#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
>> > +#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
>> > +#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
>> > +#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
>> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
>> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
>> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
>> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
>> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
>> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
>> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
>> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
>> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
>> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
>> > +#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
>> > +#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
>> > +#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
>> > +#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
>> > +#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
>> > +#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
>> > +#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
>> > +#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
>> > +#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
>> > +#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
>> > +#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
>> > +#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
>> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
>> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
>> > +#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
>> > +#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
>> > +#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
>> > +#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
>> > +#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
>> > +#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
>> > +#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
>> > +#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
>> > +#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
>> > +#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
>> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
>> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
>> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
>> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
>> > +#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
>> > +#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
>> > +#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
>> > +#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
>> > +#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
>> > +#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
>> > +#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
>> > +#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
>> > +#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
>> > +#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
>> > +#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
>> > +#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
>> > +#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
>> > +#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
>> > +#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
>> > +#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
>> > +#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
>> > +#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
>> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
>> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
>> > +#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
>> > +#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
>> > +#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
>> > +#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
>> > +#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
>> > +#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
>> > +#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
>> > +#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
>> > +#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
>> > +#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
>> > +#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
>> > +#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
>> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
>> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
>> > +#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
>> > +#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
>> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
>> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
>> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
>> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
>> > +#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
>> > +#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
>> > +#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
>> > +#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
>> > +#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
>> > +#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
>> > +#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
>> > +#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
>> > +#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
>> > +#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
>> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
>> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
>> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
>> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
>> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
>> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
>> > +#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
>> > +#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
>> > +#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
>> > +#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
>> > +#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
>> > +#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
>> > +#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
>> > +#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
>> > +#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
>> > +#define VLV_SPKR_GPIOC_54_PAD 0x4678
>> > +#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
>> > +#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
>> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
>> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
>> > +#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
>> > +#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
>> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
>> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
>> > +#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
>> > +#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
>> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
>> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
>> > +#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
>> > +#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
>> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
>> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
>> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
>> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
>> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
>> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
>> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
>> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
>> > +#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
>> > +#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
>> > +#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
>> > +#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
>> > +#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
>> > +#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
>> > +#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
>> > +#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
>> > +#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
>> > +#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
>> > +#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
>> > +#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
>> > +#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
>> > +#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
>> > +#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
>> > +#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
>> > +#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
>> > +#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
>> > +#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
>> > +#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
>> > +#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
>> > +#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
>> > +#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
>> > +#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
>> > +#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
>> > +#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
>> > +#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
>> > +#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
>> > +#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
>> > +#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
>> > +#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
>> > +#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
>> > +#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
>> > +#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
>> > +#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
>> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
>> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
>> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
>> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
>> > +#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
>> > +#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
>> > +#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
>> > +#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
>> > +#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
>> > +#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
>> > +#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
>> > +#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
>> > +#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
>> > +#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
>> > +#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
>> > +#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
>> > +#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
>> > +#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
>> > +#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
>> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
>> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
>> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
>> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
>> > +#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
>> > +#define VLV_PWM0_GPIOC_94_PAD 0x40A8
>> > +#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
>> > +#define VLV_PWM1_GPIOC_95_PAD 0x40B8
>> > +#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
>> > +#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
>> > +#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
>> > +#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
>> > +#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
>> > +#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
>> > +#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
>> > +#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
>> > +#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
>> > +#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
>> > +#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
>> > +#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
>> > +
>> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
>> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
>> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
>> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
>> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
>> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
>> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
>> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
>> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
>> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
>> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
>> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
>> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
>> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
>> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
>> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
>> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
>> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
>> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
>> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
>> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
>> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
>> > +#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
>> > +#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
>> > +#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
>> > +#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
>> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
>> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
>> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
>> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
>> > +#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
>> > +#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
>> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
>> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
>> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
>> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
>> > +#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
>> > +#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
>> > +#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
>> > +#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
>> > +#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
>> > +#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
>> > +#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
>> > +#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
>> > +#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
>> > +#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
>> > +#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
>> > +#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
>> > +#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
>> > +#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
>> > +#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
>> > +#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
>> > +#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
>> > +#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
>> > +#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
>> > +#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
>> > +#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
>> > +#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
>> > +#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
>> > +#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
>> > +#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
>> > +#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
>> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
>> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
>> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
>> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
>> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
>> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
>> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
>> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
>> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
>> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
>> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
>> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
>> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
>> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
>> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
>> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
>> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
>> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
>> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
>> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
>> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
>> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
>> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
>> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
>> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
>> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
>> >
>> > struct gpio_table {
>> > u16 function_reg;
>> > @@ -90,18 +416,181 @@ struct gpio_table { };
>> >
>> > static struct gpio_table gtable[] = {
>> > - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
>> > - { GPIO_NC_1_HV_DDI0_DDC_SDA,
>> GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
>> > - { GPIO_NC_2_HV_DDI0_DDC_SCL,
>> GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
>> > - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD,
>> 0 },
>> > - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0
>> },
>> > - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0
>> },
>> > - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
>> > - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
>> > - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
>> > - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
>> > - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
>> > - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
>> > + { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0,
>> VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
>> > + { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0,
>> VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
>> > + { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0,
>> VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
>> > + { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0,
>> VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
>> > + { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0,
>> VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
>> > + { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0,
>> VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
>> > + { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0,
>> VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
>> > + { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0,
>> VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
>> > + { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0,
>> VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
>> > + { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0,
>> VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
>> > + { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0,
>> VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
>> > + { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0,
>> VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
>> > + { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0,
>> VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
>> > + { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0,
>> VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
>> > + { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0,
>> VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
>> > + { VLV_GP_CAMERASB00_GPIONC_15_PCONF0,
>> VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
>> > + { VLV_GP_CAMERASB01_GPIONC_16_PCONF0,
>> VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
>> > + { VLV_GP_CAMERASB02_GPIONC_17_PCONF0,
>> VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
>> > + { VLV_GP_CAMERASB03_GPIONC_18_PCONF0,
>> VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
>> > + { VLV_GP_CAMERASB04_GPIONC_19_PCONF0,
>> VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
>> > + { VLV_GP_CAMERASB05_GPIONC_20_PCONF0,
>> VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
>> > + { VLV_GP_CAMERASB06_GPIONC_21_PCONF0,
>> VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
>> > + { VLV_GP_CAMERASB07_GPIONC_22_PCONF0,
>> VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
>> > + { VLV_GP_CAMERASB08_GPIONC_23_PCONF0,
>> VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
>> > + { VLV_GP_CAMERASB09_GPIONC_24_PCONF0,
>> VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
>> > + { VLV_GP_CAMERASB10_GPIONC_25_PCONF0,
>> VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
>> > + { VLV_GP_CAMERASB11_GPIONC_26_PCONF0,
>> > +VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
>> > +
>> > + { VLV_SATA_GP0_GPIOC_0_PCONF0,
>> VLV_SATA_GP0_GPIOC_0_PAD, 0},
>> > + { VLV_SATA_GP1_GPIOC_1_PCONF0,
>> VLV_SATA_GP1_GPIOC_1_PAD, 0},
>> > + { VLV_SATA_LEDN_GPIOC_2_PCONF0,
>> VLV_SATA_LEDN_GPIOC_2_PAD, 0},
>> > + { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0,
>> VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
>> > + { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0,
>> VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
>> > + { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0,
>> VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
>> > + { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0,
>> VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
>> > + { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0,
>> VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
>> > + { VLV_HDA_RSTB_GPIOC_8_PCONF0,
>> VLV_HDA_RSTB_GPIOC_8_PAD, 0},
>> > + { VLV_HDA_SYNC_GPIOC_9_PCONF0,
>> VLV_HDA_SYNC_GPIOC_9_PAD, 0},
>> > + { VLV_HDA_CLK_GPIOC_10_PCONF0,
>> VLV_HDA_CLK_GPIOC_10_PAD, 0},
>> > + { VLV_HDA_SDO_GPIOC_11_PCONF0,
>> VLV_HDA_SDO_GPIOC_11_PAD, 0},
>> > + { VLV_HDA_SDI0_GPIOC_12_PCONF0,
>> VLV_HDA_SDI0_GPIOC_12_PAD, 0},
>> > + { VLV_HDA_SDI1_GPIOC_13_PCONF0,
>> VLV_HDA_SDI1_GPIOC_13_PAD, 0},
>> > + { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0,
>> VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
>> > + { VLV_HDA_DOCKENB_GPIOC_15_PCONF0,
>> VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
>> > + { VLV_SDMMC1_CLK_GPIOC_16_PCONF0,
>> VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
>> > + { VLV_SDMMC1_D0_GPIOC_17_PCONF0,
>> VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
>> > + { VLV_SDMMC1_D1_GPIOC_18_PCONF0,
>> VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
>> > + { VLV_SDMMC1_D2_GPIOC_19_PCONF0,
>> VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
>> > + { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0,
>> VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
>> > + { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0,
>> VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
>> > + { VLV_MMC1_D5_GPIOC_22_PCONF0,
>> VLV_MMC1_D5_GPIOC_22_PAD, 0},
>> > + { VLV_MMC1_D6_GPIOC_23_PCONF0,
>> VLV_MMC1_D6_GPIOC_23_PAD, 0},
>> > + { VLV_MMC1_D7_GPIOC_24_PCONF0,
>> VLV_MMC1_D7_GPIOC_24_PAD, 0},
>> > + { VLV_SDMMC1_CMD_GPIOC_25_PCONF0,
>> VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
>> > + { VLV_MMC1_RESET_B_GPIOC_26_PCONF0,
>> VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
>> > + { VLV_SDMMC2_CLK_GPIOC_27_PCONF0,
>> VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
>> > + { VLV_SDMMC2_D0_GPIOC_28_PCONF0,
>> VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
>> > + { VLV_SDMMC2_D1_GPIOC_29_PCONF0,
>> VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
>> > + { VLV_SDMMC2_D2_GPIOC_30_PCONF0,
>> VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
>> > + { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0,
>> VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
>> > + { VLV_SDMMC2_CMD_GPIOC_32_PCONF0,
>> VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
>> > + { VLV_SDMMC3_CLK_GPIOC_33_PCONF0,
>> VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
>> > + { VLV_SDMMC3_D0_GPIOC_34_PCONF0,
>> VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
>> > + { VLV_SDMMC3_D1_GPIOC_35_PCONF0,
>> VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
>> > + { VLV_SDMMC3_D2_GPIOC_36_PCONF0,
>> VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
>> > + { VLV_SDMMC3_D3_GPIOC_37_PCONF0,
>> VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
>> > + { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0,
>> VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
>> > + { VLV_SDMMC3_CMD_GPIOC_39_PCONF0,
>> VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
>> > + { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0,
>> VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
>> > + { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0,
>> VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
>> > + { VLV_LPC_AD0_GPIOC_42_PCONF0,
>> VLV_LPC_AD0_GPIOC_42_PAD, 0},
>> > + { VLV_LPC_AD1_GPIOC_43_PCONF0,
>> VLV_LPC_AD1_GPIOC_43_PAD, 0},
>> > + { VLV_LPC_AD2_GPIOC_44_PCONF0,
>> VLV_LPC_AD2_GPIOC_44_PAD, 0},
>> > + { VLV_LPC_AD3_GPIOC_45_PCONF0,
>> VLV_LPC_AD3_GPIOC_45_PAD, 0},
>> > + { VLV_LPC_FRAMEB_GPIOC_46_PCONF0,
>> VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
>> > + { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0,
>> VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
>> > + { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0,
>> VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
>> > + { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0,
>> VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
>> > + { VLV_ILB_SERIRQ_GPIOC_50_PCONF0,
>> VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
>> > + { VLV_SMB_DATA_GPIOC_51_PCONF0,
>> VLV_SMB_DATA_GPIOC_51_PAD, 0},
>> > + { VLV_SMB_CLK_GPIOC_52_PCONF0,
>> VLV_SMB_CLK_GPIOC_52_PAD, 0},
>> > + { VLV_SMB_ALERTB_GPIOC_53_PCONF0,
>> VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
>> > + { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
>> > + { VLV_MHSI_ACDATA_GPIOC_55_PCONF0,
>> VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
>> > + { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0,
>> VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
>> > + { VLV_MHSI_ACREADY_GPIOC_57_PCONF0,
>> VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
>> > + { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0,
>> VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
>> > + { VLV_MHSI_CADATA_GPIOC_59_PCONF0,
>> VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
>> > + { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0,
>> VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
>> > + { VLV_MHSI_CAREADY_GPIOC_61_PCONF0,
>> VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
>> > + { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0,
>> VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
>> > + { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0,
>> VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
>> > + { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0,
>> VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
>> > + { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0,
>> VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
>> > + { VLV_SPI1_CS0_B_GPIOC_66_PCONF0,
>> VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
>> > + { VLV_SPI1_MISO_GPIOC_67_PCONF0,
>> VLV_SPI1_MISO_GPIOC_67_PAD, 0},
>> > + { VLV_SPI1_MOSI_GPIOC_68_PCONF0,
>> VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
>> > + { VLV_SPI1_CLK_GPIOC_69_PCONF0,
>> VLV_SPI1_CLK_GPIOC_69_PAD, 0},
>> > + { VLV_UART1_RXD_GPIOC_70_PCONF0,
>> VLV_UART1_RXD_GPIOC_70_PAD, 0},
>> > + { VLV_UART1_TXD_GPIOC_71_PCONF0,
>> VLV_UART1_TXD_GPIOC_71_PAD, 0},
>> > + { VLV_UART1_RTS_B_GPIOC_72_PCONF0,
>> VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
>> > + { VLV_UART1_CTS_B_GPIOC_73_PCONF0,
>> VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
>> > + { VLV_UART2_RXD_GPIOC_74_PCONF0,
>> VLV_UART2_RXD_GPIOC_74_PAD, 0},
>> > + { VLV_UART2_TXD_GPIOC_75_PCONF0,
>> VLV_UART2_TXD_GPIOC_75_PAD, 0},
>> > + { VLV_UART2_RTS_B_GPIOC_76_PCONF0,
>> VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
>> > + { VLV_UART2_CTS_B_GPIOC_77_PCONF0,
>> VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
>> > + { VLV_I2C0_SDA_GPIOC_78_PCONF0,
>> VLV_I2C0_SDA_GPIOC_78_PAD, 0},
>> > + { VLV_I2C0_SCL_GPIOC_79_PCONF0,
>> VLV_I2C0_SCL_GPIOC_79_PAD, 0},
>> > + { VLV_I2C1_SDA_GPIOC_80_PCONF0,
>> VLV_I2C1_SDA_GPIOC_80_PAD, 0},
>> > + { VLV_I2C1_SCL_GPIOC_81_PCONF0,
>> VLV_I2C1_SCL_GPIOC_81_PAD, 0},
>> > + { VLV_I2C2_SDA_GPIOC_82_PCONF0,
>> VLV_I2C2_SDA_GPIOC_82_PAD, 0},
>> > + { VLV_I2C2_SCL_GPIOC_83_PCONF0,
>> VLV_I2C2_SCL_GPIOC_83_PAD, 0},
>> > + { VLV_I2C3_SDA_GPIOC_84_PCONF0,
>> VLV_I2C3_SDA_GPIOC_84_PAD, 0},
>> > + { VLV_I2C3_SCL_GPIOC_85_PCONF0,
>> VLV_I2C3_SCL_GPIOC_85_PAD, 0},
>> > + { VLV_I2C4_SDA_GPIOC_86_PCONF0,
>> VLV_I2C4_SDA_GPIOC_86_PAD, 0},
>> > + { VLV_I2C4_SCL_GPIOC_87_PCONF0,
>> VLV_I2C4_SCL_GPIOC_87_PAD, 0},
>> > + { VLV_I2C5_SDA_GPIOC_88_PCONF0,
>> VLV_I2C5_SDA_GPIOC_88_PAD, 0},
>> > + { VLV_I2C5_SCL_GPIOC_89_PCONF0,
>> VLV_I2C5_SCL_GPIOC_89_PAD, 0},
>> > + { VLV_I2C6_SDA_GPIOC_90_PCONF0,
>> VLV_I2C6_SDA_GPIOC_90_PAD, 0},
>> > + { VLV_I2C6_SCL_GPIOC_91_PCONF0,
>> VLV_I2C6_SCL_GPIOC_91_PAD, 0},
>> > + { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0,
>> VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
>> > + { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0,
>> VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
>> > + { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
>> > + { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
>> > + { VLV_PLT_CLK0_GPIOC_96_PCONF0,
>> VLV_PLT_CLK0_GPIOC_96_PAD, 0},
>> > + { VLV_PLT_CLK1_GPIOC_97_PCONF0,
>> VLV_PLT_CLK1_GPIOC_97_PAD, 0},
>> > + { VLV_PLT_CLK2_GPIOC_98_PCONF0,
>> VLV_PLT_CLK2_GPIOC_98_PAD, 0},
>> > + { VLV_PLT_CLK3_GPIOC_99_PCONF0,
>> VLV_PLT_CLK3_GPIOC_99_PAD, 0},
>> > + { VLV_PLT_CLK4_GPIOC_100_PCONF0,
>> VLV_PLT_CLK4_GPIOC_100_PAD, 0},
>> > + { VLV_PLT_CLK5_GPIOC_101_PCONF0,
>> VLV_PLT_CLK5_GPIOC_101_PAD, 0},
>> > +
>> > + { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0,
>> VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
>> > + { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0,
>> VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
>> > + { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0,
>> VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
>> > + { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0,
>> VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
>> > + { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0,
>> VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
>> > + { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0,
>> VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
>> > + { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0,
>> VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
>> > + { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0,
>> VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0,
>> VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0,
>> VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0,
>> VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
>> > + { VLV_SUSPWRDNACK_GPIOS_11_PCONF0,
>> VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
>> > + { VLV_PMU_SUSCLK_GPIOS_12_PCONF0,
>> VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
>> > + { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0,
>> VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
>> > + { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0,
>> VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
>> > + { VLV_PMU_WAKE_B_GPIOS_15_PCONF0,
>> VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
>> > + { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0,
>> VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
>> > + { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0,
>> VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
>> > + { VLV_SUS_STAT_B_GPIOS_18_PCONF0,
>> VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
>> > + { VLV_USB_OC0_B_GPIOS_19_PCONF0,
>> VLV_USB_OC0_B_GPIOS_19_PAD, 0},
>> > + { VLV_USB_OC1_B_GPIOS_20_PCONF0,
>> VLV_USB_OC1_B_GPIOS_20_PAD, 0},
>> > + { VLV_SPI_CS1_B_GPIOS_21_PCONF0,
>> VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
>> > + { VLV_GPIO_DFX0_GPIOS_22_PCONF0,
>> VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
>> > + { VLV_GPIO_DFX1_GPIOS_23_PCONF0,
>> VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
>> > + { VLV_GPIO_DFX2_GPIOS_24_PCONF0,
>> VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
>> > + { VLV_GPIO_DFX3_GPIOS_25_PCONF0,
>> VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
>> > + { VLV_GPIO_DFX4_GPIOS_26_PCONF0,
>> VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
>> > + { VLV_GPIO_DFX5_GPIOS_27_PCONF0,
>> VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
>> > + { VLV_GPIO_DFX6_GPIOS_28_PCONF0,
>> VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
>> > + { VLV_GPIO_DFX7_GPIOS_29_PCONF0,
>> VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
>> > + { VLV_GPIO_DFX8_GPIOS_30_PCONF0,
>> VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
>> > + { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0,
>> VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0,
>> VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0,
>> VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0,
>> VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0,
>> VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0,
>> VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0,
>> VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0,
>> VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0,
>> VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
>> > + { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0,
>> VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
>> > + { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0,
>> VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
>> > + { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0,
>> VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
>> > + { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0,
>> > +VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
>> > };
>> >
>> > static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -201,9
>> > +690,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi,
>> const u8 *data)
>> > u8 gpio, action;
>> > u16 function, pad;
>> > u32 val;
>> > + u8 port;
>> > struct drm_device *dev = intel_dsi->base.base.dev;
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> >
>> > + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
>> > +
>> > + /*
>> > + * Skipping the first byte as it is of no
>> > + * interest for android in new version
>> > + */
>>
> [Deepak, M] Okay, will remove this comment.
>
>> That comment is unnecessary and misleading.
>>
>> > if (dev_priv->vbt.dsi.seq_version >= 3)
>> > data++;
>> >
>> > @@ -212,19 +708,24 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
>> *intel_dsi, const u8 *data)
>> > /* pull up/down */
>> > action = *data++ & 1;
>> >
>> > - if (gpio >= ARRAY_SIZE(gtable)) {
>> > - DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
>> > - goto out;
>> > - }
>> > -
>> > - if (!IS_VALLEYVIEW(dev_priv)) {
>> > - DRM_DEBUG_KMS("GPIO element not supported on this
>> platform\n");
>> > - goto out;
>> > - }
>>
>> Both of these checks are needed and added for a reason.
> [Deepak, M] Okay will add these checks back.
>>
>> > -
>> > if (dev_priv->vbt.dsi.seq_version >= 3) {
>> > - DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> > - goto out;
>> > + if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
>> > + DRM_DEBUG_DRIVER("GPIO is in the north
>> Block\n");
>> > + port = IOSF_PORT_GPIO_NC;
>> > + } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
>> > + gpio <= IOSF_MAX_GPIO_NUM_SC)
>> {
>> > + DRM_DEBUG_DRIVER("GPIO is in the south
>> Block\n");
>> > + port = IOSF_PORT_GPIO_SC;
>> > + } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
>> > + gpio <= IOSF_MAX_GPIO_NUM) {
>> > + DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
>> > + port = IOSF_PORT_GPIO_SUS;
>> > + } else {
>> > + DRM_ERROR("GPIO number is not present in the
>> table\n");
>> > + goto out;
>> > + }
>> > + } else {
>> > + port = IOSF_PORT_GPIO_NC;
>> > }
>> >
>> > function = gtable[gpio].function_reg; @@ -233,16 +734,15 @@ static
>> > const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> > mutex_lock(&dev_priv->sb_lock);
>> > if (!gtable[gpio].init) {
>> > /* program the function */
>> > - /* FIXME: remove constant below */
>> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
>> > - 0x2000CC00);
>> > + vlv_iosf_sb_write(dev_priv, port, function,
>> > + VLV_GPIO_CFG);
>> > gtable[gpio].init = 1;
>> > }
>> >
>> > - val = 0x4 | action;
>> > + val = VLV_GPIO_INPUT_DIS | action;
>> >
>> > /* pull up/down */
>> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
>> > + vlv_iosf_sb_write(dev_priv, port, pad, val);
>> > mutex_unlock(&dev_priv->sb_lock);
>> >
>> > out:
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] drm/i915/dsi: Added the generic gpio sequence support and gpio table
2016-02-19 13:36 ` Jani Nikula
@ 2016-02-19 13:46 ` Deepak M
0 siblings, 0 replies; 16+ messages in thread
From: Deepak M @ 2016-02-19 13:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, Jani Nikula
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
v3 by Jani
- rebase on previous patches
- don't return null on errors
v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros
v5 by deepak
- readded the checks which were removed in the
earlier patchset (Jani)
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 592 ++++++++++++++++++++++++++---
2 files changed, 555 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870..606dc71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_FLISDSI 0x1b
#define IOSF_PORT_GPIO_SC 0x48
#define IOSF_PORT_GPIO_SUS 0xa8
+#define IOSF_MAX_GPIO_NUM_NC 26
+#define IOSF_MAX_GPIO_NUM_SC 128
+#define IOSF_MAX_GPIO_NUM 172
#define IOSF_PORT_CCU 0xa9
#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
+#define VLV_GPIO_CFG 0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c..794bd1f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
#define NS_KHZ_RATIO 1000000
-#define GPI0_NC_0_HV_DDI0_HPD 0x4130
-#define GPIO_NC_0_HV_DDI0_PAD 0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
-#define GPIO_NC_3_PANEL0_VDDEN 0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
-#define GPIO_NC_4_PANEL0_BLKEN 0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF0 0x4180
-#define GPIO_NC_6_PAD 0x4188
-#define GPIO_NC_7_PCONF0 0x4190
-#define GPIO_NC_7_PAD 0x4198
-#define GPIO_NC_8_PCONF0 0x4170
-#define GPIO_NC_8_PAD 0x4178
-#define GPIO_NC_9_PCONF0 0x4100
-#define GPIO_NC_9_PAD 0x4108
-#define GPIO_NC_10_PCONF0 0x40E0
-#define GPIO_NC_10_PAD 0x40E8
-#define GPIO_NC_11_PCONF0 0x40F0
-#define GPIO_NC_11_PAD 0x40F8
+#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
+#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
+#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
+#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
+#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
+#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
+#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
+#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
+#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
+#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
+#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
+#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
+#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
+#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
+#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
+#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
+#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
+#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
+#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
+#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
+#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
+#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
+#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
+#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
+#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
+#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
+#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
+#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
+#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
+#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
+#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
+
+#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
+#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
+#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
+#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
+#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
+#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
+#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
+#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
+#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
+#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
+#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
+#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
+#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
+#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
+#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
+#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
+#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
+#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
+#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
+#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
+#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
+#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
+#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
+#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
+#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
+#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
+#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
+#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
+#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
+#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
+#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
+#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
+#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
+#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
+#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
+#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
+#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
+#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
+#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
+#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
+#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
+#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
+#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
+#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
+#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
+#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
+#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
+#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
+#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
+#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
+#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
+#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
+#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
+#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
+#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
+#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
+#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
+#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
+#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
+#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
+#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
+#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
+#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
+#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
+#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
+#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
+#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
+#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
+#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
+#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
+#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
+#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
+#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
+#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
+#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
+#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
+#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
+#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
+#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
+#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
+#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
+#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
+#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
+#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
+#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
+#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
+#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
+#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
+#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
+#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
+#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
+#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
+#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
+#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
+#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
+#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
+#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
+#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
+#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
+#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
+#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
+#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
+#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
+#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
+#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
+#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
+#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
+#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
+#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
+#define VLV_SPKR_GPIOC_54_PAD 0x4678
+#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
+#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
+#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
+#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
+#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
+#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
+#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
+#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
+#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
+#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
+#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
+#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
+#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
+#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
+#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
+#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
+#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
+#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
+#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
+#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
+#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
+#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
+#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
+#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
+#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
+#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
+#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
+#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
+#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
+#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
+#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
+#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
+#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
+#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
+#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
+#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
+#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
+#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
+#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
+#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
+#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
+#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
+#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
+#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
+#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
+#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
+#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
+#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
+#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
+#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
+#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
+#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
+#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
+#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
+#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
+#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
+#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
+#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
+#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
+#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
+#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
+#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
+#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
+#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
+#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
+#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
+#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
+#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
+#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
+#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
+#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
+#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
+#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
+#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
+#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
+#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
+#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
+#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
+#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
+#define VLV_PWM0_GPIOC_94_PAD 0x40A8
+#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
+#define VLV_PWM1_GPIOC_95_PAD 0x40B8
+#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
+#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
+#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
+#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
+#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
+#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
+#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
+#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
+#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
+#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
+#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
+#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
+
+#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
+#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
+#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
+#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
+#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
+#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
+#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
+#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
+#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
+#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
+#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
+#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
+#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
+#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
+#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
+#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
+#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
+#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
+#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
+#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
+#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
+#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
+#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
+#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
+#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
+#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
+#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
+#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
+#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
+#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
+#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
+#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
+#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
+#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
+#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
+#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
+#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
+#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
+#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
+#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
+#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
+#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
+#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
+#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
+#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
+#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
+#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
+#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
+#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
+#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
+#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
+#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
+#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
+#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
+#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
+#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
+#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
+#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
+#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
+#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
+#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
+#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
+#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
+#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
+#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
+#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
+#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
+#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
+#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
+#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
+#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
+#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
+#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
+#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
+#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
+#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
+#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
+#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
+#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
+#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
+#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
+#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
+#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
+#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
+#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
+#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
+#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
+#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
struct gpio_table {
u16 function_reg;
@@ -90,18 +416,181 @@ struct gpio_table {
};
static struct gpio_table gtable[] = {
- { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
- { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
- { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
- { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
- { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
- { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
- { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
- { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
- { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
- { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
- { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
- { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
+ { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0, VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
+ { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
+ { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
+ { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0, VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
+ { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0, VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
+ { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0, VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
+ { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0, VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
+ { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
+ { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
+ { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0, VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
+ { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0, VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
+ { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0, VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
+ { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0, VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
+ { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
+ { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
+ { VLV_GP_CAMERASB00_GPIONC_15_PCONF0, VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
+ { VLV_GP_CAMERASB01_GPIONC_16_PCONF0, VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
+ { VLV_GP_CAMERASB02_GPIONC_17_PCONF0, VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
+ { VLV_GP_CAMERASB03_GPIONC_18_PCONF0, VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
+ { VLV_GP_CAMERASB04_GPIONC_19_PCONF0, VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
+ { VLV_GP_CAMERASB05_GPIONC_20_PCONF0, VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
+ { VLV_GP_CAMERASB06_GPIONC_21_PCONF0, VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
+ { VLV_GP_CAMERASB07_GPIONC_22_PCONF0, VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
+ { VLV_GP_CAMERASB08_GPIONC_23_PCONF0, VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
+ { VLV_GP_CAMERASB09_GPIONC_24_PCONF0, VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
+ { VLV_GP_CAMERASB10_GPIONC_25_PCONF0, VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
+ { VLV_GP_CAMERASB11_GPIONC_26_PCONF0, VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
+
+ { VLV_SATA_GP0_GPIOC_0_PCONF0, VLV_SATA_GP0_GPIOC_0_PAD, 0},
+ { VLV_SATA_GP1_GPIOC_1_PCONF0, VLV_SATA_GP1_GPIOC_1_PAD, 0},
+ { VLV_SATA_LEDN_GPIOC_2_PCONF0, VLV_SATA_LEDN_GPIOC_2_PAD, 0},
+ { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0, VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
+ { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0, VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
+ { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0, VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
+ { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0, VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
+ { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0, VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
+ { VLV_HDA_RSTB_GPIOC_8_PCONF0, VLV_HDA_RSTB_GPIOC_8_PAD, 0},
+ { VLV_HDA_SYNC_GPIOC_9_PCONF0, VLV_HDA_SYNC_GPIOC_9_PAD, 0},
+ { VLV_HDA_CLK_GPIOC_10_PCONF0, VLV_HDA_CLK_GPIOC_10_PAD, 0},
+ { VLV_HDA_SDO_GPIOC_11_PCONF0, VLV_HDA_SDO_GPIOC_11_PAD, 0},
+ { VLV_HDA_SDI0_GPIOC_12_PCONF0, VLV_HDA_SDI0_GPIOC_12_PAD, 0},
+ { VLV_HDA_SDI1_GPIOC_13_PCONF0, VLV_HDA_SDI1_GPIOC_13_PAD, 0},
+ { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0, VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
+ { VLV_HDA_DOCKENB_GPIOC_15_PCONF0, VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
+ { VLV_SDMMC1_CLK_GPIOC_16_PCONF0, VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
+ { VLV_SDMMC1_D0_GPIOC_17_PCONF0, VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
+ { VLV_SDMMC1_D1_GPIOC_18_PCONF0, VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
+ { VLV_SDMMC1_D2_GPIOC_19_PCONF0, VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
+ { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0, VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
+ { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0, VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
+ { VLV_MMC1_D5_GPIOC_22_PCONF0, VLV_MMC1_D5_GPIOC_22_PAD, 0},
+ { VLV_MMC1_D6_GPIOC_23_PCONF0, VLV_MMC1_D6_GPIOC_23_PAD, 0},
+ { VLV_MMC1_D7_GPIOC_24_PCONF0, VLV_MMC1_D7_GPIOC_24_PAD, 0},
+ { VLV_SDMMC1_CMD_GPIOC_25_PCONF0, VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
+ { VLV_MMC1_RESET_B_GPIOC_26_PCONF0, VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
+ { VLV_SDMMC2_CLK_GPIOC_27_PCONF0, VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
+ { VLV_SDMMC2_D0_GPIOC_28_PCONF0, VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
+ { VLV_SDMMC2_D1_GPIOC_29_PCONF0, VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
+ { VLV_SDMMC2_D2_GPIOC_30_PCONF0, VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
+ { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0, VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
+ { VLV_SDMMC2_CMD_GPIOC_32_PCONF0, VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
+ { VLV_SDMMC3_CLK_GPIOC_33_PCONF0, VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
+ { VLV_SDMMC3_D0_GPIOC_34_PCONF0, VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
+ { VLV_SDMMC3_D1_GPIOC_35_PCONF0, VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
+ { VLV_SDMMC3_D2_GPIOC_36_PCONF0, VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
+ { VLV_SDMMC3_D3_GPIOC_37_PCONF0, VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
+ { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0, VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
+ { VLV_SDMMC3_CMD_GPIOC_39_PCONF0, VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
+ { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0, VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
+ { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
+ { VLV_LPC_AD0_GPIOC_42_PCONF0, VLV_LPC_AD0_GPIOC_42_PAD, 0},
+ { VLV_LPC_AD1_GPIOC_43_PCONF0, VLV_LPC_AD1_GPIOC_43_PAD, 0},
+ { VLV_LPC_AD2_GPIOC_44_PCONF0, VLV_LPC_AD2_GPIOC_44_PAD, 0},
+ { VLV_LPC_AD3_GPIOC_45_PCONF0, VLV_LPC_AD3_GPIOC_45_PAD, 0},
+ { VLV_LPC_FRAMEB_GPIOC_46_PCONF0, VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
+ { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0, VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
+ { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0, VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
+ { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0, VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
+ { VLV_ILB_SERIRQ_GPIOC_50_PCONF0, VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
+ { VLV_SMB_DATA_GPIOC_51_PCONF0, VLV_SMB_DATA_GPIOC_51_PAD, 0},
+ { VLV_SMB_CLK_GPIOC_52_PCONF0, VLV_SMB_CLK_GPIOC_52_PAD, 0},
+ { VLV_SMB_ALERTB_GPIOC_53_PCONF0, VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
+ { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
+ { VLV_MHSI_ACDATA_GPIOC_55_PCONF0, VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
+ { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0, VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
+ { VLV_MHSI_ACREADY_GPIOC_57_PCONF0, VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
+ { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0, VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
+ { VLV_MHSI_CADATA_GPIOC_59_PCONF0, VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
+ { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0, VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
+ { VLV_MHSI_CAREADY_GPIOC_61_PCONF0, VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
+ { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0, VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
+ { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0, VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
+ { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0, VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
+ { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0, VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
+ { VLV_SPI1_CS0_B_GPIOC_66_PCONF0, VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
+ { VLV_SPI1_MISO_GPIOC_67_PCONF0, VLV_SPI1_MISO_GPIOC_67_PAD, 0},
+ { VLV_SPI1_MOSI_GPIOC_68_PCONF0, VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
+ { VLV_SPI1_CLK_GPIOC_69_PCONF0, VLV_SPI1_CLK_GPIOC_69_PAD, 0},
+ { VLV_UART1_RXD_GPIOC_70_PCONF0, VLV_UART1_RXD_GPIOC_70_PAD, 0},
+ { VLV_UART1_TXD_GPIOC_71_PCONF0, VLV_UART1_TXD_GPIOC_71_PAD, 0},
+ { VLV_UART1_RTS_B_GPIOC_72_PCONF0, VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
+ { VLV_UART1_CTS_B_GPIOC_73_PCONF0, VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
+ { VLV_UART2_RXD_GPIOC_74_PCONF0, VLV_UART2_RXD_GPIOC_74_PAD, 0},
+ { VLV_UART2_TXD_GPIOC_75_PCONF0, VLV_UART2_TXD_GPIOC_75_PAD, 0},
+ { VLV_UART2_RTS_B_GPIOC_76_PCONF0, VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
+ { VLV_UART2_CTS_B_GPIOC_77_PCONF0, VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
+ { VLV_I2C0_SDA_GPIOC_78_PCONF0, VLV_I2C0_SDA_GPIOC_78_PAD, 0},
+ { VLV_I2C0_SCL_GPIOC_79_PCONF0, VLV_I2C0_SCL_GPIOC_79_PAD, 0},
+ { VLV_I2C1_SDA_GPIOC_80_PCONF0, VLV_I2C1_SDA_GPIOC_80_PAD, 0},
+ { VLV_I2C1_SCL_GPIOC_81_PCONF0, VLV_I2C1_SCL_GPIOC_81_PAD, 0},
+ { VLV_I2C2_SDA_GPIOC_82_PCONF0, VLV_I2C2_SDA_GPIOC_82_PAD, 0},
+ { VLV_I2C2_SCL_GPIOC_83_PCONF0, VLV_I2C2_SCL_GPIOC_83_PAD, 0},
+ { VLV_I2C3_SDA_GPIOC_84_PCONF0, VLV_I2C3_SDA_GPIOC_84_PAD, 0},
+ { VLV_I2C3_SCL_GPIOC_85_PCONF0, VLV_I2C3_SCL_GPIOC_85_PAD, 0},
+ { VLV_I2C4_SDA_GPIOC_86_PCONF0, VLV_I2C4_SDA_GPIOC_86_PAD, 0},
+ { VLV_I2C4_SCL_GPIOC_87_PCONF0, VLV_I2C4_SCL_GPIOC_87_PAD, 0},
+ { VLV_I2C5_SDA_GPIOC_88_PCONF0, VLV_I2C5_SDA_GPIOC_88_PAD, 0},
+ { VLV_I2C5_SCL_GPIOC_89_PCONF0, VLV_I2C5_SCL_GPIOC_89_PAD, 0},
+ { VLV_I2C6_SDA_GPIOC_90_PCONF0, VLV_I2C6_SDA_GPIOC_90_PAD, 0},
+ { VLV_I2C6_SCL_GPIOC_91_PCONF0, VLV_I2C6_SCL_GPIOC_91_PAD, 0},
+ { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0, VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
+ { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0, VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
+ { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
+ { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
+ { VLV_PLT_CLK0_GPIOC_96_PCONF0, VLV_PLT_CLK0_GPIOC_96_PAD, 0},
+ { VLV_PLT_CLK1_GPIOC_97_PCONF0, VLV_PLT_CLK1_GPIOC_97_PAD, 0},
+ { VLV_PLT_CLK2_GPIOC_98_PCONF0, VLV_PLT_CLK2_GPIOC_98_PAD, 0},
+ { VLV_PLT_CLK3_GPIOC_99_PCONF0, VLV_PLT_CLK3_GPIOC_99_PAD, 0},
+ { VLV_PLT_CLK4_GPIOC_100_PCONF0, VLV_PLT_CLK4_GPIOC_100_PAD, 0},
+ { VLV_PLT_CLK5_GPIOC_101_PCONF0, VLV_PLT_CLK5_GPIOC_101_PAD, 0},
+
+ { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0, VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
+ { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0, VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
+ { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0, VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
+ { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0, VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
+ { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0, VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
+ { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0, VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
+ { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0, VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
+ { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0, VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
+ { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
+ { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
+ { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
+ { VLV_SUSPWRDNACK_GPIOS_11_PCONF0, VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
+ { VLV_PMU_SUSCLK_GPIOS_12_PCONF0, VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
+ { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0, VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
+ { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0, VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
+ { VLV_PMU_WAKE_B_GPIOS_15_PCONF0, VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
+ { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0, VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
+ { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0, VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
+ { VLV_SUS_STAT_B_GPIOS_18_PCONF0, VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
+ { VLV_USB_OC0_B_GPIOS_19_PCONF0, VLV_USB_OC0_B_GPIOS_19_PAD, 0},
+ { VLV_USB_OC1_B_GPIOS_20_PCONF0, VLV_USB_OC1_B_GPIOS_20_PAD, 0},
+ { VLV_SPI_CS1_B_GPIOS_21_PCONF0, VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
+ { VLV_GPIO_DFX0_GPIOS_22_PCONF0, VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
+ { VLV_GPIO_DFX1_GPIOS_23_PCONF0, VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
+ { VLV_GPIO_DFX2_GPIOS_24_PCONF0, VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
+ { VLV_GPIO_DFX3_GPIOS_25_PCONF0, VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
+ { VLV_GPIO_DFX4_GPIOS_26_PCONF0, VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
+ { VLV_GPIO_DFX5_GPIOS_27_PCONF0, VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
+ { VLV_GPIO_DFX6_GPIOS_28_PCONF0, VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
+ { VLV_GPIO_DFX7_GPIOS_29_PCONF0, VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
+ { VLV_GPIO_DFX8_GPIOS_30_PCONF0, VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
+ { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0, VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
+ { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0, VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
+ { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0, VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
+ { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0, VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
+ { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0, VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
+ { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0, VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
+ { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0, VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
+ { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0, VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
+ { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0, VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
+ { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0, VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
+ { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0, VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
+ { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0, VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
+ { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
};
static inline enum port intel_dsi_seq_port_to_port(u8 port)
@@ -201,9 +690,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
u8 gpio, action;
u16 function, pad;
u32 val;
+ u8 port;
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
if (dev_priv->vbt.dsi.seq_version >= 3)
data++;
@@ -223,8 +715,23 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
}
if (dev_priv->vbt.dsi.seq_version >= 3) {
- DRM_DEBUG_KMS("GPIO element v3 not supported\n");
- goto out;
+ if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
+ DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+ port = IOSF_PORT_GPIO_NC;
+ } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
+ gpio <= IOSF_MAX_GPIO_NUM_SC) {
+ DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
+ port = IOSF_PORT_GPIO_SC;
+ } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
+ gpio <= IOSF_MAX_GPIO_NUM) {
+ DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
+ port = IOSF_PORT_GPIO_SUS;
+ } else {
+ DRM_ERROR("GPIO number is not present in the table\n");
+ goto out;
+ }
+ } else {
+ port = IOSF_PORT_GPIO_NC;
}
function = gtable[gpio].function_reg;
@@ -233,16 +740,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
mutex_lock(&dev_priv->sb_lock);
if (!gtable[gpio].init) {
/* program the function */
- /* FIXME: remove constant below */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
- 0x2000CC00);
+ vlv_iosf_sb_write(dev_priv, port, function,
+ VLV_GPIO_CFG);
gtable[gpio].init = 1;
}
- val = 0x4 | action;
+ val = VLV_GPIO_INPUT_DIS | action;
/* pull up/down */
- vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
+ vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(&dev_priv->sb_lock);
out:
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev2)
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
` (3 preceding siblings ...)
2016-02-19 13:21 ` [Generic GPIO patch 1/3] " Jani Nikula
@ 2016-02-19 15:15 ` Patchwork
2016-02-22 13:47 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev4) Patchwork
5 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-02-19 15:15 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Summary ==
Series 3623v2 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3623/revisions/2/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dpms:
incomplete -> PASS (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
Subgroup force-load-detect:
dmesg-fail -> FAIL (hsw-gt2)
fail -> SKIP (ivb-t430s)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (bsw-nuc-2)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip:14
bsw-nuc-2 total:167 pass:136 dwarn:1 dfail:0 fail:0 skip:30
byt-nuc total:167 pass:142 dwarn:0 dfail:0 fail:0 skip:25
hsw-gt2 total:167 pass:156 dwarn:0 dfail:0 fail:1 skip:10
ilk-hp8440p total:101 pass:72 dwarn:0 dfail:0 fail:0 skip:28
ivb-t430s total:167 pass:152 dwarn:0 dfail:0 fail:0 skip:15
skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
snb-dellxps total:167 pass:144 dwarn:0 dfail:1 fail:0 skip:22
Results at /archive/results/CI_IGT_test/Patchwork_1445/
e7d04bf9d65001191a0b64e322bffa713280d132 drm-intel-nightly: 2016y-02m-19d-13h-11m-43s UTC integration manifest
920bfcad42496115826c4fa3f2fc96d88c41c48e drm/i915: BXT GPIO support for backlight and panel control
d94379d51ac3af94d2f129889539d322a8dc5dd3 drm/i915: GPIO for CHT generic MIPI
3d713b0dcd2a22de7724ddd81454ff90a10e0b09 drm/i915/dsi: Added the generic gpio sequence support and gpio table
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [GPIO PATCH 1/2] drm/i915: GPIO for CHT generic MIPI
2016-02-19 13:25 ` Jani Nikula
@ 2016-02-22 13:25 ` Deepak M
2016-02-22 13:40 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Deepak M @ 2016-02-22 13:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Deepak M
From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.
v2: Removing the duplication of parsing
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 107 ++++++++++++++++++++++-------
2 files changed, 102 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 606dc71..fc57477 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
#define IOSF_PORT_GPIO_NC 0x13
+#define CHV_IOSF_PORT_GPIO_N 0x13
+#define CHV_IOSF_PORT_GPIO_SE 0x48
+#define CHV_IOSF_PORT_GPIO_SW 0xB2
+#define CHV_IOSF_PORT_GPIO_E 0xA8
+#define CHV_MAX_GPIO_NUM_N 72
+#define CHV_MAX_GPIO_NUM_SE 99
+#define CHV_MAX_GPIO_NUM_SW 197
+#define CHV_MIN_GPIO_NUM_SE 73
+#define CHV_MIN_GPIO_NUM_SW 100
+#define CHV_MIN_GPIO_NUM_E 198
#define IOSF_PORT_CCK 0x14
#define IOSF_PORT_DPIO_2 0x1a
#define IOSF_PORT_FLISDSI 0x1b
@@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_GPIO_CFG 0x2000CC00
#define VLV_GPIO_INPUT_DIS 0x04
+#define CHV_PAD_FMLY_BASE 0x4400
+#define CHV_PAD_FMLY_SIZE 0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
+#define CHV_PAD_CFG_REG_SIZE 0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY 15
+
+#define CHV_GPIO_CFG_UNLOCK 0x00000000
+#define CHV_GPIO_CFG_HIZ 0x00008100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT 1
+
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 794bd1f..4849515 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -685,34 +685,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
return data;
}
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
{
- u8 gpio, action;
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
u16 function, pad;
u32 val;
u8 port;
- struct drm_device *dev = intel_dsi->base.base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
-
- if (dev_priv->vbt.dsi.seq_version >= 3)
- data++;
-
- gpio = *data++;
-
- /* pull up/down */
- action = *data++ & 1;
-
- if (gpio >= ARRAY_SIZE(gtable)) {
- DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
- goto out;
- }
-
- if (!IS_VALLEYVIEW(dev_priv)) {
- DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
- goto out;
- }
if (dev_priv->vbt.dsi.seq_version >= 3) {
if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
@@ -728,7 +707,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
port = IOSF_PORT_GPIO_SUS;
} else {
DRM_ERROR("GPIO number is not present in the table\n");
- goto out;
+ return;
}
} else {
port = IOSF_PORT_GPIO_NC;
@@ -750,11 +729,89 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */
vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(&dev_priv->sb_lock);
+}
+
+void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u16 function, pad;
+ u16 family_num;
+ u8 block;
+
+ if (dev_priv->vbt.dsi.seq_version >= 3) {
+ if (gpio <= CHV_MAX_GPIO_NUM_N) {
+ block = CHV_IOSF_PORT_GPIO_N;
+ DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+ } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+ block = CHV_IOSF_PORT_GPIO_SE;
+ gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+ DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+ } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+ block = CHV_IOSF_PORT_GPIO_SW;
+ gpio = gpio - CHV_MIN_GPIO_NUM_SW;
+ DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
+ } else {
+ block = CHV_IOSF_PORT_GPIO_E;
+ gpio = gpio - CHV_MIN_GPIO_NUM_E;
+ DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
+ }
+ } else
+ block = IOSF_PORT_GPIO_NC;
+
+ family_num = gpio / CHV_VBT_MAX_PINS_PER_FMLY;
+ gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+ pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+ (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
+ function = pad + CHV_PAD_CFG_REG_SIZE;
+
+ mutex_lock(&dev_priv->sb_lock);
+ vlv_iosf_sb_write(dev_priv, block, function,
+ CHV_GPIO_CFG_UNLOCK);
+ vlv_iosf_sb_write(dev_priv, block, pad, CHV_GPIO_CFG_HIZ |
+ (action << CHV_GPIO_CFG_TX_STATE_SHIFT));
+ mutex_unlock(&dev_priv->sb_lock);
+
+}
+
+static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+{
+ u8 gpio, action;
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
+ if (dev_priv->vbt.dsi.seq_version >= 3)
+ data++;
+
+ gpio = *data++;
+
+ /* pull up/down */
+ action = *data++ & 1;
+
+ if (gpio >= ARRAY_SIZE(gtable)) {
+ DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
+ goto out;
+ }
+
+ if (!IS_VALLEYVIEW(dev_priv)) {
+ DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
+ goto out;
+ }
+
+ if (IS_VALLEYVIEW(dev))
+ vlv_program_gpio(intel_dsi, gpio, action);
+ else if (IS_CHERRYVIEW(dev))
+ chv_program_gpio(intel_dsi, gpio, action);
+ else
+ DRM_ERROR("GPIO programming missing for this platform.\n");
out:
return data;
}
+
static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
{
return data + *(data + 6) + 7;
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI
2016-02-19 13:34 ` Jani Nikula
@ 2016-02-22 13:26 ` Deepak M
2016-02-22 14:04 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Deepak M @ 2016-02-22 13:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Deepak M
From: Uma Shankar <uma.shankar@intel.com>
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.
v2 by Deepak
- Added the GPIO table got BXT.
- Added gpio_free
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 662 ++++++++++++++++++++++++++++-
1 file changed, 657 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 4849515..4fcc755 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
#include <drm/drm_edid.h>
#include <drm/i915_drm.h>
#include <drm/drm_panel.h>
+#include <linux/gpio.h>
#include <linux/slab.h>
#include <video/mipi_display.h>
#include <asm/intel-mid.h>
@@ -593,6 +594,634 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
};
+struct bxt_gpio_table {
+ u16 gpio_pin;
+ u16 offset;
+};
+
+#define BXT_HV_DDI0_DDC_SDA_PIN 187
+#define BXT_HV_DDI0_DDC_SCL_PIN 188
+#define BXT_HV_DDI1_DDC_SDA_PIN 189
+#define BXT_HV_DDI1_DDC_SCL_PIN 190
+#define BXT_DBI_SDA_PIN 191
+#define BXT_DBI_SCL_PIN 192
+#define BXT_PANEL0_VDDEN_PIN 193
+#define BXT_PANEL0_BKLTEN_PIN 194
+#define BXT_PANEL0_BKLTCTL_PIN 195
+#define BXT_PANEL1_VDDEN_PIN 196
+#define BXT_PANEL1_BKLTEN_PIN 197
+#define BXT_PANEL1_BKLTCTL_PIN 198
+#define BXT_DBI_CSX_PIN 199
+#define BXT_DBI_RESX_PIN 200
+#define BXT_GP_INTD_DSI_TE1_PIN 201
+#define BXT_GP_INTD_DSI_TE2_PIN 202
+#define BXT_USB_OC0_B_PIN 203
+#define BXT_USB_OC1_B_PIN 204
+#define BXT_MEX_WAKE0_B_PIN 205
+#define BXT_MEX_WAKE1_B_PIN 206
+#define BXT_EMMC0_CLK_PIN 156
+#define BXT_EMMC0_D0_PIN 157
+#define BXT_EMMC0_D1_PIN 158
+#define BXT_EMMC0_D2_PIN 159
+#define BXT_EMMC0_D3_PIN 160
+#define BXT_EMMC0_D4_PIN 161
+#define BXT_EMMC0_D5_PIN 162
+#define BXT_EMMC0_D6_PIN 163
+#define BXT_EMMC0_D7_PIN 164
+#define BXT_EMMC0_CMD_PIN 165
+#define BXT_SDIO_CLK_PIN 166
+#define BXT_SDIO_D0_PIN 167
+#define BXT_SDIO_D1_PIN 168
+#define BXT_SDIO_D2_PIN 169
+#define BXT_SDIO_D3_PIN 170
+#define BXT_SDIO_CMD_PIN 171
+#define BXT_SDCARD_CLK_PIN 172
+#define BXT_SDCARD_D0_PIN 173
+#define BXT_SDCARD_D1_PIN 174
+#define BXT_SDCARD_D2_PIN 175
+#define BXT_SDCARD_D3_PIN 176
+#define BXT_SDCARD_CD_B_PIN 177
+#define BXT_SDCARD_CMD_PIN 178
+#define BXT_SDCARD_LVL_CLK_FB_PIN 179
+#define BXT_SDCARD_LVL_CMD_DIR_PIN 180
+#define BXT_SDCARD_LVL_DAT_DIR_PIN 181
+#define BXT_EMMC0_STROBE_PIN 182
+#define BXT_SDIO_PWR_DOWN_B_PIN 183
+#define BXT_SDCARD_PWR_DOWN_B_PIN 184
+#define BXT_SDCARD_LVL_SEL_PIN 185
+#define BXT_SDCARD_LVL_WP_PIN 186
+#define BXT_LPSS_I2C0_SDA_PIN 124
+#define BXT_LPSS_I2C0_SCL_PIN 125
+#define BXT_LPSS_I2C1_SDA_PIN 126
+#define BXT_LPSS_I2C1_SCL_PIN 127
+#define BXT_LPSS_I2C2_SDA_PIN 128
+#define BXT_LPSS_I2C2_SCL_PIN 129
+#define BXT_LPSS_I2C3_SDA_PIN 130
+#define BXT_LPSS_I2C3_SCL_PIN 131
+#define BXT_LPSS_I2C4_SDA_PIN 132
+#define BXT_LPSS_I2C4_SCL_PIN 133
+#define BXT_LPSS_I2C5_SDA_PIN 134
+#define BXT_LPSS_I2C5_SCL_PIN 135
+#define BXT_LPSS_I2C6_SDA_PIN 136
+#define BXT_LPSS_I2C6_SCL_PIN 137
+#define BXT_LPSS_I2C7_SDA_PIN 138
+#define BXT_LPSS_I2C7_SCL_PIN 139
+#define BXT_ISH_I2C0_SDA_PIN 140
+#define BXT_ISH_I2C0_SCL_PIN 141
+#define BXT_ISH_I2C1_SDA_PIN 142
+#define BXT_ISH_I2C1_SCL_PIN 143
+#define BXT_ISH_I2C2_SDA_PIN 144
+#define BXT_ISH_I2C2_SCL_PIN 145
+#define BXT_ISH_GPIO_0_PIN 146
+#define BXT_ISH_GPIO_1_PIN 147
+#define BXT_ISH_GPIO_2_PIN 148
+#define BXT_ISH_GPIO_3_PIN 149
+#define BXT_ISH_GPIO_4_PIN 150
+#define BXT_ISH_GPIO_5_PIN 151
+#define BXT_ISH_GPIO_6_PIN 152
+#define BXT_ISH_GPIO_7_PIN 153
+#define BXT_ISH_GPIO_8_PIN 154
+#define BXT_ISH_GPIO_9_PIN 155
+#define BXT_AVS_I2S1_MCLK_PIN 74
+#define BXT_AVS_I2S1_BCLK_PIN 75
+#define BXT_AVS_I2S1_WS_SYNC_PIN 76
+#define BXT_AVS_I2S1_SDI_PIN 77
+#define BXT_AVS_I2S1_SDO_PIN 78
+#define BXT_AVS_M_CLK_A1_PIN 79
+#define BXT_AVS_M_CLK_B1_PIN 80
+#define BXT_AVS_M_DATA_1_PIN 81
+#define BXT_AVS_M_CLK_AB2_PIN 82
+#define BXT_AVS_M_DATA_2_PIN 83
+#define BXT_AVS_I2S2_MCLK_PIN 84
+#define BXT_AVS_I2S2_BCLK_PIN 85
+#define BXT_AVS_I2S2_WS_SYNC_PIN 86
+#define BXT_AVS_I2S2_SDI_PIN 87
+#define BXT_AVS_I2S2_SDO_PIN 88
+#define BXT_AVS_I2S3_BCLK_PIN 89
+#define BXT_AVS_I2S3_WS_SYNC_PIN 90
+#define BXT_AVS_I2S3_SDI_PIN 91
+#define BXT_AVS_I2S3_SDO_PIN 92
+#define BXT_AVS_I2S4_BCLK_PIN 93
+#define BXT_AVS_I2S4_WS_SYNC_PIN 94
+#define BXT_AVS_I2S4_SDI_PIN 95
+#define BXT_AVS_I2S4_SDO_PIN 96
+#define BXT_FST_SPI_CS0_B_PIN 97
+#define BXT_FST_SPI_CS1_B_PIN 98
+#define BXT_FST_SPI_MOSI_IO0_PIN 99
+#define BXT_FST_SPI_MISO_IO1_PIN 100
+#define BXT_FST_SPI_IO2_PIN 101
+#define BXT_FST_SPI_IO3_PIN 102
+#define BXT_FST_SPI_CLK_PIN 103
+#define BXT_GP_SSP_0_CLK_PIN 104
+#define BXT_GP_SSP_0_FS0_PIN 105
+#define BXT_GP_SSP_0_FS1_PIN 106
+#define BXT_GP_SSP_0_FS2_PIN 107
+#define BXT_GP_SSP_0_RXD_PIN 109
+#define BXT_GP_SSP_0_TXD_PIN 110
+#define BXT_GP_SSP_1_CLK_PIN 111
+#define BXT_GP_SSP_1_FS0_PIN 112
+#define BXT_GP_SSP_1_FS1_PIN 113
+#define BXT_GP_SSP_1_FS2_PIN 114
+#define BXT_GP_SSP_1_FS3_PIN 115
+#define BXT_GP_SSP_1_RXD_PIN 116
+#define BXT_GP_SSP_1_TXD_PIN 117
+#define BXT_GP_SSP_2_CLK_PIN 118
+#define BXT_GP_SSP_2_FS0_PIN 119
+#define BXT_GP_SSP_2_FS1_PIN 120
+#define BXT_GP_SSP_2_FS2_PIN 121
+#define BXT_GP_SSP_2_RXD_PIN 122
+#define BXT_GP_SSP_2_TXD_PIN 123
+#define BXT_TRACE_0_CLK_VNN_PIN 0
+#define BXT_TRACE_0_DATA0_VNN_PIN 1
+#define BXT_TRACE_0_DATA1_VNN_PIN 2
+#define BXT_TRACE_0_DATA2_VNN_PIN 3
+#define BXT_TRACE_0_DATA3_VNN_PIN 4
+#define BXT_TRACE_0_DATA4_VNN_PIN 5
+#define BXT_TRACE_0_DATA5_VNN_PIN 6
+#define BXT_TRACE_0_DATA6_VNN_PIN 7
+#define BXT_TRACE_0_DATA7_VNN_PIN 8
+#define BXT_TRACE_1_CLK_VNN_PIN 9
+#define BXT_TRACE_1_DATA0_VNN_PIN 10
+#define BXT_TRACE_1_DATA1_VNN_PIN 11
+#define BXT_TRACE_1_DATA2_VNN_PIN 12
+#define BXT_TRACE_1_DATA3_VNN_PIN 13
+#define BXT_TRACE_1_DATA4_VNN_PIN 14
+#define BXT_TRACE_1_DATA5_VNN_PIN 15
+#define BXT_TRACE_1_DATA6_VNN_PIN 16
+#define BXT_TRACE_1_DATA7_VNN_PIN 17
+#define BXT_TRACE_2_CLK_VNN_PIN 18
+#define BXT_TRACE_2_DATA0_VNN_PIN 19
+#define BXT_TRACE_2_DATA1_VNN_PIN 20
+#define BXT_TRACE_2_DATA2_VNN_PIN 21
+#define BXT_TRACE_2_DATA3_VNN_PIN 22
+#define BXT_TRACE_2_DATA4_VNN_PIN 23
+#define BXT_TRACE_2_DATA5_VNN_PIN 24
+#define BXT_TRACE_2_DATA6_VNN_PIN 25
+#define BXT_TRACE_2_DATA7_VNN_PIN 26
+#define BXT_TRIGOUT_0_PIN 27
+#define BXT_TRIGOUT_1_PIN 28
+#define BXT_TRIGIN_0_PIN 29
+#define BXT_SEC_TCK_PIN 30
+#define BXT_SEC_TDI_PIN 31
+#define BXT_SEC_TMS_PIN 32
+#define BXT_SEC_TDO_PIN 33
+#define BXT_PWM0_PIN 34
+#define BXT_PWM1_PIN 35
+#define BXT_PWM2_PIN 36
+#define BXT_PWM3_PIN 37
+#define BXT_LPSS_UART0_RXD_PIN 38
+#define BXT_LPSS_UART0_TXD_PIN 39
+#define BXT_LPSS_UART0_RTS_B_PIN 40
+#define BXT_LPSS_UART0_CTS_B_PIN 41
+#define BXT_LPSS_UART1_RXD_PIN 42
+#define BXT_LPSS_UART1_TXD_PIN 43
+#define BXT_LPSS_UART1_RTS_B_PIN 44
+#define BXT_LPSS_UART1_CTS_B_PIN 45
+#define BXT_LPSS_UART2_RXD_PIN 46
+#define BXT_LPSS_UART2_TXD_PIN 47
+#define BXT_LPSS_UART2_RTS_B_PIN 48
+#define BXT_LPSS_UART2_CTS_B_PIN 49
+#define BXT_ISH_UART0_RXD_PIN 50
+#define BXT_ISH_UART0_TXD_PIN 51
+#define BXT_ISH_UART0_RTS_B_PIN 52
+#define BXT_ISH_UART0_CTS_B_PIN 53
+#define BXT_ISH_UART1_RXD_PIN 54
+#define BXT_ISH_UART1_TXD_PIN 55
+#define BXT_ISH_UART1_RTS_B_PIN 56
+#define BXT_ISH_UART1_CTS_B_PIN 57
+#define BXT_ISH_UART2_RXD_PIN 58
+#define BXT_ISH_UART2_TXD_PIN 59
+#define BXT_ISH_UART2_RTS_B_PIN 60
+#define BXT_ISH_UART2_CTS_B_PIN 61
+#define BXT_GP_CAMERASB00_PIN 62
+#define BXT_GP_CAMERASB01_PIN 63
+#define BXT_GP_CAMERASB02_PIN 64
+#define BXT_GP_CAMERASB03_PIN 65
+#define BXT_GP_CAMERASB04_PIN 66
+#define BXT_GP_CAMERASB05_PIN 67
+#define BXT_GP_CAMERASB06_PIN 68
+#define BXT_GP_CAMERASB07_PIN 69
+#define BXT_GP_CAMERASB08_PIN 70
+#define BXT_GP_CAMERASB09_PIN 71
+#define BXT_GP_CAMERASB10_PIN 72
+#define BXT_GP_CAMERASB11_PIN 73
+
+#define BXT_HV_DDI0_DDC_SDA_OFFSET 264
+#define BXT_HV_DDI0_DDC_SCL_OFFSET 265
+#define BXT_HV_DDI1_DDC_SDA_OFFSET 266
+#define BXT_HV_DDI1_DDC_SCL_OFFSET 267
+#define BXT_DBI_SDA_OFFSET 268
+#define BXT_DBI_SCL_OFFSET 269
+#define BXT_PANEL0_VDDEN_OFFSET 270
+#define BXT_PANEL0_BKLTEN_OFFSET 271
+#define BXT_PANEL0_BKLTCTL_OFFSET 272
+#define BXT_PANEL1_VDDEN_OFFSET 273
+#define BXT_PANEL1_BKLTEN_OFFSET 274
+#define BXT_PANEL1_BKLTCTL_OFFSET 275
+#define BXT_DBI_CSX_OFFSET 276
+#define BXT_DBI_RESX_OFFSET 277
+#define BXT_GP_INTD_DSI_TE1_OFFSET 278
+#define BXT_GP_INTD_DSI_TE2_OFFSET 279
+#define BXT_USB_OC0_B_OFFSET 280
+#define BXT_USB_OC1_B_OFFSET 281
+#define BXT_MEX_WAKE0_B_OFFSET 282
+#define BXT_MEX_WAKE1_B_OFFSET 283
+#define BXT_EMMC0_CLK_OFFSET 284
+#define BXT_EMMC0_D0_OFFSET 285
+#define BXT_EMMC0_D1_OFFSET 286
+#define BXT_EMMC0_D2_OFFSET 287
+#define BXT_EMMC0_D3_OFFSET 288
+#define BXT_EMMC0_D4_OFFSET 289
+#define BXT_EMMC0_D5_OFFSET 290
+#define BXT_EMMC0_D6_OFFSET 291
+#define BXT_EMMC0_D7_OFFSET 292
+#define BXT_EMMC0_CMD_OFFSET 293
+#define BXT_SDIO_CLK_OFFSET 294
+#define BXT_SDIO_D0_OFFSET 295
+#define BXT_SDIO_D1_OFFSET 296
+#define BXT_SDIO_D2_OFFSET 297
+#define BXT_SDIO_D3_OFFSET 298
+#define BXT_SDIO_CMD_OFFSET 299
+#define BXT_SDCARD_CLK_OFFSET 300
+#define BXT_SDCARD_D0_OFFSET 301
+#define BXT_SDCARD_D1_OFFSET 302
+#define BXT_SDCARD_D2_OFFSET 303
+#define BXT_SDCARD_D3_OFFSET 304
+#define BXT_SDCARD_CD_B_OFFSET 305
+#define BXT_SDCARD_CMD_OFFSET 306
+#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307
+#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308
+#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309
+#define BXT_EMMC0_STROBE_OFFSET 310
+#define BXT_SDIO_PWR_DOWN_B_OFFSET 311
+#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312
+#define BXT_SDCARD_LVL_SEL_OFFSET 313
+#define BXT_SDCARD_LVL_WP_OFFSET 314
+#define BXT_LPSS_I2C0_SDA_OFFSET 315
+#define BXT_LPSS_I2C0_SCL_OFFSET 316
+#define BXT_LPSS_I2C1_SDA_OFFSET 317
+#define BXT_LPSS_I2C1_SCL_OFFSET 318
+#define BXT_LPSS_I2C2_SDA_OFFSET 319
+#define BXT_LPSS_I2C2_SCL_OFFSET 320
+#define BXT_LPSS_I2C3_SDA_OFFSET 321
+#define BXT_LPSS_I2C3_SCL_OFFSET 322
+#define BXT_LPSS_I2C4_SDA_OFFSET 323
+#define BXT_LPSS_I2C4_SCL_OFFSET 324
+#define BXT_LPSS_I2C5_SDA_OFFSET 325
+#define BXT_LPSS_I2C5_SCL_OFFSET 326
+#define BXT_LPSS_I2C6_SDA_OFFSET 327
+#define BXT_LPSS_I2C6_SCL_OFFSET 328
+#define BXT_LPSS_I2C7_SDA_OFFSET 329
+#define BXT_LPSS_I2C7_SCL_OFFSET 330
+#define BXT_ISH_I2C0_SDA_OFFSET 331
+#define BXT_ISH_I2C0_SCL_OFFSET 332
+#define BXT_ISH_I2C1_SDA_OFFSET 333
+#define BXT_ISH_I2C1_SCL_OFFSET 334
+#define BXT_ISH_I2C2_SDA_OFFSET 335
+#define BXT_ISH_I2C2_SCL_OFFSET 336
+#define BXT_ISH_GPIO_0_OFFSET 337
+#define BXT_ISH_GPIO_1_OFFSET 338
+#define BXT_ISH_GPIO_2_OFFSET 339
+#define BXT_ISH_GPIO_3_OFFSET 340
+#define BXT_ISH_GPIO_4_OFFSET 341
+#define BXT_ISH_GPIO_5_OFFSET 342
+#define BXT_ISH_GPIO_6_OFFSET 343
+#define BXT_ISH_GPIO_7_OFFSET 344
+#define BXT_ISH_GPIO_8_OFFSET 345
+#define BXT_ISH_GPIO_9_OFFSET 346
+#define BXT_AVS_I2S1_MCLK_OFFSET 378
+#define BXT_AVS_I2S1_BCLK_OFFSET 379
+#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380
+#define BXT_AVS_I2S1_SDI_OFFSET 381
+#define BXT_AVS_I2S1_SDO_OFFSET 382
+#define BXT_AVS_M_CLK_A1_OFFSET 383
+#define BXT_AVS_M_CLK_B1_OFFSET 384
+#define BXT_AVS_M_DATA_1_OFFSET 385
+#define BXT_AVS_M_CLK_AB2_OFFSET 386
+#define BXT_AVS_M_DATA_2_OFFSET 387
+#define BXT_AVS_I2S2_MCLK_OFFSET 388
+#define BXT_AVS_I2S2_BCLK_OFFSET 389
+#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390
+#define BXT_AVS_I2S2_SDI_OFFSET 391
+#define BXT_AVS_I2S2_SDO_OFFSET 392
+#define BXT_AVS_I2S3_BCLK_OFFSET 393
+#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394
+#define BXT_AVS_I2S3_SDI_OFFSET 395
+#define BXT_AVS_I2S3_SDO_OFFSET 396
+#define BXT_AVS_I2S4_BCLK_OFFSET 397
+#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398
+#define BXT_AVS_I2S4_SDI_OFFSET 399
+#define BXT_AVS_I2S4_SDO_OFFSET 400
+#define BXT_FST_SPI_CS0_B_OFFSET 402
+#define BXT_FST_SPI_CS1_B_OFFSET 403
+#define BXT_FST_SPI_MOSI_IO0_OFFSET 404
+#define BXT_FST_SPI_MISO_IO1_OFFSET 405
+#define BXT_FST_SPI_IO2_OFFSET 406
+#define BXT_FST_SPI_IO3_OFFSET 407
+#define BXT_FST_SPI_CLK_OFFSET 408
+#define BXT_GP_SSP_0_CLK_OFFSET 410
+#define BXT_GP_SSP_0_FS0_OFFSET 411
+#define BXT_GP_SSP_0_FS1_OFFSET 412
+#define BXT_GP_SSP_0_FS2_OFFSET 413
+#define BXT_GP_SSP_0_RXD_OFFSET 414
+#define BXT_GP_SSP_0_TXD_OFFSET 415
+#define BXT_GP_SSP_1_CLK_OFFSET 416
+#define BXT_GP_SSP_1_FS0_OFFSET 417
+#define BXT_GP_SSP_1_FS1_OFFSET 418
+#define BXT_GP_SSP_1_FS2_OFFSET 419
+#define BXT_GP_SSP_1_FS3_OFFSET 420
+#define BXT_GP_SSP_1_RXD_OFFSET 421
+#define BXT_GP_SSP_1_TXD_OFFSET 422
+#define BXT_GP_SSP_2_CLK_OFFSET 423
+#define BXT_GP_SSP_2_FS0_OFFSET 424
+#define BXT_GP_SSP_2_FS1_OFFSET 425
+#define BXT_GP_SSP_2_FS2_OFFSET 426
+#define BXT_GP_SSP_2_RXD_OFFSET 427
+#define BXT_GP_SSP_2_TXD_OFFSET 428
+#define BXT_TRACE_0_CLK_VNN_OFFSET 429
+#define BXT_TRACE_0_DATA0_VNN_OFFSET 430
+#define BXT_TRACE_0_DATA1_VNN_OFFSET 431
+#define BXT_TRACE_0_DATA2_VNN_OFFSET 432
+#define BXT_TRACE_0_DATA3_VNN_OFFSET 433
+#define BXT_TRACE_0_DATA4_VNN_OFFSET 434
+#define BXT_TRACE_0_DATA5_VNN_OFFSET 435
+#define BXT_TRACE_0_DATA6_VNN_OFFSET 436
+#define BXT_TRACE_0_DATA7_VNN_OFFSET 437
+#define BXT_TRACE_1_CLK_VNN_OFFSET 438
+#define BXT_TRACE_1_DATA0_VNN_OFFSET 439
+#define BXT_TRACE_1_DATA1_VNN_OFFSET 440
+#define BXT_TRACE_1_DATA2_VNN_OFFSET 441
+#define BXT_TRACE_1_DATA3_VNN_OFFSET 442
+#define BXT_TRACE_1_DATA4_VNN_OFFSET 443
+#define BXT_TRACE_1_DATA5_VNN_OFFSET 444
+#define BXT_TRACE_1_DATA6_VNN_OFFSET 445
+#define BXT_TRACE_1_DATA7_VNN_OFFSET 446
+#define BXT_TRACE_2_CLK_VNN_OFFSET 447
+#define BXT_TRACE_2_DATA0_VNN_OFFSET 448
+#define BXT_TRACE_2_DATA1_VNN_OFFSET 449
+#define BXT_TRACE_2_DATA2_VNN_OFFSET 450
+#define BXT_TRACE_2_DATA3_VNN_OFFSET 451
+#define BXT_TRACE_2_DATA4_VNN_OFFSET 452
+#define BXT_TRACE_2_DATA5_VNN_OFFSET 453
+#define BXT_TRACE_2_DATA6_VNN_OFFSET 454
+#define BXT_TRACE_2_DATA7_VNN_OFFSET 455
+#define BXT_TRIGOUT_0_OFFSET 456
+#define BXT_TRIGOUT_1_OFFSET 457
+#define BXT_TRIGIN_0_OFFSET 458
+#define BXT_SEC_TCK_OFFSET 459
+#define BXT_SEC_TDI_OFFSET 460
+#define BXT_SEC_TMS_OFFSET 461
+#define BXT_SEC_TDO_OFFSET 462
+#define BXT_PWM0_OFFSET 463
+#define BXT_PWM1_OFFSET 464
+#define BXT_PWM2_OFFSET 465
+#define BXT_PWM3_OFFSET 466
+#define BXT_LPSS_UART0_RXD_OFFSET 467
+#define BXT_LPSS_UART0_TXD_OFFSET 468
+#define BXT_LPSS_UART0_RTS_B_OFFSET 469
+#define BXT_LPSS_UART0_CTS_B_OFFSET 470
+#define BXT_LPSS_UART1_RXD_OFFSET 471
+#define BXT_LPSS_UART1_TXD_OFFSET 472
+#define BXT_LPSS_UART1_RTS_B_OFFSET 473
+#define BXT_LPSS_UART1_CTS_B_OFFSET 474
+#define BXT_LPSS_UART2_RXD_OFFSET 475
+#define BXT_LPSS_UART2_TXD_OFFSET 476
+#define BXT_LPSS_UART2_RTS_B_OFFSET 477
+#define BXT_LPSS_UART2_CTS_B_OFFSET 478
+#define BXT_ISH_UART0_RXD_OFFSET 479
+#define BXT_ISH_UART0_TXD_OFFSET 480
+#define BXT_ISH_UART0_RTS_B_OFFSET 481
+#define BXT_ISH_UART0_CTS_B_OFFSET 482
+#define BXT_ISH_UART1_RXD_OFFSET 483
+#define BXT_ISH_UART1_TXD_OFFSET 484
+#define BXT_ISH_UART1_RTS_B_OFFSET 485
+#define BXT_ISH_UART1_CTS_B_OFFSET 486
+#define BXT_ISH_UART2_RXD_OFFSET 487
+#define BXT_ISH_UART2_TXD_OFFSET 488
+#define BXT_ISH_UART2_RTS_B_OFFSET 489
+#define BXT_ISH_UART2_CTS_B_OFFSET 490
+#define BXT_GP_CAMERASB00_OFFSET 491
+#define BXT_GP_CAMERASB01_OFFSET 492
+#define BXT_GP_CAMERASB02_OFFSET 493
+#define BXT_GP_CAMERASB03_OFFSET 494
+#define BXT_GP_CAMERASB04_OFFSET 495
+#define BXT_GP_CAMERASB05_OFFSET 496
+#define BXT_GP_CAMERASB06_OFFSET 497
+#define BXT_GP_CAMERASB07_OFFSET 498
+#define BXT_GP_CAMERASB08_OFFSET 499
+#define BXT_GP_CAMERASB09_OFFSET 500
+#define BXT_GP_CAMERASB10_OFFSET 501
+#define BXT_GP_CAMERASB11_OFFSET 502
+
+static struct bxt_gpio_table bxt_gtable[] = {
+ {BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET},
+ {BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET},
+ {BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET},
+ {BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET},
+ {BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET},
+ {BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET},
+ {BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET},
+ {BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET},
+ {BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET},
+ {BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET},
+ {BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET},
+ {BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET},
+ {BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET},
+ {BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET},
+ {BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET},
+ {BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET},
+ {BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET},
+ {BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET},
+ {BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET},
+ {BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET},
+ {BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET},
+ {BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET},
+ {BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET},
+ {BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET},
+ {BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET},
+ {BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET},
+ {BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET},
+ {BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET},
+ {BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET},
+ {BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET},
+ {BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET},
+ {BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET},
+ {BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET},
+ {BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET},
+ {BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET},
+ {BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET},
+ {BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET},
+ {BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET},
+ {BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET},
+ {BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET},
+ {BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET},
+ {BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET},
+ {BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET},
+ {BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET},
+ {BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET},
+ {BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET},
+ {BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET},
+ {BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET},
+ {BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET},
+ {BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET},
+ {BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET},
+ {BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET},
+ {BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET},
+ {BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET},
+ {BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET},
+ {BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET},
+ {BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET},
+ {BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET},
+ {BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET},
+ {BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET},
+ {BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET},
+ {BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET},
+ {BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET},
+ {BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET},
+ {BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET},
+ {BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET},
+ {BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET},
+ {BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET},
+ {BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET},
+ {BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET},
+ {BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET},
+ {BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET},
+ {BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET},
+ {BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET},
+ {BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET},
+ {BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET},
+ {BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET},
+ {BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET},
+ {BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET},
+ {BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET},
+ {BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET},
+ {BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET},
+ {BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET},
+ {BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET},
+ {BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET},
+ {BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET},
+ {BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET},
+ {BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET},
+ {BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET},
+ {BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET},
+ {BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET},
+ {BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET},
+ {BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET},
+ {BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET},
+ {BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET},
+ {BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET},
+ {BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET},
+ {BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET},
+ {BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET},
+ {BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET},
+ {BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET},
+ {BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET},
+ {BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET},
+ {BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET},
+ {BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET},
+ {BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET},
+ {BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET},
+ {BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET},
+ {BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET},
+ {BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET},
+ {BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET},
+ {BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET},
+ {BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET},
+ {BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET},
+ {BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET},
+ {BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET},
+ {BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET},
+ {BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET},
+ {BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET},
+ {BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET},
+ {BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET},
+ {BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET},
+ {BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET},
+ {BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET},
+ {BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET},
+ {BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET},
+ {BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET},
+ {BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET},
+ {BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET},
+ {BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET},
+ {BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET},
+ {BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET},
+ {BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET},
+ {BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET},
+ {BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET},
+ {BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET},
+ {BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET},
+ {BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET},
+ {BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET},
+ {BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET},
+ {BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET},
+ {BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET},
+ {BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET},
+ {BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET},
+ {BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET},
+ {BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET},
+ {BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET},
+ {BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET},
+ {BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET},
+ {BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET},
+ {BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET},
+ {BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET},
+ {BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET},
+ {BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET},
+ {BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET},
+ {BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET},
+ {BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET},
+ {BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET},
+ {BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET},
+ {BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET},
+ {BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET},
+ {BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET},
+ {BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET},
+ {BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET},
+ {BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET},
+ {BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET},
+ {BXT_PWM0_PIN, BXT_PWM0_OFFSET},
+ {BXT_PWM1_PIN, BXT_PWM1_OFFSET},
+ {BXT_PWM2_PIN, BXT_PWM2_OFFSET},
+ {BXT_PWM3_PIN, BXT_PWM3_OFFSET},
+ {BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET},
+ {BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET},
+ {BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET},
+ {BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET},
+ {BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET},
+ {BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET},
+ {BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET},
+ {BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET},
+ {BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET},
+ {BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET},
+ {BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET},
+ {BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET},
+ {BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET},
+ {BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET},
+ {BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET},
+ {BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET},
+ {BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET},
+ {BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET},
+ {BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET},
+ {BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET},
+ {BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET},
+ {BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET},
+ {BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET},
+ {BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET},
+ {BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET},
+ {BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET},
+ {BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET},
+ {BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET},
+ {BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET},
+ {BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET},
+ {BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET},
+ {BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET},
+ {BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET},
+ {BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET},
+ {BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET},
+ {BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET},
+};
+
static inline enum port intel_dsi_seq_port_to_port(u8 port)
{
return port ? PORT_C : PORT_A;
@@ -774,6 +1403,32 @@ void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
}
+void bxt_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
+{
+ u16 function = 0, i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(bxt_gtable); i++)
+ if (bxt_gtable[i].gpio_pin == gpio)
+ function = bxt_gtable[i].offset;
+
+ if (!function) {
+ DRM_ERROR("GPIO number is not present in the table\n");
+ return;
+ }
+
+ err = gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
+ if (err) {
+ DRM_ERROR("unable to request GPIO %d\n", function);
+ goto free_gpio;
+ }
+
+ gpio_set_value(function, action);
+
+free_gpio:
+ gpio_free(function);
+}
+
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
u8 gpio, action;
@@ -795,15 +1450,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
goto out;
}
- if (!IS_VALLEYVIEW(dev_priv)) {
- DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
- goto out;
- }
-
if (IS_VALLEYVIEW(dev))
vlv_program_gpio(intel_dsi, gpio, action);
else if (IS_CHERRYVIEW(dev))
chv_program_gpio(intel_dsi, gpio, action);
+ else if (IS_BROXTON(dev))
+ bxt_program_gpio(intel_dsi, gpio, action);
else
DRM_ERROR("GPIO programming missing for this platform.\n");
--
1.9.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [GPIO PATCH 1/2] drm/i915: GPIO for CHT generic MIPI
2016-02-22 13:25 ` [GPIO PATCH 1/2] " Deepak M
@ 2016-02-22 13:40 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2016-02-22 13:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Mon, 22 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
>
> The GPIO configuration and register offsets are different from
> baytrail for cherrytrail. Port the gpio programming accordingly
> for cherrytrail in this patch.
>
> v2: Removing the duplication of parsing
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 107 ++++++++++++++++++++++-------
> 2 files changed, 102 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 606dc71..fc57477 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IOSF_PORT_NC 0x11
> #define IOSF_PORT_DPIO 0x12
> #define IOSF_PORT_GPIO_NC 0x13
> +#define CHV_IOSF_PORT_GPIO_N 0x13
> +#define CHV_IOSF_PORT_GPIO_SE 0x48
> +#define CHV_IOSF_PORT_GPIO_SW 0xB2
> +#define CHV_IOSF_PORT_GPIO_E 0xA8
> +#define CHV_MAX_GPIO_NUM_N 72
> +#define CHV_MAX_GPIO_NUM_SE 99
> +#define CHV_MAX_GPIO_NUM_SW 197
> +#define CHV_MIN_GPIO_NUM_SE 73
> +#define CHV_MIN_GPIO_NUM_SW 100
> +#define CHV_MIN_GPIO_NUM_E 198
These GPIO num definitions are not part of the *register*
definition. It's confusing to have them here.
I think for now I'd just stick them in intel_dsi_panel_vbt.c where you
use them.
> #define IOSF_PORT_CCK 0x14
> #define IOSF_PORT_DPIO_2 0x1a
> #define IOSF_PORT_FLISDSI 0x1b
> @@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VLV_GPIO_CFG 0x2000CC00
> #define VLV_GPIO_INPUT_DIS 0x04
>
> +#define CHV_PAD_FMLY_BASE 0x4400
> +#define CHV_PAD_FMLY_SIZE 0x400
> +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
> +#define CHV_PAD_CFG_REG_SIZE 0x4
> +#define CHV_VBT_MAX_PINS_PER_FMLY 15
> +
> +#define CHV_GPIO_CFG_UNLOCK 0x00000000
> +#define CHV_GPIO_CFG_HIZ 0x00008100
> +#define CHV_GPIO_CFG_TX_STATE_SHIFT 1
Ditto.
> +
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 794bd1f..4849515 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -685,34 +685,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
> return data;
> }
>
> -static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> +void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
> {
> - u8 gpio, action;
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> u16 function, pad;
> u32 val;
> u8 port;
> - struct drm_device *dev = intel_dsi->base.base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> -
> - if (dev_priv->vbt.dsi.seq_version >= 3)
> - data++;
> -
> - gpio = *data++;
> -
> - /* pull up/down */
> - action = *data++ & 1;
> -
> - if (gpio >= ARRAY_SIZE(gtable)) {
> - DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> - goto out;
> - }
> -
> - if (!IS_VALLEYVIEW(dev_priv)) {
> - DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> - goto out;
> - }
>
> if (dev_priv->vbt.dsi.seq_version >= 3) {
> if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
> @@ -728,7 +707,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> port = IOSF_PORT_GPIO_SUS;
> } else {
> DRM_ERROR("GPIO number is not present in the table\n");
> - goto out;
> + return;
> }
> } else {
> port = IOSF_PORT_GPIO_NC;
> @@ -750,11 +729,89 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> /* pull up/down */
> vlv_iosf_sb_write(dev_priv, port, pad, val);
> mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
> +{
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u16 function, pad;
> + u16 family_num;
> + u8 block;
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3) {
> + if (gpio <= CHV_MAX_GPIO_NUM_N) {
> + block = CHV_IOSF_PORT_GPIO_N;
> + DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
> + } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
> + block = CHV_IOSF_PORT_GPIO_SE;
> + gpio = gpio - CHV_MIN_GPIO_NUM_SE;
> + DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
> + } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
> + block = CHV_IOSF_PORT_GPIO_SW;
> + gpio = gpio - CHV_MIN_GPIO_NUM_SW;
> + DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
> + } else {
> + block = CHV_IOSF_PORT_GPIO_E;
> + gpio = gpio - CHV_MIN_GPIO_NUM_E;
> + DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
> + }
> + } else
> + block = IOSF_PORT_GPIO_NC;
> +
> + family_num = gpio / CHV_VBT_MAX_PINS_PER_FMLY;
> + gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
> + pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
> + (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
> + function = pad + CHV_PAD_CFG_REG_SIZE;
> +
> + mutex_lock(&dev_priv->sb_lock);
> + vlv_iosf_sb_write(dev_priv, block, function,
> + CHV_GPIO_CFG_UNLOCK);
> + vlv_iosf_sb_write(dev_priv, block, pad, CHV_GPIO_CFG_HIZ |
> + (action << CHV_GPIO_CFG_TX_STATE_SHIFT));
> + mutex_unlock(&dev_priv->sb_lock);
> +
> +}
> +
> +static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> +{
> + u8 gpio, action;
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> +
> + if (dev_priv->vbt.dsi.seq_version >= 3)
> + data++;
> +
> + gpio = *data++;
> +
> + /* pull up/down */
> + action = *data++ & 1;
> +
> + if (gpio >= ARRAY_SIZE(gtable)) {
> + DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
> + goto out;
> + }
> +
> + if (!IS_VALLEYVIEW(dev_priv)) {
> + DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> + goto out;
> + }
This will bail out on chv as well.
> +
> + if (IS_VALLEYVIEW(dev))
> + vlv_program_gpio(intel_dsi, gpio, action);
> + else if (IS_CHERRYVIEW(dev))
> + chv_program_gpio(intel_dsi, gpio, action);
> + else
> + DRM_ERROR("GPIO programming missing for this platform.\n");
>
> out:
> return data;
> }
>
> +
Superfluous whitespace.
> static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data)
> {
> return data + *(data + 6) + 7;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev4)
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
` (4 preceding siblings ...)
2016-02-19 15:15 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev2) Patchwork
@ 2016-02-22 13:47 ` Patchwork
5 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2016-02-22 13:47 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Summary ==
Series 3623v4 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3623/revisions/4/mbox/
Test gem_cs_prefetch:
Subgroup basic-default:
incomplete -> PASS (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> FAIL (hsw-gt2)
bdw-nuci7 total:165 pass:154 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:168 pass:154 dwarn:0 dfail:0 fail:0 skip:14
bsw-nuc-2 total:168 pass:137 dwarn:0 dfail:0 fail:1 skip:30
hsw-gt2 total:168 pass:156 dwarn:0 dfail:1 fail:1 skip:10
ilk-hp8440p total:168 pass:118 dwarn:0 dfail:0 fail:1 skip:49
ivb-t430s total:168 pass:153 dwarn:0 dfail:0 fail:1 skip:14
skl-i5k-2 total:168 pass:151 dwarn:1 dfail:0 fail:0 skip:16
snb-dellxps total:168 pass:145 dwarn:0 dfail:0 fail:1 skip:22
snb-x220t total:168 pass:145 dwarn:0 dfail:1 fail:1 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1455/
c278ff791cc73f90079c86f343be16214a0038b7 drm-intel-nightly: 2016y-02m-22d-09h-17m-11s UTC integration manifest
c930217291f81e46d6db7703d4c79c6215e99a37 drm/i915: GPIO for BXT generic MIPI
a14c38d52e511e96f4180de113654a8d3b952dc8 drm/i915: GPIO for CHT generic MIPI
bbd248d386c9cd5107f736ddf02c21f98987282a drm/i915/dsi: Added the generic gpio sequence support and gpio table
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI
2016-02-22 13:26 ` [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI Deepak M
@ 2016-02-22 14:04 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2016-02-22 14:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Mon, 22 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> From: Uma Shankar <uma.shankar@intel.com>
>
> Added the BXT GPIO pin configuration and programming logic for
> backlight and panel control.
>
> v2 by Deepak
> - Added the GPIO table got BXT.
> - Added gpio_free
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 662 ++++++++++++++++++++++++++++-
> 1 file changed, 657 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 4849515..4fcc755 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
> #include <drm/drm_edid.h>
> #include <drm/i915_drm.h>
> #include <drm/drm_panel.h>
> +#include <linux/gpio.h>
> #include <linux/slab.h>
> #include <video/mipi_display.h>
> #include <asm/intel-mid.h>
> @@ -593,6 +594,634 @@ static struct gpio_table gtable[] = {
> { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
> };
>
> +struct bxt_gpio_table {
> + u16 gpio_pin;
> + u16 offset;
> +};
> +
> +#define BXT_HV_DDI0_DDC_SDA_PIN 187
> +#define BXT_HV_DDI0_DDC_SCL_PIN 188
> +#define BXT_HV_DDI1_DDC_SDA_PIN 189
> +#define BXT_HV_DDI1_DDC_SCL_PIN 190
> +#define BXT_DBI_SDA_PIN 191
> +#define BXT_DBI_SCL_PIN 192
> +#define BXT_PANEL0_VDDEN_PIN 193
> +#define BXT_PANEL0_BKLTEN_PIN 194
> +#define BXT_PANEL0_BKLTCTL_PIN 195
> +#define BXT_PANEL1_VDDEN_PIN 196
> +#define BXT_PANEL1_BKLTEN_PIN 197
> +#define BXT_PANEL1_BKLTCTL_PIN 198
> +#define BXT_DBI_CSX_PIN 199
> +#define BXT_DBI_RESX_PIN 200
> +#define BXT_GP_INTD_DSI_TE1_PIN 201
> +#define BXT_GP_INTD_DSI_TE2_PIN 202
> +#define BXT_USB_OC0_B_PIN 203
> +#define BXT_USB_OC1_B_PIN 204
> +#define BXT_MEX_WAKE0_B_PIN 205
> +#define BXT_MEX_WAKE1_B_PIN 206
> +#define BXT_EMMC0_CLK_PIN 156
> +#define BXT_EMMC0_D0_PIN 157
> +#define BXT_EMMC0_D1_PIN 158
> +#define BXT_EMMC0_D2_PIN 159
> +#define BXT_EMMC0_D3_PIN 160
> +#define BXT_EMMC0_D4_PIN 161
> +#define BXT_EMMC0_D5_PIN 162
> +#define BXT_EMMC0_D6_PIN 163
> +#define BXT_EMMC0_D7_PIN 164
> +#define BXT_EMMC0_CMD_PIN 165
> +#define BXT_SDIO_CLK_PIN 166
> +#define BXT_SDIO_D0_PIN 167
> +#define BXT_SDIO_D1_PIN 168
> +#define BXT_SDIO_D2_PIN 169
> +#define BXT_SDIO_D3_PIN 170
> +#define BXT_SDIO_CMD_PIN 171
> +#define BXT_SDCARD_CLK_PIN 172
> +#define BXT_SDCARD_D0_PIN 173
> +#define BXT_SDCARD_D1_PIN 174
> +#define BXT_SDCARD_D2_PIN 175
> +#define BXT_SDCARD_D3_PIN 176
> +#define BXT_SDCARD_CD_B_PIN 177
> +#define BXT_SDCARD_CMD_PIN 178
> +#define BXT_SDCARD_LVL_CLK_FB_PIN 179
> +#define BXT_SDCARD_LVL_CMD_DIR_PIN 180
> +#define BXT_SDCARD_LVL_DAT_DIR_PIN 181
> +#define BXT_EMMC0_STROBE_PIN 182
> +#define BXT_SDIO_PWR_DOWN_B_PIN 183
> +#define BXT_SDCARD_PWR_DOWN_B_PIN 184
> +#define BXT_SDCARD_LVL_SEL_PIN 185
> +#define BXT_SDCARD_LVL_WP_PIN 186
> +#define BXT_LPSS_I2C0_SDA_PIN 124
> +#define BXT_LPSS_I2C0_SCL_PIN 125
> +#define BXT_LPSS_I2C1_SDA_PIN 126
> +#define BXT_LPSS_I2C1_SCL_PIN 127
> +#define BXT_LPSS_I2C2_SDA_PIN 128
> +#define BXT_LPSS_I2C2_SCL_PIN 129
> +#define BXT_LPSS_I2C3_SDA_PIN 130
> +#define BXT_LPSS_I2C3_SCL_PIN 131
> +#define BXT_LPSS_I2C4_SDA_PIN 132
> +#define BXT_LPSS_I2C4_SCL_PIN 133
> +#define BXT_LPSS_I2C5_SDA_PIN 134
> +#define BXT_LPSS_I2C5_SCL_PIN 135
> +#define BXT_LPSS_I2C6_SDA_PIN 136
> +#define BXT_LPSS_I2C6_SCL_PIN 137
> +#define BXT_LPSS_I2C7_SDA_PIN 138
> +#define BXT_LPSS_I2C7_SCL_PIN 139
> +#define BXT_ISH_I2C0_SDA_PIN 140
> +#define BXT_ISH_I2C0_SCL_PIN 141
> +#define BXT_ISH_I2C1_SDA_PIN 142
> +#define BXT_ISH_I2C1_SCL_PIN 143
> +#define BXT_ISH_I2C2_SDA_PIN 144
> +#define BXT_ISH_I2C2_SCL_PIN 145
> +#define BXT_ISH_GPIO_0_PIN 146
> +#define BXT_ISH_GPIO_1_PIN 147
> +#define BXT_ISH_GPIO_2_PIN 148
> +#define BXT_ISH_GPIO_3_PIN 149
> +#define BXT_ISH_GPIO_4_PIN 150
> +#define BXT_ISH_GPIO_5_PIN 151
> +#define BXT_ISH_GPIO_6_PIN 152
> +#define BXT_ISH_GPIO_7_PIN 153
> +#define BXT_ISH_GPIO_8_PIN 154
> +#define BXT_ISH_GPIO_9_PIN 155
> +#define BXT_AVS_I2S1_MCLK_PIN 74
> +#define BXT_AVS_I2S1_BCLK_PIN 75
> +#define BXT_AVS_I2S1_WS_SYNC_PIN 76
> +#define BXT_AVS_I2S1_SDI_PIN 77
> +#define BXT_AVS_I2S1_SDO_PIN 78
> +#define BXT_AVS_M_CLK_A1_PIN 79
> +#define BXT_AVS_M_CLK_B1_PIN 80
> +#define BXT_AVS_M_DATA_1_PIN 81
> +#define BXT_AVS_M_CLK_AB2_PIN 82
> +#define BXT_AVS_M_DATA_2_PIN 83
> +#define BXT_AVS_I2S2_MCLK_PIN 84
> +#define BXT_AVS_I2S2_BCLK_PIN 85
> +#define BXT_AVS_I2S2_WS_SYNC_PIN 86
> +#define BXT_AVS_I2S2_SDI_PIN 87
> +#define BXT_AVS_I2S2_SDO_PIN 88
> +#define BXT_AVS_I2S3_BCLK_PIN 89
> +#define BXT_AVS_I2S3_WS_SYNC_PIN 90
> +#define BXT_AVS_I2S3_SDI_PIN 91
> +#define BXT_AVS_I2S3_SDO_PIN 92
> +#define BXT_AVS_I2S4_BCLK_PIN 93
> +#define BXT_AVS_I2S4_WS_SYNC_PIN 94
> +#define BXT_AVS_I2S4_SDI_PIN 95
> +#define BXT_AVS_I2S4_SDO_PIN 96
> +#define BXT_FST_SPI_CS0_B_PIN 97
> +#define BXT_FST_SPI_CS1_B_PIN 98
> +#define BXT_FST_SPI_MOSI_IO0_PIN 99
> +#define BXT_FST_SPI_MISO_IO1_PIN 100
> +#define BXT_FST_SPI_IO2_PIN 101
> +#define BXT_FST_SPI_IO3_PIN 102
> +#define BXT_FST_SPI_CLK_PIN 103
> +#define BXT_GP_SSP_0_CLK_PIN 104
> +#define BXT_GP_SSP_0_FS0_PIN 105
> +#define BXT_GP_SSP_0_FS1_PIN 106
> +#define BXT_GP_SSP_0_FS2_PIN 107
> +#define BXT_GP_SSP_0_RXD_PIN 109
> +#define BXT_GP_SSP_0_TXD_PIN 110
> +#define BXT_GP_SSP_1_CLK_PIN 111
> +#define BXT_GP_SSP_1_FS0_PIN 112
> +#define BXT_GP_SSP_1_FS1_PIN 113
> +#define BXT_GP_SSP_1_FS2_PIN 114
> +#define BXT_GP_SSP_1_FS3_PIN 115
> +#define BXT_GP_SSP_1_RXD_PIN 116
> +#define BXT_GP_SSP_1_TXD_PIN 117
> +#define BXT_GP_SSP_2_CLK_PIN 118
> +#define BXT_GP_SSP_2_FS0_PIN 119
> +#define BXT_GP_SSP_2_FS1_PIN 120
> +#define BXT_GP_SSP_2_FS2_PIN 121
> +#define BXT_GP_SSP_2_RXD_PIN 122
> +#define BXT_GP_SSP_2_TXD_PIN 123
> +#define BXT_TRACE_0_CLK_VNN_PIN 0
> +#define BXT_TRACE_0_DATA0_VNN_PIN 1
> +#define BXT_TRACE_0_DATA1_VNN_PIN 2
> +#define BXT_TRACE_0_DATA2_VNN_PIN 3
> +#define BXT_TRACE_0_DATA3_VNN_PIN 4
> +#define BXT_TRACE_0_DATA4_VNN_PIN 5
> +#define BXT_TRACE_0_DATA5_VNN_PIN 6
> +#define BXT_TRACE_0_DATA6_VNN_PIN 7
> +#define BXT_TRACE_0_DATA7_VNN_PIN 8
> +#define BXT_TRACE_1_CLK_VNN_PIN 9
> +#define BXT_TRACE_1_DATA0_VNN_PIN 10
> +#define BXT_TRACE_1_DATA1_VNN_PIN 11
> +#define BXT_TRACE_1_DATA2_VNN_PIN 12
> +#define BXT_TRACE_1_DATA3_VNN_PIN 13
> +#define BXT_TRACE_1_DATA4_VNN_PIN 14
> +#define BXT_TRACE_1_DATA5_VNN_PIN 15
> +#define BXT_TRACE_1_DATA6_VNN_PIN 16
> +#define BXT_TRACE_1_DATA7_VNN_PIN 17
> +#define BXT_TRACE_2_CLK_VNN_PIN 18
> +#define BXT_TRACE_2_DATA0_VNN_PIN 19
> +#define BXT_TRACE_2_DATA1_VNN_PIN 20
> +#define BXT_TRACE_2_DATA2_VNN_PIN 21
> +#define BXT_TRACE_2_DATA3_VNN_PIN 22
> +#define BXT_TRACE_2_DATA4_VNN_PIN 23
> +#define BXT_TRACE_2_DATA5_VNN_PIN 24
> +#define BXT_TRACE_2_DATA6_VNN_PIN 25
> +#define BXT_TRACE_2_DATA7_VNN_PIN 26
> +#define BXT_TRIGOUT_0_PIN 27
> +#define BXT_TRIGOUT_1_PIN 28
> +#define BXT_TRIGIN_0_PIN 29
> +#define BXT_SEC_TCK_PIN 30
> +#define BXT_SEC_TDI_PIN 31
> +#define BXT_SEC_TMS_PIN 32
> +#define BXT_SEC_TDO_PIN 33
> +#define BXT_PWM0_PIN 34
> +#define BXT_PWM1_PIN 35
> +#define BXT_PWM2_PIN 36
> +#define BXT_PWM3_PIN 37
> +#define BXT_LPSS_UART0_RXD_PIN 38
> +#define BXT_LPSS_UART0_TXD_PIN 39
> +#define BXT_LPSS_UART0_RTS_B_PIN 40
> +#define BXT_LPSS_UART0_CTS_B_PIN 41
> +#define BXT_LPSS_UART1_RXD_PIN 42
> +#define BXT_LPSS_UART1_TXD_PIN 43
> +#define BXT_LPSS_UART1_RTS_B_PIN 44
> +#define BXT_LPSS_UART1_CTS_B_PIN 45
> +#define BXT_LPSS_UART2_RXD_PIN 46
> +#define BXT_LPSS_UART2_TXD_PIN 47
> +#define BXT_LPSS_UART2_RTS_B_PIN 48
> +#define BXT_LPSS_UART2_CTS_B_PIN 49
> +#define BXT_ISH_UART0_RXD_PIN 50
> +#define BXT_ISH_UART0_TXD_PIN 51
> +#define BXT_ISH_UART0_RTS_B_PIN 52
> +#define BXT_ISH_UART0_CTS_B_PIN 53
> +#define BXT_ISH_UART1_RXD_PIN 54
> +#define BXT_ISH_UART1_TXD_PIN 55
> +#define BXT_ISH_UART1_RTS_B_PIN 56
> +#define BXT_ISH_UART1_CTS_B_PIN 57
> +#define BXT_ISH_UART2_RXD_PIN 58
> +#define BXT_ISH_UART2_TXD_PIN 59
> +#define BXT_ISH_UART2_RTS_B_PIN 60
> +#define BXT_ISH_UART2_CTS_B_PIN 61
> +#define BXT_GP_CAMERASB00_PIN 62
> +#define BXT_GP_CAMERASB01_PIN 63
> +#define BXT_GP_CAMERASB02_PIN 64
> +#define BXT_GP_CAMERASB03_PIN 65
> +#define BXT_GP_CAMERASB04_PIN 66
> +#define BXT_GP_CAMERASB05_PIN 67
> +#define BXT_GP_CAMERASB06_PIN 68
> +#define BXT_GP_CAMERASB07_PIN 69
> +#define BXT_GP_CAMERASB08_PIN 70
> +#define BXT_GP_CAMERASB09_PIN 71
> +#define BXT_GP_CAMERASB10_PIN 72
> +#define BXT_GP_CAMERASB11_PIN 73
> +
> +#define BXT_HV_DDI0_DDC_SDA_OFFSET 264
> +#define BXT_HV_DDI0_DDC_SCL_OFFSET 265
> +#define BXT_HV_DDI1_DDC_SDA_OFFSET 266
> +#define BXT_HV_DDI1_DDC_SCL_OFFSET 267
> +#define BXT_DBI_SDA_OFFSET 268
> +#define BXT_DBI_SCL_OFFSET 269
> +#define BXT_PANEL0_VDDEN_OFFSET 270
> +#define BXT_PANEL0_BKLTEN_OFFSET 271
> +#define BXT_PANEL0_BKLTCTL_OFFSET 272
> +#define BXT_PANEL1_VDDEN_OFFSET 273
> +#define BXT_PANEL1_BKLTEN_OFFSET 274
> +#define BXT_PANEL1_BKLTCTL_OFFSET 275
> +#define BXT_DBI_CSX_OFFSET 276
> +#define BXT_DBI_RESX_OFFSET 277
> +#define BXT_GP_INTD_DSI_TE1_OFFSET 278
> +#define BXT_GP_INTD_DSI_TE2_OFFSET 279
> +#define BXT_USB_OC0_B_OFFSET 280
> +#define BXT_USB_OC1_B_OFFSET 281
> +#define BXT_MEX_WAKE0_B_OFFSET 282
> +#define BXT_MEX_WAKE1_B_OFFSET 283
> +#define BXT_EMMC0_CLK_OFFSET 284
> +#define BXT_EMMC0_D0_OFFSET 285
> +#define BXT_EMMC0_D1_OFFSET 286
> +#define BXT_EMMC0_D2_OFFSET 287
> +#define BXT_EMMC0_D3_OFFSET 288
> +#define BXT_EMMC0_D4_OFFSET 289
> +#define BXT_EMMC0_D5_OFFSET 290
> +#define BXT_EMMC0_D6_OFFSET 291
> +#define BXT_EMMC0_D7_OFFSET 292
> +#define BXT_EMMC0_CMD_OFFSET 293
> +#define BXT_SDIO_CLK_OFFSET 294
> +#define BXT_SDIO_D0_OFFSET 295
> +#define BXT_SDIO_D1_OFFSET 296
> +#define BXT_SDIO_D2_OFFSET 297
> +#define BXT_SDIO_D3_OFFSET 298
> +#define BXT_SDIO_CMD_OFFSET 299
> +#define BXT_SDCARD_CLK_OFFSET 300
> +#define BXT_SDCARD_D0_OFFSET 301
> +#define BXT_SDCARD_D1_OFFSET 302
> +#define BXT_SDCARD_D2_OFFSET 303
> +#define BXT_SDCARD_D3_OFFSET 304
> +#define BXT_SDCARD_CD_B_OFFSET 305
> +#define BXT_SDCARD_CMD_OFFSET 306
> +#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307
> +#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308
> +#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309
> +#define BXT_EMMC0_STROBE_OFFSET 310
> +#define BXT_SDIO_PWR_DOWN_B_OFFSET 311
> +#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312
> +#define BXT_SDCARD_LVL_SEL_OFFSET 313
> +#define BXT_SDCARD_LVL_WP_OFFSET 314
> +#define BXT_LPSS_I2C0_SDA_OFFSET 315
> +#define BXT_LPSS_I2C0_SCL_OFFSET 316
> +#define BXT_LPSS_I2C1_SDA_OFFSET 317
> +#define BXT_LPSS_I2C1_SCL_OFFSET 318
> +#define BXT_LPSS_I2C2_SDA_OFFSET 319
> +#define BXT_LPSS_I2C2_SCL_OFFSET 320
> +#define BXT_LPSS_I2C3_SDA_OFFSET 321
> +#define BXT_LPSS_I2C3_SCL_OFFSET 322
> +#define BXT_LPSS_I2C4_SDA_OFFSET 323
> +#define BXT_LPSS_I2C4_SCL_OFFSET 324
> +#define BXT_LPSS_I2C5_SDA_OFFSET 325
> +#define BXT_LPSS_I2C5_SCL_OFFSET 326
> +#define BXT_LPSS_I2C6_SDA_OFFSET 327
> +#define BXT_LPSS_I2C6_SCL_OFFSET 328
> +#define BXT_LPSS_I2C7_SDA_OFFSET 329
> +#define BXT_LPSS_I2C7_SCL_OFFSET 330
> +#define BXT_ISH_I2C0_SDA_OFFSET 331
> +#define BXT_ISH_I2C0_SCL_OFFSET 332
> +#define BXT_ISH_I2C1_SDA_OFFSET 333
> +#define BXT_ISH_I2C1_SCL_OFFSET 334
> +#define BXT_ISH_I2C2_SDA_OFFSET 335
> +#define BXT_ISH_I2C2_SCL_OFFSET 336
> +#define BXT_ISH_GPIO_0_OFFSET 337
> +#define BXT_ISH_GPIO_1_OFFSET 338
> +#define BXT_ISH_GPIO_2_OFFSET 339
> +#define BXT_ISH_GPIO_3_OFFSET 340
> +#define BXT_ISH_GPIO_4_OFFSET 341
> +#define BXT_ISH_GPIO_5_OFFSET 342
> +#define BXT_ISH_GPIO_6_OFFSET 343
> +#define BXT_ISH_GPIO_7_OFFSET 344
> +#define BXT_ISH_GPIO_8_OFFSET 345
> +#define BXT_ISH_GPIO_9_OFFSET 346
> +#define BXT_AVS_I2S1_MCLK_OFFSET 378
> +#define BXT_AVS_I2S1_BCLK_OFFSET 379
> +#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380
> +#define BXT_AVS_I2S1_SDI_OFFSET 381
> +#define BXT_AVS_I2S1_SDO_OFFSET 382
> +#define BXT_AVS_M_CLK_A1_OFFSET 383
> +#define BXT_AVS_M_CLK_B1_OFFSET 384
> +#define BXT_AVS_M_DATA_1_OFFSET 385
> +#define BXT_AVS_M_CLK_AB2_OFFSET 386
> +#define BXT_AVS_M_DATA_2_OFFSET 387
> +#define BXT_AVS_I2S2_MCLK_OFFSET 388
> +#define BXT_AVS_I2S2_BCLK_OFFSET 389
> +#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390
> +#define BXT_AVS_I2S2_SDI_OFFSET 391
> +#define BXT_AVS_I2S2_SDO_OFFSET 392
> +#define BXT_AVS_I2S3_BCLK_OFFSET 393
> +#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394
> +#define BXT_AVS_I2S3_SDI_OFFSET 395
> +#define BXT_AVS_I2S3_SDO_OFFSET 396
> +#define BXT_AVS_I2S4_BCLK_OFFSET 397
> +#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398
> +#define BXT_AVS_I2S4_SDI_OFFSET 399
> +#define BXT_AVS_I2S4_SDO_OFFSET 400
> +#define BXT_FST_SPI_CS0_B_OFFSET 402
> +#define BXT_FST_SPI_CS1_B_OFFSET 403
> +#define BXT_FST_SPI_MOSI_IO0_OFFSET 404
> +#define BXT_FST_SPI_MISO_IO1_OFFSET 405
> +#define BXT_FST_SPI_IO2_OFFSET 406
> +#define BXT_FST_SPI_IO3_OFFSET 407
> +#define BXT_FST_SPI_CLK_OFFSET 408
> +#define BXT_GP_SSP_0_CLK_OFFSET 410
> +#define BXT_GP_SSP_0_FS0_OFFSET 411
> +#define BXT_GP_SSP_0_FS1_OFFSET 412
> +#define BXT_GP_SSP_0_FS2_OFFSET 413
> +#define BXT_GP_SSP_0_RXD_OFFSET 414
> +#define BXT_GP_SSP_0_TXD_OFFSET 415
> +#define BXT_GP_SSP_1_CLK_OFFSET 416
> +#define BXT_GP_SSP_1_FS0_OFFSET 417
> +#define BXT_GP_SSP_1_FS1_OFFSET 418
> +#define BXT_GP_SSP_1_FS2_OFFSET 419
> +#define BXT_GP_SSP_1_FS3_OFFSET 420
> +#define BXT_GP_SSP_1_RXD_OFFSET 421
> +#define BXT_GP_SSP_1_TXD_OFFSET 422
> +#define BXT_GP_SSP_2_CLK_OFFSET 423
> +#define BXT_GP_SSP_2_FS0_OFFSET 424
> +#define BXT_GP_SSP_2_FS1_OFFSET 425
> +#define BXT_GP_SSP_2_FS2_OFFSET 426
> +#define BXT_GP_SSP_2_RXD_OFFSET 427
> +#define BXT_GP_SSP_2_TXD_OFFSET 428
> +#define BXT_TRACE_0_CLK_VNN_OFFSET 429
> +#define BXT_TRACE_0_DATA0_VNN_OFFSET 430
> +#define BXT_TRACE_0_DATA1_VNN_OFFSET 431
> +#define BXT_TRACE_0_DATA2_VNN_OFFSET 432
> +#define BXT_TRACE_0_DATA3_VNN_OFFSET 433
> +#define BXT_TRACE_0_DATA4_VNN_OFFSET 434
> +#define BXT_TRACE_0_DATA5_VNN_OFFSET 435
> +#define BXT_TRACE_0_DATA6_VNN_OFFSET 436
> +#define BXT_TRACE_0_DATA7_VNN_OFFSET 437
> +#define BXT_TRACE_1_CLK_VNN_OFFSET 438
> +#define BXT_TRACE_1_DATA0_VNN_OFFSET 439
> +#define BXT_TRACE_1_DATA1_VNN_OFFSET 440
> +#define BXT_TRACE_1_DATA2_VNN_OFFSET 441
> +#define BXT_TRACE_1_DATA3_VNN_OFFSET 442
> +#define BXT_TRACE_1_DATA4_VNN_OFFSET 443
> +#define BXT_TRACE_1_DATA5_VNN_OFFSET 444
> +#define BXT_TRACE_1_DATA6_VNN_OFFSET 445
> +#define BXT_TRACE_1_DATA7_VNN_OFFSET 446
> +#define BXT_TRACE_2_CLK_VNN_OFFSET 447
> +#define BXT_TRACE_2_DATA0_VNN_OFFSET 448
> +#define BXT_TRACE_2_DATA1_VNN_OFFSET 449
> +#define BXT_TRACE_2_DATA2_VNN_OFFSET 450
> +#define BXT_TRACE_2_DATA3_VNN_OFFSET 451
> +#define BXT_TRACE_2_DATA4_VNN_OFFSET 452
> +#define BXT_TRACE_2_DATA5_VNN_OFFSET 453
> +#define BXT_TRACE_2_DATA6_VNN_OFFSET 454
> +#define BXT_TRACE_2_DATA7_VNN_OFFSET 455
> +#define BXT_TRIGOUT_0_OFFSET 456
> +#define BXT_TRIGOUT_1_OFFSET 457
> +#define BXT_TRIGIN_0_OFFSET 458
> +#define BXT_SEC_TCK_OFFSET 459
> +#define BXT_SEC_TDI_OFFSET 460
> +#define BXT_SEC_TMS_OFFSET 461
> +#define BXT_SEC_TDO_OFFSET 462
> +#define BXT_PWM0_OFFSET 463
> +#define BXT_PWM1_OFFSET 464
> +#define BXT_PWM2_OFFSET 465
> +#define BXT_PWM3_OFFSET 466
> +#define BXT_LPSS_UART0_RXD_OFFSET 467
> +#define BXT_LPSS_UART0_TXD_OFFSET 468
> +#define BXT_LPSS_UART0_RTS_B_OFFSET 469
> +#define BXT_LPSS_UART0_CTS_B_OFFSET 470
> +#define BXT_LPSS_UART1_RXD_OFFSET 471
> +#define BXT_LPSS_UART1_TXD_OFFSET 472
> +#define BXT_LPSS_UART1_RTS_B_OFFSET 473
> +#define BXT_LPSS_UART1_CTS_B_OFFSET 474
> +#define BXT_LPSS_UART2_RXD_OFFSET 475
> +#define BXT_LPSS_UART2_TXD_OFFSET 476
> +#define BXT_LPSS_UART2_RTS_B_OFFSET 477
> +#define BXT_LPSS_UART2_CTS_B_OFFSET 478
> +#define BXT_ISH_UART0_RXD_OFFSET 479
> +#define BXT_ISH_UART0_TXD_OFFSET 480
> +#define BXT_ISH_UART0_RTS_B_OFFSET 481
> +#define BXT_ISH_UART0_CTS_B_OFFSET 482
> +#define BXT_ISH_UART1_RXD_OFFSET 483
> +#define BXT_ISH_UART1_TXD_OFFSET 484
> +#define BXT_ISH_UART1_RTS_B_OFFSET 485
> +#define BXT_ISH_UART1_CTS_B_OFFSET 486
> +#define BXT_ISH_UART2_RXD_OFFSET 487
> +#define BXT_ISH_UART2_TXD_OFFSET 488
> +#define BXT_ISH_UART2_RTS_B_OFFSET 489
> +#define BXT_ISH_UART2_CTS_B_OFFSET 490
> +#define BXT_GP_CAMERASB00_OFFSET 491
> +#define BXT_GP_CAMERASB01_OFFSET 492
> +#define BXT_GP_CAMERASB02_OFFSET 493
> +#define BXT_GP_CAMERASB03_OFFSET 494
> +#define BXT_GP_CAMERASB04_OFFSET 495
> +#define BXT_GP_CAMERASB05_OFFSET 496
> +#define BXT_GP_CAMERASB06_OFFSET 497
> +#define BXT_GP_CAMERASB07_OFFSET 498
> +#define BXT_GP_CAMERASB08_OFFSET 499
> +#define BXT_GP_CAMERASB09_OFFSET 500
> +#define BXT_GP_CAMERASB10_OFFSET 501
> +#define BXT_GP_CAMERASB11_OFFSET 502
> +
> +static struct bxt_gpio_table bxt_gtable[] = {
> + {BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET},
> + {BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET},
> + {BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET},
> + {BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET},
> + {BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET},
> + {BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET},
> + {BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET},
> + {BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET},
> + {BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET},
> + {BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET},
> + {BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET},
> + {BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET},
> + {BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET},
> + {BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET},
> + {BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET},
> + {BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET},
> + {BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET},
> + {BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET},
> + {BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET},
> + {BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET},
> + {BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET},
> + {BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET},
> + {BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET},
> + {BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET},
> + {BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET},
> + {BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET},
> + {BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET},
> + {BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET},
> + {BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET},
> + {BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET},
> + {BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET},
> + {BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET},
> + {BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET},
> + {BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET},
> + {BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET},
> + {BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET},
> + {BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET},
> + {BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET},
> + {BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET},
> + {BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET},
> + {BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET},
> + {BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET},
> + {BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET},
> + {BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET},
> + {BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET},
> + {BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET},
> + {BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET},
> + {BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET},
> + {BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET},
> + {BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET},
> + {BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET},
> + {BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET},
> + {BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET},
> + {BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET},
> + {BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET},
> + {BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET},
> + {BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET},
> + {BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET},
> + {BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET},
> + {BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET},
> + {BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET},
> + {BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET},
> + {BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET},
> + {BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET},
> + {BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET},
> + {BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET},
> + {BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET},
> + {BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET},
> + {BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET},
> + {BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET},
> + {BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET},
> + {BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET},
> + {BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET},
> + {BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET},
> + {BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET},
> + {BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET},
> + {BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET},
> + {BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET},
> + {BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET},
> + {BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET},
> + {BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET},
> + {BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET},
> + {BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET},
> + {BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET},
> + {BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET},
> + {BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET},
> + {BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET},
> + {BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET},
> + {BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET},
> + {BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET},
> + {BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET},
> + {BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET},
> + {BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET},
> + {BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET},
> + {BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET},
> + {BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET},
> + {BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET},
> + {BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET},
> + {BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET},
> + {BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET},
> + {BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET},
> + {BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET},
> + {BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET},
> + {BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET},
> + {BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET},
> + {BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET},
> + {BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET},
> + {BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET},
> + {BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET},
> + {BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET},
> + {BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET},
> + {BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET},
> + {BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET},
> + {BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET},
> + {BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET},
> + {BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET},
> + {BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET},
> + {BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET},
> + {BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET},
> + {BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET},
> + {BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET},
> + {BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET},
> + {BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET},
> + {BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET},
> + {BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET},
> + {BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET},
> + {BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET},
> + {BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET},
> + {BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET},
> + {BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET},
> + {BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET},
> + {BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET},
> + {BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET},
> + {BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET},
> + {BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET},
> + {BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET},
> + {BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET},
> + {BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET},
> + {BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET},
> + {BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET},
> + {BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET},
> + {BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET},
> + {BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET},
> + {BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET},
> + {BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET},
> + {BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET},
> + {BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET},
> + {BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET},
> + {BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET},
> + {BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET},
> + {BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET},
> + {BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET},
> + {BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET},
> + {BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET},
> + {BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET},
> + {BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET},
> + {BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET},
> + {BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET},
> + {BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET},
> + {BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET},
> + {BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET},
> + {BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET},
> + {BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET},
> + {BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET},
> + {BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET},
> + {BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET},
> + {BXT_PWM0_PIN, BXT_PWM0_OFFSET},
> + {BXT_PWM1_PIN, BXT_PWM1_OFFSET},
> + {BXT_PWM2_PIN, BXT_PWM2_OFFSET},
> + {BXT_PWM3_PIN, BXT_PWM3_OFFSET},
> + {BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET},
> + {BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET},
> + {BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET},
> + {BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET},
> + {BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET},
> + {BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET},
> + {BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET},
> + {BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET},
> + {BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET},
> + {BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET},
> + {BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET},
> + {BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET},
> + {BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET},
> + {BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET},
> + {BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET},
> + {BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET},
> + {BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET},
> + {BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET},
> + {BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET},
> + {BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET},
> + {BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET},
> + {BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET},
> + {BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET},
> + {BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET},
> + {BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET},
> + {BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET},
> + {BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET},
> + {BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET},
> + {BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET},
> + {BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET},
> + {BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET},
> + {BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET},
> + {BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET},
> + {BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET},
> + {BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET},
> + {BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET},
Which spec has all these?
Now, I'm also not at all sure we should "whitelist" tons of gpio
references here, especially since most of them are not at all about
display. It's really scary to think of our driver messing with, say,
emmc or camera gpio pins on modeset.
> +};
> +
> static inline enum port intel_dsi_seq_port_to_port(u8 port)
> {
> return port ? PORT_C : PORT_A;
> @@ -774,6 +1403,32 @@ void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
>
> }
>
> +void bxt_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
> +{
> + u16 function = 0, i;
> + int err;
> +
> + for (i = 0; i < ARRAY_SIZE(bxt_gtable); i++)
> + if (bxt_gtable[i].gpio_pin == gpio)
> + function = bxt_gtable[i].offset;
The thing you pass to gpio_set_value is the gpio number. What you call
"function" and "offset" here are (if what you're doing is correct)
simply the gpio number. That's what you should call it.
What you call "gpio" and "gpio_pin" here, then actually isn't the gpio
number, but something else. You should call it something else.
> + if (!function) {
> + DRM_ERROR("GPIO number is not present in the table\n");
> + return;
> + }
> +
> + err = gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
> + if (err) {
> + DRM_ERROR("unable to request GPIO %d\n", function);
> + goto free_gpio;
If you can't request it, you shouldn't free it.
> + }
> +
> + gpio_set_value(function, action);
You might just as well rename action to value, to be in line with
gpiolib parlance.
> +
> +free_gpio:
> + gpio_free(function);
Yes, I said that you need to free the gpio, but I also tried to say that
you are *not* supposed to request/free the gpio every time you need to
set its value. Have a look at what gpio request and free actually
involve. Requesting an output gpio forces the value according to flags,
and you may inadvertently toggle the gpio back and forth more than you
think.
You might get away with lazily requesting the gpio on first use (but
also then setting the initial value according to "action"), and then
freeing them all at driver unload.
---
Also, at least for now, please also post all the patches as a new
thread. The way you're replying to the thread with new patch revisions
will confuse patchwork.
BR,
Jani.
> +}
> +
> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> {
> u8 gpio, action;
> @@ -795,15 +1450,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> goto out;
> }
>
> - if (!IS_VALLEYVIEW(dev_priv)) {
> - DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> - goto out;
> - }
> -
> if (IS_VALLEYVIEW(dev))
> vlv_program_gpio(intel_dsi, gpio, action);
> else if (IS_CHERRYVIEW(dev))
> chv_program_gpio(intel_dsi, gpio, action);
> + else if (IS_BROXTON(dev))
> + bxt_program_gpio(intel_dsi, gpio, action);
> else
> DRM_ERROR("GPIO programming missing for this platform.\n");
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-02-22 14:05 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-19 11:23 [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Deepak M
2016-02-19 11:23 ` [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI Deepak M
2016-02-19 13:25 ` Jani Nikula
2016-02-22 13:25 ` [GPIO PATCH 1/2] " Deepak M
2016-02-22 13:40 ` Jani Nikula
2016-02-19 11:23 ` [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control Deepak M
2016-02-19 13:34 ` Jani Nikula
2016-02-22 13:26 ` [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI Deepak M
2016-02-22 14:04 ` Jani Nikula
2016-02-19 12:14 ` ✓ Fi.CI.BAT: success for series starting with [Generic,GPIO,1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table Patchwork
2016-02-19 13:21 ` [Generic GPIO patch 1/3] " Jani Nikula
2016-02-19 13:31 ` Deepak, M
2016-02-19 13:36 ` Jani Nikula
2016-02-19 13:46 ` [PATCH] " Deepak M
2016-02-19 15:15 ` ✗ Fi.CI.BAT: warning for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev2) Patchwork
2016-02-22 13:47 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/dsi: Added the generic gpio sequence support and gpio table (rev4) Patchwork
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