* [PATCH 0/4] gen9 dmc state harderning
@ 2016-02-18 15:21 Mika Kuoppala
2016-02-18 15:21 ` [PATCH 1/4] drm/i915/gen9: Check for DC state mismatch Mika Kuoppala
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:21 UTC (permalink / raw)
To: intel-gfx
There have been problems on losing state sync between dmc
and driver. I belive the interplay with racy hw access due to
intel_display_power_is_enabled() with overlapping reprogramming of
allowed dc states (DC_STATE_EN) made DMC very confused.
Imre has now get rid of the troublesome intel_display_power_is_enabled().
On my tests, that is a prerequisite for keeping dmc healthy. But as we
can see from CI/bat, it is still not enough. Sometimes the write still
doesn't stick. So here are dcm state tracking patches.
With these on top of Imre's patches, I have been able to make skl/dmc (v1.23)
symptom free on dc state keeping. With the expection that sometimes we still
need to write the dc_state_en twice. The runaway situation of dmc
not obeying the write, stucking the flip and eventually killing the gpu
is gone.
Thanks,
-Mika
Mika Kuoppala (3):
drm/i915/gen9: Verify and enforce dc6 state writes
drm/i915/gen9: Extend dmc debug mask to include cores
drm/i915/gen9: Write dc state debugmask bits only once
Patrik Jakobsson (1):
drm/i915/gen9: Check for DC state mismatch
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 10 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 67 +++++++++++++++++++++++++++------
5 files changed, 65 insertions(+), 16 deletions(-)
--
2.5.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/4] drm/i915/gen9: Check for DC state mismatch
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
@ 2016-02-18 15:21 ` Mika Kuoppala
2016-02-18 15:21 ` [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes Mika Kuoppala
` (4 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:21 UTC (permalink / raw)
To: intel-gfx
From: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
The DMC can incorrectly run off and allow DC states on it's own. We
don't know the root-cause for this yet but this patch makes it more
visible.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6644c2e354c1..9cbcb5d80b3c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -746,6 +746,7 @@ struct intel_csr {
uint32_t mmio_count;
i915_reg_t mmioaddr[8];
uint32_t mmiodata[8];
+ uint32_t dc_state;
};
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 2a7ec3141c8d..b453fccfa25d 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -243,6 +243,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
I915_WRITE(dev_priv->csr.mmioaddr[i],
dev_priv->csr.mmiodata[i]);
}
+
+ dev_priv->csr.dc_state = 0;
}
static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a2e367cf99a2..8b9290fdb3b2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
val & mask, state);
+
+ /* Check if DMC is ignoring our DC state requests */
+ if ((val & mask) != dev_priv->csr.dc_state)
+ DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
+ dev_priv->csr.dc_state, val & mask);
+
val &= ~mask;
val |= state;
I915_WRITE(DC_STATE_EN, val);
POSTING_READ(DC_STATE_EN);
+
+ dev_priv->csr.dc_state = val & mask;
}
void bxt_enable_dc9(struct drm_i915_private *dev_priv)
--
2.5.0
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
2016-02-18 15:21 ` [PATCH 1/4] drm/i915/gen9: Check for DC state mismatch Mika Kuoppala
@ 2016-02-18 15:21 ` Mika Kuoppala
2016-02-18 15:42 ` Imre Deak
2016-02-18 15:58 ` Mika Kuoppala
2016-02-18 15:21 ` [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores Mika Kuoppala
` (3 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
It has been observed that sometimes disabling the dc6 fails
and dc6 state pops back up, brief moment after disabling. This
has to be dmc save/restore timing issue or other bug in the
way dc states are handled.
Try to work around this issue as we don't have firmware fix
yet available. Verify that the value we wrote for the dmc sticks,
and also enforce it by rewriting it, if it didn't.
Testcase: kms_flip/basic-flip-vs-dpms
References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 40 +++++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8b9290fdb3b2..cb91540cfbad 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -470,6 +470,42 @@ static void gen9_set_dc_state_debugmask_memory_up(
}
}
+static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
+ u32 state)
+{
+ int rewrites = 0;
+ int rereads = 0;
+ u32 v;
+
+ I915_WRITE(DC_STATE_EN, state);
+
+ /* It has been observed that disabling the dc6 state sometimes
+ * doesn't stick and dmc keeps returning old value. Make sure
+ * the write really sticks enough times and also force rewrite until
+ * we are confident that state is exactly what we want.
+ */
+ do {
+ v = I915_READ(DC_STATE_EN);
+
+ if (v != state) {
+ I915_WRITE(DC_STATE_EN, state);
+ rewrites++;
+ } else if (rereads++ > 5) {
+ break;
+ }
+
+ } while (rewrites < 100);
+
+ if (v != state)
+ DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
+ state, v);
+
+ /* Most of the times we need one retry, avoid spam */
+ if (rewrites > 1)
+ DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
+ state, rewrites);
+}
+
static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
{
uint32_t val;
@@ -502,8 +538,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
val &= ~mask;
val |= state;
- I915_WRITE(DC_STATE_EN, val);
- POSTING_READ(DC_STATE_EN);
+
+ gen9_write_dc_state(dev_priv, val);
dev_priv->csr.dc_state = val & mask;
}
--
2.5.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
2016-02-18 15:21 ` [PATCH 1/4] drm/i915/gen9: Check for DC state mismatch Mika Kuoppala
2016-02-18 15:21 ` [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes Mika Kuoppala
@ 2016-02-18 15:21 ` Mika Kuoppala
2016-02-18 15:34 ` Imre Deak
2016-02-19 10:26 ` Mika Kuoppala
2016-02-18 15:21 ` [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once Mika Kuoppala
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:21 UTC (permalink / raw)
To: intel-gfx
Cores need to be included into the debug mask. We don't exactly
know what it does but the spec says it must be enabled. So obey.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++++++++------
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870477c1..f76cbf3e5d1e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7568,6 +7568,7 @@ enum skl_disp_power_wells {
#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
#define DC_STATE_DEBUG _MMIO(0x45520)
+#define DC_STATE_DEBUG_MASK_CORES (1<<0)
#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cb91540cfbad..1b490c7e4020 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -456,15 +456,17 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/
}
-static void gen9_set_dc_state_debugmask_memory_up(
- struct drm_i915_private *dev_priv)
+static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ uint32_t val, mask;
+
+ mask = DC_STATE_DEBUG_MASK_MEMORY_UP |
+ DC_STATE_DEBUG_MASK_CORES;
/* The below bit doesn't need to be cleared ever afterwards */
val = I915_READ(DC_STATE_DEBUG);
- if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
- val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
+ if ((val & mask) != mask) {
+ val |= mask;
I915_WRITE(DC_STATE_DEBUG, val);
POSTING_READ(DC_STATE_DEBUG);
}
@@ -525,7 +527,7 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
state = DC_STATE_EN_UPTO_DC5;
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
- gen9_set_dc_state_debugmask_memory_up(dev_priv);
+ gen9_set_dc_state_debugmask(dev_priv);
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
--
2.5.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
` (2 preceding siblings ...)
2016-02-18 15:21 ` [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores Mika Kuoppala
@ 2016-02-18 15:21 ` Mika Kuoppala
2016-02-18 15:46 ` Imre Deak
2016-02-19 11:35 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3) Patchwork
2016-02-19 13:29 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev2) Patchwork
5 siblings, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:21 UTC (permalink / raw)
To: intel-gfx
DMC debugmask bits should stick so no need to write them
everytime dc state is changed.
v2: Write after firmware has been successfully loaded (Ville)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 8 +++++---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index b453fccfa25d..902054efb902 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -220,19 +220,19 @@ static const struct stepping_info *intel_get_stepping_info(struct drm_device *de
* Everytime display comes back from low power state this function is called to
* copy the firmware from internal memory to registers.
*/
-void intel_csr_load_program(struct drm_i915_private *dev_priv)
+bool intel_csr_load_program(struct drm_i915_private *dev_priv)
{
u32 *payload = dev_priv->csr.dmc_payload;
uint32_t i, fw_size;
if (!IS_GEN9(dev_priv)) {
DRM_ERROR("No CSR support available for this platform\n");
- return;
+ return false;
}
if (!dev_priv->csr.dmc_payload) {
DRM_ERROR("Tried to program CSR with empty payload\n");
- return;
+ return false;
}
fw_size = dev_priv->csr.dmc_fw_size;
@@ -245,6 +245,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
}
dev_priv->csr.dc_state = 0;
+
+ return true;
}
static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 285b0570be9c..c208ca630e99 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1225,7 +1225,7 @@ u32 skl_plane_ctl_rotation(unsigned int rotation);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
-void intel_csr_load_program(struct drm_i915_private *);
+bool intel_csr_load_program(struct drm_i915_private *);
void intel_csr_ucode_fini(struct drm_i915_private *);
/* intel_dp.c */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1b490c7e4020..7f0577ca900e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -526,9 +526,6 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
state = DC_STATE_EN_UPTO_DC5;
- if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
- gen9_set_dc_state_debugmask(dev_priv);
-
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
val & mask, state);
@@ -2119,8 +2116,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
skl_init_cdclk(dev_priv);
- if (dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
+ if (dev_priv->csr.dmc_payload && intel_csr_load_program(dev_priv))
+ gen9_set_dc_state_debugmask(dev_priv);
}
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
--
2.5.0
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
2016-02-18 15:21 ` [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores Mika Kuoppala
@ 2016-02-18 15:34 ` Imre Deak
2016-02-18 23:43 ` Runyan, Arthur J
2016-02-19 10:26 ` Mika Kuoppala
1 sibling, 1 reply; 17+ messages in thread
From: Imre Deak @ 2016-02-18 15:34 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Runyan, Arthur J
On to, 2016-02-18 at 17:21 +0200, Mika Kuoppala wrote:
> Cores need to be included into the debug mask. We don't exactly
> know what it does but the spec says it must be enabled. So obey.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++++++++------
> 2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 3774870477c1..f76cbf3e5d1e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7568,6 +7568,7 @@ enum skl_disp_power_wells {
> #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
>
> #define DC_STATE_DEBUG _MMIO(0x45520)
> +#define DC_STATE_DEBUG_MASK_CORES (1<<0)
> #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
>
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using
> this register,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index cb91540cfbad..1b490c7e4020 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -456,15 +456,17 @@ static void assert_can_disable_dc9(struct
> drm_i915_private *dev_priv)
> */
> }
>
> -static void gen9_set_dc_state_debugmask_memory_up(
> - struct drm_i915_private *dev_priv)
> +static void gen9_set_dc_state_debugmask(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t val;
> + uint32_t val, mask;
> +
> + mask = DC_STATE_DEBUG_MASK_MEMORY_UP |
> + DC_STATE_DEBUG_MASK_CORES;
The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT
(looks like a recent addition to work around something), but it doesn't
say it's needed for other platforms. The register description doesn't
make a difference though.
Perhaps Art has more info on this, adding him.
>
> /* The below bit doesn't need to be cleared ever afterwards
> */
> val = I915_READ(DC_STATE_DEBUG);
> - if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
> - val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
> + if ((val & mask) != mask) {
> + val |= mask;
> I915_WRITE(DC_STATE_DEBUG, val);
> POSTING_READ(DC_STATE_DEBUG);
> }
> @@ -525,7 +527,7 @@ static void gen9_set_dc_state(struct
> drm_i915_private *dev_priv, uint32_t state)
> state = DC_STATE_EN_UPTO_DC5;
>
> if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> - gen9_set_dc_state_debugmask_memory_up(dev_priv);
> + gen9_set_dc_state_debugmask(dev_priv);
>
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes
2016-02-18 15:21 ` [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes Mika Kuoppala
@ 2016-02-18 15:42 ` Imre Deak
2016-02-18 15:52 ` Mika Kuoppala
2016-02-18 15:58 ` Mika Kuoppala
1 sibling, 1 reply; 17+ messages in thread
From: Imre Deak @ 2016-02-18 15:42 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Rodrigo Vivi
On to, 2016-02-18 at 17:21 +0200, Mika Kuoppala wrote:
> It has been observed that sometimes disabling the dc6 fails
> and dc6 state pops back up, brief moment after disabling. This
> has to be dmc save/restore timing issue or other bug in the
> way dc states are handled.
>
> Try to work around this issue as we don't have firmware fix
> yet available. Verify that the value we wrote for the dmc sticks,
> and also enforce it by rewriting it, if it didn't.
>
> Testcase: kms_flip/basic-flip-vs-dpms
> References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 40
> +++++++++++++++++++++++++++++++--
> 1 file changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8b9290fdb3b2..cb91540cfbad 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -470,6 +470,42 @@ static void
> gen9_set_dc_state_debugmask_memory_up(
> }
> }
>
> +static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> + u32 state)
> +{
> + int rewrites = 0;
> + int rereads = 0;
> + u32 v;
> +
> + I915_WRITE(DC_STATE_EN, state);
> +
> + /* It has been observed that disabling the dc6 state
> sometimes
> + * doesn't stick and dmc keeps returning old value. Make
> sure
> + * the write really sticks enough times and also force
> rewrite until
> + * we are confident that state is exactly what we want.
> + */
> + do {
> + v = I915_READ(DC_STATE_EN);
> +
> + if (v != state) {
> + I915_WRITE(DC_STATE_EN, state);
> + rewrites++;
Could be rereads = 0; for extra paranoia. Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> + } else if (rereads++ > 5) {
> + break;
> + }
> +
> + } while (rewrites < 100);
> +
> + if (v != state)
> + DRM_ERROR("Writing dc state to 0x%x failed, now
> 0x%x\n",
> + state, v);
> +
> + /* Most of the times we need one retry, avoid spam */
> + if (rewrites > 1)
> + DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
> + state, rewrites);
> +}
> +
> static void gen9_set_dc_state(struct drm_i915_private *dev_priv,
> uint32_t state)
> {
> uint32_t val;
> @@ -502,8 +538,8 @@ static void gen9_set_dc_state(struct
> drm_i915_private *dev_priv, uint32_t state)
>
> val &= ~mask;
> val |= state;
> - I915_WRITE(DC_STATE_EN, val);
> - POSTING_READ(DC_STATE_EN);
> +
> + gen9_write_dc_state(dev_priv, val);
>
> dev_priv->csr.dc_state = val & mask;
> }
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once
2016-02-18 15:21 ` [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once Mika Kuoppala
@ 2016-02-18 15:46 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-18 15:46 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
On to, 2016-02-18 at 17:21 +0200, Mika Kuoppala wrote:
> DMC debugmask bits should stick so no need to write them
> everytime dc state is changed.
>
> v2: Write after firmware has been successfully loaded (Ville)
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 8 +++++---
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-----
> 3 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index b453fccfa25d..902054efb902 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -220,19 +220,19 @@ static const struct stepping_info
> *intel_get_stepping_info(struct drm_device *de
> * Everytime display comes back from low power state this function
> is called to
> * copy the firmware from internal memory to registers.
> */
> -void intel_csr_load_program(struct drm_i915_private *dev_priv)
> +bool intel_csr_load_program(struct drm_i915_private *dev_priv)
> {
> u32 *payload = dev_priv->csr.dmc_payload;
> uint32_t i, fw_size;
>
> if (!IS_GEN9(dev_priv)) {
> DRM_ERROR("No CSR support available for this
> platform\n");
> - return;
> + return false;
> }
>
> if (!dev_priv->csr.dmc_payload) {
> DRM_ERROR("Tried to program CSR with empty
> payload\n");
> - return;
> + return false;
> }
>
> fw_size = dev_priv->csr.dmc_fw_size;
> @@ -245,6 +245,8 @@ void intel_csr_load_program(struct
> drm_i915_private *dev_priv)
> }
>
> dev_priv->csr.dc_state = 0;
> +
> + return true;
> }
>
> static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 285b0570be9c..c208ca630e99 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1225,7 +1225,7 @@ u32 skl_plane_ctl_rotation(unsigned int
> rotation);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> -void intel_csr_load_program(struct drm_i915_private *);
> +bool intel_csr_load_program(struct drm_i915_private *);
> void intel_csr_ucode_fini(struct drm_i915_private *);
>
> /* intel_dp.c */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1b490c7e4020..7f0577ca900e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -526,9 +526,6 @@ static void gen9_set_dc_state(struct
> drm_i915_private *dev_priv, uint32_t state)
> else if (i915.enable_dc == 1 && state >
> DC_STATE_EN_UPTO_DC5)
> state = DC_STATE_EN_UPTO_DC5;
>
> - if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> - gen9_set_dc_state_debugmask(dev_priv);
> -
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
> val & mask, state);
> @@ -2119,8 +2116,8 @@ static void skl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> skl_init_cdclk(dev_priv);
>
> - if (dev_priv->csr.dmc_payload)
> - intel_csr_load_program(dev_priv);
> + if (dev_priv->csr.dmc_payload &&
> intel_csr_load_program(dev_priv))
> + gen9_set_dc_state_debugmask(dev_priv);
> }
>
> static void skl_display_core_uninit(struct drm_i915_private
> *dev_priv)
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes
2016-02-18 15:42 ` Imre Deak
@ 2016-02-18 15:52 ` Mika Kuoppala
0 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:52 UTC (permalink / raw)
To: imre.deak, intel-gfx; +Cc: Rodrigo Vivi
Imre Deak <imre.deak@intel.com> writes:
> On to, 2016-02-18 at 17:21 +0200, Mika Kuoppala wrote:
>> It has been observed that sometimes disabling the dc6 fails
>> and dc6 state pops back up, brief moment after disabling. This
>> has to be dmc save/restore timing issue or other bug in the
>> way dc states are handled.
>>
>> Try to work around this issue as we don't have firmware fix
>> yet available. Verify that the value we wrote for the dmc sticks,
>> and also enforce it by rewriting it, if it didn't.
>>
>> Testcase: kms_flip/basic-flip-vs-dpms
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
>> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 40
>> +++++++++++++++++++++++++++++++--
>> 1 file changed, 38 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index 8b9290fdb3b2..cb91540cfbad 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -470,6 +470,42 @@ static void
>> gen9_set_dc_state_debugmask_memory_up(
>> }
>> }
>>
>> +static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
>> + u32 state)
>> +{
>> + int rewrites = 0;
>> + int rereads = 0;
>> + u32 v;
>> +
>> + I915_WRITE(DC_STATE_EN, state);
>> +
>> + /* It has been observed that disabling the dc6 state
>> sometimes
>> + * doesn't stick and dmc keeps returning old value. Make
>> sure
>> + * the write really sticks enough times and also force
>> rewrite until
>> + * we are confident that state is exactly what we want.
>> + */
>> + do {
>> + v = I915_READ(DC_STATE_EN);
>> +
>> + if (v != state) {
>> + I915_WRITE(DC_STATE_EN, state);
>> + rewrites++;
>
> Could be rereads = 0; for extra paranoia. Either way:
Oh yes, extra paranoia in here is warranted. I will
add that.
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Thanks,
-Mika
>
>> + } else if (rereads++ > 5) {
>> + break;
>> + }
>> +
>> + } while (rewrites < 100);
>> +
>> + if (v != state)
>> + DRM_ERROR("Writing dc state to 0x%x failed, now
>> 0x%x\n",
>> + state, v);
>> +
>> + /* Most of the times we need one retry, avoid spam */
>> + if (rewrites > 1)
>> + DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
>> + state, rewrites);
>> +}
>> +
>> static void gen9_set_dc_state(struct drm_i915_private *dev_priv,
>> uint32_t state)
>> {
>> uint32_t val;
>> @@ -502,8 +538,8 @@ static void gen9_set_dc_state(struct
>> drm_i915_private *dev_priv, uint32_t state)
>>
>> val &= ~mask;
>> val |= state;
>> - I915_WRITE(DC_STATE_EN, val);
>> - POSTING_READ(DC_STATE_EN);
>> +
>> + gen9_write_dc_state(dev_priv, val);
>>
>> dev_priv->csr.dc_state = val & mask;
>> }
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes
2016-02-18 15:21 ` [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes Mika Kuoppala
2016-02-18 15:42 ` Imre Deak
@ 2016-02-18 15:58 ` Mika Kuoppala
1 sibling, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-18 15:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
It has been observed that sometimes disabling the dc6 fails
and dc6 state pops back up, brief moment after disabling. This
has to be dmc save/restore timing issue or other bug in the
way dc states are handled.
Try to work around this issue as we don't have firmware fix
yet available. Verify that the value we wrote for the dmc sticks,
and also enforce it by rewriting it, if it didn't.
v2: Zero rereads on rewrite for extra paranoia (Imre)
Testcase: kms_flip/basic-flip-vs-dpms
References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 41 +++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8b9290fdb3b2..814cf5ac1ef0 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -470,6 +470,43 @@ static void gen9_set_dc_state_debugmask_memory_up(
}
}
+static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
+ u32 state)
+{
+ int rewrites = 0;
+ int rereads = 0;
+ u32 v;
+
+ I915_WRITE(DC_STATE_EN, state);
+
+ /* It has been observed that disabling the dc6 state sometimes
+ * doesn't stick and dmc keeps returning old value. Make sure
+ * the write really sticks enough times and also force rewrite until
+ * we are confident that state is exactly what we want.
+ */
+ do {
+ v = I915_READ(DC_STATE_EN);
+
+ if (v != state) {
+ I915_WRITE(DC_STATE_EN, state);
+ rewrites++;
+ rereads = 0;
+ } else if (rereads++ > 5) {
+ break;
+ }
+
+ } while (rewrites < 100);
+
+ if (v != state)
+ DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
+ state, v);
+
+ /* Most of the times we need one retry, avoid spam */
+ if (rewrites > 1)
+ DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
+ state, rewrites);
+}
+
static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
{
uint32_t val;
@@ -502,8 +539,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
val &= ~mask;
val |= state;
- I915_WRITE(DC_STATE_EN, val);
- POSTING_READ(DC_STATE_EN);
+
+ gen9_write_dc_state(dev_priv, val);
dev_priv->csr.dc_state = val & mask;
}
--
2.5.0
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
2016-02-18 15:34 ` Imre Deak
@ 2016-02-18 23:43 ` Runyan, Arthur J
0 siblings, 0 replies; 17+ messages in thread
From: Runyan, Arthur J @ 2016-02-18 23:43 UTC (permalink / raw)
To: Deak, Imre, Mika Kuoppala, intel-gfx
>-----Original Message-----
>From: Deak, Imre
...
>The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT
>(looks like a recent addition to work around something), but it doesn't
>say it's needed for other platforms. The register description doesn't
>make a difference though.
>
>Perhaps Art has more info on this, adding him.
>
Only BXT needs it programmed to 1b at the moment. Other products should keep the default.
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
2016-02-18 15:21 ` [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores Mika Kuoppala
2016-02-18 15:34 ` Imre Deak
@ 2016-02-19 10:26 ` Mika Kuoppala
2016-02-19 10:34 ` Imre Deak
1 sibling, 1 reply; 17+ messages in thread
From: Mika Kuoppala @ 2016-02-19 10:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Runyan, Arthur J
Cores need to be included into the debug mask. We don't exactly
know what it does but the spec says it must be enabled. So obey.
v2: Cores should be only set for BXT (Imre, Art)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 16 ++++++++++------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870477c1..f76cbf3e5d1e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7568,6 +7568,7 @@ enum skl_disp_power_wells {
#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
#define DC_STATE_DEBUG _MMIO(0x45520)
+#define DC_STATE_DEBUG_MASK_CORES (1<<0)
#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 814cf5ac1ef0..089701b73112 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -456,15 +456,19 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/
}
-static void gen9_set_dc_state_debugmask_memory_up(
- struct drm_i915_private *dev_priv)
+static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
- uint32_t val;
+ uint32_t val, mask;
+
+ mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
+
+ if (IS_BROXTON(dev_priv))
+ mask |= DC_STATE_DEBUG_MASK_CORES;
/* The below bit doesn't need to be cleared ever afterwards */
val = I915_READ(DC_STATE_DEBUG);
- if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
- val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
+ if ((val & mask) != mask) {
+ val |= mask;
I915_WRITE(DC_STATE_DEBUG, val);
POSTING_READ(DC_STATE_DEBUG);
}
@@ -526,7 +530,7 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
state = DC_STATE_EN_UPTO_DC5;
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
- gen9_set_dc_state_debugmask_memory_up(dev_priv);
+ gen9_set_dc_state_debugmask(dev_priv);
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
--
2.5.0
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
2016-02-19 10:26 ` Mika Kuoppala
@ 2016-02-19 10:34 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-19 10:34 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Runyan, Arthur J
On Fri, 2016-02-19 at 12:26 +0200, Mika Kuoppala wrote:
> Cores need to be included into the debug mask. We don't exactly
> know what it does but the spec says it must be enabled. So obey.
>
> v2: Cores should be only set for BXT (Imre, Art)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 16 ++++++++++------
> 2 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 3774870477c1..f76cbf3e5d1e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7568,6 +7568,7 @@ enum skl_disp_power_wells {
> #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
>
> #define DC_STATE_DEBUG _MMIO(0x45520)
> +#define DC_STATE_DEBUG_MASK_CORES (1<<0)
> #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
>
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using
> this register,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 814cf5ac1ef0..089701b73112 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -456,15 +456,19 @@ static void assert_can_disable_dc9(struct
> drm_i915_private *dev_priv)
> */
> }
>
> -static void gen9_set_dc_state_debugmask_memory_up(
> - struct drm_i915_private *dev_priv)
> +static void gen9_set_dc_state_debugmask(struct drm_i915_private
> *dev_priv)
> {
> - uint32_t val;
> + uint32_t val, mask;
> +
> + mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> +
> + if (IS_BROXTON(dev_priv))
> + mask |= DC_STATE_DEBUG_MASK_CORES;
>
> /* The below bit doesn't need to be cleared ever afterwards
> */
> val = I915_READ(DC_STATE_DEBUG);
> - if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
> - val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
> + if ((val & mask) != mask) {
> + val |= mask;
> I915_WRITE(DC_STATE_DEBUG, val);
> POSTING_READ(DC_STATE_DEBUG);
> }
> @@ -526,7 +530,7 @@ static void gen9_set_dc_state(struct
> drm_i915_private *dev_priv, uint32_t state)
> state = DC_STATE_EN_UPTO_DC5;
>
> if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> - gen9_set_dc_state_debugmask_memory_up(dev_priv);
> + gen9_set_dc_state_debugmask(dev_priv);
>
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
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^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3)
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
` (3 preceding siblings ...)
2016-02-18 15:21 ` [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once Mika Kuoppala
@ 2016-02-19 11:35 ` Patchwork
2016-02-22 15:13 ` Imre Deak
2016-02-19 13:29 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev2) Patchwork
5 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2016-02-19 11:35 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Summary ==
Series 3587v3 gen9 dmc state harderning
http://patchwork.freedesktop.org/api/1.0/series/3587/revisions/3/mbox/
Test gem_ctx_param_basic:
Subgroup basic-default:
incomplete -> PASS (snb-x220t)
Subgroup invalid-ctx-get:
incomplete -> PASS (snb-x220t)
Subgroup non-root-set-no-zeromap:
incomplete -> PASS (snb-x220t)
Subgroup root-set:
incomplete -> PASS (snb-x220t)
Subgroup root-set-no-zeromap-disabled:
incomplete -> PASS (snb-x220t)
Subgroup root-set-no-zeromap-enabled:
incomplete -> PASS (snb-x220t)
Test gem_exec_basic:
Subgroup basic-blt:
incomplete -> PASS (snb-x220t)
Test gem_flink_basic:
Subgroup bad-flink:
incomplete -> PASS (snb-x220t)
Test gem_linear_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_mmap:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Subgroup basic-small-bo:
incomplete -> PASS (snb-x220t)
Test gem_mmap_gtt:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Subgroup basic-copy:
incomplete -> PASS (snb-x220t)
Subgroup basic-read-no-prefault:
incomplete -> PASS (snb-x220t)
Subgroup basic-read-write-distinct:
incomplete -> PASS (snb-x220t)
Subgroup basic-write-cpu-read-gtt:
incomplete -> PASS (snb-x220t)
Subgroup basic-write-read-distinct:
incomplete -> PASS (snb-x220t)
Test gem_pread:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_render_linear_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_render_tiled_blits:
Subgroup basic:
incomplete -> PASS (snb-x220t)
Test gem_ringfill:
Subgroup basic-default:
incomplete -> PASS (snb-x220t)
Subgroup basic-default-bomb:
incomplete -> PASS (ivb-t430s)
Subgroup basic-default-forked:
incomplete -> PASS (snb-x220t)
Subgroup basic-default-hang:
incomplete -> PASS (snb-x220t)
Test gem_storedw_loop:
Subgroup basic-bsd1:
incomplete -> SKIP (snb-x220t)
Subgroup basic-render:
incomplete -> PASS (snb-x220t)
Subgroup basic-vebox:
incomplete -> SKIP (snb-x220t)
Test gem_sync:
Subgroup basic-blt:
incomplete -> PASS (snb-x220t)
Test gem_tiled_pread_basic:
incomplete -> PASS (snb-x220t)
Test kms_addfb_basic:
Subgroup addfb25-modifier-no-flag:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-0:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-1024:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-128:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-256:
incomplete -> PASS (snb-x220t)
Subgroup bad-pitch-999:
incomplete -> PASS (snb-x220t)
Subgroup basic-x-tiled:
incomplete -> PASS (snb-x220t)
Subgroup framebuffer-vs-set-tiling:
incomplete -> PASS (snb-x220t)
Subgroup no-handle:
incomplete -> PASS (snb-x220t)
Subgroup size-max:
incomplete -> PASS (snb-x220t)
Subgroup too-wide:
incomplete -> PASS (snb-x220t)
Subgroup unused-handle:
incomplete -> PASS (snb-x220t)
Subgroup unused-modifier:
incomplete -> PASS (snb-x220t)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
incomplete -> PASS (snb-x220t)
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (snb-x220t)
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip -> PASS (snb-x220t)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-c-frame-sequence:
incomplete -> SKIP (snb-x220t)
Subgroup read-crc-pipe-a-frame-sequence:
incomplete -> PASS (snb-x220t)
Subgroup read-crc-pipe-b:
incomplete -> PASS (snb-x220t)
Subgroup read-crc-pipe-c-frame-sequence:
incomplete -> SKIP (snb-x220t)
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (snb-x220t)
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-pci-d3-state:
incomplete -> FAIL (snb-x220t)
pass -> DMESG-WARN (byt-nuc)
Subgroup basic-rte:
dmesg-warn -> PASS (byt-nuc) UNSTABLE
Test prime_self_import:
Subgroup basic-with_two_bos:
incomplete -> PASS (snb-x220t)
bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip:14
bsw-nuc-2 total:167 pass:135 dwarn:2 dfail:0 fail:0 skip:30
byt-nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip:25
ivb-t430s total:167 pass:151 dwarn:0 dfail:0 fail:1 skip:15
skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
skl-i7k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
snb-x220t total:167 pass:143 dwarn:0 dfail:0 fail:3 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1442/
e4599905334de9349501a383afb8503a1dde5728 drm-intel-nightly: 2016y-02m-18d-17h-13m-22s UTC integration manifest
3c04c11de136a3e57ef1ad8a8835e64d35111c4f drm/i915/gen9: Write dc state debugmask bits only once
b3f3a7f737626a65ab9c776a0ae761b89bda082e drm/i915/gen9: Extend dmc debug mask to include cores
8d96d19adb27b89fc9b9433624d0075b293ce154 drm/i915/gen9: Verify and enforce dc6 state writes
91da02aa4b115f1778d2d9eccb24f48082ac4cbf drm/i915/gen9: Check for DC state mismatch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev2)
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
` (4 preceding siblings ...)
2016-02-19 11:35 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3) Patchwork
@ 2016-02-19 13:29 ` Patchwork
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-02-19 13:29 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Summary ==
Series 3587v2 gen9 dmc state harderning
http://patchwork.freedesktop.org/api/1.0/series/3587/revisions/2/mbox/
Test gem_cs_prefetch:
Subgroup basic-default:
incomplete -> PASS (snb-x220t)
Test kms_flip:
Subgroup basic-plain-flip:
pass -> INCOMPLETE (snb-x220t)
Test kms_force_connector_basic:
Subgroup force-load-detect:
dmesg-fail -> FAIL (snb-dellxps)
dmesg-fail -> FAIL (ivb-t430s)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (skl-i5k-2)
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (hsw-gt2)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-pci-d3-state:
fail -> PASS (bdw-nuci7)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> FAIL (hsw-gt2)
bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip:14
bsw-nuc-2 total:167 pass:136 dwarn:1 dfail:0 fail:0 skip:30
byt-nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip:25
hsw-gt2 total:167 pass:155 dwarn:0 dfail:1 fail:1 skip:10
ivb-t430s total:167 pass:152 dwarn:0 dfail:0 fail:1 skip:14
skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
snb-dellxps total:167 pass:144 dwarn:0 dfail:0 fail:1 skip:22
snb-x220t total:118 pass:102 dwarn:0 dfail:1 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1437/
e6add0f0dcbc2f8a1fa31980d1a784b7e7cc1a00 drm-intel-nightly: 2016y-02m-18d-14h-04m-21s UTC integration manifest
b02e522bc28143aab796d55cceff269853f91de2 drm/i915/gen9: Write dc state debugmask bits only once
10998c79375497b194aecc5db7aea49a0b7f43a2 drm/i915/gen9: Extend dmc debug mask to include cores
51debeda8ac37445d657bc06b07cb8432d4e669a drm/i915/gen9: Verify and enforce dc6 state writes
df7ed24b340c36d7c524627ca229cea9f71f078f drm/i915/gen9: Check for DC state mismatch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3)
2016-02-19 11:35 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3) Patchwork
@ 2016-02-22 15:13 ` Imre Deak
2016-02-22 15:26 ` Imre Deak
0 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2016-02-22 15:13 UTC (permalink / raw)
To: intel-gfx, Mika Kuoppala
On pe, 2016-02-19 at 11:35 +0000, Patchwork wrote:
> == Summary ==
>
> Series 3587v3 gen9 dmc state harderning
> http://patchwork.freedesktop.org/api/1.0/series/3587/revisions/3/mbox
> /
>
> Test gem_ctx_param_basic:
> Subgroup basic-default:
> incomplete -> PASS (snb-x220t)
> Subgroup invalid-ctx-get:
> incomplete -> PASS (snb-x220t)
> Subgroup non-root-set-no-zeromap:
> incomplete -> PASS (snb-x220t)
> Subgroup root-set:
> incomplete -> PASS (snb-x220t)
> Subgroup root-set-no-zeromap-disabled:
> incomplete -> PASS (snb-x220t)
> Subgroup root-set-no-zeromap-enabled:
> incomplete -> PASS (snb-x220t)
> Test gem_exec_basic:
> Subgroup basic-blt:
> incomplete -> PASS (snb-x220t)
> Test gem_flink_basic:
> Subgroup bad-flink:
> incomplete -> PASS (snb-x220t)
> Test gem_linear_blits:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Test gem_mmap:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-small-bo:
> incomplete -> PASS (snb-x220t)
> Test gem_mmap_gtt:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-copy:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-read-no-prefault:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-read-write-distinct:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-write-cpu-read-gtt:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-write-read-distinct:
> incomplete -> PASS (snb-x220t)
> Test gem_pread:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Test gem_render_linear_blits:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Test gem_render_tiled_blits:
> Subgroup basic:
> incomplete -> PASS (snb-x220t)
> Test gem_ringfill:
> Subgroup basic-default:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-default-bomb:
> incomplete -> PASS (ivb-t430s)
> Subgroup basic-default-forked:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-default-hang:
> incomplete -> PASS (snb-x220t)
> Test gem_storedw_loop:
> Subgroup basic-bsd1:
> incomplete -> SKIP (snb-x220t)
Unrelated since none of the patches affect SNB.
> Subgroup basic-render:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-vebox:
> incomplete -> SKIP (snb-x220t)
Similarly, unrelated.
> Test gem_sync:
> Subgroup basic-blt:
> incomplete -> PASS (snb-x220t)
> Test gem_tiled_pread_basic:
> incomplete -> PASS (snb-x220t)
> Test kms_addfb_basic:
> Subgroup addfb25-modifier-no-flag:
> incomplete -> PASS (snb-x220t)
> Subgroup bad-pitch-0:
> incomplete -> PASS (snb-x220t)
> Subgroup bad-pitch-1024:
> incomplete -> PASS (snb-x220t)
> Subgroup bad-pitch-128:
> incomplete -> PASS (snb-x220t)
> Subgroup bad-pitch-256:
> incomplete -> PASS (snb-x220t)
> Subgroup bad-pitch-999:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-x-tiled:
> incomplete -> PASS (snb-x220t)
> Subgroup framebuffer-vs-set-tiling:
> incomplete -> PASS (snb-x220t)
> Subgroup no-handle:
> incomplete -> PASS (snb-x220t)
> Subgroup size-max:
> incomplete -> PASS (snb-x220t)
> Subgroup too-wide:
> incomplete -> PASS (snb-x220t)
> Subgroup unused-handle:
> incomplete -> PASS (snb-x220t)
> Subgroup unused-modifier:
> incomplete -> PASS (snb-x220t)
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> incomplete -> PASS (snb-x220t)
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (snb-x220t)
Unrelated as above.
> Test kms_force_connector_basic:
> Subgroup prune-stale-modes:
> skip -> PASS (snb-x220t)
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-c-frame-sequence:
> incomplete -> SKIP (snb-x220t)
> Subgroup read-crc-pipe-a-frame-sequence:
> incomplete -> PASS (snb-x220t)
> Subgroup read-crc-pipe-b:
> incomplete -> PASS (snb-x220t)
> Subgroup read-crc-pipe-c-frame-sequence:
> incomplete -> SKIP (snb-x220t)
Unrelated as above.
> Subgroup suspend-read-crc-pipe-a:
> incomplete -> PASS (snb-x220t)
> dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
> Subgroup suspend-read-crc-pipe-b:
> pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Unrelated online-CPU lock dependency problem, to be fixed by Joonas'
patch.
> Subgroup suspend-read-crc-pipe-c:
> dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
> pass -> DMESG-WARN (bsw-nuc-2)
Unrelated platform.
> pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Online-CPU lock dependency problem.
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> incomplete -> FAIL (snb-x220t)
> pass -> DMESG-WARN (byt-nuc)
Both are unrelated platforms.
> Subgroup basic-rte:
> dmesg-warn -> PASS (byt-nuc) UNSTABLE
> Test prime_self_import:
> Subgroup basic-with_two_bos:
> incomplete -> PASS (snb-x220t)
>
> bdw-
> nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:1
> 1
> bdw-
> ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip:1
> 4
> bsw-nuc-
> 2 total:167 pass:135 dwarn:2 dfail:0 fail:0 skip:30
> byt-
> nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip:2
> 5
> ivb-
> t430s total:167 pass:151 dwarn:0 dfail:0 fail:1 skip:1
> 5
> skl-i5k-
> 2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
> skl-i7k-
> 2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
> snb-
> x220t total:167 pass:143 dwarn:0 dfail:0 fail:3 skip:2
> 1
>
> Results at /archive/results/CI_IGT_test/Patchwork_1442/
>
> e4599905334de9349501a383afb8503a1dde5728 drm-intel-nightly: 2016y-
> 02m-18d-17h-13m-22s UTC integration manifest
> 3c04c11de136a3e57ef1ad8a8835e64d35111c4f drm/i915/gen9: Write dc
> state debugmask bits only once
> b3f3a7f737626a65ab9c776a0ae761b89bda082e drm/i915/gen9: Extend dmc
> debug mask to include cores
> 8d96d19adb27b89fc9b9433624d0075b293ce154 drm/i915/gen9: Verify and
> enforce dc6 state writes
> 91da02aa4b115f1778d2d9eccb24f48082ac4cbf drm/i915/gen9: Check for DC
> state mismatch
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3)
2016-02-22 15:13 ` Imre Deak
@ 2016-02-22 15:26 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-22 15:26 UTC (permalink / raw)
To: intel-gfx, Mika Kuoppala, Patrik Jakobsson; +Cc: Jani Nikula
On ma, 2016-02-22 at 17:13 +0200, Imre Deak wrote:
> On pe, 2016-02-19 at 11:35 +0000, Patchwork wrote:
> > == Summary ==
> >
> > Series 3587v3 gen9 dmc state harderning
> > http://patchwork.freedesktop.org/api/1.0/series/3587/revisions/3/mbox/
Thanks for the patches, I pushed them to -dinq.
--Imre
> > Test gem_ctx_param_basic:
> > Subgroup basic-default:
> > incomplete -> PASS (snb-x220t)
> > Subgroup invalid-ctx-get:
> > incomplete -> PASS (snb-x220t)
> > Subgroup non-root-set-no-zeromap:
> > incomplete -> PASS (snb-x220t)
> > Subgroup root-set:
> > incomplete -> PASS (snb-x220t)
> > Subgroup root-set-no-zeromap-disabled:
> > incomplete -> PASS (snb-x220t)
> > Subgroup root-set-no-zeromap-enabled:
> > incomplete -> PASS (snb-x220t)
> > Test gem_exec_basic:
> > Subgroup basic-blt:
> > incomplete -> PASS (snb-x220t)
> > Test gem_flink_basic:
> > Subgroup bad-flink:
> > incomplete -> PASS (snb-x220t)
> > Test gem_linear_blits:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Test gem_mmap:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-small-bo:
> > incomplete -> PASS (snb-x220t)
> > Test gem_mmap_gtt:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-copy:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-read-no-prefault:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-read-write-distinct:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-write-cpu-read-gtt:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-write-read-distinct:
> > incomplete -> PASS (snb-x220t)
> > Test gem_pread:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Test gem_render_linear_blits:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Test gem_render_tiled_blits:
> > Subgroup basic:
> > incomplete -> PASS (snb-x220t)
> > Test gem_ringfill:
> > Subgroup basic-default:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-default-bomb:
> > incomplete -> PASS (ivb-t430s)
> > Subgroup basic-default-forked:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-default-hang:
> > incomplete -> PASS (snb-x220t)
> > Test gem_storedw_loop:
> > Subgroup basic-bsd1:
> > incomplete -> SKIP (snb-x220t)
>
> Unrelated since none of the patches affect SNB.
>
> > Subgroup basic-render:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-vebox:
> > incomplete -> SKIP (snb-x220t)
>
> Similarly, unrelated.
>
> > Test gem_sync:
> > Subgroup basic-blt:
> > incomplete -> PASS (snb-x220t)
> > Test gem_tiled_pread_basic:
> > incomplete -> PASS (snb-x220t)
> > Test kms_addfb_basic:
> > Subgroup addfb25-modifier-no-flag:
> > incomplete -> PASS (snb-x220t)
> > Subgroup bad-pitch-0:
> > incomplete -> PASS (snb-x220t)
> > Subgroup bad-pitch-1024:
> > incomplete -> PASS (snb-x220t)
> > Subgroup bad-pitch-128:
> > incomplete -> PASS (snb-x220t)
> > Subgroup bad-pitch-256:
> > incomplete -> PASS (snb-x220t)
> > Subgroup bad-pitch-999:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-x-tiled:
> > incomplete -> PASS (snb-x220t)
> > Subgroup framebuffer-vs-set-tiling:
> > incomplete -> PASS (snb-x220t)
> > Subgroup no-handle:
> > incomplete -> PASS (snb-x220t)
> > Subgroup size-max:
> > incomplete -> PASS (snb-x220t)
> > Subgroup too-wide:
> > incomplete -> PASS (snb-x220t)
> > Subgroup unused-handle:
> > incomplete -> PASS (snb-x220t)
> > Subgroup unused-modifier:
> > incomplete -> PASS (snb-x220t)
> > Test kms_flip:
> > Subgroup basic-flip-vs-dpms:
> > incomplete -> PASS (snb-x220t)
> > Subgroup basic-flip-vs-wf_vblank:
> > pass -> FAIL (snb-x220t)
>
> Unrelated as above.
>
> > Test kms_force_connector_basic:
> > Subgroup prune-stale-modes:
> > skip -> PASS (snb-x220t)
> > Test kms_pipe_crc_basic:
> > Subgroup nonblocking-crc-pipe-c-frame-sequence:
> > incomplete -> SKIP (snb-x220t)
> > Subgroup read-crc-pipe-a-frame-sequence:
> > incomplete -> PASS (snb-x220t)
> > Subgroup read-crc-pipe-b:
> > incomplete -> PASS (snb-x220t)
> > Subgroup read-crc-pipe-c-frame-sequence:
> > incomplete -> SKIP (snb-x220t)
>
> Unrelated as above.
>
> > Subgroup suspend-read-crc-pipe-a:
> > incomplete -> PASS (snb-x220t)
> > dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
> > Subgroup suspend-read-crc-pipe-b:
> > pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
>
> Unrelated online-CPU lock dependency problem, to be fixed by Joonas'
> patch.
>
> > Subgroup suspend-read-crc-pipe-c:
> > dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
> > pass -> DMESG-WARN (bsw-nuc-2)
>
> Unrelated platform.
>
> > pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
>
> Online-CPU lock dependency problem.
>
> > Test pm_rpm:
> > Subgroup basic-pci-d3-state:
> > incomplete -> FAIL (snb-x220t)
> > pass -> DMESG-WARN (byt-nuc)
>
> Both are unrelated platforms.
>
> > Subgroup basic-rte:
> > dmesg-warn -> PASS (byt-nuc) UNSTABLE
> > Test prime_self_import:
> > Subgroup basic-with_two_bos:
> > incomplete -> PASS (snb-x220t)
> >
> > bdw-
> > nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip
> > :1
> > 1
> > bdw-
> > ultra total:167 pass:153 dwarn:0 dfail:0 fail:0 skip
> > :1
> > 4
> > bsw-nuc-
> > 2 total:167 pass:135 dwarn:2 dfail:0 fail:0 skip:30
> > byt-
> > nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip
> > :2
> > 5
> > ivb-
> > t430s total:167 pass:151 dwarn:0 dfail:0 fail:1 skip
> > :1
> > 5
> > skl-i5k-
> > 2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
> > skl-i7k-
> > 2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
> > snb-
> > x220t total:167 pass:143 dwarn:0 dfail:0 fail:3 skip
> > :2
> > 1
> >
> > Results at /archive/results/CI_IGT_test/Patchwork_1442/
> >
> > e4599905334de9349501a383afb8503a1dde5728 drm-intel-nightly: 2016y-
> > 02m-18d-17h-13m-22s UTC integration manifest
> > 3c04c11de136a3e57ef1ad8a8835e64d35111c4f drm/i915/gen9: Write dc
> > state debugmask bits only once
> > b3f3a7f737626a65ab9c776a0ae761b89bda082e drm/i915/gen9: Extend dmc
> > debug mask to include cores
> > 8d96d19adb27b89fc9b9433624d0075b293ce154 drm/i915/gen9: Verify and
> > enforce dc6 state writes
> > 91da02aa4b115f1778d2d9eccb24f48082ac4cbf drm/i915/gen9: Check for
> > DC
> > state mismatch
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2016-02-22 15:26 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-18 15:21 [PATCH 0/4] gen9 dmc state harderning Mika Kuoppala
2016-02-18 15:21 ` [PATCH 1/4] drm/i915/gen9: Check for DC state mismatch Mika Kuoppala
2016-02-18 15:21 ` [PATCH 2/4] drm/i915/gen9: Verify and enforce dc6 state writes Mika Kuoppala
2016-02-18 15:42 ` Imre Deak
2016-02-18 15:52 ` Mika Kuoppala
2016-02-18 15:58 ` Mika Kuoppala
2016-02-18 15:21 ` [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores Mika Kuoppala
2016-02-18 15:34 ` Imre Deak
2016-02-18 23:43 ` Runyan, Arthur J
2016-02-19 10:26 ` Mika Kuoppala
2016-02-19 10:34 ` Imre Deak
2016-02-18 15:21 ` [PATCH 4/4] drm/i915/gen9: Write dc state debugmask bits only once Mika Kuoppala
2016-02-18 15:46 ` Imre Deak
2016-02-19 11:35 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev3) Patchwork
2016-02-22 15:13 ` Imre Deak
2016-02-22 15:26 ` Imre Deak
2016-02-19 13:29 ` ✗ Fi.CI.BAT: failure for gen9 dmc state harderning (rev2) Patchwork
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