[Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Alex Bennée]

Hi,

Some of these patches have been posted before and previous patches
have already been accepted upstream so I'm tagging this as a new RFC
series.

This is a series of tests built around kvm-unit-tests but built with
the express purpose of stressing the TCG, in particular MTTCG builds.

Changes from previous appearances:

 * Separated locking and barrier tests
 * Included Drew's IPI patches (used in tcg-test)
 * New TCG chaining test

The new barrier tests really only fails when running on MTTCG builds on
a weak backend. Many thanks to Will Deacon for helping me get a
working test case at the last Connect.

I'm mainly posting these for reference for others testing MTTCG as
I've still got to check I've addressed any outstanding review
comments. However there has been enough code churn some of the
comments may no longer be relevant.

The TCG tests are also useful as benchmarks for comparing the cost of
having chained basic blocks versus exiting the loop every time. The
pathological case is the computed jumps test as all the addresses are
within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
full look up each time.

Alex Bennée (8):
  config/config-arm-common: build-up tests-common target
  lib: add isaac prng library from CCAN
  arm/run: set indentation defaults for emacs
  arm/run: allow aarch64 to start arm binaries
  arm/tlbflush-test: Add TLB torture test
  arm/locking-tests: add comprehensive locking test
  arm/barrier-litmus-tests: add some litmus tests
  arm/tcg-test: some basic TCG exercising tests

Andrew Jones (3):
  arm/arm64: irq enable/disable
  arm/arm64: Add initial gic support
  arm/arm64: Add IPI test

 arm/barrier-litmus-test.c    | 258 ++++++++++++++++++++++++++++++++++++
 arm/ipi-test.c               |  58 +++++++++
 arm/locking-test.c           | 302 +++++++++++++++++++++++++++++++++++++++++++
 arm/run                      |  11 +-
 arm/tcg-test-asm.S           | 170 ++++++++++++++++++++++++
 arm/tcg-test.c               | 248 +++++++++++++++++++++++++++++++++++
 arm/tlbflush-test.c          | 194 +++++++++++++++++++++++++++
 arm/unittests.cfg            | 170 ++++++++++++++++++++++++
 config/config-arm-common.mak |  16 ++-
 lib/arm/asm/barrier.h        |  63 ++++++++-
 lib/arm/asm/gic.h            | 122 +++++++++++++++++
 lib/arm/asm/processor.h      |  10 ++
 lib/arm/io.c                 |  31 +++++
 lib/arm64/asm/barrier.h      |  50 +++++++
 lib/arm64/asm/gic.h          |   1 +
 lib/arm64/asm/processor.h    |  10 ++
 lib/prng.c                   | 162 +++++++++++++++++++++++
 lib/prng.h                   |  82 ++++++++++++
 18 files changed, 1953 insertions(+), 5 deletions(-)
 create mode 100644 arm/barrier-litmus-test.c
 create mode 100644 arm/ipi-test.c
 create mode 100644 arm/locking-test.c
 create mode 100644 arm/tcg-test-asm.S
 create mode 100644 arm/tcg-test.c
 create mode 100644 arm/tlbflush-test.c
 create mode 100644 lib/arm/asm/gic.h
 create mode 100644 lib/arm64/asm/gic.h
 create mode 100644 lib/prng.c
 create mode 100644 lib/prng.h

-- 
2.7.1

[Qemu-devel] [RFC 01/11] config/config-arm-common: build-up tests-common target

[Alex Bennée]

This is a source of needless conflicts when adding new tests and
re-basing. Let's just build up the lists of tests by hand.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 config/config-arm-common.mak | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index 698555d..e037507 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -9,9 +9,8 @@ ifeq ($(LOADADDR),)
 	LOADADDR = 0x40000000
 endif
 
-tests-common = \
-	$(TEST_DIR)/selftest.flat \
-	$(TEST_DIR)/spinlock-test.flat
+tests-common = $(TEST_DIR)/selftest.flat
+tests-common += $(TEST_DIR)/spinlock-test.flat
 
 all: test_cases
 
-- 
2.7.1

[Qemu-devel] [RFC 02/11] arm/arm64: irq enable/disable

[Alex Bennée]

From: Andrew Jones <drjones@redhat.com>

Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 lib/arm/asm/processor.h   | 10 ++++++++++
 lib/arm64/asm/processor.h | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index f25e7ee..a3a4e0b 100644
--- a/lib/arm/asm/processor.h
+++ b/lib/arm/asm/processor.h
@@ -33,6 +33,16 @@ static inline unsigned long current_cpsr(void)
 
 #define current_mode() (current_cpsr() & MODE_MASK)
 
+static inline void local_irq_enable(void)
+{
+	asm volatile("cpsie i" : : : "memory", "cc");
+}
+
+static inline void local_irq_disable(void)
+{
+	asm volatile("cpsid i" : : : "memory", "cc");
+}
+
 static inline unsigned int get_mpidr(void)
 {
 	unsigned int mpidr;
diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h
index 84d5c7c..18fa2a2 100644
--- a/lib/arm64/asm/processor.h
+++ b/lib/arm64/asm/processor.h
@@ -66,6 +66,16 @@ static inline unsigned long current_level(void)
 	return el & 0xc;
 }
 
+static inline void local_irq_enable(void)
+{
+	asm volatile("msr daifclr, #2" : : : "memory");
+}
+
+static inline void local_irq_disable(void)
+{
+	asm volatile("msr daifset, #2" : : : "memory");
+}
+
 #define DEFINE_GET_SYSREG32(reg)				\
 static inline unsigned int get_##reg(void)			\
 {								\
-- 
2.7.1

[Qemu-devel] [RFC 03/11] arm/arm64: Add initial gic support

[Alex Bennée]

From: Andrew Jones <drjones@redhat.com>

Add some gic(v2) support. This just adds enough support for an IPI
test. It's really just a starting point, and the general functions
(inlines in gic.h) may need some changes as more support is added.

Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 lib/arm/asm/gic.h   | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/arm/io.c        |  31 +++++++++++++
 lib/arm64/asm/gic.h |   1 +
 3 files changed, 154 insertions(+)
 create mode 100644 lib/arm/asm/gic.h
 create mode 100644 lib/arm64/asm/gic.h

diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
new file mode 100644
index 0000000..6f27c91
--- /dev/null
+++ b/lib/arm/asm/gic.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2015, Red Hat Inc, Andrew Jones <drjones@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ *
+ * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h
+ */
+#ifndef _ASMARM_GIC_H_
+#define _ASMARM_GIC_H_
+
+#define GIC_CPU_CTRL			0x00
+#define GIC_CPU_PRIMASK			0x04
+#define GIC_CPU_BINPOINT		0x08
+#define GIC_CPU_INTACK			0x0c
+#define GIC_CPU_EOI			0x10
+#define GIC_CPU_RUNNINGPRI		0x14
+#define GIC_CPU_HIGHPRI			0x18
+#define GIC_CPU_ALIAS_BINPOINT		0x1c
+#define GIC_CPU_ACTIVEPRIO		0xd0
+#define GIC_CPU_IDENT			0xfc
+
+#define GICC_ENABLE			0x1
+#define GICC_INT_PRI_THRESHOLD		0xf0
+#define GICC_IAR_INT_ID_MASK		0x3ff
+#define GICC_INT_SPURIOUS		1023
+#define GICC_DIS_BYPASS_MASK		0x1e0
+
+#define GIC_DIST_CTRL			0x000
+#define GIC_DIST_CTR			0x004
+#define GIC_DIST_IGROUP			0x080
+#define GIC_DIST_ENABLE_SET		0x100
+#define GIC_DIST_ENABLE_CLEAR		0x180
+#define GIC_DIST_PENDING_SET		0x200
+#define GIC_DIST_PENDING_CLEAR		0x280
+#define GIC_DIST_ACTIVE_SET		0x300
+#define GIC_DIST_ACTIVE_CLEAR		0x380
+#define GIC_DIST_PRI			0x400
+#define GIC_DIST_TARGET			0x800
+#define GIC_DIST_CONFIG			0xc00
+#define GIC_DIST_SOFTINT		0xf00
+#define GIC_DIST_SGI_PENDING_CLEAR	0xf10
+#define GIC_DIST_SGI_PENDING_SET	0xf20
+
+#define GICD_ENABLE			0x1
+#define GICD_DISABLE			0x0
+#define GICD_INT_ACTLOW_LVLTRIG		0x0
+#define GICD_INT_EN_CLR_X32		0xffffffff
+#define GICD_INT_EN_SET_SGI		0x0000ffff
+#define GICD_INT_EN_CLR_PPI		0xffff0000
+#define GICD_INT_DEF_PRI		0xa0
+#define GICD_INT_DEF_PRI_X4		((GICD_INT_DEF_PRI << 24) |\
+					(GICD_INT_DEF_PRI << 16) |\
+					(GICD_INT_DEF_PRI << 8) |\
+					GICD_INT_DEF_PRI)
+
+#define GICH_HCR			0x0
+#define GICH_VTR			0x4
+#define GICH_VMCR			0x8
+#define GICH_MISR			0x10
+#define GICH_EISR0 			0x20
+#define GICH_EISR1 			0x24
+#define GICH_ELRSR0 			0x30
+#define GICH_ELRSR1 			0x34
+#define GICH_APR			0xf0
+#define GICH_LR0			0x100
+
+#define GICH_HCR_EN			(1 << 0)
+#define GICH_HCR_UIE			(1 << 1)
+
+#define GICH_LR_VIRTUALID		(0x3ff << 0)
+#define GICH_LR_PHYSID_CPUID_SHIFT	(10)
+#define GICH_LR_PHYSID_CPUID		(7 << GICH_LR_PHYSID_CPUID_SHIFT)
+#define GICH_LR_STATE			(3 << 28)
+#define GICH_LR_PENDING_BIT		(1 << 28)
+#define GICH_LR_ACTIVE_BIT		(1 << 29)
+#define GICH_LR_EOI			(1 << 19)
+
+#define GICH_VMCR_CTRL_SHIFT		0
+#define GICH_VMCR_CTRL_MASK		(0x21f << GICH_VMCR_CTRL_SHIFT)
+#define GICH_VMCR_PRIMASK_SHIFT		27
+#define GICH_VMCR_PRIMASK_MASK		(0x1f << GICH_VMCR_PRIMASK_SHIFT)
+#define GICH_VMCR_BINPOINT_SHIFT	21
+#define GICH_VMCR_BINPOINT_MASK		(0x7 << GICH_VMCR_BINPOINT_SHIFT)
+#define GICH_VMCR_ALIAS_BINPOINT_SHIFT	18
+#define GICH_VMCR_ALIAS_BINPOINT_MASK	(0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
+
+#define GICH_MISR_EOI			(1 << 0)
+#define GICH_MISR_U			(1 << 1)
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+#define GIC_DIST_BASE			(gicv2_data.dist_base)
+#define GIC_CPU_BASE			(gicv2_data.cpu_base)
+
+struct gicv2_data {
+	void *dist_base;
+	void *cpu_base;
+};
+
+extern struct gicv2_data gicv2_data;
+
+static inline void gic_enable(void)
+{
+	writel(GICD_ENABLE, GIC_DIST_BASE + GIC_DIST_CTRL);
+	writel(0xff, GIC_CPU_BASE + GIC_CPU_PRIMASK);
+	writel(GICC_ENABLE, GIC_CPU_BASE + GIC_CPU_CTRL);
+}
+
+static inline void gic_irq_ack(void)
+{
+	unsigned int iar = readl(GIC_CPU_BASE + GIC_CPU_INTACK);
+	writel(iar, GIC_CPU_BASE + GIC_CPU_EOI);
+}
+
+static inline void gic_send_sgi(unsigned int cpu, unsigned int irq)
+{
+	writel(((1 << cpu) << 16) | irq, GIC_DIST_BASE + GIC_DIST_SOFTINT);
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASMARM_GIC_H_ */
diff --git a/lib/arm/io.c b/lib/arm/io.c
index a08d394..9eae13f 100644
--- a/lib/arm/io.c
+++ b/lib/arm/io.c
@@ -12,6 +12,7 @@
 #include <devicetree.h>
 #include <chr-testdev.h>
 #include <asm/spinlock.h>
+#include <asm/gic.h>
 #include <asm/io.h>
 
 extern void halt(int code);
@@ -62,10 +63,40 @@ static void uart0_init(void)
 	}
 }
 
+struct gicv2_data gicv2_data;
+static int gicv2_init(void)
+{
+	const char *compatible = "arm,cortex-a15-gic";
+	struct dt_pbus_reg reg;
+	struct dt_device gic;
+	struct dt_bus bus;
+	int node;
+
+	dt_bus_init_defaults(&bus);
+	dt_device_init(&gic, &bus, NULL);
+
+	node = dt_device_find_compatible(&gic, compatible);
+	assert(node >= 0 || node == -FDT_ERR_NOTFOUND);
+
+	if (node == -FDT_ERR_NOTFOUND)
+		return node;
+
+	assert(dt_pbus_translate_node(node, 0, &reg) == 0);
+
+	gicv2_data.dist_base = ioremap(reg.addr, reg.size);
+
+	assert(dt_pbus_translate_node(node, 1, &reg) == 0);
+
+	gicv2_data.cpu_base = ioremap(reg.addr, reg.size);
+
+	return 0;
+}
+
 void io_init(void)
 {
 	uart0_init();
 	chr_testdev_init();
+	assert(gicv2_init() == 0);
 }
 
 void puts(const char *s)
diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h
new file mode 100644
index 0000000..e5eb302
--- /dev/null
+++ b/lib/arm64/asm/gic.h
@@ -0,0 +1 @@
+#include "../../arm/asm/gic.h"
-- 
2.7.1

[Qemu-devel] [RFC 04/11] arm/arm64: Add IPI test

[Alex Bennée]

From: Andrew Jones <drjones@redhat.com>

Signed-off-by: Andrew Jones <drjones@redhat.com>
[ajb: slight tweak to .mak file]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 arm/ipi-test.c               | 58 ++++++++++++++++++++++++++++++++++++++++++++
 config/config-arm-common.mak |  2 ++
 2 files changed, 60 insertions(+)
 create mode 100644 arm/ipi-test.c

diff --git a/arm/ipi-test.c b/arm/ipi-test.c
new file mode 100644
index 0000000..705295f
--- /dev/null
+++ b/arm/ipi-test.c
@@ -0,0 +1,58 @@
+/*
+ * Test sending an IPI and handling IRQ exceptions.
+ *
+ * Copyright (C) 2015, Red Hat Inc, Andrew Jones <drjones@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <libcflat.h>
+#include <asm/setup.h>
+#include <asm/processor.h>
+#include <asm/gic.h>
+#include <asm/smp.h>
+#include <asm/barrier.h>
+
+static volatile bool ready, acked, done;
+
+static void irq_handler(struct pt_regs *regs __unused)
+{
+	gic_irq_ack();
+	acked = true;
+}
+
+static void ipi_test(void)
+{
+	gic_enable();
+#ifdef __arm__
+	install_exception_handler(EXCPTN_IRQ, irq_handler);
+#else
+	install_irq_handler(EL1H_IRQ, irq_handler);
+#endif
+	local_irq_enable();
+	ready = true;
+	wfi();
+	report("IPI", acked);
+	done = true;
+	halt();
+}
+
+int main(void)
+{
+	if (nr_cpus < 2) {
+		printf("ipi-test requires '-smp 2'\n");
+		abort();
+	}
+
+	gic_enable();
+	smp_boot_secondary(1, ipi_test);
+
+	while (!ready)
+		cpu_relax();
+
+	gic_send_sgi(1, 1);
+
+	while (!done)
+		cpu_relax();
+
+	return report_summary();
+}
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index e037507..d90eccc 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -11,6 +11,7 @@ endif
 
 tests-common = $(TEST_DIR)/selftest.flat
 tests-common += $(TEST_DIR)/spinlock-test.flat
+tests-common += $(TEST_DIR)/ipi-test.flat
 
 all: test_cases
 
@@ -69,3 +70,4 @@ test_cases: $(generated_files) $(tests-common) $(tests)
 
 $(TEST_DIR)/selftest.elf: $(cstart.o) $(TEST_DIR)/selftest.o
 $(TEST_DIR)/spinlock-test.elf: $(cstart.o) $(TEST_DIR)/spinlock-test.o
+$(TEST_DIR)/ipi-test.elf: $(cstart.o) $(TEST_DIR)/ipi-test.o
-- 
2.7.1

[Qemu-devel] [RFC 05/11] lib: add isaac prng library from CCAN

[Alex Bennée]

It's often useful to introduce some sort of random variation when
testing several racing CPU conditions. Instead of each test implementing
some half-arsed PRNG bring in a a decent one which has good statistical
randomness. Obviously it is deterministic for a given seed value which
is likely the behaviour you want.

I've pulled in the ISAAC library from CCAN:

    http://ccodearchive.net/info/isaac.html

I shaved off the float related stuff which is less useful for unit
testing and re-indented to fit the style. The original license was
CC0 (Public Domain) which is compatible with the LGPL v2 of
kvm-unit-tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
CC: Timothy B. Terriberry <tterribe@xiph.org>
Acked-by: Andrew Jones <drjones@redhat.com>
---
 config/config-arm-common.mak |   1 +
 lib/prng.c                   | 162 +++++++++++++++++++++++++++++++++++++++++++
 lib/prng.h                   |  82 ++++++++++++++++++++++
 3 files changed, 245 insertions(+)
 create mode 100644 lib/prng.c
 create mode 100644 lib/prng.h

diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index d90eccc..732c805 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -32,6 +32,7 @@ cflatobjs += lib/devicetree.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
+cflatobjs += lib/prng.o
 cflatobjs += lib/arm/io.o
 cflatobjs += lib/arm/setup.o
 cflatobjs += lib/arm/mmu.o
diff --git a/lib/prng.c b/lib/prng.c
new file mode 100644
index 0000000..ebd6df7
--- /dev/null
+++ b/lib/prng.c
@@ -0,0 +1,162 @@
+/*
+ * Pseudo Random Number Generator
+ *
+ * Lifted from ccan modules ilog/isaac under CC0
+ *   - http://ccodearchive.net/info/isaac.html
+ *   - http://ccodearchive.net/info/ilog.html
+ *
+ * And lightly hacked to compile under the KVM unit test environment.
+ * This provides a handy RNG for torture tests that want to vary
+ * delays and the like.
+ *
+ */
+
+/*Written by Timothy B. Terriberry (tterribe@xiph.org) 1999-2009.
+  CC0 (Public domain) - see LICENSE file for details
+  Based on the public domain implementation by Robert J. Jenkins Jr.*/
+
+#include "libcflat.h"
+
+#include <string.h>
+#include "prng.h"
+
+#define ISAAC_MASK        (0xFFFFFFFFU)
+
+/* Extract ISAAC_SZ_LOG bits (starting at bit 2). */
+static inline uint32_t lower_bits(uint32_t x)
+{
+	return (x & ((ISAAC_SZ-1) << 2)) >> 2;
+}
+
+/* Extract next ISAAC_SZ_LOG bits (starting at bit ISAAC_SZ_LOG+2). */
+static inline uint32_t upper_bits(uint32_t y)
+{
+	return (y >> (ISAAC_SZ_LOG+2)) & (ISAAC_SZ-1);
+}
+
+static void isaac_update(isaac_ctx *_ctx){
+	uint32_t *m;
+	uint32_t *r;
+	uint32_t  a;
+	uint32_t  b;
+	uint32_t  x;
+	uint32_t  y;
+	int       i;
+	m=_ctx->m;
+	r=_ctx->r;
+	a=_ctx->a;
+	b=_ctx->b+(++_ctx->c);
+	for(i=0;i<ISAAC_SZ/2;i++){
+		x=m[i];
+		a=(a^a<<13)+m[i+ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a>>6)+m[i+ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a<<2)+m[i+ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a>>16)+m[i+ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+	}
+	for(i=ISAAC_SZ/2;i<ISAAC_SZ;i++){
+		x=m[i];
+		a=(a^a<<13)+m[i-ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a>>6)+m[i-ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a<<2)+m[i-ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+		x=m[++i];
+		a=(a^a>>16)+m[i-ISAAC_SZ/2];
+		m[i]=y=m[lower_bits(x)]+a+b;
+		r[i]=b=m[upper_bits(y)]+x;
+	}
+	_ctx->b=b;
+	_ctx->a=a;
+	_ctx->n=ISAAC_SZ;
+}
+
+static void isaac_mix(uint32_t _x[8]){
+	static const unsigned char SHIFT[8]={11,2,8,16,10,4,8,9};
+	int i;
+	for(i=0;i<8;i++){
+		_x[i]^=_x[(i+1)&7]<<SHIFT[i];
+		_x[(i+3)&7]+=_x[i];
+		_x[(i+1)&7]+=_x[(i+2)&7];
+		i++;
+		_x[i]^=_x[(i+1)&7]>>SHIFT[i];
+		_x[(i+3)&7]+=_x[i];
+		_x[(i+1)&7]+=_x[(i+2)&7];
+	}
+}
+
+
+void isaac_init(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed){
+	_ctx->a=_ctx->b=_ctx->c=0;
+	memset(_ctx->r,0,sizeof(_ctx->r));
+	isaac_reseed(_ctx,_seed,_nseed);
+}
+
+void isaac_reseed(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed){
+	uint32_t *m;
+	uint32_t *r;
+	uint32_t  x[8];
+	int       i;
+	int       j;
+	m=_ctx->m;
+	r=_ctx->r;
+	if(_nseed>ISAAC_SEED_SZ_MAX)_nseed=ISAAC_SEED_SZ_MAX;
+	for(i=0;i<_nseed>>2;i++){
+		r[i]^=(uint32_t)_seed[i<<2|3]<<24|(uint32_t)_seed[i<<2|2]<<16|
+			(uint32_t)_seed[i<<2|1]<<8|_seed[i<<2];
+	}
+	_nseed-=i<<2;
+	if(_nseed>0){
+		uint32_t ri;
+		ri=_seed[i<<2];
+		for(j=1;j<_nseed;j++)ri|=(uint32_t)_seed[i<<2|j]<<(j<<3);
+		r[i++]^=ri;
+	}
+	x[0]=x[1]=x[2]=x[3]=x[4]=x[5]=x[6]=x[7]=0x9E3779B9U;
+	for(i=0;i<4;i++)isaac_mix(x);
+	for(i=0;i<ISAAC_SZ;i+=8){
+		for(j=0;j<8;j++)x[j]+=r[i+j];
+		isaac_mix(x);
+		memcpy(m+i,x,sizeof(x));
+	}
+	for(i=0;i<ISAAC_SZ;i+=8){
+		for(j=0;j<8;j++)x[j]+=m[i+j];
+		isaac_mix(x);
+		memcpy(m+i,x,sizeof(x));
+	}
+	isaac_update(_ctx);
+}
+
+uint32_t isaac_next_uint32(isaac_ctx *_ctx){
+	if(!_ctx->n)isaac_update(_ctx);
+	return _ctx->r[--_ctx->n];
+}
+
+uint32_t isaac_next_uint(isaac_ctx *_ctx,uint32_t _n){
+	uint32_t r;
+	uint32_t v;
+	uint32_t d;
+	do{
+		r=isaac_next_uint32(_ctx);
+		v=r%_n;
+		d=r-v;
+	}
+	while(((d+_n-1)&ISAAC_MASK)<d);
+	return v;
+}
diff --git a/lib/prng.h b/lib/prng.h
new file mode 100644
index 0000000..bf5776d
--- /dev/null
+++ b/lib/prng.h
@@ -0,0 +1,82 @@
+/*
+ * PRNG Header
+ */
+#ifndef __PRNG_H__
+#define __PRNG_H__
+
+# include <stdint.h>
+
+
+
+typedef struct isaac_ctx isaac_ctx;
+
+
+
+/*This value may be lowered to reduce memory usage on embedded platforms, at
+  the cost of reducing security and increasing bias.
+  Quoting Bob Jenkins: "The current best guess is that bias is detectable after
+  2**37 values for [ISAAC_SZ_LOG]=3, 2**45 for 4, 2**53 for 5, 2**61 for 6,
+  2**69 for 7, and 2**77 values for [ISAAC_SZ_LOG]=8."*/
+#define ISAAC_SZ_LOG      (8)
+#define ISAAC_SZ          (1<<ISAAC_SZ_LOG)
+#define ISAAC_SEED_SZ_MAX (ISAAC_SZ<<2)
+
+
+
+/*ISAAC is the most advanced of a series of pseudo-random number generators
+  designed by Robert J. Jenkins Jr. in 1996.
+  http://www.burtleburtle.net/bob/rand/isaac.html
+  To quote:
+  No efficient method is known for deducing their internal states.
+  ISAAC requires an amortized 18.75 instructions to produce a 32-bit value.
+  There are no cycles in ISAAC shorter than 2**40 values.
+  The expected cycle length is 2**8295 values.*/
+struct isaac_ctx{
+	unsigned n;
+	uint32_t r[ISAAC_SZ];
+	uint32_t m[ISAAC_SZ];
+	uint32_t a;
+	uint32_t b;
+	uint32_t c;
+};
+
+
+/**
+ * isaac_init - Initialize an instance of the ISAAC random number generator.
+ * @_ctx:   The instance to initialize.
+ * @_seed:  The specified seed bytes.
+ *          This may be NULL if _nseed is less than or equal to zero.
+ * @_nseed: The number of bytes to use for the seed.
+ *          If this is greater than ISAAC_SEED_SZ_MAX, the extra bytes are
+ *           ignored.
+ */
+void isaac_init(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed);
+
+/**
+ * isaac_reseed - Mix a new batch of entropy into the current state.
+ * To reset ISAAC to a known state, call isaac_init() again instead.
+ * @_ctx:   The instance to reseed.
+ * @_seed:  The specified seed bytes.
+ *          This may be NULL if _nseed is zero.
+ * @_nseed: The number of bytes to use for the seed.
+ *          If this is greater than ISAAC_SEED_SZ_MAX, the extra bytes are
+ *           ignored.
+ */
+void isaac_reseed(isaac_ctx *_ctx,const unsigned char *_seed,int _nseed);
+/**
+ * isaac_next_uint32 - Return the next random 32-bit value.
+ * @_ctx: The ISAAC instance to generate the value with.
+ */
+uint32_t isaac_next_uint32(isaac_ctx *_ctx);
+/**
+ * isaac_next_uint - Uniform random integer less than the given value.
+ * @_ctx: The ISAAC instance to generate the value with.
+ * @_n:   The upper bound on the range of numbers returned (not inclusive).
+ *        This must be greater than zero and less than 2**32.
+ *        To return integers in the full range 0...2**32-1, use
+ *         isaac_next_uint32() instead.
+ * Return: An integer uniformly distributed between 0 and _n-1 (inclusive).
+ */
+uint32_t isaac_next_uint(isaac_ctx *_ctx,uint32_t _n);
+
+#endif
-- 
2.7.1

[Qemu-devel] [RFC 06/11] arm/run: set indentation defaults for emacs

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 arm/run | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arm/run b/arm/run
index dc0a332..0eaf23a 100755
--- a/arm/run
+++ b/arm/run
@@ -1,4 +1,5 @@
 #!/bin/bash
+# -*- sh-basic-offset:8 indent-tabs-mode: t -*-
 
 if [ -z "$STANDALONE" ]; then
 	if [ ! -f config.mak ]; then
-- 
2.7.1

[Qemu-devel] [RFC 07/11] arm/run: allow aarch64 to start arm binaries

[Alex Bennée]

AArch64 hosts can happily run AArch32 binaries. We just need to ensure
that we use "cpu host,aarch64=off" when specifying the CPU type.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 arm/run | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arm/run b/arm/run
index 0eaf23a..f1a6b7d 100755
--- a/arm/run
+++ b/arm/run
@@ -38,7 +38,15 @@ if [ "$HOST" = "aarch64" ] && [ "$ACCEL" = "kvm" ]; then
 	fi
 fi
 
-qemu="${QEMU:-qemu-system-$ARCH_NAME}"
+if [ "$ARCH" = "arm" ] && [ "$HOST" = "aarch64" ]; then
+    qemu="${QEMU:-qemu-system-$HOST}"
+    if [ "$ACCEL" = "kvm" ]; then
+	processor="host,aarch64=off"
+    fi
+else
+	qemu="${QEMU:-qemu-system-$ARCH_NAME}"
+fi
+
 qpath=$(which $qemu 2>/dev/null)
 
 if [ -z "$qpath" ]; then
-- 
2.7.1

[Qemu-devel] [RFC 08/11] arm/tlbflush-test: Add TLB torture test

[Alex Bennée]

This adds a fairly brain dead torture test for TLB flushes intended for
stressing the MTTCG QEMU build. It takes the usual -smp option for
multiple CPUs.

By default it CPU0 will do a TLBIALL flush after each cycle. You can
pass options via -append to control additional aspects of the test:

  - "page" flush each page in turn (one per function)
  - "self" do the flush after each computation cycle
  - "verbose" report progress on each computation cycle

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
v2
  - rename to tlbflush-test
  - made makefile changes cleaner
  - added self/other flush mode
  - create specific prefix
  - whitespace fixes
v3
  - using new SMP framework for test runing
v4
  - merge in the unitests.cfg
---
 arm/tlbflush-test.c          | 194 +++++++++++++++++++++++++++++++++++++++++++
 arm/unittests.cfg            |  24 ++++++
 config/config-arm-common.mak |   2 +
 3 files changed, 220 insertions(+)
 create mode 100644 arm/tlbflush-test.c

diff --git a/arm/tlbflush-test.c b/arm/tlbflush-test.c
new file mode 100644
index 0000000..0375ad9
--- /dev/null
+++ b/arm/tlbflush-test.c
@@ -0,0 +1,194 @@
+#include <libcflat.h>
+#include <asm/smp.h>
+#include <asm/cpumask.h>
+#include <asm/barrier.h>
+#include <asm/mmu.h>
+
+#define SEQ_LENGTH 10
+#define SEQ_HASH 0x7cd707fe
+
+static cpumask_t smp_test_complete;
+static int flush_count = 1000000;
+static int flush_self = 0;
+static int flush_page = 0;
+static int flush_verbose = 0;
+
+/* Work functions
+ *
+ * These work functions need to be:
+ *
+ *  - page aligned, so we can flush one function at a time
+ *  - have branches, so QEMU TCG generates multiple basic blocks
+ *  - call across pages, so we exercise the TCG basic block slow path
+ */
+
+/* Adler32 */
+__attribute__((aligned(PAGE_SIZE))) uint32_t hash_array(const void *buf,
+							size_t buflen)
+{
+	const uint8_t *data = (uint8_t *) buf;
+	uint32_t s1 = 1;
+	uint32_t s2 = 0;
+
+	for (size_t n = 0; n < buflen; n++) {
+		s1 = (s1 + data[n]) % 65521;
+		s2 = (s2 + s1) % 65521;
+	}
+	return (s2 << 16) | s1;
+}
+
+__attribute__((aligned(PAGE_SIZE))) void create_fib_sequence(int length,
+							unsigned int *array)
+{
+	int i;
+
+	/* first two values */
+	array[0] = 0;
+	array[1] = 1;
+	for (i=2; i<length; i++) {
+		array[i] = array[i-2] + array[i-1];
+	}
+}
+
+__attribute__((aligned(PAGE_SIZE))) unsigned long long factorial(unsigned int n)
+{
+	unsigned int i;
+	unsigned long long fac = 1;
+	for (i=1; i<=n; i++)
+	{
+		fac = fac * i;
+	}
+	return fac;
+}
+
+__attribute__((aligned(PAGE_SIZE))) void factorial_array
+(unsigned int n, unsigned int *input, unsigned long long *output)
+{
+	unsigned int i;
+	for (i=0; i<n; i++) {
+		output[i] = factorial(input[i]);
+	}
+}
+
+__attribute__((aligned(PAGE_SIZE))) unsigned int do_computation(void)
+{
+	unsigned int fib_array[SEQ_LENGTH];
+	unsigned long long facfib_array[SEQ_LENGTH];
+	uint32_t fib_hash, facfib_hash;
+
+	create_fib_sequence(SEQ_LENGTH, &fib_array[0]);
+	fib_hash = hash_array(&fib_array[0], sizeof(fib_array));
+	factorial_array(SEQ_LENGTH, &fib_array[0], &facfib_array[0]);
+	facfib_hash = hash_array(&facfib_array[0], sizeof(facfib_array));
+
+	return (fib_hash ^ facfib_hash);
+}
+
+/* This provides a table of the work functions so we can flush each
+ * page individually
+ */
+static void * pages[] = {&hash_array, &create_fib_sequence, &factorial,
+			 &factorial_array, &do_computation};
+
+static void do_flush(int i)
+{
+	if (flush_page) {
+		flush_tlb_page((unsigned long)pages[i % ARRAY_SIZE(pages)]);
+	} else {
+		flush_tlb_all();
+	}
+}
+
+
+static void just_compute(void)
+{
+	int i, errors = 0;
+	int cpu = smp_processor_id();
+
+	uint32_t result;
+
+	printf("CPU%d online\n", cpu);
+
+	for (i=0; i < flush_count; i++) {
+		result = do_computation();
+
+		if (result != SEQ_HASH) {
+			errors++;
+			printf("CPU%d: seq%d 0x%x!=0x%x\n",
+				cpu, i, result, SEQ_HASH);
+		}
+
+		if (flush_verbose && (i % 1000) == 0) {
+			printf("CPU%d: seq%d\n", cpu, i);
+		}
+
+		if (flush_self) {
+			do_flush(i);
+		}
+	}
+
+	report("CPU%d: Done - Errors: %d\n", errors == 0, cpu, errors);
+
+	cpumask_set_cpu(cpu, &smp_test_complete);
+	if (cpu != 0)
+		halt();
+}
+
+static void just_flush(void)
+{
+	int cpu = smp_processor_id();
+	int i = 0;
+
+	/* set our CPU as done, keep flushing until everyone else
+	   finished */
+	cpumask_set_cpu(cpu, &smp_test_complete);
+
+	while (!cpumask_full(&smp_test_complete)) {
+		do_flush(i++);
+	}
+
+	report("CPU%d: Done - Triggered %d flushes\n", true, cpu, i);
+}
+
+int main(int argc, char **argv)
+{
+	int cpu, i;
+	char prefix[100];
+
+	for (i=0; i<argc; i++) {
+		char *arg = argv[i];
+
+		if (strcmp(arg, "page") == 0) {
+			flush_page = 1;
+                }
+
+                if (strcmp(arg, "self") == 0) {
+			flush_self = 1;
+                }
+
+		if (strcmp(arg, "verbose") == 0) {
+			flush_verbose = 1;
+                }
+	}
+
+	snprintf(prefix, sizeof(prefix), "tlbflush_%s_%s",
+		flush_page?"page":"all",
+		flush_self?"self":"other");
+	report_prefix_push(prefix);
+
+	for_each_present_cpu(cpu) {
+		if (cpu == 0)
+			continue;
+		smp_boot_secondary(cpu, just_compute);
+	}
+
+	if (flush_self)
+		just_compute();
+	else
+		just_flush();
+
+	while (!cpumask_full(&smp_test_complete))
+		cpu_relax();
+
+	return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 5e26da1..8aebdba 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -38,3 +38,27 @@ file = selftest.flat
 smp = $MAX_SMP
 extra_params = -append 'smp'
 groups = selftest
+
+# TLB Torture Tests
+[tlbflush::all_other]
+file = tlbflush-test.flat
+smp = $MAX_SMP
+groups = tlbflush
+
+[tlbflush::page_other]
+file = tlbflush-test.flat
+smp = $MAX_SMP
+extra_params = -append 'page'
+groups = tlbflush
+
+[tlbflush::all_self]
+file = tlbflush-test.flat
+smp = $MAX_SMP
+extra_params = -append 'self'
+groups = tlbflush
+
+[tlbflush::page_self]
+file = tlbflush-test.flat
+smp = $MAX_SMP
+extra_params = -append 'page self'
+groups = tlbflush
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index 732c805..e6ad11b 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -12,6 +12,7 @@ endif
 tests-common = $(TEST_DIR)/selftest.flat
 tests-common += $(TEST_DIR)/spinlock-test.flat
 tests-common += $(TEST_DIR)/ipi-test.flat
+tests-common += $(TEST_DIR)/tlbflush-test.flat
 
 all: test_cases
 
@@ -72,3 +73,4 @@ test_cases: $(generated_files) $(tests-common) $(tests)
 $(TEST_DIR)/selftest.elf: $(cstart.o) $(TEST_DIR)/selftest.o
 $(TEST_DIR)/spinlock-test.elf: $(cstart.o) $(TEST_DIR)/spinlock-test.o
 $(TEST_DIR)/ipi-test.elf: $(cstart.o) $(TEST_DIR)/ipi-test.o
+$(TEST_DIR)/tlbflush-test.elf: $(cstart.o) $(TEST_DIR)/tlbflush-test.o
-- 
2.7.1

[Qemu-devel] [RFC 09/11] arm/locking-tests: add comprehensive locking test

[Alex Bennée]

This test has been written mainly to stress multi-threaded TCG behaviour
but will demonstrate failure by default on real hardware. The test takes
the following parameters:

  - "lock" use GCC's locking semantics
  - "atomic" use GCC's __atomic primitives
  - "wfelock" use WaitForEvent sleep
  - "excl" use load/store exclusive semantics

Also two more options allow the test to be tweaked

  - "noshuffle" disables the memory shuffling
  - "count=%ld" set your own per-CPU increment count

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
v2
  - Don't use thumb style strexeq stuff
  - Add atomic and wfelock tests
  - Add count/noshuffle test controls
  - Move barrier tests to separate test file
v4
  - fix up unitests.cfg to use correct test name
  - move into "locking" group, remove barrier tests
  - use a table to add tests, mark which are expected to work
  - correctly report XFAIL
---
 arm/locking-test.c           | 302 +++++++++++++++++++++++++++++++++++++++++++
 arm/unittests.cfg            |  35 +++++
 config/config-arm-common.mak |   2 +
 3 files changed, 339 insertions(+)
 create mode 100644 arm/locking-test.c

diff --git a/arm/locking-test.c b/arm/locking-test.c
new file mode 100644
index 0000000..fcbe17c
--- /dev/null
+++ b/arm/locking-test.c
@@ -0,0 +1,302 @@
+#include <libcflat.h>
+#include <asm/smp.h>
+#include <asm/cpumask.h>
+#include <asm/barrier.h>
+#include <asm/mmu.h>
+
+#include <prng.h>
+
+#define MAX_CPUS 8
+
+/* Test definition structure
+ *
+ * A simple structure that describes the test name, expected pass and
+ * increment function.
+ */
+
+/* Function pointers for test */
+typedef void (*inc_fn)(int cpu);
+
+typedef struct {
+	const char *test_name;
+	bool  should_pass;
+	inc_fn main_fn;
+} test_descr_t;
+
+/* How many increments to do */
+static int increment_count = 10000000;
+static int do_shuffle = 1;
+
+/* Shared value all the tests attempt to safely increment using
+ * various forms of atomic locking and exclusive behaviour.
+ */
+static unsigned int shared_value;
+
+/* PAGE_SIZE * uint32_t means we span several pages */
+__attribute__((aligned(PAGE_SIZE))) static uint32_t memory_array[PAGE_SIZE];
+
+/* We use the alignment of the following to ensure accesses to locking
+ * and synchronisation primatives don't interfere with the page of the
+ * shared value
+ */
+__attribute__((aligned(PAGE_SIZE))) static unsigned int per_cpu_value[MAX_CPUS];
+__attribute__((aligned(PAGE_SIZE))) static cpumask_t smp_test_complete;
+__attribute__((aligned(PAGE_SIZE))) struct isaac_ctx prng_context[MAX_CPUS];
+
+/* Some of the approaches use a global lock to prevent contention. */
+static int global_lock;
+
+/* In any SMP setting this *should* fail due to cores stepping on
+ * each other updating the shared variable
+ */
+static void increment_shared(int cpu)
+{
+	(void)cpu;
+
+	shared_value++;
+}
+
+/* GCC __sync primitives are deprecated in favour of __atomic */
+static void increment_shared_with_lock(int cpu)
+{
+	(void)cpu;
+
+	while (__sync_lock_test_and_set(&global_lock, 1));
+	shared_value++;
+	__sync_lock_release(&global_lock);
+}
+
+/* In practice even __ATOMIC_RELAXED uses ARM's ldxr/stex exclusive
+ * semantics */
+static void increment_shared_with_atomic(int cpu)
+{
+	(void)cpu;
+
+	__atomic_add_fetch(&shared_value, 1, __ATOMIC_SEQ_CST);
+}
+
+
+/*
+ * Load/store exclusive with WFE (wait-for-event)
+ *
+ * See ARMv8 ARM examples:
+ *   Use of Wait For Event (WFE) and Send Event (SEV) with locks
+ */
+
+static void increment_shared_with_wfelock(int cpu)
+{
+	(void)cpu;
+
+#if defined(__aarch64__)
+	asm volatile(
+	"	mov     w1, #1\n"
+	"       sevl\n"
+	"       prfm PSTL1KEEP, [%[lock]]\n"
+	"1:     wfe\n"
+	"	ldaxr	w0, [%[lock]]\n"
+	"	cbnz    w0, 1b\n"
+	"	stxr    w0, w1, [%[lock]]\n"
+	"	cbnz	w0, 1b\n"
+	/* lock held */
+	"	ldr	w0, [%[sptr]]\n"
+	"	add	w0, w0, #0x1\n"
+	"	str	w0, [%[sptr]]\n"
+	/* now release */
+	"	stlr	wzr, [%[lock]]\n"
+	: /* out */
+	: [lock] "r" (&global_lock), [sptr] "r" (&shared_value) /* in */
+	: "w0", "w1", "cc");
+#else
+	asm volatile(
+	"	mov     r1, #1\n"
+	"1:	ldrex	r0, [%[lock]]\n"
+	"	cmp     r0, #0\n"
+	"	wfene\n"
+	"	strexeq r0, r1, [%[lock]]\n"
+	"	cmpeq	r0, #0\n"
+	"	bne	1b\n"
+	"	dmb\n"
+	/* lock held */
+	"	ldr	r0, [%[sptr]]\n"
+	"	add	r0, r0, #0x1\n"
+	"	str	r0, [%[sptr]]\n"
+	/* now release */
+	"	mov	r0, #0\n"
+	"	dmb\n"
+	"	str	r0, [%[lock]]\n"
+	"	dsb\n"
+	"	sev\n"
+	: /* out */
+	: [lock] "r" (&global_lock), [sptr] "r" (&shared_value) /* in */
+	: "r0", "r1", "cc");
+#endif
+}
+
+
+/*
+ * Hand-written version of the load/store exclusive
+ */
+static void increment_shared_with_excl(int cpu)
+{
+	(void)cpu;
+
+#if defined(__aarch64__)
+        asm volatile(
+	"1:	ldxr	w0, [%[sptr]]\n"
+	"	add     w0, w0, #0x1\n"
+	"	stxr	w1, w0, [%[sptr]]\n"
+	"	cbnz	w1, 1b\n"
+	: /* out */
+	: [sptr] "r" (&shared_value) /* in */
+	: "w0", "w1", "cc");
+#else
+	asm volatile(
+	"1:	ldrex	r0, [%[sptr]]\n"
+	"	add     r0, r0, #0x1\n"
+	"	strex	r1, r0, [%[sptr]]\n"
+	"	cmp	r1, #0\n"
+	"	bne	1b\n"
+	: /* out */
+	: [sptr] "r" (&shared_value) /* in */
+	: "r0", "r1", "cc");
+#endif
+}
+
+/* Test array */
+static test_descr_t tests[] = {
+	{ "none", false, increment_shared },
+	{ "lock", true, increment_shared_with_lock },
+	{ "atomic", true, increment_shared_with_atomic },
+	{ "wfelock", true, increment_shared_with_wfelock },
+	{ "excl", true, increment_shared_with_excl }
+};
+
+/* The idea of this is just to generate some random load/store
+ * activity which may or may not race with an un-barried incremented
+ * of the shared counter
+ */
+static void shuffle_memory(int cpu)
+{
+	int i;
+	uint32_t lspat = isaac_next_uint32(&prng_context[cpu]);
+	uint32_t seq = isaac_next_uint32(&prng_context[cpu]);
+	int count = seq & 0x1f;
+	uint32_t val=0;
+
+	seq >>= 5;
+
+	for (i=0; i<count; i++) {
+		int index = seq & ~PAGE_MASK;
+		if (lspat & 1) {
+			val ^= memory_array[index];
+		} else {
+			memory_array[index] = val;
+		}
+		seq >>= PAGE_SHIFT;
+		seq ^= lspat;
+		lspat >>= 1;
+	}
+
+}
+
+static inc_fn increment_function;
+
+static void do_increment(void)
+{
+	int i;
+	int cpu = smp_processor_id();
+
+	printf("CPU%d: online and ++ing\n", cpu);
+
+	for (i=0; i < increment_count; i++) {
+		per_cpu_value[cpu]++;
+		increment_function(cpu);
+
+		if (do_shuffle)
+			shuffle_memory(cpu);
+	}
+
+	printf("CPU%d: Done, %d incs\n", cpu, per_cpu_value[cpu]);
+
+	cpumask_set_cpu(cpu, &smp_test_complete);
+	if (cpu != 0)
+		halt();
+}
+
+static void setup_and_run_test(test_descr_t *test)
+{
+	unsigned int i, sum = 0;
+	int cpu, cpu_cnt = 0;
+
+	increment_function = test->main_fn;
+
+	/* fill our random page */
+        for (i=0; i<PAGE_SIZE; i++) {
+		memory_array[i] = isaac_next_uint32(&prng_context[0]);
+	}
+
+	for_each_present_cpu(cpu) {
+		uint32_t seed2 = isaac_next_uint32(&prng_context[0]);
+		cpu_cnt++;
+		if (cpu == 0)
+			continue;
+
+		isaac_init(&prng_context[cpu], (unsigned char *) &seed2, sizeof(seed2));
+		smp_boot_secondary(cpu, do_increment);
+	}
+
+	do_increment();
+
+	while (!cpumask_full(&smp_test_complete))
+		cpu_relax();
+
+	/* All CPUs done, do we add up */
+	for_each_present_cpu(cpu) {
+		sum += per_cpu_value[cpu];
+	}
+
+	if (test->should_pass) {
+		report("total incs %d", sum == shared_value, shared_value);
+	} else {
+		report_xfail("total incs %d", true, sum == shared_value, shared_value);
+	}
+}
+
+int main(int argc, char **argv)
+{
+	static const unsigned char seed[] = "myseed";
+	test_descr_t *test = &tests[0];
+	int i;
+	unsigned int j;
+
+	isaac_init(&prng_context[0], &seed[0], sizeof(seed));
+
+	for (i=0; i<argc; i++) {
+		char *arg = argv[i];
+
+		/* Check for test name */
+		for (j = 0; j < ARRAY_SIZE(tests); j++) {
+			if (strcmp(arg, tests[j].test_name) == 0)
+				test = &tests[j];
+		}
+
+		/* Test modifiers */
+		if (strcmp(arg, "noshuffle") == 0) {
+			do_shuffle = 0;
+			report_prefix_push("noshuffle");
+		} else if (strstr(arg, "count=") != NULL) {
+			char *p = strstr(arg, "=");
+			increment_count = atol(p+1);
+		} else {
+			isaac_reseed(&prng_context[0], (unsigned char *) arg, strlen(arg));
+		}
+	}
+
+	if (test) {
+		setup_and_run_test(test);
+	} else {
+		report("Unknown test", false);
+	}
+
+	return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 8aebdba..1a61b31 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -62,3 +62,38 @@ file = tlbflush-test.flat
 smp = $MAX_SMP
 extra_params = -append 'page self'
 groups = tlbflush
+
+# Locking tests
+[locking::none]
+file = locking-test.flat
+smp = $MAX_SMP
+groups = locking
+accel = tcg
+
+[locking::lock]
+file = locking-test.flat
+smp = $MAX_SMP
+extra_params = -append 'lock'
+groups = locking
+accel = tcg
+
+[locking::atomic]
+file = locking-test.flat
+smp = $MAX_SMP
+extra_params = -append 'atomic'
+groups = locking
+accel = tcg
+
+[locking::wfelock]
+file = locking-test.flat
+smp = $MAX_SMP
+extra_params = -append 'wfelock'
+groups = locking
+accel = tcg
+
+[locking::excl]
+file = locking-test.flat
+smp = $MAX_SMP
+extra_params = -append 'excl'
+groups = locking
+accel = tcg
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index e6ad11b..6857261 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -13,6 +13,7 @@ tests-common = $(TEST_DIR)/selftest.flat
 tests-common += $(TEST_DIR)/spinlock-test.flat
 tests-common += $(TEST_DIR)/ipi-test.flat
 tests-common += $(TEST_DIR)/tlbflush-test.flat
+tests-common += $(TEST_DIR)/locking-test.flat
 
 all: test_cases
 
@@ -74,3 +75,4 @@ $(TEST_DIR)/selftest.elf: $(cstart.o) $(TEST_DIR)/selftest.o
 $(TEST_DIR)/spinlock-test.elf: $(cstart.o) $(TEST_DIR)/spinlock-test.o
 $(TEST_DIR)/ipi-test.elf: $(cstart.o) $(TEST_DIR)/ipi-test.o
 $(TEST_DIR)/tlbflush-test.elf: $(cstart.o) $(TEST_DIR)/tlbflush-test.o
+$(TEST_DIR)/locking-test.elf: $(cstart.o) $(TEST_DIR)/locking-test.o
-- 
2.7.1

[Qemu-devel] [RFC 10/11] arm/barrier-litmus-tests: add some litmus tests

[Alex Bennée]

This adds a framework for adding simple barrier litmus tests against
ARM. The litmus tests aren't as comprehensive as the academic exercises
which will attempt to do all sorts of things to keep racing CPUs synced
up. These tests do honour the "sync" parameter to do a poor-mans
equivilent.

I've imported a few more of the barrier primatives from the Linux source
tree so we consistently use macros.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
  - add a unittest.cfg
---
 arm/barrier-litmus-test.c    | 258 +++++++++++++++++++++++++++++++++++++++++++
 arm/unittests.cfg            |  21 ++++
 config/config-arm-common.mak |   2 +
 lib/arm/asm/barrier.h        |  63 ++++++++++-
 lib/arm64/asm/barrier.h      |  50 +++++++++
 5 files changed, 393 insertions(+), 1 deletion(-)
 create mode 100644 arm/barrier-litmus-test.c

diff --git a/arm/barrier-litmus-test.c b/arm/barrier-litmus-test.c
new file mode 100644
index 0000000..45cdcdc
--- /dev/null
+++ b/arm/barrier-litmus-test.c
@@ -0,0 +1,258 @@
+/*
+ * ARM Barrier Litmus Tests
+ *
+ * This test provides a framework for testing barrier conditions on
+ * the processor. It's simpler than the more involved barrier testing
+ * frameworks as we are looking for simple failures of QEMU's TCG not
+ * weird edge cases the silicon gets wrong.
+ */
+
+#include <libcflat.h>
+#include <asm/smp.h>
+#include <asm/cpumask.h>
+#include <asm/barrier.h>
+#include <asm/mmu.h>
+
+#define MAX_CPUS 8
+
+/* Array size and access controls */
+static int array_size = 100000;
+static int wait_if_ahead = 0;
+
+/*
+ * These test_array_* structures are a contiguous array modified by two or more
+ * competing CPUs. The padding is to ensure the variables do not share
+ * cache lines.
+ *
+ * All structures start zeroed.
+ */
+
+typedef struct test_array
+{
+	volatile unsigned int x;
+	uint8_t dummy[64];
+	volatile unsigned int y;
+	uint8_t dummy2[64];
+	volatile int z;
+} test_array;
+
+volatile test_array *array;
+
+/* Test definition structure
+ *
+ * The first function will always run on the primary CPU, it is
+ * usually the one that will detect any weirdness and trigger the
+ * failure of the test.
+ */
+
+typedef void (*test_fn)(void);
+
+typedef struct {
+	const char *test_name;
+	bool  should_pass;
+	test_fn main_fn;
+	test_fn secondary_fns[MAX_CPUS-1];
+} test_descr_t;
+
+/* Litmus tests */
+
+/* Simple Message Passing
+ *
+ * x is the message data
+ * y is the flag to indicate the data is ready
+ *
+ * Reading x == 0 when y == 1 is a failure.
+ */
+
+void message_passing_write(void)
+{
+	int i;
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		entry->x = 1;
+		entry->y = 1;
+	}
+
+	halt();
+}
+
+void message_passing_read(void)
+{
+	int i;
+	int errors = 0, ready = 0;
+
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		unsigned int x,y;
+		y = entry->y;
+		x = entry->x;
+
+		if (y && !x)
+			errors++;
+		ready += y;
+	}
+
+	report_xfail("mp: %d errors, %d ready", true, errors == 0, errors, ready);
+}
+
+/* Simple Message Passing with barriers */
+void message_passing_write_barrier(void)
+{
+	int i;
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		entry->x = 1;
+		smp_wmb();
+		entry->y = 1;
+	}
+
+	halt();
+}
+
+void message_passing_read_barrier(void)
+{
+	int i;
+	int errors = 0, ready = 0, not_ready = 0;
+
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		unsigned int x, y;
+		y = entry->y;
+		smp_rmb();
+		x = entry->x;
+
+		if (y && !x)
+			errors++;
+
+		if (y) {
+			ready++;
+		} else {
+			not_ready++;
+
+			if (not_ready > 2) {
+				entry = &array[i+1];
+				do {
+					not_ready = 0;
+				} while (wait_if_ahead && !entry->y);
+			}
+		}
+	}
+
+	report("mp barrier: %d errors, %d ready", errors == 0, errors, ready);
+}
+
+/* Simple Message Passing with Acquire/Release */
+void message_passing_write_release(void)
+{
+	int i;
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		entry->x = 1;
+		smp_store_release(&entry->y, 1);
+	}
+
+	halt();
+}
+
+void message_passing_read_acquire(void)
+{
+	int i;
+	int errors = 0, ready = 0, not_ready = 0;
+
+	for (i=0; i< array_size; i++) {
+		volatile test_array *entry = &array[i];
+		unsigned int x, y;
+		y = smp_load_acquire(&entry->y);
+		x = entry->x;
+
+		if (y && !x)
+			errors++;
+
+		if (y) {
+			ready++;
+		} else {
+			not_ready++;
+
+			if (not_ready > 2) {
+				entry = &array[i+1];
+				do {
+					not_ready = 0;
+				} while (wait_if_ahead && !entry->y);
+			}
+		}
+	}
+
+	report("mp acqrel: %d errors, %d ready", errors == 0, errors, ready);
+}
+
+
+/* Test array */
+static test_descr_t tests[] = {
+
+	{ "mp",         false,
+	  message_passing_read,
+	  { message_passing_write }
+	},
+
+	{ "mp_barrier", true,
+	  message_passing_read_barrier,
+	  { message_passing_write_barrier }
+	},
+
+	{ "mp_acqrel", true,
+	  message_passing_read_acquire,
+	  { message_passing_write_release }
+	}
+};
+
+
+void setup_and_run_litmus(test_descr_t *test)
+{
+	array = calloc(array_size, sizeof(test_array));
+
+	if (array) {
+		int i = 0;
+		printf("Allocated test array @ %p\n", array);
+
+		while (test->secondary_fns[i]) {
+			smp_boot_secondary(i+1, test->secondary_fns[i]);
+			i++;
+		}
+
+		test->main_fn();
+	} else {
+		report("%s: failed to allocate memory",false, test->test_name);
+	}
+}
+
+int main(int argc, char **argv)
+{
+	int i;
+	unsigned int j;
+	test_descr_t *test = NULL;
+
+	for (i=0; i<argc; i++) {
+		char *arg = argv[i];
+
+		for (j = 0; j < ARRAY_SIZE(tests); j++) {
+			if (strcmp(arg, tests[j].test_name) == 0)
+				test = & tests[j];
+		}
+
+		/* Test modifiers */
+		if (strstr(arg, "count=") != NULL) {
+			char *p = strstr(arg, "=");
+			array_size = atol(p+1);
+		} else if (strcmp (arg, "wait") == 0) {
+			wait_if_ahead = 1;
+		}
+	}
+
+	if (test) {
+		setup_and_run_litmus(test);
+	} else {
+		report("Unknown test", false);
+	}
+
+	return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 1a61b31..3f05cfa 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -97,3 +97,24 @@ smp = $MAX_SMP
 extra_params = -append 'excl'
 groups = locking
 accel = tcg
+
+[barrier-litmus::mp]
+file = barrier-litmus-test.flat
+smp = 2
+extra_params = -append 'mp'
+groups = barrier
+accel = tcg
+
+[barrier-litmus::mp-barrier]
+file = barrier-litmus-test.flat
+smp = 2
+extra_params = -append 'mp_barrier'
+groups = barrier
+accel = tcg
+
+[barrier-litmus::mp-acqrel]
+file = barrier-litmus-test.flat
+smp = 2
+extra_params = -append 'mp_acqrel'
+groups = barrier
+accel = tcg
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index 6857261..023a0c3 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -14,6 +14,7 @@ tests-common += $(TEST_DIR)/spinlock-test.flat
 tests-common += $(TEST_DIR)/ipi-test.flat
 tests-common += $(TEST_DIR)/tlbflush-test.flat
 tests-common += $(TEST_DIR)/locking-test.flat
+tests-common += $(TEST_DIR)/barrier-litmus-test.flat
 
 all: test_cases
 
@@ -76,3 +77,4 @@ $(TEST_DIR)/spinlock-test.elf: $(cstart.o) $(TEST_DIR)/spinlock-test.o
 $(TEST_DIR)/ipi-test.elf: $(cstart.o) $(TEST_DIR)/ipi-test.o
 $(TEST_DIR)/tlbflush-test.elf: $(cstart.o) $(TEST_DIR)/tlbflush-test.o
 $(TEST_DIR)/locking-test.elf: $(cstart.o) $(TEST_DIR)/locking-test.o
+$(TEST_DIR)/barrier-litmus-test.elf: $(cstart.o) $(TEST_DIR)/barrier-litmus-test.o
diff --git a/lib/arm/asm/barrier.h b/lib/arm/asm/barrier.h
index 394a4a2..e3b7a2e 100644
--- a/lib/arm/asm/barrier.h
+++ b/lib/arm/asm/barrier.h
@@ -1,9 +1,11 @@
 #ifndef _ASMARM_BARRIER_H_
 #define _ASMARM_BARRIER_H_
 /*
- * Adapted form arch/arm/include/asm/barrier.h
+ * Adapted from arch/arm/include/asm/barrier.h
  */
 
+#include <stdint.h>
+
 #define sev()		asm volatile("sev" : : : "memory")
 #define wfe()		asm volatile("wfe" : : : "memory")
 #define wfi()		asm volatile("wfi" : : : "memory")
@@ -20,4 +22,63 @@
 #define smp_rmb()	smp_mb()
 #define smp_wmb()	dmb(ishst)
 
+extern void abort(void);
+
+static inline void __write_once_size(volatile void *p, void *res, int size)
+{
+	switch (size) {
+	case 1: *(volatile uint8_t *)p = *(uint8_t *)res; break;
+	case 2: *(volatile uint16_t *)p = *(uint16_t *)res; break;
+	case 4: *(volatile uint32_t *)p = *(uint32_t *)res; break;
+	case 8: *(volatile uint64_t *)p = *(uint64_t *)res; break;
+	default:
+		/* unhandled case */
+		abort();
+	}
+}
+
+#define WRITE_ONCE(x, val) \
+({							\
+	union { typeof(x) __val; char __c[1]; } __u =	\
+		{ .__val = (typeof(x)) (val) }; \
+	__write_once_size(&(x), __u.__c, sizeof(x));	\
+	__u.__val;					\
+})
+
+#define smp_store_release(p, v)						\
+do {									\
+	smp_mb();							\
+	WRITE_ONCE(*p, v);						\
+} while (0)
+
+
+static inline
+void __read_once_size(const volatile void *p, void *res, int size)
+{
+	switch (size) {
+	case 1: *(uint8_t *)res = *(volatile uint8_t *)p; break;
+	case 2: *(uint16_t *)res = *(volatile uint16_t *)p; break;
+	case 4: *(uint32_t *)res = *(volatile uint32_t *)p; break;
+	case 8: *(uint64_t *)res = *(volatile uint64_t *)p; break;
+	default:
+		/* unhandled case */
+		abort();
+	}
+}
+
+#define READ_ONCE(x)							\
+({									\
+	union { typeof(x) __val; char __c[1]; } __u;			\
+	__read_once_size(&(x), __u.__c, sizeof(x));			\
+	__u.__val;							\
+})
+
+
+#define smp_load_acquire(p)						\
+({									\
+	typeof(*p) ___p1 = READ_ONCE(*p);				\
+	smp_mb();							\
+	___p1;								\
+})
+
 #endif /* _ASMARM_BARRIER_H_ */
diff --git a/lib/arm64/asm/barrier.h b/lib/arm64/asm/barrier.h
index dbdac9d..aafabdc 100644
--- a/lib/arm64/asm/barrier.h
+++ b/lib/arm64/asm/barrier.h
@@ -19,4 +19,54 @@
 #define smp_rmb()	dmb(ishld)
 #define smp_wmb()	dmb(ishst)
 
+#define smp_store_release(p, v)						\
+do {									\
+	switch (sizeof(*p)) {						\
+	case 1:								\
+		asm volatile ("stlrb %w1, %0"				\
+				: "=Q" (*p) : "r" (v) : "memory");	\
+		break;							\
+	case 2:								\
+		asm volatile ("stlrh %w1, %0"				\
+				: "=Q" (*p) : "r" (v) : "memory");	\
+		break;							\
+	case 4:								\
+		asm volatile ("stlr %w1, %0"				\
+				: "=Q" (*p) : "r" (v) : "memory");	\
+		break;							\
+	case 8:								\
+		asm volatile ("stlr %1, %0"				\
+				: "=Q" (*p) : "r" (v) : "memory");	\
+		break;							\
+	}								\
+} while (0)
+
+#define smp_load_acquire(p)						\
+({									\
+	union { typeof(*p) __val; char __c[1]; } __u;			\
+	switch (sizeof(*p)) {						\
+	case 1:								\
+		asm volatile ("ldarb %w0, %1"				\
+			: "=r" (*(u8 *)__u.__c)				\
+			: "Q" (*p) : "memory");				\
+		break;							\
+	case 2:								\
+		asm volatile ("ldarh %w0, %1"				\
+			: "=r" (*(u16 *)__u.__c)			\
+			: "Q" (*p) : "memory");				\
+		break;							\
+	case 4:								\
+		asm volatile ("ldar %w0, %1"				\
+			: "=r" (*(u32 *)__u.__c)			\
+			: "Q" (*p) : "memory");				\
+		break;							\
+	case 8:								\
+		asm volatile ("ldar %0, %1"				\
+			: "=r" (*(u64 *)__u.__c)			\
+			: "Q" (*p) : "memory");				\
+		break;							\
+	}								\
+	__u.__val;							\
+})
+
 #endif /* _ASMARM64_BARRIER_H_ */
-- 
2.7.1

[Qemu-devel] [RFC 11/11] arm/tcg-test: some basic TCG exercising tests

[Alex Bennée]

These tests are not really aimed at KVM at all but exist to stretch
QEMU's TCG code generator. In particular these exercise the ability of
the TCG to:

  * Chain TranslationBlocks together (tight)
  * Handle heavy usage of the tb_jump_cache (paged)
  * Pathological case of computed local jumps (computed)

In addition the tests can be varied by adding IPI IRQs or SMC sequences
into the mix to stress the tcg_exit and invalidation mechanisms.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 arm/tcg-test-asm.S           | 170 +++++++++++++++++++++++++++++
 arm/tcg-test.c               | 248 +++++++++++++++++++++++++++++++++++++++++++
 arm/unittests.cfg            |  90 ++++++++++++++++
 config/config-arm-common.mak |   2 +
 4 files changed, 510 insertions(+)
 create mode 100644 arm/tcg-test-asm.S
 create mode 100644 arm/tcg-test.c

diff --git a/arm/tcg-test-asm.S b/arm/tcg-test-asm.S
new file mode 100644
index 0000000..6e823b7
--- /dev/null
+++ b/arm/tcg-test-asm.S
@@ -0,0 +1,170 @@
+/*
+ * TCG Test assembler functions for armv7 tests.
+ *
+ * Copyright (C) 2016, Linaro Ltd, Alex Bennée <alex.bennee@linaro.org>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ *
+ * These helper functions are written in pure asm to control the size
+ * of the basic blocks and ensure they fit neatly into page
+ * aligned chunks. The pattern of branches they follow is determined by
+ * the 32 bit seed they are passed. It should be the same for each set.
+ *
+ * Calling convention
+ *  - r0, iterations
+ *  - r1, jump pattern
+ *  - r2-r3, scratch
+ *
+ * Returns r0
+ */
+
+.arm
+
+.section .text
+
+/* Tight - all blocks should quickly be patched and should run
+ * very fast unless irqs or smc gets in the way
+ */
+
+.global tight_start
+tight_start:
+        subs    r0, r0, #1
+        beq     tight_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     tightA
+        b       tight_start
+
+tightA:
+        subs    r0, r0, #1
+        beq     tight_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     tightB
+        b       tight_start
+
+tightB:
+        subs    r0, r0, #1
+        beq     tight_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     tight_start
+        b       tightA
+
+.global tight_end
+tight_end:
+        mov     pc, lr
+
+/*
+ * Computed jumps cannot be hardwired into the basic blocks so each one
+ * will cause an exit for the main execution loop to look up the next block.
+ *
+ * There is some caching which should ameliorate the cost a little.
+ */
+
+        /* Align << 13 == 4096 byte alignment */
+        .align 13
+        .global computed_start
+computed_start:
+        subs    r0, r0, #1
+        beq     computed_end
+
+        /* Jump table */
+        ror     r1, r1, #1
+        and     r2, r1, #1
+        adr     r3, computed_jump_table
+        ldr     r2, [r3, r2, lsl #2]
+        mov     pc, r2
+
+        b       computed_err
+
+computed_jump_table:
+        .word   computed_start
+        .word   computedA
+
+computedA:
+        subs    r0, r0, #1
+        beq     computed_end
+
+        /* Jump into code */
+        ror     r1, r1, #1
+        and     r2, r1, #1
+        adr     r3, 1f
+        add	r3, r2, lsl #2
+        mov     pc, r3
+1:      b       computed_start
+        b       computedB
+
+        b       computed_err
+
+
+computedB:
+        subs    r0, r0, #1
+        beq     computed_end
+        ror     r1, r1, #1
+
+        /* Conditional register load */
+        adr     r3, computedA
+        tst     r1, #1
+        adreq   r3, computed_start
+        mov     pc, r3
+
+        b       computed_err
+
+computed_err:
+        mov     r0, #1
+        .global computed_end
+computed_end:
+        mov     pc, lr
+
+
+/*
+ * Page hoping
+ *
+ * Each block is in a different page, hence the blocks never get joined
+ */
+        /* Align << 13 == 4096 byte alignment */
+        .align 13
+        .global paged_start
+paged_start:
+        subs    r0, r0, #1
+        beq     paged_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     pagedA
+        b       paged_start
+
+        /* Align << 13 == 4096 byte alignment */
+        .align 13
+pagedA:
+        subs    r0, r0, #1
+        beq     paged_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     pagedB
+        b       paged_start
+
+        /* Align << 13 == 4096 byte alignment */
+        .align 13
+pagedB:
+        subs    r0, r0, #1
+        beq     paged_end
+
+        ror     r1, r1, #1
+        tst     r1, #1
+        beq     paged_start
+        b       pagedA
+
+        /* Align << 13 == 4096 byte alignment */
+        .align 13
+.global paged_end
+paged_end:
+        mov     pc, lr
+
+.global test_code_end
+test_code_end:
diff --git a/arm/tcg-test.c b/arm/tcg-test.c
new file mode 100644
index 0000000..6fa61ba
--- /dev/null
+++ b/arm/tcg-test.c
@@ -0,0 +1,248 @@
+/*
+ * ARM TCG Tests
+ *
+ * These tests are explicitly aimed at stretching the QEMU TCG engine.
+ */
+
+#include <libcflat.h>
+#include <asm/smp.h>
+#include <asm/cpumask.h>
+#include <asm/barrier.h>
+#include <asm/mmu.h>
+#include <asm/gic.h>
+
+#include <prng.h>
+
+#define MAX_CPUS 8
+
+/* These entry points are in the assembly code */
+extern int tight_start(uint32_t count, uint32_t pattern);
+extern int computed_start(uint32_t count, uint32_t pattern);
+extern int paged_start(uint32_t count, uint32_t pattern);
+extern uint32_t tight_end;
+extern uint32_t computed_end;
+extern uint32_t paged_end;
+extern unsigned long test_code_end;
+
+typedef int (*test_fn)(uint32_t count, uint32_t pattern);
+
+typedef struct {
+	const char *test_name;
+	bool       should_pass;
+	test_fn    start_fn;
+	uint32_t   *code_end;
+} test_descr_t;
+
+/* Test array */
+static test_descr_t tests[] = {
+       /*
+	* Tight chain.
+	*
+	* These are a bunch of basic blocks that have fixed branches in
+	* a page aligned space. The branches taken are decided by a
+	* psuedo-random bitmap for each CPU.
+	*
+	* Once the basic blocks have been chained together by the TCG they
+	* should run until they reach their block count. This will be the
+	* most efficient mode in which generated code is run. The only other
+	* exits will be caused by interrupts or TB invalidation.
+	*/
+	{ "tight", true, tight_start, &tight_end },
+	/*
+	 * Computed jumps.
+	 *
+	 * A bunch of basic blocks which just do computed jumps so the basic
+	 * block is never chained but they are all within a page (maybe not
+	 * required). This will exercise the cache lookup but not the new
+	 * generation.
+	 */
+	{ "computed", true, computed_start, &computed_end },
+        /*
+	 * Page ping pong.
+	 *
+	 * Have the blocks are separated by PAGE_SIZE so they can never
+	 * be chained together.
+	 *
+	 */
+	{ "paged", true, paged_start, &paged_end}
+};
+
+static test_descr_t *test = NULL;
+
+static int iterations = 100000;
+static int rounds = 1000;
+static int mod_freq = 5;
+static uint32_t pattern[MAX_CPUS];
+
+static int smc = 0;
+static int irq = 0;
+static int irq_cnt[MAX_CPUS];
+static int errors[MAX_CPUS];
+
+static cpumask_t smp_test_complete;
+
+
+/* This triggers TCGs SMC detection by writing values to the executing
+ * code pages. We are not actually modifying the instructions and the
+ * underlying code will remain unchanged. However this should trigger
+ * invalidation of the Translation Blocks
+ */
+
+void trigger_smc_detection(uint32_t *start, uint32_t *end)
+{
+	volatile uint32_t *ptr = start;
+	while (ptr < end) {
+		uint32_t inst = *ptr;
+		*ptr++ = inst;
+	}
+}
+
+/* Handler for receiving IRQs */
+
+static void irq_handler(struct pt_regs *regs __unused)
+{
+	int cpu = smp_processor_id();
+	irq_cnt[cpu]++;
+	gic_irq_ack();
+}
+
+/* This triggers cross-CPU IRQs. Each IRQ should cause the basic block
+ * execution to finish the main run-loop get entered again.
+ */
+int send_cross_cpu_irqs(int this_cpu)
+{
+	int cpu, sent = 0;
+
+	for_each_present_cpu(cpu) {
+		if (cpu != this_cpu) {
+			gic_send_sgi(cpu, 1);
+			sent++;
+		}
+	}
+
+	return sent;
+}
+
+
+void do_test(void)
+{
+	int cpu = smp_processor_id();
+	int i;
+	int sent_irqs = 0;
+
+	printf("CPU%d: online and setting up with pattern 0x%x\n", cpu, pattern[cpu]);
+
+	if (irq) {
+		gic_enable();
+#ifdef __arm__
+		install_exception_handler(EXCPTN_IRQ, irq_handler);
+#else
+		install_irq_handler(EL1H_IRQ, irq_handler);
+#endif
+		local_irq_enable();
+	}
+
+	for (i=0; i<rounds; i++)
+	{
+		/* Enter the blocks */
+		errors[cpu] += test->start_fn(iterations, pattern[cpu]);
+
+		if ((i + cpu) % mod_freq == 0)
+		{
+			if (smc) {
+				trigger_smc_detection((uint32_t *) test->start_fn,
+						test->code_end);
+			}
+			if (irq) {
+				sent_irqs += send_cross_cpu_irqs(cpu);
+			}
+		}
+	}
+
+	if (irq) {
+		printf("CPU%d: Done with %d irqs sent and %d received\n", cpu, sent_irqs, irq_cnt[cpu]);
+	} else {
+		printf("CPU%d: Done with %d errors\n", cpu, errors[cpu]);
+	}
+
+	cpumask_set_cpu(cpu, &smp_test_complete);
+	if (cpu != 0)
+		halt();
+}
+
+
+void setup_and_run_tcg_test(void)
+{
+	static const unsigned char seed[] = "tcg-test";
+	struct isaac_ctx prng_context;
+	int cpu;
+
+	isaac_init(&prng_context, &seed[0], sizeof(seed));
+
+	if (irq) {
+		gic_enable();
+	}
+
+	/* boot other CPUs */
+	for_each_present_cpu(cpu) {
+		pattern[cpu] = isaac_next_uint32(&prng_context);
+
+		if (cpu == 0)
+			continue;
+
+		smp_boot_secondary(cpu, do_test);
+	}
+
+	do_test();
+
+	while (!cpumask_full(&smp_test_complete))
+		cpu_relax();
+
+	/* how do we detect errors other than not crashing? */
+	report("passed", true);
+}
+
+int main(int argc, char **argv)
+{
+	int i;
+	unsigned int j;
+
+	for (i=0; i<argc; i++) {
+		char *arg = argv[i];
+
+		for (j = 0; j < ARRAY_SIZE(tests); j++) {
+			if (strcmp(arg, tests[j].test_name) == 0)
+				test = & tests[j];
+		}
+
+		/* Test modifiers */
+		if (strstr(arg, "mod=") != NULL) {
+			char *p = strstr(arg, "=");
+			mod_freq = atol(p+1);
+		}
+
+		if (strcmp(arg, "smc") == 0) {
+			unsigned long test_start = (unsigned long) &tight_start;
+			unsigned long test_end = (unsigned long) &test_code_end;
+
+			smc = 1;
+			mmu_set_range_ptes(mmu_idmap, test_start, test_start, test_end,
+					__pgprot(PTE_WBWA));
+
+			report_prefix_push("smc");
+		}
+
+		if (strcmp(arg, "irq") == 0) {
+			irq = 1;
+			report_prefix_push("irq");
+		}
+	}
+
+	if (test) {
+		setup_and_run_tcg_test();
+	} else {
+		report("Unknown test", false);
+	}
+
+	return report_summary();
+}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 3f05cfa..c00be15 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -39,6 +39,11 @@ smp = $MAX_SMP
 extra_params = -append 'smp'
 groups = selftest
 
+[irq-ipi]
+file = ipi-test.flat
+smp = 2
+group = irq
+
 # TLB Torture Tests
 [tlbflush::all_other]
 file = tlbflush-test.flat
@@ -118,3 +123,88 @@ smp = 2
 extra_params = -append 'mp_acqrel'
 groups = barrier
 accel = tcg
+
+# TCG Tests
+[tcg::tight]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'tight'
+groups = tcg
+accel = tcg
+
+[tcg::tight-smc]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'tight smc'
+groups = tcg
+accel = tcg
+
+[tcg::tight-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'tight irq'
+groups = tcg
+accel = tcg
+
+[tcg::tight-smc-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'tight smc irq'
+groups = tcg
+accel = tcg
+
+[tcg::computed]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'computed'
+groups = tcg
+accel = tcg
+
+[tcg::computed-smc]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'computed smc'
+groups = tcg
+accel = tcg
+
+[tcg::computed-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'computed irq'
+groups = tcg
+accel = tcg
+
+[tcg::computed-smc-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'computed smc irq'
+groups = tcg
+accel = tcg
+
+[tcg::paged]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'paged'
+groups = tcg
+accel = tcg
+
+[tcg::paged-smc]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'paged smc'
+groups = tcg
+accel = tcg
+
+[tcg::paged-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'paged irq'
+groups = tcg
+accel = tcg
+
+[tcg::paged-smc-irq]
+file = tcg-test.flat
+smp = $MAX_SMP
+extra_params = -append 'paged smc irq'
+groups = tcg
+accel = tcg
diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
index 023a0c3..23208b0 100644
--- a/config/config-arm-common.mak
+++ b/config/config-arm-common.mak
@@ -15,6 +15,7 @@ tests-common += $(TEST_DIR)/ipi-test.flat
 tests-common += $(TEST_DIR)/tlbflush-test.flat
 tests-common += $(TEST_DIR)/locking-test.flat
 tests-common += $(TEST_DIR)/barrier-litmus-test.flat
+tests-common += $(TEST_DIR)/tcg-test.flat
 
 all: test_cases
 
@@ -78,3 +79,4 @@ $(TEST_DIR)/ipi-test.elf: $(cstart.o) $(TEST_DIR)/ipi-test.o
 $(TEST_DIR)/tlbflush-test.elf: $(cstart.o) $(TEST_DIR)/tlbflush-test.o
 $(TEST_DIR)/locking-test.elf: $(cstart.o) $(TEST_DIR)/locking-test.o
 $(TEST_DIR)/barrier-litmus-test.elf: $(cstart.o) $(TEST_DIR)/barrier-litmus-test.o
+$(TEST_DIR)/tcg-test.elf: $(cstart.o) $(TEST_DIR)/tcg-test.o $(TEST_DIR)/tcg-test-asm.o
-- 
2.7.1

Re: [Qemu-devel] [RFC 07/11] arm/run: allow aarch64 to start arm binaries

[Andrew Jones]

On Fri, Feb 26, 2016 at 01:15:29PM +0000, Alex Bennée wrote:
> AArch64 hosts can happily run AArch32 binaries. We just need to ensure
> that we use "cpu host,aarch64=off" when specifying the CPU type.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  arm/run | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arm/run b/arm/run
> index 0eaf23a..f1a6b7d 100755
> --- a/arm/run
> +++ b/arm/run
> @@ -38,7 +38,15 @@ if [ "$HOST" = "aarch64" ] && [ "$ACCEL" = "kvm" ]; then
>  	fi
>  fi
>  
> -qemu="${QEMU:-qemu-system-$ARCH_NAME}"
> +if [ "$ARCH" = "arm" ] && [ "$HOST" = "aarch64" ]; then
> +    qemu="${QEMU:-qemu-system-$HOST}"
> +    if [ "$ACCEL" = "kvm" ]; then
> +	processor="host,aarch64=off"
> +    fi
> +else
> +	qemu="${QEMU:-qemu-system-$ARCH_NAME}"
> +fi

We've got 3382e7795 "arm/run: allow tests to run in AArch32 mode"
already, so I this patch should no longer be necessary.

Thanks,
drew


> +
>  qpath=$(which $qemu 2>/dev/null)
>  
>  if [ -z "$qpath" ]; then
> -- 
> 2.7.1
> 

Re: [Qemu-devel] [RFC 01/11] config/config-arm-common: build-up tests-common target

[Andrew Jones]

On Fri, Feb 26, 2016 at 01:15:23PM +0000, Alex Bennée wrote:
> This is a source of needless conflicts when adding new tests and
> re-basing. Let's just build up the lists of tests by hand.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  config/config-arm-common.mak | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
> index 698555d..e037507 100644
> --- a/config/config-arm-common.mak
> +++ b/config/config-arm-common.mak
> @@ -9,9 +9,8 @@ ifeq ($(LOADADDR),)
>  	LOADADDR = 0x40000000
>  endif
>  
> -tests-common = \
> -	$(TEST_DIR)/selftest.flat \
> -	$(TEST_DIR)/spinlock-test.flat
> +tests-common = $(TEST_DIR)/selftest.flat
> +tests-common += $(TEST_DIR)/spinlock-test.flat
>  
>  all: test_cases
>  
> -- 
> 2.7.1
> 
>

I agree with this patch, but we could probably just squash it
with the addition of the next test.

drew

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Andrew Jones]

On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
> Hi,
> 
> Some of these patches have been posted before and previous patches
> have already been accepted upstream so I'm tagging this as a new RFC
> series.
> 
> This is a series of tests built around kvm-unit-tests but built with
> the express purpose of stressing the TCG, in particular MTTCG builds.
> 
> Changes from previous appearances:
> 
>  * Separated locking and barrier tests
>  * Included Drew's IPI patches (used in tcg-test)
>  * New TCG chaining test
> 
> The new barrier tests really only fails when running on MTTCG builds on
> a weak backend. Many thanks to Will Deacon for helping me get a
> working test case at the last Connect.
> 
> I'm mainly posting these for reference for others testing MTTCG as
> I've still got to check I've addressed any outstanding review
> comments. However there has been enough code churn some of the
> comments may no longer be relevant.
> 
> The TCG tests are also useful as benchmarks for comparing the cost of
> having chained basic blocks versus exiting the loop every time. The
> pathological case is the computed jumps test as all the addresses are
> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
> full look up each time.
> 
> Alex Bennée (8):
>   config/config-arm-common: build-up tests-common target
>   lib: add isaac prng library from CCAN
>   arm/run: set indentation defaults for emacs
>   arm/run: allow aarch64 to start arm binaries
>   arm/tlbflush-test: Add TLB torture test
>   arm/locking-tests: add comprehensive locking test
>   arm/barrier-litmus-tests: add some litmus tests
>   arm/tcg-test: some basic TCG exercising tests
> 
> Andrew Jones (3):
>   arm/arm64: irq enable/disable
>   arm/arm64: Add initial gic support
>   arm/arm64: Add IPI test

I've actually updated these patches a bit, and started extending the
series to also work with a v3 gic. I'll pick that back up and get it
posted for you (hopefully next week). Or I'll at least update my
arm/ipi-test branch with the changes I've made for gicv2...

drew

Re: [Qemu-devel] [RFC 01/11] config/config-arm-common: build-up tests-common target

[Alex Bennée]

Andrew Jones <drjones@redhat.com> writes:

> On Fri, Feb 26, 2016 at 01:15:23PM +0000, Alex Bennée wrote:
>> This is a source of needless conflicts when adding new tests and
>> re-basing. Let's just build up the lists of tests by hand.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>>  config/config-arm-common.mak | 5 ++---
>>  1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/config/config-arm-common.mak b/config/config-arm-common.mak
>> index 698555d..e037507 100644
>> --- a/config/config-arm-common.mak
>> +++ b/config/config-arm-common.mak
>> @@ -9,9 +9,8 @@ ifeq ($(LOADADDR),)
>>  	LOADADDR = 0x40000000
>>  endif
>>
>> -tests-common = \
>> -	$(TEST_DIR)/selftest.flat \
>> -	$(TEST_DIR)/spinlock-test.flat
>> +tests-common = $(TEST_DIR)/selftest.flat
>> +tests-common += $(TEST_DIR)/spinlock-test.flat
>>
>>  all: test_cases
>>
>> --
>> 2.7.1
>>
>>
>
> I agree with this patch, but we could probably just squash it
> with the addition of the next test.

It was originally but during yet-another-rebase I thought I'd just
separate the patch so it wasn't dependant on what was merged next!

>
> drew


--
Alex Bennée

Re: [Qemu-devel] [RFC 07/11] arm/run: allow aarch64 to start arm binaries

[Alex Bennée]

Andrew Jones <drjones@redhat.com> writes:

> On Fri, Feb 26, 2016 at 01:15:29PM +0000, Alex Bennée wrote:
>> AArch64 hosts can happily run AArch32 binaries. We just need to ensure
>> that we use "cpu host,aarch64=off" when specifying the CPU type.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>>  arm/run | 10 +++++++++-
>>  1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/arm/run b/arm/run
>> index 0eaf23a..f1a6b7d 100755
>> --- a/arm/run
>> +++ b/arm/run
>> @@ -38,7 +38,15 @@ if [ "$HOST" = "aarch64" ] && [ "$ACCEL" = "kvm" ]; then
>>  	fi
>>  fi
>>
>> -qemu="${QEMU:-qemu-system-$ARCH_NAME}"
>> +if [ "$ARCH" = "arm" ] && [ "$HOST" = "aarch64" ]; then
>> +    qemu="${QEMU:-qemu-system-$HOST}"
>> +    if [ "$ACCEL" = "kvm" ]; then
>> +	processor="host,aarch64=off"
>> +    fi
>> +else
>> +	qemu="${QEMU:-qemu-system-$ARCH_NAME}"
>> +fi
>
> We've got 3382e7795 "arm/run: allow tests to run in AArch32 mode"
> already, so I this patch should no longer be necessary.

Ahh good spot. I'll drop that.

Thanks.

>
> Thanks,
> drew
>
>
>> +
>>  qpath=$(which $qemu 2>/dev/null)
>>
>>  if [ -z "$qpath" ]; then
>> --
>> 2.7.1
>>


--
Alex Bennée

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Alex Bennée]

Andrew Jones <drjones@redhat.com> writes:

> On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
>> Hi,
>>
>> Some of these patches have been posted before and previous patches
>> have already been accepted upstream so I'm tagging this as a new RFC
>> series.
>>
>> This is a series of tests built around kvm-unit-tests but built with
>> the express purpose of stressing the TCG, in particular MTTCG builds.
>>
>> Changes from previous appearances:
>>
>>  * Separated locking and barrier tests
>>  * Included Drew's IPI patches (used in tcg-test)
>>  * New TCG chaining test
>>
>> The new barrier tests really only fails when running on MTTCG builds on
>> a weak backend. Many thanks to Will Deacon for helping me get a
>> working test case at the last Connect.
>>
>> I'm mainly posting these for reference for others testing MTTCG as
>> I've still got to check I've addressed any outstanding review
>> comments. However there has been enough code churn some of the
>> comments may no longer be relevant.
>>
>> The TCG tests are also useful as benchmarks for comparing the cost of
>> having chained basic blocks versus exiting the loop every time. The
>> pathological case is the computed jumps test as all the addresses are
>> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
>> full look up each time.
>>
>> Alex Bennée (8):
>>   config/config-arm-common: build-up tests-common target
>>   lib: add isaac prng library from CCAN
>>   arm/run: set indentation defaults for emacs
>>   arm/run: allow aarch64 to start arm binaries
>>   arm/tlbflush-test: Add TLB torture test
>>   arm/locking-tests: add comprehensive locking test
>>   arm/barrier-litmus-tests: add some litmus tests
>>   arm/tcg-test: some basic TCG exercising tests
>>
>> Andrew Jones (3):
>>   arm/arm64: irq enable/disable
>>   arm/arm64: Add initial gic support
>>   arm/arm64: Add IPI test
>
> I've actually updated these patches a bit, and started extending the
> series to also work with a v3 gic. I'll pick that back up and get it
> posted for you (hopefully next week). Or I'll at least update my
> arm/ipi-test branch with the changes I've made for gicv2...

Cool.

One thing I noticed was a slight disparity between the number of IPI
IRQs sent and the number received. However I'm assuming this could well
be without any explicit synchronisation a second IPI can get swallowed
up if the first hasn't been acknowledged yet.

Is there any sane/safe way for gic_send_sgi to know if the IRQ was
pending when it flips the bit?

>
> drew


--
Alex Bennée

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Andrew Jones]

On Fri, Feb 26, 2016 at 02:54:33PM +0000, Alex Bennée wrote:
> 
> Andrew Jones <drjones@redhat.com> writes:
> 
> > On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
> >> Hi,
> >>
> >> Some of these patches have been posted before and previous patches
> >> have already been accepted upstream so I'm tagging this as a new RFC
> >> series.
> >>
> >> This is a series of tests built around kvm-unit-tests but built with
> >> the express purpose of stressing the TCG, in particular MTTCG builds.
> >>
> >> Changes from previous appearances:
> >>
> >>  * Separated locking and barrier tests
> >>  * Included Drew's IPI patches (used in tcg-test)
> >>  * New TCG chaining test
> >>
> >> The new barrier tests really only fails when running on MTTCG builds on
> >> a weak backend. Many thanks to Will Deacon for helping me get a
> >> working test case at the last Connect.
> >>
> >> I'm mainly posting these for reference for others testing MTTCG as
> >> I've still got to check I've addressed any outstanding review
> >> comments. However there has been enough code churn some of the
> >> comments may no longer be relevant.
> >>
> >> The TCG tests are also useful as benchmarks for comparing the cost of
> >> having chained basic blocks versus exiting the loop every time. The
> >> pathological case is the computed jumps test as all the addresses are
> >> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
> >> full look up each time.
> >>
> >> Alex Bennée (8):
> >>   config/config-arm-common: build-up tests-common target
> >>   lib: add isaac prng library from CCAN
> >>   arm/run: set indentation defaults for emacs
> >>   arm/run: allow aarch64 to start arm binaries
> >>   arm/tlbflush-test: Add TLB torture test
> >>   arm/locking-tests: add comprehensive locking test
> >>   arm/barrier-litmus-tests: add some litmus tests
> >>   arm/tcg-test: some basic TCG exercising tests
> >>
> >> Andrew Jones (3):
> >>   arm/arm64: irq enable/disable
> >>   arm/arm64: Add initial gic support
> >>   arm/arm64: Add IPI test
> >
> > I've actually updated these patches a bit, and started extending the
> > series to also work with a v3 gic. I'll pick that back up and get it
> > posted for you (hopefully next week). Or I'll at least update my
> > arm/ipi-test branch with the changes I've made for gicv2...
> 
> Cool.
> 
> One thing I noticed was a slight disparity between the number of IPI
> IRQs sent and the number received. However I'm assuming this could well
> be without any explicit synchronisation a second IPI can get swallowed
> up if the first hasn't been acknowledged yet.

Hmm, this version of the test only sends/receives a single IPI, so
it should always be one/one. Or, are you watching the interrupts
somewhere else, and seeing more generated?

> 
> Is there any sane/safe way for gic_send_sgi to know if the IRQ was
> pending when it flips the bit?

The new version wraps the acking in an if (iar != GICC_INT_SPURIOUS)
condition (I ripped that off of Marc's assembler version). That may
"fix" things for you, but then the question is why do you see spurious
interrupts? I'll add code that counts spurious interrupts too.

Thanks,
drew

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Alex Bennée]

Andrew Jones <drjones@redhat.com> writes:

> On Fri, Feb 26, 2016 at 02:54:33PM +0000, Alex Bennée wrote:
>>
>> Andrew Jones <drjones@redhat.com> writes:
>>
>> > On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
>> >> Hi,
>> >>
>> >> Some of these patches have been posted before and previous patches
>> >> have already been accepted upstream so I'm tagging this as a new RFC
>> >> series.
>> >>
>> >> This is a series of tests built around kvm-unit-tests but built with
>> >> the express purpose of stressing the TCG, in particular MTTCG builds.
>> >>
>> >> Changes from previous appearances:
>> >>
>> >>  * Separated locking and barrier tests
>> >>  * Included Drew's IPI patches (used in tcg-test)
>> >>  * New TCG chaining test
>> >>
>> >> The new barrier tests really only fails when running on MTTCG builds on
>> >> a weak backend. Many thanks to Will Deacon for helping me get a
>> >> working test case at the last Connect.
>> >>
>> >> I'm mainly posting these for reference for others testing MTTCG as
>> >> I've still got to check I've addressed any outstanding review
>> >> comments. However there has been enough code churn some of the
>> >> comments may no longer be relevant.
>> >>
>> >> The TCG tests are also useful as benchmarks for comparing the cost of
>> >> having chained basic blocks versus exiting the loop every time. The
>> >> pathological case is the computed jumps test as all the addresses are
>> >> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
>> >> full look up each time.
>> >>
>> >> Alex Bennée (8):
>> >>   config/config-arm-common: build-up tests-common target
>> >>   lib: add isaac prng library from CCAN
>> >>   arm/run: set indentation defaults for emacs
>> >>   arm/run: allow aarch64 to start arm binaries
>> >>   arm/tlbflush-test: Add TLB torture test
>> >>   arm/locking-tests: add comprehensive locking test
>> >>   arm/barrier-litmus-tests: add some litmus tests
>> >>   arm/tcg-test: some basic TCG exercising tests
>> >>
>> >> Andrew Jones (3):
>> >>   arm/arm64: irq enable/disable
>> >>   arm/arm64: Add initial gic support
>> >>   arm/arm64: Add IPI test
>> >
>> > I've actually updated these patches a bit, and started extending the
>> > series to also work with a v3 gic. I'll pick that back up and get it
>> > posted for you (hopefully next week). Or I'll at least update my
>> > arm/ipi-test branch with the changes I've made for gicv2...
>>
>> Cool.
>>
>> One thing I noticed was a slight disparity between the number of IPI
>> IRQs sent and the number received. However I'm assuming this could well
>> be without any explicit synchronisation a second IPI can get swallowed
>> up if the first hasn't been acknowledged yet.
>
> Hmm, this version of the test only sends/receives a single IPI, so
> it should always be one/one. Or, are you watching the interrupts
> somewhere else, and seeing more generated?

Sorry I should have been clear. In my tcg-test with the "irq" modifier
which sends an IRQ to every CPU every n-iterations.

>> Is there any sane/safe way for gic_send_sgi to know if the IRQ was
>> pending when it flips the bit?
>
> The new version wraps the acking in an if (iar != GICC_INT_SPURIOUS)
> condition (I ripped that off of Marc's assembler version). That may
> "fix" things for you, but then the question is why do you see spurious
> interrupts? I'll add code that counts spurious interrupts too.

Not spurious, less received than sent. I'll double check the code and
make sure I count them up right.

>
> Thanks,
> drew


--
Alex Bennée

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Alex Bennée]

Andrew Jones <drjones@redhat.com> writes:

> On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
>> Hi,
>>
>> Some of these patches have been posted before and previous patches
>> have already been accepted upstream so I'm tagging this as a new RFC
>> series.
>>
>> This is a series of tests built around kvm-unit-tests but built with
>> the express purpose of stressing the TCG, in particular MTTCG builds.
>>
>> Changes from previous appearances:
>>
>>  * Separated locking and barrier tests
>>  * Included Drew's IPI patches (used in tcg-test)
>>  * New TCG chaining test
>>
>> The new barrier tests really only fails when running on MTTCG builds on
>> a weak backend. Many thanks to Will Deacon for helping me get a
>> working test case at the last Connect.
>>
>> I'm mainly posting these for reference for others testing MTTCG as
>> I've still got to check I've addressed any outstanding review
>> comments. However there has been enough code churn some of the
>> comments may no longer be relevant.
>>
>> The TCG tests are also useful as benchmarks for comparing the cost of
>> having chained basic blocks versus exiting the loop every time. The
>> pathological case is the computed jumps test as all the addresses are
>> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
>> full look up each time.
>>
>> Alex Bennée (8):
>>   config/config-arm-common: build-up tests-common target
>>   lib: add isaac prng library from CCAN
>>   arm/run: set indentation defaults for emacs
>>   arm/run: allow aarch64 to start arm binaries
>>   arm/tlbflush-test: Add TLB torture test
>>   arm/locking-tests: add comprehensive locking test
>>   arm/barrier-litmus-tests: add some litmus tests
>>   arm/tcg-test: some basic TCG exercising tests
>>
>> Andrew Jones (3):
>>   arm/arm64: irq enable/disable
>>   arm/arm64: Add initial gic support
>>   arm/arm64: Add IPI test
>
> I've actually updated these patches a bit, and started extending the
> series to also work with a v3 gic. I'll pick that back up and get it
> posted for you (hopefully next week). Or I'll at least update my
> arm/ipi-test branch with the changes I've made for gicv2...

I'm getting ready to post the current iteration and I realised I hadn't
seen your updates. Have they gone public anywhere?

>
> drew


--
Alex Bennée

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Andrew Jones]

On Wed, Apr 27, 2016 at 04:09:00PM +0100, Alex Bennée wrote:
> 
> Andrew Jones <drjones@redhat.com> writes:
> 
> > On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
> >> Hi,
> >>
> >> Some of these patches have been posted before and previous patches
> >> have already been accepted upstream so I'm tagging this as a new RFC
> >> series.
> >>
> >> This is a series of tests built around kvm-unit-tests but built with
> >> the express purpose of stressing the TCG, in particular MTTCG builds.
> >>
> >> Changes from previous appearances:
> >>
> >>  * Separated locking and barrier tests
> >>  * Included Drew's IPI patches (used in tcg-test)
> >>  * New TCG chaining test
> >>
> >> The new barrier tests really only fails when running on MTTCG builds on
> >> a weak backend. Many thanks to Will Deacon for helping me get a
> >> working test case at the last Connect.
> >>
> >> I'm mainly posting these for reference for others testing MTTCG as
> >> I've still got to check I've addressed any outstanding review
> >> comments. However there has been enough code churn some of the
> >> comments may no longer be relevant.
> >>
> >> The TCG tests are also useful as benchmarks for comparing the cost of
> >> having chained basic blocks versus exiting the loop every time. The
> >> pathological case is the computed jumps test as all the addresses are
> >> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
> >> full look up each time.
> >>
> >> Alex Bennée (8):
> >>   config/config-arm-common: build-up tests-common target
> >>   lib: add isaac prng library from CCAN
> >>   arm/run: set indentation defaults for emacs
> >>   arm/run: allow aarch64 to start arm binaries
> >>   arm/tlbflush-test: Add TLB torture test
> >>   arm/locking-tests: add comprehensive locking test
> >>   arm/barrier-litmus-tests: add some litmus tests
> >>   arm/tcg-test: some basic TCG exercising tests
> >>
> >> Andrew Jones (3):
> >>   arm/arm64: irq enable/disable
> >>   arm/arm64: Add initial gic support
> >>   arm/arm64: Add IPI test
> >
> > I've actually updated these patches a bit, and started extending the
> > series to also work with a v3 gic. I'll pick that back up and get it
> > posted for you (hopefully next week). Or I'll at least update my
> > arm/ipi-test branch with the changes I've made for gicv2...
> 
> I'm getting ready to post the current iteration and I realised I hadn't
> seen your updates. Have they gone public anywhere?

Sorry. I didn't finish polishing the gicv3 stuff so didn't end up
sending anything. I'll send something tomorrow (same story as last time,
if not gicv3 stuff, at least updated gicv2 :-)

Thanks,
drew

Re: [Qemu-devel] [RFC 00/11] Current MTTCG kvm-unit-test patches

[Andrew Jones]

On Wed, Apr 27, 2016 at 05:26:16PM +0200, Andrew Jones wrote:
> On Wed, Apr 27, 2016 at 04:09:00PM +0100, Alex Bennée wrote:
> > 
> > Andrew Jones <drjones@redhat.com> writes:
> > 
> > > On Fri, Feb 26, 2016 at 01:15:22PM +0000, Alex Bennée wrote:
> > >> Hi,
> > >>
> > >> Some of these patches have been posted before and previous patches
> > >> have already been accepted upstream so I'm tagging this as a new RFC
> > >> series.
> > >>
> > >> This is a series of tests built around kvm-unit-tests but built with
> > >> the express purpose of stressing the TCG, in particular MTTCG builds.
> > >>
> > >> Changes from previous appearances:
> > >>
> > >>  * Separated locking and barrier tests
> > >>  * Included Drew's IPI patches (used in tcg-test)
> > >>  * New TCG chaining test
> > >>
> > >> The new barrier tests really only fails when running on MTTCG builds on
> > >> a weak backend. Many thanks to Will Deacon for helping me get a
> > >> working test case at the last Connect.
> > >>
> > >> I'm mainly posting these for reference for others testing MTTCG as
> > >> I've still got to check I've addressed any outstanding review
> > >> comments. However there has been enough code churn some of the
> > >> comments may no longer be relevant.
> > >>
> > >> The TCG tests are also useful as benchmarks for comparing the cost of
> > >> having chained basic blocks versus exiting the loop every time. The
> > >> pathological case is the computed jumps test as all the addresses are
> > >> within a PAGE_SIZE boundary the tb_jump_cache has no effect meaning a
> > >> full look up each time.
> > >>
> > >> Alex Bennée (8):
> > >>   config/config-arm-common: build-up tests-common target
> > >>   lib: add isaac prng library from CCAN
> > >>   arm/run: set indentation defaults for emacs
> > >>   arm/run: allow aarch64 to start arm binaries
> > >>   arm/tlbflush-test: Add TLB torture test
> > >>   arm/locking-tests: add comprehensive locking test
> > >>   arm/barrier-litmus-tests: add some litmus tests
> > >>   arm/tcg-test: some basic TCG exercising tests
> > >>
> > >> Andrew Jones (3):
> > >>   arm/arm64: irq enable/disable
> > >>   arm/arm64: Add initial gic support
> > >>   arm/arm64: Add IPI test
> > >
> > > I've actually updated these patches a bit, and started extending the
> > > series to also work with a v3 gic. I'll pick that back up and get it
> > > posted for you (hopefully next week). Or I'll at least update my
> > > arm/ipi-test branch with the changes I've made for gicv2...
> > 
> > I'm getting ready to post the current iteration and I realised I hadn't
> > seen your updates. Have they gone public anywhere?
> 
> Sorry. I didn't finish polishing the gicv3 stuff so didn't end up
> sending anything. I'll send something tomorrow (same story as last time,
> if not gicv3 stuff, at least updated gicv2 :-)

I didn't find enough time to play with gicv3 today, but I considered
it in the framework (added some stub functions). New branch is here[*].
I hope to add the gicv3 functionality and post soon.

[*] https://github.com/rhdrjones/kvm-unit-tests/commits/arm/ipi-test-new

Thanks,
drew