From: Lee Jones <lee.jones@linaro.org>
To: Christoph Fritz <chf.fritz@googlemail.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Fabio Estevam <fabio.estevam@nxp.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/2] MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
Date: Tue, 8 Mar 2016 11:32:53 +0700 [thread overview]
Message-ID: <20160308043253.GH13692@x1> (raw)
In-Reply-To: <1456411669-4699-2-git-send-email-chf.fritz@googlemail.com>
On Thu, 25 Feb 2016, Christoph Fritz wrote:
> This patch adds macros to define masks and bits for imx6sx
> PCIe registers. This is based on a patch by Richard Zhu.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 5 +++++
> 1 file changed, 5 insertions(+)
I will change the non-conformant $SUBJECT line for you this time, but
please be more vigilant in the future.
Patch applied.
> diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> index 558a485..238c8db 100644
> --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> @@ -422,6 +422,7 @@
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26)
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26)
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26)
> +#define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
> @@ -435,6 +436,10 @@
> #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
> #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
>
> +#define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30)
> +#define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0)
> +#define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0)
> +
> /* For imx6ul iomux gpr register field define */
> #define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
> #define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
WARNING: multiple messages have this Message-ID (diff)
From: lee.jones@linaro.org (Lee Jones)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/2] MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
Date: Tue, 8 Mar 2016 11:32:53 +0700 [thread overview]
Message-ID: <20160308043253.GH13692@x1> (raw)
In-Reply-To: <1456411669-4699-2-git-send-email-chf.fritz@googlemail.com>
On Thu, 25 Feb 2016, Christoph Fritz wrote:
> This patch adds macros to define masks and bits for imx6sx
> PCIe registers. This is based on a patch by Richard Zhu.
>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> ---
> include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 5 +++++
> 1 file changed, 5 insertions(+)
I will change the non-conformant $SUBJECT line for you this time, but
please be more vigilant in the future.
Patch applied.
> diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> index 558a485..238c8db 100644
> --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> @@ -422,6 +422,7 @@
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26)
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26)
> #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26)
> +#define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
> #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
> @@ -435,6 +436,10 @@
> #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
> #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
>
> +#define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30)
> +#define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0)
> +#define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0)
> +
> /* For imx6ul iomux gpr register field define */
> #define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
> #define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2016-03-08 4:32 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-25 14:47 [PATCH v3 0/2] Add PCIe driver support for imx6sx Christoph Fritz
2016-02-25 14:47 ` Christoph Fritz
2016-02-25 14:47 ` [PATCH v3 1/2] MFD: imx6sx: Add PCIe register definitions for iomuxc gpr Christoph Fritz
2016-02-25 14:47 ` Christoph Fritz
2016-03-08 4:32 ` Lee Jones [this message]
2016-03-08 4:32 ` Lee Jones
2016-02-25 14:47 ` [PATCH v3 2/2] PCI: imx6: add initial imx6sx support Christoph Fritz
2016-02-25 14:47 ` Christoph Fritz
2016-03-11 17:58 ` Bjorn Helgaas
2016-03-11 17:58 ` Bjorn Helgaas
2016-03-13 23:26 ` Christoph Fritz
2016-03-13 23:26 ` Christoph Fritz
2016-03-13 23:30 ` PCI: imx6: Factor out ref clock enable Christoph Fritz
2016-03-20 7:29 ` Christoph Fritz
2016-03-20 7:29 ` Christoph Fritz
2016-04-05 21:56 ` Bjorn Helgaas
2016-04-05 21:56 ` Bjorn Helgaas
2016-03-13 23:31 ` [PATCH v4] PCI: imx6: Add initial imx6sx support Christoph Fritz
2016-03-13 23:31 ` Christoph Fritz
2016-03-20 7:30 ` Christoph Fritz
2016-03-20 7:30 ` Christoph Fritz
2016-04-05 21:56 ` Bjorn Helgaas
2016-04-05 21:56 ` Bjorn Helgaas
2016-03-03 1:41 ` [PATCH v3 0/2] Add PCIe driver support for imx6sx Christoph Fritz
2016-03-03 1:41 ` Christoph Fritz
2016-03-03 1:46 ` Richard Zhu
2016-03-03 1:46 ` Richard Zhu
2016-03-03 1:48 ` Richard Zhu
2016-03-03 1:48 ` Richard Zhu
2016-03-07 8:20 ` Christoph Fritz
2016-03-07 8:20 ` Christoph Fritz
2016-03-09 15:39 ` Christoph Fritz
2016-03-09 15:39 ` Christoph Fritz
2016-03-09 15:53 ` Lucas Stach
2016-03-09 15:53 ` Lucas Stach
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