[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

[Lokesh Vutla]

This series fixes miscellaneous bugs for the emif driver. 

Lokesh Vutla (4):
  ARM: DRA7: emif: Fix updating of refresh ctrl shadow
  ARM: DRA7: emif: Fix DDR init sequence during warm reset
  ARM: DRA7: emif: Check for enable bits before updating leveling output
  ARM: DRA7: emif: Enable interleaving for higher address space

 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
 arch/arm/include/asm/emif.h                  |  9 +++++
 3 files changed, 67 insertions(+), 26 deletions(-)

-- 
2.1.4

[U-Boot] [PATCH 1/4] ARM: DRA7: emif: Fix updating of refresh ctrl shadow

[Lokesh Vutla]

On DRA7, refresh ctrl shadow should be updated with
the final value.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index bf7bf26..90c241a 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -163,7 +163,11 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	if (!is_dra7xx())
+		writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	else
+		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
+
 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
-- 
2.1.4

[U-Boot] [PATCH 2/4] ARM: DRA7: emif: Fix DDR init sequence during warm reset

[Lokesh Vutla]

Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 90c241a..6b33b45 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -327,8 +327,10 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	if (warm_reset())
+	if (warm_reset()) {
 		emif_reset_phy(base);
+		writel(0x0, &emif->emif_pwr_mgmt_ctrl);
+	}
 	do_ext_phy_settings(base, regs);
 
 	writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
-- 
2.1.4

[U-Boot] [PATCH 3/4] ARM: DRA7: emif: Check for enable bits before updating leveling output

[Lokesh Vutla]

Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 38 ++++++++++++++++------------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 +++++++++++++++++++------
 arch/arm/include/asm/emif.h                  |  6 +++++
 3 files changed, 54 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 6b33b45..3673884 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -250,33 +250,39 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
-	u32 reg, i;
+	u32 reg, i, phy;
 
 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+	phy = readl(&emif->emif_ddr_phy_ctrl_1);
 
 	/* Update PHY_REG_RDDQS_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
-	for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+		for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
-	for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+		for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
-	for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+		for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Disable Leveling */
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index a8d63c2..c386e64 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -643,11 +643,12 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 	u32 *emif_ext_phy_ctrl_base = 0;
 	u32 emif_nr;
 	const u32 *ext_phy_ctrl_const_regs;
-	u32 i, hw_leveling, size;
+	u32 i, hw_leveling, size, phy;
 
 	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
 	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+	phy = regs->emif_ddr_phy_ctlr_1_init;
 
 	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 
@@ -657,18 +658,35 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 
-	if (!hw_leveling) {
-		/*
-		 * Copy the predefined PHY register values
-		 * in case of sw leveling
-		 */
-		for (i = 1; i < 25; i++) {
+	/*
+	 * Copy the predefined PHY register values
+	 * if leveling is disabled.
+	 */
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
+		for (i = 1; i < 6; i++) {
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2]);
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
 		}
-	} else {
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
+		for (i = 6; i < 11; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
+		for (i = 11; i < 25; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (hw_leveling) {
 		/*
 		 * Write the init value for HW levling to occur
 		 */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 7986e6e..b03cf5a 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -478,6 +478,12 @@
 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT		25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK		(1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT	26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK		(1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT		27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK		(1 << 27)
 
 /* DDR_PHY_CTRL_2 */
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0
-- 
2.1.4

[U-Boot] [PATCH 4/4] ARM: DRA7: emif: Enable interleaving for higher address space

[Lokesh Vutla]

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 2 ++
 arch/arm/include/asm/emif.h                  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 3673884..697d6e0 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1329,6 +1329,8 @@ void dmm_init(u32 base)
 			&hw_lisa_map_regs->dmm_lisa_map_1);
 		writel(lisa_map_regs->dmm_lisa_map_0,
 			&hw_lisa_map_regs->dmm_lisa_map_0);
+
+		setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
 	}
 
 	/*
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b03cf5a..3183130 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -545,6 +545,9 @@
 
 /* Memory Adapter */
 #define MA_BASE				0x482AF040
+#define MA_PRIORITY			0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT	8
+#define MA_HIMEM_INTERLEAVE_UN_MASK	(1 << 8)
 
 /* DMM_LISA_MAP */
 #define EMIF_SYS_ADDR_SHIFT		24
-- 
2.1.4

[U-Boot] [PATCH 1/4] ARM: DRA7: emif: Fix updating of refresh ctrl shadow

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:28PM +0530, Lokesh Vutla wrote:

> On DRA7, refresh ctrl shadow should be updated with
> the final value.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 2/4] ARM: DRA7: emif: Fix DDR init sequence during warm reset

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:29PM +0530, Lokesh Vutla wrote:

> Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
> enables Self refresh mode by default and during warm reset the EMIF
> contents are preserved. After warm reset EMIF sees that it is idle and
> puts DDR in self-refresh. When in SR, leveling operations cannot be done
> as DDR can only accept SR exit command, so its hanging during warm reset.
> In order to fix this reset the power management control register before
> EMIF initialization if it is a warm reset.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 3/4] ARM: DRA7: emif: Check for enable bits before updating leveling output

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:30PM +0530, Lokesh Vutla wrote:

> Read and write leveling can be enabled independently. Check for these
> enable bits before updating the read and write leveling output values.
> This will allow to use the combination of software and hardware leveling.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 4/4] ARM: DRA7: emif: Enable interleaving for higher address space

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:31PM +0530, Lokesh Vutla wrote:

> Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
> enable interleaving for this higher memory to increase performance.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:27PM +0530, Lokesh Vutla wrote:

> This series fixes miscellaneous bugs for the emif driver. 
> 
> Lokesh Vutla (4):
>   ARM: DRA7: emif: Fix updating of refresh ctrl shadow
>   ARM: DRA7: emif: Fix DDR init sequence during warm reset
>   ARM: DRA7: emif: Check for enable bits before updating leveling output
>   ARM: DRA7: emif: Enable interleaving for higher address space
> 
>  arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
>  arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
>  arch/arm/include/asm/emif.h                  |  9 +++++
>  3 files changed, 67 insertions(+), 26 deletions(-)

Note that my board is still unable to boot from mainline with these
applied but still works with the TI vendor tree.

-- 
Tom
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[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

[Lokesh Vutla]

On Tuesday 08 March 2016 05:06 AM, Tom Rini wrote:
> On Sat, Mar 05, 2016 at 05:32:27PM +0530, Lokesh Vutla wrote:
> 
>> This series fixes miscellaneous bugs for the emif driver. 
>>
>> Lokesh Vutla (4):
>>   ARM: DRA7: emif: Fix updating of refresh ctrl shadow
>>   ARM: DRA7: emif: Fix DDR init sequence during warm reset
>>   ARM: DRA7: emif: Check for enable bits before updating leveling output
>>   ARM: DRA7: emif: Enable interleaving for higher address space
>>
>>  arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
>>  arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
>>  arch/arm/include/asm/emif.h                  |  9 +++++
>>  3 files changed, 67 insertions(+), 26 deletions(-)
> 
> Note that my board is still unable to boot from mainline with these
> applied but still works with the TI vendor tree.

Hmm..I guess you are talking about DRA72-evm. SPL even doesn't come up
or U-boot is failing. Can I see the logs? And what switch settings are
you using?(Ill try to reproduce in my place)

Thanks and regards,
Lokesh

> 

[U-Boot] [PATCH 0/4] ARM: DRA7: emif: Miscellaneous bug fixes

[Tom Rini]

On Tue, Mar 08, 2016 at 09:07:28AM +0530, Lokesh Vutla wrote:
> On Tuesday 08 March 2016 05:06 AM, Tom Rini wrote:
> > On Sat, Mar 05, 2016 at 05:32:27PM +0530, Lokesh Vutla wrote:
> > 
> >> This series fixes miscellaneous bugs for the emif driver. 
> >>
> >> Lokesh Vutla (4):
> >>   ARM: DRA7: emif: Fix updating of refresh ctrl shadow
> >>   ARM: DRA7: emif: Fix DDR init sequence during warm reset
> >>   ARM: DRA7: emif: Check for enable bits before updating leveling output
> >>   ARM: DRA7: emif: Enable interleaving for higher address space
> >>
> >>  arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
> >>  arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
> >>  arch/arm/include/asm/emif.h                  |  9 +++++
> >>  3 files changed, 67 insertions(+), 26 deletions(-)
> > 
> > Note that my board is still unable to boot from mainline with these
> > applied but still works with the TI vendor tree.
> 
> Hmm..I guess you are talking about DRA72-evm. SPL even doesn't come up
> or U-boot is failing. Can I see the logs? And what switch settings are
> you using?(Ill try to reproduce in my place)

SPL doesn't even come up so no output.  SD card boot settings.  I can
send you SW2/SW3/SW5 off-list in a bit.

-- 
Tom
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[U-Boot] [U-Boot, 1/4] ARM: DRA7: emif: Fix updating of refresh ctrl shadow

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:28PM +0530, Lokesh Vutla wrote:

> On DRA7, refresh ctrl shadow should be updated with
> the final value.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 2/4] ARM: DRA7: emif: Fix DDR init sequence during warm reset

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:29PM +0530, Lokesh Vutla wrote:

> Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
> enables Self refresh mode by default and during warm reset the EMIF
> contents are preserved. After warm reset EMIF sees that it is idle and
> puts DDR in self-refresh. When in SR, leveling operations cannot be done
> as DDR can only accept SR exit command, so its hanging during warm reset.
> In order to fix this reset the power management control register before
> EMIF initialization if it is a warm reset.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 3/4] ARM: DRA7: emif: Check for enable bits before updating leveling output

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:30PM +0530, Lokesh Vutla wrote:

> Read and write leveling can be enabled independently. Check for these
> enable bits before updating the read and write leveling output values.
> This will allow to use the combination of software and hardware leveling.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, 4/4] ARM: DRA7: emif: Enable interleaving for higher address space

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:31PM +0530, Lokesh Vutla wrote:

> Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
> enable interleaving for this higher memory to increase performance.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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