* [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders
@ 2016-03-18 15:05 Jani Nikula
2016-03-18 15:05 ` [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
v2 of adding bxt dsi transcoder support [1], addressing Ville's review,
which makes this cleaner.
BR,
Jani.
[1] http://mid.gmane.org/cover.1458070699.git.jani.nikula@intel.com
Jani Nikula (6):
drm/i915: split get/set pipe timings to timings and src size
drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma
drm/i915: abstract get config for cpu transcoder
drm/i915/bxt: add dsi transcoders
drm/i915/dsi: use the BIT macro for clarity
drm/i915/bxt: allow dsi on any pipe
drivers/gpu/drm/i915/i915_drv.h | 13 ++
drivers/gpu/drm/i915/intel_ddi.c | 6 +
drivers/gpu/drm/i915/intel_display.c | 230 ++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_dsi.c | 28 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +
6 files changed, 223 insertions(+), 63 deletions(-)
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:25 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma Jani Nikula
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
Prep work for DSI transcoders. No functional changes.
v2: call split functions at a higher level (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 74b0165238dc..a356a0a78b82 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -96,6 +96,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_i915_gem_object *obj);
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
+static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n,
struct intel_link_m_n *m2_n2);
@@ -4827,6 +4828,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
+ intel_set_pipe_src_size(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc,
@@ -4913,6 +4915,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
+ intel_set_pipe_src_size(intel_crtc);
if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
@@ -6120,6 +6123,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
+ intel_set_pipe_src_size(intel_crtc);
if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6192,6 +6196,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
+ intel_set_pipe_src_size(intel_crtc);
i9xx_set_pipeconf(intel_crtc);
@@ -7719,6 +7724,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
(pipe == PIPE_B || pipe == PIPE_C))
I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
+}
+
+static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
+{
+ struct drm_device *dev = intel_crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum pipe pipe = intel_crtc->pipe;
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
@@ -7760,6 +7773,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
pipe_config->base.adjusted_mode.crtc_vtotal += 1;
pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
}
+}
+
+static void intel_get_pipe_src_size(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 tmp;
tmp = I915_READ(PIPESRC(crtc->pipe));
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
@@ -8125,6 +8146,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_pipe_src_size(crtc, pipe_config);
i9xx_get_pfit_config(crtc, pipe_config);
@@ -9364,6 +9386,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
}
intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_pipe_src_size(crtc, pipe_config);
ironlake_get_pfit_config(crtc, pipe_config);
@@ -9972,6 +9995,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
haswell_get_ddi_port_state(crtc, pipe_config);
intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_pipe_src_size(crtc, pipe_config);
if (INTEL_INFO(dev)->gen >= 9) {
skl_init_scalers(dev, crtc, pipe_config);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
2016-03-18 15:05 ` [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:29 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder Jani Nikula
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
Prep work for DSI transcoders. No functional changes.
v2: call split functions at a higher level (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a356a0a78b82..eece50ed3ea6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -102,6 +102,8 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m2_n2);
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
+static void haswell_set_pipe_gamma(struct drm_crtc *crtc);
+static void haswell_set_pipemisc(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
@@ -4928,6 +4930,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
}
haswell_set_pipeconf(crtc);
+ haswell_set_pipe_gamma(crtc);
+ haswell_set_pipemisc(crtc);
intel_set_pipe_csc(crtc);
@@ -8764,16 +8768,12 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
static void haswell_set_pipeconf(struct drm_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
- uint32_t val;
+ u32 val = 0;
- val = 0;
-
- if (IS_HASWELL(dev) && intel_crtc->config->dither)
+ if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
@@ -8783,12 +8783,24 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
I915_WRITE(PIPECONF(cpu_transcoder), val);
POSTING_READ(PIPECONF(cpu_transcoder));
+}
+
+static void haswell_set_pipe_gamma(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
+}
+
+static void haswell_set_pipemisc(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
- val = 0;
+ if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
+ u32 val = 0;
switch (intel_crtc->config->pipe_bpp) {
case 18:
@@ -8811,7 +8823,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
- I915_WRITE(PIPEMISC(pipe), val);
+ I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
}
}
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
2016-03-18 15:05 ` [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size Jani Nikula
2016-03-18 15:05 ` [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:31 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders Jani Nikula
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
Makes it neater to add the same for DSI transcoder. No functional
changes.
v2: rename to hsw_get_transcoder_state and add a comment about grabbing
power reference (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 87 +++++++++++++++++++++---------------
1 file changed, 51 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eece50ed3ea6..98d8b563b9a1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9910,6 +9910,53 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
+static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config,
+ unsigned long *power_domain_mask)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum intel_display_power_domain power_domain;
+ u32 tmp;
+
+ pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
+
+ /*
+ * XXX: Do intel_display_power_get_if_enabled before reading this (for
+ * consistency and less surprising code; it's in always on power).
+ */
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
+ if (tmp & TRANS_DDI_FUNC_ENABLE) {
+ enum pipe trans_edp_pipe;
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ default:
+ WARN(1, "unknown pipe linked to edp transcoder\n");
+ case TRANS_DDI_EDP_INPUT_A_ONOFF:
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ trans_edp_pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ trans_edp_pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ trans_edp_pipe = PIPE_C;
+ break;
+ }
+
+ if (trans_edp_pipe == crtc->pipe)
+ pipe_config->cpu_transcoder = TRANSCODER_EDP;
+ }
+
+ power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
+ if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
+ return false;
+ *power_domain_mask |= BIT(power_domain);
+
+ tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
+
+ return tmp & PIPECONF_ENABLE;
+}
+
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -9960,48 +10007,18 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
enum intel_display_power_domain power_domain;
unsigned long power_domain_mask;
- uint32_t tmp;
- bool ret;
+ bool active;
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false;
power_domain_mask = BIT(power_domain);
- ret = false;
-
- pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
- tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
- if (tmp & TRANS_DDI_FUNC_ENABLE) {
- enum pipe trans_edp_pipe;
- switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
- default:
- WARN(1, "unknown pipe linked to edp transcoder\n");
- case TRANS_DDI_EDP_INPUT_A_ONOFF:
- case TRANS_DDI_EDP_INPUT_A_ON:
- trans_edp_pipe = PIPE_A;
- break;
- case TRANS_DDI_EDP_INPUT_B_ONOFF:
- trans_edp_pipe = PIPE_B;
- break;
- case TRANS_DDI_EDP_INPUT_C_ONOFF:
- trans_edp_pipe = PIPE_C;
- break;
- }
-
- if (trans_edp_pipe == crtc->pipe)
- pipe_config->cpu_transcoder = TRANSCODER_EDP;
- }
+ active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
- power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
- if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
- goto out;
- power_domain_mask |= BIT(power_domain);
-
- tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
- if (!(tmp & PIPECONF_ENABLE))
+ if (!active)
goto out;
haswell_get_ddi_port_state(crtc, pipe_config);
@@ -10038,13 +10055,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- ret = true;
-
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv, power_domain);
- return ret;
+ return active;
}
static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
` (2 preceding siblings ...)
2016-03-18 15:05 ` [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:38 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity Jani Nikula
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
The BXT display connections have DSI transcoders A and C that can be
muxed to any pipe, not unlike the eDP transcoder. Add the notion of DSI
transcoders.
The "normal" transcoders A, B and C are not used with BXT DSI, so care
must be taken to avoid accessing those registers with DSI transcoders in
the hardware state readout, modeset, and generally everywhere.
v2: addressing comments by Ville:
- rename the dsi get config function to hsw_get_dsi_transcoder_state
- rebase onto the higher level split of pipe/transcoder functions
- use more has_dsi_encoder as we can now because of the above,
with no need to look at the transcoder so much
- rename IS_DSI_TRANSCODER to transcoder_is_dsi
- use the above a bit more instead of comparing to < TRANSCODER_EDP
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 13 +++++
drivers/gpu/drm/i915/intel_ddi.c | 6 +++
drivers/gpu/drm/i915/intel_display.c | 91 +++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_dsi.c | 9 ++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++
6 files changed, 116 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f330a53c19b9..5e700770c403 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -127,6 +127,8 @@ enum transcoder {
TRANSCODER_B,
TRANSCODER_C,
TRANSCODER_EDP,
+ TRANSCODER_DSI_A,
+ TRANSCODER_DSI_C,
I915_MAX_TRANSCODERS
};
@@ -141,11 +143,20 @@ static inline const char *transcoder_name(enum transcoder transcoder)
return "C";
case TRANSCODER_EDP:
return "EDP";
+ case TRANSCODER_DSI_A:
+ return "DSI A";
+ case TRANSCODER_DSI_C:
+ return "DSI C";
default:
return "<invalid>";
}
}
+static inline bool transcoder_is_dsi(enum transcoder transcoder)
+{
+ return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
+}
+
/*
* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
* number of planes per CRTC. Not all platforms really have this many planes,
@@ -196,6 +207,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_DSI_A,
+ POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
POWER_DOMAIN_PORT_DDI_B_LANES,
POWER_DOMAIN_PORT_DDI_C_LANES,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 91654ffc3a42..e6c3a80e1360 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1061,6 +1061,8 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
+ WARN_ON(transcoder_is_dsi(cpu_transcoder));
+
temp = TRANS_MSA_SYNC_CLK;
switch (intel_crtc->config->pipe_bpp) {
case 18:
@@ -1942,6 +1944,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_hdmi *intel_hdmi;
u32 temp, flags = 0;
+ /* XXX: DSI transcoder paranoia */
+ if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ return;
+
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 98d8b563b9a1..28ead66ed987 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4900,6 +4900,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
+ enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->state);
@@ -4916,11 +4917,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
if (intel_crtc->config->has_dp_encoder)
intel_dp_set_m_n(intel_crtc, M1_N1);
- intel_set_pipe_timings(intel_crtc);
+ if (!intel_crtc->config->has_dsi_encoder)
+ intel_set_pipe_timings(intel_crtc);
+
intel_set_pipe_src_size(intel_crtc);
- if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
- I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
+ if (cpu_transcoder != TRANSCODER_EDP &&
+ !transcoder_is_dsi(cpu_transcoder)) {
+ I915_WRITE(PIPE_MULT(cpu_transcoder),
intel_crtc->config->pixel_multiplier - 1);
}
@@ -4929,7 +4933,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
&intel_crtc->config->fdi_m_n, NULL);
}
- haswell_set_pipeconf(crtc);
+ if (!intel_crtc->config->has_dsi_encoder)
+ haswell_set_pipeconf(crtc);
+
haswell_set_pipe_gamma(crtc);
haswell_set_pipemisc(crtc);
@@ -4972,7 +4978,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
dev_priv->display.initial_watermarks(pipe_config);
else
intel_update_watermarks(crtc);
- intel_enable_pipe(intel_crtc);
+
+ /* XXX: Do the pipe assertions at the right place for BXT DSI. */
+ if (!intel_crtc->config->has_dsi_encoder)
+ intel_enable_pipe(intel_crtc);
if (intel_crtc->config->has_pch_encoder)
lpt_pch_enable(crtc);
@@ -5105,7 +5114,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
- intel_disable_pipe(intel_crtc);
+ /* XXX: Do the pipe assertions at the right place for BXT DSI. */
+ if (!intel_crtc->config->has_dsi_encoder)
+ intel_disable_pipe(intel_crtc);
if (intel_crtc->config->dp_encoder_is_mst)
intel_ddi_set_vc_payload_alloc(crtc, false);
@@ -9957,6 +9968,47 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
return tmp & PIPECONF_ENABLE;
}
+static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config,
+ unsigned long *power_domain_mask)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum intel_display_power_domain power_domain;
+ enum port port;
+ enum transcoder cpu_transcoder;
+ u32 tmp;
+
+ pipe_config->has_dsi_encoder = false;
+
+ for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
+ if (port == PORT_A)
+ cpu_transcoder = TRANSCODER_DSI_A;
+ else
+ cpu_transcoder = TRANSCODER_DSI_C;
+
+ power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+ if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
+ continue;
+ *power_domain_mask |= BIT(power_domain);
+
+ /* XXX: this works for video mode only */
+ tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
+ if (!(tmp & DPI_ENABLE))
+ continue;
+
+ tmp = I915_READ(MIPI_CTRL(port));
+ if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
+ continue;
+
+ pipe_config->cpu_transcoder = cpu_transcoder;
+ pipe_config->has_dsi_encoder = true;
+ break;
+ }
+
+ return pipe_config->has_dsi_encoder;
+}
+
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10018,12 +10070,22 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
+ if (IS_BROXTON(dev_priv)) {
+ bxt_get_dsi_transcoder_state(crtc, pipe_config,
+ &power_domain_mask);
+ WARN_ON(active && pipe_config->has_dsi_encoder);
+ if (pipe_config->has_dsi_encoder)
+ active = true;
+ }
+
if (!active)
goto out;
- haswell_get_ddi_port_state(crtc, pipe_config);
+ if (!pipe_config->has_dsi_encoder) {
+ haswell_get_ddi_port_state(crtc, pipe_config);
+ intel_get_pipe_timings(crtc, pipe_config);
+ }
- intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
if (INTEL_INFO(dev)->gen >= 9) {
@@ -10048,7 +10110,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
(I915_READ(IPS_CTL) & IPS_ENABLE);
- if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
+ if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
} else {
@@ -15520,10 +15583,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
/* Clear any frame start delays used for debugging left by the BIOS */
- I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
+ if (!transcoder_is_dsi(cpu_transcoder)) {
+ i915_reg_t reg = PIPECONF(cpu_transcoder);
+
+ I915_WRITE(reg,
+ I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
+ }
/* restore vblank interrupts to correct state */
drm_crtc_vblank_reset(&crtc->base);
@@ -16194,6 +16262,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->pipe[i].stat = I915_READ(PIPESTAT(i));
}
+ /* Note: this does not include DSI transcoders. */
error->num_transcoders = INTEL_INFO(dev)->num_pipes;
if (HAS_DDI(dev_priv->dev))
error->num_transcoders++; /* Account for eDP. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5136eeffc24e..ba45245ad6c8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -437,7 +437,8 @@ struct intel_crtc_state {
bool has_infoframe;
/* CPU Transcoder for the pipe. Currently this can only differ from the
- * pipe on Haswell (where we have a special eDP transcoder). */
+ * pipe on Haswell and later (where we have a special eDP transcoder)
+ * and Broxton (where we have special DSI transcoders). */
enum transcoder cpu_transcoder;
/*
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3562bf337e62..1981212ffc8d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -268,6 +268,7 @@ static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
static bool intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
@@ -284,6 +285,14 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
+ if (IS_BROXTON(dev_priv)) {
+ /* Dual link goes to DSI transcoder A. */
+ if (intel_dsi->ports == BIT(PORT_C))
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
+ else
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
+ }
+
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2e88a5e06884..d189a0012277 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -89,6 +89,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_DSI_A:
+ return "TRANSCODER_DSI_A";
+ case POWER_DOMAIN_TRANSCODER_DSI_C:
+ return "TRANSCODER_DSI_C";
case POWER_DOMAIN_PORT_DDI_A_LANES:
return "PORT_DDI_A_LANES";
case POWER_DOMAIN_PORT_DDI_B_LANES:
@@ -419,6 +423,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT(POWER_DOMAIN_PIPE_A) | \
BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
+ BIT(POWER_DOMAIN_TRANSCODER_DSI_A) | \
+ BIT(POWER_DOMAIN_TRANSCODER_DSI_C) | \
BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
BIT(POWER_DOMAIN_PORT_DSI) | \
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
` (3 preceding siblings ...)
2016-03-18 15:05 ` [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:38 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe Jani Nikula
2016-03-21 9:59 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2) Patchwork
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1981212ffc8d..dd6f7bc4f444 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -412,7 +412,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
temp &= ~LANE_CONFIGURATION_MASK;
temp &= ~DUAL_LINK_MODE_MASK;
- if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
+ if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
temp |= (intel_dsi->dual_link - 1)
<< DUAL_LINK_MODE_SHIFT;
temp |= intel_crtc->pipe ?
@@ -1200,14 +1200,14 @@ void intel_dsi_init(struct drm_device *dev)
/* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
if (port == PORT_A)
- intel_encoder->crtc_mask = 1 << PIPE_A;
+ intel_encoder->crtc_mask = BIT(PIPE_A);
else
- intel_encoder->crtc_mask = 1 << PIPE_B;
+ intel_encoder->crtc_mask = BIT(PIPE_B);
if (dev_priv->vbt.dsi.config->dual_link)
- intel_dsi->ports = (1 << PORT_A) | (1 << PORT_C);
+ intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
else
- intel_dsi->ports = 1 << port;
+ intel_dsi->ports = BIT(port);
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
` (4 preceding siblings ...)
2016-03-18 15:05 ` [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity Jani Nikula
@ 2016-03-18 15:05 ` Jani Nikula
2016-03-18 15:39 ` Ville Syrjälä
2016-03-21 9:59 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2) Patchwork
6 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-03-18 15:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
BXT isn't as limited as BYT and CHT regarding DSI pipes and ports.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index dd6f7bc4f444..456676c00059 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1198,8 +1198,13 @@ void intel_dsi_init(struct drm_device *dev)
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
- /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
- if (port == PORT_A)
+ /*
+ * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
+ * port C. BXT isn't limited like this.
+ */
+ if (IS_BROXTON(dev_priv))
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ else if (port == PORT_A)
intel_encoder->crtc_mask = BIT(PIPE_A);
else
intel_encoder->crtc_mask = BIT(PIPE_B);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size
2016-03-18 15:05 ` [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size Jani Nikula
@ 2016-03-18 15:25 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:39PM +0200, Jani Nikula wrote:
> Prep work for DSI transcoders. No functional changes.
>
> v2: call split functions at a higher level (Ville)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 74b0165238dc..a356a0a78b82 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -96,6 +96,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> struct drm_i915_gem_object *obj);
> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> +static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
> static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> struct intel_link_m_n *m_n,
> struct intel_link_m_n *m2_n2);
> @@ -4827,6 +4828,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
> + intel_set_pipe_src_size(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder) {
> intel_cpu_transcoder_set_m_n(intel_crtc,
> @@ -4913,6 +4915,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
> + intel_set_pipe_src_size(intel_crtc);
>
> if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
> I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
> @@ -6120,6 +6123,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
> + intel_set_pipe_src_size(intel_crtc);
>
> if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6192,6 +6196,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
> + intel_set_pipe_src_size(intel_crtc);
>
> i9xx_set_pipeconf(intel_crtc);
>
> @@ -7719,6 +7724,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> (pipe == PIPE_B || pipe == PIPE_C))
> I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
>
> +}
> +
> +static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
> +{
> + struct drm_device *dev = intel_crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum pipe pipe = intel_crtc->pipe;
> +
> /* pipesrc controls the size that is scaled from, which should
> * always be the user's requested size.
> */
> @@ -7760,6 +7773,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
> pipe_config->base.adjusted_mode.crtc_vtotal += 1;
> pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
> }
> +}
> +
> +static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 tmp;
>
> tmp = I915_READ(PIPESRC(crtc->pipe));
> pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> @@ -8125,6 +8146,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>
> intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_pipe_src_size(crtc, pipe_config);
>
> i9xx_get_pfit_config(crtc, pipe_config);
>
> @@ -9364,6 +9386,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> }
>
> intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_pipe_src_size(crtc, pipe_config);
>
> ironlake_get_pfit_config(crtc, pipe_config);
>
> @@ -9972,6 +9995,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> haswell_get_ddi_port_state(crtc, pipe_config);
>
> intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_pipe_src_size(crtc, pipe_config);
>
> if (INTEL_INFO(dev)->gen >= 9) {
> skl_init_scalers(dev, crtc, pipe_config);
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma
2016-03-18 15:05 ` [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma Jani Nikula
@ 2016-03-18 15:29 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:40PM +0200, Jani Nikula wrote:
> Prep work for DSI transcoders. No functional changes.
>
> v2: call split functions at a higher level (Ville)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++----------
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a356a0a78b82..eece50ed3ea6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -102,6 +102,8 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> struct intel_link_m_n *m2_n2);
> static void ironlake_set_pipeconf(struct drm_crtc *crtc);
> static void haswell_set_pipeconf(struct drm_crtc *crtc);
> +static void haswell_set_pipe_gamma(struct drm_crtc *crtc);
> +static void haswell_set_pipemisc(struct drm_crtc *crtc);
> static void intel_set_pipe_csc(struct drm_crtc *crtc);
> static void vlv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> @@ -4928,6 +4930,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> }
>
> haswell_set_pipeconf(crtc);
> + haswell_set_pipe_gamma(crtc);
> + haswell_set_pipemisc(crtc);
>
> intel_set_pipe_csc(crtc);
>
> @@ -8764,16 +8768,12 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
>
> static void haswell_set_pipeconf(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum pipe pipe = intel_crtc->pipe;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> - uint32_t val;
> + u32 val = 0;
>
> - val = 0;
> -
> - if (IS_HASWELL(dev) && intel_crtc->config->dither)
> + if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> @@ -8783,12 +8783,24 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
>
> I915_WRITE(PIPECONF(cpu_transcoder), val);
> POSTING_READ(PIPECONF(cpu_transcoder));
> +}
> +
> +static void haswell_set_pipe_gamma(struct drm_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>
> I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
> POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
> +}
> +
> +static void haswell_set_pipemisc(struct drm_crtc *crtc)
As a followuo could perhaps name this broadwell_... and move the gen
check outside? Not sure it would be any nicer though.
Anyways, your way results in a more minimal patch which is nice for
this series.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +{
> + struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>
> - if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
> - val = 0;
> + if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
> + u32 val = 0;
>
> switch (intel_crtc->config->pipe_bpp) {
> case 18:
> @@ -8811,7 +8823,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
> if (intel_crtc->config->dither)
> val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>
> - I915_WRITE(PIPEMISC(pipe), val);
> + I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
> }
> }
>
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder
2016-03-18 15:05 ` [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder Jani Nikula
@ 2016-03-18 15:31 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:41PM +0200, Jani Nikula wrote:
> Makes it neater to add the same for DSI transcoder. No functional
> changes.
>
> v2: rename to hsw_get_transcoder_state and add a comment about grabbing
> power reference (Ville)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 87 +++++++++++++++++++++---------------
> 1 file changed, 51 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eece50ed3ea6..98d8b563b9a1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9910,6 +9910,53 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
> pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> }
>
> +static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config,
> + unsigned long *power_domain_mask)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum intel_display_power_domain power_domain;
> + u32 tmp;
> +
> + pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> +
> + /*
> + * XXX: Do intel_display_power_get_if_enabled before reading this (for
> + * consistency and less surprising code; it's in always on power).
> + */
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> + if (tmp & TRANS_DDI_FUNC_ENABLE) {
> + enum pipe trans_edp_pipe;
> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> + default:
> + WARN(1, "unknown pipe linked to edp transcoder\n");
> + case TRANS_DDI_EDP_INPUT_A_ONOFF:
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + trans_edp_pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + trans_edp_pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + trans_edp_pipe = PIPE_C;
> + break;
> + }
> +
> + if (trans_edp_pipe == crtc->pipe)
> + pipe_config->cpu_transcoder = TRANSCODER_EDP;
> + }
> +
> + power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> + if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> + return false;
> + *power_domain_mask |= BIT(power_domain);
> +
> + tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
> +
> + return tmp & PIPECONF_ENABLE;
> +}
> +
> static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -9960,48 +10007,18 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum intel_display_power_domain power_domain;
> unsigned long power_domain_mask;
> - uint32_t tmp;
> - bool ret;
> + bool active;
>
> power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> return false;
> power_domain_mask = BIT(power_domain);
>
> - ret = false;
> -
> - pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> pipe_config->shared_dpll = NULL;
>
> - tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> - if (tmp & TRANS_DDI_FUNC_ENABLE) {
> - enum pipe trans_edp_pipe;
> - switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> - default:
> - WARN(1, "unknown pipe linked to edp transcoder\n");
> - case TRANS_DDI_EDP_INPUT_A_ONOFF:
> - case TRANS_DDI_EDP_INPUT_A_ON:
> - trans_edp_pipe = PIPE_A;
> - break;
> - case TRANS_DDI_EDP_INPUT_B_ONOFF:
> - trans_edp_pipe = PIPE_B;
> - break;
> - case TRANS_DDI_EDP_INPUT_C_ONOFF:
> - trans_edp_pipe = PIPE_C;
> - break;
> - }
> -
> - if (trans_edp_pipe == crtc->pipe)
> - pipe_config->cpu_transcoder = TRANSCODER_EDP;
> - }
> + active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
>
> - power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> - if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> - goto out;
> - power_domain_mask |= BIT(power_domain);
> -
> - tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
> - if (!(tmp & PIPECONF_ENABLE))
> + if (!active)
> goto out;
>
> haswell_get_ddi_port_state(crtc, pipe_config);
> @@ -10038,13 +10055,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> - ret = true;
> -
> out:
> for_each_power_domain(power_domain, power_domain_mask)
> intel_display_power_put(dev_priv, power_domain);
>
> - return ret;
> + return active;
> }
>
> static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders
2016-03-18 15:05 ` [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders Jani Nikula
@ 2016-03-18 15:38 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:42PM +0200, Jani Nikula wrote:
> The BXT display connections have DSI transcoders A and C that can be
> muxed to any pipe, not unlike the eDP transcoder. Add the notion of DSI
> transcoders.
>
> The "normal" transcoders A, B and C are not used with BXT DSI, so care
> must be taken to avoid accessing those registers with DSI transcoders in
> the hardware state readout, modeset, and generally everywhere.
>
> v2: addressing comments by Ville:
> - rename the dsi get config function to hsw_get_dsi_transcoder_state
> - rebase onto the higher level split of pipe/transcoder functions
> - use more has_dsi_encoder as we can now because of the above,
> with no need to look at the transcoder so much
> - rename IS_DSI_TRANSCODER to transcoder_is_dsi
> - use the above a bit more instead of comparing to < TRANSCODER_EDP
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 13 +++++
> drivers/gpu/drm/i915/intel_ddi.c | 6 +++
> drivers/gpu/drm/i915/intel_display.c | 91 +++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_dsi.c | 9 ++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++
> 6 files changed, 116 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f330a53c19b9..5e700770c403 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -127,6 +127,8 @@ enum transcoder {
> TRANSCODER_B,
> TRANSCODER_C,
> TRANSCODER_EDP,
> + TRANSCODER_DSI_A,
> + TRANSCODER_DSI_C,
> I915_MAX_TRANSCODERS
> };
>
> @@ -141,11 +143,20 @@ static inline const char *transcoder_name(enum transcoder transcoder)
> return "C";
> case TRANSCODER_EDP:
> return "EDP";
> + case TRANSCODER_DSI_A:
> + return "DSI A";
> + case TRANSCODER_DSI_C:
> + return "DSI C";
> default:
> return "<invalid>";
> }
> }
>
> +static inline bool transcoder_is_dsi(enum transcoder transcoder)
> +{
> + return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
> +}
> +
> /*
> * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> * number of planes per CRTC. Not all platforms really have this many planes,
> @@ -196,6 +207,8 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> POWER_DOMAIN_TRANSCODER_EDP,
> + POWER_DOMAIN_TRANSCODER_DSI_A,
> + POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> POWER_DOMAIN_PORT_DDI_B_LANES,
> POWER_DOMAIN_PORT_DDI_C_LANES,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 91654ffc3a42..e6c3a80e1360 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1061,6 +1061,8 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
> uint32_t temp;
>
> if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
> + WARN_ON(transcoder_is_dsi(cpu_transcoder));
> +
> temp = TRANS_MSA_SYNC_CLK;
> switch (intel_crtc->config->pipe_bpp) {
> case 18:
> @@ -1942,6 +1944,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_hdmi *intel_hdmi;
> u32 temp, flags = 0;
>
> + /* XXX: DSI transcoder paranoia */
> + if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
> + return;
> +
> temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (temp & TRANS_DDI_PHSYNC)
> flags |= DRM_MODE_FLAG_PHSYNC;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 98d8b563b9a1..28ead66ed987 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4900,6 +4900,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> + enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc->state);
>
> @@ -4916,11 +4917,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_dp_encoder)
> intel_dp_set_m_n(intel_crtc, M1_N1);
>
> - intel_set_pipe_timings(intel_crtc);
> + if (!intel_crtc->config->has_dsi_encoder)
> + intel_set_pipe_timings(intel_crtc);
> +
> intel_set_pipe_src_size(intel_crtc);
>
> - if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
> - I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
> + if (cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(cpu_transcoder)) {
> + I915_WRITE(PIPE_MULT(cpu_transcoder),
> intel_crtc->config->pixel_multiplier - 1);
> }
>
> @@ -4929,7 +4933,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> &intel_crtc->config->fdi_m_n, NULL);
> }
>
> - haswell_set_pipeconf(crtc);
> + if (!intel_crtc->config->has_dsi_encoder)
> + haswell_set_pipeconf(crtc);
> +
> haswell_set_pipe_gamma(crtc);
> haswell_set_pipemisc(crtc);
>
> @@ -4972,7 +4978,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.initial_watermarks(pipe_config);
> else
> intel_update_watermarks(crtc);
> - intel_enable_pipe(intel_crtc);
> +
> + /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> + if (!intel_crtc->config->has_dsi_encoder)
> + intel_enable_pipe(intel_crtc);
>
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
> @@ -5105,7 +5114,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
>
> - intel_disable_pipe(intel_crtc);
> + /* XXX: Do the pipe assertions at the right place for BXT DSI. */
> + if (!intel_crtc->config->has_dsi_encoder)
> + intel_disable_pipe(intel_crtc);
>
> if (intel_crtc->config->dp_encoder_is_mst)
> intel_ddi_set_vc_payload_alloc(crtc, false);
> @@ -9957,6 +9968,47 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> return tmp & PIPECONF_ENABLE;
> }
>
> +static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config,
> + unsigned long *power_domain_mask)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum intel_display_power_domain power_domain;
> + enum port port;
> + enum transcoder cpu_transcoder;
> + u32 tmp;
> +
> + pipe_config->has_dsi_encoder = false;
> +
> + for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
> + if (port == PORT_A)
> + cpu_transcoder = TRANSCODER_DSI_A;
> + else
> + cpu_transcoder = TRANSCODER_DSI_C;
> +
> + power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> + if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> + continue;
> + *power_domain_mask |= BIT(power_domain);
> +
> + /* XXX: this works for video mode only */
> + tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
> + if (!(tmp & DPI_ENABLE))
> + continue;
> +
> + tmp = I915_READ(MIPI_CTRL(port));
> + if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
> + continue;
> +
> + pipe_config->cpu_transcoder = cpu_transcoder;
> + pipe_config->has_dsi_encoder = true;
> + break;
> + }
> +
> + return pipe_config->has_dsi_encoder;
> +}
> +
> static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -10018,12 +10070,22 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>
> active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
>
> + if (IS_BROXTON(dev_priv)) {
> + bxt_get_dsi_transcoder_state(crtc, pipe_config,
> + &power_domain_mask);
> + WARN_ON(active && pipe_config->has_dsi_encoder);
The warn could use a small comment perhaps, explaining that DSI and DDI
transcoders shouldn't be enabled at the same time.
Anyway, patch looks good to me
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + if (pipe_config->has_dsi_encoder)
> + active = true;
> + }
> +
> if (!active)
> goto out;
>
> - haswell_get_ddi_port_state(crtc, pipe_config);
> + if (!pipe_config->has_dsi_encoder) {
> + haswell_get_ddi_port_state(crtc, pipe_config);
> + intel_get_pipe_timings(crtc, pipe_config);
> + }
>
> - intel_get_pipe_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
>
> if (INTEL_INFO(dev)->gen >= 9) {
> @@ -10048,7 +10110,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
> (I915_READ(IPS_CTL) & IPS_ENABLE);
>
> - if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
> + if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
> + !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> pipe_config->pixel_multiplier =
> I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
> } else {
> @@ -15520,10 +15583,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>
> /* Clear any frame start delays used for debugging left by the BIOS */
> - I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
> + if (!transcoder_is_dsi(cpu_transcoder)) {
> + i915_reg_t reg = PIPECONF(cpu_transcoder);
> +
> + I915_WRITE(reg,
> + I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
> + }
>
> /* restore vblank interrupts to correct state */
> drm_crtc_vblank_reset(&crtc->base);
> @@ -16194,6 +16262,7 @@ intel_display_capture_error_state(struct drm_device *dev)
> error->pipe[i].stat = I915_READ(PIPESTAT(i));
> }
>
> + /* Note: this does not include DSI transcoders. */
> error->num_transcoders = INTEL_INFO(dev)->num_pipes;
> if (HAS_DDI(dev_priv->dev))
> error->num_transcoders++; /* Account for eDP. */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5136eeffc24e..ba45245ad6c8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -437,7 +437,8 @@ struct intel_crtc_state {
> bool has_infoframe;
>
> /* CPU Transcoder for the pipe. Currently this can only differ from the
> - * pipe on Haswell (where we have a special eDP transcoder). */
> + * pipe on Haswell and later (where we have a special eDP transcoder)
> + * and Broxton (where we have special DSI transcoders). */
> enum transcoder cpu_transcoder;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3562bf337e62..1981212ffc8d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -268,6 +268,7 @@ static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
> static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> @@ -284,6 +285,14 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> /* DSI uses short packets for sync events, so clear mode flags for DSI */
> adjusted_mode->flags = 0;
>
> + if (IS_BROXTON(dev_priv)) {
> + /* Dual link goes to DSI transcoder A. */
> + if (intel_dsi->ports == BIT(PORT_C))
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> + else
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
> + }
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 2e88a5e06884..d189a0012277 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -89,6 +89,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "TRANSCODER_C";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> + case POWER_DOMAIN_TRANSCODER_DSI_A:
> + return "TRANSCODER_DSI_A";
> + case POWER_DOMAIN_TRANSCODER_DSI_C:
> + return "TRANSCODER_DSI_C";
> case POWER_DOMAIN_PORT_DDI_A_LANES:
> return "PORT_DDI_A_LANES";
> case POWER_DOMAIN_PORT_DDI_B_LANES:
> @@ -419,6 +423,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT(POWER_DOMAIN_PIPE_A) | \
> BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
> + BIT(POWER_DOMAIN_TRANSCODER_DSI_A) | \
> + BIT(POWER_DOMAIN_TRANSCODER_DSI_C) | \
> BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> BIT(POWER_DOMAIN_PORT_DSI) | \
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity
2016-03-18 15:05 ` [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity Jani Nikula
@ 2016-03-18 15:38 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:43PM +0200, Jani Nikula wrote:
> No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 1981212ffc8d..dd6f7bc4f444 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -412,7 +412,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> temp &= ~LANE_CONFIGURATION_MASK;
> temp &= ~DUAL_LINK_MODE_MASK;
>
> - if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> + if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
> temp |= (intel_dsi->dual_link - 1)
> << DUAL_LINK_MODE_SHIFT;
> temp |= intel_crtc->pipe ?
> @@ -1200,14 +1200,14 @@ void intel_dsi_init(struct drm_device *dev)
>
> /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
> if (port == PORT_A)
> - intel_encoder->crtc_mask = 1 << PIPE_A;
> + intel_encoder->crtc_mask = BIT(PIPE_A);
> else
> - intel_encoder->crtc_mask = 1 << PIPE_B;
> + intel_encoder->crtc_mask = BIT(PIPE_B);
>
> if (dev_priv->vbt.dsi.config->dual_link)
> - intel_dsi->ports = (1 << PORT_A) | (1 << PORT_C);
> + intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
> else
> - intel_dsi->ports = 1 << port;
> + intel_dsi->ports = BIT(port);
>
> /* Create a DSI host (and a device) for each port. */
> for_each_dsi_port(port, intel_dsi->ports) {
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe
2016-03-18 15:05 ` [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe Jani Nikula
@ 2016-03-18 15:39 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2016-03-18 15:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Fri, Mar 18, 2016 at 05:05:44PM +0200, Jani Nikula wrote:
> BXT isn't as limited as BYT and CHT regarding DSI pipes and ports.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index dd6f7bc4f444..456676c00059 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1198,8 +1198,13 @@ void intel_dsi_init(struct drm_device *dev)
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> intel_connector->unregister = intel_connector_unregister;
>
> - /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
> - if (port == PORT_A)
> + /*
> + * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
> + * port C. BXT isn't limited like this.
> + */
> + if (IS_BROXTON(dev_priv))
> + intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> + else if (port == PORT_A)
> intel_encoder->crtc_mask = BIT(PIPE_A);
> else
> intel_encoder->crtc_mask = BIT(PIPE_B);
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2)
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
` (5 preceding siblings ...)
2016-03-18 15:05 ` [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe Jani Nikula
@ 2016-03-21 9:59 ` Patchwork
2016-03-21 13:04 ` Jani Nikula
6 siblings, 1 reply; 15+ messages in thread
From: Patchwork @ 2016-03-21 9:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: add dsi transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/4483/
State : failure
== Summary ==
Series 4483v2 drm/i915/bxt: add dsi transcoders
http://patchwork.freedesktop.org/api/1.0/series/4483/revisions/2/mbox/
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (bsw-nuc-2)
Test kms_force_connector_basic:
Subgroup force-load-detect:
pass -> SKIP (ivb-t430s)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
dmesg-warn -> PASS (snb-x220t)
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (hsw-gt2)
Test pm_rpm:
Subgroup basic-rte:
pass -> DMESG-WARN (snb-x220t)
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:155 dwarn:1 dfail:0 fail:1 skip:37
hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63
ivb-t430s total:194 pass:168 dwarn:0 dfail:0 fail:0 skip:26
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34
snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1646/
e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest
237a0d0eaaea5982367e27bc2a3839cea6faf672 drm/i915/bxt: allow dsi on any pipe
d058539f1a1d4a2fe6325451424e9b270440a530 drm/i915/dsi: use the BIT macro for clarity
b066b2d209f1708463cffd9599e8edac54c9f899 drm/i915/bxt: add dsi transcoders
5f89c5760b7352513e544759c7abd709b0de057b drm/i915: abstract get config for cpu transcoder
9eadc9e55255efee261c71b0e56ebea2d0386f0d drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma
e3c9075c8dd572eac9ce3eca2533f03e1a9b1857 drm/i915: split get/set pipe timings to timings and src size
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2)
2016-03-21 9:59 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2) Patchwork
@ 2016-03-21 13:04 ` Jani Nikula
0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2016-03-21 13:04 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On Mon, 21 Mar 2016, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> [ text/plain ]
> == Series Details ==
>
> Series: drm/i915/bxt: add dsi transcoders (rev2)
> URL : https://patchwork.freedesktop.org/series/4483/
> State : failure
>
> == Summary ==
>
> Series 4483v2 drm/i915/bxt: add dsi transcoders
> http://patchwork.freedesktop.org/api/1.0/series/4483/revisions/2/mbox/
>
> Test kms_flip:
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (bsw-nuc-2)
> Test kms_force_connector_basic:
> Subgroup force-load-detect:
> pass -> SKIP (ivb-t430s)
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-a:
> dmesg-warn -> PASS (snb-x220t)
> Subgroup suspend-read-crc-pipe-c:
> incomplete -> PASS (hsw-gt2)
> Test pm_rpm:
> Subgroup basic-rte:
> pass -> DMESG-WARN (snb-x220t)
Existing issues not related to dsi.
Pushed the series, thanks for the review.
BR,
Jani.
>
> bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
> bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
> bsw-nuc-2 total:194 pass:155 dwarn:1 dfail:0 fail:1 skip:37
> hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22
> hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
> ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63
> ivb-t430s total:194 pass:168 dwarn:0 dfail:0 fail:0 skip:26
> skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34
> snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33
>
> Results at /archive/results/CI_IGT_test/Patchwork_1646/
>
> e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest
> 237a0d0eaaea5982367e27bc2a3839cea6faf672 drm/i915/bxt: allow dsi on any pipe
> d058539f1a1d4a2fe6325451424e9b270440a530 drm/i915/dsi: use the BIT macro for clarity
> b066b2d209f1708463cffd9599e8edac54c9f899 drm/i915/bxt: add dsi transcoders
> 5f89c5760b7352513e544759c7abd709b0de057b drm/i915: abstract get config for cpu transcoder
> 9eadc9e55255efee261c71b0e56ebea2d0386f0d drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma
> e3c9075c8dd572eac9ce3eca2533f03e1a9b1857 drm/i915: split get/set pipe timings to timings and src size
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2016-03-21 13:04 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-18 15:05 [PATCH v2 0/6] drm/i915/bxt: add dsi transcoders Jani Nikula
2016-03-18 15:05 ` [PATCH v2 1/6] drm/i915: split get/set pipe timings to timings and src size Jani Nikula
2016-03-18 15:25 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 2/6] drm/i915: split set pipeconf to pipeconf, pipemisc, pipe_gamma Jani Nikula
2016-03-18 15:29 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 3/6] drm/i915: abstract get config for cpu transcoder Jani Nikula
2016-03-18 15:31 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 4/6] drm/i915/bxt: add dsi transcoders Jani Nikula
2016-03-18 15:38 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 5/6] drm/i915/dsi: use the BIT macro for clarity Jani Nikula
2016-03-18 15:38 ` Ville Syrjälä
2016-03-18 15:05 ` [PATCH v2 6/6] drm/i915/bxt: allow dsi on any pipe Jani Nikula
2016-03-18 15:39 ` Ville Syrjälä
2016-03-21 9:59 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: add dsi transcoders (rev2) Patchwork
2016-03-21 13:04 ` Jani Nikula
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