* [PATCH 0/3] Gen8 Engine reset preparatory patches
@ 2016-03-18 20:07 Arun Siluvery
2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Arun Siluvery @ 2016-03-18 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
First batch of prep patches for Engine reset feature available from Gen8
onwards. The reset code is recently prep'd to support this feature, now
others can follow now.
Arun Siluvery (2):
drm/i915/tdr: Prepare error handler to accept mask of hung engines
drm/i915: Update i915.reset to handle engine resets
Tomas Elf (1):
drm/i915/tdr: Initialize hangcheck struct for each engine
drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++----
drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++--------
drivers/gpu/drm/i915/i915_params.c | 6 +++---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++-
8 files changed, 38 insertions(+), 20 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery @ 2016-03-18 20:07 ` Arun Siluvery 2016-03-18 20:48 ` Chris Wilson 2016-03-21 16:26 ` [PATCH v2] " Arun Siluvery 2016-03-18 20:07 ` [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines Arun Siluvery ` (4 subsequent siblings) 5 siblings, 2 replies; 15+ messages in thread From: Arun Siluvery @ 2016-03-18 20:07 UTC (permalink / raw) To: intel-gfx; +Cc: Tomas Elf, Mika Kuoppala From: Tomas Elf <tomas.elf@intel.com> Initialize hangcheck struct during driver load. Since we do the same after recovering from a reset, this is extracted into a helper function. Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 3f439a0..c5d1673 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -945,6 +945,16 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) } } +static void i915_hangcheck_init(struct drm_device *dev) +{ + int i; + struct intel_engine_cs *engine; + struct drm_i915_private *dev_priv = dev->dev_private; + + for_each_engine(engine, dev_priv, i) + intel_engine_init_hangcheck(engine); +} + static int i915_workqueues_init(struct drm_i915_private *dev_priv) { /* @@ -1233,6 +1243,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) i915_gem_load_init_fences(dev_priv); + i915_hangcheck_init(dev); + /* On the 945G/GM, the chipset reports the MSI capability on the * integrated graphics even though the support isn't actually there * according to the published specs. It doesn't appear to function diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f330a53..549a232 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2718,6 +2718,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_device *dev); extern int i915_reset(struct drm_device *dev); +extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3a23b95..40ef4ea 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1606,7 +1606,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) engine->next_context_status_buffer = next_context_status_buffer_hw; DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); return 0; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index df0ef5b..ce59850 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -555,6 +555,11 @@ static bool stop_ring(struct intel_engine_cs *engine) return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; } +void intel_engine_init_hangcheck(struct intel_engine_cs *engine) +{ + memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); +} + static int init_ring_common(struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; @@ -634,7 +639,7 @@ static int init_ring_common(struct intel_engine_cs *engine) ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; intel_ring_update_space(ringbuf); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); out: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery @ 2016-03-18 20:48 ` Chris Wilson 2016-03-18 21:22 ` Arun Siluvery 2016-03-21 16:26 ` [PATCH v2] " Arun Siluvery 1 sibling, 1 reply; 15+ messages in thread From: Chris Wilson @ 2016-03-18 20:48 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Tomas Elf, Mika Kuoppala On Fri, Mar 18, 2016 at 08:07:54PM +0000, Arun Siluvery wrote: > From: Tomas Elf <tomas.elf@intel.com> > > Initialize hangcheck struct during driver load. Since we do the same after > recovering from a reset, this is extracted into a helper function. > > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Tomas Elf <tomas.elf@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_lrc.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- > 4 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 3f439a0..c5d1673 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -945,6 +945,16 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) > } > } > > +static void i915_hangcheck_init(struct drm_device *dev) > +{ > + int i; > + struct intel_engine_cs *engine; > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + for_each_engine(engine, dev_priv, i) > + intel_engine_init_hangcheck(engine); > +} > + > static int i915_workqueues_init(struct drm_i915_private *dev_priv) > { > /* > @@ -1233,6 +1243,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) > > i915_gem_load_init_fences(dev_priv); > > + i915_hangcheck_init(dev); This is tautological. If we are clearing the per-engine hangcheck in ring->init_hw() then we will do later anyway. So why now? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-18 20:48 ` Chris Wilson @ 2016-03-18 21:22 ` Arun Siluvery 2016-03-18 21:34 ` Chris Wilson 0 siblings, 1 reply; 15+ messages in thread From: Arun Siluvery @ 2016-03-18 21:22 UTC (permalink / raw) To: Chris Wilson, intel-gfx, Mika Kuoppala, Tomas Elf On 18/03/2016 20:48, Chris Wilson wrote: > On Fri, Mar 18, 2016 at 08:07:54PM +0000, Arun Siluvery wrote: >> From: Tomas Elf <tomas.elf@intel.com> >> >> Initialize hangcheck struct during driver load. Since we do the same after >> recovering from a reset, this is extracted into a helper function. >> >> Cc: Mika Kuoppala <mika.kuoppala@intel.com> >> Signed-off-by: Tomas Elf <tomas.elf@intel.com> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> >> --- >> drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/intel_lrc.c | 2 +- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- >> 4 files changed, 20 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c >> index 3f439a0..c5d1673 100644 >> --- a/drivers/gpu/drm/i915/i915_dma.c >> +++ b/drivers/gpu/drm/i915/i915_dma.c >> @@ -945,6 +945,16 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) >> } >> } >> >> +static void i915_hangcheck_init(struct drm_device *dev) >> +{ >> + int i; >> + struct intel_engine_cs *engine; >> + struct drm_i915_private *dev_priv = dev->dev_private; >> + >> + for_each_engine(engine, dev_priv, i) >> + intel_engine_init_hangcheck(engine); >> +} >> + >> static int i915_workqueues_init(struct drm_i915_private *dev_priv) >> { >> /* >> @@ -1233,6 +1243,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) >> >> i915_gem_load_init_fences(dev_priv); >> >> + i915_hangcheck_init(dev); > > This is tautological. If we are clearing the per-engine hangcheck in > ring->init_hw() then we will do later anyway. So why now? It was doing slightly more earlier but now it is not required. The helper function intel_engine_init_hangcheck() also doesn't add much value so this patch can be ignored. regards Arun > -Chris > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-18 21:22 ` Arun Siluvery @ 2016-03-18 21:34 ` Chris Wilson 0 siblings, 0 replies; 15+ messages in thread From: Chris Wilson @ 2016-03-18 21:34 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Tomas Elf, Mika Kuoppala On Fri, Mar 18, 2016 at 09:22:55PM +0000, Arun Siluvery wrote: > On 18/03/2016 20:48, Chris Wilson wrote: > >On Fri, Mar 18, 2016 at 08:07:54PM +0000, Arun Siluvery wrote: > >>From: Tomas Elf <tomas.elf@intel.com> > >> > >>Initialize hangcheck struct during driver load. Since we do the same after > >>recovering from a reset, this is extracted into a helper function. > >> > >>Cc: Mika Kuoppala <mika.kuoppala@intel.com> > >>Signed-off-by: Tomas Elf <tomas.elf@intel.com> > >>Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > >>--- > >> drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ > >> drivers/gpu/drm/i915/i915_drv.h | 1 + > >> drivers/gpu/drm/i915/intel_lrc.c | 2 +- > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- > >> 4 files changed, 20 insertions(+), 2 deletions(-) > >> > >>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > >>index 3f439a0..c5d1673 100644 > >>--- a/drivers/gpu/drm/i915/i915_dma.c > >>+++ b/drivers/gpu/drm/i915/i915_dma.c > >>@@ -945,6 +945,16 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) > >> } > >> } > >> > >>+static void i915_hangcheck_init(struct drm_device *dev) > >>+{ > >>+ int i; > >>+ struct intel_engine_cs *engine; > >>+ struct drm_i915_private *dev_priv = dev->dev_private; > >>+ > >>+ for_each_engine(engine, dev_priv, i) > >>+ intel_engine_init_hangcheck(engine); > >>+} > >>+ > >> static int i915_workqueues_init(struct drm_i915_private *dev_priv) > >> { > >> /* > >>@@ -1233,6 +1243,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) > >> > >> i915_gem_load_init_fences(dev_priv); > >> > >>+ i915_hangcheck_init(dev); > > > >This is tautological. If we are clearing the per-engine hangcheck in > >ring->init_hw() then we will do later anyway. So why now? > > It was doing slightly more earlier but now it is not required. The > helper function intel_engine_init_hangcheck() also doesn't add much > value so this patch can be ignored. The helper function is ok, it adds a little bit of documentation which is far more meaningful than memset(). I was just wondering if there was an actual requirement I missed for i915_driver_init_hw() to do so, or if there will be. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery 2016-03-18 20:48 ` Chris Wilson @ 2016-03-21 16:26 ` Arun Siluvery 2016-03-21 17:15 ` Chris Wilson 1 sibling, 1 reply; 15+ messages in thread From: Arun Siluvery @ 2016-03-21 16:26 UTC (permalink / raw) To: intel-gfx; +Cc: Tomas Elf, Mika Kuoppala From: Tomas Elf <tomas.elf@intel.com> Initialize hangcheck struct during driver load. Since we do the same after recovering from a reset, this is extracted into a helper function. v2: remove redundant hangcheck init during load as this is done when engines are initialized (Chris) Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f330a53..549a232 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2718,6 +2718,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_device *dev); extern int i915_reset(struct drm_device *dev); +extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3a23b95..40ef4ea 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1606,7 +1606,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) engine->next_context_status_buffer = next_context_status_buffer_hw; DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); return 0; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index df0ef5b..ce59850 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -555,6 +555,11 @@ static bool stop_ring(struct intel_engine_cs *engine) return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; } +void intel_engine_init_hangcheck(struct intel_engine_cs *engine) +{ + memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); +} + static int init_ring_common(struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; @@ -634,7 +639,7 @@ static int init_ring_common(struct intel_engine_cs *engine) ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; intel_ring_update_space(ringbuf); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); out: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2] drm/i915/tdr: Initialize hangcheck struct for each engine 2016-03-21 16:26 ` [PATCH v2] " Arun Siluvery @ 2016-03-21 17:15 ` Chris Wilson 0 siblings, 0 replies; 15+ messages in thread From: Chris Wilson @ 2016-03-21 17:15 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Tomas Elf, Mika Kuoppala On Mon, Mar 21, 2016 at 04:26:59PM +0000, Arun Siluvery wrote: > From: Tomas Elf <tomas.elf@intel.com> > > Initialize hangcheck struct during driver load. Since we do the same after > recovering from a reset, this is extracted into a helper function. > > v2: remove redundant hangcheck init during load as this is done when > engines are initialized (Chris) > > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Tomas Elf <tomas.elf@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery 2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery @ 2016-03-18 20:07 ` Arun Siluvery 2016-03-22 12:04 ` Mika Kuoppala 2016-03-18 20:07 ` [PATCH 3/3] drm/i915: Update i915.reset to handle engine resets Arun Siluvery ` (3 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Arun Siluvery @ 2016-03-18 20:07 UTC (permalink / raw) To: intel-gfx; +Cc: Tomas Elf, Mika Kuoppala In preparation for engine reset, the wedged argument of i915_handle_error() is extended to reflect as a mask of engines that are hung. This is further passed down to error state capture functions which are also updated. Engine reset recovery mechanism uses this mask and schedules recovery work for those particular engines. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++---- drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++-------- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 549a232..49ac065 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2735,7 +2735,7 @@ bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); /* i915_irq.c */ void i915_queue_hangcheck(struct drm_device *dev); __printf(3, 4) -void i915_handle_error(struct drm_device *dev, bool wedged, +void i915_handle_error(struct drm_device *dev, u32 engine_mask, const char *fmt, ...); extern void intel_irq_init(struct drm_i915_private *dev_priv); @@ -3321,7 +3321,7 @@ static inline void i915_error_state_buf_release( { kfree(eb->buf); } -void i915_capture_error_state(struct drm_device *dev, bool wedge, +void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, const char *error_msg); void i915_error_state_get(struct drm_device *dev, struct i915_error_state_file_priv *error_priv); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index db8600a..1f8ff06 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1301,7 +1301,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, static void i915_error_capture_msg(struct drm_device *dev, struct drm_i915_error_state *error, - bool wedged, + u32 engine_mask, const char *error_msg) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1324,7 +1324,7 @@ static void i915_error_capture_msg(struct drm_device *dev, scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, ", reason: %s, action: %s", error_msg, - wedged ? "reset" : "continue"); + engine_mask ? "reset" : "continue"); } static void i915_capture_gen_state(struct drm_i915_private *dev_priv, @@ -1347,7 +1347,7 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv, * out a structure which becomes available in debugfs for user level tools * to pick up. */ -void i915_capture_error_state(struct drm_device *dev, bool wedged, +void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, const char *error_msg) { static bool warned; @@ -1375,7 +1375,7 @@ void i915_capture_error_state(struct drm_device *dev, bool wedged, error->overlay = intel_overlay_capture_error_state(dev); error->display = intel_display_capture_error_state(dev); - i915_error_capture_msg(dev, error, wedged, error_msg); + i915_error_capture_msg(dev, error, engine_mask, error_msg); DRM_INFO("%s\n", error->error_msg); spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8f3e330..a55a7cc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2653,14 +2653,14 @@ static void i915_report_and_clear_eir(struct drm_device *dev) /** * i915_handle_error - handle a gpu error * @dev: drm device - * + * @engine_mask: mask representing engines that are hung * Do some basic checking of register state at error time and * dump it to the syslog. Also call i915_capture_error_state() to make * sure we get a record and make it available in debugfs. Fire a uevent * so userspace knows something bad happened (should trigger collection * of a ring dump etc.). */ -void i915_handle_error(struct drm_device *dev, bool wedged, +void i915_handle_error(struct drm_device *dev, u32 engine_mask, const char *fmt, ...) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -2671,10 +2671,10 @@ void i915_handle_error(struct drm_device *dev, bool wedged, vscnprintf(error_msg, sizeof(error_msg), fmt, args); va_end(args); - i915_capture_error_state(dev, wedged, error_msg); + i915_capture_error_state(dev, engine_mask, error_msg); i915_report_and_clear_eir(dev); - if (wedged) { + if (engine_mask) { atomic_or(I915_RESET_IN_PROGRESS_FLAG, &dev_priv->gpu_error.reset_counter); @@ -3033,7 +3033,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) */ tmp = I915_READ_CTL(engine); if (tmp & RING_WAIT) { - i915_handle_error(dev, false, + i915_handle_error(dev, 0, "Kicking stuck wait on %s", engine->name); I915_WRITE_CTL(engine, tmp); @@ -3045,7 +3045,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) default: return HANGCHECK_HUNG; case 1: - i915_handle_error(dev, false, + i915_handle_error(dev, 0, "Kicking stuck semaphore on %s", engine->name); I915_WRITE_CTL(engine, tmp); @@ -3189,12 +3189,12 @@ static void i915_hangcheck_elapsed(struct work_struct *work) DRM_INFO("%s on %s\n", stuck[i] ? "stuck" : "no progress", engine->name); - rings_hung++; + rings_hung |= intel_engine_flag(engine); } } if (rings_hung) { - i915_handle_error(dev, true, "Ring hung"); + i915_handle_error(dev, rings_hung, "Engine(s) hung"); goto out; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines 2016-03-18 20:07 ` [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines Arun Siluvery @ 2016-03-22 12:04 ` Mika Kuoppala 0 siblings, 0 replies; 15+ messages in thread From: Mika Kuoppala @ 2016-03-22 12:04 UTC (permalink / raw) To: Arun Siluvery, intel-gfx; +Cc: Tomas Elf Arun Siluvery <arun.siluvery@linux.intel.com> writes: > [ text/plain ] > In preparation for engine reset, the wedged argument of i915_handle_error() > is extended to reflect as a mask of engines that are hung. This is further > passed down to error state capture functions which are also updated. > > Engine reset recovery mechanism uses this mask and schedules recovery work > for those particular engines. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Tomas Elf <tomas.elf@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++---- > drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++-------- > 3 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 549a232..49ac065 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2735,7 +2735,7 @@ bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); > /* i915_irq.c */ > void i915_queue_hangcheck(struct drm_device *dev); > __printf(3, 4) > -void i915_handle_error(struct drm_device *dev, bool wedged, > +void i915_handle_error(struct drm_device *dev, u32 engine_mask, > const char *fmt, ...); > > extern void intel_irq_init(struct drm_i915_private *dev_priv); > @@ -3321,7 +3321,7 @@ static inline void i915_error_state_buf_release( > { > kfree(eb->buf); > } > -void i915_capture_error_state(struct drm_device *dev, bool wedge, > +void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, > const char *error_msg); > void i915_error_state_get(struct drm_device *dev, > struct i915_error_state_file_priv *error_priv); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index db8600a..1f8ff06 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1301,7 +1301,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > > static void i915_error_capture_msg(struct drm_device *dev, > struct drm_i915_error_state *error, > - bool wedged, > + u32 engine_mask, > const char *error_msg) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -1324,7 +1324,7 @@ static void i915_error_capture_msg(struct drm_device *dev, > scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, > ", reason: %s, action: %s", > error_msg, > - wedged ? "reset" : "continue"); > + engine_mask ? "reset" : "continue"); > } > > static void i915_capture_gen_state(struct drm_i915_private *dev_priv, > @@ -1347,7 +1347,7 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv, > * out a structure which becomes available in debugfs for user level tools > * to pick up. > */ > -void i915_capture_error_state(struct drm_device *dev, bool wedged, > +void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, > const char *error_msg) > { > static bool warned; > @@ -1375,7 +1375,7 @@ void i915_capture_error_state(struct drm_device *dev, bool wedged, > error->overlay = intel_overlay_capture_error_state(dev); > error->display = intel_display_capture_error_state(dev); > > - i915_error_capture_msg(dev, error, wedged, error_msg); > + i915_error_capture_msg(dev, error, engine_mask, error_msg); > DRM_INFO("%s\n", error->error_msg); > > spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8f3e330..a55a7cc 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2653,14 +2653,14 @@ static void i915_report_and_clear_eir(struct drm_device *dev) > /** > * i915_handle_error - handle a gpu error > * @dev: drm device > - * > + * @engine_mask: mask representing engines that are hung > * Do some basic checking of register state at error time and > * dump it to the syslog. Also call i915_capture_error_state() to make > * sure we get a record and make it available in debugfs. Fire a uevent > * so userspace knows something bad happened (should trigger collection > * of a ring dump etc.). > */ > -void i915_handle_error(struct drm_device *dev, bool wedged, > +void i915_handle_error(struct drm_device *dev, u32 engine_mask, > const char *fmt, ...) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -2671,10 +2671,10 @@ void i915_handle_error(struct drm_device *dev, bool wedged, > vscnprintf(error_msg, sizeof(error_msg), fmt, args); > va_end(args); > > - i915_capture_error_state(dev, wedged, error_msg); > + i915_capture_error_state(dev, engine_mask, error_msg); > i915_report_and_clear_eir(dev); > > - if (wedged) { > + if (engine_mask) { > atomic_or(I915_RESET_IN_PROGRESS_FLAG, > &dev_priv->gpu_error.reset_counter); > > @@ -3033,7 +3033,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) > */ > tmp = I915_READ_CTL(engine); > if (tmp & RING_WAIT) { > - i915_handle_error(dev, false, > + i915_handle_error(dev, 0, > "Kicking stuck wait on %s", > engine->name); > I915_WRITE_CTL(engine, tmp); > @@ -3045,7 +3045,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) > default: > return HANGCHECK_HUNG; > case 1: > - i915_handle_error(dev, false, > + i915_handle_error(dev, 0, > "Kicking stuck semaphore on %s", > engine->name); > I915_WRITE_CTL(engine, tmp); > @@ -3189,12 +3189,12 @@ static void i915_hangcheck_elapsed(struct work_struct *work) > DRM_INFO("%s on %s\n", > stuck[i] ? "stuck" : "no progress", > engine->name); > - rings_hung++; > + rings_hung |= intel_engine_flag(engine); We can change the int to u32 when we rename rings_hung to engines_hung. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > } > } > > if (rings_hung) { > - i915_handle_error(dev, true, "Ring hung"); > + i915_handle_error(dev, rings_hung, "Engine(s) hung"); > goto out; > } > > -- > 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/3] drm/i915: Update i915.reset to handle engine resets 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery 2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery 2016-03-18 20:07 ` [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines Arun Siluvery @ 2016-03-18 20:07 ` Arun Siluvery 2016-03-21 11:49 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 15+ messages in thread From: Arun Siluvery @ 2016-03-18 20:07 UTC (permalink / raw) To: intel-gfx; +Cc: Mika Kuoppala In preparation for engine reset work update this parameter to handle more than one type of reset. Default at the moment is still full gpu reset. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_params.c | 6 +++--- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 1779f02..e4f9d6a 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -45,7 +45,7 @@ struct i915_params i915 __read_mostly = { .fastboot = 0, .prefault_disable = 0, .load_detect_test = 0, - .reset = true, + .reset = 1, .invert_brightness = 0, .disable_display = 0, .enable_cmd_parser = 1, @@ -108,8 +108,8 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type, "Override/Ignore selection of SDVO panel mode in the VBT " "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); -module_param_named_unsafe(reset, i915.reset, bool, 0600); -MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); +module_param_named_unsafe(reset, i915.reset, int, 0600); +MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset [default], 2=engine reset)"); module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644); MODULE_PARM_DESC(enable_hangcheck, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 02bc278..9b13c10 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -34,6 +34,7 @@ struct i915_params { int lvds_channel_mode; int panel_use_ssc; int vbt_sdvo_panel_type; + int reset; int enable_rc6; int enable_dc; int enable_fbc; @@ -55,7 +56,6 @@ struct i915_params { bool fastboot; bool prefault_disable; bool load_detect_test; - bool reset; bool disable_display; bool enable_guc_submission; bool verbose_state_checks; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery ` (2 preceding siblings ...) 2016-03-18 20:07 ` [PATCH 3/3] drm/i915: Update i915.reset to handle engine resets Arun Siluvery @ 2016-03-21 11:49 ` Patchwork 2016-03-21 16:13 ` Arun Siluvery 2016-03-21 16:29 ` Arun Siluvery 2016-03-22 9:07 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches (rev2) Patchwork 2016-03-22 13:09 ` [PATCH 0/3] Gen8 Engine reset preparatory patches Mika Kuoppala 5 siblings, 2 replies; 15+ messages in thread From: Patchwork @ 2016-03-21 11:49 UTC (permalink / raw) To: arun.siluvery; +Cc: intel-gfx == Series Details == Series: Gen8 Engine reset preparatory patches URL : https://patchwork.freedesktop.org/series/4649/ State : warning == Summary == Series 4649v1 Gen8 Engine reset preparatory patches http://patchwork.freedesktop.org/api/1.0/series/4649/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default-s3: dmesg-warn -> PASS (bsw-nuc-2) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: fail -> PASS (byt-nuc) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-a: dmesg-warn -> PASS (snb-x220t) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> DMESG-WARN (byt-nuc) Subgroup basic-rte: pass -> DMESG-WARN (snb-x220t) pass -> DMESG-WARN (snb-dellxps) bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21 bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37 byt-nuc total:194 pass:158 dwarn:1 dfail:0 fail:0 skip:35 hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22 hsw-gt2 total:63 pass:56 dwarn:1 dfail:0 fail:0 skip:5 ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63 ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25 skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 snb-dellxps total:194 pass:158 dwarn:2 dfail:0 fail:0 skip:34 snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1651/ e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest 7c0f4608adca88e892b960731daa63a7e517ae6a drm/i915: Update i915.reset to handle engine resets 6ed4bf4ebc4670b287988f96fa64ea0dfd4a8203 drm/i915/tdr: Prepare error handler to accept mask of hung engines 0bac550038d55cbdf4ccaad57d371a41b22f90e7 drm/i915/tdr: Initialize hangcheck struct for each engine _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches 2016-03-21 11:49 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches Patchwork @ 2016-03-21 16:13 ` Arun Siluvery 2016-03-21 16:29 ` Arun Siluvery 1 sibling, 0 replies; 15+ messages in thread From: Arun Siluvery @ 2016-03-21 16:13 UTC (permalink / raw) To: intel-gfx On 21/03/2016 11:49, Patchwork wrote: > == Series Details == > > Series: Gen8 Engine reset preparatory patches > URL : https://patchwork.freedesktop.org/series/4649/ > State : warning > > == Summary == > > Series 4649v1 Gen8 Engine reset preparatory patches > http://patchwork.freedesktop.org/api/1.0/series/4649/revisions/1/mbox/ > > Test gem_ringfill: > Subgroup basic-default-s3: > dmesg-warn -> PASS (bsw-nuc-2) > Test kms_flip: > Subgroup basic-flip-vs-wf_vblank: > fail -> PASS (byt-nuc) > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-a: > dmesg-warn -> PASS (snb-x220t) > Test pm_rpm: > Subgroup basic-pci-d3-state: > pass -> DMESG-WARN (byt-nuc) unrelated and known issue, Bug 94164 - [BAT BYT/BSW] pm_rpm@basic-pci-d3-state *ERROR* Unclaimed access detected prior to suspending https://bugs.freedesktop.org/show_bug.cgi?id=94164 > Subgroup basic-rte: > pass -> DMESG-WARN (snb-x220t) > pass -> DMESG-WARN (snb-dellxps) unrelated and known issue, Bug 94349 - [SNB HSW BDW BAT IGT] igt/kms_pipe_crc_basic: Device suspended during HW access https://bugs.freedesktop.org/show_bug.cgi?id=94349 regards Arun > > bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12 > bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21 > bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37 > byt-nuc total:194 pass:158 dwarn:1 dfail:0 fail:0 skip:35 > hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22 > hsw-gt2 total:63 pass:56 dwarn:1 dfail:0 fail:0 skip:5 > ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63 > ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25 > skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 > snb-dellxps total:194 pass:158 dwarn:2 dfail:0 fail:0 skip:34 > snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33 > > Results at /archive/results/CI_IGT_test/Patchwork_1651/ > > e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest > 7c0f4608adca88e892b960731daa63a7e517ae6a drm/i915: Update i915.reset to handle engine resets > 6ed4bf4ebc4670b287988f96fa64ea0dfd4a8203 drm/i915/tdr: Prepare error handler to accept mask of hung engines > 0bac550038d55cbdf4ccaad57d371a41b22f90e7 drm/i915/tdr: Initialize hangcheck struct for each engine > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches 2016-03-21 11:49 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches Patchwork 2016-03-21 16:13 ` Arun Siluvery @ 2016-03-21 16:29 ` Arun Siluvery 1 sibling, 0 replies; 15+ messages in thread From: Arun Siluvery @ 2016-03-21 16:29 UTC (permalink / raw) To: intel-gfx On 21/03/2016 11:49, Patchwork wrote: > == Series Details == > > Series: Gen8 Engine reset preparatory patches > URL : https://patchwork.freedesktop.org/series/4649/ > State : warning > > == Summary == > > Series 4649v1 Gen8 Engine reset preparatory patches > http://patchwork.freedesktop.org/api/1.0/series/4649/revisions/1/mbox/ > > Test gem_ringfill: > Subgroup basic-default-s3: > dmesg-warn -> PASS (bsw-nuc-2) > Test kms_flip: > Subgroup basic-flip-vs-wf_vblank: > fail -> PASS (byt-nuc) > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-a: > dmesg-warn -> PASS (snb-x220t) > Test pm_rpm: > Subgroup basic-pci-d3-state: > pass -> DMESG-WARN (byt-nuc) unrelated and known issue, Bug 94164 - [BAT BYT/BSW] pm_rpm@basic-pci-d3-state *ERROR* Unclaimed access detected prior to suspending https://bugs.freedesktop.org/show_bug.cgi?id=94164 > Subgroup basic-rte: > pass -> DMESG-WARN (snb-x220t) > pass -> DMESG-WARN (snb-dellxps) unrelated and known issue, Bug 94349 - [SNB HSW BDW BAT IGT] igt/kms_pipe_crc_basic: Device suspended during HW access https://bugs.freedesktop.org/show_bug.cgi?id=94349 previous reply didn't made it to the list, sending again. regards Arun > > bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12 > bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21 > bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37 > byt-nuc total:194 pass:158 dwarn:1 dfail:0 fail:0 skip:35 > hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22 > hsw-gt2 total:63 pass:56 dwarn:1 dfail:0 fail:0 skip:5 > ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63 > ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25 > skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 > snb-dellxps total:194 pass:158 dwarn:2 dfail:0 fail:0 skip:34 > snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33 > > Results at /archive/results/CI_IGT_test/Patchwork_1651/ > > e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest > 7c0f4608adca88e892b960731daa63a7e517ae6a drm/i915: Update i915.reset to handle engine resets > 6ed4bf4ebc4670b287988f96fa64ea0dfd4a8203 drm/i915/tdr: Prepare error handler to accept mask of hung engines > 0bac550038d55cbdf4ccaad57d371a41b22f90e7 drm/i915/tdr: Initialize hangcheck struct for each engine > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches (rev2) 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery ` (3 preceding siblings ...) 2016-03-21 11:49 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches Patchwork @ 2016-03-22 9:07 ` Patchwork 2016-03-22 13:09 ` [PATCH 0/3] Gen8 Engine reset preparatory patches Mika Kuoppala 5 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2016-03-22 9:07 UTC (permalink / raw) To: arun.siluvery; +Cc: intel-gfx == Series Details == Series: Gen8 Engine reset preparatory patches (rev2) URL : https://patchwork.freedesktop.org/series/4649/ State : warning == Summary == Series 4649v2 Gen8 Engine reset preparatory patches http://patchwork.freedesktop.org/api/1.0/series/4649/revisions/2/mbox/ Test kms_flip: Subgroup basic-flip-vs-dpms: dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (hsw-brixbox) Subgroup basic-plain-flip: dmesg-warn -> PASS (bdw-ultra) Test kms_force_connector_basic: Subgroup force-connector-state: pass -> SKIP (ivb-t430s) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-b: pass -> SKIP (hsw-brixbox) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> PASS (bsw-nuc-2) Test pm_rpm: Subgroup basic-pci-d3-state: fail -> DMESG-FAIL (snb-x220t) pass -> DMESG-WARN (snb-dellxps) Subgroup basic-rte: pass -> DMESG-WARN (bsw-nuc-2) dmesg-warn -> PASS (snb-dellxps) dmesg-warn -> PASS (byt-nuc) UNSTABLE bdw-nuci7 total:192 pass:180 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultra total:192 pass:171 dwarn:0 dfail:0 fail:0 skip:21 bsw-nuc-2 total:192 pass:154 dwarn:1 dfail:0 fail:0 skip:37 byt-nuc total:192 pass:157 dwarn:0 dfail:0 fail:0 skip:35 hsw-brixbox total:192 pass:168 dwarn:1 dfail:0 fail:0 skip:23 ilk-hp8440p total:192 pass:129 dwarn:0 dfail:0 fail:0 skip:63 ivb-t430s total:192 pass:166 dwarn:0 dfail:0 fail:0 skip:26 skl-i5k-2 total:192 pass:169 dwarn:0 dfail:0 fail:0 skip:23 skl-i7k-2 total:192 pass:169 dwarn:0 dfail:0 fail:0 skip:23 snb-dellxps total:192 pass:157 dwarn:1 dfail:0 fail:0 skip:34 snb-x220t total:192 pass:157 dwarn:1 dfail:1 fail:0 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1666/ 4b39223f6e3bef4dfa678f7239dcd87c38e20e96 drm-intel-nightly: 2016y-03m-21d-18h-43m-18s UTC integration manifest 5a5d13e93c178526e252c1d16d1a1a07b5ffbf5e drm/i915: Update i915.reset to handle engine resets b1f9c41920a13427d6c34854f185f651d5906333 drm/i915/tdr: Prepare error handler to accept mask of hung engines 8c44cb0ee612be9e037d40f6391ad622a76d2b36 drm/i915/tdr: Initialize hangcheck struct for each engine _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/3] Gen8 Engine reset preparatory patches 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery ` (4 preceding siblings ...) 2016-03-22 9:07 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches (rev2) Patchwork @ 2016-03-22 13:09 ` Mika Kuoppala 5 siblings, 0 replies; 15+ messages in thread From: Mika Kuoppala @ 2016-03-22 13:09 UTC (permalink / raw) To: Arun Siluvery, intel-gfx Arun Siluvery <arun.siluvery@linux.intel.com> writes: > [ text/plain ] > First batch of prep patches for Engine reset feature available from Gen8 > onwards. The reset code is recently prep'd to support this feature, now > others can follow now. > > Arun Siluvery (2): > drm/i915/tdr: Prepare error handler to accept mask of hung engines > drm/i915: Update i915.reset to handle engine resets > > Tomas Elf (1): > drm/i915/tdr: Initialize hangcheck struct for each engine > Patches 1/3 [v2] and 2/3 pushed. Thanks for patches and review. -Mika > drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 5 +++-- > drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++---- > drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++-------- > drivers/gpu/drm/i915/i915_params.c | 6 +++--- > drivers/gpu/drm/i915/i915_params.h | 2 +- > drivers/gpu/drm/i915/intel_lrc.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- > 8 files changed, 38 insertions(+), 20 deletions(-) > > -- > 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2016-03-22 13:11 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-03-18 20:07 [PATCH 0/3] Gen8 Engine reset preparatory patches Arun Siluvery 2016-03-18 20:07 ` [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine Arun Siluvery 2016-03-18 20:48 ` Chris Wilson 2016-03-18 21:22 ` Arun Siluvery 2016-03-18 21:34 ` Chris Wilson 2016-03-21 16:26 ` [PATCH v2] " Arun Siluvery 2016-03-21 17:15 ` Chris Wilson 2016-03-18 20:07 ` [PATCH 2/3] drm/i915/tdr: Prepare error handler to accept mask of hung engines Arun Siluvery 2016-03-22 12:04 ` Mika Kuoppala 2016-03-18 20:07 ` [PATCH 3/3] drm/i915: Update i915.reset to handle engine resets Arun Siluvery 2016-03-21 11:49 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches Patchwork 2016-03-21 16:13 ` Arun Siluvery 2016-03-21 16:29 ` Arun Siluvery 2016-03-22 9:07 ` ✗ Fi.CI.BAT: warning for Gen8 Engine reset preparatory patches (rev2) Patchwork 2016-03-22 13:09 ` [PATCH 0/3] Gen8 Engine reset preparatory patches Mika Kuoppala
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