[Qemu-devel] [PATCH v3 00/10] ppc: preparing pnv landing

[Qemu-devel] [PATCH v3 00/10] ppc: preparing pnv landing

[Cédric Le Goater]

Hello,

This is a first mini-serie of patches adding support for new ppc SPRs.
They were taken from Ben's larger patchset adding the ppc powernv
platform and they should already be useful for the pseries guest
migration.

Initial patches come from :

	https://github.com/ozbenh/qemu/commits/powernv

The changes are mostly due to the rebase on Dave's 2.6 branch:

	https://github.com/dgibson/qemu/commits/ppc-for-2.6 ppc-for-2.6-20160316

A couple more are bisect and checkpatch fixes and finally some patches
were merge to reduce the noise.

Changes since v2:

  - removed LPCR setting in patch 04/10 "ppc: Create cpu_ppc_set_papr() helper"
  - fixed has_iamr condition in gen_spr_amr()

Changes since v1:

  - dropped patches which are not fixes for 2.6 :
 
   	ppc: Add number of threads per core to the processor definition
  	ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
 	ppc: Better figure out if processor has HV mode
  	ppc: Add placeholder SPRs for DPDES and DHDES on P8
  	ppc: SPURR & PURR are HV writeable and privileged
  	ppc: Add dummy write to VTB
  	ppc: Add dummy POWER8 MPPR register
	
  - fixed else if condition in gen_op_mfspr()
  - removed all hunks except those related to AMOR and DAWR*


The patchset is also available here: 

	https://github.com/legoater/qemu/commits/for-2.6

It was quickly tested with a pseries guest using KVM and TCG.

Thanks,

C.


Benjamin Herrenschmidt (10):
  ppc: Update SPR definitions
  ppc: Add macros to register hypervisor mode SPRs
  ppc: Add a bunch of hypervisor SPRs to Book3s
  ppc: Create cpu_ppc_set_papr() helper
  ppc: Add dummy SPR_IC for POWER8
  ppc: Initialize AMOR in PAPR mode
  ppc: Fix writing to AMR/UAMOR
  ppc: Add POWER8 IAMR register
  ppc: Add dummy CIABR SPR
  ppc: A couple more dummy POWER8 Book4 regs

 hw/ppc/spapr.c              |  11 +-
 target-ppc/cpu.h            |  61 +++++++++--
 target-ppc/translate.c      |  26 +++--
 target-ppc/translate_init.c | 241 ++++++++++++++++++++++++++++++++++++++++----
 4 files changed, 291 insertions(+), 48 deletions(-)

-- 
2.1.4

[Qemu-devel] [PATCH v3 01/10] ppc: Update SPR definitions

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Add definitions for additional SPR numbers and SPR bit definitions
that will be relevant for subsequent improvements to POWER8 emulation

Also fix the definition of LPIDR which was incorrect (and is different
for server and embedded).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/cpu.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 7 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8d90d862de17..9ce301f18922 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -474,9 +474,17 @@ struct ppc_slb_t {
 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 
-#define LPCR_ILE (1 << (63-38))
-#define LPCR_AIL_SHIFT (63-40)      /* Alternate interrupt location */
-#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
+/* LPCR bits */
+#define LPCR_VPM0         (1ull << (63 - 0))
+#define LPCR_VPM1         (1ull << (63 - 1))
+#define LPCR_ISL          (1ull << (63 - 2))
+#define LPCR_KBV          (1ull << (63 - 3))
+#define LPCR_ILE          (1ull << (63 - 38))
+#define LPCR_MER          (1ull << (63 - 52))
+#define LPCR_LPES0        (1ull << (63 - 60))
+#define LPCR_LPES1        (1ull << (63 - 61))
+#define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
+#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 
 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
@@ -1381,6 +1389,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_MPC_ICTRL         (0x09E)
 #define SPR_MPC_BAR           (0x09F)
 #define SPR_PSPB              (0x09F)
+#define SPR_DAWR              (0x0B4)
+#define SPR_RPR               (0x0BA)
+#define SPR_DAWRX             (0x0BC)
+#define SPR_HFSCR             (0x0BE)
 #define SPR_VRSAVE            (0x100)
 #define SPR_USPRG0            (0x100)
 #define SPR_USPRG1            (0x101)
@@ -1435,19 +1447,25 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_HSRR1             (0x13B)
 #define SPR_BOOKE_IAC4        (0x13B)
 #define SPR_BOOKE_DAC1        (0x13C)
-#define SPR_LPIDR             (0x13D)
+#define SPR_MMCRH             (0x13C)
 #define SPR_DABR2             (0x13D)
 #define SPR_BOOKE_DAC2        (0x13D)
+#define SPR_TFMR              (0x13D)
 #define SPR_BOOKE_DVC1        (0x13E)
 #define SPR_LPCR              (0x13E)
 #define SPR_BOOKE_DVC2        (0x13F)
+#define SPR_LPIDR             (0x13F)
 #define SPR_BOOKE_TSR         (0x150)
+#define SPR_HMER              (0x150)
+#define SPR_HMEER             (0x151)
 #define SPR_PCR               (0x152)
+#define SPR_BOOKE_LPIDR       (0x152)
 #define SPR_BOOKE_TCR         (0x154)
 #define SPR_BOOKE_TLB0PS      (0x158)
 #define SPR_BOOKE_TLB1PS      (0x159)
 #define SPR_BOOKE_TLB2PS      (0x15A)
 #define SPR_BOOKE_TLB3PS      (0x15B)
+#define SPR_AMOR              (0x15D)
 #define SPR_BOOKE_MAS7_MAS3   (0x174)
 #define SPR_BOOKE_IVOR0       (0x190)
 #define SPR_BOOKE_IVOR1       (0x191)
@@ -1667,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_RCPU_L2U_RA3      (0x32B)
 #define SPR_TAR               (0x32F)
 #define SPR_VTB               (0x351)
+#define SPR_MMCRC             (0x353)
 #define SPR_440_INV0          (0x370)
 #define SPR_440_INV1          (0x371)
 #define SPR_440_INV2          (0x372)
@@ -1705,6 +1724,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_440_DVLIM         (0x398)
 #define SPR_750_WPAR          (0x399)
 #define SPR_440_IVLIM         (0x399)
+#define SPR_TSCR              (0x399)
 #define SPR_750_DMAU          (0x39A)
 #define SPR_750_DMAL          (0x39B)
 #define SPR_440_RSTCFG        (0x39B)
@@ -1879,9 +1899,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
 
 /* HID0 bits */
-#define HID0_DEEPNAP        (1 << 24)
-#define HID0_DOZE           (1 << 23)
-#define HID0_NAP            (1 << 22)
+#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
+#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
+#define HID0_NAP            (1 << 22)           /* pre-2.06 */
+#define HID0_HILE           (1ull << (63 - 19)) /* POWER8 */
 
 /*****************************************************************************/
 /* PowerPC Instructions types definitions                                    */
@@ -2230,6 +2251,25 @@ enum {
     PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
 };
 
+/* HMER/HMEER */
+enum {
+    HMER_MALFUNCTION_ALERT      = 1ull << (63 - 0),
+    HMER_PROC_RECV_DONE         = 1ull << (63 - 2),
+    HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
+    HMER_TFAC_ERROR             = 1ull << (63 - 4),
+    HMER_TFMR_PARITY_ERROR      = 1ull << (63 - 5),
+    HMER_XSCOM_FAIL             = 1ull << (63 - 8),
+    HMER_XSCOM_DONE             = 1ull << (63 - 9),
+    HMER_PROC_RECV_AGAIN        = 1ull << (63 - 11),
+    HMER_WARN_RISE              = 1ull << (63 - 14),
+    HMER_WARN_FALL              = 1ull << (63 - 15),
+    HMER_SCOM_FIR_HMI           = 1ull << (63 - 16),
+    HMER_TRIG_FIR_HMI           = 1ull << (63 - 17),
+    HMER_HYP_RESOURCE_ERR       = 1ull << (63 - 20),
+    HMER_XSCOM_STATUS_MASK      = 7ull << (63 - 23),
+    HMER_XSCOM_STATUS_LSH       = (63 - 23),
+};
+
 /*****************************************************************************/
 
 static inline target_ulong cpu_read_xer(CPUPPCState *env)
-- 
2.1.4

[Qemu-devel] [PATCH v3 02/10] ppc: Add macros to register hypervisor mode SPRs

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The current set of spr_register_* macros only take the user and
supervisor function pointers. To make the transition easy, we
don't change that but we add "_hv" variants that can be used to
register all 3 sets.

To simplify the transition, users of the "old" macro will set the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: fixed else if condition in gen_op_mfspr() ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
 target-ppc/translate.c      | 26 ++++++++++++++++----------
 target-ppc/translate_init.c | 35 +++++++++++++++++++++++++++++++----
 2 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e402ff920314..6f0e7b4face6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4282,14 +4282,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
     uint32_t sprn = SPR(ctx->opcode);
 
-#if !defined(CONFIG_USER_ONLY)
-    if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+    read_cb = ctx->spr_cb[sprn].uea_read;
+#else
+    if (ctx->pr) {
+        read_cb = ctx->spr_cb[sprn].uea_read;
+    } else if (ctx->hv) {
         read_cb = ctx->spr_cb[sprn].hea_read;
-    else if (!ctx->pr)
+    } else {
         read_cb = ctx->spr_cb[sprn].oea_read;
-    else
+    }
 #endif
-        read_cb = ctx->spr_cb[sprn].uea_read;
     if (likely(read_cb != NULL)) {
         if (likely(read_cb != SPR_NOACCESS)) {
             (*read_cb)(ctx, rD(ctx->opcode), sprn);
@@ -4437,14 +4440,17 @@ static void gen_mtspr(DisasContext *ctx)
     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
     uint32_t sprn = SPR(ctx->opcode);
 
-#if !defined(CONFIG_USER_ONLY)
-    if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+    write_cb = ctx->spr_cb[sprn].uea_write;
+#else
+    if (ctx->pr) {
+        write_cb = ctx->spr_cb[sprn].uea_write;
+    } else if (ctx->hv) {
         write_cb = ctx->spr_cb[sprn].hea_write;
-    else if (!ctx->pr)
+    } else {
         write_cb = ctx->spr_cb[sprn].oea_write;
-    else
+    }
 #endif
-        write_cb = ctx->spr_cb[sprn].uea_write;
     if (likely(write_cb != NULL)) {
         if (likely(write_cb != SPR_NOACCESS)) {
             (*write_cb)(ctx, sprn, rS(ctx->opcode));
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fb206aff29ad..6a11b41206e5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -579,17 +579,33 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
                          oea_read, oea_write, one_reg_id, initial_value)       \
     _spr_register(env, num, name, uea_read, uea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
+    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 #else
 #if !defined(CONFIG_KVM)
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
-                         oea_read, oea_write, one_reg_id, initial_value) \
+                         oea_read, oea_write, one_reg_id, initial_value)       \
+    _spr_register(env, num, name, uea_read, uea_write,                         \
+                  oea_read, oea_write, oea_read, oea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
     _spr_register(env, num, name, uea_read, uea_write,                         \
-                  oea_read, oea_write, initial_value)
+                  oea_read, oea_write, hea_read, hea_write, initial_value)
 #else
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
-                         oea_read, oea_write, one_reg_id, initial_value) \
+                         oea_read, oea_write, one_reg_id, initial_value)       \
+    _spr_register(env, num, name, uea_read, uea_write,                         \
+                  oea_read, oea_write, oea_read, oea_write,                    \
+                  one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
     _spr_register(env, num, name, uea_read, uea_write,                         \
-                  oea_read, oea_write, one_reg_id, initial_value)
+                  oea_read, oea_write, hea_read, hea_write,                    \
+                  one_reg_id, initial_value)
 #endif
 #endif
 
@@ -598,6 +614,13 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
     spr_register_kvm(env, num, name, uea_read, uea_write,                      \
                      oea_read, oea_write, 0, initial_value)
 
+#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
+                        oea_read, oea_write, hea_read, hea_write,              \
+                        initial_value)                                         \
+    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
+                        oea_read, oea_write, hea_read, hea_write,              \
+                        0, initial_value)
+
 static inline void _spr_register(CPUPPCState *env, int num,
                                  const char *name,
                                  void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
@@ -606,6 +629,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
 
                                  void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
                                  void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
+                                 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
+                                 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
 #endif
 #if defined(CONFIG_KVM)
                                  uint64_t one_reg_id,
@@ -633,6 +658,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
 #if !defined(CONFIG_USER_ONLY)
     spr->oea_read = oea_read;
     spr->oea_write = oea_write;
+    spr->hea_read = hea_read;
+    spr->hea_write = hea_write;
 #endif
 #if defined(CONFIG_KVM)
     spr->one_reg_id = one_reg_id,
-- 
2.1.4

[Qemu-devel] [PATCH v3 03/10] ppc: Add a bunch of hypervisor SPRs to Book3s

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

We don't give them a KVM reg number to most of the registers yet as no
current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
number is needed since this register can be set by the guest via the
H_SET_MODE hypercall.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs'
      changed the commit log with a proposal of Thomas Huth
      removed all hunks except those related to AMOR and DAWR* ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate_init.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6a11b41206e5..4cb3dd5076c1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_UAMOR, 0);
+    spr_register_hv(env, SPR_AMOR, "AMOR",
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    &spr_read_generic, &spr_write_generic,
+                    0);
 #endif /* !CONFIG_USER_ONLY */
 }
 #endif /* TARGET_PPC64 */
@@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
                      KVM_REG_PPC_DABRX, 0x00000000);
 }
 
+static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+{
+    spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        &spr_read_generic, &spr_write_generic,
+                        KVM_REG_PPC_DAWR, 0x00000000);
+    spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        &spr_read_generic, &spr_write_generic,
+                        KVM_REG_PPC_DAWRX, 0x00000000);
+}
+
 static void gen_spr_970_dbg(CPUPPCState *env)
 {
     /* Breakpoints */
@@ -7960,6 +7979,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
     }
     if (version < BOOK3S_CPU_POWER8) {
         gen_spr_book3s_dbg(env);
+    } else {
+        gen_spr_book3s_207_dbg(env);
     }
 #if !defined(CONFIG_USER_ONLY)
     switch (version) {
-- 
2.1.4

[Qemu-devel] [PATCH v3 04/10] ppc: Create cpu_ppc_set_papr() helper

[Cédric Le Goater]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=a, Size: 3164 bytes --]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: removed LPCR setting ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---

 Changes since v2:

 - removed LPCR setting

 hw/ppc/spapr.c              |   11 ++---------
 target-ppc/cpu.h            |    1 +
 target-ppc/translate_init.c |   23 ++++++++++++++++++++++-
 3 files changed, 25 insertions(+), 10 deletions(-)

Index: qemu-dgibson-for-2.6.git/hw/ppc/spapr.c
===================================================================
--- qemu-dgibson-for-2.6.git.orig/hw/ppc/spapr.c
+++ qemu-dgibson-for-2.6.git/hw/ppc/spapr.c
@@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineS
     /* Set time-base frequency to 512 MHz */
     cpu_ppc_tb_init(env, TIMEBASE_FREQ);
 
-    /* PAPR always has exception vectors in RAM not ROM. To ensure this,
-     * MSR[IP] should never be set.
-     */
-    env->msr_mask &= ~(1 << 6);
-
-    /* Tell KVM that we're in PAPR mode */
-    if (kvm_enabled()) {
-        kvmppc_set_papr(cpu);
-    }
+    /* Enable PAPR mode in TCG or KVM */
+    cpu_ppc_set_papr(cpu);
 
     if (cpu->max_compat) {
         Error *local_err = NULL;
Index: qemu-dgibson-for-2.6.git/target-ppc/cpu.h
===================================================================
--- qemu-dgibson-for-2.6.git.orig/target-ppc/cpu.h
+++ qemu-dgibson-for-2.6.git/target-ppc/cpu.h
@@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env,
 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 void ppc_tlb_invalidate_all (CPUPPCState *env);
 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+void cpu_ppc_set_papr(PowerPCCPU *cpu);
 #endif
 #endif
 
Index: qemu-dgibson-for-2.6.git/target-ppc/translate_init.c
===================================================================
--- qemu-dgibson-for-2.6.git.orig/target-ppc/translate_init.c
+++ qemu-dgibson-for-2.6.git/target-ppc/translate_init.c
@@ -8380,8 +8380,29 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc,
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
 }
-#endif /* defined (TARGET_PPC64) */
 
+#if !defined(CONFIG_USER_ONLY)
+
+void cpu_ppc_set_papr(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    /* PAPR always has exception vectors in RAM not ROM. To ensure this,
+     * MSR[IP] should never be set.
+     *
+     * We also disallow setting of MSR_HV
+     */
+    env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+
+    /* Tell KVM that we're in PAPR mode */
+    if (kvm_enabled()) {
+        kvmppc_set_papr(cpu);
+    }
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#endif /* defined (TARGET_PPC64) */
 
 /*****************************************************************************/
 /* Generic CPU instantiation routine                                         */

[Qemu-devel] [PATCH v3 05/10] ppc: Add dummy SPR_IC for POWER8

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

It's supposed to be an instruction counter. For now make us not
crash when accessing it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---

 This is required for patch "ppc: A couple more dummy POWER8 Book4 regs"

 target-ppc/cpu.h            |  1 +
 target-ppc/translate_init.c | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a7da0d3e95a9..167c73f863b3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1685,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_MPC_MD_DBRAM1     (0x32A)
 #define SPR_RCPU_L2U_RA3      (0x32B)
 #define SPR_TAR               (0x32F)
+#define SPR_IC                (0x350)
 #define SPR_VTB               (0x351)
 #define SPR_MMCRC             (0x353)
 #define SPR_440_INV0          (0x370)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index aaf8ad79361e..fa8d217295b9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7924,6 +7924,17 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
                      KVM_REG_PPC_PSPB, 0);
 }
 
+static void gen_spr_power8_ic(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+    spr_register_hv(env, SPR_IC, "IC",
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    &spr_read_generic, SPR_NOACCESS,
+                    &spr_read_generic, &spr_write_generic,
+                    0);
+#endif
+}
+
 static void init_proc_book3s_64(CPUPPCState *env, int version)
 {
     gen_spr_ne_601(env);
@@ -7976,6 +7987,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
         gen_spr_power8_tm(env);
         gen_spr_power8_pspb(env);
         gen_spr_vtb(env);
+        gen_spr_power8_ic(env);
     }
     if (version < BOOK3S_CPU_POWER8) {
         gen_spr_book3s_dbg(env);
-- 
2.1.4

[Qemu-devel] [PATCH v3 06/10] ppc: Initialize AMOR in PAPR mode

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Make sure we give the guest full authorization

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate_init.c |    4 ++++
 1 file changed, 4 insertions(+)

Index: qemu-dgibson-for-2.6.git/target-ppc/translate_init.c
===================================================================
--- qemu-dgibson-for-2.6.git.orig/target-ppc/translate_init.c
+++ qemu-dgibson-for-2.6.git/target-ppc/translate_init.c
@@ -8398,6 +8398,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc,
 void cpu_ppc_set_papr(PowerPCCPU *cpu)
 {
     CPUPPCState *env = &cpu->env;
+    ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
 
     /* PAPR always has exception vectors in RAM not ROM. To ensure this,
      * MSR[IP] should never be set.
@@ -8406,6 +8407,9 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
      */
     env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
 
+    /* Set a full AMOR so guest can use the AMR as it sees fit */
+    env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
+
     /* Tell KVM that we're in PAPR mode */
     if (kvm_enabled()) {
         kvmppc_set_papr(cpu);

[Qemu-devel] [PATCH v3 07/10] ppc: Fix writing to AMR/UAMOR

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The masks weren't chosen nor applied properly. The architecture specifies
that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.

The writes to UAMOR are masked by AMOR for HV=0

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: moved gen_spr_amr() prototype change to next patch ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate_init.c | 74 ++++++++++++++++++++++++++++++++++++---------
 1 file changed, 59 insertions(+), 15 deletions(-)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b1d1949d24e2..4514188ff07c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1063,26 +1063,68 @@ static void gen_spr_7xx (CPUPPCState *env)
 
 #ifdef TARGET_PPC64
 #ifndef CONFIG_USER_ONLY
-static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
+static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_load_spr(cpu_gpr[gprn], SPR_AMR);
-    spr_load_dump_spr(SPR_AMR);
-}
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
 
-static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
-{
-    gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
+    /* Note, the HV=1 PR=0 case is handled earlier by simply using
+     * spr_write_generic for HV mode in the SPR table
+     */
+
+    /* Build insertion mask into t1 based on context */
+    if (ctx->pr) {
+        gen_load_spr(t1, SPR_UAMOR);
+    } else {
+        gen_load_spr(t1, SPR_AMOR);
+    }
+
+    /* Mask new bits into t2 */
+    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+    /* Load AMR and clear new bits in t0 */
+    gen_load_spr(t0, SPR_AMR);
+    tcg_gen_andc_tl(t0, t0, t1);
+
+    /* Or'in new bits and write it out */
+    tcg_gen_or_tl(t0, t0, t2);
+    gen_store_spr(SPR_AMR, t0);
     spr_store_dump_spr(SPR_AMR);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
 }
 
-static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
+static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
+
+    /* Note, the HV=1 case is handled earlier by simply using
+     * spr_write_generic for HV mode in the SPR table
+     */
 
+    /* Build insertion mask into t1 based on context */
+    gen_load_spr(t1, SPR_AMOR);
+
+    /* Mask new bits into t2 */
+    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+    /* Load AMR and clear new bits in t0 */
     gen_load_spr(t0, SPR_UAMOR);
-    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
-    gen_store_spr(SPR_AMR, t0);
-    spr_store_dump_spr(SPR_AMR);
+    tcg_gen_andc_tl(t0, t0, t1);
+
+    /* Or'in new bits and write it out */
+    tcg_gen_or_tl(t0, t0, t2);
+    gen_store_spr(SPR_UAMOR, t0);
+    spr_store_dump_spr(SPR_UAMOR);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
 }
 #endif /* CONFIG_USER_ONLY */
 
@@ -1094,15 +1136,17 @@ static void gen_spr_amr (CPUPPCState *env)
      * userspace accessible, 29 is privileged.  So we only need to set
      * the kvm ONE_REG id on one of them, we use 29 */
     spr_register(env, SPR_UAMR, "UAMR",
-                 &spr_read_uamr, &spr_write_uamr_pr,
-                 &spr_read_uamr, &spr_write_uamr,
+                 &spr_read_generic, &spr_write_amr,
+                 &spr_read_generic, &spr_write_amr,
                  0);
-    spr_register_kvm(env, SPR_AMR, "AMR",
+    spr_register_kvm_hv(env, SPR_AMR, "AMR",
                      SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_amr,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_AMR, 0);
-    spr_register_kvm(env, SPR_UAMOR, "UAMOR",
+    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
                      SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_uamor,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_UAMOR, 0);
     spr_register_hv(env, SPR_AMOR, "AMOR",
-- 
2.1.4

[Qemu-devel] [PATCH v3 08/10] ppc: Add POWER8 IAMR register

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

With appropriate AMR-like masks. Not actually used by the translation
logic at that point

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR)
      changed gen_spr_amr() prototype ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---

 Changes since v2:

 - fixed has_iamr condition in gen_spr_amr()

 target-ppc/cpu.h            |  1 +
 target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++++--
 2 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 167c73f863b3..a3c4fb112a3e 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1360,6 +1360,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_BOOKE_CSRR0       (0x03A)
 #define SPR_BOOKE_CSRR1       (0x03B)
 #define SPR_BOOKE_DEAR        (0x03D)
+#define SPR_IAMR              (0x03D)
 #define SPR_BOOKE_ESR         (0x03E)
 #define SPR_BOOKE_IVPR        (0x03F)
 #define SPR_MPC_EIE           (0x050)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4514188ff07c..c78b532e8f3c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1126,9 +1126,39 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
     tcg_temp_free(t1);
     tcg_temp_free(t2);
 }
+
+static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+{
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
+
+    /* Note, the HV=1 case is handled earlier by simply using
+     * spr_write_generic for HV mode in the SPR table
+     */
+
+    /* Build insertion mask into t1 based on context */
+    gen_load_spr(t1, SPR_AMOR);
+
+    /* Mask new bits into t2 */
+    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+    /* Load AMR and clear new bits in t0 */
+    gen_load_spr(t0, SPR_IAMR);
+    tcg_gen_andc_tl(t0, t0, t1);
+
+    /* Or'in new bits and write it out */
+    tcg_gen_or_tl(t0, t0, t2);
+    gen_store_spr(SPR_IAMR, t0);
+    spr_store_dump_spr(SPR_IAMR);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
+}
 #endif /* CONFIG_USER_ONLY */
 
-static void gen_spr_amr (CPUPPCState *env)
+static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
 {
 #ifndef CONFIG_USER_ONLY
     /* Virtual Page Class Key protection */
@@ -1154,6 +1184,13 @@ static void gen_spr_amr (CPUPPCState *env)
                     SPR_NOACCESS, SPR_NOACCESS,
                     &spr_read_generic, &spr_write_generic,
                     0);
+    if (has_iamr) {
+        spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
+                            SPR_NOACCESS, SPR_NOACCESS,
+                            &spr_read_generic, &spr_write_iamr,
+                            &spr_read_generic, &spr_write_generic,
+                            KVM_REG_PPC_IAMR, 0);
+    }
 #endif /* !CONFIG_USER_ONLY */
 }
 #endif /* TARGET_PPC64 */
@@ -8000,7 +8037,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
     case BOOK3S_CPU_POWER7:
     case BOOK3S_CPU_POWER8:
         gen_spr_book3s_ids(env);
-        gen_spr_amr(env);
+        gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
         gen_spr_book3s_purr(env);
         env->ci_large_pages = true;
         break;
-- 
2.1.4

[Qemu-devel] [PATCH v3 09/10] ppc: Add dummy CIABR SPR

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

We should implement HW breakpoint/watchpoint, qemu supports them...

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/cpu.h            | 1 +
 target-ppc/translate_init.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a3c4fb112a3e..29c48600d950 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1393,6 +1393,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_PSPB              (0x09F)
 #define SPR_DAWR              (0x0B4)
 #define SPR_RPR               (0x0BA)
+#define SPR_CIABR             (0x0BB)
 #define SPR_DAWRX             (0x0BC)
 #define SPR_HFSCR             (0x0BE)
 #define SPR_VRSAVE            (0x100)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c78b532e8f3c..5f53098faef7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7589,6 +7589,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
                         SPR_NOACCESS, SPR_NOACCESS,
                         &spr_read_generic, &spr_write_generic,
                         KVM_REG_PPC_DAWRX, 0x00000000);
+    spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        &spr_read_generic, &spr_write_generic,
+                        KVM_REG_PPC_CIABR, 0x00000000);
 }
 
 static void gen_spr_970_dbg(CPUPPCState *env)
-- 
2.1.4

[Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs

[Cédric Le Goater]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/cpu.h            |  3 +++
 target-ppc/translate_init.c | 12 ++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 29c48600d950..676081e69dc0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1355,7 +1355,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_SRR1              (0x01B)
 #define SPR_CFAR              (0x01C)
 #define SPR_AMR               (0x01D)
+#define SPR_ACOP              (0x01F)
 #define SPR_BOOKE_PID         (0x030)
+#define SPR_BOOKS_PID         (0x030)
 #define SPR_BOOKE_DECAR       (0x036)
 #define SPR_BOOKE_CSRR0       (0x03A)
 #define SPR_BOOKE_CSRR1       (0x03B)
@@ -1706,6 +1708,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
 #define SPR_POWER_SPMC1       (0x37C)
 #define SPR_POWER_SPMC2       (0x37D)
 #define SPR_POWER_MMCRS       (0x37E)
+#define SPR_WORT              (0x37F)
 #define SPR_PPR               (0x380)
 #define SPR_750_GQR0          (0x390)
 #define SPR_440_DNV0          (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 5f53098faef7..51e8058c468e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8018,6 +8018,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
                     &spr_read_generic, SPR_NOACCESS,
                     &spr_read_generic, &spr_write_generic,
                     0);
+    spr_register_kvm(env, SPR_ACOP, "ACOP",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_ACOP, 0);
+    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PID, 0);
+    spr_register_kvm(env, SPR_WORT, "WORT",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_WORT, 0);
 #endif
 }
 
-- 
2.1.4

Re: [Qemu-devel] [PATCH v3 00/10] ppc: preparing pnv landing

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 891 bytes --]

On Mon, Mar 21, 2016 at 01:52:30PM +0100, Cédric Le Goater wrote:
> Hello,
> 
> This is a first mini-serie of patches adding support for new ppc SPRs.
> They were taken from Ben's larger patchset adding the ppc powernv
> platform and they should already be useful for the pseries guest
> migration.
> 
> Initial patches come from :
> 
> 	https://github.com/ozbenh/qemu/commits/powernv
> 
> The changes are mostly due to the rebase on Dave's 2.6 branch:
> 
> 	https://github.com/dgibson/qemu/commits/ppc-for-2.6 ppc-for-2.6-20160316
> 
> A couple more are bisect and checkpatch fixes and finally some patches
> were merge to reduce the noise.

Applied to ppc-for-2.6, thanks.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v3 04/10] ppc: Create cpu_ppc_set_papr() helper

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 995 bytes --]

On Mon, Mar 21, 2016 at 01:52:34PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> to it. This allows us to add a few more things such as disabling setting
> of MSR:HV and appropriate LPCR bits which will be used when fixing
> the exception model.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> [clg: removed LPCR setting ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>

Nothing wrong with the patch, but your mailer seems to have done
something really weird with the headers:

> Content-Type: text/plain; charset=a

Oddly enough, git am had some trouble with charset "a".

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v3 04/10] ppc: Create cpu_ppc_set_papr() helper

[Cédric Le Goater]

On 03/22/2016 12:15 AM, David Gibson wrote:
> On Mon, Mar 21, 2016 at 01:52:34PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
>> to it. This allows us to add a few more things such as disabling setting
>> of MSR:HV and appropriate LPCR bits which will be used when fixing
>> the exception model.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> [clg: removed LPCR setting ]
>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> 
> Nothing wrong with the patch, but your mailer seems to have done
> something really weird with the headers:
> 
>> Content-Type: text/plain; charset=a
> 
> Oddly enough, git am had some trouble with charset "a".
> 

Ah. Interesting. 

When the patch was sent, git send-email requested a change on the 
Content-type (a switch to UTF8). Most probably because of the accent 
on my first name. It seems something went wrong. I will look into it.

Thanks,

C.

Re: [Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs

[Thomas Huth]

On 21.03.2016 13:52, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>  target-ppc/cpu.h            |  3 +++
>  target-ppc/translate_init.c | 12 ++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 29c48600d950..676081e69dc0 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1355,7 +1355,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_SRR1              (0x01B)
>  #define SPR_CFAR              (0x01C)
>  #define SPR_AMR               (0x01D)
> +#define SPR_ACOP              (0x01F)
>  #define SPR_BOOKE_PID         (0x030)
> +#define SPR_BOOKS_PID         (0x030)
>  #define SPR_BOOKE_DECAR       (0x036)
>  #define SPR_BOOKE_CSRR0       (0x03A)
>  #define SPR_BOOKE_CSRR1       (0x03B)
> @@ -1706,6 +1708,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_POWER_SPMC1       (0x37C)
>  #define SPR_POWER_SPMC2       (0x37D)
>  #define SPR_POWER_MMCRS       (0x37E)
> +#define SPR_WORT              (0x37F)
>  #define SPR_PPR               (0x380)
>  #define SPR_750_GQR0          (0x390)
>  #define SPR_440_DNV0          (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 5f53098faef7..51e8058c468e 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8018,6 +8018,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
>                      &spr_read_generic, SPR_NOACCESS,
>                      &spr_read_generic, &spr_write_generic,
>                      0);
> +    spr_register_kvm(env, SPR_ACOP, "ACOP",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_ACOP, 0);
> +    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_PID, 0);
> +    spr_register_kvm(env, SPR_WORT, "WORT",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_WORT, 0);
>  #endif
>  }

In the original patch, the registers had been added to a function called
gen_spr_power8_book4() ... now they are added to gen_spr_power8_ic() ...
was that on purpose or rather by accident?

 Thomas

Re: [Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs

[Cédric Le Goater]

On 03/22/2016 02:56 PM, Thomas Huth wrote:
> On 21.03.2016 13:52, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
>> Reviewed-by: Thomas Huth <thuth@redhat.com>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>>  target-ppc/cpu.h            |  3 +++
>>  target-ppc/translate_init.c | 12 ++++++++++++
>>  2 files changed, 15 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 29c48600d950..676081e69dc0 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1355,7 +1355,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>>  #define SPR_SRR1              (0x01B)
>>  #define SPR_CFAR              (0x01C)
>>  #define SPR_AMR               (0x01D)
>> +#define SPR_ACOP              (0x01F)
>>  #define SPR_BOOKE_PID         (0x030)
>> +#define SPR_BOOKS_PID         (0x030)
>>  #define SPR_BOOKE_DECAR       (0x036)
>>  #define SPR_BOOKE_CSRR0       (0x03A)
>>  #define SPR_BOOKE_CSRR1       (0x03B)
>> @@ -1706,6 +1708,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>>  #define SPR_POWER_SPMC1       (0x37C)
>>  #define SPR_POWER_SPMC2       (0x37D)
>>  #define SPR_POWER_MMCRS       (0x37E)
>> +#define SPR_WORT              (0x37F)
>>  #define SPR_PPR               (0x380)
>>  #define SPR_750_GQR0          (0x390)
>>  #define SPR_440_DNV0          (0x390)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 5f53098faef7..51e8058c468e 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8018,6 +8018,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
>>                      &spr_read_generic, SPR_NOACCESS,
>>                      &spr_read_generic, &spr_write_generic,
>>                      0);
>> +    spr_register_kvm(env, SPR_ACOP, "ACOP",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_ACOP, 0);
>> +    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_PID, 0);
>> +    spr_register_kvm(env, SPR_WORT, "WORT",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_WORT, 0);
>>  #endif
>>  }
> 
> In the original patch, the registers had been added to a function called
> gen_spr_power8_book4() ... now they are added to gen_spr_power8_ic() ...
> was that on purpose or rather by accident?

This is an accident which occurred when I removed SPR_MPPR. I will send a
fix.

Thanks,

C. 

Re: [Qemu-devel] [PATCH v3 04/10] ppc: Create cpu_ppc_set_papr() helper

[David Gibson]

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On Tue, Mar 22, 2016 at 08:05:08AM +0100, Cédric Le Goater wrote:
> On 03/22/2016 12:15 AM, David Gibson wrote:
> > On Mon, Mar 21, 2016 at 01:52:34PM +0100, Cédric Le Goater wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> >> to it. This allows us to add a few more things such as disabling setting
> >> of MSR:HV and appropriate LPCR bits which will be used when fixing
> >> the exception model.
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> >> [clg: removed LPCR setting ]
> >> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> > 
> > Nothing wrong with the patch, but your mailer seems to have done
> > something really weird with the headers:
> > 
> >> Content-Type: text/plain; charset=a
> > 
> > Oddly enough, git am had some trouble with charset "a".
> > 
> 
> Ah. Interesting. 
> 
> When the patch was sent, git send-email requested a change on the 
> Content-type (a switch to UTF8). Most probably because of the accent 
> on my first name. It seems something went wrong. I will look into it.

Right, as far as I can tell the content was valid UTF-8, including the
accent, just the header was wrong - I was able to apply by hand
editing the mbox to say UTF-8 instead.

For some reason it only happened to this one mail.  The other ones in
the series showed up as UTF-8, although at least some had the same accent.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 00/10] ppc: preparing pnv landing

[Cédric Le Goater]

On 03/22/2016 12:14 AM, David Gibson wrote:
> On Mon, Mar 21, 2016 at 01:52:30PM +0100, Cédric Le Goater wrote:
>> Hello,
>>
>> This is a first mini-serie of patches adding support for new ppc SPRs.
>> They were taken from Ben's larger patchset adding the ppc powernv
>> platform and they should already be useful for the pseries guest
>> migration.
>>
>> Initial patches come from :
>>
>> 	https://github.com/ozbenh/qemu/commits/powernv
>>
>> The changes are mostly due to the rebase on Dave's 2.6 branch:
>>
>> 	https://github.com/dgibson/qemu/commits/ppc-for-2.6 ppc-for-2.6-20160316
>>
>> A couple more are bisect and checkpatch fixes and finally some patches
>> were merge to reduce the noise.
> 
> Applied to ppc-for-2.6, thanks.


Hello David,

I have identified this next serie of prerequisites for PowerNV that should 
not need too much discussion. When would be the right time to send them ? 

	[PATCH 01/77] ppc: Remove MMU_MODEn_SUFFIX definitions
	[PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on
	[PATCH 03/77] ppc: Do some batching of TCG tlb flushes
	[PATCH 07/77] ppc: Add a bunch of hypervisor SPRs to Book3s
	[PATCH 09/77] ppc: Fix hreg_store_msr() so that non-HV mode cannot
	[PATCH 10/77] ppc: Fix rfi/rfid/hrfi/... emulation
	[PATCH 12/77] ppc: Better figure out if processor has HV mode
	[PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only
	[PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie
	[PATCH 15/77] ppc: Fix sign extension issue in mtmsr(d) emulation
	[PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops
	[PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8


The exception model changes are rather invasive but they are complex so 
I will keep them for later and I would like to try getting the xics changes 
out of the way first. They are a pain to maintain out of the mainline tree. 
Could we follow on with xics then ? 

Thanks,

C.

Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 00/10] ppc: preparing pnv landing

[David Gibson]

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On Wed, Apr 13, 2016 at 11:15:15AM +0200, Cédric Le Goater wrote:
> On 03/22/2016 12:14 AM, David Gibson wrote:
> > On Mon, Mar 21, 2016 at 01:52:30PM +0100, Cédric Le Goater wrote:
> >> Hello,
> >>
> >> This is a first mini-serie of patches adding support for new ppc SPRs.
> >> They were taken from Ben's larger patchset adding the ppc powernv
> >> platform and they should already be useful for the pseries guest
> >> migration.
> >>
> >> Initial patches come from :
> >>
> >> 	https://github.com/ozbenh/qemu/commits/powernv
> >>
> >> The changes are mostly due to the rebase on Dave's 2.6 branch:
> >>
> >> 	https://github.com/dgibson/qemu/commits/ppc-for-2.6 ppc-for-2.6-20160316
> >>
> >> A couple more are bisect and checkpatch fixes and finally some patches
> >> were merge to reduce the noise.
> > 
> > Applied to ppc-for-2.6, thanks.
> 
> 
> Hello David,
> 
> I have identified this next serie of prerequisites for PowerNV that should 
> not need too much discussion. When would be the right time to send them ? 
> 
> 	[PATCH 01/77] ppc: Remove MMU_MODEn_SUFFIX definitions
> 	[PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on
> 	[PATCH 03/77] ppc: Do some batching of TCG tlb flushes
> 	[PATCH 07/77] ppc: Add a bunch of hypervisor SPRs to Book3s
> 	[PATCH 09/77] ppc: Fix hreg_store_msr() so that non-HV mode cannot
> 	[PATCH 10/77] ppc: Fix rfi/rfid/hrfi/... emulation
> 	[PATCH 12/77] ppc: Better figure out if processor has HV mode
> 	[PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only
> 	[PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie
> 	[PATCH 15/77] ppc: Fix sign extension issue in mtmsr(d) emulation
> 	[PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops
> 	[PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8
> 
> 
> The exception model changes are rather invasive but they are complex so 
> I will keep them for later and I would like to try getting the xics changes 
> out of the way first. They are a pain to maintain out of the mainline tree. 
> Could we follow on with xics then ? 

So, obviously none of these will be merged before 2.7.  That said,
I've already started a ppc-for-2.7 tree, so I'm ok with posting the
next batch for review before mainline 2.7 opens.  I can't promise I'll
be able to review them quickly, but I'm ok for you to post them any
time, really.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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