* [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt
@ 2016-03-18 11:11 Jani Nikula
2016-03-18 11:11 ` [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion Jani Nikula
` (9 more replies)
0 siblings, 10 replies; 23+ messages in thread
From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, jani.nikula
Next iteration after [1]. Plenty of changes around VLV macros and
tables. I wish I could get my hands on a CHV gpio table spec. BXT is
included.
BR,
Jani.
[1] http://mid.gmane.org/cover.1458226863.git.jani.nikula@intel.com
Jani Nikula (8):
drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion
drm/i915/dsi: add support for DSI sequence block v2 gpio element
drm/i915/dsi: clean up vlv gpio table and definitions
drm/i915/dsi: add gpio indexes to the gpio table
drm/i915/dsi: abstract VLV gpio element execution to a separate
function
drm/i915/dsi: add support for sequence block v3 gpio for VLV
drm/i915/chv: add more IOSF port definitions
drm/i915/bxt: add bxt dsi gpio element support
Yogesh Mohan Marimuthu (1):
drm/i915/dsi: add support for gpio elements on CHV
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 893 ++++++++++++++++++++++++++---
2 files changed, 826 insertions(+), 71 deletions(-)
--
2.1.4
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^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-03-24 11:57 ` Mika Kahola 2016-03-18 11:11 ` [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element Jani Nikula ` (8 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula The DSI sequence blocks contain gpio index references, not actual gpio numbers. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 8302a972d2d4..f687b2e9d8ca 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) { - u8 gpio, action; + u8 gpio_index, action; u16 function, pad; u32 val; struct drm_device *dev = intel_dsi->base.base.dev; @@ -207,13 +207,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) if (dev_priv->vbt.dsi.seq_version >= 3) data++; - gpio = *data++; + gpio_index = *data++; /* pull up/down */ action = *data++ & 1; - if (gpio >= ARRAY_SIZE(gtable)) { - DRM_DEBUG_KMS("unknown gpio %u\n", gpio); + if (gpio_index >= ARRAY_SIZE(gtable)) { + DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); goto out; } @@ -227,16 +227,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) goto out; } - function = gtable[gpio].function_reg; - pad = gtable[gpio].pad_reg; + function = gtable[gpio_index].function_reg; + pad = gtable[gpio_index].pad_reg; mutex_lock(&dev_priv->sb_lock); - if (!gtable[gpio].init) { + if (!gtable[gpio_index].init) { /* program the function */ /* FIXME: remove constant below */ vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, 0x2000CC00); - gtable[gpio].init = 1; + gtable[gpio_index].init = 1; } val = 0x4 | action; -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion 2016-03-18 11:11 ` [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion Jani Nikula @ 2016-03-24 11:57 ` Mika Kahola 2016-04-01 11:53 ` Jani Nikula 0 siblings, 1 reply; 23+ messages in thread From: Mika Kahola @ 2016-03-24 11:57 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx Housekeeping stuff. Reviewed-by: Mika Kahola <mika.kahola@intel.com> On Fri, 2016-03-18 at 13:11 +0200, Jani Nikula wrote: > The DSI sequence blocks contain gpio index references, not actual gpio > numbers. No functional changes. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index 8302a972d2d4..f687b2e9d8ca 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) > > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > - u8 gpio, action; > + u8 gpio_index, action; > u16 function, pad; > u32 val; > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -207,13 +207,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > if (dev_priv->vbt.dsi.seq_version >= 3) > data++; > > - gpio = *data++; > + gpio_index = *data++; > > /* pull up/down */ > action = *data++ & 1; > > - if (gpio >= ARRAY_SIZE(gtable)) { > - DRM_DEBUG_KMS("unknown gpio %u\n", gpio); > + if (gpio_index >= ARRAY_SIZE(gtable)) { > + DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); > goto out; > } > > @@ -227,16 +227,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > goto out; > } > > - function = gtable[gpio].function_reg; > - pad = gtable[gpio].pad_reg; > + function = gtable[gpio_index].function_reg; > + pad = gtable[gpio_index].pad_reg; > > mutex_lock(&dev_priv->sb_lock); > - if (!gtable[gpio].init) { > + if (!gtable[gpio_index].init) { > /* program the function */ > /* FIXME: remove constant below */ > vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, > 0x2000CC00); > - gtable[gpio].init = 1; > + gtable[gpio_index].init = 1; > } > > val = 0x4 | action; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion 2016-03-24 11:57 ` Mika Kahola @ 2016-04-01 11:53 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-04-01 11:53 UTC (permalink / raw) To: mika.kahola; +Cc: Deepak M, intel-gfx On Thu, 24 Mar 2016, Mika Kahola <mika.kahola@intel.com> wrote: > Housekeeping stuff. > > Reviewed-by: Mika Kahola <mika.kahola@intel.com> Thanks, pushed this one patch to drm-intel-next-queued. BR, Jani. > > On Fri, 2016-03-18 at 13:11 +0200, Jani Nikula wrote: >> The DSI sequence blocks contain gpio index references, not actual gpio >> numbers. No functional changes. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 16 ++++++++-------- >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> index 8302a972d2d4..f687b2e9d8ca 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) >> >> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> { >> - u8 gpio, action; >> + u8 gpio_index, action; >> u16 function, pad; >> u32 val; >> struct drm_device *dev = intel_dsi->base.base.dev; >> @@ -207,13 +207,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> if (dev_priv->vbt.dsi.seq_version >= 3) >> data++; >> >> - gpio = *data++; >> + gpio_index = *data++; >> >> /* pull up/down */ >> action = *data++ & 1; >> >> - if (gpio >= ARRAY_SIZE(gtable)) { >> - DRM_DEBUG_KMS("unknown gpio %u\n", gpio); >> + if (gpio_index >= ARRAY_SIZE(gtable)) { >> + DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); >> goto out; >> } >> >> @@ -227,16 +227,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> goto out; >> } >> >> - function = gtable[gpio].function_reg; >> - pad = gtable[gpio].pad_reg; >> + function = gtable[gpio_index].function_reg; >> + pad = gtable[gpio_index].pad_reg; >> >> mutex_lock(&dev_priv->sb_lock); >> - if (!gtable[gpio].init) { >> + if (!gtable[gpio_index].init) { >> /* program the function */ >> /* FIXME: remove constant below */ >> vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, >> 0x2000CC00); >> - gtable[gpio].init = 1; >> + gtable[gpio_index].init = 1; >> } >> >> val = 0x4 | action; > > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula 2016-03-18 11:11 ` [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-04-04 16:19 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions Jani Nikula ` (7 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula In sequence block v2, and only in v2, the gpio source (i.e. IOSF port) is specified separately. v2: initialize gpio_source to 0 and handle v1 and v2 in the same branch Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index f687b2e9d8ca..af1a47b5224f 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) { - u8 gpio_index, action; + u8 gpio_source, gpio_index, action, port; u16 function, pad; u32 val; struct drm_device *dev = intel_dsi->base.base.dev; @@ -209,6 +209,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) gpio_index = *data++; + /* gpio source in sequence v2 only */ + if (dev_priv->vbt.dsi.seq_version == 2) + gpio_source = (*data >> 1) & 3; + else + gpio_source = 0; + /* pull up/down */ action = *data++ & 1; @@ -225,6 +231,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) if (dev_priv->vbt.dsi.seq_version >= 3) { DRM_DEBUG_KMS("GPIO element v3 not supported\n"); goto out; + } else { + if (gpio_source == 0) { + port = IOSF_PORT_GPIO_NC; + } else if (gpio_source == 1) { + port = IOSF_PORT_GPIO_SC; + } else { + DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + goto out; + } } function = gtable[gpio_index].function_reg; @@ -234,15 +249,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) if (!gtable[gpio_index].init) { /* program the function */ /* FIXME: remove constant below */ - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, - 0x2000CC00); + vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00); gtable[gpio_index].init = 1; } val = 0x4 | action; /* pull up/down */ - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val); + vlv_iosf_sb_write(dev_priv, port, pad, val); mutex_unlock(&dev_priv->sb_lock); out: -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element 2016-03-18 11:11 ` [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element Jani Nikula @ 2016-04-04 16:19 ` Ville Syrjälä 2016-04-05 7:33 ` Jani Nikula 0 siblings, 1 reply; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 16:19 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:10PM +0200, Jani Nikula wrote: > In sequence block v2, and only in v2, the gpio source (i.e. IOSF port) > is specified separately. > > v2: initialize gpio_source to 0 and handle v1 and v2 in the same branch > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index f687b2e9d8ca..af1a47b5224f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) > > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > - u8 gpio_index, action; > + u8 gpio_source, gpio_index, action, port; > u16 function, pad; > u32 val; > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -209,6 +209,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > > gpio_index = *data++; > > + /* gpio source in sequence v2 only */ > + if (dev_priv->vbt.dsi.seq_version == 2) > + gpio_source = (*data >> 1) & 3; > + else > + gpio_source = 0; > + > /* pull up/down */ > action = *data++ & 1; > > @@ -225,6 +231,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > if (dev_priv->vbt.dsi.seq_version >= 3) { > DRM_DEBUG_KMS("GPIO element v3 not supported\n"); > goto out; > + } else { > + if (gpio_source == 0) { > + port = IOSF_PORT_GPIO_NC; > + } else if (gpio_source == 1) { > + port = IOSF_PORT_GPIO_SC; > + } else { > + DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); > + goto out; > + } > } > > function = gtable[gpio_index].function_reg; > @@ -234,15 +249,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > if (!gtable[gpio_index].init) { > /* program the function */ > /* FIXME: remove constant below */ > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, > - 0x2000CC00); > + vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00); > gtable[gpio_index].init = 1; > } > > val = 0x4 | action; > > /* pull up/down */ > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val); > + vlv_iosf_sb_write(dev_priv, port, pad, val); > mutex_unlock(&dev_priv->sb_lock); > > out: > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element 2016-04-04 16:19 ` Ville Syrjälä @ 2016-04-05 7:33 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-04-05 7:33 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Deepak M, intel-gfx On Mon, 04 Apr 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Fri, Mar 18, 2016 at 01:11:10PM +0200, Jani Nikula wrote: >> In sequence block v2, and only in v2, the gpio source (i.e. IOSF port) >> is specified separately. >> >> v2: initialize gpio_source to 0 and handle v1 and v2 in the same branch >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pushed to drm-intel-next-queued, thanks for the review. BR, Jani. > >> --- >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 22 ++++++++++++++++++---- >> 1 file changed, 18 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> index f687b2e9d8ca..af1a47b5224f 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> @@ -198,7 +198,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) >> >> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> { >> - u8 gpio_index, action; >> + u8 gpio_source, gpio_index, action, port; >> u16 function, pad; >> u32 val; >> struct drm_device *dev = intel_dsi->base.base.dev; >> @@ -209,6 +209,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> >> gpio_index = *data++; >> >> + /* gpio source in sequence v2 only */ >> + if (dev_priv->vbt.dsi.seq_version == 2) >> + gpio_source = (*data >> 1) & 3; >> + else >> + gpio_source = 0; >> + >> /* pull up/down */ >> action = *data++ & 1; >> >> @@ -225,6 +231,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> if (dev_priv->vbt.dsi.seq_version >= 3) { >> DRM_DEBUG_KMS("GPIO element v3 not supported\n"); >> goto out; >> + } else { >> + if (gpio_source == 0) { >> + port = IOSF_PORT_GPIO_NC; >> + } else if (gpio_source == 1) { >> + port = IOSF_PORT_GPIO_SC; >> + } else { >> + DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); >> + goto out; >> + } >> } >> >> function = gtable[gpio_index].function_reg; >> @@ -234,15 +249,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> if (!gtable[gpio_index].init) { >> /* program the function */ >> /* FIXME: remove constant below */ >> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function, >> - 0x2000CC00); >> + vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00); >> gtable[gpio_index].init = 1; >> } >> >> val = 0x4 | action; >> >> /* pull up/down */ >> - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val); >> + vlv_iosf_sb_write(dev_priv, port, pad, val); >> mutex_unlock(&dev_priv->sb_lock); >> >> out: >> -- >> 2.1.4 -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula 2016-03-18 11:11 ` [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion Jani Nikula 2016-03-18 11:11 ` [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-04-04 17:07 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table Jani Nikula ` (6 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula Define and store the pad base offset in the array, and reference the pconf0 and padval registers through macros. Add VLV prefixes to macros. Use spec nomenclature for pconf0 and padval. v2: Address Ville's review comments, squash another patch here. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 87 ++++++++++++++---------------- 1 file changed, 39 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index af1a47b5224f..b04d88e6127b 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -58,50 +58,41 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) #define NS_KHZ_RATIO 1000000 -#define GPI0_NC_0_HV_DDI0_HPD 0x4130 -#define GPIO_NC_0_HV_DDI0_PAD 0x4138 -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 -#define GPIO_NC_3_PANEL0_VDDEN 0x4140 -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 -#define GPIO_NC_4_PANEL0_BLKEN 0x4150 -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160 -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 -#define GPIO_NC_6_PCONF0 0x4180 -#define GPIO_NC_6_PAD 0x4188 -#define GPIO_NC_7_PCONF0 0x4190 -#define GPIO_NC_7_PAD 0x4198 -#define GPIO_NC_8_PCONF0 0x4170 -#define GPIO_NC_8_PAD 0x4178 -#define GPIO_NC_9_PCONF0 0x4100 -#define GPIO_NC_9_PAD 0x4108 -#define GPIO_NC_10_PCONF0 0x40E0 -#define GPIO_NC_10_PAD 0x40E8 -#define GPIO_NC_11_PCONF0 0x40F0 -#define GPIO_NC_11_PAD 0x40F8 +/* base offsets for gpio pads */ +#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 +#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 +#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 +#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 +#define VLV_GPIO_NC_4_PANEL0_BLKEN 0x4150 +#define VLV_GPIO_NC_5_PANEL0_BLKCTL 0x4160 +#define VLV_GPIO_NC_6_PCONF0 0x4180 +#define VLV_GPIO_NC_7_PCONF0 0x4190 +#define VLV_GPIO_NC_8_PCONF0 0x4170 +#define VLV_GPIO_NC_9_PCONF0 0x4100 +#define VLV_GPIO_NC_10_PCONF0 0x40E0 +#define VLV_GPIO_NC_11_PCONF0 0x40F0 + +#define VLV_GPIO_PCONF0(base_offset) (base_offset) +#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) struct gpio_table { - u16 function_reg; - u16 pad_reg; - u8 init; + u16 base_offset; + bool init; }; -static struct gpio_table gtable[] = { - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, - { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, - { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} +static struct gpio_table vlv_gpio_table[] = { + { VLV_GPIO_NC_0_HV_DDI0_HPD }, + { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, + { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, + { VLV_GPIO_NC_3_PANEL0_VDDEN }, + { VLV_GPIO_NC_4_PANEL0_BLKEN }, + { VLV_GPIO_NC_5_PANEL0_BLKCTL }, + { VLV_GPIO_NC_6_PCONF0 }, + { VLV_GPIO_NC_7_PCONF0 }, + { VLV_GPIO_NC_8_PCONF0 }, + { VLV_GPIO_NC_9_PCONF0 }, + { VLV_GPIO_NC_10_PCONF0 }, + { VLV_GPIO_NC_11_PCONF0 }, }; static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -199,7 +190,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) { u8 gpio_source, gpio_index, action, port; - u16 function, pad; + u16 pconf0, padval; u32 val; struct drm_device *dev = intel_dsi->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -218,7 +209,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) /* pull up/down */ action = *data++ & 1; - if (gpio_index >= ARRAY_SIZE(gtable)) { + if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); goto out; } @@ -242,21 +233,21 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) } } - function = gtable[gpio_index].function_reg; - pad = gtable[gpio_index].pad_reg; + pconf0 = VLV_GPIO_PCONF0(vlv_gpio_table[gpio_index].base_offset); + padval = VLV_GPIO_PAD_VAL(vlv_gpio_table[gpio_index].base_offset); mutex_lock(&dev_priv->sb_lock); - if (!gtable[gpio_index].init) { + if (!vlv_gpio_table[gpio_index].init) { /* program the function */ /* FIXME: remove constant below */ - vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00); - gtable[gpio_index].init = 1; + vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); + vlv_gpio_table[gpio_index].init = true; } val = 0x4 | action; /* pull up/down */ - vlv_iosf_sb_write(dev_priv, port, pad, val); + vlv_iosf_sb_write(dev_priv, port, padval, val); mutex_unlock(&dev_priv->sb_lock); out: -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions 2016-03-18 11:11 ` [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions Jani Nikula @ 2016-04-04 17:07 ` Ville Syrjälä 0 siblings, 0 replies; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 17:07 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:11PM +0200, Jani Nikula wrote: > Define and store the pad base offset in the array, and reference the > pconf0 and padval registers through macros. Add VLV prefixes to > macros. Use spec nomenclature for pconf0 and padval. > > v2: Address Ville's review comments, squash another patch here. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 87 ++++++++++++++---------------- > 1 file changed, 39 insertions(+), 48 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index af1a47b5224f..b04d88e6127b 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -58,50 +58,41 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) > > #define NS_KHZ_RATIO 1000000 > > -#define GPI0_NC_0_HV_DDI0_HPD 0x4130 > -#define GPIO_NC_0_HV_DDI0_PAD 0x4138 > -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 > -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 > -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 > -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 > -#define GPIO_NC_3_PANEL0_VDDEN 0x4140 > -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 > -#define GPIO_NC_4_PANEL0_BLKEN 0x4150 > -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 > -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160 > -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 > -#define GPIO_NC_6_PCONF0 0x4180 > -#define GPIO_NC_6_PAD 0x4188 > -#define GPIO_NC_7_PCONF0 0x4190 > -#define GPIO_NC_7_PAD 0x4198 > -#define GPIO_NC_8_PCONF0 0x4170 > -#define GPIO_NC_8_PAD 0x4178 > -#define GPIO_NC_9_PCONF0 0x4100 > -#define GPIO_NC_9_PAD 0x4108 > -#define GPIO_NC_10_PCONF0 0x40E0 > -#define GPIO_NC_10_PAD 0x40E8 > -#define GPIO_NC_11_PCONF0 0x40F0 > -#define GPIO_NC_11_PAD 0x40F8 > +/* base offsets for gpio pads */ > +#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 > +#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 > +#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 > +#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 > +#define VLV_GPIO_NC_4_PANEL0_BLKEN 0x4150 > +#define VLV_GPIO_NC_5_PANEL0_BLKCTL 0x4160 > +#define VLV_GPIO_NC_6_PCONF0 0x4180 > +#define VLV_GPIO_NC_7_PCONF0 0x4190 > +#define VLV_GPIO_NC_8_PCONF0 0x4170 > +#define VLV_GPIO_NC_9_PCONF0 0x4100 > +#define VLV_GPIO_NC_10_PCONF0 0x40E0 > +#define VLV_GPIO_NC_11_PCONF0 0x40F0 Still looks wonky with those unnamed ones using _PCONF0, and some of the named ones not matching the spec 100%. Digging through the spec I came up with this list: #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 > + > +#define VLV_GPIO_PCONF0(base_offset) (base_offset) > +#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) > > struct gpio_table { > - u16 function_reg; > - u16 pad_reg; > - u8 init; > + u16 base_offset; > + bool init; > }; > > -static struct gpio_table gtable[] = { > - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, > - { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, > - { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, > - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, > - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, > - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, > - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, > - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, > - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, > - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, > - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, > - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} > +static struct gpio_table vlv_gpio_table[] = { > + { VLV_GPIO_NC_0_HV_DDI0_HPD }, > + { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, > + { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, > + { VLV_GPIO_NC_3_PANEL0_VDDEN }, > + { VLV_GPIO_NC_4_PANEL0_BLKEN }, > + { VLV_GPIO_NC_5_PANEL0_BLKCTL }, > + { VLV_GPIO_NC_6_PCONF0 }, > + { VLV_GPIO_NC_7_PCONF0 }, > + { VLV_GPIO_NC_8_PCONF0 }, > + { VLV_GPIO_NC_9_PCONF0 }, > + { VLV_GPIO_NC_10_PCONF0 }, > + { VLV_GPIO_NC_11_PCONF0 }, > }; > > static inline enum port intel_dsi_seq_port_to_port(u8 port) > @@ -199,7 +190,7 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > u8 gpio_source, gpio_index, action, port; > - u16 function, pad; > + u16 pconf0, padval; > u32 val; > struct drm_device *dev = intel_dsi->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -218,7 +209,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > /* pull up/down */ > action = *data++ & 1; > > - if (gpio_index >= ARRAY_SIZE(gtable)) { > + if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { > DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); > goto out; > } > @@ -242,21 +233,21 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > } > } > > - function = gtable[gpio_index].function_reg; > - pad = gtable[gpio_index].pad_reg; > + pconf0 = VLV_GPIO_PCONF0(vlv_gpio_table[gpio_index].base_offset); > + padval = VLV_GPIO_PAD_VAL(vlv_gpio_table[gpio_index].base_offset); > > mutex_lock(&dev_priv->sb_lock); > - if (!gtable[gpio_index].init) { > + if (!vlv_gpio_table[gpio_index].init) { > /* program the function */ > /* FIXME: remove constant below */ > - vlv_iosf_sb_write(dev_priv, port, function, 0x2000CC00); > - gtable[gpio_index].init = 1; > + vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); > + vlv_gpio_table[gpio_index].init = true; > } > > val = 0x4 | action; > > /* pull up/down */ > - vlv_iosf_sb_write(dev_priv, port, pad, val); > + vlv_iosf_sb_write(dev_priv, port, padval, val); > mutex_unlock(&dev_priv->sb_lock); > > out: > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (2 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-04-04 17:37 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 5/9] drm/i915/dsi: abstract VLV gpio element execution to a separate function Jani Nikula ` (5 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula This lets us specify the exact gpios we want to let through, without leaving holes in the array. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 54 ++++++++++++++++++------------ 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index b04d88e6127b..744368d01ee6 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -75,24 +75,25 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) #define VLV_GPIO_PCONF0(base_offset) (base_offset) #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) -struct gpio_table { +struct vlv_gpio_map { + u8 gpio_index; u16 base_offset; bool init; }; -static struct gpio_table vlv_gpio_table[] = { - { VLV_GPIO_NC_0_HV_DDI0_HPD }, - { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, - { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, - { VLV_GPIO_NC_3_PANEL0_VDDEN }, - { VLV_GPIO_NC_4_PANEL0_BLKEN }, - { VLV_GPIO_NC_5_PANEL0_BLKCTL }, - { VLV_GPIO_NC_6_PCONF0 }, - { VLV_GPIO_NC_7_PCONF0 }, - { VLV_GPIO_NC_8_PCONF0 }, - { VLV_GPIO_NC_9_PCONF0 }, - { VLV_GPIO_NC_10_PCONF0 }, - { VLV_GPIO_NC_11_PCONF0 }, +static struct vlv_gpio_map vlv_gpio_table[] = { + { 0, VLV_GPIO_NC_0_HV_DDI0_HPD }, + { 1, VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, + { 2, VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, + { 3, VLV_GPIO_NC_3_PANEL0_VDDEN }, + { 4, VLV_GPIO_NC_4_PANEL0_BLKEN }, + { 5, VLV_GPIO_NC_5_PANEL0_BLKCTL }, + { 6, VLV_GPIO_NC_6_PCONF0 }, + { 7, VLV_GPIO_NC_7_PCONF0 }, + { 8, VLV_GPIO_NC_8_PCONF0 }, + { 9, VLV_GPIO_NC_9_PCONF0 }, + { 10, VLV_GPIO_NC_10_PCONF0 }, + { 11, VLV_GPIO_NC_11_PCONF0 }, }; static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -194,6 +195,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) u32 val; struct drm_device *dev = intel_dsi->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct vlv_gpio_map *map = NULL; + int i; if (dev_priv->vbt.dsi.seq_version >= 3) data++; @@ -209,13 +212,20 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) /* pull up/down */ action = *data++ & 1; - if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { - DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); + if (!IS_VALLEYVIEW(dev_priv)) { + DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); goto out; } - if (!IS_VALLEYVIEW(dev_priv)) { - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); + for (i = 0; i < ARRAY_SIZE(vlv_gpio_table); i++) { + if (gpio_index == vlv_gpio_table[i].gpio_index) { + map = &vlv_gpio_table[i]; + break; + } + } + + if (!map) { + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); goto out; } @@ -233,15 +243,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) } } - pconf0 = VLV_GPIO_PCONF0(vlv_gpio_table[gpio_index].base_offset); - padval = VLV_GPIO_PAD_VAL(vlv_gpio_table[gpio_index].base_offset); + pconf0 = VLV_GPIO_PCONF0(map->base_offset); + padval = VLV_GPIO_PAD_VAL(map->base_offset); mutex_lock(&dev_priv->sb_lock); - if (!vlv_gpio_table[gpio_index].init) { + if (!map->init) { /* program the function */ /* FIXME: remove constant below */ vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); - vlv_gpio_table[gpio_index].init = true; + map->init = true; } val = 0x4 | action; -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table 2016-03-18 11:11 ` [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table Jani Nikula @ 2016-04-04 17:37 ` Ville Syrjälä 0 siblings, 0 replies; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 17:37 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:12PM +0200, Jani Nikula wrote: > This lets us specify the exact gpios we want to let through, without > leaving holes in the array. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 54 ++++++++++++++++++------------ > 1 file changed, 32 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index b04d88e6127b..744368d01ee6 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -75,24 +75,25 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) > #define VLV_GPIO_PCONF0(base_offset) (base_offset) > #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) > > -struct gpio_table { > +struct vlv_gpio_map { > + u8 gpio_index; Not really sure what we want to do with this one, since it's not really used in the series. Based on that I'd drop it for now. Anyways, u8+u16+bool doesn't pack all that nicely. Putting the bool and u8 next to each other would be better. > u16 base_offset; > bool init; > }; > > -static struct gpio_table vlv_gpio_table[] = { > - { VLV_GPIO_NC_0_HV_DDI0_HPD }, > - { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, > - { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, > - { VLV_GPIO_NC_3_PANEL0_VDDEN }, > - { VLV_GPIO_NC_4_PANEL0_BLKEN }, > - { VLV_GPIO_NC_5_PANEL0_BLKCTL }, > - { VLV_GPIO_NC_6_PCONF0 }, > - { VLV_GPIO_NC_7_PCONF0 }, > - { VLV_GPIO_NC_8_PCONF0 }, > - { VLV_GPIO_NC_9_PCONF0 }, > - { VLV_GPIO_NC_10_PCONF0 }, > - { VLV_GPIO_NC_11_PCONF0 }, > +static struct vlv_gpio_map vlv_gpio_table[] = { > + { 0, VLV_GPIO_NC_0_HV_DDI0_HPD }, > + { 1, VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, > + { 2, VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, > + { 3, VLV_GPIO_NC_3_PANEL0_VDDEN }, > + { 4, VLV_GPIO_NC_4_PANEL0_BLKEN }, > + { 5, VLV_GPIO_NC_5_PANEL0_BLKCTL }, > + { 6, VLV_GPIO_NC_6_PCONF0 }, > + { 7, VLV_GPIO_NC_7_PCONF0 }, > + { 8, VLV_GPIO_NC_8_PCONF0 }, > + { 9, VLV_GPIO_NC_9_PCONF0 }, > + { 10, VLV_GPIO_NC_10_PCONF0 }, > + { 11, VLV_GPIO_NC_11_PCONF0 }, > }; > > static inline enum port intel_dsi_seq_port_to_port(u8 port) > @@ -194,6 +195,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > u32 val; > struct drm_device *dev = intel_dsi->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > + struct vlv_gpio_map *map = NULL; > + int i; > > if (dev_priv->vbt.dsi.seq_version >= 3) > data++; > @@ -209,13 +212,20 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > /* pull up/down */ > action = *data++ & 1; > > - if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { > - DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); > + if (!IS_VALLEYVIEW(dev_priv)) { > + DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > goto out; > } > > - if (!IS_VALLEYVIEW(dev_priv)) { > - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > + for (i = 0; i < ARRAY_SIZE(vlv_gpio_table); i++) { > + if (gpio_index == vlv_gpio_table[i].gpio_index) { > + map = &vlv_gpio_table[i]; > + break; > + } > + } > + > + if (!map) { > + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); > goto out; > } > > @@ -233,15 +243,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > } > } > > - pconf0 = VLV_GPIO_PCONF0(vlv_gpio_table[gpio_index].base_offset); > - padval = VLV_GPIO_PAD_VAL(vlv_gpio_table[gpio_index].base_offset); > + pconf0 = VLV_GPIO_PCONF0(map->base_offset); > + padval = VLV_GPIO_PAD_VAL(map->base_offset); > > mutex_lock(&dev_priv->sb_lock); > - if (!vlv_gpio_table[gpio_index].init) { > + if (!map->init) { > /* program the function */ > /* FIXME: remove constant below */ > vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); > - vlv_gpio_table[gpio_index].init = true; > + map->init = true; > } > > val = 0x4 | action; > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 5/9] drm/i915/dsi: abstract VLV gpio element execution to a separate function 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (3 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-03-18 11:11 ` [PATCH v2 6/9] drm/i915/dsi: add support for sequence block v3 gpio for VLV Jani Nikula ` (4 subsequent siblings) 9 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula Prepare for future. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 63 ++++++++++++++++-------------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 744368d01ee6..3f84c0f96eeb 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -188,35 +188,15 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) return data; } -static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) +static void vlv_exec_gpio(struct drm_i915_private *dev_priv, + u8 gpio_source, u8 gpio_index, u8 action) { - u8 gpio_source, gpio_index, action, port; - u16 pconf0, padval; - u32 val; - struct drm_device *dev = intel_dsi->base.base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; struct vlv_gpio_map *map = NULL; + u32 val; + u16 pconf0, padval; + u8 port; int i; - if (dev_priv->vbt.dsi.seq_version >= 3) - data++; - - gpio_index = *data++; - - /* gpio source in sequence v2 only */ - if (dev_priv->vbt.dsi.seq_version == 2) - gpio_source = (*data >> 1) & 3; - else - gpio_source = 0; - - /* pull up/down */ - action = *data++ & 1; - - if (!IS_VALLEYVIEW(dev_priv)) { - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); - goto out; - } - for (i = 0; i < ARRAY_SIZE(vlv_gpio_table); i++) { if (gpio_index == vlv_gpio_table[i].gpio_index) { map = &vlv_gpio_table[i]; @@ -226,12 +206,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) if (!map) { DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); - goto out; + return; } if (dev_priv->vbt.dsi.seq_version >= 3) { DRM_DEBUG_KMS("GPIO element v3 not supported\n"); - goto out; + return; } else { if (gpio_source == 0) { port = IOSF_PORT_GPIO_NC; @@ -239,7 +219,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) port = IOSF_PORT_GPIO_SC; } else { DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); - goto out; + return; } } @@ -259,8 +239,33 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) /* pull up/down */ vlv_iosf_sb_write(dev_priv, port, padval, val); mutex_unlock(&dev_priv->sb_lock); +} + +static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) +{ + struct drm_device *dev = intel_dsi->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u8 gpio_source, gpio_index, action; + + if (dev_priv->vbt.dsi.seq_version >= 3) + data++; + + gpio_index = *data++; + + /* gpio source in sequence v2 only */ + if (dev_priv->vbt.dsi.seq_version == 2) + gpio_source = (*data >> 1) & 3; + else + gpio_source = 0; + + /* pull up/down */ + action = *data++ & 1; + + if (IS_VALLEYVIEW(dev_priv)) + vlv_exec_gpio(dev_priv, gpio_source, gpio_index, action); + else + DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); -out: return data; } -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 6/9] drm/i915/dsi: add support for sequence block v3 gpio for VLV 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (4 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 5/9] drm/i915/dsi: abstract VLV gpio element execution to a separate function Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-03-18 11:11 ` [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions Jani Nikula ` (3 subsequent siblings) 9 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula Just put the iosf port in the gpio table. The table might include some duplication, but this approach keeps the code the cleanest. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 3f84c0f96eeb..ca48f7aa6a05 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -77,23 +77,24 @@ static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) struct vlv_gpio_map { u8 gpio_index; + u8 port; u16 base_offset; bool init; }; static struct vlv_gpio_map vlv_gpio_table[] = { - { 0, VLV_GPIO_NC_0_HV_DDI0_HPD }, - { 1, VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, - { 2, VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, - { 3, VLV_GPIO_NC_3_PANEL0_VDDEN }, - { 4, VLV_GPIO_NC_4_PANEL0_BLKEN }, - { 5, VLV_GPIO_NC_5_PANEL0_BLKCTL }, - { 6, VLV_GPIO_NC_6_PCONF0 }, - { 7, VLV_GPIO_NC_7_PCONF0 }, - { 8, VLV_GPIO_NC_8_PCONF0 }, - { 9, VLV_GPIO_NC_9_PCONF0 }, - { 10, VLV_GPIO_NC_10_PCONF0 }, - { 11, VLV_GPIO_NC_11_PCONF0 }, + { 0, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_0_HV_DDI0_HPD }, + { 1, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, + { 2, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, + { 3, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_3_PANEL0_VDDEN }, + { 4, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_4_PANEL0_BLKEN }, + { 5, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_5_PANEL0_BLKCTL }, + { 6, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_6_PCONF0 }, + { 7, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_7_PCONF0 }, + { 8, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_8_PCONF0 }, + { 9, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_9_PCONF0 }, + { 10, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_10_PCONF0 }, + { 11, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_11_PCONF0 }, }; static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -210,8 +211,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, } if (dev_priv->vbt.dsi.seq_version >= 3) { - DRM_DEBUG_KMS("GPIO element v3 not supported\n"); - return; + port = map->port; } else { if (gpio_source == 0) { port = IOSF_PORT_GPIO_NC; -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (5 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 6/9] drm/i915/dsi: add support for sequence block v3 gpio for VLV Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-04-04 17:43 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV Jani Nikula ` (2 subsequent siblings) 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 07e04495cd9a..6e36c0d51023 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -623,6 +623,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define IOSF_PORT_GPIO_SC 0x48 #define IOSF_PORT_GPIO_SUS 0xa8 #define IOSF_PORT_CCU 0xa9 +#define CHV_IOSF_PORT_GPIO_N 0x13 +#define CHV_IOSF_PORT_GPIO_SE 0x48 +#define CHV_IOSF_PORT_GPIO_E 0xa8 +#define CHV_IOSF_PORT_GPIO_SW 0xb2 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions 2016-03-18 11:11 ` [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions Jani Nikula @ 2016-04-04 17:43 ` Ville Syrjälä 2016-04-05 7:34 ` Jani Nikula 0 siblings, 1 reply; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 17:43 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:15PM +0200, Jani Nikula wrote: > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 07e04495cd9a..6e36c0d51023 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -623,6 +623,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define IOSF_PORT_GPIO_SC 0x48 > #define IOSF_PORT_GPIO_SUS 0xa8 > #define IOSF_PORT_CCU 0xa9 > +#define CHV_IOSF_PORT_GPIO_N 0x13 > +#define CHV_IOSF_PORT_GPIO_SE 0x48 > +#define CHV_IOSF_PORT_GPIO_E 0xa8 > +#define CHV_IOSF_PORT_GPIO_SW 0xb2 > #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) > #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) > > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions 2016-04-04 17:43 ` Ville Syrjälä @ 2016-04-05 7:34 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-04-05 7:34 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Deepak M, intel-gfx On Mon, 04 Apr 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Fri, Mar 18, 2016 at 01:11:15PM +0200, Jani Nikula wrote: >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pushed to drm-intel-next-queued, thanks for the review. BR, Jani. > >> --- >> drivers/gpu/drm/i915/i915_reg.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 07e04495cd9a..6e36c0d51023 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -623,6 +623,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> #define IOSF_PORT_GPIO_SC 0x48 >> #define IOSF_PORT_GPIO_SUS 0xa8 >> #define IOSF_PORT_CCU 0xa9 >> +#define CHV_IOSF_PORT_GPIO_N 0x13 >> +#define CHV_IOSF_PORT_GPIO_SE 0x48 >> +#define CHV_IOSF_PORT_GPIO_E 0xa8 >> +#define CHV_IOSF_PORT_GPIO_SW 0xb2 >> #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) >> #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) >> >> -- >> 2.1.4 -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (6 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-04-04 18:11 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support Jani Nikula 2016-03-21 8:52 ` ✗ Fi.CI.BAT: warning for drm/i915/dsi: improved gpio element support for vlv/chv/bxt Patchwork 9 siblings, 1 reply; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Add support for CHV gpio programming in DSI gpio elements. XXX: I'd like to have a gpio table for chv as well as others. [Rewritten by Jani, based on earlier work by Yogesh and Deepak.] Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 66 ++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index ca48f7aa6a05..f8d3f608e9c8 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -97,6 +97,23 @@ static struct vlv_gpio_map vlv_gpio_table[] = { { 11, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_11_PCONF0 }, }; +#define CHV_MAX_GPIO_NUM_N 72 +#define CHV_MAX_GPIO_NUM_SE 99 +#define CHV_MAX_GPIO_NUM_SW 197 +#define CHV_MIN_GPIO_NUM_SE 73 +#define CHV_MIN_GPIO_NUM_SW 100 +#define CHV_MIN_GPIO_NUM_E 198 + +#define CHV_PAD_FMLY_BASE 0x4400 +#define CHV_PAD_FMLY_SIZE 0x400 +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8 +#define CHV_PAD_CFG_REG_SIZE 0x4 +#define CHV_VBT_MAX_PINS_PER_FMLY 15 + +#define CHV_GPIO_CFG_UNLOCK 0x00000000 +#define CHV_GPIO_CFG_HIZ 0x00008100 +#define CHV_GPIO_CFG_TX_STATE_SHIFT 1 + static inline enum port intel_dsi_seq_port_to_port(u8 port) { return port ? PORT_C : PORT_A; @@ -241,6 +258,53 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, mutex_unlock(&dev_priv->sb_lock); } +static void chv_exec_gpio(struct drm_i915_private *dev_priv, + u8 gpio_source, u8 gpio_index, u8 action) +{ + u16 pconf0, padval; + u16 family_num; + u8 port; + + /* XXX: add a table similar to vlv for checking gpio indexes */ + if (dev_priv->vbt.dsi.seq_version >= 3) { + if (gpio_index <= CHV_MAX_GPIO_NUM_N) { + port = CHV_IOSF_PORT_GPIO_N; + } else if (gpio_index <= CHV_MAX_GPIO_NUM_SE) { + port = CHV_IOSF_PORT_GPIO_SE; + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SE; + } else if (gpio_index <= CHV_MAX_GPIO_NUM_SW) { + port = CHV_IOSF_PORT_GPIO_SW; + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SW; + } else { + port = CHV_IOSF_PORT_GPIO_E; + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_E; + } + } else if (dev_priv->vbt.dsi.seq_version == 2) { + if (gpio_source == 0) { + port = IOSF_PORT_GPIO_NC; + } else if (gpio_source == 1) { + port = IOSF_PORT_GPIO_SC; + } else { + DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + return; + } + } else { + port = IOSF_PORT_GPIO_NC; + } + + family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; + gpio_index = gpio_index - (family_num * CHV_VBT_MAX_PINS_PER_FMLY); + padval = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) + + (((u16)gpio_index) * CHV_PAD_CFG_0_1_REG_SIZE); + pconf0 = padval + CHV_PAD_CFG_REG_SIZE; + + mutex_lock(&dev_priv->sb_lock); + vlv_iosf_sb_write(dev_priv, port, pconf0, CHV_GPIO_CFG_UNLOCK); + vlv_iosf_sb_write(dev_priv, port, padval, CHV_GPIO_CFG_HIZ | + (action << CHV_GPIO_CFG_TX_STATE_SHIFT)); + mutex_unlock(&dev_priv->sb_lock); +} + static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) { struct drm_device *dev = intel_dsi->base.base.dev; @@ -263,6 +327,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) if (IS_VALLEYVIEW(dev_priv)) vlv_exec_gpio(dev_priv, gpio_source, gpio_index, action); + else if (IS_CHERRYVIEW(dev_priv)) + chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); else DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV 2016-03-18 11:11 ` [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV Jani Nikula @ 2016-04-04 18:11 ` Ville Syrjälä 0 siblings, 0 replies; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 18:11 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:16PM +0200, Jani Nikula wrote: > From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> > > Add support for CHV gpio programming in DSI gpio elements. > > XXX: I'd like to have a gpio table for chv as well as others. > > [Rewritten by Jani, based on earlier work by Yogesh and Deepak.] > > Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> > Signed-off-by: Deepak M <m.deepak@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 66 ++++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index ca48f7aa6a05..f8d3f608e9c8 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -97,6 +97,23 @@ static struct vlv_gpio_map vlv_gpio_table[] = { > { 11, IOSF_PORT_GPIO_NC, VLV_GPIO_NC_11_PCONF0 }, > }; > > +#define CHV_MAX_GPIO_NUM_N 72 > +#define CHV_MAX_GPIO_NUM_SE 99 > +#define CHV_MAX_GPIO_NUM_SW 197 > +#define CHV_MIN_GPIO_NUM_SE 73 > +#define CHV_MIN_GPIO_NUM_SW 100 > +#define CHV_MIN_GPIO_NUM_E 198 Not sure why we need min+max for these. I would probably just do something like: #define CHV_GPIO_IDX_START_N 0 #define CHV_GPIO_IDX_START_SE 73 #define CHV_GPIO_IDX_START_SW 100 #define CHV_GPIO_IDX_START_SE 198 > + > +#define CHV_PAD_FMLY_BASE 0x4400 > +#define CHV_PAD_FMLY_SIZE 0x400 > +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8 > +#define CHV_PAD_CFG_REG_SIZE 0x4 I'd hide all the uglies that use these in macros like: #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) > +#define CHV_VBT_MAX_PINS_PER_FMLY 15 > + > +#define CHV_GPIO_CFG_UNLOCK 0x00000000 Maybe just define the bit for documentation purpose and just write a raw 0 to the register. #define CHV_GPIO_CFGLOCK (1 << 31) > +#define CHV_GPIO_CFG_HIZ 0x00008100 That's still not hiz. #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) #define CHV_GPIO_GPIOCFG_GPO (1 << 8) #define CHV_GPIO_GPIOCFG_GPI (2 << 8) #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) #define CHV_GPIO_GPIOEN (1 << 15) > +#define CHV_GPIO_CFG_TX_STATE_SHIFT 1 Maybe #define CHV_GPIO_GPIOTXSTATE(state) ((state) << 1) > + > static inline enum port intel_dsi_seq_port_to_port(u8 port) > { > return port ? PORT_C : PORT_A; > @@ -241,6 +258,53 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, > mutex_unlock(&dev_priv->sb_lock); > } > > +static void chv_exec_gpio(struct drm_i915_private *dev_priv, > + u8 gpio_source, u8 gpio_index, u8 action) > +{ > + u16 pconf0, padval; cfg0, cfg1 to match the reg names. Or just drop them entirely since the parametrized macros I suggested earlier would make thing very clear without temp variables. > + u16 family_num; > + u8 port; > + > + /* XXX: add a table similar to vlv for checking gpio indexes */ If we bother going that far, then I think we should just go for gpiolib instead. > + if (dev_priv->vbt.dsi.seq_version >= 3) { > + if (gpio_index <= CHV_MAX_GPIO_NUM_N) { > + port = CHV_IOSF_PORT_GPIO_N; > + } else if (gpio_index <= CHV_MAX_GPIO_NUM_SE) { > + port = CHV_IOSF_PORT_GPIO_SE; > + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SE; > + } else if (gpio_index <= CHV_MAX_GPIO_NUM_SW) { > + port = CHV_IOSF_PORT_GPIO_SW; > + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_SW; > + } else { > + port = CHV_IOSF_PORT_GPIO_E; > + gpio_index = gpio_index - CHV_MIN_GPIO_NUM_E; > + } > + } else if (dev_priv->vbt.dsi.seq_version == 2) { > + if (gpio_source == 0) { > + port = IOSF_PORT_GPIO_NC; > + } else if (gpio_source == 1) { > + port = IOSF_PORT_GPIO_SC; > + } else { > + DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); > + return; > + } > + } else { > + port = IOSF_PORT_GPIO_NC; > + } > + > + family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; > + gpio_index = gpio_index - (family_num * CHV_VBT_MAX_PINS_PER_FMLY); I'd still use % for clarity. > + padval = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) + > + (((u16)gpio_index) * CHV_PAD_CFG_0_1_REG_SIZE); > + pconf0 = padval + CHV_PAD_CFG_REG_SIZE; > + > + mutex_lock(&dev_priv->sb_lock); > + vlv_iosf_sb_write(dev_priv, port, pconf0, CHV_GPIO_CFG_UNLOCK); > + vlv_iosf_sb_write(dev_priv, port, padval, CHV_GPIO_CFG_HIZ | > + (action << CHV_GPIO_CFG_TX_STATE_SHIFT)); > + mutex_unlock(&dev_priv->sb_lock); > +} > + > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -263,6 +327,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > > if (IS_VALLEYVIEW(dev_priv)) > vlv_exec_gpio(dev_priv, gpio_source, gpio_index, action); > + else if (IS_CHERRYVIEW(dev_priv)) > + chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); > else > DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (7 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV Jani Nikula @ 2016-03-18 11:11 ` Jani Nikula 2016-03-23 10:55 ` Mika Kahola 2016-04-04 17:46 ` Ville Syrjälä 2016-03-21 8:52 ` ✗ Fi.CI.BAT: warning for drm/i915/dsi: improved gpio element support for vlv/chv/bxt Patchwork 9 siblings, 2 replies; 23+ messages in thread From: Jani Nikula @ 2016-03-18 11:11 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak M, jani.nikula Use a table similar to vlv to check for accepted gpio indexes. For now, add all, but this list should be trimmed down. Use managed gpio request, which will be automatically released when the driver is detached. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 667 ++++++++++++++++++++++++++++- 1 file changed, 666 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index f8d3f608e9c8..6b8dc15f3656 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -29,6 +29,7 @@ #include <drm/drm_edid.h> #include <drm/i915_drm.h> #include <drm/drm_panel.h> +#include <linux/gpio.h> #include <linux/slab.h> #include <video/mipi_display.h> #include <asm/intel-mid.h> @@ -114,6 +115,636 @@ static struct vlv_gpio_map vlv_gpio_table[] = { #define CHV_GPIO_CFG_HIZ 0x00008100 #define CHV_GPIO_CFG_TX_STATE_SHIFT 1 +#define BXT_HV_DDI0_DDC_SDA_PIN 187 +#define BXT_HV_DDI0_DDC_SCL_PIN 188 +#define BXT_HV_DDI1_DDC_SDA_PIN 189 +#define BXT_HV_DDI1_DDC_SCL_PIN 190 +#define BXT_DBI_SDA_PIN 191 +#define BXT_DBI_SCL_PIN 192 +#define BXT_PANEL0_VDDEN_PIN 193 +#define BXT_PANEL0_BKLTEN_PIN 194 +#define BXT_PANEL0_BKLTCTL_PIN 195 +#define BXT_PANEL1_VDDEN_PIN 196 +#define BXT_PANEL1_BKLTEN_PIN 197 +#define BXT_PANEL1_BKLTCTL_PIN 198 +#define BXT_DBI_CSX_PIN 199 +#define BXT_DBI_RESX_PIN 200 +#define BXT_GP_INTD_DSI_TE1_PIN 201 +#define BXT_GP_INTD_DSI_TE2_PIN 202 +#define BXT_USB_OC0_B_PIN 203 +#define BXT_USB_OC1_B_PIN 204 +#define BXT_MEX_WAKE0_B_PIN 205 +#define BXT_MEX_WAKE1_B_PIN 206 +#define BXT_EMMC0_CLK_PIN 156 +#define BXT_EMMC0_D0_PIN 157 +#define BXT_EMMC0_D1_PIN 158 +#define BXT_EMMC0_D2_PIN 159 +#define BXT_EMMC0_D3_PIN 160 +#define BXT_EMMC0_D4_PIN 161 +#define BXT_EMMC0_D5_PIN 162 +#define BXT_EMMC0_D6_PIN 163 +#define BXT_EMMC0_D7_PIN 164 +#define BXT_EMMC0_CMD_PIN 165 +#define BXT_SDIO_CLK_PIN 166 +#define BXT_SDIO_D0_PIN 167 +#define BXT_SDIO_D1_PIN 168 +#define BXT_SDIO_D2_PIN 169 +#define BXT_SDIO_D3_PIN 170 +#define BXT_SDIO_CMD_PIN 171 +#define BXT_SDCARD_CLK_PIN 172 +#define BXT_SDCARD_D0_PIN 173 +#define BXT_SDCARD_D1_PIN 174 +#define BXT_SDCARD_D2_PIN 175 +#define BXT_SDCARD_D3_PIN 176 +#define BXT_SDCARD_CD_B_PIN 177 +#define BXT_SDCARD_CMD_PIN 178 +#define BXT_SDCARD_LVL_CLK_FB_PIN 179 +#define BXT_SDCARD_LVL_CMD_DIR_PIN 180 +#define BXT_SDCARD_LVL_DAT_DIR_PIN 181 +#define BXT_EMMC0_STROBE_PIN 182 +#define BXT_SDIO_PWR_DOWN_B_PIN 183 +#define BXT_SDCARD_PWR_DOWN_B_PIN 184 +#define BXT_SDCARD_LVL_SEL_PIN 185 +#define BXT_SDCARD_LVL_WP_PIN 186 +#define BXT_LPSS_I2C0_SDA_PIN 124 +#define BXT_LPSS_I2C0_SCL_PIN 125 +#define BXT_LPSS_I2C1_SDA_PIN 126 +#define BXT_LPSS_I2C1_SCL_PIN 127 +#define BXT_LPSS_I2C2_SDA_PIN 128 +#define BXT_LPSS_I2C2_SCL_PIN 129 +#define BXT_LPSS_I2C3_SDA_PIN 130 +#define BXT_LPSS_I2C3_SCL_PIN 131 +#define BXT_LPSS_I2C4_SDA_PIN 132 +#define BXT_LPSS_I2C4_SCL_PIN 133 +#define BXT_LPSS_I2C5_SDA_PIN 134 +#define BXT_LPSS_I2C5_SCL_PIN 135 +#define BXT_LPSS_I2C6_SDA_PIN 136 +#define BXT_LPSS_I2C6_SCL_PIN 137 +#define BXT_LPSS_I2C7_SDA_PIN 138 +#define BXT_LPSS_I2C7_SCL_PIN 139 +#define BXT_ISH_I2C0_SDA_PIN 140 +#define BXT_ISH_I2C0_SCL_PIN 141 +#define BXT_ISH_I2C1_SDA_PIN 142 +#define BXT_ISH_I2C1_SCL_PIN 143 +#define BXT_ISH_I2C2_SDA_PIN 144 +#define BXT_ISH_I2C2_SCL_PIN 145 +#define BXT_ISH_GPIO_0_PIN 146 +#define BXT_ISH_GPIO_1_PIN 147 +#define BXT_ISH_GPIO_2_PIN 148 +#define BXT_ISH_GPIO_3_PIN 149 +#define BXT_ISH_GPIO_4_PIN 150 +#define BXT_ISH_GPIO_5_PIN 151 +#define BXT_ISH_GPIO_6_PIN 152 +#define BXT_ISH_GPIO_7_PIN 153 +#define BXT_ISH_GPIO_8_PIN 154 +#define BXT_ISH_GPIO_9_PIN 155 +#define BXT_AVS_I2S1_MCLK_PIN 74 +#define BXT_AVS_I2S1_BCLK_PIN 75 +#define BXT_AVS_I2S1_WS_SYNC_PIN 76 +#define BXT_AVS_I2S1_SDI_PIN 77 +#define BXT_AVS_I2S1_SDO_PIN 78 +#define BXT_AVS_M_CLK_A1_PIN 79 +#define BXT_AVS_M_CLK_B1_PIN 80 +#define BXT_AVS_M_DATA_1_PIN 81 +#define BXT_AVS_M_CLK_AB2_PIN 82 +#define BXT_AVS_M_DATA_2_PIN 83 +#define BXT_AVS_I2S2_MCLK_PIN 84 +#define BXT_AVS_I2S2_BCLK_PIN 85 +#define BXT_AVS_I2S2_WS_SYNC_PIN 86 +#define BXT_AVS_I2S2_SDI_PIN 87 +#define BXT_AVS_I2S2_SDO_PIN 88 +#define BXT_AVS_I2S3_BCLK_PIN 89 +#define BXT_AVS_I2S3_WS_SYNC_PIN 90 +#define BXT_AVS_I2S3_SDI_PIN 91 +#define BXT_AVS_I2S3_SDO_PIN 92 +#define BXT_AVS_I2S4_BCLK_PIN 93 +#define BXT_AVS_I2S4_WS_SYNC_PIN 94 +#define BXT_AVS_I2S4_SDI_PIN 95 +#define BXT_AVS_I2S4_SDO_PIN 96 +#define BXT_FST_SPI_CS0_B_PIN 97 +#define BXT_FST_SPI_CS1_B_PIN 98 +#define BXT_FST_SPI_MOSI_IO0_PIN 99 +#define BXT_FST_SPI_MISO_IO1_PIN 100 +#define BXT_FST_SPI_IO2_PIN 101 +#define BXT_FST_SPI_IO3_PIN 102 +#define BXT_FST_SPI_CLK_PIN 103 +#define BXT_GP_SSP_0_CLK_PIN 104 +#define BXT_GP_SSP_0_FS0_PIN 105 +#define BXT_GP_SSP_0_FS1_PIN 106 +#define BXT_GP_SSP_0_FS2_PIN 107 +#define BXT_GP_SSP_0_RXD_PIN 109 +#define BXT_GP_SSP_0_TXD_PIN 110 +#define BXT_GP_SSP_1_CLK_PIN 111 +#define BXT_GP_SSP_1_FS0_PIN 112 +#define BXT_GP_SSP_1_FS1_PIN 113 +#define BXT_GP_SSP_1_FS2_PIN 114 +#define BXT_GP_SSP_1_FS3_PIN 115 +#define BXT_GP_SSP_1_RXD_PIN 116 +#define BXT_GP_SSP_1_TXD_PIN 117 +#define BXT_GP_SSP_2_CLK_PIN 118 +#define BXT_GP_SSP_2_FS0_PIN 119 +#define BXT_GP_SSP_2_FS1_PIN 120 +#define BXT_GP_SSP_2_FS2_PIN 121 +#define BXT_GP_SSP_2_RXD_PIN 122 +#define BXT_GP_SSP_2_TXD_PIN 123 +#define BXT_TRACE_0_CLK_VNN_PIN 0 +#define BXT_TRACE_0_DATA0_VNN_PIN 1 +#define BXT_TRACE_0_DATA1_VNN_PIN 2 +#define BXT_TRACE_0_DATA2_VNN_PIN 3 +#define BXT_TRACE_0_DATA3_VNN_PIN 4 +#define BXT_TRACE_0_DATA4_VNN_PIN 5 +#define BXT_TRACE_0_DATA5_VNN_PIN 6 +#define BXT_TRACE_0_DATA6_VNN_PIN 7 +#define BXT_TRACE_0_DATA7_VNN_PIN 8 +#define BXT_TRACE_1_CLK_VNN_PIN 9 +#define BXT_TRACE_1_DATA0_VNN_PIN 10 +#define BXT_TRACE_1_DATA1_VNN_PIN 11 +#define BXT_TRACE_1_DATA2_VNN_PIN 12 +#define BXT_TRACE_1_DATA3_VNN_PIN 13 +#define BXT_TRACE_1_DATA4_VNN_PIN 14 +#define BXT_TRACE_1_DATA5_VNN_PIN 15 +#define BXT_TRACE_1_DATA6_VNN_PIN 16 +#define BXT_TRACE_1_DATA7_VNN_PIN 17 +#define BXT_TRACE_2_CLK_VNN_PIN 18 +#define BXT_TRACE_2_DATA0_VNN_PIN 19 +#define BXT_TRACE_2_DATA1_VNN_PIN 20 +#define BXT_TRACE_2_DATA2_VNN_PIN 21 +#define BXT_TRACE_2_DATA3_VNN_PIN 22 +#define BXT_TRACE_2_DATA4_VNN_PIN 23 +#define BXT_TRACE_2_DATA5_VNN_PIN 24 +#define BXT_TRACE_2_DATA6_VNN_PIN 25 +#define BXT_TRACE_2_DATA7_VNN_PIN 26 +#define BXT_TRIGOUT_0_PIN 27 +#define BXT_TRIGOUT_1_PIN 28 +#define BXT_TRIGIN_0_PIN 29 +#define BXT_SEC_TCK_PIN 30 +#define BXT_SEC_TDI_PIN 31 +#define BXT_SEC_TMS_PIN 32 +#define BXT_SEC_TDO_PIN 33 +#define BXT_PWM0_PIN 34 +#define BXT_PWM1_PIN 35 +#define BXT_PWM2_PIN 36 +#define BXT_PWM3_PIN 37 +#define BXT_LPSS_UART0_RXD_PIN 38 +#define BXT_LPSS_UART0_TXD_PIN 39 +#define BXT_LPSS_UART0_RTS_B_PIN 40 +#define BXT_LPSS_UART0_CTS_B_PIN 41 +#define BXT_LPSS_UART1_RXD_PIN 42 +#define BXT_LPSS_UART1_TXD_PIN 43 +#define BXT_LPSS_UART1_RTS_B_PIN 44 +#define BXT_LPSS_UART1_CTS_B_PIN 45 +#define BXT_LPSS_UART2_RXD_PIN 46 +#define BXT_LPSS_UART2_TXD_PIN 47 +#define BXT_LPSS_UART2_RTS_B_PIN 48 +#define BXT_LPSS_UART2_CTS_B_PIN 49 +#define BXT_ISH_UART0_RXD_PIN 50 +#define BXT_ISH_UART0_TXD_PIN 51 +#define BXT_ISH_UART0_RTS_B_PIN 52 +#define BXT_ISH_UART0_CTS_B_PIN 53 +#define BXT_ISH_UART1_RXD_PIN 54 +#define BXT_ISH_UART1_TXD_PIN 55 +#define BXT_ISH_UART1_RTS_B_PIN 56 +#define BXT_ISH_UART1_CTS_B_PIN 57 +#define BXT_ISH_UART2_RXD_PIN 58 +#define BXT_ISH_UART2_TXD_PIN 59 +#define BXT_ISH_UART2_RTS_B_PIN 60 +#define BXT_ISH_UART2_CTS_B_PIN 61 +#define BXT_GP_CAMERASB00_PIN 62 +#define BXT_GP_CAMERASB01_PIN 63 +#define BXT_GP_CAMERASB02_PIN 64 +#define BXT_GP_CAMERASB03_PIN 65 +#define BXT_GP_CAMERASB04_PIN 66 +#define BXT_GP_CAMERASB05_PIN 67 +#define BXT_GP_CAMERASB06_PIN 68 +#define BXT_GP_CAMERASB07_PIN 69 +#define BXT_GP_CAMERASB08_PIN 70 +#define BXT_GP_CAMERASB09_PIN 71 +#define BXT_GP_CAMERASB10_PIN 72 +#define BXT_GP_CAMERASB11_PIN 73 + +#define BXT_HV_DDI0_DDC_SDA_OFFSET 264 +#define BXT_HV_DDI0_DDC_SCL_OFFSET 265 +#define BXT_HV_DDI1_DDC_SDA_OFFSET 266 +#define BXT_HV_DDI1_DDC_SCL_OFFSET 267 +#define BXT_DBI_SDA_OFFSET 268 +#define BXT_DBI_SCL_OFFSET 269 +#define BXT_PANEL0_VDDEN_OFFSET 270 +#define BXT_PANEL0_BKLTEN_OFFSET 271 +#define BXT_PANEL0_BKLTCTL_OFFSET 272 +#define BXT_PANEL1_VDDEN_OFFSET 273 +#define BXT_PANEL1_BKLTEN_OFFSET 274 +#define BXT_PANEL1_BKLTCTL_OFFSET 275 +#define BXT_DBI_CSX_OFFSET 276 +#define BXT_DBI_RESX_OFFSET 277 +#define BXT_GP_INTD_DSI_TE1_OFFSET 278 +#define BXT_GP_INTD_DSI_TE2_OFFSET 279 +#define BXT_USB_OC0_B_OFFSET 280 +#define BXT_USB_OC1_B_OFFSET 281 +#define BXT_MEX_WAKE0_B_OFFSET 282 +#define BXT_MEX_WAKE1_B_OFFSET 283 +#define BXT_EMMC0_CLK_OFFSET 284 +#define BXT_EMMC0_D0_OFFSET 285 +#define BXT_EMMC0_D1_OFFSET 286 +#define BXT_EMMC0_D2_OFFSET 287 +#define BXT_EMMC0_D3_OFFSET 288 +#define BXT_EMMC0_D4_OFFSET 289 +#define BXT_EMMC0_D5_OFFSET 290 +#define BXT_EMMC0_D6_OFFSET 291 +#define BXT_EMMC0_D7_OFFSET 292 +#define BXT_EMMC0_CMD_OFFSET 293 +#define BXT_SDIO_CLK_OFFSET 294 +#define BXT_SDIO_D0_OFFSET 295 +#define BXT_SDIO_D1_OFFSET 296 +#define BXT_SDIO_D2_OFFSET 297 +#define BXT_SDIO_D3_OFFSET 298 +#define BXT_SDIO_CMD_OFFSET 299 +#define BXT_SDCARD_CLK_OFFSET 300 +#define BXT_SDCARD_D0_OFFSET 301 +#define BXT_SDCARD_D1_OFFSET 302 +#define BXT_SDCARD_D2_OFFSET 303 +#define BXT_SDCARD_D3_OFFSET 304 +#define BXT_SDCARD_CD_B_OFFSET 305 +#define BXT_SDCARD_CMD_OFFSET 306 +#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307 +#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308 +#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309 +#define BXT_EMMC0_STROBE_OFFSET 310 +#define BXT_SDIO_PWR_DOWN_B_OFFSET 311 +#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312 +#define BXT_SDCARD_LVL_SEL_OFFSET 313 +#define BXT_SDCARD_LVL_WP_OFFSET 314 +#define BXT_LPSS_I2C0_SDA_OFFSET 315 +#define BXT_LPSS_I2C0_SCL_OFFSET 316 +#define BXT_LPSS_I2C1_SDA_OFFSET 317 +#define BXT_LPSS_I2C1_SCL_OFFSET 318 +#define BXT_LPSS_I2C2_SDA_OFFSET 319 +#define BXT_LPSS_I2C2_SCL_OFFSET 320 +#define BXT_LPSS_I2C3_SDA_OFFSET 321 +#define BXT_LPSS_I2C3_SCL_OFFSET 322 +#define BXT_LPSS_I2C4_SDA_OFFSET 323 +#define BXT_LPSS_I2C4_SCL_OFFSET 324 +#define BXT_LPSS_I2C5_SDA_OFFSET 325 +#define BXT_LPSS_I2C5_SCL_OFFSET 326 +#define BXT_LPSS_I2C6_SDA_OFFSET 327 +#define BXT_LPSS_I2C6_SCL_OFFSET 328 +#define BXT_LPSS_I2C7_SDA_OFFSET 329 +#define BXT_LPSS_I2C7_SCL_OFFSET 330 +#define BXT_ISH_I2C0_SDA_OFFSET 331 +#define BXT_ISH_I2C0_SCL_OFFSET 332 +#define BXT_ISH_I2C1_SDA_OFFSET 333 +#define BXT_ISH_I2C1_SCL_OFFSET 334 +#define BXT_ISH_I2C2_SDA_OFFSET 335 +#define BXT_ISH_I2C2_SCL_OFFSET 336 +#define BXT_ISH_GPIO_0_OFFSET 337 +#define BXT_ISH_GPIO_1_OFFSET 338 +#define BXT_ISH_GPIO_2_OFFSET 339 +#define BXT_ISH_GPIO_3_OFFSET 340 +#define BXT_ISH_GPIO_4_OFFSET 341 +#define BXT_ISH_GPIO_5_OFFSET 342 +#define BXT_ISH_GPIO_6_OFFSET 343 +#define BXT_ISH_GPIO_7_OFFSET 344 +#define BXT_ISH_GPIO_8_OFFSET 345 +#define BXT_ISH_GPIO_9_OFFSET 346 +#define BXT_AVS_I2S1_MCLK_OFFSET 378 +#define BXT_AVS_I2S1_BCLK_OFFSET 379 +#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380 +#define BXT_AVS_I2S1_SDI_OFFSET 381 +#define BXT_AVS_I2S1_SDO_OFFSET 382 +#define BXT_AVS_M_CLK_A1_OFFSET 383 +#define BXT_AVS_M_CLK_B1_OFFSET 384 +#define BXT_AVS_M_DATA_1_OFFSET 385 +#define BXT_AVS_M_CLK_AB2_OFFSET 386 +#define BXT_AVS_M_DATA_2_OFFSET 387 +#define BXT_AVS_I2S2_MCLK_OFFSET 388 +#define BXT_AVS_I2S2_BCLK_OFFSET 389 +#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390 +#define BXT_AVS_I2S2_SDI_OFFSET 391 +#define BXT_AVS_I2S2_SDO_OFFSET 392 +#define BXT_AVS_I2S3_BCLK_OFFSET 393 +#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394 +#define BXT_AVS_I2S3_SDI_OFFSET 395 +#define BXT_AVS_I2S3_SDO_OFFSET 396 +#define BXT_AVS_I2S4_BCLK_OFFSET 397 +#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398 +#define BXT_AVS_I2S4_SDI_OFFSET 399 +#define BXT_AVS_I2S4_SDO_OFFSET 400 +#define BXT_FST_SPI_CS0_B_OFFSET 402 +#define BXT_FST_SPI_CS1_B_OFFSET 403 +#define BXT_FST_SPI_MOSI_IO0_OFFSET 404 +#define BXT_FST_SPI_MISO_IO1_OFFSET 405 +#define BXT_FST_SPI_IO2_OFFSET 406 +#define BXT_FST_SPI_IO3_OFFSET 407 +#define BXT_FST_SPI_CLK_OFFSET 408 +#define BXT_GP_SSP_0_CLK_OFFSET 410 +#define BXT_GP_SSP_0_FS0_OFFSET 411 +#define BXT_GP_SSP_0_FS1_OFFSET 412 +#define BXT_GP_SSP_0_FS2_OFFSET 413 +#define BXT_GP_SSP_0_RXD_OFFSET 414 +#define BXT_GP_SSP_0_TXD_OFFSET 415 +#define BXT_GP_SSP_1_CLK_OFFSET 416 +#define BXT_GP_SSP_1_FS0_OFFSET 417 +#define BXT_GP_SSP_1_FS1_OFFSET 418 +#define BXT_GP_SSP_1_FS2_OFFSET 419 +#define BXT_GP_SSP_1_FS3_OFFSET 420 +#define BXT_GP_SSP_1_RXD_OFFSET 421 +#define BXT_GP_SSP_1_TXD_OFFSET 422 +#define BXT_GP_SSP_2_CLK_OFFSET 423 +#define BXT_GP_SSP_2_FS0_OFFSET 424 +#define BXT_GP_SSP_2_FS1_OFFSET 425 +#define BXT_GP_SSP_2_FS2_OFFSET 426 +#define BXT_GP_SSP_2_RXD_OFFSET 427 +#define BXT_GP_SSP_2_TXD_OFFSET 428 +#define BXT_TRACE_0_CLK_VNN_OFFSET 429 +#define BXT_TRACE_0_DATA0_VNN_OFFSET 430 +#define BXT_TRACE_0_DATA1_VNN_OFFSET 431 +#define BXT_TRACE_0_DATA2_VNN_OFFSET 432 +#define BXT_TRACE_0_DATA3_VNN_OFFSET 433 +#define BXT_TRACE_0_DATA4_VNN_OFFSET 434 +#define BXT_TRACE_0_DATA5_VNN_OFFSET 435 +#define BXT_TRACE_0_DATA6_VNN_OFFSET 436 +#define BXT_TRACE_0_DATA7_VNN_OFFSET 437 +#define BXT_TRACE_1_CLK_VNN_OFFSET 438 +#define BXT_TRACE_1_DATA0_VNN_OFFSET 439 +#define BXT_TRACE_1_DATA1_VNN_OFFSET 440 +#define BXT_TRACE_1_DATA2_VNN_OFFSET 441 +#define BXT_TRACE_1_DATA3_VNN_OFFSET 442 +#define BXT_TRACE_1_DATA4_VNN_OFFSET 443 +#define BXT_TRACE_1_DATA5_VNN_OFFSET 444 +#define BXT_TRACE_1_DATA6_VNN_OFFSET 445 +#define BXT_TRACE_1_DATA7_VNN_OFFSET 446 +#define BXT_TRACE_2_CLK_VNN_OFFSET 447 +#define BXT_TRACE_2_DATA0_VNN_OFFSET 448 +#define BXT_TRACE_2_DATA1_VNN_OFFSET 449 +#define BXT_TRACE_2_DATA2_VNN_OFFSET 450 +#define BXT_TRACE_2_DATA3_VNN_OFFSET 451 +#define BXT_TRACE_2_DATA4_VNN_OFFSET 452 +#define BXT_TRACE_2_DATA5_VNN_OFFSET 453 +#define BXT_TRACE_2_DATA6_VNN_OFFSET 454 +#define BXT_TRACE_2_DATA7_VNN_OFFSET 455 +#define BXT_TRIGOUT_0_OFFSET 456 +#define BXT_TRIGOUT_1_OFFSET 457 +#define BXT_TRIGIN_0_OFFSET 458 +#define BXT_SEC_TCK_OFFSET 459 +#define BXT_SEC_TDI_OFFSET 460 +#define BXT_SEC_TMS_OFFSET 461 +#define BXT_SEC_TDO_OFFSET 462 +#define BXT_PWM0_OFFSET 463 +#define BXT_PWM1_OFFSET 464 +#define BXT_PWM2_OFFSET 465 +#define BXT_PWM3_OFFSET 466 +#define BXT_LPSS_UART0_RXD_OFFSET 467 +#define BXT_LPSS_UART0_TXD_OFFSET 468 +#define BXT_LPSS_UART0_RTS_B_OFFSET 469 +#define BXT_LPSS_UART0_CTS_B_OFFSET 470 +#define BXT_LPSS_UART1_RXD_OFFSET 471 +#define BXT_LPSS_UART1_TXD_OFFSET 472 +#define BXT_LPSS_UART1_RTS_B_OFFSET 473 +#define BXT_LPSS_UART1_CTS_B_OFFSET 474 +#define BXT_LPSS_UART2_RXD_OFFSET 475 +#define BXT_LPSS_UART2_TXD_OFFSET 476 +#define BXT_LPSS_UART2_RTS_B_OFFSET 477 +#define BXT_LPSS_UART2_CTS_B_OFFSET 478 +#define BXT_ISH_UART0_RXD_OFFSET 479 +#define BXT_ISH_UART0_TXD_OFFSET 480 +#define BXT_ISH_UART0_RTS_B_OFFSET 481 +#define BXT_ISH_UART0_CTS_B_OFFSET 482 +#define BXT_ISH_UART1_RXD_OFFSET 483 +#define BXT_ISH_UART1_TXD_OFFSET 484 +#define BXT_ISH_UART1_RTS_B_OFFSET 485 +#define BXT_ISH_UART1_CTS_B_OFFSET 486 +#define BXT_ISH_UART2_RXD_OFFSET 487 +#define BXT_ISH_UART2_TXD_OFFSET 488 +#define BXT_ISH_UART2_RTS_B_OFFSET 489 +#define BXT_ISH_UART2_CTS_B_OFFSET 490 +#define BXT_GP_CAMERASB00_OFFSET 491 +#define BXT_GP_CAMERASB01_OFFSET 492 +#define BXT_GP_CAMERASB02_OFFSET 493 +#define BXT_GP_CAMERASB03_OFFSET 494 +#define BXT_GP_CAMERASB04_OFFSET 495 +#define BXT_GP_CAMERASB05_OFFSET 496 +#define BXT_GP_CAMERASB06_OFFSET 497 +#define BXT_GP_CAMERASB07_OFFSET 498 +#define BXT_GP_CAMERASB08_OFFSET 499 +#define BXT_GP_CAMERASB09_OFFSET 500 +#define BXT_GP_CAMERASB10_OFFSET 501 +#define BXT_GP_CAMERASB11_OFFSET 502 + +struct bxt_gpio_map { + u8 gpio_index; + u16 gpio_number; + bool requested; +}; + +/* XXX: take out everything that is not related to DSI display */ +static struct bxt_gpio_map bxt_gpio_table[] = { + { BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET }, + { BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET }, + { BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET }, + { BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET }, + { BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET }, + { BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET }, + { BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET }, + { BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET }, + { BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET }, + { BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET }, + { BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET }, + { BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET }, + { BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET }, + { BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET }, + { BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET }, + { BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET }, + { BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET }, + { BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET }, + { BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET }, + { BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET }, + { BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET }, + { BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET }, + { BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET }, + { BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET }, + { BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET }, + { BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET }, + { BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET }, + { BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET }, + { BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET }, + { BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET }, + { BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET }, + { BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET }, + { BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET }, + { BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET }, + { BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET }, + { BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET }, + { BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET }, + { BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET }, + { BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET }, + { BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET }, + { BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET }, + { BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET }, + { BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET }, + { BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET }, + { BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET }, + { BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET }, + { BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET }, + { BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET }, + { BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET }, + { BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET }, + { BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET }, + { BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET }, + { BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET }, + { BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET }, + { BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET }, + { BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET }, + { BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET }, + { BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET }, + { BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET }, + { BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET }, + { BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET }, + { BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET }, + { BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET }, + { BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET }, + { BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET }, + { BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET }, + { BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET }, + { BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET }, + { BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET }, + { BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET }, + { BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET }, + { BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET }, + { BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET }, + { BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET }, + { BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET }, + { BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET }, + { BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET }, + { BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET }, + { BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET }, + { BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET }, + { BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET }, + { BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET }, + { BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET }, + { BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET }, + { BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET }, + { BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET }, + { BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET }, + { BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET }, + { BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET }, + { BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET }, + { BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET }, + { BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET }, + { BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET }, + { BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET }, + { BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET }, + { BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET }, + { BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET }, + { BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET }, + { BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET }, + { BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET }, + { BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET }, + { BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET }, + { BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET }, + { BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET }, + { BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET }, + { BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET }, + { BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET }, + { BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET }, + { BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET }, + { BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET }, + { BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET }, + { BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET }, + { BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET }, + { BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET }, + { BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET }, + { BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET }, + { BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET }, + { BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET }, + { BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET }, + { BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET }, + { BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET }, + { BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET }, + { BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET }, + { BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET }, + { BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET }, + { BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET }, + { BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET }, + { BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET }, + { BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET }, + { BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET }, + { BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET }, + { BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET }, + { BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET }, + { BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET }, + { BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET }, + { BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET }, + { BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET }, + { BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET }, + { BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET }, + { BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET }, + { BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET }, + { BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET }, + { BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET }, + { BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET }, + { BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET }, + { BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET }, + { BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET }, + { BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET }, + { BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET }, + { BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET }, + { BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET }, + { BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET }, + { BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET }, + { BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET }, + { BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET }, + { BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET }, + { BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET }, + { BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET }, + { BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET }, + { BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET }, + { BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET }, + { BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET }, + { BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET }, + { BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET }, + { BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET }, + { BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET }, + { BXT_PWM0_PIN, BXT_PWM0_OFFSET }, + { BXT_PWM1_PIN, BXT_PWM1_OFFSET }, + { BXT_PWM2_PIN, BXT_PWM2_OFFSET }, + { BXT_PWM3_PIN, BXT_PWM3_OFFSET }, + { BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET }, + { BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET }, + { BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET }, + { BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET }, + { BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET }, + { BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET }, + { BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET }, + { BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET }, + { BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET }, + { BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET }, + { BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET }, + { BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET }, + { BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET }, + { BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET }, + { BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET }, + { BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET }, + { BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET }, + { BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET }, + { BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET }, + { BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET }, + { BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET }, + { BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET }, + { BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET }, + { BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET }, + { BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET }, + { BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET }, + { BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET }, + { BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET }, + { BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET }, + { BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET }, + { BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET }, + { BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET }, + { BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET }, + { BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET }, + { BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET }, + { BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET }, +}; + static inline enum port intel_dsi_seq_port_to_port(u8 port) { return port ? PORT_C : PORT_A; @@ -305,6 +936,40 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, mutex_unlock(&dev_priv->sb_lock); } +static void bxt_exec_gpio(struct drm_i915_private *dev_priv, + u8 gpio_source, u8 gpio_index, u8 action) +{ + struct bxt_gpio_map *map = NULL; + unsigned int gpio; + int i; + + for (i = 0; i < ARRAY_SIZE(bxt_gpio_table); i++) { + if (gpio_index == bxt_gpio_table[i].gpio_index) { + map = &bxt_gpio_table[i]; + break; + } + } + + if (!map) { + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); + return; + } + + gpio = map->gpio_number; + + if (!map->requested) { + int ret = devm_gpio_request_one(dev_priv->dev->dev, gpio, + GPIOF_DIR_OUT, "MIPI DSI"); + if (ret) { + DRM_ERROR("unable to request GPIO %u (%d)\n", gpio, ret); + return; + } + map->requested = true; + } + + gpio_set_value(gpio, action); +} + static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) { struct drm_device *dev = intel_dsi->base.base.dev; @@ -330,7 +995,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) else if (IS_CHERRYVIEW(dev_priv)) chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); else - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); + bxt_exec_gpio(dev_priv, gpio_source, gpio_index, action); return data; } -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support 2016-03-18 11:11 ` [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support Jani Nikula @ 2016-03-23 10:55 ` Mika Kahola 2016-03-23 11:19 ` Jani Nikula 2016-04-04 17:46 ` Ville Syrjälä 1 sibling, 1 reply; 23+ messages in thread From: Mika Kahola @ 2016-03-23 10:55 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, 2016-03-18 at 13:11 +0200, Jani Nikula wrote: > Use a table similar to vlv to check for accepted gpio indexes. For now, > add all, but this list should be trimmed down. Use managed gpio request, > which will be automatically released when the driver is detached. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 667 ++++++++++++++++++++++++++++- > 1 file changed, 666 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index f8d3f608e9c8..6b8dc15f3656 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -29,6 +29,7 @@ > #include <drm/drm_edid.h> > #include <drm/i915_drm.h> > #include <drm/drm_panel.h> > +#include <linux/gpio.h> > #include <linux/slab.h> > #include <video/mipi_display.h> > #include <asm/intel-mid.h> > @@ -114,6 +115,636 @@ static struct vlv_gpio_map vlv_gpio_table[] = { > #define CHV_GPIO_CFG_HIZ 0x00008100 > #define CHV_GPIO_CFG_TX_STATE_SHIFT 1 > > +#define BXT_HV_DDI0_DDC_SDA_PIN 187 > +#define BXT_HV_DDI0_DDC_SCL_PIN 188 > +#define BXT_HV_DDI1_DDC_SDA_PIN 189 > +#define BXT_HV_DDI1_DDC_SCL_PIN 190 > +#define BXT_DBI_SDA_PIN 191 > +#define BXT_DBI_SCL_PIN 192 > +#define BXT_PANEL0_VDDEN_PIN 193 > +#define BXT_PANEL0_BKLTEN_PIN 194 > +#define BXT_PANEL0_BKLTCTL_PIN 195 > +#define BXT_PANEL1_VDDEN_PIN 196 > +#define BXT_PANEL1_BKLTEN_PIN 197 > +#define BXT_PANEL1_BKLTCTL_PIN 198 > +#define BXT_DBI_CSX_PIN 199 > +#define BXT_DBI_RESX_PIN 200 > +#define BXT_GP_INTD_DSI_TE1_PIN 201 > +#define BXT_GP_INTD_DSI_TE2_PIN 202 > +#define BXT_USB_OC0_B_PIN 203 > +#define BXT_USB_OC1_B_PIN 204 > +#define BXT_MEX_WAKE0_B_PIN 205 > +#define BXT_MEX_WAKE1_B_PIN 206 > +#define BXT_EMMC0_CLK_PIN 156 > +#define BXT_EMMC0_D0_PIN 157 > +#define BXT_EMMC0_D1_PIN 158 > +#define BXT_EMMC0_D2_PIN 159 > +#define BXT_EMMC0_D3_PIN 160 > +#define BXT_EMMC0_D4_PIN 161 > +#define BXT_EMMC0_D5_PIN 162 > +#define BXT_EMMC0_D6_PIN 163 > +#define BXT_EMMC0_D7_PIN 164 > +#define BXT_EMMC0_CMD_PIN 165 > +#define BXT_SDIO_CLK_PIN 166 > +#define BXT_SDIO_D0_PIN 167 > +#define BXT_SDIO_D1_PIN 168 > +#define BXT_SDIO_D2_PIN 169 > +#define BXT_SDIO_D3_PIN 170 > +#define BXT_SDIO_CMD_PIN 171 > +#define BXT_SDCARD_CLK_PIN 172 > +#define BXT_SDCARD_D0_PIN 173 > +#define BXT_SDCARD_D1_PIN 174 > +#define BXT_SDCARD_D2_PIN 175 > +#define BXT_SDCARD_D3_PIN 176 > +#define BXT_SDCARD_CD_B_PIN 177 > +#define BXT_SDCARD_CMD_PIN 178 > +#define BXT_SDCARD_LVL_CLK_FB_PIN 179 > +#define BXT_SDCARD_LVL_CMD_DIR_PIN 180 > +#define BXT_SDCARD_LVL_DAT_DIR_PIN 181 > +#define BXT_EMMC0_STROBE_PIN 182 > +#define BXT_SDIO_PWR_DOWN_B_PIN 183 > +#define BXT_SDCARD_PWR_DOWN_B_PIN 184 > +#define BXT_SDCARD_LVL_SEL_PIN 185 > +#define BXT_SDCARD_LVL_WP_PIN 186 > +#define BXT_LPSS_I2C0_SDA_PIN 124 > +#define BXT_LPSS_I2C0_SCL_PIN 125 > +#define BXT_LPSS_I2C1_SDA_PIN 126 > +#define BXT_LPSS_I2C1_SCL_PIN 127 > +#define BXT_LPSS_I2C2_SDA_PIN 128 > +#define BXT_LPSS_I2C2_SCL_PIN 129 > +#define BXT_LPSS_I2C3_SDA_PIN 130 > +#define BXT_LPSS_I2C3_SCL_PIN 131 > +#define BXT_LPSS_I2C4_SDA_PIN 132 > +#define BXT_LPSS_I2C4_SCL_PIN 133 > +#define BXT_LPSS_I2C5_SDA_PIN 134 > +#define BXT_LPSS_I2C5_SCL_PIN 135 > +#define BXT_LPSS_I2C6_SDA_PIN 136 > +#define BXT_LPSS_I2C6_SCL_PIN 137 > +#define BXT_LPSS_I2C7_SDA_PIN 138 > +#define BXT_LPSS_I2C7_SCL_PIN 139 > +#define BXT_ISH_I2C0_SDA_PIN 140 > +#define BXT_ISH_I2C0_SCL_PIN 141 > +#define BXT_ISH_I2C1_SDA_PIN 142 > +#define BXT_ISH_I2C1_SCL_PIN 143 > +#define BXT_ISH_I2C2_SDA_PIN 144 > +#define BXT_ISH_I2C2_SCL_PIN 145 > +#define BXT_ISH_GPIO_0_PIN 146 > +#define BXT_ISH_GPIO_1_PIN 147 > +#define BXT_ISH_GPIO_2_PIN 148 > +#define BXT_ISH_GPIO_3_PIN 149 > +#define BXT_ISH_GPIO_4_PIN 150 > +#define BXT_ISH_GPIO_5_PIN 151 > +#define BXT_ISH_GPIO_6_PIN 152 > +#define BXT_ISH_GPIO_7_PIN 153 > +#define BXT_ISH_GPIO_8_PIN 154 > +#define BXT_ISH_GPIO_9_PIN 155 > +#define BXT_AVS_I2S1_MCLK_PIN 74 > +#define BXT_AVS_I2S1_BCLK_PIN 75 > +#define BXT_AVS_I2S1_WS_SYNC_PIN 76 > +#define BXT_AVS_I2S1_SDI_PIN 77 > +#define BXT_AVS_I2S1_SDO_PIN 78 > +#define BXT_AVS_M_CLK_A1_PIN 79 > +#define BXT_AVS_M_CLK_B1_PIN 80 > +#define BXT_AVS_M_DATA_1_PIN 81 > +#define BXT_AVS_M_CLK_AB2_PIN 82 > +#define BXT_AVS_M_DATA_2_PIN 83 > +#define BXT_AVS_I2S2_MCLK_PIN 84 > +#define BXT_AVS_I2S2_BCLK_PIN 85 > +#define BXT_AVS_I2S2_WS_SYNC_PIN 86 > +#define BXT_AVS_I2S2_SDI_PIN 87 > +#define BXT_AVS_I2S2_SDO_PIN 88 > +#define BXT_AVS_I2S3_BCLK_PIN 89 > +#define BXT_AVS_I2S3_WS_SYNC_PIN 90 > +#define BXT_AVS_I2S3_SDI_PIN 91 > +#define BXT_AVS_I2S3_SDO_PIN 92 > +#define BXT_AVS_I2S4_BCLK_PIN 93 > +#define BXT_AVS_I2S4_WS_SYNC_PIN 94 > +#define BXT_AVS_I2S4_SDI_PIN 95 > +#define BXT_AVS_I2S4_SDO_PIN 96 > +#define BXT_FST_SPI_CS0_B_PIN 97 > +#define BXT_FST_SPI_CS1_B_PIN 98 > +#define BXT_FST_SPI_MOSI_IO0_PIN 99 > +#define BXT_FST_SPI_MISO_IO1_PIN 100 > +#define BXT_FST_SPI_IO2_PIN 101 > +#define BXT_FST_SPI_IO3_PIN 102 > +#define BXT_FST_SPI_CLK_PIN 103 > +#define BXT_GP_SSP_0_CLK_PIN 104 > +#define BXT_GP_SSP_0_FS0_PIN 105 > +#define BXT_GP_SSP_0_FS1_PIN 106 > +#define BXT_GP_SSP_0_FS2_PIN 107 > +#define BXT_GP_SSP_0_RXD_PIN 109 > +#define BXT_GP_SSP_0_TXD_PIN 110 > +#define BXT_GP_SSP_1_CLK_PIN 111 > +#define BXT_GP_SSP_1_FS0_PIN 112 > +#define BXT_GP_SSP_1_FS1_PIN 113 > +#define BXT_GP_SSP_1_FS2_PIN 114 > +#define BXT_GP_SSP_1_FS3_PIN 115 > +#define BXT_GP_SSP_1_RXD_PIN 116 > +#define BXT_GP_SSP_1_TXD_PIN 117 > +#define BXT_GP_SSP_2_CLK_PIN 118 > +#define BXT_GP_SSP_2_FS0_PIN 119 > +#define BXT_GP_SSP_2_FS1_PIN 120 > +#define BXT_GP_SSP_2_FS2_PIN 121 > +#define BXT_GP_SSP_2_RXD_PIN 122 > +#define BXT_GP_SSP_2_TXD_PIN 123 > +#define BXT_TRACE_0_CLK_VNN_PIN 0 > +#define BXT_TRACE_0_DATA0_VNN_PIN 1 > +#define BXT_TRACE_0_DATA1_VNN_PIN 2 > +#define BXT_TRACE_0_DATA2_VNN_PIN 3 > +#define BXT_TRACE_0_DATA3_VNN_PIN 4 > +#define BXT_TRACE_0_DATA4_VNN_PIN 5 > +#define BXT_TRACE_0_DATA5_VNN_PIN 6 > +#define BXT_TRACE_0_DATA6_VNN_PIN 7 > +#define BXT_TRACE_0_DATA7_VNN_PIN 8 > +#define BXT_TRACE_1_CLK_VNN_PIN 9 > +#define BXT_TRACE_1_DATA0_VNN_PIN 10 > +#define BXT_TRACE_1_DATA1_VNN_PIN 11 > +#define BXT_TRACE_1_DATA2_VNN_PIN 12 > +#define BXT_TRACE_1_DATA3_VNN_PIN 13 > +#define BXT_TRACE_1_DATA4_VNN_PIN 14 > +#define BXT_TRACE_1_DATA5_VNN_PIN 15 > +#define BXT_TRACE_1_DATA6_VNN_PIN 16 > +#define BXT_TRACE_1_DATA7_VNN_PIN 17 > +#define BXT_TRACE_2_CLK_VNN_PIN 18 > +#define BXT_TRACE_2_DATA0_VNN_PIN 19 > +#define BXT_TRACE_2_DATA1_VNN_PIN 20 > +#define BXT_TRACE_2_DATA2_VNN_PIN 21 > +#define BXT_TRACE_2_DATA3_VNN_PIN 22 > +#define BXT_TRACE_2_DATA4_VNN_PIN 23 > +#define BXT_TRACE_2_DATA5_VNN_PIN 24 > +#define BXT_TRACE_2_DATA6_VNN_PIN 25 > +#define BXT_TRACE_2_DATA7_VNN_PIN 26 > +#define BXT_TRIGOUT_0_PIN 27 > +#define BXT_TRIGOUT_1_PIN 28 > +#define BXT_TRIGIN_0_PIN 29 > +#define BXT_SEC_TCK_PIN 30 > +#define BXT_SEC_TDI_PIN 31 > +#define BXT_SEC_TMS_PIN 32 > +#define BXT_SEC_TDO_PIN 33 > +#define BXT_PWM0_PIN 34 > +#define BXT_PWM1_PIN 35 > +#define BXT_PWM2_PIN 36 > +#define BXT_PWM3_PIN 37 > +#define BXT_LPSS_UART0_RXD_PIN 38 > +#define BXT_LPSS_UART0_TXD_PIN 39 > +#define BXT_LPSS_UART0_RTS_B_PIN 40 > +#define BXT_LPSS_UART0_CTS_B_PIN 41 > +#define BXT_LPSS_UART1_RXD_PIN 42 > +#define BXT_LPSS_UART1_TXD_PIN 43 > +#define BXT_LPSS_UART1_RTS_B_PIN 44 > +#define BXT_LPSS_UART1_CTS_B_PIN 45 > +#define BXT_LPSS_UART2_RXD_PIN 46 > +#define BXT_LPSS_UART2_TXD_PIN 47 > +#define BXT_LPSS_UART2_RTS_B_PIN 48 > +#define BXT_LPSS_UART2_CTS_B_PIN 49 > +#define BXT_ISH_UART0_RXD_PIN 50 > +#define BXT_ISH_UART0_TXD_PIN 51 > +#define BXT_ISH_UART0_RTS_B_PIN 52 > +#define BXT_ISH_UART0_CTS_B_PIN 53 > +#define BXT_ISH_UART1_RXD_PIN 54 > +#define BXT_ISH_UART1_TXD_PIN 55 > +#define BXT_ISH_UART1_RTS_B_PIN 56 > +#define BXT_ISH_UART1_CTS_B_PIN 57 > +#define BXT_ISH_UART2_RXD_PIN 58 > +#define BXT_ISH_UART2_TXD_PIN 59 > +#define BXT_ISH_UART2_RTS_B_PIN 60 > +#define BXT_ISH_UART2_CTS_B_PIN 61 > +#define BXT_GP_CAMERASB00_PIN 62 > +#define BXT_GP_CAMERASB01_PIN 63 > +#define BXT_GP_CAMERASB02_PIN 64 > +#define BXT_GP_CAMERASB03_PIN 65 > +#define BXT_GP_CAMERASB04_PIN 66 > +#define BXT_GP_CAMERASB05_PIN 67 > +#define BXT_GP_CAMERASB06_PIN 68 > +#define BXT_GP_CAMERASB07_PIN 69 > +#define BXT_GP_CAMERASB08_PIN 70 > +#define BXT_GP_CAMERASB09_PIN 71 > +#define BXT_GP_CAMERASB10_PIN 72 > +#define BXT_GP_CAMERASB11_PIN 73 > + > +#define BXT_HV_DDI0_DDC_SDA_OFFSET 264 > +#define BXT_HV_DDI0_DDC_SCL_OFFSET 265 > +#define BXT_HV_DDI1_DDC_SDA_OFFSET 266 > +#define BXT_HV_DDI1_DDC_SCL_OFFSET 267 > +#define BXT_DBI_SDA_OFFSET 268 > +#define BXT_DBI_SCL_OFFSET 269 > +#define BXT_PANEL0_VDDEN_OFFSET 270 > +#define BXT_PANEL0_BKLTEN_OFFSET 271 > +#define BXT_PANEL0_BKLTCTL_OFFSET 272 > +#define BXT_PANEL1_VDDEN_OFFSET 273 > +#define BXT_PANEL1_BKLTEN_OFFSET 274 > +#define BXT_PANEL1_BKLTCTL_OFFSET 275 > +#define BXT_DBI_CSX_OFFSET 276 > +#define BXT_DBI_RESX_OFFSET 277 > +#define BXT_GP_INTD_DSI_TE1_OFFSET 278 > +#define BXT_GP_INTD_DSI_TE2_OFFSET 279 > +#define BXT_USB_OC0_B_OFFSET 280 > +#define BXT_USB_OC1_B_OFFSET 281 > +#define BXT_MEX_WAKE0_B_OFFSET 282 > +#define BXT_MEX_WAKE1_B_OFFSET 283 > +#define BXT_EMMC0_CLK_OFFSET 284 > +#define BXT_EMMC0_D0_OFFSET 285 > +#define BXT_EMMC0_D1_OFFSET 286 > +#define BXT_EMMC0_D2_OFFSET 287 > +#define BXT_EMMC0_D3_OFFSET 288 > +#define BXT_EMMC0_D4_OFFSET 289 > +#define BXT_EMMC0_D5_OFFSET 290 > +#define BXT_EMMC0_D6_OFFSET 291 > +#define BXT_EMMC0_D7_OFFSET 292 > +#define BXT_EMMC0_CMD_OFFSET 293 > +#define BXT_SDIO_CLK_OFFSET 294 > +#define BXT_SDIO_D0_OFFSET 295 > +#define BXT_SDIO_D1_OFFSET 296 > +#define BXT_SDIO_D2_OFFSET 297 > +#define BXT_SDIO_D3_OFFSET 298 > +#define BXT_SDIO_CMD_OFFSET 299 > +#define BXT_SDCARD_CLK_OFFSET 300 > +#define BXT_SDCARD_D0_OFFSET 301 > +#define BXT_SDCARD_D1_OFFSET 302 > +#define BXT_SDCARD_D2_OFFSET 303 > +#define BXT_SDCARD_D3_OFFSET 304 > +#define BXT_SDCARD_CD_B_OFFSET 305 > +#define BXT_SDCARD_CMD_OFFSET 306 > +#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307 > +#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308 > +#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309 > +#define BXT_EMMC0_STROBE_OFFSET 310 > +#define BXT_SDIO_PWR_DOWN_B_OFFSET 311 > +#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312 > +#define BXT_SDCARD_LVL_SEL_OFFSET 313 > +#define BXT_SDCARD_LVL_WP_OFFSET 314 > +#define BXT_LPSS_I2C0_SDA_OFFSET 315 > +#define BXT_LPSS_I2C0_SCL_OFFSET 316 > +#define BXT_LPSS_I2C1_SDA_OFFSET 317 > +#define BXT_LPSS_I2C1_SCL_OFFSET 318 > +#define BXT_LPSS_I2C2_SDA_OFFSET 319 > +#define BXT_LPSS_I2C2_SCL_OFFSET 320 > +#define BXT_LPSS_I2C3_SDA_OFFSET 321 > +#define BXT_LPSS_I2C3_SCL_OFFSET 322 > +#define BXT_LPSS_I2C4_SDA_OFFSET 323 > +#define BXT_LPSS_I2C4_SCL_OFFSET 324 > +#define BXT_LPSS_I2C5_SDA_OFFSET 325 > +#define BXT_LPSS_I2C5_SCL_OFFSET 326 > +#define BXT_LPSS_I2C6_SDA_OFFSET 327 > +#define BXT_LPSS_I2C6_SCL_OFFSET 328 > +#define BXT_LPSS_I2C7_SDA_OFFSET 329 > +#define BXT_LPSS_I2C7_SCL_OFFSET 330 > +#define BXT_ISH_I2C0_SDA_OFFSET 331 > +#define BXT_ISH_I2C0_SCL_OFFSET 332 > +#define BXT_ISH_I2C1_SDA_OFFSET 333 > +#define BXT_ISH_I2C1_SCL_OFFSET 334 > +#define BXT_ISH_I2C2_SDA_OFFSET 335 > +#define BXT_ISH_I2C2_SCL_OFFSET 336 > +#define BXT_ISH_GPIO_0_OFFSET 337 > +#define BXT_ISH_GPIO_1_OFFSET 338 > +#define BXT_ISH_GPIO_2_OFFSET 339 > +#define BXT_ISH_GPIO_3_OFFSET 340 > +#define BXT_ISH_GPIO_4_OFFSET 341 > +#define BXT_ISH_GPIO_5_OFFSET 342 > +#define BXT_ISH_GPIO_6_OFFSET 343 > +#define BXT_ISH_GPIO_7_OFFSET 344 > +#define BXT_ISH_GPIO_8_OFFSET 345 > +#define BXT_ISH_GPIO_9_OFFSET 346 > +#define BXT_AVS_I2S1_MCLK_OFFSET 378 > +#define BXT_AVS_I2S1_BCLK_OFFSET 379 > +#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380 > +#define BXT_AVS_I2S1_SDI_OFFSET 381 > +#define BXT_AVS_I2S1_SDO_OFFSET 382 > +#define BXT_AVS_M_CLK_A1_OFFSET 383 > +#define BXT_AVS_M_CLK_B1_OFFSET 384 > +#define BXT_AVS_M_DATA_1_OFFSET 385 > +#define BXT_AVS_M_CLK_AB2_OFFSET 386 > +#define BXT_AVS_M_DATA_2_OFFSET 387 > +#define BXT_AVS_I2S2_MCLK_OFFSET 388 > +#define BXT_AVS_I2S2_BCLK_OFFSET 389 > +#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390 > +#define BXT_AVS_I2S2_SDI_OFFSET 391 > +#define BXT_AVS_I2S2_SDO_OFFSET 392 > +#define BXT_AVS_I2S3_BCLK_OFFSET 393 > +#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394 > +#define BXT_AVS_I2S3_SDI_OFFSET 395 > +#define BXT_AVS_I2S3_SDO_OFFSET 396 > +#define BXT_AVS_I2S4_BCLK_OFFSET 397 > +#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398 > +#define BXT_AVS_I2S4_SDI_OFFSET 399 > +#define BXT_AVS_I2S4_SDO_OFFSET 400 > +#define BXT_FST_SPI_CS0_B_OFFSET 402 > +#define BXT_FST_SPI_CS1_B_OFFSET 403 > +#define BXT_FST_SPI_MOSI_IO0_OFFSET 404 > +#define BXT_FST_SPI_MISO_IO1_OFFSET 405 > +#define BXT_FST_SPI_IO2_OFFSET 406 > +#define BXT_FST_SPI_IO3_OFFSET 407 > +#define BXT_FST_SPI_CLK_OFFSET 408 > +#define BXT_GP_SSP_0_CLK_OFFSET 410 > +#define BXT_GP_SSP_0_FS0_OFFSET 411 > +#define BXT_GP_SSP_0_FS1_OFFSET 412 > +#define BXT_GP_SSP_0_FS2_OFFSET 413 > +#define BXT_GP_SSP_0_RXD_OFFSET 414 > +#define BXT_GP_SSP_0_TXD_OFFSET 415 > +#define BXT_GP_SSP_1_CLK_OFFSET 416 > +#define BXT_GP_SSP_1_FS0_OFFSET 417 > +#define BXT_GP_SSP_1_FS1_OFFSET 418 > +#define BXT_GP_SSP_1_FS2_OFFSET 419 > +#define BXT_GP_SSP_1_FS3_OFFSET 420 > +#define BXT_GP_SSP_1_RXD_OFFSET 421 > +#define BXT_GP_SSP_1_TXD_OFFSET 422 > +#define BXT_GP_SSP_2_CLK_OFFSET 423 > +#define BXT_GP_SSP_2_FS0_OFFSET 424 > +#define BXT_GP_SSP_2_FS1_OFFSET 425 > +#define BXT_GP_SSP_2_FS2_OFFSET 426 > +#define BXT_GP_SSP_2_RXD_OFFSET 427 > +#define BXT_GP_SSP_2_TXD_OFFSET 428 > +#define BXT_TRACE_0_CLK_VNN_OFFSET 429 > +#define BXT_TRACE_0_DATA0_VNN_OFFSET 430 > +#define BXT_TRACE_0_DATA1_VNN_OFFSET 431 > +#define BXT_TRACE_0_DATA2_VNN_OFFSET 432 > +#define BXT_TRACE_0_DATA3_VNN_OFFSET 433 > +#define BXT_TRACE_0_DATA4_VNN_OFFSET 434 > +#define BXT_TRACE_0_DATA5_VNN_OFFSET 435 > +#define BXT_TRACE_0_DATA6_VNN_OFFSET 436 > +#define BXT_TRACE_0_DATA7_VNN_OFFSET 437 > +#define BXT_TRACE_1_CLK_VNN_OFFSET 438 > +#define BXT_TRACE_1_DATA0_VNN_OFFSET 439 > +#define BXT_TRACE_1_DATA1_VNN_OFFSET 440 > +#define BXT_TRACE_1_DATA2_VNN_OFFSET 441 > +#define BXT_TRACE_1_DATA3_VNN_OFFSET 442 > +#define BXT_TRACE_1_DATA4_VNN_OFFSET 443 > +#define BXT_TRACE_1_DATA5_VNN_OFFSET 444 > +#define BXT_TRACE_1_DATA6_VNN_OFFSET 445 > +#define BXT_TRACE_1_DATA7_VNN_OFFSET 446 > +#define BXT_TRACE_2_CLK_VNN_OFFSET 447 > +#define BXT_TRACE_2_DATA0_VNN_OFFSET 448 > +#define BXT_TRACE_2_DATA1_VNN_OFFSET 449 > +#define BXT_TRACE_2_DATA2_VNN_OFFSET 450 > +#define BXT_TRACE_2_DATA3_VNN_OFFSET 451 > +#define BXT_TRACE_2_DATA4_VNN_OFFSET 452 > +#define BXT_TRACE_2_DATA5_VNN_OFFSET 453 > +#define BXT_TRACE_2_DATA6_VNN_OFFSET 454 > +#define BXT_TRACE_2_DATA7_VNN_OFFSET 455 > +#define BXT_TRIGOUT_0_OFFSET 456 > +#define BXT_TRIGOUT_1_OFFSET 457 > +#define BXT_TRIGIN_0_OFFSET 458 > +#define BXT_SEC_TCK_OFFSET 459 > +#define BXT_SEC_TDI_OFFSET 460 > +#define BXT_SEC_TMS_OFFSET 461 > +#define BXT_SEC_TDO_OFFSET 462 > +#define BXT_PWM0_OFFSET 463 > +#define BXT_PWM1_OFFSET 464 > +#define BXT_PWM2_OFFSET 465 > +#define BXT_PWM3_OFFSET 466 > +#define BXT_LPSS_UART0_RXD_OFFSET 467 > +#define BXT_LPSS_UART0_TXD_OFFSET 468 > +#define BXT_LPSS_UART0_RTS_B_OFFSET 469 > +#define BXT_LPSS_UART0_CTS_B_OFFSET 470 > +#define BXT_LPSS_UART1_RXD_OFFSET 471 > +#define BXT_LPSS_UART1_TXD_OFFSET 472 > +#define BXT_LPSS_UART1_RTS_B_OFFSET 473 > +#define BXT_LPSS_UART1_CTS_B_OFFSET 474 > +#define BXT_LPSS_UART2_RXD_OFFSET 475 > +#define BXT_LPSS_UART2_TXD_OFFSET 476 > +#define BXT_LPSS_UART2_RTS_B_OFFSET 477 > +#define BXT_LPSS_UART2_CTS_B_OFFSET 478 > +#define BXT_ISH_UART0_RXD_OFFSET 479 > +#define BXT_ISH_UART0_TXD_OFFSET 480 > +#define BXT_ISH_UART0_RTS_B_OFFSET 481 > +#define BXT_ISH_UART0_CTS_B_OFFSET 482 > +#define BXT_ISH_UART1_RXD_OFFSET 483 > +#define BXT_ISH_UART1_TXD_OFFSET 484 > +#define BXT_ISH_UART1_RTS_B_OFFSET 485 > +#define BXT_ISH_UART1_CTS_B_OFFSET 486 > +#define BXT_ISH_UART2_RXD_OFFSET 487 > +#define BXT_ISH_UART2_TXD_OFFSET 488 > +#define BXT_ISH_UART2_RTS_B_OFFSET 489 > +#define BXT_ISH_UART2_CTS_B_OFFSET 490 > +#define BXT_GP_CAMERASB00_OFFSET 491 > +#define BXT_GP_CAMERASB01_OFFSET 492 > +#define BXT_GP_CAMERASB02_OFFSET 493 > +#define BXT_GP_CAMERASB03_OFFSET 494 > +#define BXT_GP_CAMERASB04_OFFSET 495 > +#define BXT_GP_CAMERASB05_OFFSET 496 > +#define BXT_GP_CAMERASB06_OFFSET 497 > +#define BXT_GP_CAMERASB07_OFFSET 498 > +#define BXT_GP_CAMERASB08_OFFSET 499 > +#define BXT_GP_CAMERASB09_OFFSET 500 > +#define BXT_GP_CAMERASB10_OFFSET 501 > +#define BXT_GP_CAMERASB11_OFFSET 502 > + > +struct bxt_gpio_map { > + u8 gpio_index; > + u16 gpio_number; > + bool requested; > +}; > + > +/* XXX: take out everything that is not related to DSI display */ > +static struct bxt_gpio_map bxt_gpio_table[] = { > + { BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET }, > + { BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET }, > + { BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET }, > + { BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET }, > + { BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET }, > + { BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET }, > + { BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET }, > + { BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET }, > + { BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET }, > + { BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET }, > + { BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET }, > + { BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET }, > + { BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET }, > + { BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET }, > + { BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET }, > + { BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET }, > + { BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET }, > + { BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET }, > + { BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET }, > + { BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET }, > + { BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET }, > + { BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET }, > + { BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET }, > + { BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET }, > + { BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET }, > + { BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET }, > + { BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET }, > + { BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET }, > + { BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET }, > + { BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET }, > + { BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET }, > + { BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET }, > + { BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET }, > + { BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET }, > + { BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET }, > + { BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET }, > + { BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET }, > + { BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET }, > + { BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET }, > + { BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET }, > + { BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET }, > + { BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET }, > + { BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET }, > + { BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET }, > + { BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET }, > + { BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET }, > + { BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET }, > + { BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET }, > + { BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET }, > + { BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET }, > + { BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET }, > + { BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET }, > + { BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET }, > + { BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET }, > + { BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET }, > + { BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET }, > + { BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET }, > + { BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET }, > + { BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET }, > + { BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET }, > + { BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET }, > + { BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET }, > + { BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET }, > + { BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET }, > + { BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET }, > + { BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET }, > + { BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET }, > + { BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET }, > + { BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET }, > + { BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET }, > + { BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET }, > + { BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET }, > + { BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET }, > + { BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET }, > + { BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET }, > + { BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET }, > + { BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET }, > + { BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET }, > + { BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET }, > + { BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET }, > + { BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET }, > + { BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET }, > + { BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET }, > + { BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET }, > + { BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET }, > + { BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET }, > + { BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET }, > + { BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET }, > + { BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET }, > + { BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET }, > + { BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET }, > + { BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET }, > + { BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET }, > + { BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET }, > + { BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET }, > + { BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET }, > + { BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET }, > + { BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET }, > + { BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET }, > + { BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET }, > + { BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET }, > + { BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET }, > + { BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET }, > + { BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET }, > + { BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET }, > + { BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET }, > + { BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET }, > + { BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET }, > + { BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET }, > + { BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET }, > + { BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET }, > + { BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET }, > + { BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET }, > + { BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET }, > + { BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET }, > + { BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET }, > + { BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET }, > + { BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET }, > + { BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET }, > + { BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET }, > + { BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET }, > + { BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET }, > + { BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET }, > + { BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET }, > + { BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET }, > + { BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET }, > + { BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET }, > + { BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET }, > + { BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET }, > + { BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET }, > + { BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET }, > + { BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET }, > + { BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET }, > + { BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET }, > + { BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET }, > + { BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET }, > + { BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET }, > + { BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET }, > + { BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET }, > + { BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET }, > + { BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET }, > + { BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET }, > + { BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET }, > + { BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET }, > + { BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET }, > + { BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET }, > + { BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET }, > + { BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET }, > + { BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET }, > + { BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET }, > + { BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET }, > + { BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET }, > + { BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET }, > + { BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET }, > + { BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET }, > + { BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET }, > + { BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET }, > + { BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET }, > + { BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET }, > + { BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET }, > + { BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET }, > + { BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET }, > + { BXT_PWM0_PIN, BXT_PWM0_OFFSET }, > + { BXT_PWM1_PIN, BXT_PWM1_OFFSET }, > + { BXT_PWM2_PIN, BXT_PWM2_OFFSET }, > + { BXT_PWM3_PIN, BXT_PWM3_OFFSET }, > + { BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET }, > + { BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET }, > + { BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET }, > + { BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET }, > + { BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET }, > + { BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET }, > + { BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET }, > + { BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET }, > + { BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET }, > + { BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET }, > + { BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET }, > + { BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET }, > + { BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET }, > + { BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET }, > + { BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET }, > + { BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET }, > + { BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET }, > + { BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET }, > + { BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET }, > + { BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET }, > + { BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET }, > + { BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET }, > + { BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET }, > + { BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET }, > + { BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET }, > + { BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET }, > + { BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET }, > + { BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET }, > + { BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET }, > + { BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET }, > + { BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET }, > + { BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET }, > + { BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET }, > + { BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET }, > + { BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET }, > + { BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET }, > +}; > + > static inline enum port intel_dsi_seq_port_to_port(u8 port) > { > return port ? PORT_C : PORT_A; > @@ -305,6 +936,40 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, > mutex_unlock(&dev_priv->sb_lock); > } > > +static void bxt_exec_gpio(struct drm_i915_private *dev_priv, > + u8 gpio_source, u8 gpio_index, u8 action) > +{ > + struct bxt_gpio_map *map = NULL; > + unsigned int gpio; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(bxt_gpio_table); i++) { > + if (gpio_index == bxt_gpio_table[i].gpio_index) { > + map = &bxt_gpio_table[i]; > + break; > + } > + } > + > + if (!map) { > + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); > + return; > + } > + > + gpio = map->gpio_number; > + > + if (!map->requested) { > + int ret = devm_gpio_request_one(dev_priv->dev->dev, gpio, > + GPIOF_DIR_OUT, "MIPI DSI"); > + if (ret) { > + DRM_ERROR("unable to request GPIO %u (%d)\n", gpio, ret); > + return; > + } > + map->requested = true; > + } > + > + gpio_set_value(gpio, action); > +} > + > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -330,7 +995,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > else if (IS_CHERRYVIEW(dev_priv)) > chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); > else > - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > + bxt_exec_gpio(dev_priv, gpio_source, gpio_index, action); Should we check for BXT platform here before entering to gpio routine and if not BXT in question leave the debug message as is? > return data; > } -- Mika Kahola - Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support 2016-03-23 10:55 ` Mika Kahola @ 2016-03-23 11:19 ` Jani Nikula 0 siblings, 0 replies; 23+ messages in thread From: Jani Nikula @ 2016-03-23 11:19 UTC (permalink / raw) To: mika.kahola; +Cc: Deepak M, intel-gfx On Wed, 23 Mar 2016, Mika Kahola <mika.kahola@intel.com> wrote: > On Fri, 2016-03-18 at 13:11 +0200, Jani Nikula wrote: >> Use a table similar to vlv to check for accepted gpio indexes. For now, >> add all, but this list should be trimmed down. Use managed gpio request, >> which will be automatically released when the driver is detached. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 667 ++++++++++++++++++++++++++++- >> 1 file changed, 666 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> index f8d3f608e9c8..6b8dc15f3656 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c >> @@ -29,6 +29,7 @@ >> #include <drm/drm_edid.h> >> #include <drm/i915_drm.h> >> #include <drm/drm_panel.h> >> +#include <linux/gpio.h> >> #include <linux/slab.h> >> #include <video/mipi_display.h> >> #include <asm/intel-mid.h> >> @@ -114,6 +115,636 @@ static struct vlv_gpio_map vlv_gpio_table[] = { >> #define CHV_GPIO_CFG_HIZ 0x00008100 >> #define CHV_GPIO_CFG_TX_STATE_SHIFT 1 >> >> +#define BXT_HV_DDI0_DDC_SDA_PIN 187 >> +#define BXT_HV_DDI0_DDC_SCL_PIN 188 >> +#define BXT_HV_DDI1_DDC_SDA_PIN 189 >> +#define BXT_HV_DDI1_DDC_SCL_PIN 190 >> +#define BXT_DBI_SDA_PIN 191 >> +#define BXT_DBI_SCL_PIN 192 >> +#define BXT_PANEL0_VDDEN_PIN 193 >> +#define BXT_PANEL0_BKLTEN_PIN 194 >> +#define BXT_PANEL0_BKLTCTL_PIN 195 >> +#define BXT_PANEL1_VDDEN_PIN 196 >> +#define BXT_PANEL1_BKLTEN_PIN 197 >> +#define BXT_PANEL1_BKLTCTL_PIN 198 >> +#define BXT_DBI_CSX_PIN 199 >> +#define BXT_DBI_RESX_PIN 200 >> +#define BXT_GP_INTD_DSI_TE1_PIN 201 >> +#define BXT_GP_INTD_DSI_TE2_PIN 202 >> +#define BXT_USB_OC0_B_PIN 203 >> +#define BXT_USB_OC1_B_PIN 204 >> +#define BXT_MEX_WAKE0_B_PIN 205 >> +#define BXT_MEX_WAKE1_B_PIN 206 >> +#define BXT_EMMC0_CLK_PIN 156 >> +#define BXT_EMMC0_D0_PIN 157 >> +#define BXT_EMMC0_D1_PIN 158 >> +#define BXT_EMMC0_D2_PIN 159 >> +#define BXT_EMMC0_D3_PIN 160 >> +#define BXT_EMMC0_D4_PIN 161 >> +#define BXT_EMMC0_D5_PIN 162 >> +#define BXT_EMMC0_D6_PIN 163 >> +#define BXT_EMMC0_D7_PIN 164 >> +#define BXT_EMMC0_CMD_PIN 165 >> +#define BXT_SDIO_CLK_PIN 166 >> +#define BXT_SDIO_D0_PIN 167 >> +#define BXT_SDIO_D1_PIN 168 >> +#define BXT_SDIO_D2_PIN 169 >> +#define BXT_SDIO_D3_PIN 170 >> +#define BXT_SDIO_CMD_PIN 171 >> +#define BXT_SDCARD_CLK_PIN 172 >> +#define BXT_SDCARD_D0_PIN 173 >> +#define BXT_SDCARD_D1_PIN 174 >> +#define BXT_SDCARD_D2_PIN 175 >> +#define BXT_SDCARD_D3_PIN 176 >> +#define BXT_SDCARD_CD_B_PIN 177 >> +#define BXT_SDCARD_CMD_PIN 178 >> +#define BXT_SDCARD_LVL_CLK_FB_PIN 179 >> +#define BXT_SDCARD_LVL_CMD_DIR_PIN 180 >> +#define BXT_SDCARD_LVL_DAT_DIR_PIN 181 >> +#define BXT_EMMC0_STROBE_PIN 182 >> +#define BXT_SDIO_PWR_DOWN_B_PIN 183 >> +#define BXT_SDCARD_PWR_DOWN_B_PIN 184 >> +#define BXT_SDCARD_LVL_SEL_PIN 185 >> +#define BXT_SDCARD_LVL_WP_PIN 186 >> +#define BXT_LPSS_I2C0_SDA_PIN 124 >> +#define BXT_LPSS_I2C0_SCL_PIN 125 >> +#define BXT_LPSS_I2C1_SDA_PIN 126 >> +#define BXT_LPSS_I2C1_SCL_PIN 127 >> +#define BXT_LPSS_I2C2_SDA_PIN 128 >> +#define BXT_LPSS_I2C2_SCL_PIN 129 >> +#define BXT_LPSS_I2C3_SDA_PIN 130 >> +#define BXT_LPSS_I2C3_SCL_PIN 131 >> +#define BXT_LPSS_I2C4_SDA_PIN 132 >> +#define BXT_LPSS_I2C4_SCL_PIN 133 >> +#define BXT_LPSS_I2C5_SDA_PIN 134 >> +#define BXT_LPSS_I2C5_SCL_PIN 135 >> +#define BXT_LPSS_I2C6_SDA_PIN 136 >> +#define BXT_LPSS_I2C6_SCL_PIN 137 >> +#define BXT_LPSS_I2C7_SDA_PIN 138 >> +#define BXT_LPSS_I2C7_SCL_PIN 139 >> +#define BXT_ISH_I2C0_SDA_PIN 140 >> +#define BXT_ISH_I2C0_SCL_PIN 141 >> +#define BXT_ISH_I2C1_SDA_PIN 142 >> +#define BXT_ISH_I2C1_SCL_PIN 143 >> +#define BXT_ISH_I2C2_SDA_PIN 144 >> +#define BXT_ISH_I2C2_SCL_PIN 145 >> +#define BXT_ISH_GPIO_0_PIN 146 >> +#define BXT_ISH_GPIO_1_PIN 147 >> +#define BXT_ISH_GPIO_2_PIN 148 >> +#define BXT_ISH_GPIO_3_PIN 149 >> +#define BXT_ISH_GPIO_4_PIN 150 >> +#define BXT_ISH_GPIO_5_PIN 151 >> +#define BXT_ISH_GPIO_6_PIN 152 >> +#define BXT_ISH_GPIO_7_PIN 153 >> +#define BXT_ISH_GPIO_8_PIN 154 >> +#define BXT_ISH_GPIO_9_PIN 155 >> +#define BXT_AVS_I2S1_MCLK_PIN 74 >> +#define BXT_AVS_I2S1_BCLK_PIN 75 >> +#define BXT_AVS_I2S1_WS_SYNC_PIN 76 >> +#define BXT_AVS_I2S1_SDI_PIN 77 >> +#define BXT_AVS_I2S1_SDO_PIN 78 >> +#define BXT_AVS_M_CLK_A1_PIN 79 >> +#define BXT_AVS_M_CLK_B1_PIN 80 >> +#define BXT_AVS_M_DATA_1_PIN 81 >> +#define BXT_AVS_M_CLK_AB2_PIN 82 >> +#define BXT_AVS_M_DATA_2_PIN 83 >> +#define BXT_AVS_I2S2_MCLK_PIN 84 >> +#define BXT_AVS_I2S2_BCLK_PIN 85 >> +#define BXT_AVS_I2S2_WS_SYNC_PIN 86 >> +#define BXT_AVS_I2S2_SDI_PIN 87 >> +#define BXT_AVS_I2S2_SDO_PIN 88 >> +#define BXT_AVS_I2S3_BCLK_PIN 89 >> +#define BXT_AVS_I2S3_WS_SYNC_PIN 90 >> +#define BXT_AVS_I2S3_SDI_PIN 91 >> +#define BXT_AVS_I2S3_SDO_PIN 92 >> +#define BXT_AVS_I2S4_BCLK_PIN 93 >> +#define BXT_AVS_I2S4_WS_SYNC_PIN 94 >> +#define BXT_AVS_I2S4_SDI_PIN 95 >> +#define BXT_AVS_I2S4_SDO_PIN 96 >> +#define BXT_FST_SPI_CS0_B_PIN 97 >> +#define BXT_FST_SPI_CS1_B_PIN 98 >> +#define BXT_FST_SPI_MOSI_IO0_PIN 99 >> +#define BXT_FST_SPI_MISO_IO1_PIN 100 >> +#define BXT_FST_SPI_IO2_PIN 101 >> +#define BXT_FST_SPI_IO3_PIN 102 >> +#define BXT_FST_SPI_CLK_PIN 103 >> +#define BXT_GP_SSP_0_CLK_PIN 104 >> +#define BXT_GP_SSP_0_FS0_PIN 105 >> +#define BXT_GP_SSP_0_FS1_PIN 106 >> +#define BXT_GP_SSP_0_FS2_PIN 107 >> +#define BXT_GP_SSP_0_RXD_PIN 109 >> +#define BXT_GP_SSP_0_TXD_PIN 110 >> +#define BXT_GP_SSP_1_CLK_PIN 111 >> +#define BXT_GP_SSP_1_FS0_PIN 112 >> +#define BXT_GP_SSP_1_FS1_PIN 113 >> +#define BXT_GP_SSP_1_FS2_PIN 114 >> +#define BXT_GP_SSP_1_FS3_PIN 115 >> +#define BXT_GP_SSP_1_RXD_PIN 116 >> +#define BXT_GP_SSP_1_TXD_PIN 117 >> +#define BXT_GP_SSP_2_CLK_PIN 118 >> +#define BXT_GP_SSP_2_FS0_PIN 119 >> +#define BXT_GP_SSP_2_FS1_PIN 120 >> +#define BXT_GP_SSP_2_FS2_PIN 121 >> +#define BXT_GP_SSP_2_RXD_PIN 122 >> +#define BXT_GP_SSP_2_TXD_PIN 123 >> +#define BXT_TRACE_0_CLK_VNN_PIN 0 >> +#define BXT_TRACE_0_DATA0_VNN_PIN 1 >> +#define BXT_TRACE_0_DATA1_VNN_PIN 2 >> +#define BXT_TRACE_0_DATA2_VNN_PIN 3 >> +#define BXT_TRACE_0_DATA3_VNN_PIN 4 >> +#define BXT_TRACE_0_DATA4_VNN_PIN 5 >> +#define BXT_TRACE_0_DATA5_VNN_PIN 6 >> +#define BXT_TRACE_0_DATA6_VNN_PIN 7 >> +#define BXT_TRACE_0_DATA7_VNN_PIN 8 >> +#define BXT_TRACE_1_CLK_VNN_PIN 9 >> +#define BXT_TRACE_1_DATA0_VNN_PIN 10 >> +#define BXT_TRACE_1_DATA1_VNN_PIN 11 >> +#define BXT_TRACE_1_DATA2_VNN_PIN 12 >> +#define BXT_TRACE_1_DATA3_VNN_PIN 13 >> +#define BXT_TRACE_1_DATA4_VNN_PIN 14 >> +#define BXT_TRACE_1_DATA5_VNN_PIN 15 >> +#define BXT_TRACE_1_DATA6_VNN_PIN 16 >> +#define BXT_TRACE_1_DATA7_VNN_PIN 17 >> +#define BXT_TRACE_2_CLK_VNN_PIN 18 >> +#define BXT_TRACE_2_DATA0_VNN_PIN 19 >> +#define BXT_TRACE_2_DATA1_VNN_PIN 20 >> +#define BXT_TRACE_2_DATA2_VNN_PIN 21 >> +#define BXT_TRACE_2_DATA3_VNN_PIN 22 >> +#define BXT_TRACE_2_DATA4_VNN_PIN 23 >> +#define BXT_TRACE_2_DATA5_VNN_PIN 24 >> +#define BXT_TRACE_2_DATA6_VNN_PIN 25 >> +#define BXT_TRACE_2_DATA7_VNN_PIN 26 >> +#define BXT_TRIGOUT_0_PIN 27 >> +#define BXT_TRIGOUT_1_PIN 28 >> +#define BXT_TRIGIN_0_PIN 29 >> +#define BXT_SEC_TCK_PIN 30 >> +#define BXT_SEC_TDI_PIN 31 >> +#define BXT_SEC_TMS_PIN 32 >> +#define BXT_SEC_TDO_PIN 33 >> +#define BXT_PWM0_PIN 34 >> +#define BXT_PWM1_PIN 35 >> +#define BXT_PWM2_PIN 36 >> +#define BXT_PWM3_PIN 37 >> +#define BXT_LPSS_UART0_RXD_PIN 38 >> +#define BXT_LPSS_UART0_TXD_PIN 39 >> +#define BXT_LPSS_UART0_RTS_B_PIN 40 >> +#define BXT_LPSS_UART0_CTS_B_PIN 41 >> +#define BXT_LPSS_UART1_RXD_PIN 42 >> +#define BXT_LPSS_UART1_TXD_PIN 43 >> +#define BXT_LPSS_UART1_RTS_B_PIN 44 >> +#define BXT_LPSS_UART1_CTS_B_PIN 45 >> +#define BXT_LPSS_UART2_RXD_PIN 46 >> +#define BXT_LPSS_UART2_TXD_PIN 47 >> +#define BXT_LPSS_UART2_RTS_B_PIN 48 >> +#define BXT_LPSS_UART2_CTS_B_PIN 49 >> +#define BXT_ISH_UART0_RXD_PIN 50 >> +#define BXT_ISH_UART0_TXD_PIN 51 >> +#define BXT_ISH_UART0_RTS_B_PIN 52 >> +#define BXT_ISH_UART0_CTS_B_PIN 53 >> +#define BXT_ISH_UART1_RXD_PIN 54 >> +#define BXT_ISH_UART1_TXD_PIN 55 >> +#define BXT_ISH_UART1_RTS_B_PIN 56 >> +#define BXT_ISH_UART1_CTS_B_PIN 57 >> +#define BXT_ISH_UART2_RXD_PIN 58 >> +#define BXT_ISH_UART2_TXD_PIN 59 >> +#define BXT_ISH_UART2_RTS_B_PIN 60 >> +#define BXT_ISH_UART2_CTS_B_PIN 61 >> +#define BXT_GP_CAMERASB00_PIN 62 >> +#define BXT_GP_CAMERASB01_PIN 63 >> +#define BXT_GP_CAMERASB02_PIN 64 >> +#define BXT_GP_CAMERASB03_PIN 65 >> +#define BXT_GP_CAMERASB04_PIN 66 >> +#define BXT_GP_CAMERASB05_PIN 67 >> +#define BXT_GP_CAMERASB06_PIN 68 >> +#define BXT_GP_CAMERASB07_PIN 69 >> +#define BXT_GP_CAMERASB08_PIN 70 >> +#define BXT_GP_CAMERASB09_PIN 71 >> +#define BXT_GP_CAMERASB10_PIN 72 >> +#define BXT_GP_CAMERASB11_PIN 73 >> + >> +#define BXT_HV_DDI0_DDC_SDA_OFFSET 264 >> +#define BXT_HV_DDI0_DDC_SCL_OFFSET 265 >> +#define BXT_HV_DDI1_DDC_SDA_OFFSET 266 >> +#define BXT_HV_DDI1_DDC_SCL_OFFSET 267 >> +#define BXT_DBI_SDA_OFFSET 268 >> +#define BXT_DBI_SCL_OFFSET 269 >> +#define BXT_PANEL0_VDDEN_OFFSET 270 >> +#define BXT_PANEL0_BKLTEN_OFFSET 271 >> +#define BXT_PANEL0_BKLTCTL_OFFSET 272 >> +#define BXT_PANEL1_VDDEN_OFFSET 273 >> +#define BXT_PANEL1_BKLTEN_OFFSET 274 >> +#define BXT_PANEL1_BKLTCTL_OFFSET 275 >> +#define BXT_DBI_CSX_OFFSET 276 >> +#define BXT_DBI_RESX_OFFSET 277 >> +#define BXT_GP_INTD_DSI_TE1_OFFSET 278 >> +#define BXT_GP_INTD_DSI_TE2_OFFSET 279 >> +#define BXT_USB_OC0_B_OFFSET 280 >> +#define BXT_USB_OC1_B_OFFSET 281 >> +#define BXT_MEX_WAKE0_B_OFFSET 282 >> +#define BXT_MEX_WAKE1_B_OFFSET 283 >> +#define BXT_EMMC0_CLK_OFFSET 284 >> +#define BXT_EMMC0_D0_OFFSET 285 >> +#define BXT_EMMC0_D1_OFFSET 286 >> +#define BXT_EMMC0_D2_OFFSET 287 >> +#define BXT_EMMC0_D3_OFFSET 288 >> +#define BXT_EMMC0_D4_OFFSET 289 >> +#define BXT_EMMC0_D5_OFFSET 290 >> +#define BXT_EMMC0_D6_OFFSET 291 >> +#define BXT_EMMC0_D7_OFFSET 292 >> +#define BXT_EMMC0_CMD_OFFSET 293 >> +#define BXT_SDIO_CLK_OFFSET 294 >> +#define BXT_SDIO_D0_OFFSET 295 >> +#define BXT_SDIO_D1_OFFSET 296 >> +#define BXT_SDIO_D2_OFFSET 297 >> +#define BXT_SDIO_D3_OFFSET 298 >> +#define BXT_SDIO_CMD_OFFSET 299 >> +#define BXT_SDCARD_CLK_OFFSET 300 >> +#define BXT_SDCARD_D0_OFFSET 301 >> +#define BXT_SDCARD_D1_OFFSET 302 >> +#define BXT_SDCARD_D2_OFFSET 303 >> +#define BXT_SDCARD_D3_OFFSET 304 >> +#define BXT_SDCARD_CD_B_OFFSET 305 >> +#define BXT_SDCARD_CMD_OFFSET 306 >> +#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307 >> +#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308 >> +#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309 >> +#define BXT_EMMC0_STROBE_OFFSET 310 >> +#define BXT_SDIO_PWR_DOWN_B_OFFSET 311 >> +#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312 >> +#define BXT_SDCARD_LVL_SEL_OFFSET 313 >> +#define BXT_SDCARD_LVL_WP_OFFSET 314 >> +#define BXT_LPSS_I2C0_SDA_OFFSET 315 >> +#define BXT_LPSS_I2C0_SCL_OFFSET 316 >> +#define BXT_LPSS_I2C1_SDA_OFFSET 317 >> +#define BXT_LPSS_I2C1_SCL_OFFSET 318 >> +#define BXT_LPSS_I2C2_SDA_OFFSET 319 >> +#define BXT_LPSS_I2C2_SCL_OFFSET 320 >> +#define BXT_LPSS_I2C3_SDA_OFFSET 321 >> +#define BXT_LPSS_I2C3_SCL_OFFSET 322 >> +#define BXT_LPSS_I2C4_SDA_OFFSET 323 >> +#define BXT_LPSS_I2C4_SCL_OFFSET 324 >> +#define BXT_LPSS_I2C5_SDA_OFFSET 325 >> +#define BXT_LPSS_I2C5_SCL_OFFSET 326 >> +#define BXT_LPSS_I2C6_SDA_OFFSET 327 >> +#define BXT_LPSS_I2C6_SCL_OFFSET 328 >> +#define BXT_LPSS_I2C7_SDA_OFFSET 329 >> +#define BXT_LPSS_I2C7_SCL_OFFSET 330 >> +#define BXT_ISH_I2C0_SDA_OFFSET 331 >> +#define BXT_ISH_I2C0_SCL_OFFSET 332 >> +#define BXT_ISH_I2C1_SDA_OFFSET 333 >> +#define BXT_ISH_I2C1_SCL_OFFSET 334 >> +#define BXT_ISH_I2C2_SDA_OFFSET 335 >> +#define BXT_ISH_I2C2_SCL_OFFSET 336 >> +#define BXT_ISH_GPIO_0_OFFSET 337 >> +#define BXT_ISH_GPIO_1_OFFSET 338 >> +#define BXT_ISH_GPIO_2_OFFSET 339 >> +#define BXT_ISH_GPIO_3_OFFSET 340 >> +#define BXT_ISH_GPIO_4_OFFSET 341 >> +#define BXT_ISH_GPIO_5_OFFSET 342 >> +#define BXT_ISH_GPIO_6_OFFSET 343 >> +#define BXT_ISH_GPIO_7_OFFSET 344 >> +#define BXT_ISH_GPIO_8_OFFSET 345 >> +#define BXT_ISH_GPIO_9_OFFSET 346 >> +#define BXT_AVS_I2S1_MCLK_OFFSET 378 >> +#define BXT_AVS_I2S1_BCLK_OFFSET 379 >> +#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380 >> +#define BXT_AVS_I2S1_SDI_OFFSET 381 >> +#define BXT_AVS_I2S1_SDO_OFFSET 382 >> +#define BXT_AVS_M_CLK_A1_OFFSET 383 >> +#define BXT_AVS_M_CLK_B1_OFFSET 384 >> +#define BXT_AVS_M_DATA_1_OFFSET 385 >> +#define BXT_AVS_M_CLK_AB2_OFFSET 386 >> +#define BXT_AVS_M_DATA_2_OFFSET 387 >> +#define BXT_AVS_I2S2_MCLK_OFFSET 388 >> +#define BXT_AVS_I2S2_BCLK_OFFSET 389 >> +#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390 >> +#define BXT_AVS_I2S2_SDI_OFFSET 391 >> +#define BXT_AVS_I2S2_SDO_OFFSET 392 >> +#define BXT_AVS_I2S3_BCLK_OFFSET 393 >> +#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394 >> +#define BXT_AVS_I2S3_SDI_OFFSET 395 >> +#define BXT_AVS_I2S3_SDO_OFFSET 396 >> +#define BXT_AVS_I2S4_BCLK_OFFSET 397 >> +#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398 >> +#define BXT_AVS_I2S4_SDI_OFFSET 399 >> +#define BXT_AVS_I2S4_SDO_OFFSET 400 >> +#define BXT_FST_SPI_CS0_B_OFFSET 402 >> +#define BXT_FST_SPI_CS1_B_OFFSET 403 >> +#define BXT_FST_SPI_MOSI_IO0_OFFSET 404 >> +#define BXT_FST_SPI_MISO_IO1_OFFSET 405 >> +#define BXT_FST_SPI_IO2_OFFSET 406 >> +#define BXT_FST_SPI_IO3_OFFSET 407 >> +#define BXT_FST_SPI_CLK_OFFSET 408 >> +#define BXT_GP_SSP_0_CLK_OFFSET 410 >> +#define BXT_GP_SSP_0_FS0_OFFSET 411 >> +#define BXT_GP_SSP_0_FS1_OFFSET 412 >> +#define BXT_GP_SSP_0_FS2_OFFSET 413 >> +#define BXT_GP_SSP_0_RXD_OFFSET 414 >> +#define BXT_GP_SSP_0_TXD_OFFSET 415 >> +#define BXT_GP_SSP_1_CLK_OFFSET 416 >> +#define BXT_GP_SSP_1_FS0_OFFSET 417 >> +#define BXT_GP_SSP_1_FS1_OFFSET 418 >> +#define BXT_GP_SSP_1_FS2_OFFSET 419 >> +#define BXT_GP_SSP_1_FS3_OFFSET 420 >> +#define BXT_GP_SSP_1_RXD_OFFSET 421 >> +#define BXT_GP_SSP_1_TXD_OFFSET 422 >> +#define BXT_GP_SSP_2_CLK_OFFSET 423 >> +#define BXT_GP_SSP_2_FS0_OFFSET 424 >> +#define BXT_GP_SSP_2_FS1_OFFSET 425 >> +#define BXT_GP_SSP_2_FS2_OFFSET 426 >> +#define BXT_GP_SSP_2_RXD_OFFSET 427 >> +#define BXT_GP_SSP_2_TXD_OFFSET 428 >> +#define BXT_TRACE_0_CLK_VNN_OFFSET 429 >> +#define BXT_TRACE_0_DATA0_VNN_OFFSET 430 >> +#define BXT_TRACE_0_DATA1_VNN_OFFSET 431 >> +#define BXT_TRACE_0_DATA2_VNN_OFFSET 432 >> +#define BXT_TRACE_0_DATA3_VNN_OFFSET 433 >> +#define BXT_TRACE_0_DATA4_VNN_OFFSET 434 >> +#define BXT_TRACE_0_DATA5_VNN_OFFSET 435 >> +#define BXT_TRACE_0_DATA6_VNN_OFFSET 436 >> +#define BXT_TRACE_0_DATA7_VNN_OFFSET 437 >> +#define BXT_TRACE_1_CLK_VNN_OFFSET 438 >> +#define BXT_TRACE_1_DATA0_VNN_OFFSET 439 >> +#define BXT_TRACE_1_DATA1_VNN_OFFSET 440 >> +#define BXT_TRACE_1_DATA2_VNN_OFFSET 441 >> +#define BXT_TRACE_1_DATA3_VNN_OFFSET 442 >> +#define BXT_TRACE_1_DATA4_VNN_OFFSET 443 >> +#define BXT_TRACE_1_DATA5_VNN_OFFSET 444 >> +#define BXT_TRACE_1_DATA6_VNN_OFFSET 445 >> +#define BXT_TRACE_1_DATA7_VNN_OFFSET 446 >> +#define BXT_TRACE_2_CLK_VNN_OFFSET 447 >> +#define BXT_TRACE_2_DATA0_VNN_OFFSET 448 >> +#define BXT_TRACE_2_DATA1_VNN_OFFSET 449 >> +#define BXT_TRACE_2_DATA2_VNN_OFFSET 450 >> +#define BXT_TRACE_2_DATA3_VNN_OFFSET 451 >> +#define BXT_TRACE_2_DATA4_VNN_OFFSET 452 >> +#define BXT_TRACE_2_DATA5_VNN_OFFSET 453 >> +#define BXT_TRACE_2_DATA6_VNN_OFFSET 454 >> +#define BXT_TRACE_2_DATA7_VNN_OFFSET 455 >> +#define BXT_TRIGOUT_0_OFFSET 456 >> +#define BXT_TRIGOUT_1_OFFSET 457 >> +#define BXT_TRIGIN_0_OFFSET 458 >> +#define BXT_SEC_TCK_OFFSET 459 >> +#define BXT_SEC_TDI_OFFSET 460 >> +#define BXT_SEC_TMS_OFFSET 461 >> +#define BXT_SEC_TDO_OFFSET 462 >> +#define BXT_PWM0_OFFSET 463 >> +#define BXT_PWM1_OFFSET 464 >> +#define BXT_PWM2_OFFSET 465 >> +#define BXT_PWM3_OFFSET 466 >> +#define BXT_LPSS_UART0_RXD_OFFSET 467 >> +#define BXT_LPSS_UART0_TXD_OFFSET 468 >> +#define BXT_LPSS_UART0_RTS_B_OFFSET 469 >> +#define BXT_LPSS_UART0_CTS_B_OFFSET 470 >> +#define BXT_LPSS_UART1_RXD_OFFSET 471 >> +#define BXT_LPSS_UART1_TXD_OFFSET 472 >> +#define BXT_LPSS_UART1_RTS_B_OFFSET 473 >> +#define BXT_LPSS_UART1_CTS_B_OFFSET 474 >> +#define BXT_LPSS_UART2_RXD_OFFSET 475 >> +#define BXT_LPSS_UART2_TXD_OFFSET 476 >> +#define BXT_LPSS_UART2_RTS_B_OFFSET 477 >> +#define BXT_LPSS_UART2_CTS_B_OFFSET 478 >> +#define BXT_ISH_UART0_RXD_OFFSET 479 >> +#define BXT_ISH_UART0_TXD_OFFSET 480 >> +#define BXT_ISH_UART0_RTS_B_OFFSET 481 >> +#define BXT_ISH_UART0_CTS_B_OFFSET 482 >> +#define BXT_ISH_UART1_RXD_OFFSET 483 >> +#define BXT_ISH_UART1_TXD_OFFSET 484 >> +#define BXT_ISH_UART1_RTS_B_OFFSET 485 >> +#define BXT_ISH_UART1_CTS_B_OFFSET 486 >> +#define BXT_ISH_UART2_RXD_OFFSET 487 >> +#define BXT_ISH_UART2_TXD_OFFSET 488 >> +#define BXT_ISH_UART2_RTS_B_OFFSET 489 >> +#define BXT_ISH_UART2_CTS_B_OFFSET 490 >> +#define BXT_GP_CAMERASB00_OFFSET 491 >> +#define BXT_GP_CAMERASB01_OFFSET 492 >> +#define BXT_GP_CAMERASB02_OFFSET 493 >> +#define BXT_GP_CAMERASB03_OFFSET 494 >> +#define BXT_GP_CAMERASB04_OFFSET 495 >> +#define BXT_GP_CAMERASB05_OFFSET 496 >> +#define BXT_GP_CAMERASB06_OFFSET 497 >> +#define BXT_GP_CAMERASB07_OFFSET 498 >> +#define BXT_GP_CAMERASB08_OFFSET 499 >> +#define BXT_GP_CAMERASB09_OFFSET 500 >> +#define BXT_GP_CAMERASB10_OFFSET 501 >> +#define BXT_GP_CAMERASB11_OFFSET 502 >> + >> +struct bxt_gpio_map { >> + u8 gpio_index; >> + u16 gpio_number; >> + bool requested; >> +}; >> + >> +/* XXX: take out everything that is not related to DSI display */ >> +static struct bxt_gpio_map bxt_gpio_table[] = { >> + { BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET }, >> + { BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET }, >> + { BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET }, >> + { BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET }, >> + { BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET }, >> + { BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET }, >> + { BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET }, >> + { BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET }, >> + { BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET }, >> + { BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET }, >> + { BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET }, >> + { BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET }, >> + { BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET }, >> + { BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET }, >> + { BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET }, >> + { BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET }, >> + { BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET }, >> + { BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET }, >> + { BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET }, >> + { BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET }, >> + { BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET }, >> + { BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET }, >> + { BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET }, >> + { BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET }, >> + { BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET }, >> + { BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET }, >> + { BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET }, >> + { BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET }, >> + { BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET }, >> + { BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET }, >> + { BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET }, >> + { BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET }, >> + { BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET }, >> + { BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET }, >> + { BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET }, >> + { BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET }, >> + { BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET }, >> + { BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET }, >> + { BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET }, >> + { BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET }, >> + { BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET }, >> + { BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET }, >> + { BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET }, >> + { BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET }, >> + { BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET }, >> + { BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET }, >> + { BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET }, >> + { BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET }, >> + { BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET }, >> + { BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET }, >> + { BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET }, >> + { BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET }, >> + { BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET }, >> + { BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET }, >> + { BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET }, >> + { BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET }, >> + { BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET }, >> + { BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET }, >> + { BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET }, >> + { BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET }, >> + { BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET }, >> + { BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET }, >> + { BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET }, >> + { BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET }, >> + { BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET }, >> + { BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET }, >> + { BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET }, >> + { BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET }, >> + { BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET }, >> + { BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET }, >> + { BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET }, >> + { BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET }, >> + { BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET }, >> + { BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET }, >> + { BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET }, >> + { BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET }, >> + { BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET }, >> + { BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET }, >> + { BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET }, >> + { BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET }, >> + { BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET }, >> + { BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET }, >> + { BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET }, >> + { BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET }, >> + { BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET }, >> + { BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET }, >> + { BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET }, >> + { BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET }, >> + { BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET }, >> + { BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET }, >> + { BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET }, >> + { BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET }, >> + { BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET }, >> + { BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET }, >> + { BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET }, >> + { BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET }, >> + { BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET }, >> + { BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET }, >> + { BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET }, >> + { BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET }, >> + { BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET }, >> + { BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET }, >> + { BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET }, >> + { BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET }, >> + { BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET }, >> + { BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET }, >> + { BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET }, >> + { BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET }, >> + { BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET }, >> + { BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET }, >> + { BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET }, >> + { BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET }, >> + { BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET }, >> + { BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET }, >> + { BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET }, >> + { BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET }, >> + { BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET }, >> + { BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET }, >> + { BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET }, >> + { BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET }, >> + { BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET }, >> + { BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET }, >> + { BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET }, >> + { BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET }, >> + { BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET }, >> + { BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET }, >> + { BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET }, >> + { BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET }, >> + { BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET }, >> + { BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET }, >> + { BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET }, >> + { BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET }, >> + { BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET }, >> + { BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET }, >> + { BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET }, >> + { BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET }, >> + { BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET }, >> + { BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET }, >> + { BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET }, >> + { BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET }, >> + { BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET }, >> + { BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET }, >> + { BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET }, >> + { BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET }, >> + { BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET }, >> + { BXT_PWM0_PIN, BXT_PWM0_OFFSET }, >> + { BXT_PWM1_PIN, BXT_PWM1_OFFSET }, >> + { BXT_PWM2_PIN, BXT_PWM2_OFFSET }, >> + { BXT_PWM3_PIN, BXT_PWM3_OFFSET }, >> + { BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET }, >> + { BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET }, >> + { BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET }, >> + { BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET }, >> + { BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET }, >> + { BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET }, >> + { BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET }, >> + { BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET }, >> + { BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET }, >> + { BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET }, >> + { BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET }, >> + { BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET }, >> + { BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET }, >> + { BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET }, >> + { BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET }, >> + { BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET }, >> + { BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET }, >> + { BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET }, >> + { BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET }, >> + { BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET }, >> + { BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET }, >> + { BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET }, >> + { BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET }, >> + { BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET }, >> + { BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET }, >> + { BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET }, >> + { BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET }, >> + { BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET }, >> + { BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET }, >> + { BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET }, >> + { BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET }, >> + { BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET }, >> + { BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET }, >> + { BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET }, >> + { BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET }, >> + { BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET }, >> +}; >> + >> static inline enum port intel_dsi_seq_port_to_port(u8 port) >> { >> return port ? PORT_C : PORT_A; >> @@ -305,6 +936,40 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, >> mutex_unlock(&dev_priv->sb_lock); >> } >> >> +static void bxt_exec_gpio(struct drm_i915_private *dev_priv, >> + u8 gpio_source, u8 gpio_index, u8 action) >> +{ >> + struct bxt_gpio_map *map = NULL; >> + unsigned int gpio; >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(bxt_gpio_table); i++) { >> + if (gpio_index == bxt_gpio_table[i].gpio_index) { >> + map = &bxt_gpio_table[i]; >> + break; >> + } >> + } >> + >> + if (!map) { >> + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); >> + return; >> + } >> + >> + gpio = map->gpio_number; >> + >> + if (!map->requested) { >> + int ret = devm_gpio_request_one(dev_priv->dev->dev, gpio, >> + GPIOF_DIR_OUT, "MIPI DSI"); >> + if (ret) { >> + DRM_ERROR("unable to request GPIO %u (%d)\n", gpio, ret); >> + return; >> + } >> + map->requested = true; >> + } >> + >> + gpio_set_value(gpio, action); >> +} >> + >> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> { >> struct drm_device *dev = intel_dsi->base.base.dev; >> @@ -330,7 +995,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) >> else if (IS_CHERRYVIEW(dev_priv)) >> chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); >> else >> - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); >> + bxt_exec_gpio(dev_priv, gpio_source, gpio_index, action); > Should we check for BXT platform here before entering to gpio routine > and if not BXT in question leave the debug message as is? I don't think so. We don't initialize DSI or anything other than vlv, chv, and bxt. DSI enabling for new platforms need to cover these. BR, Jani. > > >> return data; >> } -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support 2016-03-18 11:11 ` [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support Jani Nikula 2016-03-23 10:55 ` Mika Kahola @ 2016-04-04 17:46 ` Ville Syrjälä 1 sibling, 0 replies; 23+ messages in thread From: Ville Syrjälä @ 2016-04-04 17:46 UTC (permalink / raw) To: Jani Nikula; +Cc: Deepak M, intel-gfx On Fri, Mar 18, 2016 at 01:11:17PM +0200, Jani Nikula wrote: > Use a table similar to vlv to check for accepted gpio indexes. For now, > add all, but this list should be trimmed down. Use managed gpio request, > which will be automatically released when the driver is detached. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 667 ++++++++++++++++++++++++++++- > 1 file changed, 666 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > index f8d3f608e9c8..6b8dc15f3656 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c > @@ -29,6 +29,7 @@ > #include <drm/drm_edid.h> > #include <drm/i915_drm.h> > #include <drm/drm_panel.h> > +#include <linux/gpio.h> > #include <linux/slab.h> > #include <video/mipi_display.h> > #include <asm/intel-mid.h> > @@ -114,6 +115,636 @@ static struct vlv_gpio_map vlv_gpio_table[] = { > #define CHV_GPIO_CFG_HIZ 0x00008100 > #define CHV_GPIO_CFG_TX_STATE_SHIFT 1 > > +#define BXT_HV_DDI0_DDC_SDA_PIN 187 > +#define BXT_HV_DDI0_DDC_SCL_PIN 188 > +#define BXT_HV_DDI1_DDC_SDA_PIN 189 > +#define BXT_HV_DDI1_DDC_SCL_PIN 190 More magic numbers without explanation. This also suffers from the same problem that the i2c seq patch has, as in requesting/frobbing random gpios. We should really use the consumer gpio consumer API I think to make sure we get the right thing. > +#define BXT_DBI_SDA_PIN 191 > +#define BXT_DBI_SCL_PIN 192 > +#define BXT_PANEL0_VDDEN_PIN 193 > +#define BXT_PANEL0_BKLTEN_PIN 194 > +#define BXT_PANEL0_BKLTCTL_PIN 195 > +#define BXT_PANEL1_VDDEN_PIN 196 > +#define BXT_PANEL1_BKLTEN_PIN 197 > +#define BXT_PANEL1_BKLTCTL_PIN 198 > +#define BXT_DBI_CSX_PIN 199 > +#define BXT_DBI_RESX_PIN 200 > +#define BXT_GP_INTD_DSI_TE1_PIN 201 > +#define BXT_GP_INTD_DSI_TE2_PIN 202 > +#define BXT_USB_OC0_B_PIN 203 > +#define BXT_USB_OC1_B_PIN 204 > +#define BXT_MEX_WAKE0_B_PIN 205 > +#define BXT_MEX_WAKE1_B_PIN 206 > +#define BXT_EMMC0_CLK_PIN 156 > +#define BXT_EMMC0_D0_PIN 157 > +#define BXT_EMMC0_D1_PIN 158 > +#define BXT_EMMC0_D2_PIN 159 > +#define BXT_EMMC0_D3_PIN 160 > +#define BXT_EMMC0_D4_PIN 161 > +#define BXT_EMMC0_D5_PIN 162 > +#define BXT_EMMC0_D6_PIN 163 > +#define BXT_EMMC0_D7_PIN 164 > +#define BXT_EMMC0_CMD_PIN 165 > +#define BXT_SDIO_CLK_PIN 166 > +#define BXT_SDIO_D0_PIN 167 > +#define BXT_SDIO_D1_PIN 168 > +#define BXT_SDIO_D2_PIN 169 > +#define BXT_SDIO_D3_PIN 170 > +#define BXT_SDIO_CMD_PIN 171 > +#define BXT_SDCARD_CLK_PIN 172 > +#define BXT_SDCARD_D0_PIN 173 > +#define BXT_SDCARD_D1_PIN 174 > +#define BXT_SDCARD_D2_PIN 175 > +#define BXT_SDCARD_D3_PIN 176 > +#define BXT_SDCARD_CD_B_PIN 177 > +#define BXT_SDCARD_CMD_PIN 178 > +#define BXT_SDCARD_LVL_CLK_FB_PIN 179 > +#define BXT_SDCARD_LVL_CMD_DIR_PIN 180 > +#define BXT_SDCARD_LVL_DAT_DIR_PIN 181 > +#define BXT_EMMC0_STROBE_PIN 182 > +#define BXT_SDIO_PWR_DOWN_B_PIN 183 > +#define BXT_SDCARD_PWR_DOWN_B_PIN 184 > +#define BXT_SDCARD_LVL_SEL_PIN 185 > +#define BXT_SDCARD_LVL_WP_PIN 186 > +#define BXT_LPSS_I2C0_SDA_PIN 124 > +#define BXT_LPSS_I2C0_SCL_PIN 125 > +#define BXT_LPSS_I2C1_SDA_PIN 126 > +#define BXT_LPSS_I2C1_SCL_PIN 127 > +#define BXT_LPSS_I2C2_SDA_PIN 128 > +#define BXT_LPSS_I2C2_SCL_PIN 129 > +#define BXT_LPSS_I2C3_SDA_PIN 130 > +#define BXT_LPSS_I2C3_SCL_PIN 131 > +#define BXT_LPSS_I2C4_SDA_PIN 132 > +#define BXT_LPSS_I2C4_SCL_PIN 133 > +#define BXT_LPSS_I2C5_SDA_PIN 134 > +#define BXT_LPSS_I2C5_SCL_PIN 135 > +#define BXT_LPSS_I2C6_SDA_PIN 136 > +#define BXT_LPSS_I2C6_SCL_PIN 137 > +#define BXT_LPSS_I2C7_SDA_PIN 138 > +#define BXT_LPSS_I2C7_SCL_PIN 139 > +#define BXT_ISH_I2C0_SDA_PIN 140 > +#define BXT_ISH_I2C0_SCL_PIN 141 > +#define BXT_ISH_I2C1_SDA_PIN 142 > +#define BXT_ISH_I2C1_SCL_PIN 143 > +#define BXT_ISH_I2C2_SDA_PIN 144 > +#define BXT_ISH_I2C2_SCL_PIN 145 > +#define BXT_ISH_GPIO_0_PIN 146 > +#define BXT_ISH_GPIO_1_PIN 147 > +#define BXT_ISH_GPIO_2_PIN 148 > +#define BXT_ISH_GPIO_3_PIN 149 > +#define BXT_ISH_GPIO_4_PIN 150 > +#define BXT_ISH_GPIO_5_PIN 151 > +#define BXT_ISH_GPIO_6_PIN 152 > +#define BXT_ISH_GPIO_7_PIN 153 > +#define BXT_ISH_GPIO_8_PIN 154 > +#define BXT_ISH_GPIO_9_PIN 155 > +#define BXT_AVS_I2S1_MCLK_PIN 74 > +#define BXT_AVS_I2S1_BCLK_PIN 75 > +#define BXT_AVS_I2S1_WS_SYNC_PIN 76 > +#define BXT_AVS_I2S1_SDI_PIN 77 > +#define BXT_AVS_I2S1_SDO_PIN 78 > +#define BXT_AVS_M_CLK_A1_PIN 79 > +#define BXT_AVS_M_CLK_B1_PIN 80 > +#define BXT_AVS_M_DATA_1_PIN 81 > +#define BXT_AVS_M_CLK_AB2_PIN 82 > +#define BXT_AVS_M_DATA_2_PIN 83 > +#define BXT_AVS_I2S2_MCLK_PIN 84 > +#define BXT_AVS_I2S2_BCLK_PIN 85 > +#define BXT_AVS_I2S2_WS_SYNC_PIN 86 > +#define BXT_AVS_I2S2_SDI_PIN 87 > +#define BXT_AVS_I2S2_SDO_PIN 88 > +#define BXT_AVS_I2S3_BCLK_PIN 89 > +#define BXT_AVS_I2S3_WS_SYNC_PIN 90 > +#define BXT_AVS_I2S3_SDI_PIN 91 > +#define BXT_AVS_I2S3_SDO_PIN 92 > +#define BXT_AVS_I2S4_BCLK_PIN 93 > +#define BXT_AVS_I2S4_WS_SYNC_PIN 94 > +#define BXT_AVS_I2S4_SDI_PIN 95 > +#define BXT_AVS_I2S4_SDO_PIN 96 > +#define BXT_FST_SPI_CS0_B_PIN 97 > +#define BXT_FST_SPI_CS1_B_PIN 98 > +#define BXT_FST_SPI_MOSI_IO0_PIN 99 > +#define BXT_FST_SPI_MISO_IO1_PIN 100 > +#define BXT_FST_SPI_IO2_PIN 101 > +#define BXT_FST_SPI_IO3_PIN 102 > +#define BXT_FST_SPI_CLK_PIN 103 > +#define BXT_GP_SSP_0_CLK_PIN 104 > +#define BXT_GP_SSP_0_FS0_PIN 105 > +#define BXT_GP_SSP_0_FS1_PIN 106 > +#define BXT_GP_SSP_0_FS2_PIN 107 > +#define BXT_GP_SSP_0_RXD_PIN 109 > +#define BXT_GP_SSP_0_TXD_PIN 110 > +#define BXT_GP_SSP_1_CLK_PIN 111 > +#define BXT_GP_SSP_1_FS0_PIN 112 > +#define BXT_GP_SSP_1_FS1_PIN 113 > +#define BXT_GP_SSP_1_FS2_PIN 114 > +#define BXT_GP_SSP_1_FS3_PIN 115 > +#define BXT_GP_SSP_1_RXD_PIN 116 > +#define BXT_GP_SSP_1_TXD_PIN 117 > +#define BXT_GP_SSP_2_CLK_PIN 118 > +#define BXT_GP_SSP_2_FS0_PIN 119 > +#define BXT_GP_SSP_2_FS1_PIN 120 > +#define BXT_GP_SSP_2_FS2_PIN 121 > +#define BXT_GP_SSP_2_RXD_PIN 122 > +#define BXT_GP_SSP_2_TXD_PIN 123 > +#define BXT_TRACE_0_CLK_VNN_PIN 0 > +#define BXT_TRACE_0_DATA0_VNN_PIN 1 > +#define BXT_TRACE_0_DATA1_VNN_PIN 2 > +#define BXT_TRACE_0_DATA2_VNN_PIN 3 > +#define BXT_TRACE_0_DATA3_VNN_PIN 4 > +#define BXT_TRACE_0_DATA4_VNN_PIN 5 > +#define BXT_TRACE_0_DATA5_VNN_PIN 6 > +#define BXT_TRACE_0_DATA6_VNN_PIN 7 > +#define BXT_TRACE_0_DATA7_VNN_PIN 8 > +#define BXT_TRACE_1_CLK_VNN_PIN 9 > +#define BXT_TRACE_1_DATA0_VNN_PIN 10 > +#define BXT_TRACE_1_DATA1_VNN_PIN 11 > +#define BXT_TRACE_1_DATA2_VNN_PIN 12 > +#define BXT_TRACE_1_DATA3_VNN_PIN 13 > +#define BXT_TRACE_1_DATA4_VNN_PIN 14 > +#define BXT_TRACE_1_DATA5_VNN_PIN 15 > +#define BXT_TRACE_1_DATA6_VNN_PIN 16 > +#define BXT_TRACE_1_DATA7_VNN_PIN 17 > +#define BXT_TRACE_2_CLK_VNN_PIN 18 > +#define BXT_TRACE_2_DATA0_VNN_PIN 19 > +#define BXT_TRACE_2_DATA1_VNN_PIN 20 > +#define BXT_TRACE_2_DATA2_VNN_PIN 21 > +#define BXT_TRACE_2_DATA3_VNN_PIN 22 > +#define BXT_TRACE_2_DATA4_VNN_PIN 23 > +#define BXT_TRACE_2_DATA5_VNN_PIN 24 > +#define BXT_TRACE_2_DATA6_VNN_PIN 25 > +#define BXT_TRACE_2_DATA7_VNN_PIN 26 > +#define BXT_TRIGOUT_0_PIN 27 > +#define BXT_TRIGOUT_1_PIN 28 > +#define BXT_TRIGIN_0_PIN 29 > +#define BXT_SEC_TCK_PIN 30 > +#define BXT_SEC_TDI_PIN 31 > +#define BXT_SEC_TMS_PIN 32 > +#define BXT_SEC_TDO_PIN 33 > +#define BXT_PWM0_PIN 34 > +#define BXT_PWM1_PIN 35 > +#define BXT_PWM2_PIN 36 > +#define BXT_PWM3_PIN 37 > +#define BXT_LPSS_UART0_RXD_PIN 38 > +#define BXT_LPSS_UART0_TXD_PIN 39 > +#define BXT_LPSS_UART0_RTS_B_PIN 40 > +#define BXT_LPSS_UART0_CTS_B_PIN 41 > +#define BXT_LPSS_UART1_RXD_PIN 42 > +#define BXT_LPSS_UART1_TXD_PIN 43 > +#define BXT_LPSS_UART1_RTS_B_PIN 44 > +#define BXT_LPSS_UART1_CTS_B_PIN 45 > +#define BXT_LPSS_UART2_RXD_PIN 46 > +#define BXT_LPSS_UART2_TXD_PIN 47 > +#define BXT_LPSS_UART2_RTS_B_PIN 48 > +#define BXT_LPSS_UART2_CTS_B_PIN 49 > +#define BXT_ISH_UART0_RXD_PIN 50 > +#define BXT_ISH_UART0_TXD_PIN 51 > +#define BXT_ISH_UART0_RTS_B_PIN 52 > +#define BXT_ISH_UART0_CTS_B_PIN 53 > +#define BXT_ISH_UART1_RXD_PIN 54 > +#define BXT_ISH_UART1_TXD_PIN 55 > +#define BXT_ISH_UART1_RTS_B_PIN 56 > +#define BXT_ISH_UART1_CTS_B_PIN 57 > +#define BXT_ISH_UART2_RXD_PIN 58 > +#define BXT_ISH_UART2_TXD_PIN 59 > +#define BXT_ISH_UART2_RTS_B_PIN 60 > +#define BXT_ISH_UART2_CTS_B_PIN 61 > +#define BXT_GP_CAMERASB00_PIN 62 > +#define BXT_GP_CAMERASB01_PIN 63 > +#define BXT_GP_CAMERASB02_PIN 64 > +#define BXT_GP_CAMERASB03_PIN 65 > +#define BXT_GP_CAMERASB04_PIN 66 > +#define BXT_GP_CAMERASB05_PIN 67 > +#define BXT_GP_CAMERASB06_PIN 68 > +#define BXT_GP_CAMERASB07_PIN 69 > +#define BXT_GP_CAMERASB08_PIN 70 > +#define BXT_GP_CAMERASB09_PIN 71 > +#define BXT_GP_CAMERASB10_PIN 72 > +#define BXT_GP_CAMERASB11_PIN 73 > + > +#define BXT_HV_DDI0_DDC_SDA_OFFSET 264 > +#define BXT_HV_DDI0_DDC_SCL_OFFSET 265 > +#define BXT_HV_DDI1_DDC_SDA_OFFSET 266 > +#define BXT_HV_DDI1_DDC_SCL_OFFSET 267 > +#define BXT_DBI_SDA_OFFSET 268 > +#define BXT_DBI_SCL_OFFSET 269 > +#define BXT_PANEL0_VDDEN_OFFSET 270 > +#define BXT_PANEL0_BKLTEN_OFFSET 271 > +#define BXT_PANEL0_BKLTCTL_OFFSET 272 > +#define BXT_PANEL1_VDDEN_OFFSET 273 > +#define BXT_PANEL1_BKLTEN_OFFSET 274 > +#define BXT_PANEL1_BKLTCTL_OFFSET 275 > +#define BXT_DBI_CSX_OFFSET 276 > +#define BXT_DBI_RESX_OFFSET 277 > +#define BXT_GP_INTD_DSI_TE1_OFFSET 278 > +#define BXT_GP_INTD_DSI_TE2_OFFSET 279 > +#define BXT_USB_OC0_B_OFFSET 280 > +#define BXT_USB_OC1_B_OFFSET 281 > +#define BXT_MEX_WAKE0_B_OFFSET 282 > +#define BXT_MEX_WAKE1_B_OFFSET 283 > +#define BXT_EMMC0_CLK_OFFSET 284 > +#define BXT_EMMC0_D0_OFFSET 285 > +#define BXT_EMMC0_D1_OFFSET 286 > +#define BXT_EMMC0_D2_OFFSET 287 > +#define BXT_EMMC0_D3_OFFSET 288 > +#define BXT_EMMC0_D4_OFFSET 289 > +#define BXT_EMMC0_D5_OFFSET 290 > +#define BXT_EMMC0_D6_OFFSET 291 > +#define BXT_EMMC0_D7_OFFSET 292 > +#define BXT_EMMC0_CMD_OFFSET 293 > +#define BXT_SDIO_CLK_OFFSET 294 > +#define BXT_SDIO_D0_OFFSET 295 > +#define BXT_SDIO_D1_OFFSET 296 > +#define BXT_SDIO_D2_OFFSET 297 > +#define BXT_SDIO_D3_OFFSET 298 > +#define BXT_SDIO_CMD_OFFSET 299 > +#define BXT_SDCARD_CLK_OFFSET 300 > +#define BXT_SDCARD_D0_OFFSET 301 > +#define BXT_SDCARD_D1_OFFSET 302 > +#define BXT_SDCARD_D2_OFFSET 303 > +#define BXT_SDCARD_D3_OFFSET 304 > +#define BXT_SDCARD_CD_B_OFFSET 305 > +#define BXT_SDCARD_CMD_OFFSET 306 > +#define BXT_SDCARD_LVL_CLK_FB_OFFSET 307 > +#define BXT_SDCARD_LVL_CMD_DIR_OFFSET 308 > +#define BXT_SDCARD_LVL_DAT_DIR_OFFSET 309 > +#define BXT_EMMC0_STROBE_OFFSET 310 > +#define BXT_SDIO_PWR_DOWN_B_OFFSET 311 > +#define BXT_SDCARD_PWR_DOWN_B_OFFSET 312 > +#define BXT_SDCARD_LVL_SEL_OFFSET 313 > +#define BXT_SDCARD_LVL_WP_OFFSET 314 > +#define BXT_LPSS_I2C0_SDA_OFFSET 315 > +#define BXT_LPSS_I2C0_SCL_OFFSET 316 > +#define BXT_LPSS_I2C1_SDA_OFFSET 317 > +#define BXT_LPSS_I2C1_SCL_OFFSET 318 > +#define BXT_LPSS_I2C2_SDA_OFFSET 319 > +#define BXT_LPSS_I2C2_SCL_OFFSET 320 > +#define BXT_LPSS_I2C3_SDA_OFFSET 321 > +#define BXT_LPSS_I2C3_SCL_OFFSET 322 > +#define BXT_LPSS_I2C4_SDA_OFFSET 323 > +#define BXT_LPSS_I2C4_SCL_OFFSET 324 > +#define BXT_LPSS_I2C5_SDA_OFFSET 325 > +#define BXT_LPSS_I2C5_SCL_OFFSET 326 > +#define BXT_LPSS_I2C6_SDA_OFFSET 327 > +#define BXT_LPSS_I2C6_SCL_OFFSET 328 > +#define BXT_LPSS_I2C7_SDA_OFFSET 329 > +#define BXT_LPSS_I2C7_SCL_OFFSET 330 > +#define BXT_ISH_I2C0_SDA_OFFSET 331 > +#define BXT_ISH_I2C0_SCL_OFFSET 332 > +#define BXT_ISH_I2C1_SDA_OFFSET 333 > +#define BXT_ISH_I2C1_SCL_OFFSET 334 > +#define BXT_ISH_I2C2_SDA_OFFSET 335 > +#define BXT_ISH_I2C2_SCL_OFFSET 336 > +#define BXT_ISH_GPIO_0_OFFSET 337 > +#define BXT_ISH_GPIO_1_OFFSET 338 > +#define BXT_ISH_GPIO_2_OFFSET 339 > +#define BXT_ISH_GPIO_3_OFFSET 340 > +#define BXT_ISH_GPIO_4_OFFSET 341 > +#define BXT_ISH_GPIO_5_OFFSET 342 > +#define BXT_ISH_GPIO_6_OFFSET 343 > +#define BXT_ISH_GPIO_7_OFFSET 344 > +#define BXT_ISH_GPIO_8_OFFSET 345 > +#define BXT_ISH_GPIO_9_OFFSET 346 > +#define BXT_AVS_I2S1_MCLK_OFFSET 378 > +#define BXT_AVS_I2S1_BCLK_OFFSET 379 > +#define BXT_AVS_I2S1_WS_SYNC_OFFSET 380 > +#define BXT_AVS_I2S1_SDI_OFFSET 381 > +#define BXT_AVS_I2S1_SDO_OFFSET 382 > +#define BXT_AVS_M_CLK_A1_OFFSET 383 > +#define BXT_AVS_M_CLK_B1_OFFSET 384 > +#define BXT_AVS_M_DATA_1_OFFSET 385 > +#define BXT_AVS_M_CLK_AB2_OFFSET 386 > +#define BXT_AVS_M_DATA_2_OFFSET 387 > +#define BXT_AVS_I2S2_MCLK_OFFSET 388 > +#define BXT_AVS_I2S2_BCLK_OFFSET 389 > +#define BXT_AVS_I2S2_WS_SYNC_OFFSET 390 > +#define BXT_AVS_I2S2_SDI_OFFSET 391 > +#define BXT_AVS_I2S2_SDO_OFFSET 392 > +#define BXT_AVS_I2S3_BCLK_OFFSET 393 > +#define BXT_AVS_I2S3_WS_SYNC_OFFSET 394 > +#define BXT_AVS_I2S3_SDI_OFFSET 395 > +#define BXT_AVS_I2S3_SDO_OFFSET 396 > +#define BXT_AVS_I2S4_BCLK_OFFSET 397 > +#define BXT_AVS_I2S4_WS_SYNC_OFFSET 398 > +#define BXT_AVS_I2S4_SDI_OFFSET 399 > +#define BXT_AVS_I2S4_SDO_OFFSET 400 > +#define BXT_FST_SPI_CS0_B_OFFSET 402 > +#define BXT_FST_SPI_CS1_B_OFFSET 403 > +#define BXT_FST_SPI_MOSI_IO0_OFFSET 404 > +#define BXT_FST_SPI_MISO_IO1_OFFSET 405 > +#define BXT_FST_SPI_IO2_OFFSET 406 > +#define BXT_FST_SPI_IO3_OFFSET 407 > +#define BXT_FST_SPI_CLK_OFFSET 408 > +#define BXT_GP_SSP_0_CLK_OFFSET 410 > +#define BXT_GP_SSP_0_FS0_OFFSET 411 > +#define BXT_GP_SSP_0_FS1_OFFSET 412 > +#define BXT_GP_SSP_0_FS2_OFFSET 413 > +#define BXT_GP_SSP_0_RXD_OFFSET 414 > +#define BXT_GP_SSP_0_TXD_OFFSET 415 > +#define BXT_GP_SSP_1_CLK_OFFSET 416 > +#define BXT_GP_SSP_1_FS0_OFFSET 417 > +#define BXT_GP_SSP_1_FS1_OFFSET 418 > +#define BXT_GP_SSP_1_FS2_OFFSET 419 > +#define BXT_GP_SSP_1_FS3_OFFSET 420 > +#define BXT_GP_SSP_1_RXD_OFFSET 421 > +#define BXT_GP_SSP_1_TXD_OFFSET 422 > +#define BXT_GP_SSP_2_CLK_OFFSET 423 > +#define BXT_GP_SSP_2_FS0_OFFSET 424 > +#define BXT_GP_SSP_2_FS1_OFFSET 425 > +#define BXT_GP_SSP_2_FS2_OFFSET 426 > +#define BXT_GP_SSP_2_RXD_OFFSET 427 > +#define BXT_GP_SSP_2_TXD_OFFSET 428 > +#define BXT_TRACE_0_CLK_VNN_OFFSET 429 > +#define BXT_TRACE_0_DATA0_VNN_OFFSET 430 > +#define BXT_TRACE_0_DATA1_VNN_OFFSET 431 > +#define BXT_TRACE_0_DATA2_VNN_OFFSET 432 > +#define BXT_TRACE_0_DATA3_VNN_OFFSET 433 > +#define BXT_TRACE_0_DATA4_VNN_OFFSET 434 > +#define BXT_TRACE_0_DATA5_VNN_OFFSET 435 > +#define BXT_TRACE_0_DATA6_VNN_OFFSET 436 > +#define BXT_TRACE_0_DATA7_VNN_OFFSET 437 > +#define BXT_TRACE_1_CLK_VNN_OFFSET 438 > +#define BXT_TRACE_1_DATA0_VNN_OFFSET 439 > +#define BXT_TRACE_1_DATA1_VNN_OFFSET 440 > +#define BXT_TRACE_1_DATA2_VNN_OFFSET 441 > +#define BXT_TRACE_1_DATA3_VNN_OFFSET 442 > +#define BXT_TRACE_1_DATA4_VNN_OFFSET 443 > +#define BXT_TRACE_1_DATA5_VNN_OFFSET 444 > +#define BXT_TRACE_1_DATA6_VNN_OFFSET 445 > +#define BXT_TRACE_1_DATA7_VNN_OFFSET 446 > +#define BXT_TRACE_2_CLK_VNN_OFFSET 447 > +#define BXT_TRACE_2_DATA0_VNN_OFFSET 448 > +#define BXT_TRACE_2_DATA1_VNN_OFFSET 449 > +#define BXT_TRACE_2_DATA2_VNN_OFFSET 450 > +#define BXT_TRACE_2_DATA3_VNN_OFFSET 451 > +#define BXT_TRACE_2_DATA4_VNN_OFFSET 452 > +#define BXT_TRACE_2_DATA5_VNN_OFFSET 453 > +#define BXT_TRACE_2_DATA6_VNN_OFFSET 454 > +#define BXT_TRACE_2_DATA7_VNN_OFFSET 455 > +#define BXT_TRIGOUT_0_OFFSET 456 > +#define BXT_TRIGOUT_1_OFFSET 457 > +#define BXT_TRIGIN_0_OFFSET 458 > +#define BXT_SEC_TCK_OFFSET 459 > +#define BXT_SEC_TDI_OFFSET 460 > +#define BXT_SEC_TMS_OFFSET 461 > +#define BXT_SEC_TDO_OFFSET 462 > +#define BXT_PWM0_OFFSET 463 > +#define BXT_PWM1_OFFSET 464 > +#define BXT_PWM2_OFFSET 465 > +#define BXT_PWM3_OFFSET 466 > +#define BXT_LPSS_UART0_RXD_OFFSET 467 > +#define BXT_LPSS_UART0_TXD_OFFSET 468 > +#define BXT_LPSS_UART0_RTS_B_OFFSET 469 > +#define BXT_LPSS_UART0_CTS_B_OFFSET 470 > +#define BXT_LPSS_UART1_RXD_OFFSET 471 > +#define BXT_LPSS_UART1_TXD_OFFSET 472 > +#define BXT_LPSS_UART1_RTS_B_OFFSET 473 > +#define BXT_LPSS_UART1_CTS_B_OFFSET 474 > +#define BXT_LPSS_UART2_RXD_OFFSET 475 > +#define BXT_LPSS_UART2_TXD_OFFSET 476 > +#define BXT_LPSS_UART2_RTS_B_OFFSET 477 > +#define BXT_LPSS_UART2_CTS_B_OFFSET 478 > +#define BXT_ISH_UART0_RXD_OFFSET 479 > +#define BXT_ISH_UART0_TXD_OFFSET 480 > +#define BXT_ISH_UART0_RTS_B_OFFSET 481 > +#define BXT_ISH_UART0_CTS_B_OFFSET 482 > +#define BXT_ISH_UART1_RXD_OFFSET 483 > +#define BXT_ISH_UART1_TXD_OFFSET 484 > +#define BXT_ISH_UART1_RTS_B_OFFSET 485 > +#define BXT_ISH_UART1_CTS_B_OFFSET 486 > +#define BXT_ISH_UART2_RXD_OFFSET 487 > +#define BXT_ISH_UART2_TXD_OFFSET 488 > +#define BXT_ISH_UART2_RTS_B_OFFSET 489 > +#define BXT_ISH_UART2_CTS_B_OFFSET 490 > +#define BXT_GP_CAMERASB00_OFFSET 491 > +#define BXT_GP_CAMERASB01_OFFSET 492 > +#define BXT_GP_CAMERASB02_OFFSET 493 > +#define BXT_GP_CAMERASB03_OFFSET 494 > +#define BXT_GP_CAMERASB04_OFFSET 495 > +#define BXT_GP_CAMERASB05_OFFSET 496 > +#define BXT_GP_CAMERASB06_OFFSET 497 > +#define BXT_GP_CAMERASB07_OFFSET 498 > +#define BXT_GP_CAMERASB08_OFFSET 499 > +#define BXT_GP_CAMERASB09_OFFSET 500 > +#define BXT_GP_CAMERASB10_OFFSET 501 > +#define BXT_GP_CAMERASB11_OFFSET 502 > + > +struct bxt_gpio_map { > + u8 gpio_index; > + u16 gpio_number; > + bool requested; > +}; > + > +/* XXX: take out everything that is not related to DSI display */ > +static struct bxt_gpio_map bxt_gpio_table[] = { > + { BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET }, > + { BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET }, > + { BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET }, > + { BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET }, > + { BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET }, > + { BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET }, > + { BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET }, > + { BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET }, > + { BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET }, > + { BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET }, > + { BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET }, > + { BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET }, > + { BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET }, > + { BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET }, > + { BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET }, > + { BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET }, > + { BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET }, > + { BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET }, > + { BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET }, > + { BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET }, > + { BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET }, > + { BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET }, > + { BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET }, > + { BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET }, > + { BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET }, > + { BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET }, > + { BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET }, > + { BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET }, > + { BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET }, > + { BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET }, > + { BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET }, > + { BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET }, > + { BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET }, > + { BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET }, > + { BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET }, > + { BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET }, > + { BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET }, > + { BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET }, > + { BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET }, > + { BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET }, > + { BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET }, > + { BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET }, > + { BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET }, > + { BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET }, > + { BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET }, > + { BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET }, > + { BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET }, > + { BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET }, > + { BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET }, > + { BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET }, > + { BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET }, > + { BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET }, > + { BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET }, > + { BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET }, > + { BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET }, > + { BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET }, > + { BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET }, > + { BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET }, > + { BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET }, > + { BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET }, > + { BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET }, > + { BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET }, > + { BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET }, > + { BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET }, > + { BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET }, > + { BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET }, > + { BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET }, > + { BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET }, > + { BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET }, > + { BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET }, > + { BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET }, > + { BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET }, > + { BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET }, > + { BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET }, > + { BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET }, > + { BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET }, > + { BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET }, > + { BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET }, > + { BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET }, > + { BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET }, > + { BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET }, > + { BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET }, > + { BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET }, > + { BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET }, > + { BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET }, > + { BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET }, > + { BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET }, > + { BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET }, > + { BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET }, > + { BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET }, > + { BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET }, > + { BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET }, > + { BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET }, > + { BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET }, > + { BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET }, > + { BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET }, > + { BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET }, > + { BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET }, > + { BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET }, > + { BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET }, > + { BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET }, > + { BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET }, > + { BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET }, > + { BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET }, > + { BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET }, > + { BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET }, > + { BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET }, > + { BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET }, > + { BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET }, > + { BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET }, > + { BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET }, > + { BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET }, > + { BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET }, > + { BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET }, > + { BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET }, > + { BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET }, > + { BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET }, > + { BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET }, > + { BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET }, > + { BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET }, > + { BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET }, > + { BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET }, > + { BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET }, > + { BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET }, > + { BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET }, > + { BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET }, > + { BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET }, > + { BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET }, > + { BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET }, > + { BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET }, > + { BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET }, > + { BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET }, > + { BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET }, > + { BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET }, > + { BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET }, > + { BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET }, > + { BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET }, > + { BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET }, > + { BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET }, > + { BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET }, > + { BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET }, > + { BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET }, > + { BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET }, > + { BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET }, > + { BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET }, > + { BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET }, > + { BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET }, > + { BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET }, > + { BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET }, > + { BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET }, > + { BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET }, > + { BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET }, > + { BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET }, > + { BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET }, > + { BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET }, > + { BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET }, > + { BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET }, > + { BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET }, > + { BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET }, > + { BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET }, > + { BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET }, > + { BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET }, > + { BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET }, > + { BXT_PWM0_PIN, BXT_PWM0_OFFSET }, > + { BXT_PWM1_PIN, BXT_PWM1_OFFSET }, > + { BXT_PWM2_PIN, BXT_PWM2_OFFSET }, > + { BXT_PWM3_PIN, BXT_PWM3_OFFSET }, > + { BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET }, > + { BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET }, > + { BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET }, > + { BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET }, > + { BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET }, > + { BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET }, > + { BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET }, > + { BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET }, > + { BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET }, > + { BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET }, > + { BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET }, > + { BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET }, > + { BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET }, > + { BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET }, > + { BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET }, > + { BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET }, > + { BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET }, > + { BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET }, > + { BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET }, > + { BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET }, > + { BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET }, > + { BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET }, > + { BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET }, > + { BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET }, > + { BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET }, > + { BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET }, > + { BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET }, > + { BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET }, > + { BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET }, > + { BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET }, > + { BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET }, > + { BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET }, > + { BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET }, > + { BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET }, > + { BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET }, > + { BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET }, > +}; > + > static inline enum port intel_dsi_seq_port_to_port(u8 port) > { > return port ? PORT_C : PORT_A; > @@ -305,6 +936,40 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, > mutex_unlock(&dev_priv->sb_lock); > } > > +static void bxt_exec_gpio(struct drm_i915_private *dev_priv, > + u8 gpio_source, u8 gpio_index, u8 action) > +{ > + struct bxt_gpio_map *map = NULL; > + unsigned int gpio; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(bxt_gpio_table); i++) { > + if (gpio_index == bxt_gpio_table[i].gpio_index) { > + map = &bxt_gpio_table[i]; > + break; > + } > + } > + > + if (!map) { > + DRM_DEBUG_KMS("invalid gpio index %u\n", gpio_index); > + return; > + } > + > + gpio = map->gpio_number; > + > + if (!map->requested) { > + int ret = devm_gpio_request_one(dev_priv->dev->dev, gpio, > + GPIOF_DIR_OUT, "MIPI DSI"); > + if (ret) { > + DRM_ERROR("unable to request GPIO %u (%d)\n", gpio, ret); > + return; > + } > + map->requested = true; > + } > + > + gpio_set_value(gpio, action); > +} > + > static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > { > struct drm_device *dev = intel_dsi->base.base.dev; > @@ -330,7 +995,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) > else if (IS_CHERRYVIEW(dev_priv)) > chv_exec_gpio(dev_priv, gpio_source, gpio_index, action); > else > - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); > + bxt_exec_gpio(dev_priv, gpio_source, gpio_index, action); > > return data; > } > -- > 2.1.4 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915/dsi: improved gpio element support for vlv/chv/bxt 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula ` (8 preceding siblings ...) 2016-03-18 11:11 ` [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support Jani Nikula @ 2016-03-21 8:52 ` Patchwork 9 siblings, 0 replies; 23+ messages in thread From: Patchwork @ 2016-03-21 8:52 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsi: improved gpio element support for vlv/chv/bxt URL : https://patchwork.freedesktop.org/series/4625/ State : warning == Summary == Series 4625v1 drm/i915/dsi: improved gpio element support for vlv/chv/bxt http://patchwork.freedesktop.org/api/1.0/series/4625/revisions/1/mbox/ Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (bdw-ultra) Subgroup basic-flip-vs-wf_vblank: pass -> DMESG-WARN (snb-x220t) fail -> PASS (byt-nuc) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (hsw-gt2) Test pm_rpm: Subgroup basic-rte: pass -> DMESG-WARN (bsw-nuc-2) bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultra total:194 pass:172 dwarn:1 dfail:0 fail:0 skip:21 bsw-nuc-2 total:194 pass:155 dwarn:2 dfail:0 fail:0 skip:37 byt-nuc total:194 pass:159 dwarn:0 dfail:0 fail:0 skip:35 hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22 hsw-gt2 total:105 pass:96 dwarn:1 dfail:0 fail:0 skip:7 ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63 ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25 skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11 snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34 snb-x220t total:194 pass:158 dwarn:2 dfail:0 fail:1 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1644/ e7a7673e9840fe8b50a5a2894c75565ec7858a00 drm-intel-nightly: 2016y-03m-19d-10h-09m-53s UTC integration manifest 998e9391c6c2e25f777b9a7b7b46423e32f0f39e drm/i915/bxt: add bxt dsi gpio element support 546396ae105cee65c686a9940719267c8e12af69 drm/i915/dsi: add support for gpio elements on CHV 63b8abef413bc1921ecd27264278f72c95a38369 drm/i915/chv: add more IOSF port definitions 10995d3a6093c058a5716b312977d115817d4962 drm/i915/dsi: add support for sequence block v3 gpio for VLV 3925e0e04b1f5b0596c990667c29c5be64b834e0 drm/i915/dsi: abstract VLV gpio element execution to a separate function 8c77772d023516b1e0edb3bd8991dbfdecfc1580 drm/i915/dsi: add gpio indexes to the gpio table cdebf626fe262fbf2ac4354da0711023a72a8109 drm/i915/dsi: clean up vlv gpio table and definitions ed54f96a117804b66d4908adfffc6d5ef1772671 drm/i915/dsi: add support for DSI sequence block v2 gpio element 0244a22ec36ecf44b51f9a5d685022fdff5b3843 drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-04-05 7:35 UTC | newest] Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-03-18 11:11 [PATCH v2 0/9] drm/i915/dsi: improved gpio element support for vlv/chv/bxt Jani Nikula 2016-03-18 11:11 ` [PATCH v2 1/9] drm/i915/dsi: refer to gpio index instead of gpio to avoid confusion Jani Nikula 2016-03-24 11:57 ` Mika Kahola 2016-04-01 11:53 ` Jani Nikula 2016-03-18 11:11 ` [PATCH v2 2/9] drm/i915/dsi: add support for DSI sequence block v2 gpio element Jani Nikula 2016-04-04 16:19 ` Ville Syrjälä 2016-04-05 7:33 ` Jani Nikula 2016-03-18 11:11 ` [PATCH v2 3/9] drm/i915/dsi: clean up vlv gpio table and definitions Jani Nikula 2016-04-04 17:07 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 4/9] drm/i915/dsi: add gpio indexes to the gpio table Jani Nikula 2016-04-04 17:37 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 5/9] drm/i915/dsi: abstract VLV gpio element execution to a separate function Jani Nikula 2016-03-18 11:11 ` [PATCH v2 6/9] drm/i915/dsi: add support for sequence block v3 gpio for VLV Jani Nikula 2016-03-18 11:11 ` [PATCH v2 7/9] drm/i915/chv: add more IOSF port definitions Jani Nikula 2016-04-04 17:43 ` Ville Syrjälä 2016-04-05 7:34 ` Jani Nikula 2016-03-18 11:11 ` [PATCH v2 8/9] drm/i915/dsi: add support for gpio elements on CHV Jani Nikula 2016-04-04 18:11 ` Ville Syrjälä 2016-03-18 11:11 ` [PATCH v2 9/9] drm/i915/bxt: add bxt dsi gpio element support Jani Nikula 2016-03-23 10:55 ` Mika Kahola 2016-03-23 11:19 ` Jani Nikula 2016-04-04 17:46 ` Ville Syrjälä 2016-03-21 8:52 ` ✗ Fi.CI.BAT: warning for drm/i915/dsi: improved gpio element support for vlv/chv/bxt Patchwork
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