* [PATCH 0/3] edram size calculation @ 2016-04-08 11:54 Mika Kuoppala 2016-04-08 11:54 ` [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ Mika Kuoppala ` (3 more replies) 0 siblings, 4 replies; 10+ messages in thread From: Mika Kuoppala @ 2016-04-08 11:54 UTC (permalink / raw) To: intel-gfx The skl I have reported wrong amount in dmesg. Mika Kuoppala (3): drm/i915: Don't program eLLC IDI hash mask for gen9+ drm/i915: Store and use edram capabilities drm/i915: Calculate edram size drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-- drivers/gpu/drm/i915/i915_drv.h | 7 +++-- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 5 +++- drivers/gpu/drm/i915/intel_uncore.c | 52 ++++++++++++++++++++++++++++--------- 6 files changed, 55 insertions(+), 19 deletions(-) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ 2016-04-08 11:54 [PATCH 0/3] edram size calculation Mika Kuoppala @ 2016-04-08 11:54 ` Mika Kuoppala 2016-04-08 12:08 ` Chris Wilson 2016-04-08 11:54 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: Mika Kuoppala @ 2016-04-08 11:54 UTC (permalink / raw) To: intel-gfx For gen9 onwards, eDRAM is a true memory side cache. So there is no need to program idi has mask as it is for eLLC only. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5a65a7663b88..71db5ca04483 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4841,7 +4841,7 @@ i915_gem_init_hw(struct drm_device *dev) /* Double layer security blanket, see i915_gem_init() */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - if (dev_priv->ellc_size) + if (dev_priv->ellc_size && INTEL_INFO(dev)->gen < 9) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev)) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ 2016-04-08 11:54 ` [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ Mika Kuoppala @ 2016-04-08 12:08 ` Chris Wilson 2016-04-13 9:57 ` Matthew Auld 0 siblings, 1 reply; 10+ messages in thread From: Chris Wilson @ 2016-04-08 12:08 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Fri, Apr 08, 2016 at 02:54:03PM +0300, Mika Kuoppala wrote: > For gen9 onwards, eDRAM is a true memory side cache. So > there is no need to program idi has mask as it is for eLLC > only. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 5a65a7663b88..71db5ca04483 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4841,7 +4841,7 @@ i915_gem_init_hw(struct drm_device *dev) > /* Double layer security blanket, see i915_gem_init() */ > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > - if (dev_priv->ellc_size) > + if (dev_priv->ellc_size && INTEL_INFO(dev)->gen < 9) INTEL_GEN(dev_priv) < 9 -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ 2016-04-08 12:08 ` Chris Wilson @ 2016-04-13 9:57 ` Matthew Auld 0 siblings, 0 replies; 10+ messages in thread From: Matthew Auld @ 2016-04-13 9:57 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx Seems to be in-line with the spec, so with Chris' comment addressed and s/idi has mask/idi hash mask/: Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Store and use edram capabilities 2016-04-08 11:54 [PATCH 0/3] edram size calculation Mika Kuoppala 2016-04-08 11:54 ` [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ Mika Kuoppala @ 2016-04-08 11:54 ` Mika Kuoppala 2016-04-08 12:10 ` Chris Wilson 2016-04-08 11:54 ` [PATCH 3/3] drm/i915: Calculate edram size Mika Kuoppala 2016-04-08 12:58 ` ✓ Fi.CI.BAT: success for edram size calculation Patchwork 3 siblings, 1 reply; 10+ messages in thread From: Mika Kuoppala @ 2016-04-08 11:54 UTC (permalink / raw) To: intel-gfx Store the edram capabilities instead of only the size of edram. This is preparatory patch to allow edram size calculation based on edram capability bits for gen9+. With gen9 the edram is behind llc and is a separate entity. With hsw/bdw it was more of a victim cache for LLC so the name 'eLLC' might be warranted. Regardless, rename all mentions of eLLC to EDRAM to clear the confusion. v2: return bytes for edram size (Chris) s/eLLC/eDRAM in output if we are gen > 8 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-- drivers/gpu/drm/i915/i915_drv.h | 7 +++++-- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 39 +++++++++++++++++++++++++------------ 6 files changed, 39 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ebbf4e400684..dc9a987acff6 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2402,10 +2402,11 @@ static int i915_llc(struct seq_file *m, void *data) struct drm_info_node *node = m->private; struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; + const bool edram = INTEL_INFO(dev_priv)->gen > 8; - /* Size calculation for LLC is a bit of a pain. Ignore for now. */ seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); - seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); + seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", + intel_uncore_edram_size(dev_priv)/1024/1024); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a93e5dd4fa9a..80ae4c7307d8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1863,7 +1863,7 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; /* Cannot be determined by PCIID. You must always read a register. */ - size_t ellc_size; + u32 edram_cap; /* gen6+ rps state */ struct intel_gen6_power_mgmt rps; @@ -2616,8 +2616,9 @@ struct drm_i915_cmd_table { #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) +#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED) #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ - __I915__(dev)->ellc_size) + HAS_EDRAM(dev)) #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) @@ -2794,6 +2795,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, enum forcewake_domains domains); void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, enum forcewake_domains domains); +u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); + void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); static inline bool intel_vgpu_active(struct drm_device *dev) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 71db5ca04483..7310da8f08b9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4841,7 +4841,7 @@ i915_gem_init_hw(struct drm_device *dev) /* Double layer security blanket, see i915_gem_init() */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - if (dev_priv->ellc_size && INTEL_INFO(dev)->gen < 9) + if (HAS_EDRAM(dev) && INTEL_INFO(dev)->gen < 9) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev)) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index da6e3a533095..75c2109dfc6c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3172,7 +3172,8 @@ int i915_ggtt_init_hw(struct drm_device *dev) } else if (INTEL_INFO(dev)->gen < 8) { ggtt->probe = gen6_gmch_probe; ggtt->base.cleanup = gen6_gmch_remove; - if (IS_HASWELL(dev) && dev_priv->ellc_size) + + if (HAS_EDRAM(dev)) ggtt->base.pte_encode = iris_pte_encode; else if (IS_HASWELL(dev)) ggtt->base.pte_encode = hsw_pte_encode; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0744759170d3..3bd52185b946 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6870,7 +6870,7 @@ enum skl_disp_power_wells { #define HSW_IDICR _MMIO(0x9008) #define IDIHASHMSK(x) (((x) & 0x3f) << 16) -#define HSW_EDRAM_PRESENT _MMIO(0x120010) +#define HSW_EDRAM_CAP _MMIO(0x120010) #define EDRAM_ENABLED 0x1 #define GEN6_UCGCTL1 _MMIO(0x9400) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index ac2ac07b505b..2cd975856eeb 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -310,21 +310,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void intel_uncore_ellc_detect(struct drm_device *dev) +u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; + if (!HAS_EDRAM(dev_priv)) + return 0; + + /* The docs do not explain exactly how the calculation can be + * made. It is somewhat guessable, but for now, it's always + * 128MB. + */ + + return 128 * 1024 * 1024; +} - if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || - INTEL_INFO(dev)->gen >= 9) && - (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { - /* The docs do not explain exactly how the calculation can be - * made. It is somewhat guessable, but for now, it's always - * 128MB. - * NB: We can't write IDICR yet because we do not have gt funcs +static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) +{ + if (IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv) || + INTEL_INFO(dev_priv)->gen >= 9) { + dev_priv->edram_cap = __raw_i915_read32(dev_priv, + HSW_EDRAM_CAP); + + /* NB: We can't write IDICR yet because we do not have gt funcs * set up */ - dev_priv->ellc_size = 128; - DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); + } else { + dev_priv->edram_cap = 0; } + + if (HAS_EDRAM(dev_priv)) + DRM_INFO("Found %lluMB of eDRAM\n", + intel_uncore_edram_size(dev_priv) / (1024 * 1024)); } static bool @@ -1253,7 +1268,7 @@ void intel_uncore_init(struct drm_device *dev) i915_check_vgpu(dev); - intel_uncore_ellc_detect(dev); + intel_uncore_edram_detect(dev_priv); intel_uncore_fw_domains_init(dev); __intel_uncore_early_sanitize(dev, false); -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915: Store and use edram capabilities 2016-04-08 11:54 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala @ 2016-04-08 12:10 ` Chris Wilson 0 siblings, 0 replies; 10+ messages in thread From: Chris Wilson @ 2016-04-08 12:10 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx On Fri, Apr 08, 2016 at 02:54:04PM +0300, Mika Kuoppala wrote: > Store the edram capabilities instead of only the size of > edram. This is preparatory patch to allow edram size calculation > based on edram capability bits for gen9+. With gen9 the > edram is behind llc and is a separate entity. With hsw/bdw > it was more of a victim cache for LLC so the name 'eLLC' might > be warranted. Regardless, rename all mentions of eLLC to EDRAM to > clear the confusion. > > v2: return bytes for edram size (Chris) > s/eLLC/eDRAM in output if we are gen > 8 > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> With INTEL_GEN where introduced Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915: Calculate edram size 2016-04-08 11:54 [PATCH 0/3] edram size calculation Mika Kuoppala 2016-04-08 11:54 ` [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ Mika Kuoppala 2016-04-08 11:54 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala @ 2016-04-08 11:54 ` Mika Kuoppala 2016-04-13 10:36 ` Matthew Auld 2016-04-08 12:58 ` ✓ Fi.CI.BAT: success for edram size calculation Patchwork 3 siblings, 1 reply; 10+ messages in thread From: Mika Kuoppala @ 2016-04-08 11:54 UTC (permalink / raw) To: intel-gfx With gen9+ the edram capabilities are defined so that we can calculate the edram (ellc) size accordingly. Note that there are undefined combinations for some subset of edram capability bits. Return the closest size for undefined indexes. Even if we get it wrong with beginning of future gen enabling, the size information is currently only used for boot message and in debugfs entry. v2: Use function instead of hard to read macro (Daniel) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_uncore.c | 21 +++++++++++++++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3bd52185b946..7fa3598a15e7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6872,6 +6872,9 @@ enum skl_disp_power_wells { #define IDIHASHMSK(x) (((x) & 0x3f) << 16) #define HSW_EDRAM_CAP _MMIO(0x120010) #define EDRAM_ENABLED 0x1 +#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) +#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) +#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) #define GEN6_UCGCTL1 _MMIO(0x9400) # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 2cd975856eeb..2798295f6e51 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -310,17 +310,30 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +static u64 gen9_edram_size(struct drm_i915_private *dev_priv) +{ + const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; + const unsigned int sets[4] = { 1, 1, 2, 2 }; + const u32 cap = dev_priv->edram_cap; + + return EDRAM_NUM_BANKS(cap) * + ways[EDRAM_WAYS_IDX(cap)] * + sets[EDRAM_SETS_IDX(cap)] * + 1024 * 1024; +} + u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) { if (!HAS_EDRAM(dev_priv)) return 0; - /* The docs do not explain exactly how the calculation can be - * made. It is somewhat guessable, but for now, it's always - * 128MB. + /* The needed capability bits for size calculation + * are not there with pre gen9 so return 128MB always. */ + if (INTEL_INFO(dev_priv)->gen < 9) + return 128 * 1024 * 1024; - return 128 * 1024 * 1024; + return gen9_edram_size(dev_priv); } static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Calculate edram size 2016-04-08 11:54 ` [PATCH 3/3] drm/i915: Calculate edram size Mika Kuoppala @ 2016-04-13 10:36 ` Matthew Auld 0 siblings, 0 replies; 10+ messages in thread From: Matthew Auld @ 2016-04-13 10:36 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx Looks good, so with s/INTEL_INFO/INTEL_GEN/: Reviewed-by: Matthew Auld <matthew.auld@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for edram size calculation 2016-04-08 11:54 [PATCH 0/3] edram size calculation Mika Kuoppala ` (2 preceding siblings ...) 2016-04-08 11:54 ` [PATCH 3/3] drm/i915: Calculate edram size Mika Kuoppala @ 2016-04-08 12:58 ` Patchwork 3 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2016-04-08 12:58 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx == Series Details == Series: edram size calculation URL : https://patchwork.freedesktop.org/series/5457/ State : success == Summary == Series 5457v1 edram size calculation http://patchwork.freedesktop.org/api/1.0/series/5457/revisions/1/mbox/ Test gem_exec_basic: Subgroup basic-bsd: dmesg-warn -> PASS (bsw-nuc-2) Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (bsw-nuc-2) Test gem_sync: Subgroup basic-bsd: dmesg-warn -> PASS (bsw-nuc-2) Test pm_rpm: Subgroup basic-rte: dmesg-warn -> PASS (bsw-nuc-2) bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12 bsw-nuc-2 total:196 pass:159 dwarn:0 dfail:0 fail:0 skip:37 byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35 hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22 hsw-gt2 total:196 pass:179 dwarn:0 dfail:0 fail:0 skip:17 ilk-hp8440p total:196 pass:132 dwarn:0 dfail:0 fail:0 skip:64 ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25 skl-i7k-2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23 skl-nuci5 total:196 pass:185 dwarn:0 dfail:0 fail:0 skip:11 snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34 snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1843/ 949884a57b51aa158e3ae9afe1f08130cdb7a3ef drm-intel-nightly: 2016y-04m-08d-10h-45m-28s UTC integration manifest 2708ebba186b507cd7e6f9b745d9e38f4c7b67c0 drm/i915: Calculate edram size 1350456345505fe31d7b60b2ad0ddce6de9bdcf2 drm/i915: Store and use edram capabilities 7eb48c897775f11f3b55777567a424a4eefcec34 drm/i915: Don't program eLLC IDI hash mask for gen9+ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [CI-RUN PATCH 0/3] ci-run of edram size patches @ 2016-04-13 14:26 Mika Kuoppala 2016-04-13 14:26 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala 0 siblings, 1 reply; 10+ messages in thread From: Mika Kuoppala @ 2016-04-13 14:26 UTC (permalink / raw) To: intel-gfx Mika Kuoppala (3): drm/i915: Don't program eLLC IDI hash mask for gen9+ drm/i915: Store and use edram capabilities drm/i915: Calculate edram size drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-- drivers/gpu/drm/i915/i915_drv.h | 7 +++-- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 5 +++- drivers/gpu/drm/i915/intel_uncore.c | 52 ++++++++++++++++++++++++++++--------- 6 files changed, 55 insertions(+), 19 deletions(-) -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Store and use edram capabilities 2016-04-13 14:26 [CI-RUN PATCH 0/3] ci-run of edram size patches Mika Kuoppala @ 2016-04-13 14:26 ` Mika Kuoppala 0 siblings, 0 replies; 10+ messages in thread From: Mika Kuoppala @ 2016-04-13 14:26 UTC (permalink / raw) To: intel-gfx Store the edram capabilities instead of only the size of edram. This is preparatory patch to allow edram size calculation based on edram capability bits for gen9+. With gen9 the edram is behind llc and is a separate entity. With hsw/bdw it was more of a victim cache for LLC so the name 'eLLC' might be warranted. Regardless, rename all mentions of eLLC to EDRAM to clear the confusion. v2: return bytes for edram size (Chris) s/eLLC/eDRAM in output if we are gen > 8 v3: rebase, INTEL_GEN (Chris) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-- drivers/gpu/drm/i915/i915_drv.h | 7 +++++-- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 39 +++++++++++++++++++++++++------------ 6 files changed, 39 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2d11b4948a74..16afaee10b02 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2404,10 +2404,11 @@ static int i915_llc(struct seq_file *m, void *data) struct drm_info_node *node = m->private; struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; + const bool edram = INTEL_GEN(dev_priv) > 8; - /* Size calculation for LLC is a bit of a pain. Ignore for now. */ seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); - seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); + seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", + intel_uncore_edram_size(dev_priv)/1024/1024); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d1e6e580a92d..986281ebc224 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1873,7 +1873,7 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; /* Cannot be determined by PCIID. You must always read a register. */ - size_t ellc_size; + u32 edram_cap; /* gen6+ rps state */ struct intel_gen6_power_mgmt rps; @@ -2624,8 +2624,9 @@ struct drm_i915_cmd_table { #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) +#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED) #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ - __I915__(dev)->ellc_size) + HAS_EDRAM(dev)) #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) @@ -2803,6 +2804,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, enum forcewake_domains domains); void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, enum forcewake_domains domains); +u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); + void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); static inline bool intel_vgpu_active(struct drm_device *dev) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3e1222b57fee..2843813290d8 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4892,7 +4892,7 @@ i915_gem_init_hw(struct drm_device *dev) /* Double layer security blanket, see i915_gem_init() */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - if (dev_priv->ellc_size && INTEL_GEN(dev_priv) < 9) + if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev)) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c5cb04907525..9f165feb54ae 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3172,7 +3172,8 @@ int i915_ggtt_init_hw(struct drm_device *dev) } else if (INTEL_INFO(dev)->gen < 8) { ggtt->probe = gen6_gmch_probe; ggtt->base.cleanup = gen6_gmch_remove; - if (IS_HASWELL(dev) && dev_priv->ellc_size) + + if (HAS_EDRAM(dev)) ggtt->base.pte_encode = iris_pte_encode; else if (IS_HASWELL(dev)) ggtt->base.pte_encode = hsw_pte_encode; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cea5a390d8c9..bedce95aa046 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6882,7 +6882,7 @@ enum skl_disp_power_wells { #define HSW_IDICR _MMIO(0x9008) #define IDIHASHMSK(x) (((x) & 0x3f) << 16) -#define HSW_EDRAM_PRESENT _MMIO(0x120010) +#define HSW_EDRAM_CAP _MMIO(0x120010) #define EDRAM_ENABLED 0x1 #define GEN6_UCGCTL1 _MMIO(0x9400) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 144700cd360b..89cda6342ce2 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -315,21 +315,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void intel_uncore_ellc_detect(struct drm_device *dev) +u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; + if (!HAS_EDRAM(dev_priv)) + return 0; + + /* The docs do not explain exactly how the calculation can be + * made. It is somewhat guessable, but for now, it's always + * 128MB. + */ + + return 128 * 1024 * 1024; +} + +static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) +{ + if (IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv) || + INTEL_GEN(dev_priv) >= 9) { + dev_priv->edram_cap = __raw_i915_read32(dev_priv, + HSW_EDRAM_CAP); - if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || - INTEL_INFO(dev)->gen >= 9) && - (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { - /* The docs do not explain exactly how the calculation can be - * made. It is somewhat guessable, but for now, it's always - * 128MB. - * NB: We can't write IDICR yet because we do not have gt funcs + /* NB: We can't write IDICR yet because we do not have gt funcs * set up */ - dev_priv->ellc_size = 128; - DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); + } else { + dev_priv->edram_cap = 0; } + + if (HAS_EDRAM(dev_priv)) + DRM_INFO("Found %lluMB of eDRAM\n", + intel_uncore_edram_size(dev_priv) / (1024 * 1024)); } static bool @@ -1301,7 +1316,7 @@ void intel_uncore_init(struct drm_device *dev) i915_check_vgpu(dev); - intel_uncore_ellc_detect(dev); + intel_uncore_edram_detect(dev_priv); intel_uncore_fw_domains_init(dev); __intel_uncore_early_sanitize(dev, false); -- 2.5.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-04-13 14:26 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-04-08 11:54 [PATCH 0/3] edram size calculation Mika Kuoppala 2016-04-08 11:54 ` [PATCH 1/3] drm/i915: Don't program eLLC IDI hash mask for gen9+ Mika Kuoppala 2016-04-08 12:08 ` Chris Wilson 2016-04-13 9:57 ` Matthew Auld 2016-04-08 11:54 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala 2016-04-08 12:10 ` Chris Wilson 2016-04-08 11:54 ` [PATCH 3/3] drm/i915: Calculate edram size Mika Kuoppala 2016-04-13 10:36 ` Matthew Auld 2016-04-08 12:58 ` ✓ Fi.CI.BAT: success for edram size calculation Patchwork 2016-04-13 14:26 [CI-RUN PATCH 0/3] ci-run of edram size patches Mika Kuoppala 2016-04-13 14:26 ` [PATCH 2/3] drm/i915: Store and use edram capabilities Mika Kuoppala
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