[PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM

[PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM

[Imre Deak]

This patchset works around/fixes a few DMC and PHY issues and enables
display power well support and runtime PM.

CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
CC: Matt Ropert <matthew.d.roper@intel.com>

Imre Deak (16):
  drm/i915/bxt: Reject DMC firmware versions with known bugs
  drm/i915/bxt: Fix GRC code register field definitions
  drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
  drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR
  drm/i915/gen9: Make power well disabling synchronous
  drm/i915/gen9: Fix DMC/DC state asserts
  drm/i915/bxt: Suspend power domains during suspend-to-idle
  drm/i915/skl: Unexport skl_pw1_misc_io_init
  drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
  drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
  drm/i915/bxt: Don't toggle power well 1 on-demand
  drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
  drm/i915/bxt: Don't reprogram an already enabled DDI PHY
  drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
  Revert "drm/i915/bxt: Disable power well support"
  drm/i915/bxt: Enable runtime PM

 drivers/gpu/drm/i915/i915_drv.c         |  25 +---
 drivers/gpu/drm/i915/i915_drv.h         |   3 +-
 drivers/gpu/drm/i915/i915_reg.h         |   6 +-
 drivers/gpu/drm/i915/intel_csr.c        |  20 ++-
 drivers/gpu/drm/i915/intel_ddi.c        | 182 +++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c    |  62 +++++----
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |   5 +-
 drivers/gpu/drm/i915/intel_drv.h        |  14 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 217 +++++++++++++++++++++-----------
 9 files changed, 384 insertions(+), 150 deletions(-)

-- 
2.5.0

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[PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs

[Imre Deak]

DMC version 1.06 has a known bug, where the firmware polls forever for a port
PLL to lock, if the PLL was disabled when entering DC5. Version 1.07 fixes
this, so make that the minimum required version on BXT.

CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 3f57cb9..d57b00e 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -50,6 +50,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
 #define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)
+#define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
 
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
@@ -281,6 +282,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 	uint32_t i;
 	uint32_t *dmc_payload;
+	uint32_t required_min_version;
 
 	if (!fw)
 		return NULL;
@@ -296,15 +298,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 
 	csr->version = css_header->version;
 
-	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
-	    csr->version < SKL_CSR_VERSION_REQUIRED) {
-		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
+	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+		required_min_version = SKL_CSR_VERSION_REQUIRED;
+	} else if (IS_BROXTON(dev_priv)) {
+		required_min_version = BXT_CSR_VERSION_REQUIRED;
+	} else {
+		MISSING_CASE(INTEL_REVID(dev_priv));
+		required_min_version = 0;
+	}
+
+	if (csr->version < required_min_version) {
+		DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
 			 " please upgrade to v%u.%u or later"
 			   " [" FIRMWARE_URL "].\n",
 			 CSR_VERSION_MAJOR(csr->version),
 			 CSR_VERSION_MINOR(csr->version),
-			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
-			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
+			 CSR_VERSION_MAJOR(required_min_version),
+			 CSR_VERSION_MINOR(required_min_version));
 		return NULL;
 	}
 
-- 
2.5.0

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[PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions

[Imre Deak]

This has been corrected in BSpec quite some time ago, but we missed it
somehow. The wrong field definitions resulted in configuring PHY0 with
an incorrect GRC value.

CC: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6df3c59..f4a91bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1373,10 +1373,10 @@ enum skl_disp_power_wells {
  * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
  * after testing.
  */
-#define   GRC_CODE_SHIFT		23
-#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
+#define   GRC_CODE_SHIFT		24
+#define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
 #define   GRC_CODE_FAST_SHIFT		16
-#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
+#define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
 #define   GRC_CODE_SLOW_SHIFT		8
 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
 #define   GRC_CODE_NOM_MASK		0xFF
-- 
2.5.0

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[PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[Imre Deak]

This register is read-only, so we have never actually set
OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
comment about this. I filed a specification update request to clarify
this there.

CC: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>

---

[ Art, CC'ing you in case you know if this would have an effect on
  anything. ]
---
 drivers/gpu/drm/i915/intel_ddi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2758622..f91306e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 	 * enabled.
 	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
 	 * power down the second channel on PHY0 as well.
+	 *
+	 * FIXME: Clarify programming of the following, the register is
+	 * read-only with bit 6 fixed at 0 at least in stepping A.
 	 */
 	if (phy == DPIO_PHY1)
 		val |= OCL2_LDOFUSE_PWR_DIS;
-- 
2.5.0

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[PATCH 04/16] drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR

[Imre Deak]

DMC forces on power well 1 by setting the corresponding request bit both
in the BIOS and the DEBUG power well request register. This is somewhat
unexpected since the firmware should really just save and restore state
but not alter it. We also depend on being able to disable power well 1,
before entering the DC9 state. To fix this make sure these request bits
are cleared whenever we want to disable the given power wells.

I've filed a bug about this, but fixing that may take a while and having
this sanity check in place makes sense even for future firmware
versions.

At the same time also check the KVMR request bits. I haven't seen this
being altered, but we don't expect any request bits in here either, so
sanitize this register as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 39 +++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d189a00..d20fd8f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -630,6 +630,42 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
+static void
+bxt_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
+				 struct i915_power_well *power_well)
+{
+	enum skl_disp_power_wells power_well_id = power_well->data;
+	u32 val;
+	u32 mask;
+
+	mask = SKL_POWER_WELL_REQ(power_well_id);
+
+	val = I915_READ(HSW_PWR_WELL_KVMR);
+	if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
+				   power_well->name))
+		I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
+
+	val = I915_READ(HSW_PWR_WELL_BIOS);
+	val |= I915_READ(HSW_PWR_WELL_DEBUG);
+
+	if (!(val & mask))
+		return;
+
+	/*
+	 * DMC is known to force on the request bits for power well 1 but we
+	 * don't expect any other request bits to be set, so WARN for those.
+	 */
+	if (power_well_id == SKL_DISP_PW_1)
+		DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
+				 "by DMC\n", power_well->name);
+	else
+		WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
+			  power_well->name);
+
+	I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
+	I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
+}
+
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			struct i915_power_well *power_well, bool enable)
 {
@@ -696,6 +732,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			POSTING_READ(HSW_PWR_WELL_DRIVER);
 			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 		}
+
+		if (IS_BROXTON(dev_priv))
+			bxt_sanitize_power_well_requests(dev_priv, power_well);
 	}
 
 	if (check_fuse_status) {
-- 
2.5.0

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[PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous

[Imre Deak]

So far we only power well enabling was synchronous not disabling. Since
we don't exactly know how the firmware (both DMC and PCU) synchronizes
against the actual power well state during DC transitions, make the
disabling also synchronous.

CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d20fd8f..f5f6e89 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 
 		if (!is_enabled) {
 			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
-			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
-				state_mask), 1))
-				DRM_ERROR("%s enable timeout\n",
-					power_well->name);
 			check_fuse_status = true;
 		}
 	} else {
@@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			bxt_sanitize_power_well_requests(dev_priv, power_well);
 	}
 
+	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
+		     1))
+		DRM_ERROR("%s %s timeout\n",
+			  power_well->name, enable ? "enable" : "disable");
+
 	if (check_fuse_status) {
 		if (power_well->data == SKL_DISP_PW_1) {
 			if (wait_for((I915_READ(SKL_FUSE_STATUS) &
-- 
2.5.0

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[PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts

[Imre Deak]

The display power well support and DC state management doesn't depend on
runtime PM support, so remove the incorrect asserts about this.

Also Broxton does support DC5, so the related assert in
assert_can_enable_dc5() is incorrect. There is a more generic and
correct assert for this already in gen9_set_dc_state(), so we can remove
all the other ones.

At the same time convert WARNs to WARN_ONCE for consistency with the
other DC state asserts.

CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++++++++++---------------------
 1 file changed, 11 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f5f6e89..b16315e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -443,15 +443,13 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 
 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
-
-	WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
-	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
-		"DC9 already programmed to be enabled.\n");
-	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
-		"DC5 still not disabled to enable DC9.\n");
-	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
-	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
+	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
+		  "DC9 already programmed to be enabled.\n");
+	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
+		  "DC5 still not disabled to enable DC9.\n");
+	WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
+	WARN_ONCE(intel_irqs_enabled(dev_priv),
+		  "Interrupts not disabled yet.\n");
 
 	 /*
 	  * TODO: check for the following to verify the conditions to enter DC9
@@ -464,9 +462,10 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 
 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 {
-	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
-	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
-		"DC5 still not disabled.\n");
+	WARN_ONCE(intel_irqs_enabled(dev_priv),
+		  "Interrupts not disabled yet.\n");
+	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
+		  "DC5 still not disabled.\n");
 
 	 /*
 	  * TODO: check for the following to verify DC9 state was indeed
@@ -573,13 +572,9 @@ static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 
 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
 	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 					SKL_DISP_PW_2);
 
-	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
-		  "Platform doesn't support DC5.\n");
-	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 	WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 
 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
@@ -600,11 +595,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 
 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
-
-	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
-		  "Platform doesn't support DC6.\n");
-	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 		  "Backlight is not disabled.\n");
 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
-- 
2.5.0

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[PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle

[Imre Deak]

On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC
firmware assistance where the target display power state is DC6. On
Broxton on the other hand we don't use the firmware for this, but rely
instead on a manual DC9 flow. For this we have to uninitialize the
display following the BSpec display uninit sequence, just as during
S3/S4, so make sure we follow this sequence.

CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 020a31c..aa7df10 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -657,7 +657,8 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 
 	disable_rpm_wakeref_asserts(dev_priv);
 
-	fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
+	fw_csr = !IS_BROXTON(dev_priv) &&
+		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
 	/*
 	 * In case of firmware assisted context save/restore don't manually
 	 * deinit the power domains. This also means the CSR/DMC firmware will
@@ -837,7 +838,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	intel_uncore_sanitize(dev);
 
-	if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
+	if (IS_BROXTON(dev_priv) ||
+	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
 		intel_power_domains_init_hw(dev_priv, true);
 
 out:
-- 
2.5.0

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[PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Imre Deak]

On Broxton we need to enable/disable power well 1 during the init/unit display
sequence similarly to Skylake/Kabylake. The code for this will be added in a
follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
a simple function called only from a single place and having it inlined in the
Skylake display core init/unit functions will make it easier to compare it
with its Broxton counterpart.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h        |  2 --
 drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------------------
 2 files changed, 18 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..8ba2ac3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b16315e..58ed8bc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
 	},
 };
 
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
-{
-	struct i915_power_well *well;
-
-	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
-		return;
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_enable(dev_priv, well);
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
-	intel_power_well_enable(dev_priv, well);
-}
-
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
-{
-	struct i915_power_well *well;
-
-	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
-		return;
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_disable(dev_priv, well);
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
-	intel_power_well_disable(dev_priv, well);
-}
-
 static struct i915_power_well bxt_power_wells[] = {
 	{
 		.name = "always-on",
@@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
 }
 
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
-				  bool resume)
+				   bool resume)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
 	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
-	skl_pw1_misc_io_init(dev_priv);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+	intel_power_well_enable(dev_priv, well);
+
 	mutex_unlock(&power_domains->lock);
 
 	if (!resume)
@@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
@@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	/* The spec doesn't call for removing the reset handshake flag */
 	/* disable PG1 and Misc I/O */
+
 	mutex_lock(&power_domains->lock);
-	skl_pw1_misc_io_fini(dev_priv);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+	intel_power_well_enable(dev_priv, well);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+
 	mutex_unlock(&power_domains->lock);
 }
 
-- 
2.5.0

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[PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers

[Imre Deak]

For internal APIs passing dev_priv is preferred to reduce indirections,
so convert over a few DDI PHY, CDCLK helpers.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c       | 12 ++++--------
 drivers/gpu/drm/i915/intel_ddi.c      | 10 ++++------
 drivers/gpu/drm/i915/intel_display.c  | 18 +++++++-----------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h      |  8 ++++----
 5 files changed, 21 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aa7df10..3998f6a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 
 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
-
 	/* TODO: when DC5 support is added disable DC5 here. */
 
-	broxton_ddi_phy_uninit(dev);
-	broxton_uninit_cdclk(dev);
+	broxton_ddi_phy_uninit(dev_priv);
+	broxton_uninit_cdclk(dev_priv);
 	bxt_enable_dc9(dev_priv);
 
 	return 0;
@@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
 
 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
-
 	/* TODO: when CSR FW support is added make sure the FW is loaded */
 
 	bxt_disable_dc9(dev_priv);
@@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
 	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
 	 * is available.
 	 */
-	broxton_init_cdclk(dev);
-	broxton_ddi_phy_init(dev);
+	broxton_init_cdclk(dev_priv);
+	broxton_ddi_phy_init(dev_priv);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f91306e..29017a4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
 }
 
-void broxton_ddi_phy_init(struct drm_device *dev)
+void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)
 {
 	/* Enable PHY1 first since it provides Rcomp for PHY0 */
-	broxton_phy_init(dev->dev_private, DPIO_PHY1);
-	broxton_phy_init(dev->dev_private, DPIO_PHY0);
+	broxton_phy_init(dev_priv, DPIO_PHY1);
+	broxton_phy_init(dev_priv, DPIO_PHY0);
 }
 
 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
@@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
 }
 
-void broxton_ddi_phy_uninit(struct drm_device *dev)
+void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
 	broxton_phy_uninit(dev_priv, DPIO_PHY1);
 	broxton_phy_uninit(dev_priv, DPIO_PHY0);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e6b5ee5..d9da89d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev)
 		intel_update_max_cdclk(dev);
 }
 
-static void broxton_set_cdclk(struct drm_device *dev, int frequency)
+static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t divider;
 	uint32_t ratio;
 	uint32_t current_freq;
@@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency)
 		return;
 	}
 
-	intel_update_cdclk(dev);
+	intel_update_cdclk(dev_priv->dev);
 }
 
-void broxton_init_cdclk(struct drm_device *dev)
+void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t val;
 
 	/*
@@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev)
 	 * - check if setting the max (or any) cdclk freq is really necessary
 	 *   here, it belongs to modeset time
 	 */
-	broxton_set_cdclk(dev, 624000);
+	broxton_set_cdclk(dev_priv, 624000);
 
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
 	POSTING_READ(DBUF_CTL);
@@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev)
 		DRM_ERROR("DBuf power enable timeout!\n");
 }
 
-void broxton_uninit_cdclk(struct drm_device *dev)
+void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
 	POSTING_READ(DBUF_CTL);
 
@@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev)
 		DRM_ERROR("DBuf power disable timeout!\n");
 
 	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
-	broxton_set_cdclk(dev, 19200);
+	broxton_set_cdclk(dev_priv, 19200);
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
@@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 		to_intel_atomic_state(old_state);
 	unsigned int req_cdclk = old_intel_state->dev_cdclk;
 
-	broxton_set_cdclk(dev, req_cdclk);
+	broxton_set_cdclk(to_i915(dev), req_cdclk);
 }
 
 /* compute the max rate for new configuration */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 1175eeb..fbe88b8 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
 	} else if (IS_BROXTON(dev)) {
-		broxton_init_cdclk(dev);
-		broxton_ddi_phy_init(dev);
+		broxton_init_cdclk(dev_priv);
+		broxton_ddi_phy_init(dev_priv);
 	} else {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8ba2ac3..e8843a7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
-void broxton_init_cdclk(struct drm_device *dev);
-void broxton_uninit_cdclk(struct drm_device *dev);
-void broxton_ddi_phy_init(struct drm_device *dev);
-void broxton_ddi_phy_uninit(struct drm_device *dev);
+void broxton_init_cdclk(struct drm_i915_private *dev_priv);
+void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
+void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
+void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
-- 
2.5.0

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[PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit

[Imre Deak]

The power-down step logically belongs to the individual PHY uninit
sequence so move it there. The only functional change is that we will
power down now PHY 1 separately before PHY 0 and preserve the other bits
in the register which are defined as reserved.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 29017a4..d16effd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1849,15 +1849,16 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
 	val &= ~COMMON_RESET_DIS;
 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+
+	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+	val &= ~GT_DISPLAY_POWER_ON(phy);
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
 }
 
 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
 {
 	broxton_phy_uninit(dev_priv, DPIO_PHY1);
 	broxton_phy_uninit(dev_priv, DPIO_PHY0);
-
-	/* FIXME: do this in broxton_phy_uninit per phy */
-	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
 }
 
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
-- 
2.5.0

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[PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand

[Imre Deak]

Power well 1 is managed by the DMC firmware so don't toggle it on-demand
from the driver. This means we need to follow the BSpec display
initialization sequence during driver loading and resuming (both system
and runtime) and enable power well 1 only once there. Afterwards DMC
will toggle power well 1 whenever entering/exiting DC5.

For this to work we also need to do away getting the PLL power domain,
since that just kept runtime PM disabled for good.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 15 +------
 drivers/gpu/drm/i915/intel_display.c    | 17 --------
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  5 +--
 drivers/gpu/drm/i915/intel_drv.h        |  2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 75 +++++++++++++++++++++++++++------
 5 files changed, 66 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3998f6a..3f56ddf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1070,10 +1070,7 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 
 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
 {
-	/* TODO: when DC5 support is added disable DC5 here. */
-
-	broxton_ddi_phy_uninit(dev_priv);
-	broxton_uninit_cdclk(dev_priv);
+	bxt_display_core_uninit(dev_priv);
 	bxt_enable_dc9(dev_priv);
 
 	return 0;
@@ -1081,16 +1078,8 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
 
 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
 {
-	/* TODO: when CSR FW support is added make sure the FW is loaded */
-
 	bxt_disable_dc9(dev_priv);
-
-	/*
-	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
-	 * is available.
-	 */
-	broxton_init_cdclk(dev_priv);
-	broxton_ddi_phy_init(dev_priv);
+	bxt_display_core_init(dev_priv, true);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d9da89d..1fbe619 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5442,21 +5442,6 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
 
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
-	/*
-	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
-	 * or else the reset will hang because there is no PCH to respond.
-	 * Move the handshake programming to initialization sequence.
-	 * Previously was left up to BIOS.
-	 */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
-
-	/* Enable PG1 for cdclk */
-	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
-
 	/* check if cd clock is enabled */
 	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
 		DRM_DEBUG_KMS("Display already initialized\n");
@@ -5493,8 +5478,6 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
 	broxton_set_cdclk(dev_priv, 19200);
-
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
 static const struct skl_cdclk_entry {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index fbe88b8..a060b67 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1644,10 +1644,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
-	} else if (IS_BROXTON(dev)) {
-		broxton_init_cdclk(dev_priv);
-		broxton_ddi_phy_init(dev_priv);
-	} else {
+	} else if (!IS_BROXTON(dev_priv)) {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
 		 * let's just check its state and print errors in case
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e8843a7..4c2083d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1460,6 +1460,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
+void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 58ed8bc..0c30635 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -419,25 +419,13 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 	BIT(POWER_DOMAIN_VGA) |				\
 	BIT(POWER_DOMAIN_GMBUS) |			\
 	BIT(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (		\
-	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
-	BIT(POWER_DOMAIN_PIPE_A) |			\
-	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\
-	BIT(POWER_DOMAIN_TRANSCODER_DSI_A) |		\
-	BIT(POWER_DOMAIN_TRANSCODER_DSI_C) |		\
-	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\
-	BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |		\
-	BIT(POWER_DOMAIN_PORT_DSI) |			\
-	BIT(POWER_DOMAIN_AUX_A) |			\
-	BIT(POWER_DOMAIN_PLLS) |			\
-	BIT(POWER_DOMAIN_INIT))
 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
 	BIT(POWER_DOMAIN_MODESET) |			\
 	BIT(POWER_DOMAIN_AUX_A) |			\
 	BIT(POWER_DOMAIN_INIT))
 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
-	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
+	(POWER_DOMAIN_MASK & ~(				\
 	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
 	BIT(POWER_DOMAIN_INIT))
 
@@ -1930,7 +1918,7 @@ static struct i915_power_well bxt_power_wells[] = {
 	},
 	{
 		.name = "power well 1",
-		.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
+		.domains = 0,
 		.ops = &skl_power_well_ops,
 		.data = SKL_DISP_PW_1,
 	},
@@ -2166,6 +2154,61 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 	mutex_unlock(&power_domains->lock);
 }
 
+void bxt_display_core_init(struct drm_i915_private *dev_priv,
+			   bool resume)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
+	uint32_t val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/*
+	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
+	 * or else the reset will hang because there is no PCH to respond.
+	 * Move the handshake programming to initialization sequence.
+	 * Previously was left up to BIOS.
+	 */
+	val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+	/* Enable PG1 */
+	mutex_lock(&power_domains->lock);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+
+	mutex_unlock(&power_domains->lock);
+
+	broxton_init_cdclk(dev_priv);
+	broxton_ddi_phy_init(dev_priv);
+
+	if (resume && dev_priv->csr.dmc_payload)
+		intel_csr_load_program(dev_priv);
+}
+
+void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	broxton_ddi_phy_uninit(dev_priv);
+	broxton_uninit_cdclk(dev_priv);
+
+	/* The spec doesn't call for removing the reset handshake flag */
+
+	/* Disable PG1 */
+	mutex_lock(&power_domains->lock);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_disable(dev_priv, well);
+
+	mutex_unlock(&power_domains->lock);
+}
+
 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_well *cmn_bc =
@@ -2297,6 +2340,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		skl_display_core_init(dev_priv, resume);
+	} else if (IS_BROXTON(dev)) {
+		bxt_display_core_init(dev_priv, resume);
 	} else if (IS_CHERRYVIEW(dev)) {
 		mutex_lock(&power_domains->lock);
 		chv_phy_control_init(dev_priv);
@@ -2334,6 +2379,8 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		skl_display_core_uninit(dev_priv);
+	else if (IS_BROXTON(dev_priv))
+		bxt_display_core_uninit(dev_priv);
 }
 
 /**
-- 
2.5.0

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[PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK

[Imre Deak]

When determining whether CDCLK is enabled by BIOS and so we should skip
reprogramming it, we didn't check the related DBUF power request and
state. In theory BIOS could enable one without the other so check for
this case and reprogram things if something is amiss.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1fbe619..447d46e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5440,14 +5440,38 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
 	intel_update_cdclk(dev_priv->dev);
 }
 
+static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
+{
+	if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
+		return false;
+
+	/* TODO: Check for a valid CDCLK rate */
+
+	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
+		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
+
+		return false;
+	}
+
+	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
+		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
+
+		return false;
+	}
+
+	return true;
+}
+
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	/* check if cd clock is enabled */
-	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
-		DRM_DEBUG_KMS("Display already initialized\n");
+	if (broxton_cdclk_is_enabled(dev_priv)) {
+		DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
 		return;
 	}
 
+	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
+
 	/*
 	 * FIXME:
 	 * - The initial CDCLK needs to be read from VBT.
-- 
2.5.0

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[PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY

[Imre Deak]

If BIOS has already programmed and enabled a PHY, don't reprogram it as
that may interfere with the currently active outputs. A follow-up patch
will add state verification, so we can catch any misconfiguration on
BIOS's behalf.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d16effd..8f06d6c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1722,12 +1722,52 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 	}
 }
 
+static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
+				   enum dpio_phy phy)
+{
+	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
+		return false;
+
+	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
+		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
+				 phy);
+
+		return false;
+	}
+
+	if (phy == DPIO_PHY1 &&
+	   !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
+		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
+
+		return false;
+	}
+
+	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
+		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
+				 phy);
+
+		return false;
+	}
+
+	return true;
+}
+
 static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     enum dpio_phy phy)
 {
 	enum port port;
 	u32 ports, val;
 
+	if (broxton_phy_is_enabled(dev_priv, phy)) {
+		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
+				 "won't reprogram it\n", phy);
+
+		return;
+	}
+
+	DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy);
+
 	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 	val |= GT_DISPLAY_POWER_ON(phy);
 	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
-- 
2.5.0

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[PATCH 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK

[Imre Deak]

I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything related.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/intel_ddi.c        | 124 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |   5 ++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |   8 +++
 5 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3ebb2f..0449ebf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1901,6 +1901,7 @@ struct drm_i915_private {
 	u32 fdi_rx_config;
 
 	u32 chv_phy_control;
+	u32 bxt_phy_grc;
 
 	u32 suspend_count;
 	bool suspended_to_idle;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8f06d6c..362fe23 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1753,6 +1753,13 @@ static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
+
+	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+}
+
 static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     enum dpio_phy phy)
 {
@@ -1762,6 +1769,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 	if (broxton_phy_is_enabled(dev_priv, phy)) {
 		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
 				 "won't reprogram it\n", phy);
+		/* Still read out the GRC value for state verification */
+		if (phy == DPIO_PHY1)
+			dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);
 
 		return;
 	}
@@ -1857,8 +1867,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     10))
 			DRM_ERROR("timeout waiting for PHY1 GRC\n");
 
-		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
-		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+		val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,
+							      DPIO_PHY1);
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
@@ -1901,6 +1911,116 @@ void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
 	broxton_phy_uninit(dev_priv, DPIO_PHY0);
 }
 
+static inline bool __printf(6, 7)
+__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+		       i915_reg_t reg, u32 mask, u32 expected,
+		       const char *reg_fmt, ...)
+{
+	struct va_format vaf;
+	va_list args;
+	u32 val;
+
+	val = I915_READ(reg);
+	if ((val & mask) == expected)
+		return true;
+
+	va_start(args, reg_fmt);
+	vaf.fmt = reg_fmt;
+	vaf.va = &args;
+
+	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
+			 "current %08x, expected %08x (mask %08x)\n",
+			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
+			 mask);
+
+	va_end(args);
+
+	return false;
+}
+
+static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
+				     enum dpio_phy phy)
+{
+	enum port port;
+	u32 ports;
+	uint32_t mask;
+	bool ok;
+
+#define _CHK(reg, mask, exp, fmt, ...)					\
+	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
+			       ## __VA_ARGS__)
+
+	/* We expect the PHY to be always enabled */
+	if (!broxton_phy_is_enabled(dev_priv, phy))
+		return false;
+
+	ok = true;
+
+	if (phy == DPIO_PHY0)
+		ports = BIT(PORT_B) | BIT(PORT_C);
+	else
+		ports = BIT(PORT_A);
+
+	for_each_port_masked(port, ports) {
+		int lane;
+
+		for (lane = 0; lane < 4; lane++)
+			ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane),
+				    LATENCY_OPTIM,
+				    lane != 1 ? LATENCY_OPTIM : 0,
+				    "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane);
+	}
+
+	/* PLL Rcomp code offset */
+	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
+		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW9(%d)", phy);
+	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
+		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW10(%d)", phy);
+
+	/* Power gating */
+	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
+	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
+		    "BXT_PORT_CL1CM_DW28(%d)", phy);
+
+	if (phy == DPIO_PHY0)
+		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
+			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
+			   "BXT_PORT_CL2CM_DW6_BC");
+
+	/*
+	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
+	 * at least on stepping A this bit is read-only and fixed at 0.
+	 */
+
+	if (phy == DPIO_PHY0) {
+		u32 grc_code = dev_priv->bxt_phy_grc;
+
+		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
+		           grc_code << GRC_CODE_SLOW_SHIFT |
+			   grc_code;
+		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
+		       GRC_CODE_NOM_MASK;
+		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
+			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
+
+		mask = GRC_DIS | GRC_RDY_OVRD;
+		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
+			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
+	}
+
+	return ok;
+#undef _CHK
+}
+
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv)
+{
+	if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) ||
+	    !broxton_phy_verify_state(dev_priv, DPIO_PHY1))
+		i915_report_error(dev_priv, "DDI PHY state mismatch\n");
+}
+
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 447d46e..b5140d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5462,6 +5462,11 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
 	return true;
 }
 
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
+{
+	return broxton_cdclk_is_enabled(dev_priv);
+}
+
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	/* check if cd clock is enabled */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4c2083d..4708c49 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1224,8 +1224,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0c30635..342f997 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -797,6 +797,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	if (IS_BROXTON(dev_priv)) {
+		broxton_cdclk_verify_state(dev_priv);
+		broxton_ddi_phy_verify_state(dev_priv);
+	}
 }
 
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@@ -2184,6 +2189,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	broxton_init_cdclk(dev_priv);
 	broxton_ddi_phy_init(dev_priv);
 
+	broxton_cdclk_verify_state(dev_priv);
+	broxton_ddi_phy_verify_state(dev_priv);
+
 	if (resume && dev_priv->csr.dmc_payload)
 		intel_csr_load_program(dev_priv);
 }
-- 
2.5.0

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[PATCH 15/16] Revert "drm/i915/bxt: Disable power well support"

[Imre Deak]

With the preceding fixes power well support should be functional on
Broxton, I could enter/exit DC5 without problems.

This reverts commit 18024199579882265653bfe9e2b1a3dcb5697cd9.

CC: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 342f997..4441734 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1948,11 +1948,6 @@ sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 	if (disable_power_well >= 0)
 		return !!disable_power_well;
 
-	if (IS_BROXTON(dev_priv)) {
-		DRM_DEBUG_KMS("Disabling display power well support\n");
-		return 0;
-	}
-
 	return 1;
 }
 
-- 
2.5.0

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[PATCH 16/16] drm/i915/bxt: Enable runtime PM

[Imre Deak]

With the preceding fixes runtime PM should be functional, I could
runtime suspend/resume the device without problems.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0449ebf..099cdee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-				 IS_KABYLAKE(dev))
+				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
-- 
2.5.0

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Re: [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit

[Jani Nikula]

On Fri, 01 Apr 2016, Imre Deak <imre.deak@intel.com> wrote:
> The power-down step logically belongs to the individual PHY uninit
> sequence so move it there. The only functional change is that we will
> power down now PHY 1 separately before PHY 0 and preserve the other bits
> in the register which are defined as reserved.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 29017a4..d16effd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1849,15 +1849,16 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
>  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
>  	val &= ~COMMON_RESET_DIS;
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> +
> +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> +	val &= ~GT_DISPLAY_POWER_ON(phy);
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>  }
>  
>  void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  {
>  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);

Unrelated to this patch, but since you're hashing stuff around here...

The init order is:

void broxton_ddi_phy_init(struct drm_device *dev)
{
	/* Enable PHY1 first since it provides Rcomp for PHY0 */
	broxton_phy_init(dev->dev_private, DPIO_PHY1);
	broxton_phy_init(dev->dev_private, DPIO_PHY0);
}

Should the uninit order be reversed?

BR,
Jani.



> -
> -	/* FIXME: do this in broxton_phy_uninit per phy */
> -	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
>  }
>  
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit

[Imre Deak]

On pe, 2016-04-01 at 16:29 +0300, Jani Nikula wrote:
> On Fri, 01 Apr 2016, Imre Deak <imre.deak@intel.com> wrote:
> > The power-down step logically belongs to the individual PHY uninit
> > sequence so move it there. The only functional change is that we
> > will
> > power down now PHY 1 separately before PHY 0 and preserve the other
> > bits
> > in the register which are defined as reserved.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 7 ++++---
> >  1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 29017a4..d16effd 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1849,15 +1849,16 @@ static void broxton_phy_uninit(struct
> > drm_i915_private *dev_priv,
> >  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> >  	val &= ~COMMON_RESET_DIS;
> >  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> > +
> > +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> > +	val &= ~GT_DISPLAY_POWER_ON(phy);
> > +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> >  }
> >  
> >  void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
> >  {
> >  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
> >  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
> 
> Unrelated to this patch, but since you're hashing stuff around
> here...
> 
> The init order is:
> 
> void broxton_ddi_phy_init(struct drm_device *dev)
> {
> 	/* Enable PHY1 first since it provides Rcomp for PHY0 */
> 	broxton_phy_init(dev->dev_private, DPIO_PHY1);
> 	broxton_phy_init(dev->dev_private, DPIO_PHY0);
> }
> 
> Should the uninit order be reversed?

That would be logical, but the bspec specifies this uninit order. The
init order is also fixed in the above way but it's understandable why.

--Imre

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✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Fix/enable display power well support/runtime PM
URL   : https://patchwork.freedesktop.org/series/5177/
State : failure

== Summary ==

  CC [M]  drivers/gpu/drm/i915/intel_dp_link_training.o
  CC [M]  drivers/gpu/drm/i915/intel_dp_mst.o
  CC [M]  drivers/gpu/drm/i915/intel_dp.o
  CC [M]  drivers/gpu/drm/i915/intel_dsi.o
  CC [M]  drivers/gpu/drm/i915/intel_dsi_panel_vbt.o
  CC [M]  drivers/gpu/drm/i915/intel_dsi_pll.o
  CC [M]  drivers/gpu/drm/i915/intel_dvo.o
  CC [M]  drivers/gpu/drm/i915/intel_hdmi.o
  CC [M]  drivers/gpu/drm/i915/intel_i2c.o
  CC [M]  drivers/gpu/drm/i915/intel_lvds.o
  CC [M]  drivers/gpu/drm/i915/intel_panel.o
  CC [M]  drivers/gpu/drm/i915/intel_sdvo.o
  CC [M]  drivers/gpu/drm/i915/intel_tv.o
  CC [M]  drivers/gpu/drm/i915/i915_vgpu.o
  CC [M]  drivers/gpu/drm/i915/i915_dma.o
drivers/gpu/drm/i915/intel_ddi.c: In function '__phy_reg_verify_state':
drivers/gpu/drm/i915/intel_ddi.c:1915:1: error: function '__phy_reg_verify_state' can never be inlined because it uses variable argument lists
 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 ^
scripts/Makefile.build:291: recipe for target 'drivers/gpu/drm/i915/intel_ddi.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_ddi.o] Error 1
make[4]: *** Waiting for unfinished jobs....
scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:440: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:962: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[PATCH v2 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK

[Imre Deak]

I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything related.

v2:
- Inlining __phy_reg_verify_state() doesn't make sense and also
  incorrect, so don't do it (PW/CI gcc)

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/intel_ddi.c        | 124 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |   5 ++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |   8 +++
 5 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3ebb2f..0449ebf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1901,6 +1901,7 @@ struct drm_i915_private {
 	u32 fdi_rx_config;
 
 	u32 chv_phy_control;
+	u32 bxt_phy_grc;
 
 	u32 suspend_count;
 	bool suspended_to_idle;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8f06d6c..a27176d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1753,6 +1753,13 @@ static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
+
+	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+}
+
 static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     enum dpio_phy phy)
 {
@@ -1762,6 +1769,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 	if (broxton_phy_is_enabled(dev_priv, phy)) {
 		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
 				 "won't reprogram it\n", phy);
+		/* Still read out the GRC value for state verification */
+		if (phy == DPIO_PHY1)
+			dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);
 
 		return;
 	}
@@ -1857,8 +1867,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     10))
 			DRM_ERROR("timeout waiting for PHY1 GRC\n");
 
-		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
-		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+		val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,
+							      DPIO_PHY1);
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
@@ -1901,6 +1911,116 @@ void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
 	broxton_phy_uninit(dev_priv, DPIO_PHY0);
 }
 
+static bool __printf(6, 7)
+__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+		       i915_reg_t reg, u32 mask, u32 expected,
+		       const char *reg_fmt, ...)
+{
+	struct va_format vaf;
+	va_list args;
+	u32 val;
+
+	val = I915_READ(reg);
+	if ((val & mask) == expected)
+		return true;
+
+	va_start(args, reg_fmt);
+	vaf.fmt = reg_fmt;
+	vaf.va = &args;
+
+	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
+			 "current %08x, expected %08x (mask %08x)\n",
+			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
+			 mask);
+
+	va_end(args);
+
+	return false;
+}
+
+static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
+				     enum dpio_phy phy)
+{
+	enum port port;
+	u32 ports;
+	uint32_t mask;
+	bool ok;
+
+#define _CHK(reg, mask, exp, fmt, ...)					\
+	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
+			       ## __VA_ARGS__)
+
+	/* We expect the PHY to be always enabled */
+	if (!broxton_phy_is_enabled(dev_priv, phy))
+		return false;
+
+	ok = true;
+
+	if (phy == DPIO_PHY0)
+		ports = BIT(PORT_B) | BIT(PORT_C);
+	else
+		ports = BIT(PORT_A);
+
+	for_each_port_masked(port, ports) {
+		int lane;
+
+		for (lane = 0; lane < 4; lane++)
+			ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane),
+				    LATENCY_OPTIM,
+				    lane != 1 ? LATENCY_OPTIM : 0,
+				    "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane);
+	}
+
+	/* PLL Rcomp code offset */
+	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
+		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW9(%d)", phy);
+	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
+		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW10(%d)", phy);
+
+	/* Power gating */
+	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
+	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
+		    "BXT_PORT_CL1CM_DW28(%d)", phy);
+
+	if (phy == DPIO_PHY0)
+		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
+			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
+			   "BXT_PORT_CL2CM_DW6_BC");
+
+	/*
+	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
+	 * at least on stepping A this bit is read-only and fixed at 0.
+	 */
+
+	if (phy == DPIO_PHY0) {
+		u32 grc_code = dev_priv->bxt_phy_grc;
+
+		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
+		           grc_code << GRC_CODE_SLOW_SHIFT |
+			   grc_code;
+		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
+		       GRC_CODE_NOM_MASK;
+		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
+			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
+
+		mask = GRC_DIS | GRC_RDY_OVRD;
+		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
+			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
+	}
+
+	return ok;
+#undef _CHK
+}
+
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv)
+{
+	if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) ||
+	    !broxton_phy_verify_state(dev_priv, DPIO_PHY1))
+		i915_report_error(dev_priv, "DDI PHY state mismatch\n");
+}
+
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 447d46e..b5140d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5462,6 +5462,11 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
 	return true;
 }
 
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
+{
+	return broxton_cdclk_is_enabled(dev_priv);
+}
+
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	/* check if cd clock is enabled */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4c2083d..4708c49 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1224,8 +1224,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0c30635..342f997 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -797,6 +797,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	if (IS_BROXTON(dev_priv)) {
+		broxton_cdclk_verify_state(dev_priv);
+		broxton_ddi_phy_verify_state(dev_priv);
+	}
 }
 
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@@ -2184,6 +2189,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	broxton_init_cdclk(dev_priv);
 	broxton_ddi_phy_init(dev_priv);
 
+	broxton_cdclk_verify_state(dev_priv);
+	broxton_ddi_phy_verify_state(dev_priv);
+
 	if (resume && dev_priv->csr.dmc_payload)
 		intel_csr_load_program(dev_priv);
 }
-- 
2.5.0

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✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2)
URL   : https://patchwork.freedesktop.org/series/5177/
State : success

== Summary ==

Series 5177v2 drm/i915/bxt: Fix/enable display power well support/runtime PM
http://patchwork.freedesktop.org/api/1.0/series/5177/revisions/2/mbox/

Test kms_force_connector_basic:
        Subgroup force-edid:
                skip       -> PASS       (ivb-t430s)

bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:159  dwarn:0   dfail:0   fail:0   skip:37 
byt-nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:196  pass:179  dwarn:0   dfail:0   fail:0   skip:17 
ilk-hp8440p      total:196  pass:132  dwarn:0   dfail:0   fail:0   skip:64 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:162  dwarn:0   dfail:0   fail:1   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1776/

38b47023a604068e2a222ac166f5f8ef7d56e352 drm-intel-nightly: 2016y-04m-01d-12h-04m-08s UTC integration manifest
6ecf9df2f371419ba5ccc7a85732ef8b97c959ab drm/i915/bxt: Enable runtime PM
b96b17750521fffb383ebe9bd3979a7fa0f3aa16 Revert "drm/i915/bxt: Disable power well support"
bb74c386bbb9f3351d43175f1f17fb2981a6482d drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
ebde74eba32cc64f5cf72995378e191f46de6c79 drm/i915/bxt: Don't reprogram an already enabled DDI PHY
0d3c7f52c1896c3643bb367a1bdc3b4489f14c10 drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
064941fc5cfbc67631b32835986b227e574bf27c drm/i915/bxt: Don't toggle power well 1 on-demand
db7c5db132ff858368e26df9c7a4de0cab6f25b9 drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
524368601f649a030761aa7750578254dba15cc1 drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
81c9ae2fb46bc24bc8cc327a2ed208da93bd00fd drm/i915/skl: Unexport skl_pw1_misc_io_init
948658fe12a8d508c00911661d28a20da0313b62 drm/i915/bxt: Suspend power domains during suspend-to-idle
e8a20e5f896ee0e1b68ee31751c55e78db98fd12 drm/i915/gen9: Fix DMC/DC state asserts
c26080e3ac58bce4420bc56b7cd00db7ee445012 drm/i915/gen9: Make power well disabling synchronous
29cce09852a809d5f097b20ea796cb73c2a9e4a9 drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR
7e6c803c6b361aed28a5e4b8a3b36bade9d1ddc8 drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
074d6e56b6b6d0e8a3f93b6247772e66778e0104 drm/i915/bxt: Fix GRC code register field definitions
51d897b70b52eee0095edd475e9d10504988c297 drm/i915/bxt: Reject DMC firmware versions with known bugs

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Re: [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> So far we only power well enabling was synchronous not disabling. Since
> we don't exactly know how the firmware (both DMC and PCU) synchronizes
> against the actual power well state during DC transitions, make the
> disabling also synchronous.
> 
> CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d20fd8f..f5f6e89 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  
>  		if (!is_enabled) {
>  			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> -			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> -				state_mask), 1))
> -				DRM_ERROR("%s enable timeout\n",
> -					power_well->name);
>  			check_fuse_status = true;
>  		}
>  	} else {
> @@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			bxt_sanitize_power_well_requests(dev_priv, power_well);
>  	}
>  
> +	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> +		     1))
> +		DRM_ERROR("%s %s timeout\n",
> +			  power_well->name, enable ? "enable" : "disable");
> +
>  	if (check_fuse_status) {
>  		if (power_well->data == SKL_DISP_PW_1) {
>  			if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> -- 
> 2.5.0
> 

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Re: [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 04:02:37PM +0300, Imre Deak wrote:
> The display power well support and DC state management doesn't depend on
> runtime PM support, so remove the incorrect asserts about this.
> 
> Also Broxton does support DC5, so the related assert in
> assert_can_enable_dc5() is incorrect. There is a more generic and
> correct assert for this already in gen9_set_dc_state(), so we can remove
> all the other ones.
> 
> At the same time convert WARNs to WARN_ONCE for consistency with the
> other DC state asserts.
> 
> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++++++++++---------------------
>  1 file changed, 11 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f5f6e89..b16315e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -443,15 +443,13 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  
>  static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
> -	WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
> -	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> -		"DC9 already programmed to be enabled.\n");
> -	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> -		"DC5 still not disabled to enable DC9.\n");
> -	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
> -	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> +	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> +		  "DC9 already programmed to be enabled.\n");
> +	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> +		  "DC5 still not disabled to enable DC9.\n");
> +	WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
> +	WARN_ONCE(intel_irqs_enabled(dev_priv),
> +		  "Interrupts not disabled yet.\n");
>  
>  	 /*
>  	  * TODO: check for the following to verify the conditions to enter DC9
> @@ -464,9 +462,10 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
>  
>  static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
>  {
> -	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> -	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> -		"DC5 still not disabled.\n");
> +	WARN_ONCE(intel_irqs_enabled(dev_priv),
> +		  "Interrupts not disabled yet.\n");
> +	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> +		  "DC5 still not disabled.\n");
>  
>  	 /*
>  	  * TODO: check for the following to verify DC9 state was indeed
> @@ -573,13 +572,9 @@ static void assert_csr_loaded(struct drm_i915_private *dev_priv)
>  
>  static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
>  	bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
>  					SKL_DISP_PW_2);
>  
> -	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
> -		  "Platform doesn't support DC5.\n");
> -	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
>  	WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
>  
>  	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
> @@ -600,11 +595,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>  
>  static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
> -	WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
> -		  "Platform doesn't support DC6.\n");
> -	WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
>  	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
>  		  "Backlight is not disabled.\n");
>  	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
> -- 
> 2.5.0
> 

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Re: [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 04:02:38PM +0300, Imre Deak wrote:
> On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC
> firmware assistance where the target display power state is DC6. On
> Broxton on the other hand we don't use the firmware for this, but rely
> instead on a manual DC9 flow. For this we have to uninitialize the
> display following the BSpec display uninit sequence, just as during
> S3/S4, so make sure we follow this sequence.
> 
> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 020a31c..aa7df10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -657,7 +657,8 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
>  
>  	disable_rpm_wakeref_asserts(dev_priv);
>  
> -	fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
> +	fw_csr = !IS_BROXTON(dev_priv) &&
> +		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
>  	/*
>  	 * In case of firmware assisted context save/restore don't manually
>  	 * deinit the power domains. This also means the CSR/DMC firmware will
> @@ -837,7 +838,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  
>  	intel_uncore_sanitize(dev);
>  
> -	if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
> +	if (IS_BROXTON(dev_priv) ||
> +	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
>  		intel_power_domains_init_hw(dev_priv, true);
>  
>  out:
> -- 
> 2.5.0
> 

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Re: [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Patrik Jakobsson]

On Fri, Apr 01, 2016 at 04:02:39PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
> a simple function called only from a single place and having it inlined in the
> Skylake display core init/unit functions will make it easier to compare it
> with its Broxton counterpart.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h        |  2 --
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------------------
>  2 files changed, 18 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9255b56..8ba2ac3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_fini(struct drm_i915_private *);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>  void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
>  const char *
>  intel_display_power_domain_str(enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b16315e..58ed8bc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
>  	},
>  };
>  
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> -{
> -	struct i915_power_well *well;
> -
> -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> -		return;
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_enable(dev_priv, well);
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> -	intel_power_well_enable(dev_priv, well);
> -}
> -
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> -{
> -	struct i915_power_well *well;
> -
> -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> -		return;
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_disable(dev_priv, well);
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> -	intel_power_well_disable(dev_priv, well);
> -}
> -
>  static struct i915_power_well bxt_power_wells[] = {
>  	{
>  		.name = "always-on",
> @@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
>  }
>  
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
> -				  bool resume)
> +				   bool resume)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
>  	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	/* enable PG1 and Misc I/O */
>  	mutex_lock(&power_domains->lock);
> -	skl_pw1_misc_io_init(dev_priv);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_enable(dev_priv, well);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> +	intel_power_well_enable(dev_priv, well);
> +
>  	mutex_unlock(&power_domains->lock);
>  
>  	if (!resume)
> @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
>  	/* disable PG1 and Misc I/O */
> +
>  	mutex_lock(&power_domains->lock);
> -	skl_pw1_misc_io_fini(dev_priv);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> +	intel_power_well_enable(dev_priv, well);

Should be intel_power_well_disable(...)

> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_enable(dev_priv, well);

Same here.

> +
>  	mutex_unlock(&power_domains->lock);
>  }
>  
> -- 
> 2.5.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Imre Deak]

On ma, 2016-04-04 at 14:30 +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 04:02:39PM +0300, Imre Deak wrote:
> > On Broxton we need to enable/disable power well 1 during the
> > init/unit display
> > sequence similarly to Skylake/Kabylake. The code for this will be
> > added in a
> > follow-up patch, but to prepare for that unexport
> > skl_pw1_misc_io_init(). It's
> > a simple function called only from a single place and having it
> > inlined in the
> > Skylake display core init/unit functions will make it easier to
> > compare it
> > with its Broxton counterpart.
> > 
> > No functional change.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h        |  2 --
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------
> > ------------
> >  2 files changed, 18 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 9255b56..8ba2ac3 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct
> > drm_i915_private *);
> >  void intel_power_domains_fini(struct drm_i915_private *);
> >  void intel_power_domains_init_hw(struct drm_i915_private
> > *dev_priv, bool resume);
> >  void intel_power_domains_suspend(struct drm_i915_private
> > *dev_priv);
> > -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> > -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
> >  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> >  const char *
> >  intel_display_power_domain_str(enum intel_display_power_domain
> > domain);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index b16315e..58ed8bc 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1921,34 +1921,6 @@ static struct i915_power_well
> > skl_power_wells[] = {
> >  	},
> >  };
> >  
> > -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> > -{
> > -	struct i915_power_well *well;
> > -
> > -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> > -		return;
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > -	intel_power_well_enable(dev_priv, well);
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > -	intel_power_well_enable(dev_priv, well);
> > -}
> > -
> > -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> > -{
> > -	struct i915_power_well *well;
> > -
> > -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> > -		return;
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > -	intel_power_well_disable(dev_priv, well);
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > -	intel_power_well_disable(dev_priv, well);
> > -}
> > -
> >  static struct i915_power_well bxt_power_wells[] = {
> >  	{
> >  		.name = "always-on",
> > @@ -2139,9 +2111,10 @@ static void
> > intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  static void skl_display_core_init(struct drm_i915_private
> > *dev_priv,
> > -				  bool resume)
> > +				   bool resume)
> >  {
> >  	struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > +	struct i915_power_well *well;
> >  	uint32_t val;
> >  
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >  
> >  	/* enable PG1 and Misc I/O */
> >  	mutex_lock(&power_domains->lock);
> > -	skl_pw1_misc_io_init(dev_priv);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_enable(dev_priv, well);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > +	intel_power_well_enable(dev_priv, well);
> > +
> >  	mutex_unlock(&power_domains->lock);
> >  
> >  	if (!resume)
> > @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >  static void skl_display_core_uninit(struct drm_i915_private
> > *dev_priv)
> >  {
> >  	struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > +	struct i915_power_well *well;
> >  
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> > @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct
> > drm_i915_private *dev_priv)
> >  
> >  	/* The spec doesn't call for removing the reset handshake
> > flag */
> >  	/* disable PG1 and Misc I/O */
> > +
> >  	mutex_lock(&power_domains->lock);
> > -	skl_pw1_misc_io_fini(dev_priv);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > +	intel_power_well_enable(dev_priv, well);
> 
> Should be intel_power_well_disable(...)
> 
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_enable(dev_priv, well);
> 
> Same here.

Oops, thanks for catching it.

--Imre

> 
> > +
> >  	mutex_unlock(&power_domains->lock);
> >  }
> >  
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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[PATCH v2 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Imre Deak]

On Broxton we need to enable/disable power well 1 during the init/unit display
sequence similarly to Skylake/Kabylake. The code for this will be added in a
follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
a simple function called only from a single place and having it inlined in the
Skylake display core init/unit functions will make it easier to compare it
with its Broxton counterpart.

No functional change.

v2:
- Fix incorrect enable vs. disable power well call in
  skl_display_core_uninit() (Patrik)

CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h        |  2 --
 drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------------------
 2 files changed, 18 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..8ba2ac3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b16315e..8d401bb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
 	},
 };
 
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
-{
-	struct i915_power_well *well;
-
-	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
-		return;
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_enable(dev_priv, well);
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
-	intel_power_well_enable(dev_priv, well);
-}
-
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
-{
-	struct i915_power_well *well;
-
-	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
-		return;
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_disable(dev_priv, well);
-
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
-	intel_power_well_disable(dev_priv, well);
-}
-
 static struct i915_power_well bxt_power_wells[] = {
 	{
 		.name = "always-on",
@@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
 }
 
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
-				  bool resume)
+				   bool resume)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
 	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
-	skl_pw1_misc_io_init(dev_priv);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+	intel_power_well_enable(dev_priv, well);
+
 	mutex_unlock(&power_domains->lock);
 
 	if (!resume)
@@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
@@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	/* The spec doesn't call for removing the reset handshake flag */
 	/* disable PG1 and Misc I/O */
+
 	mutex_lock(&power_domains->lock);
-	skl_pw1_misc_io_fini(dev_priv);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+	intel_power_well_disable(dev_priv, well);
+
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_disable(dev_priv, well);
+
 	mutex_unlock(&power_domains->lock);
 }
 
-- 
2.5.0

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Re: [PATCH v2 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Patrik Jakobsson]

On Mon, Apr 04, 2016 at 03:42:57PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
> a simple function called only from a single place and having it inlined in the
> Skylake display core init/unit functions will make it easier to compare it
> with its Broxton counterpart.
> 
> No functional change.
> 
> v2:
> - Fix incorrect enable vs. disable power well call in
>   skl_display_core_uninit() (Patrik)
> 
> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h        |  2 --
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------------------
>  2 files changed, 18 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9255b56..8ba2ac3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_fini(struct drm_i915_private *);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>  void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
>  const char *
>  intel_display_power_domain_str(enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b16315e..8d401bb 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
>  	},
>  };
>  
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> -{
> -	struct i915_power_well *well;
> -
> -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> -		return;
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_enable(dev_priv, well);
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> -	intel_power_well_enable(dev_priv, well);
> -}
> -
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> -{
> -	struct i915_power_well *well;
> -
> -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> -		return;
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_disable(dev_priv, well);
> -
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> -	intel_power_well_disable(dev_priv, well);
> -}
> -
>  static struct i915_power_well bxt_power_wells[] = {
>  	{
>  		.name = "always-on",
> @@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
>  }
>  
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
> -				  bool resume)
> +				   bool resume)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
>  	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	/* enable PG1 and Misc I/O */
>  	mutex_lock(&power_domains->lock);
> -	skl_pw1_misc_io_init(dev_priv);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_enable(dev_priv, well);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> +	intel_power_well_enable(dev_priv, well);
> +
>  	mutex_unlock(&power_domains->lock);
>  
>  	if (!resume)
> @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
>  	/* disable PG1 and Misc I/O */
> +
>  	mutex_lock(&power_domains->lock);
> -	skl_pw1_misc_io_fini(dev_priv);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> +	intel_power_well_disable(dev_priv, well);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_disable(dev_priv, well);
> +

I see you've flipped the order here. Probably for the better since I'm guessing
the old behaviour was by accident and not by design, but perhaps we should
mention this in the commit.

With above comment fixed,
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

>  	mutex_unlock(&power_domains->lock);
>  }
>  
> -- 
> 2.5.0
> 

-- 
---
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Re: [PATCH v2 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init

[Imre Deak]

On ma, 2016-04-04 at 15:01 +0200, Patrik Jakobsson wrote:
> On Mon, Apr 04, 2016 at 03:42:57PM +0300, Imre Deak wrote:
> > On Broxton we need to enable/disable power well 1 during the
> > init/unit display
> > sequence similarly to Skylake/Kabylake. The code for this will be
> > added in a
> > follow-up patch, but to prepare for that unexport
> > skl_pw1_misc_io_init(). It's
> > a simple function called only from a single place and having it
> > inlined in the
> > Skylake display core init/unit functions will make it easier to
> > compare it
> > with its Broxton counterpart.
> > 
> > No functional change.
> > 
> > v2:
> > - Fix incorrect enable vs. disable power well call in
> >   skl_display_core_uninit() (Patrik)
> > 
> > CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h        |  2 --
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------
> > ------------
> >  2 files changed, 18 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 9255b56..8ba2ac3 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct
> > drm_i915_private *);
> >  void intel_power_domains_fini(struct drm_i915_private *);
> >  void intel_power_domains_init_hw(struct drm_i915_private
> > *dev_priv, bool resume);
> >  void intel_power_domains_suspend(struct drm_i915_private
> > *dev_priv);
> > -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> > -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
> >  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> >  const char *
> >  intel_display_power_domain_str(enum intel_display_power_domain
> > domain);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index b16315e..8d401bb 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1921,34 +1921,6 @@ static struct i915_power_well
> > skl_power_wells[] = {
> >  	},
> >  };
> >  
> > -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> > -{
> > -	struct i915_power_well *well;
> > -
> > -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> > -		return;
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > -	intel_power_well_enable(dev_priv, well);
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > -	intel_power_well_enable(dev_priv, well);
> > -}
> > -
> > -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> > -{
> > -	struct i915_power_well *well;
> > -
> > -	if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> > -		return;
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > -	intel_power_well_disable(dev_priv, well);
> > -
> > -	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > -	intel_power_well_disable(dev_priv, well);
> > -}
> > -
> >  static struct i915_power_well bxt_power_wells[] = {
> >  	{
> >  		.name = "always-on",
> > @@ -2139,9 +2111,10 @@ static void
> > intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
> >  }
> >  
> >  static void skl_display_core_init(struct drm_i915_private
> > *dev_priv,
> > -				  bool resume)
> > +				   bool resume)
> >  {
> >  	struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > +	struct i915_power_well *well;
> >  	uint32_t val;
> >  
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >  
> >  	/* enable PG1 and Misc I/O */
> >  	mutex_lock(&power_domains->lock);
> > -	skl_pw1_misc_io_init(dev_priv);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_enable(dev_priv, well);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > +	intel_power_well_enable(dev_priv, well);
> > +
> >  	mutex_unlock(&power_domains->lock);
> >  
> >  	if (!resume)
> > @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >  static void skl_display_core_uninit(struct drm_i915_private
> > *dev_priv)
> >  {
> >  	struct i915_power_domains *power_domains = &dev_priv-
> > >power_domains;
> > +	struct i915_power_well *well;
> >  
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> > @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct
> > drm_i915_private *dev_priv)
> >  
> >  	/* The spec doesn't call for removing the reset handshake
> > flag */
> >  	/* disable PG1 and Misc I/O */
> > +
> >  	mutex_lock(&power_domains->lock);
> > -	skl_pw1_misc_io_fini(dev_priv);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> > +	intel_power_well_disable(dev_priv, well);
> > +
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_disable(dev_priv, well);
> > +
> 
> I see you've flipped the order here. Probably for the better since
> I'm guessing
> the old behaviour was by accident and not by design, but perhaps we
> should
> mention this in the commit.

Yes, the reversed uninit order is the correct one. I'll mention this
change in the log.

> 
> With above comment fixed,
> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> 
> >  	mutex_unlock(&power_domains->lock);
> >  }
> >  
> > -- 
> > 2.5.0
> > 
> 
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✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3)
URL   : https://patchwork.freedesktop.org/series/5177/
State : failure

== Summary ==

  CC [M]  drivers/net/ethernet/realtek/8139cp.o
  CC [M]  drivers/net/ethernet/realtek/8139too.o
  LD      drivers/pci/pcie/pcieportdrv.o
  CC [M]  drivers/net/ethernet/realtek/r8169.o
  LD      drivers/net/ethernet/renesas/built-in.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_82575.o
  LD [M]  drivers/mmc/core/mmc_core.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_nvm.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mac.o
  LD      drivers/net/ethernet/smsc/built-in.o
  CC [M]  drivers/net/ethernet/smsc/smsc9420.o
  LD      drivers/net/ethernet/synopsys/built-in.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_phy.o
  LD      drivers/mmc/built-in.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_mbx.o
  CC [M]  drivers/net/ethernet/intel/igb/e1000_i210.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_ptp.o
  CC [M]  drivers/net/ethernet/intel/igb/igb_hwmon.o
  LD      drivers/pci/pcie/aer/aerdriver.o
  LD      drivers/pci/pcie/aer/built-in.o
  LD      drivers/pci/pcie/built-in.o
  LD      drivers/pci/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  LD [M]  drivers/net/ethernet/intel/igbvf/igbvf.o
  LD [M]  drivers/net/ethernet/broadcom/genet/genet.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  LD      drivers/net/ethernet/built-in.o
  LD      drivers/net/built-in.o
Makefile:962: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[PATCH v3 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK

[Imre Deak]

I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything related.

v2:
- Inlining __phy_reg_verify_state() doesn't make sense and also
  incorrect, so don't do it (PW/CI gcc)
v3:
- Rebase on latest -nightly

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/intel_ddi.c        | 124 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |   5 ++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c |   8 +++
 5 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd18772..6f4a721 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1908,6 +1908,7 @@ struct drm_i915_private {
 	 * crappiness (can't read out DPLL_MD for pipes B & C).
 	 */
 	u32 chv_dpll_md[I915_MAX_PIPES];
+	u32 bxt_phy_grc;
 
 	u32 suspend_count;
 	bool suspended_to_idle;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d944bff..fd20119 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1753,6 +1753,13 @@ static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
 	return true;
 }
 
+static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
+
+	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+}
+
 static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     enum dpio_phy phy)
 {
@@ -1762,6 +1769,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 	if (broxton_phy_is_enabled(dev_priv, phy)) {
 		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
 				 "won't reprogram it\n", phy);
+		/* Still read out the GRC value for state verification */
+		if (phy == DPIO_PHY1)
+			dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);
 
 		return;
 	}
@@ -1857,8 +1867,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
 			     10))
 			DRM_ERROR("timeout waiting for PHY1 GRC\n");
 
-		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
-		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+		val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,
+							      DPIO_PHY1);
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
@@ -1901,6 +1911,116 @@ void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
 	broxton_phy_uninit(dev_priv, DPIO_PHY0);
 }
 
+static bool __printf(6, 7)
+__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+		       i915_reg_t reg, u32 mask, u32 expected,
+		       const char *reg_fmt, ...)
+{
+	struct va_format vaf;
+	va_list args;
+	u32 val;
+
+	val = I915_READ(reg);
+	if ((val & mask) == expected)
+		return true;
+
+	va_start(args, reg_fmt);
+	vaf.fmt = reg_fmt;
+	vaf.va = &args;
+
+	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
+			 "current %08x, expected %08x (mask %08x)\n",
+			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
+			 mask);
+
+	va_end(args);
+
+	return false;
+}
+
+static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
+				     enum dpio_phy phy)
+{
+	enum port port;
+	u32 ports;
+	uint32_t mask;
+	bool ok;
+
+#define _CHK(reg, mask, exp, fmt, ...)					\
+	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
+			       ## __VA_ARGS__)
+
+	/* We expect the PHY to be always enabled */
+	if (!broxton_phy_is_enabled(dev_priv, phy))
+		return false;
+
+	ok = true;
+
+	if (phy == DPIO_PHY0)
+		ports = BIT(PORT_B) | BIT(PORT_C);
+	else
+		ports = BIT(PORT_A);
+
+	for_each_port_masked(port, ports) {
+		int lane;
+
+		for (lane = 0; lane < 4; lane++)
+			ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane),
+				    LATENCY_OPTIM,
+				    lane != 1 ? LATENCY_OPTIM : 0,
+				    "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane);
+	}
+
+	/* PLL Rcomp code offset */
+	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
+		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW9(%d)", phy);
+	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
+		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW10(%d)", phy);
+
+	/* Power gating */
+	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
+	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
+		    "BXT_PORT_CL1CM_DW28(%d)", phy);
+
+	if (phy == DPIO_PHY0)
+		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
+			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
+			   "BXT_PORT_CL2CM_DW6_BC");
+
+	/*
+	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
+	 * at least on stepping A this bit is read-only and fixed at 0.
+	 */
+
+	if (phy == DPIO_PHY0) {
+		u32 grc_code = dev_priv->bxt_phy_grc;
+
+		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
+		           grc_code << GRC_CODE_SLOW_SHIFT |
+			   grc_code;
+		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
+		       GRC_CODE_NOM_MASK;
+		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
+			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
+
+		mask = GRC_DIS | GRC_RDY_OVRD;
+		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
+			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
+	}
+
+	return ok;
+#undef _CHK
+}
+
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv)
+{
+	if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) ||
+	    !broxton_phy_verify_state(dev_priv, DPIO_PHY1))
+		i915_report_error(dev_priv, "DDI PHY state mismatch\n");
+}
+
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8999fe8..842ca5d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5460,6 +5460,11 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
 	return true;
 }
 
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
+{
+	return broxton_cdclk_is_enabled(dev_priv);
+}
+
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	/* check if cd clock is enabled */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4c2083d..4708c49 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1224,8 +1224,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
+bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
+void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e60b02e..59b30c9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -797,6 +797,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	if (IS_BROXTON(dev_priv)) {
+		broxton_cdclk_verify_state(dev_priv);
+		broxton_ddi_phy_verify_state(dev_priv);
+	}
 }
 
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@@ -2184,6 +2189,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	broxton_init_cdclk(dev_priv);
 	broxton_ddi_phy_init(dev_priv);
 
+	broxton_cdclk_verify_state(dev_priv);
+	broxton_ddi_phy_verify_state(dev_priv);
+
 	if (resume && dev_priv->csr.dmc_payload)
 		intel_csr_load_program(dev_priv);
 }
-- 
2.5.0

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✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4)
URL   : https://patchwork.freedesktop.org/series/5177/
State : failure

== Summary ==

Series 5177v4 drm/i915/bxt: Fix/enable display power well support/runtime PM
http://patchwork.freedesktop.org/api/1.0/series/5177/revisions/4/mbox/

Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> DMESG-WARN (skl-nuci5)
                pass       -> DMESG-WARN (skl-i7k-2)
Test kms_force_connector_basic:
        Subgroup force-load-detect:
                pass       -> SKIP       (snb-x220t)
        Subgroup prune-stale-modes:
                skip       -> PASS       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (skl-nuci5)
                pass       -> DMESG-WARN (skl-i7k-2)
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (hsw-gt2)
                pass       -> DMESG-WARN (skl-nuci5)
                pass       -> DMESG-WARN (skl-i7k-2)
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (skl-nuci5)
                pass       -> DMESG-WARN (skl-i7k-2)

bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:159  dwarn:0   dfail:0   fail:0   skip:37 
byt-nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:196  pass:179  dwarn:0   dfail:0   fail:0   skip:17 
ilk-hp8440p      total:196  pass:132  dwarn:0   dfail:0   fail:0   skip:64 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
skl-i7k-2        total:196  pass:169  dwarn:4   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:181  dwarn:4   dfail:0   fail:0   skip:11 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:161  dwarn:0   dfail:0   fail:1   skip:34 
BOOT FAILED for bdw-nuci7

Results at /archive/results/CI_IGT_test/Patchwork_1792/

aedfaaef290af9c8df7d9f4adf22cbe21704d091 drm-intel-nightly: 2016y-04m-04d-13h-09m-54s UTC integration manifest
0856c119319cb46ce75deb40ceb354cfc94a0f3d drm/i915/bxt: Enable runtime PM
c7dc45a16dfd3efb2dcc9faae2713e67bb52f23f Revert "drm/i915/bxt: Disable power well support"
50b663dd828817c64ef4f5d4fc2aa9b28c4177e0 drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
85628341a1f806116d6728ac5955221131f6cdcb drm/i915/bxt: Don't reprogram an already enabled DDI PHY
a4826afc34198a6384fcaace3924b8aa0c4aeca6 drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
053c5d3774a47ac9d35c93b0efaeef9bdc4bab05 drm/i915/bxt: Don't toggle power well 1 on-demand
ed38c6615e2e6f45ab8fd18683c4fa0e19ec614f drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
9c52a0e1eb6caf4315205820d3eed6c82c44fb03 drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
5161e56e9e810ef1fe02f4e8a1b26f577027beff drm/i915/skl: Unexport skl_pw1_misc_io_init
b615884026b3c6e5b26769256e41a104ed57e443 drm/i915/bxt: Suspend power domains during suspend-to-idle
268e9266500fb8fa163df5e864edefd047006cbd drm/i915/gen9: Fix DMC/DC state asserts
8790850ad164b4b9d64824fa918a34f88ebecf1b drm/i915/gen9: Make power well disabling synchronous
a57cdf35ae7c264efec7699d439ab834c6ece96b drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR
5b7b27b56eefe803c55799da91b9aec290d367df drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
d3bb08086ddbb824e230bbec068b12909e2d5fd9 drm/i915/bxt: Fix GRC code register field definitions
d90dbdf335eb4124a7e9c6952c926f32d4496151 drm/i915/bxt: Reject DMC firmware versions with known bugs

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Re: [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous

[Patrik Jakobsson]

On Mon, Apr 04, 2016 at 12:34:30PM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> > So far we only power well enabling was synchronous not disabling. Since
> > we don't exactly know how the firmware (both DMC and PCU) synchronizes
> > against the actual power well state during DC transitions, make the
> > disabling also synchronous.
> > 
> > CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

Perhaps I was too quick with the review. I'm getting timeouts when trying to
disable MISC IO and PW1 on SKL. Need to have a closer look at what's going on
here.

-Patrik

> 
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index d20fd8f..f5f6e89 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> >  
> >  		if (!is_enabled) {
> >  			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > -			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> > -				state_mask), 1))
> > -				DRM_ERROR("%s enable timeout\n",
> > -					power_well->name);
> >  			check_fuse_status = true;
> >  		}
> >  	} else {
> > @@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> >  			bxt_sanitize_power_well_requests(dev_priv, power_well);
> >  	}
> >  
> > +	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> > +		     1))
> > +		DRM_ERROR("%s %s timeout\n",
> > +			  power_well->name, enable ? "enable" : "disable");
> > +
> >  	if (check_fuse_status) {
> >  		if (power_well->data == SKL_DISP_PW_1) {
> >  			if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> > -- 
> > 2.5.0
> > 
> 
> -- 
> ---
> Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
---
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Re: [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous

[Imre Deak]

On ti, 2016-04-05 at 10:26 +0200, Patrik Jakobsson wrote:
> On Mon, Apr 04, 2016 at 12:34:30PM +0200, Patrik Jakobsson wrote:
> > On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> > > So far we only power well enabling was synchronous not disabling.
> > > Since
> > > we don't exactly know how the firmware (both DMC and PCU)
> > > synchronizes
> > > against the actual power well state during DC transitions, make
> > > the
> > > disabling also synchronous.
> > > 
> > > CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> 
> Perhaps I was too quick with the review. I'm getting timeouts when
> trying to
> disable MISC IO and PW1 on SKL. Need to have a closer look at what's
> going on
> here.

The problem is the same that I fixed already on BXT in 04/16. The
firmware doesn't properly save/restore the request bits for these power
wells. It's an existing issue, so good that we found it. I'll follow up
with an updated version of patch 4 that addresses this on SKL as well.

--Imre

> 
> -Patrik
> 
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++----
> > >  1 file changed, 5 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index d20fd8f..f5f6e89 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -720,10 +720,6 @@ static void skl_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > >  
> > >  		if (!is_enabled) {
> > >  			DRM_DEBUG_KMS("Enabling %s\n",
> > > power_well->name);
> > > -			if
> > > (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> > > -				state_mask), 1))
> > > -				DRM_ERROR("%s enable timeout\n",
> > > -					power_well->name);
> > >  			check_fuse_status = true;
> > >  		}
> > >  	} else {
> > > @@ -737,6 +733,11 @@ static void skl_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > >  			bxt_sanitize_power_well_requests(dev_pri
> > > v, power_well);
> > >  	}
> > >  
> > > +	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) &
> > > state_mask) == enable,
> > > +		     1))
> > > +		DRM_ERROR("%s %s timeout\n",
> > > +			  power_well->name, enable ? "enable" :
> > > "disable");
> > > +
> > >  	if (check_fuse_status) {
> > >  		if (power_well->data == SKL_DISP_PW_1) {
> > >  			if (wait_for((I915_READ(SKL_FUSE_STATUS)
> > > &
> > > -- 
> > > 2.5.0
> > > 
> > 
> > -- 
> > ---
> > Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40
> > Kista, Stockholm, Sweden Registration Number: 556189-6027 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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[PATCH v2 04/16] drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR

[Imre Deak]

DMC forces on power well 1 and the misc IO power well by setting the
corresponding request bits both in the BIOS and the DEBUG power well
request registers. This is somewhat unexpected since the firmware should
really just save and restore state but not alter it. We also depend on
being able to disable power well 1, and the misc IO power well before
entering S3/S4 on BXT and SKL or entering DC9 on BXT. To fix this make
sure these request bits are cleared whenever we want to disable the
given power wells.

On SKL there is another twist where the firmware also clears the power
well 1 request bit in HSW_POWER_WELL_DRIVER (but not that of the misc IO
power well). This happens to not cause a problem due to the forced-on
request bits in the other request registers.

I've filed a bug about all this, but fixing that may take a while and
having this sanity check in place makes sense even for future firmware
versions.

At the same time also check the KVMR request bits. I haven't seen this
being altered, but we don't expect any request bits in here either, so
sanitize this register as well.

v2:
- apply the workaround on SKL as well

CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d189a00..6ffa6ad 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -630,6 +630,44 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
+static void
+gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
+				  struct i915_power_well *power_well)
+{
+	enum skl_disp_power_wells power_well_id = power_well->data;
+	u32 val;
+	u32 mask;
+
+	mask = SKL_POWER_WELL_REQ(power_well_id);
+
+	val = I915_READ(HSW_PWR_WELL_KVMR);
+	if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
+				   power_well->name))
+		I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
+
+	val = I915_READ(HSW_PWR_WELL_BIOS);
+	val |= I915_READ(HSW_PWR_WELL_DEBUG);
+
+	if (!(val & mask))
+		return;
+
+	/*
+	 * DMC is known to force on the request bits for power well 1 on SKL
+	 * and BXT and the misc IO power well on SKL but we don't expect any
+	 * other request bits to be set, so WARN for those.
+	 */
+	if (power_well_id == SKL_DISP_PW_1 ||
+	    (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
+		DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
+				 "by DMC\n", power_well->name);
+	else
+		WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
+			  power_well->name);
+
+	I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
+	I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
+}
+
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			struct i915_power_well *power_well, bool enable)
 {
@@ -696,6 +734,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			POSTING_READ(HSW_PWR_WELL_DRIVER);
 			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 		}
+
+		if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+			gen9_sanitize_power_well_requests(dev_priv, power_well);
 	}
 
 	if (check_fuse_status) {
-- 
2.5.0

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✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5)
URL   : https://patchwork.freedesktop.org/series/5177/
State : success

== Summary ==

Series 5177v5 drm/i915/bxt: Fix/enable display power well support/runtime PM
http://patchwork.freedesktop.org/api/1.0/series/5177/revisions/5/mbox/

Test core_auth:
        Subgroup basic-auth:
                incomplete -> PASS       (bdw-nuci7)
Test drv_getparams_basic:
        Subgroup basic-eu-total:
                incomplete -> PASS       (bdw-nuci7)
Test drv_module_reload_basic:
                fail       -> PASS       (snb-dellxps)
                skip       -> PASS       (skl-nuci5)
Test gem_basic:
        Subgroup create-close:
                incomplete -> PASS       (bdw-nuci7)
Test gem_ctx_create:
        Subgroup basic:
                incomplete -> PASS       (bdw-nuci7)
Test gem_ctx_param_basic:
        Subgroup basic-default:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup invalid-ctx-get:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup invalid-ctx-set:
                incomplete -> PASS       (bdw-nuci7)
Test gem_exec_basic:
        Subgroup basic-blt:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup gtt-bsd1:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup readonly-bsd:
                incomplete -> PASS       (bdw-nuci7)
Test gem_exec_parse:
        Subgroup basic-rejected:
                incomplete -> SKIP       (bdw-nuci7)
Test gem_exec_store:
        Subgroup basic-render:
                incomplete -> PASS       (bdw-nuci7)
Test gem_exec_suspend:
        Subgroup basic-s4:
                fail       -> SKIP       (snb-dellxps)
Test gem_mmap_gtt:
        Subgroup basic-read-no-prefault:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-small-bo:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-small-copy-xy:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-write-gtt:
                incomplete -> PASS       (bdw-nuci7)
Test gem_render_linear_blits:
        Subgroup basic:
                incomplete -> PASS       (bdw-nuci7)
Test gem_ringfill:
        Subgroup basic-default-forked:
                incomplete -> PASS       (bdw-nuci7)
Test gem_storedw_loop:
        Subgroup basic-blt:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-bsd2:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-render:
                incomplete -> PASS       (bdw-nuci7) UNSTABLE
Test gem_sync:
        Subgroup basic-bsd1:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup basic-render:
                incomplete -> PASS       (bdw-nuci7) UNSTABLE
        Subgroup basic-vebox:
                incomplete -> PASS       (bdw-nuci7)
Test kms_addfb_basic:
        Subgroup addfb25-x-tiled:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup addfb25-x-tiled-mismatch:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup bad-pitch-0:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup bo-too-small-due-to-tiling:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup unused-handle:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup unused-modifier:
                incomplete -> PASS       (bdw-nuci7)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (byt-nuc)
Test kms_force_connector_basic:
        Subgroup force-edid:
                incomplete -> SKIP       (bdw-nuci7)
        Subgroup force-load-detect:
                incomplete -> SKIP       (bdw-nuci7)
Test kms_pipe_crc_basic:
        Subgroup nonblocking-crc-pipe-a:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup nonblocking-crc-pipe-b:
                incomplete -> PASS       (bdw-nuci7)
        Subgroup read-crc-pipe-c-frame-sequence:
                incomplete -> PASS       (bdw-nuci7)
Test kms_setmode:
        Subgroup basic-clone-single-crtc:
                incomplete -> PASS       (bdw-nuci7)
Test kms_sink_crc_basic:
                incomplete -> SKIP       (bdw-nuci7)
Test pm_rpm:
        Subgroup basic-rte:
                incomplete -> PASS       (bdw-nuci7)

bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:196  pass:159  dwarn:0   dfail:0   fail:0   skip:37 
byt-nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
ilk-hp8440p      total:196  pass:131  dwarn:1   dfail:0   fail:0   skip:64 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:162  dwarn:0   dfail:0   fail:1   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1799/

16ff3549b531ad5dde6b4526397ddcb511ad946c drm-intel-nightly: 2016y-04m-05d-10h-57m-52s UTC integration manifest
74ded94de63993b98529980cf68db6ecde61ed5b drm/i915/bxt: Enable runtime PM
64f709d5670bd0918434388bb4f539004b11a5d5 Revert "drm/i915/bxt: Disable power well support"
204aecc73fb8fd8fbc758a588a134711783fc53a drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
d64074feb5decdf7751611b040b94d51c0af992a drm/i915/bxt: Don't reprogram an already enabled DDI PHY
90926cc7e8281a7610dc7f15dafa648ab8233596 drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
fe02ee43ddc23ca66423bbb87416691d4847fb91 drm/i915/bxt: Don't toggle power well 1 on-demand
c4f630c150655db366133e8795509b489461d5bf drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
e43a8eb6f86ecb361005a8704d40d64f10914658 drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
67db90d8a64436808af14a5bebfb61bf9855383c drm/i915/skl: Unexport skl_pw1_misc_io_init
87a90697f7f7dd51ec787d4aab1a1eea5a123d85 drm/i915/bxt: Suspend power domains during suspend-to-idle
9c1a2b77e384519d0442a99ae0d752ea82d7ffe7 drm/i915/gen9: Fix DMC/DC state asserts
0ec1dddfebe4185722f65edf5313207c6d21c4e5 drm/i915/gen9: Make power well disabling synchronous
40ce3ac626d495c481b29acb8fe7b6f392c5473c drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR
4685ad6e3b5b54efb6c4f62d364e5cb26fdb5a60 drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
51f8cc5725f92c0c03d54aa54bfc0de37841fb5c drm/i915/bxt: Fix GRC code register field definitions
118cdc7546997a2914927297fa7dbf1bad53297e drm/i915/bxt: Reject DMC firmware versions with known bugs

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Re: [PATCH v2 04/16] drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR

[Patrik Jakobsson]

On Tue, Apr 05, 2016 at 01:26:05PM +0300, Imre Deak wrote:
> DMC forces on power well 1 and the misc IO power well by setting the
> corresponding request bits both in the BIOS and the DEBUG power well
> request registers. This is somewhat unexpected since the firmware should
> really just save and restore state but not alter it. We also depend on
> being able to disable power well 1, and the misc IO power well before
> entering S3/S4 on BXT and SKL or entering DC9 on BXT. To fix this make
> sure these request bits are cleared whenever we want to disable the
> given power wells.
> 
> On SKL there is another twist where the firmware also clears the power
> well 1 request bit in HSW_POWER_WELL_DRIVER (but not that of the misc IO
> power well). This happens to not cause a problem due to the forced-on
> request bits in the other request registers.
> 
> I've filed a bug about all this, but fixing that may take a while and
> having this sanity check in place makes sense even for future firmware
> versions.
> 
> At the same time also check the KVMR request bits. I haven't seen this
> being altered, but we don't expect any request bits in here either, so
> sanitize this register as well.
> 
> v2:
> - apply the workaround on SKL as well
> 
> CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Hmm, more DMC fun.

Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 41 +++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d189a00..6ffa6ad 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -630,6 +630,44 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  }
>  
> +static void
> +gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
> +				  struct i915_power_well *power_well)
> +{
> +	enum skl_disp_power_wells power_well_id = power_well->data;
> +	u32 val;
> +	u32 mask;
> +
> +	mask = SKL_POWER_WELL_REQ(power_well_id);
> +
> +	val = I915_READ(HSW_PWR_WELL_KVMR);
> +	if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
> +				   power_well->name))
> +		I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
> +
> +	val = I915_READ(HSW_PWR_WELL_BIOS);
> +	val |= I915_READ(HSW_PWR_WELL_DEBUG);
> +
> +	if (!(val & mask))
> +		return;
> +
> +	/*
> +	 * DMC is known to force on the request bits for power well 1 on SKL
> +	 * and BXT and the misc IO power well on SKL but we don't expect any
> +	 * other request bits to be set, so WARN for those.
> +	 */
> +	if (power_well_id == SKL_DISP_PW_1 ||
> +	    (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
> +		DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
> +				 "by DMC\n", power_well->name);
> +	else
> +		WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
> +			  power_well->name);
> +
> +	I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
> +	I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
> +}
> +
>  static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			struct i915_power_well *power_well, bool enable)
>  {
> @@ -696,6 +734,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			POSTING_READ(HSW_PWR_WELL_DRIVER);
>  			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>  		}
> +
> +		if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> +			gen9_sanitize_power_well_requests(dev_priv, power_well);
>  	}
>  
>  	if (check_fuse_status) {
> -- 
> 2.5.0
> 

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Re: [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:33PM +0300, Imre Deak wrote:
> This has been corrected in BSpec quite some time ago, but we missed it
> somehow. The wrong field definitions resulted in configuring PHY0 with
> an incorrect GRC value.
> 
> CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6df3c59..f4a91bb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1373,10 +1373,10 @@ enum skl_disp_power_wells {
>   * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
>   * after testing.
>   */

The FIXME can go, no?

Matches my PHY docs as well as bspec now.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> -#define   GRC_CODE_SHIFT		23
> -#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)
> +#define   GRC_CODE_SHIFT		24
> +#define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
>  #define   GRC_CODE_FAST_SHIFT		16
> -#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)
> +#define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
>  #define   GRC_CODE_SLOW_SHIFT		8
>  #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
>  #define   GRC_CODE_NOM_MASK		0xFF
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions

[Imre Deak]

On pe, 2016-04-08 at 20:22 +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 04:02:33PM +0300, Imre Deak wrote:
> > This has been corrected in BSpec quite some time ago, but we missed
> > it
> > somehow. The wrong field definitions resulted in configuring PHY0
> > with
> > an incorrect GRC value.
> > 
> > CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6df3c59..f4a91bb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1373,10 +1373,10 @@ enum skl_disp_power_wells {
> >   * FIXME: BSpec/CHV ConfigDB disagrees on the following two
> > fields, fix them
> >   * after testing.
> >   */
> 
> The FIXME can go, no?

Ah yea will remove it. So we did think about this already earlier..

> Matches my PHY docs as well as bspec now.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > -#define   GRC_CODE_SHIFT		23
> > -#define   GRC_CODE_MASK			(0x1FF <<
> > GRC_CODE_SHIFT)
> > +#define   GRC_CODE_SHIFT		24
> > +#define   GRC_CODE_MASK			(0xFF <<
> > GRC_CODE_SHIFT)
> >  #define   GRC_CODE_FAST_SHIFT		16
> > -#define   GRC_CODE_FAST_MASK		(0x7F <<
> > GRC_CODE_FAST_SHIFT)
> > +#define   GRC_CODE_FAST_MASK		(0xFF <<
> > GRC_CODE_FAST_SHIFT)
> >  #define   GRC_CODE_SLOW_SHIFT		8
> >  #define   GRC_CODE_SLOW_MASK		(0xFF <<
> > GRC_CODE_SLOW_SHIFT)
> >  #define   GRC_CODE_NOM_MASK		0xFF
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> This register is read-only, so we have never actually set
> OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
> comment about this. I filed a specification update request to clarify
> this there.

Hmm. Interesting. It's r/w on my CHV, and the PHY spec agrees. Of course
I can't really tell whether it has any effect on the x1 PHY. If I set it
on the x2 PHY it definitely makes the channel unusable.

> 
> CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> ---
> 
> [ Art, CC'ing you in case you know if this would have an effect on
>   anything. ]
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2758622..f91306e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	 * enabled.
>  	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
>  	 * power down the second channel on PHY0 as well.
> +	 *
> +	 * FIXME: Clarify programming of the following, the register is
> +	 * read-only with bit 6 fixed at 0 at least in stepping A.
>  	 */
>  	if (phy == DPIO_PHY1)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
> -- 
> 2.5.0
> 
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Re: [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote:
> For internal APIs passing dev_priv is preferred to reduce indirections,
> so convert over a few DDI PHY, CDCLK helpers.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c       | 12 ++++--------
>  drivers/gpu/drm/i915/intel_ddi.c      | 10 ++++------
>  drivers/gpu/drm/i915/intel_display.c  | 18 +++++++-----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ++--
>  drivers/gpu/drm/i915/intel_drv.h      |  8 ++++----
>  5 files changed, 21 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aa7df10..3998f6a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when DC5 support is added disable DC5 here. */
>  
> -	broxton_ddi_phy_uninit(dev);
> -	broxton_uninit_cdclk(dev);
> +	broxton_ddi_phy_uninit(dev_priv);
> +	broxton_uninit_cdclk(dev_priv);
>  	bxt_enable_dc9(dev_priv);
>  
>  	return 0;
> @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when CSR FW support is added make sure the FW is loaded */
>  
>  	bxt_disable_dc9(dev_priv);
> @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
>  	 * is available.
>  	 */
> -	broxton_init_cdclk(dev);
> -	broxton_ddi_phy_init(dev);
> +	broxton_init_cdclk(dev_priv);
> +	broxton_ddi_phy_init(dev_priv);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f91306e..29017a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_init(struct drm_device *dev)
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)
>  {
>  	/* Enable PHY1 first since it provides Rcomp for PHY0 */
> -	broxton_phy_init(dev->dev_private, DPIO_PHY1);
> -	broxton_phy_init(dev->dev_private, DPIO_PHY0);
> +	broxton_phy_init(dev_priv, DPIO_PHY1);
> +	broxton_phy_init(dev_priv, DPIO_PHY0);
>  }
>  
>  static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
> @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_uninit(struct drm_device *dev)
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e6b5ee5..d9da89d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev)
>  		intel_update_max_cdclk(dev);
>  }
>  
> -static void broxton_set_cdclk(struct drm_device *dev, int frequency)
> +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t divider;
>  	uint32_t ratio;
>  	uint32_t current_freq;
> @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency)
>  		return;
>  	}
>  
> -	intel_update_cdclk(dev);
> +	intel_update_cdclk(dev_priv->dev);
>  }
>  
> -void broxton_init_cdclk(struct drm_device *dev)
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t val;
>  
>  	/*
> @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev)
>  	 * - check if setting the max (or any) cdclk freq is really necessary
>  	 *   here, it belongs to modeset time
>  	 */
> -	broxton_set_cdclk(dev, 624000);
> +	broxton_set_cdclk(dev_priv, 624000);
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
> @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power enable timeout!\n");
>  }
>  
> -void broxton_uninit_cdclk(struct drm_device *dev)
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
>  
> @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power disable timeout!\n");
>  
>  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> -	broxton_set_cdclk(dev, 19200);
> +	broxton_set_cdclk(dev_priv, 19200);
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  }
> @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  		to_intel_atomic_state(old_state);
>  	unsigned int req_cdclk = old_intel_state->dev_cdclk;
>  
> -	broxton_set_cdclk(dev, req_cdclk);
> +	broxton_set_cdclk(to_i915(dev), req_cdclk);
>  }
>  
>  /* compute the max rate for new configuration */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1175eeb..fbe88b8 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
>  	} else if (IS_BROXTON(dev)) {
> -		broxton_init_cdclk(dev);
> -		broxton_ddi_phy_init(dev);
> +		broxton_init_cdclk(dev_priv);
> +		broxton_ddi_phy_init(dev_priv);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8ba2ac3..e8843a7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev);
>  void intel_finish_reset(struct drm_device *dev);
>  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> -void broxton_init_cdclk(struct drm_device *dev);
> -void broxton_uninit_cdclk(struct drm_device *dev);
> -void broxton_ddi_phy_init(struct drm_device *dev);
> -void broxton_ddi_phy_uninit(struct drm_device *dev);
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:41PM +0300, Imre Deak wrote:
> The power-down step logically belongs to the individual PHY uninit
> sequence so move it there. The only functional change is that we will
> power down now PHY 1 separately before PHY 0 and preserve the other bits
> in the register which are defined as reserved.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 29017a4..d16effd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1849,15 +1849,16 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
>  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
>  	val &= ~COMMON_RESET_DIS;
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> +
> +	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> +	val &= ~GT_DISPLAY_POWER_ON(phy);
> +	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>  }
>  
>  void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  {
>  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
> -
> -	/* FIXME: do this in broxton_phy_uninit per phy */
> -	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
>  }
>  
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:42PM +0300, Imre Deak wrote:
> Power well 1 is managed by the DMC firmware so don't toggle it on-demand
> from the driver. This means we need to follow the BSpec display
> initialization sequence during driver loading and resuming (both system
> and runtime) and enable power well 1 only once there. Afterwards DMC
> will toggle power well 1 whenever entering/exiting DC5.
> 
> For this to work we also need to do away getting the PLL power domain,
> since that just kept runtime PM disabled for good.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Make it more like SKL (which also needs more work in this area,
but that's another matter).

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c         | 15 +------
>  drivers/gpu/drm/i915/intel_display.c    | 17 --------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  5 +--
>  drivers/gpu/drm/i915/intel_drv.h        |  2 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 75 +++++++++++++++++++++++++++------
>  5 files changed, 66 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3998f6a..3f56ddf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1070,10 +1070,7 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  {
> -	/* TODO: when DC5 support is added disable DC5 here. */
> -
> -	broxton_ddi_phy_uninit(dev_priv);
> -	broxton_uninit_cdclk(dev_priv);
> +	bxt_display_core_uninit(dev_priv);
>  	bxt_enable_dc9(dev_priv);
>  
>  	return 0;
> @@ -1081,16 +1078,8 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  {
> -	/* TODO: when CSR FW support is added make sure the FW is loaded */
> -
>  	bxt_disable_dc9(dev_priv);
> -
> -	/*
> -	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
> -	 * is available.
> -	 */
> -	broxton_init_cdclk(dev_priv);
> -	broxton_ddi_phy_init(dev_priv);
> +	bxt_display_core_init(dev_priv, true);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d9da89d..1fbe619 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5442,21 +5442,6 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	uint32_t val;
> -
> -	/*
> -	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> -	 * or else the reset will hang because there is no PCH to respond.
> -	 * Move the handshake programming to initialization sequence.
> -	 * Previously was left up to BIOS.
> -	 */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> -
> -	/* Enable PG1 for cdclk */
> -	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> -
>  	/* check if cd clock is enabled */
>  	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
>  		DRM_DEBUG_KMS("Display already initialized\n");
> @@ -5493,8 +5478,6 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
>  	broxton_set_cdclk(dev_priv, 19200);
> -
> -	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  }
>  
>  static const struct skl_cdclk_entry {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index fbe88b8..a060b67 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1644,10 +1644,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
> -	} else if (IS_BROXTON(dev)) {
> -		broxton_init_cdclk(dev_priv);
> -		broxton_ddi_phy_init(dev_priv);
> -	} else {
> +	} else if (!IS_BROXTON(dev_priv)) {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
>  		 * let's just check its state and print errors in case
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e8843a7..4c2083d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1460,6 +1460,8 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_fini(struct drm_i915_private *);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>  void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> +void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
>  const char *
>  intel_display_power_domain_str(enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 58ed8bc..0c30635 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -419,25 +419,13 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT(POWER_DOMAIN_VGA) |				\
>  	BIT(POWER_DOMAIN_GMBUS) |			\
>  	BIT(POWER_DOMAIN_INIT))
> -#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (		\
> -	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
> -	BIT(POWER_DOMAIN_PIPE_A) |			\
> -	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\
> -	BIT(POWER_DOMAIN_TRANSCODER_DSI_A) |		\
> -	BIT(POWER_DOMAIN_TRANSCODER_DSI_C) |		\
> -	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\
> -	BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |		\
> -	BIT(POWER_DOMAIN_PORT_DSI) |			\
> -	BIT(POWER_DOMAIN_AUX_A) |			\
> -	BIT(POWER_DOMAIN_PLLS) |			\
> -	BIT(POWER_DOMAIN_INIT))
>  #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (		\
>  	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
>  	BIT(POWER_DOMAIN_MODESET) |			\
>  	BIT(POWER_DOMAIN_AUX_A) |			\
>  	BIT(POWER_DOMAIN_INIT))
>  #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
> -	(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
> +	(POWER_DOMAIN_MASK & ~(				\
>  	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> @@ -1930,7 +1918,7 @@ static struct i915_power_well bxt_power_wells[] = {
>  	},
>  	{
>  		.name = "power well 1",
> -		.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
> +		.domains = 0,
>  		.ops = &skl_power_well_ops,
>  		.data = SKL_DISP_PW_1,
>  	},
> @@ -2166,6 +2154,61 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&power_domains->lock);
>  }
>  
> +void bxt_display_core_init(struct drm_i915_private *dev_priv,
> +			   bool resume)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
> +	uint32_t val;
> +
> +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> +	/*
> +	 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> +	 * or else the reset will hang because there is no PCH to respond.
> +	 * Move the handshake programming to initialization sequence.
> +	 * Previously was left up to BIOS.
> +	 */
> +	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +
> +	/* Enable PG1 */
> +	mutex_lock(&power_domains->lock);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_enable(dev_priv, well);
> +
> +	mutex_unlock(&power_domains->lock);
> +
> +	broxton_init_cdclk(dev_priv);
> +	broxton_ddi_phy_init(dev_priv);
> +
> +	if (resume && dev_priv->csr.dmc_payload)
> +		intel_csr_load_program(dev_priv);
> +}
> +
> +void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
> +
> +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> +	broxton_ddi_phy_uninit(dev_priv);
> +	broxton_uninit_cdclk(dev_priv);
> +
> +	/* The spec doesn't call for removing the reset handshake flag */
> +
> +	/* Disable PG1 */
> +	mutex_lock(&power_domains->lock);
> +
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_disable(dev_priv, well);
> +
> +	mutex_unlock(&power_domains->lock);
> +}
> +
>  static void chv_phy_control_init(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_power_well *cmn_bc =
> @@ -2297,6 +2340,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>  
>  	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>  		skl_display_core_init(dev_priv, resume);
> +	} else if (IS_BROXTON(dev)) {
> +		bxt_display_core_init(dev_priv, resume);
>  	} else if (IS_CHERRYVIEW(dev)) {
>  		mutex_lock(&power_domains->lock);
>  		chv_phy_control_init(dev_priv);
> @@ -2334,6 +2379,8 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		skl_display_core_uninit(dev_priv);
> +	else if (IS_BROXTON(dev_priv))
> +		bxt_display_core_uninit(dev_priv);
>  }
>  
>  /**
> -- 
> 2.5.0
> 
> _______________________________________________
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-- 
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Intel OTC
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Re: [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[Imre Deak]

On pe, 2016-04-08 at 21:02 +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> > This register is read-only, so we have never actually set
> > OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a
> > code
> > comment about this. I filed a specification update request to
> > clarify
> > this there.
> 
> Hmm. Interesting. It's r/w on my CHV, and the PHY spec agrees. Of
> course
> I can't really tell whether it has any effect on the x1 PHY. If I set
> it
> on the x2 PHY it definitely makes the channel unusable.

Note that meanwhile the corresponding BSpec change request got updated
to "Confirmed"/"Won't be fixed".

> > CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > ---
> > 
> > [ Art, CC'ing you in case you know if this would have an effect on
> >   anything. ]
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 2758622..f91306e 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct
> > drm_i915_private *dev_priv,
> >  	 * enabled.
> >  	 * TODO: port C is only connected on BXT-P, so on BXT0/1
> > we should
> >  	 * power down the second channel on PHY0 as well.
> > +	 *
> > +	 * FIXME: Clarify programming of the following, the
> > register is
> > +	 * read-only with bit 6 fixed at 0 at least in stepping A.
> >  	 */
> >  	if (phy == DPIO_PHY1)
> >  		val |= OCL2_LDOFUSE_PWR_DIS;
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY

[Ville Syrjälä]

On Fri, Apr 01, 2016 at 04:02:44PM +0300, Imre Deak wrote:
> If BIOS has already programmed and enabled a PHY, don't reprogram it as
> that may interfere with the currently active outputs. A follow-up patch
> will add state verification, so we can catch any misconfiguration on
> BIOS's behalf.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Looks sane.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index d16effd..8f06d6c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1722,12 +1722,52 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>  	}
>  }
>  
> +static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
> +				   enum dpio_phy phy)
> +{
> +	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
> +		return false;
> +
> +	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
> +				 phy);
> +
> +		return false;
> +	}
> +
> +	if (phy == DPIO_PHY1 &&
> +	   !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
> +		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
> +
> +		return false;
> +	}
> +
> +	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
> +				 phy);
> +
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  			     enum dpio_phy phy)
>  {
>  	enum port port;
>  	u32 ports, val;
>  
> +	if (broxton_phy_is_enabled(dev_priv, phy)) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
> +				 "won't reprogram it\n", phy);
> +
> +		return;
> +	}
> +
> +	DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy);
> +
>  	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
>  	val |= GT_DISPLAY_POWER_ON(phy);
>  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[Imre Deak]

On pe, 2016-04-08 at 21:12 +0300, Imre Deak wrote:
> On pe, 2016-04-08 at 21:02 +0300, Ville Syrjälä wrote:
> > On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> > > This register is read-only, so we have never actually set
> > > OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add
> > > a
> > > code
> > > comment about this. I filed a specification update request to
> > > clarify
> > > this there.
> > 
> > Hmm. Interesting. It's r/w on my CHV, and the PHY spec agrees. Of
> > course
> > I can't really tell whether it has any effect on the x1 PHY. If I
> > set
> > it
> > on the x2 PHY it definitely makes the channel unusable.
> 
> Note that meanwhile the corresponding BSpec change request got
> updated
> to "Confirmed"/"Won't be fixed".

Sorry, it's just "Confirmed".

> > > CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > 
> > > ---
> > > 
> > > [ Art, CC'ing you in case you know if this would have an effect
> > > on
> > >   anything. ]
> > > ---
> > >  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 2758622..f91306e 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct
> > > drm_i915_private *dev_priv,
> > >  	 * enabled.
> > >  	 * TODO: port C is only connected on BXT-P, so on BXT0/1
> > > we should
> > >  	 * power down the second channel on PHY0 as well.
> > > +	 *
> > > +	 * FIXME: Clarify programming of the following, the
> > > register is
> > > +	 * read-only with bit 6 fixed at 0 at least in stepping
> > > A.
> > >  	 */
> > >  	if (phy == DPIO_PHY1)
> > >  		val |= OCL2_LDOFUSE_PWR_DIS;
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Re: [PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs

[Mika Kuoppala]

Imre Deak <imre.deak@intel.com> writes:

> [ text/plain ]
> DMC version 1.06 has a known bug, where the firmware polls forever for a port
> PLL to lock, if the PLL was disabled when entering DC5. Version 1.07 fixes
> this, so make that the minimum required version on BXT.
>

If this would be for already released hw, we would need to be
more descriptive about the symptoms. Like 'it hangs the box'.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


> CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 20 +++++++++++++++-----
>  1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 3f57cb9..d57b00e 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -50,6 +50,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
>  MODULE_FIRMWARE(I915_CSR_BXT);
>  
>  #define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)
> +#define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
>  
>  #define CSR_MAX_FW_SIZE			0x2FFF
>  #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
> @@ -281,6 +282,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
>  	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
>  	uint32_t i;
>  	uint32_t *dmc_payload;
> +	uint32_t required_min_version;
>  
>  	if (!fw)
>  		return NULL;
> @@ -296,15 +298,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
>  
>  	csr->version = css_header->version;
>  
> -	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> -	    csr->version < SKL_CSR_VERSION_REQUIRED) {
> -		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
> +	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> +		required_min_version = SKL_CSR_VERSION_REQUIRED;
> +	} else if (IS_BROXTON(dev_priv)) {
> +		required_min_version = BXT_CSR_VERSION_REQUIRED;
> +	} else {
> +		MISSING_CASE(INTEL_REVID(dev_priv));
> +		required_min_version = 0;
> +	}
> +
> +	if (csr->version < required_min_version) {
> +		DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
>  			 " please upgrade to v%u.%u or later"
>  			   " [" FIRMWARE_URL "].\n",
>  			 CSR_VERSION_MAJOR(csr->version),
>  			 CSR_VERSION_MINOR(csr->version),
> -			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
> -			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
> +			 CSR_VERSION_MAJOR(required_min_version),
> +			 CSR_VERSION_MINOR(required_min_version));
>  		return NULL;
>  	}
>  
> -- 
> 2.5.0
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Re: [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK

[Mika Kuoppala]

Imre Deak <imre.deak@intel.com> writes:

> [ text/plain ]
> When determining whether CDCLK is enabled by BIOS and so we should skip
> reprogramming it, we didn't check the related DBUF power request and
> state. In theory BIOS could enable one without the other so check for
> this case and reprogram things if something is amiss.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1fbe619..447d46e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5440,14 +5440,38 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  	intel_update_cdclk(dev_priv->dev);
>  }
>  
> +static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
> +{
> +	if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
> +		return false;
> +
> +	/* TODO: Check for a valid CDCLK rate */
> +

Discussed about the pll lock in irc with Imre. I think pll lock bit
should be included in the sanity inspection here too.

But that can be follow ups.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
> +		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
> +
> +		return false;
> +	}
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
> +		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
> +
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	/* check if cd clock is enabled */
> -	if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
> -		DRM_DEBUG_KMS("Display already initialized\n");
> +	if (broxton_cdclk_is_enabled(dev_priv)) {
> +		DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
>  		return;
>  	}
>  
> +	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
> +
>  	/*
>  	 * FIXME:
>  	 * - The initial CDCLK needs to be read from VBT.
> -- 
> 2.5.0
>
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Re: [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

[David Weinehall]

On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> This register is read-only, so we have never actually set
> OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
> comment about this. I filed a specification update request to clarify
> this there.
> 
> CC: Arthur J Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

> 
> ---
> 
> [ Art, CC'ing you in case you know if this would have an effect on
>   anything. ]
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2758622..f91306e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	 * enabled.
>  	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
>  	 * power down the second channel on PHY0 as well.
> +	 *
> +	 * FIXME: Clarify programming of the following, the register is
> +	 * read-only with bit 6 fixed at 0 at least in stepping A.
>  	 */
>  	if (phy == DPIO_PHY1)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
> -- 
> 2.5.0
> 
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Re: [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers

[David Weinehall]

On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote:
> For internal APIs passing dev_priv is preferred to reduce indirections,
> so convert over a few DDI PHY, CDCLK helpers.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c       | 12 ++++--------
>  drivers/gpu/drm/i915/intel_ddi.c      | 10 ++++------
>  drivers/gpu/drm/i915/intel_display.c  | 18 +++++++-----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ++--
>  drivers/gpu/drm/i915/intel_drv.h      |  8 ++++----
>  5 files changed, 21 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aa7df10..3998f6a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when DC5 support is added disable DC5 here. */
>  
> -	broxton_ddi_phy_uninit(dev);
> -	broxton_uninit_cdclk(dev);
> +	broxton_ddi_phy_uninit(dev_priv);
> +	broxton_uninit_cdclk(dev_priv);
>  	bxt_enable_dc9(dev_priv);
>  
>  	return 0;
> @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when CSR FW support is added make sure the FW is loaded */
>  
>  	bxt_disable_dc9(dev_priv);
> @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
>  	 * is available.
>  	 */
> -	broxton_init_cdclk(dev);
> -	broxton_ddi_phy_init(dev);
> +	broxton_init_cdclk(dev_priv);
> +	broxton_ddi_phy_init(dev_priv);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f91306e..29017a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_init(struct drm_device *dev)
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)
>  {
>  	/* Enable PHY1 first since it provides Rcomp for PHY0 */
> -	broxton_phy_init(dev->dev_private, DPIO_PHY1);
> -	broxton_phy_init(dev->dev_private, DPIO_PHY0);
> +	broxton_phy_init(dev_priv, DPIO_PHY1);
> +	broxton_phy_init(dev_priv, DPIO_PHY0);
>  }
>  
>  static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
> @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_uninit(struct drm_device *dev)
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e6b5ee5..d9da89d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev)
>  		intel_update_max_cdclk(dev);
>  }
>  
> -static void broxton_set_cdclk(struct drm_device *dev, int frequency)
> +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t divider;
>  	uint32_t ratio;
>  	uint32_t current_freq;
> @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency)
>  		return;
>  	}
>  
> -	intel_update_cdclk(dev);
> +	intel_update_cdclk(dev_priv->dev);
>  }
>  
> -void broxton_init_cdclk(struct drm_device *dev)
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t val;
>  
>  	/*
> @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev)
>  	 * - check if setting the max (or any) cdclk freq is really necessary
>  	 *   here, it belongs to modeset time
>  	 */
> -	broxton_set_cdclk(dev, 624000);
> +	broxton_set_cdclk(dev_priv, 624000);
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
> @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power enable timeout!\n");
>  }
>  
> -void broxton_uninit_cdclk(struct drm_device *dev)
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
>  
> @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power disable timeout!\n");
>  
>  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> -	broxton_set_cdclk(dev, 19200);
> +	broxton_set_cdclk(dev_priv, 19200);
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  }
> @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  		to_intel_atomic_state(old_state);
>  	unsigned int req_cdclk = old_intel_state->dev_cdclk;
>  
> -	broxton_set_cdclk(dev, req_cdclk);
> +	broxton_set_cdclk(to_i915(dev), req_cdclk);
>  }
>  
>  /* compute the max rate for new configuration */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1175eeb..fbe88b8 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
>  	} else if (IS_BROXTON(dev)) {
> -		broxton_init_cdclk(dev);
> -		broxton_ddi_phy_init(dev);
> +		broxton_init_cdclk(dev_priv);
> +		broxton_ddi_phy_init(dev_priv);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8ba2ac3..e8843a7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev);
>  void intel_finish_reset(struct drm_device *dev);
>  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> -void broxton_init_cdclk(struct drm_device *dev);
> -void broxton_uninit_cdclk(struct drm_device *dev);
> -void broxton_ddi_phy_init(struct drm_device *dev);
> -void broxton_ddi_phy_uninit(struct drm_device *dev);
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> -- 
> 2.5.0
> 
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Re: [PATCH v3 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK

[David Weinehall]

On Mon, Apr 04, 2016 at 05:27:10PM +0300, Imre Deak wrote:
> I caught a few errors in our current PHY/CDCLK programming by sanity
> checking the actual programmed state, so I thought it would be also
> useful for the future. In addition to verifying the state after
> programming it also verify it after exiting DC5, to make sure DMC
> restored/kept intact everything related.
> 
> v2:
> - Inlining __phy_reg_verify_state() doesn't make sense and also
>   incorrect, so don't do it (PW/CI gcc)
> v3:
> - Rebase on latest -nightly
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h         |   1 +
>  drivers/gpu/drm/i915/intel_ddi.c        | 124 +++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_display.c    |   5 ++
>  drivers/gpu/drm/i915/intel_drv.h        |   2 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c |   8 +++
>  5 files changed, 138 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd18772..6f4a721 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1908,6 +1908,7 @@ struct drm_i915_private {
>  	 * crappiness (can't read out DPLL_MD for pipes B & C).
>  	 */
>  	u32 chv_dpll_md[I915_MAX_PIPES];
> +	u32 bxt_phy_grc;
>  
>  	u32 suspend_count;
>  	bool suspended_to_idle;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index d944bff..fd20119 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1753,6 +1753,13 @@ static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
>  	return true;
>  }
>  
> +static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +{
> +	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
> +
> +	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
> +}
> +
>  static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  			     enum dpio_phy phy)
>  {
> @@ -1762,6 +1769,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	if (broxton_phy_is_enabled(dev_priv, phy)) {
>  		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
>  				 "won't reprogram it\n", phy);
> +		/* Still read out the GRC value for state verification */
> +		if (phy == DPIO_PHY1)
> +			dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);
>  
>  		return;
>  	}
> @@ -1857,8 +1867,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  			     10))
>  			DRM_ERROR("timeout waiting for PHY1 GRC\n");
>  
> -		val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
> -		val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
> +		val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,
> +							      DPIO_PHY1);
>  		grc_code = val << GRC_CODE_FAST_SHIFT |
>  			   val << GRC_CODE_SLOW_SHIFT |
>  			   val;
> @@ -1901,6 +1911,116 @@ void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
>  }
>  
> +static bool __printf(6, 7)
> +__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> +		       i915_reg_t reg, u32 mask, u32 expected,
> +		       const char *reg_fmt, ...)
> +{
> +	struct va_format vaf;
> +	va_list args;
> +	u32 val;
> +
> +	val = I915_READ(reg);
> +	if ((val & mask) == expected)
> +		return true;
> +
> +	va_start(args, reg_fmt);
> +	vaf.fmt = reg_fmt;
> +	vaf.va = &args;
> +
> +	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
> +			 "current %08x, expected %08x (mask %08x)\n",
> +			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
> +			 mask);
> +
> +	va_end(args);
> +
> +	return false;
> +}
> +
> +static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
> +				     enum dpio_phy phy)
> +{
> +	enum port port;
> +	u32 ports;
> +	uint32_t mask;
> +	bool ok;
> +
> +#define _CHK(reg, mask, exp, fmt, ...)					\
> +	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
> +			       ## __VA_ARGS__)
> +
> +	/* We expect the PHY to be always enabled */
> +	if (!broxton_phy_is_enabled(dev_priv, phy))
> +		return false;
> +
> +	ok = true;
> +
> +	if (phy == DPIO_PHY0)
> +		ports = BIT(PORT_B) | BIT(PORT_C);
> +	else
> +		ports = BIT(PORT_A);
> +
> +	for_each_port_masked(port, ports) {
> +		int lane;
> +
> +		for (lane = 0; lane < 4; lane++)
> +			ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane),
> +				    LATENCY_OPTIM,
> +				    lane != 1 ? LATENCY_OPTIM : 0,
> +				    "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane);
> +	}
> +
> +	/* PLL Rcomp code offset */
> +	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
> +		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
> +		    "BXT_PORT_CL1CM_DW9(%d)", phy);
> +	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
> +		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
> +		    "BXT_PORT_CL1CM_DW10(%d)", phy);
> +
> +	/* Power gating */
> +	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
> +	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
> +		    "BXT_PORT_CL1CM_DW28(%d)", phy);
> +
> +	if (phy == DPIO_PHY0)
> +		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
> +			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
> +			   "BXT_PORT_CL2CM_DW6_BC");
> +
> +	/*
> +	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
> +	 * at least on stepping A this bit is read-only and fixed at 0.
> +	 */
> +
> +	if (phy == DPIO_PHY0) {
> +		u32 grc_code = dev_priv->bxt_phy_grc;
> +
> +		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
> +		           grc_code << GRC_CODE_SLOW_SHIFT |
> +			   grc_code;
> +		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
> +		       GRC_CODE_NOM_MASK;
> +		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
> +			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
> +
> +		mask = GRC_DIS | GRC_RDY_OVRD;
> +		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
> +			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
> +	}
> +
> +	return ok;
> +#undef _CHK
> +}
> +
> +void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv)
> +{
> +	if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) ||
> +	    !broxton_phy_verify_state(dev_priv, DPIO_PHY1))
> +		i915_report_error(dev_priv, "DDI PHY state mismatch\n");
> +}
> +
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8999fe8..842ca5d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5460,6 +5460,11 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
>  	return true;
>  }
>  
> +bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
> +{
> +	return broxton_cdclk_is_enabled(dev_priv);
> +}
> +
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	/* check if cd clock is enabled */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4c2083d..4708c49 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1224,8 +1224,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv);
>  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> +bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
>  void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
>  void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e60b02e..59b30c9 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -797,6 +797,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>  					  struct i915_power_well *power_well)
>  {
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> +	if (IS_BROXTON(dev_priv)) {
> +		broxton_cdclk_verify_state(dev_priv);
> +		broxton_ddi_phy_verify_state(dev_priv);
> +	}
>  }
>  
>  static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> @@ -2184,6 +2189,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  	broxton_init_cdclk(dev_priv);
>  	broxton_ddi_phy_init(dev_priv);
>  
> +	broxton_cdclk_verify_state(dev_priv);
> +	broxton_ddi_phy_verify_state(dev_priv);
> +
>  	if (resume && dev_priv->csr.dmc_payload)
>  		intel_csr_load_program(dev_priv);
>  }
> -- 
> 2.5.0
> 
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Re: [PATCH 16/16] drm/i915/bxt: Enable runtime PM

[David Weinehall]

On Fri, Apr 01, 2016 at 04:02:47PM +0300, Imre Deak wrote:
> With the preceding fixes runtime PM should be functional, I could
> runtime suspend/resume the device without problems.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0449ebf..099cdee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
>  				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
>  				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> -				 IS_KABYLAKE(dev))
> +				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>  
> -- 
> 2.5.0
> 
> _______________________________________________
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Re: [PATCH 15/16] Revert "drm/i915/bxt: Disable power well support"

[David Weinehall]

On Fri, Apr 01, 2016 at 04:02:46PM +0300, Imre Deak wrote:
> With the preceding fixes power well support should be functional on
> Broxton, I could enter/exit DC5 without problems.
> 
> This reverts commit 18024199579882265653bfe9e2b1a3dcb5697cd9.
> 
> CC: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

Great work!

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 342f997..4441734 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1948,11 +1948,6 @@ sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  	if (disable_power_well >= 0)
>  		return !!disable_power_well;
>  
> -	if (IS_BROXTON(dev_priv)) {
> -		DRM_DEBUG_KMS("Disabling display power well support\n");
> -		return 0;
> -	}
> -
>  	return 1;
>  }
>  
> -- 
> 2.5.0
> 
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Re: ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5)

[Imre Deak]

On ti, 2016-04-05 at 12:19 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/bxt: Fix/enable display power well support/runtime
> PM (rev5)
> URL   : https://patchwork.freedesktop.org/series/5177/
> State : success

Thanks for the reviews, I pushed the patchset to -dinq.

As agreed during the review I also updated the commit message of
patches 1,8 and removed the code comment that became stale from patch
2.

--Imre

> 
> == Summary ==
> 
> Series 5177v5 drm/i915/bxt: Fix/enable display power well
> support/runtime PM
> http://patchwork.freedesktop.org/api/1.0/series/5177/revisions/5/mbox
> /
> 
> Test core_auth:
>         Subgroup basic-auth:
>                 incomplete -> PASS       (bdw-nuci7)
> Test drv_getparams_basic:
>         Subgroup basic-eu-total:
>                 incomplete -> PASS       (bdw-nuci7)
> Test drv_module_reload_basic:
>                 fail       -> PASS       (snb-dellxps)
>                 skip       -> PASS       (skl-nuci5)
> Test gem_basic:
>         Subgroup create-close:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_ctx_create:
>         Subgroup basic:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_ctx_param_basic:
>         Subgroup basic-default:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup invalid-ctx-get:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup invalid-ctx-set:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_exec_basic:
>         Subgroup basic-blt:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup gtt-bsd1:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup readonly-bsd:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_exec_parse:
>         Subgroup basic-rejected:
>                 incomplete -> SKIP       (bdw-nuci7)
> Test gem_exec_store:
>         Subgroup basic-render:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_exec_suspend:
>         Subgroup basic-s4:
>                 fail       -> SKIP       (snb-dellxps)
> Test gem_mmap_gtt:
>         Subgroup basic-read-no-prefault:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-small-bo:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-small-copy-xy:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-write-gtt:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_render_linear_blits:
>         Subgroup basic:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_ringfill:
>         Subgroup basic-default-forked:
>                 incomplete -> PASS       (bdw-nuci7)
> Test gem_storedw_loop:
>         Subgroup basic-blt:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-bsd2:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-render:
>                 incomplete -> PASS       (bdw-nuci7) UNSTABLE
> Test gem_sync:
>         Subgroup basic-bsd1:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup basic-render:
>                 incomplete -> PASS       (bdw-nuci7) UNSTABLE
>         Subgroup basic-vebox:
>                 incomplete -> PASS       (bdw-nuci7)
> Test kms_addfb_basic:
>         Subgroup addfb25-x-tiled:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup addfb25-x-tiled-mismatch:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup bad-pitch-0:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup bo-too-small-due-to-tiling:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup unused-handle:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup unused-modifier:
>                 incomplete -> PASS       (bdw-nuci7)
> Test kms_flip:
>         Subgroup basic-flip-vs-dpms:
>                 pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE
>         Subgroup basic-flip-vs-wf_vblank:
>                 fail       -> PASS       (byt-nuc)
> Test kms_force_connector_basic:
>         Subgroup force-edid:
>                 incomplete -> SKIP       (bdw-nuci7)
>         Subgroup force-load-detect:
>                 incomplete -> SKIP       (bdw-nuci7)
> Test kms_pipe_crc_basic:
>         Subgroup nonblocking-crc-pipe-a:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup nonblocking-crc-pipe-b:
>                 incomplete -> PASS       (bdw-nuci7)
>         Subgroup read-crc-pipe-c-frame-sequence:
>                 incomplete -> PASS       (bdw-nuci7)
> Test kms_setmode:
>         Subgroup basic-clone-single-crtc:
>                 incomplete -> PASS       (bdw-nuci7)
> Test kms_sink_crc_basic:
>                 incomplete -> SKIP       (bdw-nuci7)
> Test pm_rpm:
>         Subgroup basic-rte:
>                 incomplete -> PASS       (bdw-nuci7)
> 
> bdw-
> nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:1
> 2 
> bdw-
> ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:2
> 1 
> bsw-nuc-
> 2        total:196  pass:159  dwarn:0   dfail:0   fail:0   skip:37 
> byt-
> nuc          total:196  pass:161  dwarn:0   dfail:0   fail:0   skip:3
> 5 
> hsw-
> brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:2
> 2 
> ilk-
> hp8440p      total:196  pass:131  dwarn:1   dfail:0   fail:0   skip:6
> 4 
> ivb-
> t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:2
> 5 
> skl-i7k-
> 2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
> skl-
> nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:1
> 1 
> snb-
> dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:3
> 4 
> snb-
> x220t        total:196  pass:162  dwarn:0   dfail:0   fail:1   skip:3
> 3 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1799/
> 
> 16ff3549b531ad5dde6b4526397ddcb511ad946c drm-intel-nightly: 2016y-
> 04m-05d-10h-57m-52s UTC integration manifest
> 74ded94de63993b98529980cf68db6ecde61ed5b drm/i915/bxt: Enable runtime
> PM
> 64f709d5670bd0918434388bb4f539004b11a5d5 Revert "drm/i915/bxt:
> Disable power well support"
> 204aecc73fb8fd8fbc758a588a134711783fc53a drm/i915/bxt: Add HW state
> verification for DDI PHY and CDCLK
> d64074feb5decdf7751611b040b94d51c0af992a drm/i915/bxt: Don't
> reprogram an already enabled DDI PHY
> 90926cc7e8281a7610dc7f15dafa648ab8233596 drm/i915/bxt: Sanitize the
> DBUF HW state together with CDCLK
> fe02ee43ddc23ca66423bbb87416691d4847fb91 drm/i915/bxt: Don't toggle
> power well 1 on-demand
> c4f630c150655db366133e8795509b489461d5bf drm/i915/bxt: Power down DDI
> PHYs separately during the per PHY uninit
> e43a8eb6f86ecb361005a8704d40d64f10914658 drm/i915/bxt: Pass
> drm_i915_private to DDI PHY, CDCLK helpers
> 67db90d8a64436808af14a5bebfb61bf9855383c drm/i915/skl: Unexport
> skl_pw1_misc_io_init
> 87a90697f7f7dd51ec787d4aab1a1eea5a123d85 drm/i915/bxt: Suspend power
> domains during suspend-to-idle
> 9c1a2b77e384519d0442a99ae0d752ea82d7ffe7 drm/i915/gen9: Fix DMC/DC
> state asserts
> 0ec1dddfebe4185722f65edf5313207c6d21c4e5 drm/i915/gen9: Make power
> well disabling synchronous
> 40ce3ac626d495c481b29acb8fe7b6f392c5473c drm/i915/gen9: Reset
> secondary power well requests left on by DMC/KVMR
> 4685ad6e3b5b54efb6c4f62d364e5cb26fdb5a60 drm/i915/bxt: Add a note
> about BXT_PORT_CL1CM_DW30 being read-only
> 51f8cc5725f92c0c03d54aa54bfc0de37841fb5c drm/i915/bxt: Fix GRC code
> register field definitions
> 118cdc7546997a2914927297fa7dbf1bad53297e drm/i915/bxt: Reject DMC
> firmware versions with known bugs
> 
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