[PATCH 0026/1529] Fix typo

* [PATCH 0026/1529] Fix typo
@ 2016-05-21 11:38 Andrea Gelmini
  0 siblings, 0 replies; only message in thread
From: Andrea Gelmini @ 2016-05-21 11:38 UTC (permalink / raw)
  To: andrea.gelmini-PT7Us6ch6G9eoWH0uzbU5w
  Cc: trivial-DgEjT+Ai2ygdnm+yROfE0A, dt-DgEjT+Ai2ygdnm+yROfE0A,
	pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
	devicetree-KcIKpvwj1kUDXYZnReoRVg, galak-sgV2jX0FEOL9JmXXK+q4OQ,
	computersforpeace-Re5JQEeQqe8AvxtiuMwx3w, sr-ynQEQJNshbs,
	devicetree-u79uwXL29TY76Z2rM5mHXA

Signed-off-by: Andrea Gelmini <andrea.gelmini-PT7Us6ch6G9eoWH0uzbU5w@public.gmane.org>
---
 Documentation/devicetree/bindings/mtd/fsmc-nand.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index 32636eb..3fb682f 100644
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -13,7 +13,7 @@ Optional properties:
 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
   are:
   byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
-                 are valid. Zero means one clockcycle, 15 means 16 clock
+                 are valid. Zero means one clock cycle, 15 means 16 clock
                  cycles.
   byte 1 TAR   : ALE to RE delay, 4 bits are valid. Same format as TCLR.
   byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
-- 
2.8.2.534.g1f66975

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply related	[flat|nested] only message in thread