[PATCH 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC submission

[PATCH 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC submission

[Sagar Arun Kamble]

On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT
expired interrupt (bit 9). Host turbo also updates this register
in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
ARAT timer interrupt is needed in GuC for various features. It also
facilitates halting GuC and hence achieving RC6. PM interrupt routing
will not impact RPS interrupt reception by host as GuC will redirect
them.
This patch fixes igt test pm_rc6_residency. Tested with SKL GuC v6.1
and BXT GuC v5.1 and v8.7.

Cc: Chris Harris <chris.harris@intel.com>
Cc: Zhe Wang <zhe1.wang@intel.com>
Cc: Deepak S <deepak.s@intel.com>
Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  8 ++++++++
 drivers/gpu/drm/i915/i915_irq.c            | 14 ++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h            |  3 ++-
 drivers/gpu/drm/i915/intel_guc.h           |  3 +++
 drivers/gpu/drm/i915/intel_guc_loader.c    |  2 ++
 drivers/gpu/drm/i915/intel_pm.c            | 16 +++++++++++++++-
 6 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 169242a..4749588 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -941,6 +941,14 @@ void i915_guc_submission_disable(struct drm_device *dev)
 	guc->execbuf_client = NULL;
 }
 
+void i915_guc_get_pm_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_guc *guc = &dev_priv->guc;
+
+	guc->pm_intr_mask = I915_READ(GEN6_PMINTRMSK);
+}
+
 void i915_guc_submission_fini(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0d9414..25c0b192 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -364,6 +364,8 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 
 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+
 	/*
 	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 	 * if GEN6_PM_UP_EI_EXPIRED is masked.
@@ -373,8 +375,16 @@ u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 
-	if (INTEL_INFO(dev_priv)->gen >= 8)
-		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	/*
+	 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+	 * interrupt based on mask set by GuC.
+	*/
+	if (INTEL_INFO(dev_priv)->gen >= 8) {
+		if (guc->pm_intr_mask & GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+			mask &= guc->pm_intr_mask | ~GEN8_ARAT_EXPIRED_INT_MASK;
+		else
+			mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	}
 
 	return mask;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86fbf72..98c20d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7030,7 +7030,8 @@ enum skl_disp_power_wells {
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
 #define GEN6_PMINTRMSK				_MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_ARAT_EXPIRED_INT_MASK		(1<<9)
 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9d79c4c..65904ab 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -135,6 +135,8 @@ struct intel_guc {
 
 	uint64_t submissions[GUC_MAX_ENGINES_NUM];
 	uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
+
+	uint32_t pm_intr_mask;
 };
 
 /* intel_guc_loader.c */
@@ -151,6 +153,7 @@ int i915_guc_submission_enable(struct drm_device *dev);
 int i915_guc_submit(struct i915_guc_client *client,
 		    struct drm_i915_gem_request *rq);
 void i915_guc_submission_disable(struct drm_device *dev);
+void i915_guc_get_pm_state(struct drm_device *dev);
 void i915_guc_submission_fini(struct drm_device *dev);
 int i915_guc_wq_check_space(struct i915_guc_client *client);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e1..33c6046 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -476,6 +476,8 @@ int intel_guc_ucode_load(struct drm_device *dev)
 		/* The execbuf_client will be recreated. Release it first. */
 		i915_guc_submission_disable(dev);
 
+		i915_guc_get_pm_state(dev);
+
 		err = i915_guc_submission_enable(dev);
 		if (err)
 			goto fail;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..c5e2311 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4708,6 +4708,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	struct intel_guc *guc = &dev_priv->guc;
+	u32 mask = 0xffffffff;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -4715,7 +4718,18 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 		else
 			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 		dev_priv->rps.last_adj = 0;
-		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+
+		/*
+		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+		 * interrupt based on mask set by GuC.
+		*/
+		if (INTEL_INFO(dev_priv)->gen >= 8) {
+			if (guc->pm_intr_mask & GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+				mask &= guc->pm_intr_mask | ~GEN8_ARAT_EXPIRED_INT_MASK;
+			else
+				mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+		}
+		I915_WRITE(GEN6_PMINTRMSK, mask);
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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Re: [PATCH 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC submission

[Chris Wilson]

On Mon, May 30, 2016 at 03:22:31PM +0530, Sagar Arun Kamble wrote:
> On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT
> expired interrupt (bit 9). Host turbo also updates this register
> in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
> ARAT timer interrupt is needed in GuC for various features. It also
> facilitates halting GuC and hence achieving RC6. PM interrupt routing
> will not impact RPS interrupt reception by host as GuC will redirect
> them.
> This patch fixes igt test pm_rc6_residency. Tested with SKL GuC v6.1
> and BXT GuC v5.1 and v8.7.

i915_irq/intel_pm do not want to be mucking around inside intel_guc.

Move the mask to dev_priv->rps, have it initialised during early irq
setup and modify the mask when guc loads (presumably also triggering a
resanitize just in case).
-Chris

-- 
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[PATCH v2 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Sagar Arun Kamble]

On Loading, GuC sets PM interrupts routing (bit 31) and unmasks ARAT
expired interrupt (bit 9). Host turbo also updates this register
in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
ARAT timer interrupt is needed in GuC for various features. It also
facilitates halting GuC and hence achieving RC6. PM interrupt routing
will not impact RPS interrupt reception by host as GuC will redirect
them.
This patch fixes igt test pm_rc6_residency that was failing with guc
load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.

v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)

Cc: Chris Harris <chris.harris@intel.com>
Cc: Zhe Wang <zhe1.wang@intel.com>
Cc: Deepak S <deepak.s@intel.com>
Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  2 ++
 drivers/gpu/drm/i915/i915_irq.c         | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h         |  3 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c |  2 ++
 drivers/gpu/drm/i915/intel_pm.c         | 17 ++++++++++++++++-
 5 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f0b02..38535d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1132,6 +1132,8 @@ struct intel_gen6_power_mgmt {
 	bool interrupts_enabled;
 	u32 pm_iir;
 
+	u32 pm_intr_mask;
+
 	/* Frequencies are stored in potentially platform dependent multiples.
 	 * In other words, *_freq needs to be multiplied by X to be interesting.
 	 * Soft limits are those which are used for the dynamic reclocking done
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0d9414..85086d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -373,8 +373,18 @@ u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 
-	if (INTEL_INFO(dev_priv)->gen >= 8)
-		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	/*
+	 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+	 * interrupt based on mask set by GuC.
+	*/
+	if (INTEL_INFO(dev_priv)->gen >= 8) {
+		if (dev_priv->rps.pm_intr_mask &
+		    GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+			mask &= dev_priv->rps.pm_intr_mask |
+				~GEN8_ARAT_EXPIRED_INT_MASK;
+		else
+			mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	}
 
 	return mask;
 }
@@ -4580,6 +4590,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	else
 		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
 
+	dev_priv->rps.pm_intr_mask = ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
 	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
 			  i915_hangcheck_elapsed);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86fbf72..98c20d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7030,7 +7030,8 @@ enum skl_disp_power_wells {
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
 #define GEN6_PMINTRMSK				_MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_ARAT_EXPIRED_INT_MASK		(1<<9)
 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e1..1695f69 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -476,6 +476,8 @@ int intel_guc_ucode_load(struct drm_device *dev)
 		/* The execbuf_client will be recreated. Release it first. */
 		i915_guc_submission_disable(dev);
 
+		dev_priv->rps.pm_intr_mask = I915_READ(GEN6_PMINTRMSK);
+
 		err = i915_guc_submission_enable(dev);
 		if (err)
 			goto fail;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..193ff46 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4708,6 +4708,8 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	u32 mask = 0xffffffff;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.enabled) {
 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -4715,7 +4717,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 		else
 			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 		dev_priv->rps.last_adj = 0;
-		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+
+		/*
+		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
+		 * interrupt based on mask set by GuC.
+		*/
+		if (INTEL_INFO(dev_priv)->gen >= 8) {
+			if (dev_priv->rps.pm_intr_mask &
+			    GEN8_PMINTR_REDIRECT_TO_NON_DISP)
+				mask &= dev_priv->rps.pm_intr_mask |
+					~GEN8_ARAT_EXPIRED_INT_MASK;
+			else
+				mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+		}
+		I915_WRITE(GEN6_PMINTRMSK, mask);
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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Re: [PATCH v2 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Mon, May 30, 2016 at 04:51:03PM +0530, Sagar Arun Kamble wrote:
> @@ -4580,6 +4590,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	else
>  		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
>  
> +	dev_priv->rps.pm_intr_mask = ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;

I was hoping for something along the lines of

	dev_priv->rps.pm_intr_keep = 0;
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8) {
		u32 tmp;

		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

		/*
		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
		 * interrupt based on mask set by GuC.
		 */
		tmp = I915_READ(GEN6_PMINTRMSK));
		if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP)
			dev_priv->rps.pm_intr_keep = tmp | ~GEN8_ARAT_EXPIRED_INT_MASK;
	}

then gen6_sanitize_rps_pm_mask() just becomes
	mask &= ~dev_priv->rps.pm_intr_keep

Note that reading PMINTRMSK to answer a question of whether we have
enabled something is odd, i.e. shouldn't we be applying the
dev_priv->rps.pm_intr_keep fixup when we redirect interrupts to the GuC?

> @@ -4715,7 +4717,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  		else
>  			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
>  		dev_priv->rps.last_adj = 0;
> -		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> +
> +		/*
> +		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
> +		 * interrupt based on mask set by GuC.
> +		*/
> +		if (INTEL_INFO(dev_priv)->gen >= 8) {
> +			if (dev_priv->rps.pm_intr_mask &
> +			    GEN8_PMINTR_REDIRECT_TO_NON_DISP)
> +				mask &= dev_priv->rps.pm_intr_mask |
> +					~GEN8_ARAT_EXPIRED_INT_MASK;
> +			else
> +				mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
> +		}
> +		I915_WRITE(GEN6_PMINTRMSK, mask);

This should be a call to gen6_sanitize_rps_pm_mask(). Ville has a patch
on the list to do that, please pull it in.
-Chris

-- 
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[PATCH 1/2] SNB (and IVB too I suppose) starts to misbehave if the GPU gets stuck in an infinite batch buffer loop. The GPU apparently hogs something critical and CPUs start to lose interrupts and whatnot. We can keep the system limping along by unmasking some interrupts in GEN6_PMINTRMSK. The EI up interrupt has been previously chosen for that task, so let's never mask it.

[Sagar Arun Kamble]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

v2: s/gen6_rps_pm_mask/gen6_sanitize_rps_pm_mask/ (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..aee56ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4715,7 +4715,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 		else
 			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 		dev_priv->rps.last_adj = 0;
-		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+		I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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[PATCH v3 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Sagar Arun Kamble]

On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
expired interrupt (bit 9). Host turbo also updates this register
in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
ARAT timer interrupt is needed in GuC for various features. It also
facilitates halting GuC and hence achieving RC6. PM interrupt routing
will not impact RPS interrupt reception by host as GuC will redirect
them.
This patch fixes igt test pm_rc6_residency that was failing with guc
load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.

v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)

v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)

Cc: Chris Harris <chris.harris@intel.com>
Cc: Zhe Wang <zhe1.wang@intel.com>
Cc: Deepak S <deepak.s@intel.com>
Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  2 ++
 drivers/gpu/drm/i915/i915_irq.c         | 36 +++++++++++++++++++++------------
 drivers/gpu/drm/i915/i915_reg.h         |  3 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c |  5 +++++
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f0b02..6a69ed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1132,6 +1132,8 @@ struct intel_gen6_power_mgmt {
 	bool interrupts_enabled;
 	u32 pm_iir;
 
+	u32 pm_intr_keep;
+
 	/* Frequencies are stored in potentially platform dependent multiples.
 	 * In other words, *_freq needs to be multiplied by X to be interesting.
 	 * Soft limits are those which are used for the dynamic reclocking done
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0d9414..96849f2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -364,19 +364,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 
 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 {
-	/*
-	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
-	 * if GEN6_PM_UP_EI_EXPIRED is masked.
-	 *
-	 * TODO: verify if this can be reproduced on VLV,CHV.
-	 */
-	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
-		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
-
-	if (INTEL_INFO(dev_priv)->gen >= 8)
-		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
-
-	return mask;
+	return (mask & ~dev_priv->rps.pm_intr_keep);
 }
 
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
@@ -4580,6 +4568,28 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	else
 		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
 
+	dev_priv->rps.pm_intr_keep = 0;
+
+	/*
+	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
+	 * if GEN6_PM_UP_EI_EXPIRED is masked.
+	 *
+	 * TODO: verify if this can be reproduced on VLV,CHV.
+	 */
+	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
+		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
+
+	/*
+	 * If GuC submission is enabled keep PM interrupts routed to GuC
+	 * and unmask ARAT Expired interrupt as it is needed by GuC.
+	*/
+	if (INTEL_INFO(dev_priv)->gen >= 8) {
+		if (i915.enable_guc_submission)
+			dev_priv->rps.pm_intr_keep |= GEN8_ARAT_EXPIRED_INT_MASK;
+		else
+			dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	}
+
 	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
 			  i915_hangcheck_elapsed);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86fbf72..98c20d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7030,7 +7030,8 @@ enum skl_disp_power_wells {
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
 #define GEN6_PMINTRMSK				_MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_ARAT_EXPIRED_INT_MASK		(1<<9)
 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e1..51a3939 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -476,6 +476,11 @@ int intel_guc_ucode_load(struct drm_device *dev)
 		/* The execbuf_client will be recreated. Release it first. */
 		i915_guc_submission_disable(dev);
 
+		WARN_ON(!(I915_READ(GEN6_PMINTRMSK) |
+				GEN8_PMINTR_REDIRECT_TO_NON_DISP));
+		WARN_ON(I915_READ(GEN6_PMINTRMSK) |
+				GEN8_ARAT_EXPIRED_INT_MASK);
+
 		err = i915_guc_submission_enable(dev);
 		if (err)
 			goto fail;
-- 
1.9.1

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[PATCH 1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB

[Sagar Arun Kamble]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

SNB (and IVB too I suppose) starts to misbehave if the GPU gets stuck
in an infinite batch buffer loop. The GPU apparently hogs something
critical and CPUs start to lose interrupts and whatnot. We can keep
the system limping along by unmasking some interrupts in
GEN6_PMINTRMSK. The EI up interrupt has been previously chosen for
that task, so let's never mask it.

v2: s/gen6_rps_pm_mask/gen6_sanitize_rps_pm_mask/ (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adb6463..aee56ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4715,7 +4715,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 		else
 			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
 		dev_priv->rps.last_adj = 0;
-		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+		I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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Re: [PATCH v3 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Tue, May 31, 2016 at 12:16:11AM +0530, Sagar Arun Kamble wrote:
>  void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
> @@ -4580,6 +4568,28 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	else
>  		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
>  
> +	dev_priv->rps.pm_intr_keep = 0;
> +
> +	/*
> +	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
> +	 * if GEN6_PM_UP_EI_EXPIRED is masked.
> +	 *
> +	 * TODO: verify if this can be reproduced on VLV,CHV.
> +	 */
> +	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
> +		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
> +
> +	/*
> +	 * If GuC submission is enabled keep PM interrupts routed to GuC
> +	 * and unmask ARAT Expired interrupt as it is needed by GuC.
> +	*/
> +	if (INTEL_INFO(dev_priv)->gen >= 8) {
> +		if (i915.enable_guc_submission)
> +			dev_priv->rps.pm_intr_keep |= GEN8_ARAT_EXPIRED_INT_MASK;
> +		else
> +			dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

The logic doesn't match the comment. Don't you want

if (i915.enable_guc_submission) {
	dev_priv->rps.pm_intr_keep |= GEN8_ARAT_EXPIRED_INT_MASK;
	dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
}

as implied by the comment? Although I'm guessing the
i915.enable_guc_submission will be refined in future, it should do for
now.

> +		WARN_ON(!(I915_READ(GEN6_PMINTRMSK) |
> +				GEN8_PMINTR_REDIRECT_TO_NON_DISP));

Always false;

> +		WARN_ON(I915_READ(GEN6_PMINTRMSK) |
> +				GEN8_ARAT_EXPIRED_INT_MASK);

Always true.

I don't this was quite what you meant :)

But the patch is a lot neater now!
-Chris

-- 
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Re: [PATCH v3 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Kamble, Sagar A]

On 5/31/2016 1:48 AM, Chris Wilson wrote:
> On Tue, May 31, 2016 at 12:16:11AM +0530, Sagar Arun Kamble wrote:
>>   void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>> @@ -4580,6 +4568,28 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>   	else
>>   		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
>>   
>> +	dev_priv->rps.pm_intr_keep = 0;
>> +
>> +	/*
>> +	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
>> +	 * if GEN6_PM_UP_EI_EXPIRED is masked.
>> +	 *
>> +	 * TODO: verify if this can be reproduced on VLV,CHV.
>> +	 */
>> +	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
>> +		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
>> +
>> +	/*
>> +	 * If GuC submission is enabled keep PM interrupts routed to GuC
>> +	 * and unmask ARAT Expired interrupt as it is needed by GuC.
>> +	*/
>> +	if (INTEL_INFO(dev_priv)->gen >= 8) {
>> +		if (i915.enable_guc_submission)
>> +			dev_priv->rps.pm_intr_keep |= GEN8_ARAT_EXPIRED_INT_MASK;
>> +		else
>> +			dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
> The logic doesn't match the comment. Don't you want
>
> if (i915.enable_guc_submission) {
> 	dev_priv->rps.pm_intr_keep |= GEN8_ARAT_EXPIRED_INT_MASK;
> 	dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
> }
We don't want to keep GEN8_PMINTR_REDIRECT_TO_NON_DISP if GuC submission 
is used.
I added WARN_ON for bits of GEN6_PMINTRMASK if GuC has set expected.
With GuC loaded bit 31 will be set and bit 9 is reset. GuC might reset 
other bits if it needs
those interrupts. I am extending the logic to other interrupts to make 
it extensible.
Certainly this patch is looking more neat now :) ... Thank you.
>
> as implied by the comment? Although I'm guessing the
> i915.enable_guc_submission will be refined in future, it should do for
> now.
>
>> +		WARN_ON(!(I915_READ(GEN6_PMINTRMSK) |
>> +				GEN8_PMINTR_REDIRECT_TO_NON_DISP));
> Always false;
>
>> +		WARN_ON(I915_READ(GEN6_PMINTRMSK) |
>> +				GEN8_ARAT_EXPIRED_INT_MASK);
> Always true.
>
> I don't this was quite what you meant :)
>
> But the patch is a lot neater now!
> -Chris
>

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[PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Sagar Arun Kamble]

On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
expired interrupt (bit 9). Host turbo also updates this register
in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
ARAT timer interrupt is needed in GuC for various features. It also
facilitates halting GuC and hence achieving RC6. PM interrupt routing
will not impact RPS interrupt reception by host as GuC will redirect
them.
This patch fixes igt test pm_rc6_residency that was failing with guc
load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.

v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)

v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)

v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)

Cc: Chris Harris <chris.harris@intel.com>
Cc: Zhe Wang <zhe1.wang@intel.com>
Cc: Deepak S <deepak.s@intel.com>
Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |  1 +
 drivers/gpu/drm/i915/i915_drv.h         |  2 ++
 drivers/gpu/drm/i915/i915_irq.c         | 28 +++++++++++++++-------------
 drivers/gpu/drm/i915/i915_reg.h         |  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 11 +++++++++++
 5 files changed, 30 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24f4105..4733b80 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1281,6 +1281,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		}
 		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
 			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+		seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
 			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f0b02..6a69ed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1132,6 +1132,8 @@ struct intel_gen6_power_mgmt {
 	bool interrupts_enabled;
 	u32 pm_iir;
 
+	u32 pm_intr_keep;
+
 	/* Frequencies are stored in potentially platform dependent multiples.
 	 * In other words, *_freq needs to be multiplied by X to be interesting.
 	 * Soft limits are those which are used for the dynamic reclocking done
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f0d9414..65b5aadc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -364,19 +364,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 
 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 {
-	/*
-	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
-	 * if GEN6_PM_UP_EI_EXPIRED is masked.
-	 *
-	 * TODO: verify if this can be reproduced on VLV,CHV.
-	 */
-	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
-		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
-
-	if (INTEL_INFO(dev_priv)->gen >= 8)
-		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
-
-	return mask;
+	return (mask & ~dev_priv->rps.pm_intr_keep);
 }
 
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
@@ -4580,6 +4568,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	else
 		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
 
+	dev_priv->rps.pm_intr_keep = 0;
+
+	/*
+	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
+	 * if GEN6_PM_UP_EI_EXPIRED is masked.
+	 *
+	 * TODO: verify if this can be reproduced on VLV,CHV.
+	 */
+	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
+		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
+
+	if (INTEL_INFO(dev_priv)->gen >= 8)
+		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
 	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
 			  i915_hangcheck_elapsed);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86fbf72..ba9d9f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7030,7 +7030,7 @@ enum skl_disp_power_wells {
 #define VLV_RCEDATA				_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
 #define GEN6_PMINTRMSK				_MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
+#define   GEN8_PMINTR_REDIRECT_TO_NON_DISP	(1<<31)
 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e1..79fb6db 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -103,6 +103,7 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
 	int irqs;
+	u32 tmp;
 
 	/* tell all command streamers to forward interrupts and vblank to GuC */
 	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
@@ -117,6 +118,16 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 	I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 	I915_WRITE(GUC_WD_VECS_IER, ~irqs);
+
+	/*
+	 * If GuC has routed PM interrupts to itself, don't keep it.
+	 * and keep other interrupts those are unmasked by GuC.
+	*/
+	tmp = I915_READ(GEN6_PMINTRMSK);
+	if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
+		dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
+		dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+	}
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
> On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
> expired interrupt (bit 9). Host turbo also updates this register
> in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
> ARAT timer interrupt is needed in GuC for various features. It also
> facilitates halting GuC and hence achieving RC6. PM interrupt routing
> will not impact RPS interrupt reception by host as GuC will redirect
> them.
> This patch fixes igt test pm_rc6_residency that was failing with guc
> load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
> 
> v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
> 
> v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
> 
> v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
> 
> Cc: Chris Harris <chris.harris@intel.com>
> Cc: Zhe Wang <zhe1.wang@intel.com>
> Cc: Deepak S <deepak.s@intel.com>
> Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

I can understand what you mean by this patch, perfect!
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
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✗ Ro.CI.BAT: warning for series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB

[Patchwork]

== Series Details ==

Series: series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB
URL   : https://patchwork.freedesktop.org/series/7990/
State : warning

== Summary ==

Series 7990v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7990/revisions/1/mbox

Test gem_busy:
        Subgroup basic-parallel-render:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
        Subgroup basic-render:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_close_race:
        Subgroup basic-process:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_exec_basic:
        Subgroup readonly-render:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_exec_flush:
        Subgroup basic-uc-prw-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-uc-ro-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_parallel:
        Subgroup basic:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_exec_store:
        Subgroup basic-all:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
        Subgroup basic-blt:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_flink_basic:
        Subgroup bad-flink:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-short:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-small-copy:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-bsd:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_tiled_pread_basic:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-framebuffer-vs-set-tiling:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup addfb25-x-tiled:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup addfb25-y-tiled-small:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-1024:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-63:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-x-tiled:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup too-high:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup too-wide:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_force_connector_basic:
        Subgroup force-edid:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)

fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
fi-byt-n2820     total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-ivb2-i7-3770  total:102  pass:42   dwarn:37  dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:175  dwarn:8   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
fi-bsw-n3050 failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1055/

031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
5779419 drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB

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✗ Ro.CI.BAT: warning for series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5)
URL   : https://patchwork.freedesktop.org/series/7972/
State : warning

== Summary ==

Series 7972v5 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7972/revisions/5/mbox

Test gem_busy:
        Subgroup basic-parallel-bsd:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_close_race:
        Subgroup basic-process:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_ctx_exec:
        Subgroup basic:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_exec_basic:
        Subgroup readonly-render:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_exec_flush:
        Subgroup basic-wb-pro-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_store:
        Subgroup basic-blt:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-ivb2-i7-3770)
Test gem_exec_suspend:
        Subgroup basic:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_storedw_loop:
        Subgroup basic-bsd:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-framebuffer-vs-set-tiling:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup addfb25-x-tiled:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-1024:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-63:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-65536:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-999:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup too-high:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup too-wide:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
fi-bsw-n3050     total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-byt-n2820     total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:52   pass:37   dwarn:0   dfail:0   fail:0   skip:14 
ro-ivb2-i7-3770  total:102  pass:44   dwarn:35  dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:177  dwarn:6   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1057/

031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
db75f2f drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

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Re: ✗ Ro.CI.BAT: warning for series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5)

[Kamble, Sagar A]

Warnings are not related to the patch. Kindly push this patch.
Have filed bug for IVB warnings: 
https://bugs.freedesktop.org/show_bug.cgi?id=96293
For SKL warnings there is already a bug: 
https://bugs.freedesktop.org/show_bug.cgi?id=95632

Thanks
Sagar

On 5/31/2016 5:08 PM, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5)
> URL   : https://patchwork.freedesktop.org/series/7972/
> State : warning
>
> == Summary ==
>
> Series 7972v5 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/7972/revisions/5/mbox
>
> Test gem_busy:
>          Subgroup basic-parallel-bsd:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_close_race:
>          Subgroup basic-process:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_cs_tlb:
>          Subgroup basic-default:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_ctx_exec:
>          Subgroup basic:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_exec_basic:
>          Subgroup readonly-render:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_exec_flush:
>          Subgroup basic-wb-pro-default:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_exec_store:
>          Subgroup basic-blt:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
>          Subgroup basic-default:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_exec_suspend:
>          Subgroup basic:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_storedw_loop:
>          Subgroup basic-bsd:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_addfb_basic:
>          Subgroup addfb25-framebuffer-vs-set-tiling:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup addfb25-x-tiled:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-1024:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-63:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-65536:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-999:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup too-high:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup too-wide:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_flip:
>          Subgroup basic-flip-vs-wf_vblank:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_force_connector_basic:
>          Subgroup force-connector-state:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test kms_psr_sink_crc:
>          Subgroup psr_basic:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>
> fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> fi-bsw-n3050     total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40
> fi-byt-n2820     total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38
> fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19
> fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25
> fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39
> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26
> ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39
> ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23
> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19
> ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57
> ro-ivb-i7-3770   total:52   pass:37   dwarn:0   dfail:0   fail:0   skip:14
> ro-ivb2-i7-3770  total:102  pass:44   dwarn:35  dfail:0   fail:0   skip:22
> ro-skl-i7-6700hq total:204  pass:177  dwarn:6   dfail:0   fail:0   skip:21
> ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29
> ro-bdw-i7-5557U failed to connect after reboot
> ro-ivb-i7-3770 failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1057/
>
> 031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
> db75f2f drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled
>

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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Matt Roper]

On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote:
> On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
> > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
> > expired interrupt (bit 9). Host turbo also updates this register
> > in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
> > ARAT timer interrupt is needed in GuC for various features. It also
> > facilitates halting GuC and hence achieving RC6. PM interrupt routing
> > will not impact RPS interrupt reception by host as GuC will redirect
> > them.
> > This patch fixes igt test pm_rc6_residency that was failing with guc
> > load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
> > 
> > v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
> > 
> > v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
> > 
> > v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
> > 
> > Cc: Chris Harris <chris.harris@intel.com>
> > Cc: Zhe Wang <zhe1.wang@intel.com>
> > Cc: Deepak S <deepak.s@intel.com>
> > Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
> > Cc: Akash Goel <akash.goel@intel.com>
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> 
> I can understand what you mean by this patch, perfect!
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris

Testcase: igt/pm_rc6_residency
Tested-by: Matt Roper <matthew.d.roper@intel.com>

Merged to dinq.  Thanks for the patch and review.


Matt

> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote:
> On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote:
> > On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
> > > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
> > > expired interrupt (bit 9). Host turbo also updates this register
> > > in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
> > > ARAT timer interrupt is needed in GuC for various features. It also
> > > facilitates halting GuC and hence achieving RC6. PM interrupt routing
> > > will not impact RPS interrupt reception by host as GuC will redirect
> > > them.
> > > This patch fixes igt test pm_rc6_residency that was failing with guc
> > > load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
> > > 
> > > v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
> > > 
> > > v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
> > > 
> > > v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
> > > 
> > > Cc: Chris Harris <chris.harris@intel.com>
> > > Cc: Zhe Wang <zhe1.wang@intel.com>
> > > Cc: Deepak S <deepak.s@intel.com>
> > > Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
> > > Cc: Akash Goel <akash.goel@intel.com>
> > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > 
> > I can understand what you mean by this patch, perfect!
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > -Chris
> 
> Testcase: igt/pm_rc6_residency
> Tested-by: Matt Roper <matthew.d.roper@intel.com>
> 
> Merged to dinq.  Thanks for the patch and review.

This was only the second patch, it also wants the first patch to always
use gen6_sanitize_pm_mask otherwise we loose the interrupt bypass from
gen6_rps_idle(). That should have been caught by the testcase...
-Chris

-- 
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Re: ✗ Ro.CI.BAT: warning for series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB

[Kamble, Sagar A]

These warnings are too not related to the patch.
Kindly push this patch.

On 5/31/2016 4:35 PM, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB
> URL   : https://patchwork.freedesktop.org/series/7990/
> State : warning
>
> == Summary ==
>
> Series 7990v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/7990/revisions/1/mbox
>
> Test gem_busy:
>          Subgroup basic-parallel-render:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
>          Subgroup basic-render:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_close_race:
>          Subgroup basic-process:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_cs_tlb:
>          Subgroup basic-default:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_exec_basic:
>          Subgroup readonly-render:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_exec_flush:
>          Subgroup basic-uc-prw-default:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup basic-uc-ro-default:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_exec_parallel:
>          Subgroup basic:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_exec_store:
>          Subgroup basic-all:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
>          Subgroup basic-blt:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
>          Subgroup basic-default:
>                  dmesg-warn -> PASS       (ro-ivb2-i7-3770)
> Test gem_flink_basic:
>          Subgroup bad-flink:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_mmap_gtt:
>          Subgroup basic-short:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup basic-small-copy:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_storedw_loop:
>          Subgroup basic-bsd:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_tiled_pread_basic:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test kms_addfb_basic:
>          Subgroup addfb25-framebuffer-vs-set-tiling:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup addfb25-x-tiled:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup addfb25-y-tiled-small:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-1024:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-63:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup basic-x-tiled:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup too-high:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup too-wide:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_force_connector_basic:
>          Subgroup force-edid:
>                  pass       -> DMESG-WARN (ro-ivb2-i7-3770)
>
> fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> fi-byt-n2820     total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38
> fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19
> fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25
> fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39
> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26
> ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39
> ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23
> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19
> ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57
> ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26
> ro-ivb2-i7-3770  total:102  pass:42   dwarn:37  dfail:0   fail:0   skip:22
> ro-skl-i7-6700hq total:204  pass:175  dwarn:8   dfail:0   fail:0   skip:21
> ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29
> fi-bsw-n3050 failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1055/
>
> 031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
> 5779419 drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB
>

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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Kamble, Sagar A]

On 6/1/2016 12:24 PM, Chris Wilson wrote:
> On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote:
>> On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote:
>>> On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
>>>> On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
>>>> expired interrupt (bit 9). Host turbo also updates this register
>>>> in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
>>>> ARAT timer interrupt is needed in GuC for various features. It also
>>>> facilitates halting GuC and hence achieving RC6. PM interrupt routing
>>>> will not impact RPS interrupt reception by host as GuC will redirect
>>>> them.
>>>> This patch fixes igt test pm_rc6_residency that was failing with guc
>>>> load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
>>>>
>>>> v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
>>>>
>>>> v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
>>>>
>>>> v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
>>>>
>>>> Cc: Chris Harris <chris.harris@intel.com>
>>>> Cc: Zhe Wang <zhe1.wang@intel.com>
>>>> Cc: Deepak S <deepak.s@intel.com>
>>>> Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
>>>> Cc: Akash Goel <akash.goel@intel.com>
>>>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>> I can understand what you mean by this patch, perfect!
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> -Chris
>> Testcase: igt/pm_rc6_residency
>> Tested-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> Merged to dinq.  Thanks for the patch and review.
> This was only the second patch, it also wants the first patch to always
> use gen6_sanitize_pm_mask otherwise we loose the interrupt bypass from
> gen6_rps_idle(). That should have been caught by the testcase...
> -Chris
BAT picked up these patches separately. I had submitted them in sequence 
although I updated current patch twice posting them together.
How is this supposed to work?
>

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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Matt Roper]

On Wed, Jun 01, 2016 at 07:54:42AM +0100, Chris Wilson wrote:
> On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote:
> > On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote:
> > > On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
> > > > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
> > > > expired interrupt (bit 9). Host turbo also updates this register
> > > > in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
> > > > ARAT timer interrupt is needed in GuC for various features. It also
> > > > facilitates halting GuC and hence achieving RC6. PM interrupt routing
> > > > will not impact RPS interrupt reception by host as GuC will redirect
> > > > them.
> > > > This patch fixes igt test pm_rc6_residency that was failing with guc
> > > > load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
> > > > 
> > > > v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
> > > > 
> > > > v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
> > > > 
> > > > v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
> > > > 
> > > > Cc: Chris Harris <chris.harris@intel.com>
> > > > Cc: Zhe Wang <zhe1.wang@intel.com>
> > > > Cc: Deepak S <deepak.s@intel.com>
> > > > Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
> > > > Cc: Akash Goel <akash.goel@intel.com>
> > > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > 
> > > I can understand what you mean by this patch, perfect!
> > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > -Chris
> > 
> > Testcase: igt/pm_rc6_residency
> > Tested-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > Merged to dinq.  Thanks for the patch and review.
> 
> This was only the second patch, it also wants the first patch to always
> use gen6_sanitize_pm_mask otherwise we loose the interrupt bypass from
> gen6_rps_idle(). That should have been caught by the testcase...
> -Chris

Hmm, I guess is misunderstood the message thread flow here and didn't
realize there was another patch necessary as well.  I did find that just
this one patch caused the IGT to start passing where it had failed
before (on BXT), so not sure why I didn't run into problems.  I did
merge in a couple un-related TSC patches (required to keep my BXT stable
in general) before testing, but I don't think that would have changed
the behavior here.


Matt

> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Kamble, Sagar A]

On 6/1/2016 7:59 PM, Matt Roper wrote:
> On Wed, Jun 01, 2016 at 07:54:42AM +0100, Chris Wilson wrote:
>> On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote:
>>> On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote:
>>>> On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote:
>>>>> On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT
>>>>> expired interrupt (bit 9). Host turbo also updates this register
>>>>> in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists.
>>>>> ARAT timer interrupt is needed in GuC for various features. It also
>>>>> facilitates halting GuC and hence achieving RC6. PM interrupt routing
>>>>> will not impact RPS interrupt reception by host as GuC will redirect
>>>>> them.
>>>>> This patch fixes igt test pm_rc6_residency that was failing with guc
>>>>> load/submission enabled. Tested with SKL GuC v6.1 and BXT GuC v5.1 and v8.7.
>>>>>
>>>>> v2: i915_irq/i915_pm decoupling from intel_guc. (ChrisW)
>>>>>
>>>>> v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
>>>>>
>>>>> v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
>>>>>
>>>>> Cc: Chris Harris <chris.harris@intel.com>
>>>>> Cc: Zhe Wang <zhe1.wang@intel.com>
>>>>> Cc: Deepak S <deepak.s@intel.com>
>>>>> Cc: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
>>>>> Cc: Akash Goel <akash.goel@intel.com>
>>>>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>>> I can understand what you mean by this patch, perfect!
>>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>> -Chris
>>> Testcase: igt/pm_rc6_residency
>>> Tested-by: Matt Roper <matthew.d.roper@intel.com>
>>>
>>> Merged to dinq.  Thanks for the patch and review.
>> This was only the second patch, it also wants the first patch to always
>> use gen6_sanitize_pm_mask otherwise we loose the interrupt bypass from
>> gen6_rps_idle(). That should have been caught by the testcase...
>> -Chris
> Hmm, I guess is misunderstood the message thread flow here and didn't
> realize there was another patch necessary as well.  I did find that just
> this one patch caused the IGT to start passing where it had failed
> before (on BXT), so not sure why I didn't run into problems.  I did
> merge in a couple un-related TSC patches (required to keep my BXT stable
> in general) before testing, but I don't think that would have changed
> the behavior here.
Testcase did not catch it because guc loading/submission is disabled by 
default.
I have submitted BAT request with guc loading/submission enabled on trybot.
Waiting for the results.
>
>
> Matt
>
>> -- 
>> Chris Wilson, Intel Open Source Technology Centre

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Re: [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Thu, Jun 02, 2016 at 05:42:08PM +0530, Kamble, Sagar A wrote:
> On 6/1/2016 7:59 PM, Matt Roper wrote:
> >Hmm, I guess is misunderstood the message thread flow here and didn't
> >realize there was another patch necessary as well.  I did find that just
> >this one patch caused the IGT to start passing where it had failed
> >before (on BXT), so not sure why I didn't run into problems.  I did
> >merge in a couple un-related TSC patches (required to keep my BXT stable
> >in general) before testing, but I don't think that would have changed
> >the behavior here.
> Testcase did not catch it because guc loading/submission is disabled
> by default.

That's the unspoken question, to make sure that the testcase is
sufficient (in case we needed a new test).

> I have submitted BAT request with guc loading/submission enabled on trybot.
> Waiting for the results.

Ah, you need to send the patches as a single series. Pull them into a
local branch, then git send-email -4 --to trybot.

Fwiw, this is the script I use:

#!/bin/bash

COMMIT=$1
INTEL=intel
DIN=${INTEL}/drm-intel-nightly

git fetch ${INTEL}
git merge-base --is-ancestor ${DIN} ${COMMIT:-HEAD} || {
	echo Tree is out of date
	exit 1
}

git send-email --to intel-gfx-trybot@lists.freedesktop.org --suppress-cc=all ${DIN}..${COMMIT}

Definitely not fool^Wmeproof!
-Chris

-- 
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