drm/i915 4.5/4.6 stable backport request for CHV

drm/i915 4.5/4.6 stable backport request for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Several nasty i915 regressions affecting CHV slipped through
to 4.5 and 4.6.

The first fix we want in 4.5 and 4.6 is
commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
It won't cherry-pick cleanly to either one, so I've included conflict
free versions for both. This one fixes display FIFO underruns that can
lead to the screen totally blanking out.

The other one I'd like to have in 4.6 is
commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
which avoids a totally corrupted display in some cases.

And the third on is a bit more annoying. The regression is caused by
commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
which I though we had prevented from getting out on its own, but turns
out I was wrong. It basically makes the GPU unusable, so we do need to
fix it somehow. The simple solution would be to revert it in 4.6 only.
The more complicated solution is to backport the proper fix, which more
or less requires the following set of commits [1], which is maybe a bit
too much for stable. I could try to trim it a bit perhaps, but then we
start to enter the territory of untested code which I don't particularly
like. Let me know what you think.

[1]
 1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
 a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
 4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
 7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
 34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
 e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
 71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
 6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
 9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
 d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
 8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
 9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
 ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
 93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")

Cc: stable@vger.kernel.org
-- 
Ville Syrjälä
Intel OTC

[PATCH for v4.5] drm/i915: Fix watermarks for VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

commit caed361d83b2 upstream

commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.

This caused underruns on modeset and plane enable/disable on CHV,
and often those can lead to a dead pipe.

So let's bring back the pre vs. post thing, and let's toss in an
explicit wm update to valleyview_crtc_enable() to avoid having to
put it into the common code.

This is more or less a partial revert of the offending commit.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.5
---
 drivers/gpu/drm/i915/intel_atomic.c  |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 3 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d0b1c9afa35e..6314446f58fa 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
-	crtc_state->wm_changed = false;
+	crtc_state->update_wm_pre = false;
+	crtc_state->update_wm_post = false;
 
 	return &crtc_state->base;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 39b00b9daf2d..207391e89599 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4816,7 +4816,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
 
 	crtc->wm.cxsr_allowed = true;
 
-	if (pipe_config->wm_changed && pipe_config->base.active)
+	if (pipe_config->update_wm_post && pipe_config->base.active)
 		intel_update_watermarks(&crtc->base);
 
 	if (atomic->update_fbc)
@@ -4850,7 +4850,7 @@ static void intel_pre_plane_update(struct intel_crtc *crtc)
 		intel_set_memory_cxsr(dev_priv, false);
 	}
 
-	if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
+	if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre)
 		intel_update_watermarks(&crtc->base);
 }
 
@@ -6229,6 +6229,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	intel_crtc_load_lut(crtc);
 
+	intel_update_watermarks(crtc);
 	intel_enable_pipe(intel_crtc);
 
 	assert_vblank_disabled(crtc);
@@ -11881,8 +11882,14 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 			 plane->base.id, was_visible, visible,
 			 turn_off, turn_on, mode_changed);
 
-	if (turn_on || turn_off) {
-		pipe_config->wm_changed = true;
+	if (turn_on) {
+		pipe_config->update_wm_pre = true;
+
+		/* must disable cxsr around plane enable/disable */
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			pipe_config->disable_cxsr = true;
+	} else if (turn_off) {
+		pipe_config->update_wm_post = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
@@ -11891,7 +11898,9 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 			pipe_config->disable_cxsr = true;
 		}
 	} else if (intel_wm_need_update(plane, plane_state)) {
-		pipe_config->wm_changed = true;
+		/* FIXME bollocks */
+		pipe_config->update_wm_pre = true;
+		pipe_config->update_wm_post = true;
 	}
 
 	if (visible || was_visible)
@@ -12036,7 +12045,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	}
 
 	if (mode_changed && !crtc_state->active)
-		pipe_config->wm_changed = true;
+		pipe_config->update_wm_post = true;
 
 	if (mode_changed && crtc_state->enable &&
 	    dev_priv->display.crtc_compute_clock &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1ae61f488987..c6f045ecb15a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -367,7 +367,7 @@ struct intel_crtc_state {
 
 	bool update_pipe; /* can a fast modeset be performed? */
 	bool disable_cxsr;
-	bool wm_changed; /* watermarks are updated */
+	bool update_wm_pre, update_wm_post; /* watermarks are updated */
 
 	/* Pipe source size (ie. panel fitter input size)
 	 * All planes will be positioned inside this space,
-- 
2.7.4

[PATCH for v4.6] drm/i915: Fix watermarks for VLV/CHV

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

commit caed361d83b2 upstream

commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.

This caused underruns on modeset and plane enable/disable on CHV,
and often those can lead to a dead pipe.

So let's bring back the pre vs. post thing, and let's toss in an
explicit wm update to valleyview_crtc_enable() to avoid having to
put it into the common code.

This is more or less a partial revert of the offending commit.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.6
---
 drivers/gpu/drm/i915/intel_atomic.c  |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 3 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 8e579a8505ac..e7c1686e479c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
-	crtc_state->wm_changed = false;
+	crtc_state->update_wm_pre = false;
+	crtc_state->update_wm_post = false;
 	crtc_state->fb_changed = false;
 
 	return &crtc_state->base;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0104a06d01fd..c7fc229cb242 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4796,7 +4796,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
 
 	crtc->wm.cxsr_allowed = true;
 
-	if (pipe_config->wm_changed && pipe_config->base.active)
+	if (pipe_config->update_wm_post && pipe_config->base.active)
 		intel_update_watermarks(&crtc->base);
 
 	if (atomic->update_fbc)
@@ -4843,7 +4843,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
 			intel_set_memory_cxsr(dev_priv, false);
 	}
 
-	if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
+	if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre)
 		intel_update_watermarks(&crtc->base);
 }
 
@@ -6210,6 +6210,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	intel_crtc_load_lut(crtc);
 
+	intel_update_watermarks(crtc);
 	intel_enable_pipe(intel_crtc);
 
 	assert_vblank_disabled(crtc);
@@ -11833,14 +11834,22 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 			 plane->base.id, was_visible, visible,
 			 turn_off, turn_on, mode_changed);
 
-	if (turn_on || turn_off) {
-		pipe_config->wm_changed = true;
+	if (turn_on) {
+		pipe_config->update_wm_pre = true;
+
+		/* must disable cxsr around plane enable/disable */
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			pipe_config->disable_cxsr = true;
+	} else if (turn_off) {
+		pipe_config->update_wm_post = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->type != DRM_PLANE_TYPE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (intel_wm_need_update(plane, plane_state)) {
-		pipe_config->wm_changed = true;
+		/* FIXME bollocks */
+		pipe_config->update_wm_pre = true;
+		pipe_config->update_wm_post = true;
 	}
 
 	if (visible || was_visible)
@@ -11940,7 +11949,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	}
 
 	if (mode_changed && !crtc_state->active)
-		pipe_config->wm_changed = true;
+		pipe_config->update_wm_post = true;
 
 	if (mode_changed && crtc_state->enable &&
 	    dev_priv->display.crtc_compute_clock &&
@@ -13453,12 +13462,12 @@ static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
 		return true;
 
 	/* wm changes, need vblank before final wm's */
-	if (crtc_state->wm_changed)
+	if (crtc_state->update_wm_post)
 		return true;
 
 	/*
 	 * cxsr is re-enabled after vblank.
-	 * This is already handled by crtc_state->wm_changed,
+	 * This is already handled by crtc_state->update_wm_post,
 	 * but added for clarity.
 	 */
 	if (crtc_state->disable_cxsr)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d0770c23fde..faf180c40f55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -378,7 +378,7 @@ struct intel_crtc_state {
 
 	bool update_pipe; /* can a fast modeset be performed? */
 	bool disable_cxsr;
-	bool wm_changed; /* watermarks are updated */
+	bool update_wm_pre, update_wm_post; /* watermarks are updated */
 	bool fb_changed; /* fb on any of the planes is changed */
 
 	/* Pipe source size (ie. panel fitter input size)
-- 
2.7.4

[PATCH for v4.6] drm/i915: Fix watermarks for VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

commit caed361d83b2 upstream

commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.

This caused underruns on modeset and plane enable/disable on CHV,
and often those can lead to a dead pipe.

So let's bring back the pre vs. post thing, and let's toss in an
explicit wm update to valleyview_crtc_enable() to avoid having to
put it into the common code.

This is more or less a partial revert of the offending commit.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.6
---
 drivers/gpu/drm/i915/intel_atomic.c  |  3 ++-
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 3 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 8e579a8505ac..e7c1686e479c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
-	crtc_state->wm_changed = false;
+	crtc_state->update_wm_pre = false;
+	crtc_state->update_wm_post = false;
 	crtc_state->fb_changed = false;
 
 	return &crtc_state->base;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0104a06d01fd..c7fc229cb242 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4796,7 +4796,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
 
 	crtc->wm.cxsr_allowed = true;
 
-	if (pipe_config->wm_changed && pipe_config->base.active)
+	if (pipe_config->update_wm_post && pipe_config->base.active)
 		intel_update_watermarks(&crtc->base);
 
 	if (atomic->update_fbc)
@@ -4843,7 +4843,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
 			intel_set_memory_cxsr(dev_priv, false);
 	}
 
-	if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
+	if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre)
 		intel_update_watermarks(&crtc->base);
 }
 
@@ -6210,6 +6210,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	intel_crtc_load_lut(crtc);
 
+	intel_update_watermarks(crtc);
 	intel_enable_pipe(intel_crtc);
 
 	assert_vblank_disabled(crtc);
@@ -11833,14 +11834,22 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 			 plane->base.id, was_visible, visible,
 			 turn_off, turn_on, mode_changed);
 
-	if (turn_on || turn_off) {
-		pipe_config->wm_changed = true;
+	if (turn_on) {
+		pipe_config->update_wm_pre = true;
+
+		/* must disable cxsr around plane enable/disable */
+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
+			pipe_config->disable_cxsr = true;
+	} else if (turn_off) {
+		pipe_config->update_wm_post = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->type != DRM_PLANE_TYPE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (intel_wm_need_update(plane, plane_state)) {
-		pipe_config->wm_changed = true;
+		/* FIXME bollocks */
+		pipe_config->update_wm_pre = true;
+		pipe_config->update_wm_post = true;
 	}
 
 	if (visible || was_visible)
@@ -11940,7 +11949,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	}
 
 	if (mode_changed && !crtc_state->active)
-		pipe_config->wm_changed = true;
+		pipe_config->update_wm_post = true;
 
 	if (mode_changed && crtc_state->enable &&
 	    dev_priv->display.crtc_compute_clock &&
@@ -13453,12 +13462,12 @@ static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
 		return true;
 
 	/* wm changes, need vblank before final wm's */
-	if (crtc_state->wm_changed)
+	if (crtc_state->update_wm_post)
 		return true;
 
 	/*
 	 * cxsr is re-enabled after vblank.
-	 * This is already handled by crtc_state->wm_changed,
+	 * This is already handled by crtc_state->update_wm_post,
 	 * but added for clarity.
 	 */
 	if (crtc_state->disable_cxsr)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d0770c23fde..faf180c40f55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -378,7 +378,7 @@ struct intel_crtc_state {
 
 	bool update_pipe; /* can a fast modeset be performed? */
 	bool disable_cxsr;
-	bool wm_changed; /* watermarks are updated */
+	bool update_wm_pre, update_wm_post; /* watermarks are updated */
 	bool fb_changed; /* fb on any of the planes is changed */
 
 	/* Pipe source size (ie. panel fitter input size)
-- 
2.7.4

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✗ Ro.CI.BAT: failure for drm/i915: Fix watermarks for VLV/CHV

[Patchwork]

== Series Details ==

Series: drm/i915: Fix watermarks for VLV/CHV
URL   : https://patchwork.freedesktop.org/series/7867/
State : failure

== Summary ==

Applying: drm/i915: Fix watermarks for VLV/CHV
Patch failed at 0001 drm/i915: Fix watermarks for VLV/CHV
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: drm/i915 4.5/4.6 stable backport request for CHV

[Greg KH]

On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> 
> Several nasty i915 regressions affecting CHV slipped through
> to 4.5 and 4.6.
> 
> The first fix we want in 4.5 and 4.6 is
> commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> It won't cherry-pick cleanly to either one, so I've included conflict
> free versions for both. This one fixes display FIFO underruns that can
> lead to the screen totally blanking out.

Now applied, thanks.

> The other one I'd like to have in 4.6 is
> commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> which avoids a totally corrupted display in some cases.

Now applied.

> And the third on is a bit more annoying. The regression is caused by
> commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> which I though we had prevented from getting out on its own, but turns
> out I was wrong. It basically makes the GPU unusable, so we do need to
> fix it somehow. The simple solution would be to revert it in 4.6 only.
> The more complicated solution is to backport the proper fix, which more
> or less requires the following set of commits [1], which is maybe a bit
> too much for stable. I could try to trim it a bit perhaps, but then we
> start to enter the territory of untested code which I don't particularly
> like. Let me know what you think.
> 
> [1]
>  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
>  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
>  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
>  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
>  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
>  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
>  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
>  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
>  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
>  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
>  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
>  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
>  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
>  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")

I think reverting that one patch for 4.6 makes more sense than adding
all of these patches.  I'll do that if you want me to.

thanks,

greg k-h

Re: drm/i915 4.5/4.6 stable backport request for CHV

[Greg KH]

On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Several nasty i915 regressions affecting CHV slipped through
> to 4.5 and 4.6.
> 
> The first fix we want in 4.5 and 4.6 is
> commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> It won't cherry-pick cleanly to either one, so I've included conflict
> free versions for both. This one fixes display FIFO underruns that can
> lead to the screen totally blanking out.

Now applied, thanks.

> The other one I'd like to have in 4.6 is
> commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> which avoids a totally corrupted display in some cases.

Now applied.

> And the third on is a bit more annoying. The regression is caused by
> commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> which I though we had prevented from getting out on its own, but turns
> out I was wrong. It basically makes the GPU unusable, so we do need to
> fix it somehow. The simple solution would be to revert it in 4.6 only.
> The more complicated solution is to backport the proper fix, which more
> or less requires the following set of commits [1], which is maybe a bit
> too much for stable. I could try to trim it a bit perhaps, but then we
> start to enter the territory of untested code which I don't particularly
> like. Let me know what you think.
> 
> [1]
>  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
>  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
>  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
>  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
>  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
>  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
>  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
>  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
>  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
>  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
>  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
>  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
>  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
>  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")

I think reverting that one patch for 4.6 makes more sense than adding
all of these patches.  I'll do that if you want me to.

thanks,

greg k-h

Re: drm/i915 4.5/4.6 stable backport request for CHV

[Ville Syrjälä]

On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > 
> > Several nasty i915 regressions affecting CHV slipped through
> > to 4.5 and 4.6.
> > 
> > The first fix we want in 4.5 and 4.6 is
> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> > It won't cherry-pick cleanly to either one, so I've included conflict
> > free versions for both. This one fixes display FIFO underruns that can
> > lead to the screen totally blanking out.
> 
> Now applied, thanks.
> 
> > The other one I'd like to have in 4.6 is
> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> > which avoids a totally corrupted display in some cases.
> 
> Now applied.
> 
> > And the third on is a bit more annoying. The regression is caused by
> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> > which I though we had prevented from getting out on its own, but turns
> > out I was wrong. It basically makes the GPU unusable, so we do need to
> > fix it somehow. The simple solution would be to revert it in 4.6 only.
> > The more complicated solution is to backport the proper fix, which more
> > or less requires the following set of commits [1], which is maybe a bit
> > too much for stable. I could try to trim it a bit perhaps, but then we
> > start to enter the territory of untested code which I don't particularly
> > like. Let me know what you think.
> > 
> > [1]
> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> 
> I think reverting that one patch for 4.6 makes more sense than adding
> all of these patches.  I'll do that if you want me to.

That works for me. Thanks.

-- 
Ville Syrj�l�
Intel OTC

Re: drm/i915 4.5/4.6 stable backport request for CHV

[Ville Syrjälä]

On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Several nasty i915 regressions affecting CHV slipped through
> > to 4.5 and 4.6.
> > 
> > The first fix we want in 4.5 and 4.6 is
> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> > It won't cherry-pick cleanly to either one, so I've included conflict
> > free versions for both. This one fixes display FIFO underruns that can
> > lead to the screen totally blanking out.
> 
> Now applied, thanks.
> 
> > The other one I'd like to have in 4.6 is
> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> > which avoids a totally corrupted display in some cases.
> 
> Now applied.
> 
> > And the third on is a bit more annoying. The regression is caused by
> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> > which I though we had prevented from getting out on its own, but turns
> > out I was wrong. It basically makes the GPU unusable, so we do need to
> > fix it somehow. The simple solution would be to revert it in 4.6 only.
> > The more complicated solution is to backport the proper fix, which more
> > or less requires the following set of commits [1], which is maybe a bit
> > too much for stable. I could try to trim it a bit perhaps, but then we
> > start to enter the territory of untested code which I don't particularly
> > like. Let me know what you think.
> > 
> > [1]
> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> 
> I think reverting that one patch for 4.6 makes more sense than adding
> all of these patches.  I'll do that if you want me to.

That works for me. Thanks.

-- 
Ville Syrjälä
Intel OTC

Re: [Intel-gfx] drm/i915 4.5/4.6 stable backport request for CHV

[Daniel Vetter]

On Mon, Jun 6, 2016 at 11:32 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
>> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Several nasty i915 regressions affecting CHV slipped through
>> > to 4.5 and 4.6.
>> >
>> > The first fix we want in 4.5 and 4.6 is
>> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
>> > It won't cherry-pick cleanly to either one, so I've included conflict
>> > free versions for both. This one fixes display FIFO underruns that can
>> > lead to the screen totally blanking out.
>>
>> Now applied, thanks.
>>
>> > The other one I'd like to have in 4.6 is
>> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
>> > which avoids a totally corrupted display in some cases.
>>
>> Now applied.
>>
>> > And the third on is a bit more annoying. The regression is caused by
>> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
>> > which I though we had prevented from getting out on its own, but turns
>> > out I was wrong. It basically makes the GPU unusable, so we do need to
>> > fix it somehow. The simple solution would be to revert it in 4.6 only.
>> > The more complicated solution is to backport the proper fix, which more
>> > or less requires the following set of commits [1], which is maybe a bit
>> > too much for stable. I could try to trim it a bit perhaps, but then we
>> > start to enter the territory of untested code which I don't particularly
>> > like. Let me know what you think.
>> >
>> > [1]
>> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
>> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
>> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
>> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
>> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
>> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
>> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
>> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
>> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
>> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
>> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
>> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
>> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
>> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
>>
>> I think reverting that one patch for 4.6 makes more sense than adding
>> all of these patches.  I'll do that if you want me to.
>
> That works for me. Thanks.

Has this happened? I just got a ping on irc that braswell in 4.6 is
still entirely toasted :(
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: drm/i915 4.5/4.6 stable backport request for CHV

[Daniel Vetter]

On Mon, Jun 6, 2016 at 11:32 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
>> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Several nasty i915 regressions affecting CHV slipped through
>> > to 4.5 and 4.6.
>> >
>> > The first fix we want in 4.5 and 4.6 is
>> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
>> > It won't cherry-pick cleanly to either one, so I've included conflict
>> > free versions for both. This one fixes display FIFO underruns that can
>> > lead to the screen totally blanking out.
>>
>> Now applied, thanks.
>>
>> > The other one I'd like to have in 4.6 is
>> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
>> > which avoids a totally corrupted display in some cases.
>>
>> Now applied.
>>
>> > And the third on is a bit more annoying. The regression is caused by
>> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
>> > which I though we had prevented from getting out on its own, but turns
>> > out I was wrong. It basically makes the GPU unusable, so we do need to
>> > fix it somehow. The simple solution would be to revert it in 4.6 only.
>> > The more complicated solution is to backport the proper fix, which more
>> > or less requires the following set of commits [1], which is maybe a bit
>> > too much for stable. I could try to trim it a bit perhaps, but then we
>> > start to enter the territory of untested code which I don't particularly
>> > like. Let me know what you think.
>> >
>> > [1]
>> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
>> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
>> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
>> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
>> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
>> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
>> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
>> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
>> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
>> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
>> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
>> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
>> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
>> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
>>
>> I think reverting that one patch for 4.6 makes more sense than adding
>> all of these patches.  I'll do that if you want me to.
>
> That works for me. Thanks.

Has this happened? I just got a ping on irc that braswell in 4.6 is
still entirely toasted :(
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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Re: drm/i915 4.5/4.6 stable backport request for CHV

[Peter Frühberger]

[-- Attachment #1.1: Type: text/plain, Size: 3499 bytes --]

Hi guys,

2016-06-06 11:32 GMT+02:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:

> On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> > On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com
> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Several nasty i915 regressions affecting CHV slipped through
> > > to 4.5 and 4.6.
> > >
> > > The first fix we want in 4.5 and 4.6 is
> > > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> > > It won't cherry-pick cleanly to either one, so I've included conflict
> > > free versions for both. This one fixes display FIFO underruns that can
> > > lead to the screen totally blanking out.
> >
> > Now applied, thanks.
> >
> > > The other one I'd like to have in 4.6 is
> > > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to
> .update_plane()")
> > > which avoids a totally corrupted display in some cases.
> >
> > Now applied.
> >
> > > And the third on is a bit more annoying. The regression is caused by
> > > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after
> one pass")
> > > which I though we had prevented from getting out on its own, but turns
> > > out I was wrong. It basically makes the GPU unusable, so we do need to
> > > fix it somehow. The simple solution would be to revert it in 4.6 only.
> > > The more complicated solution is to backport the proper fix, which more
> > > or less requires the following set of commits [1], which is maybe a bit
> > > too much for stable. I could try to trim it a bit perhaps, but then we
> > > start to enter the territory of untested code which I don't
> particularly
> > > like. Let me know what you think.
> > >
> > > [1]
> > >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> > >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> > >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> > >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> > >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> > >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> > >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to
> vlv_display_irq_reset()")
> > >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh
> display irq postinstall")
> > >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in
> vlv_display_irq_postinstall()")
> > >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when
> turning on the power well")
> > >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more
> logical place")
> > >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs
> aren't flagged as enabled")
> > >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> > >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> >
> > I think reverting that one patch for 4.6 makes more sense than adding
> > all of these patches.  I'll do that if you want me to.
>
> That works for me. Thanks.
>
> --
> Ville Syrjälä
> Intel OTC


Sorry for bothering you. Will the revert make it into 4.6.3? Without it BSW
on 4.6 is not really usable.

Thanks much in advance
Peter



-- 
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==============================================================
Fingerprint: 4606 DA19 EC2E 9A0B 0157  C81B DA07 CF63 1A99 5A9B

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Re: [Intel-gfx] drm/i915 4.5/4.6 stable backport request for CHV

[Greg KH]

On Wed, Jun 22, 2016 at 03:55:03PM +0200, Daniel Vetter wrote:
> On Mon, Jun 6, 2016 at 11:32 AM, Ville Syrj�l�
> <ville.syrjala@linux.intel.com> wrote:
> > On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> >> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> >> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> >> >
> >> > Several nasty i915 regressions affecting CHV slipped through
> >> > to 4.5 and 4.6.
> >> >
> >> > The first fix we want in 4.5 and 4.6 is
> >> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> >> > It won't cherry-pick cleanly to either one, so I've included conflict
> >> > free versions for both. This one fixes display FIFO underruns that can
> >> > lead to the screen totally blanking out.
> >>
> >> Now applied, thanks.
> >>
> >> > The other one I'd like to have in 4.6 is
> >> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> >> > which avoids a totally corrupted display in some cases.
> >>
> >> Now applied.
> >>
> >> > And the third on is a bit more annoying. The regression is caused by
> >> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> >> > which I though we had prevented from getting out on its own, but turns
> >> > out I was wrong. It basically makes the GPU unusable, so we do need to
> >> > fix it somehow. The simple solution would be to revert it in 4.6 only.
> >> > The more complicated solution is to backport the proper fix, which more
> >> > or less requires the following set of commits [1], which is maybe a bit
> >> > too much for stable. I could try to trim it a bit perhaps, but then we
> >> > start to enter the territory of untested code which I don't particularly
> >> > like. Let me know what you think.
> >> >
> >> > [1]
> >> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> >> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> >> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> >> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> >> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> >> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> >> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
> >> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
> >> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
> >> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
> >> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
> >> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
> >> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> >> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> >>
> >> I think reverting that one patch for 4.6 makes more sense than adding
> >> all of these patches.  I'll do that if you want me to.
> >
> > That works for me. Thanks.
> 
> Has this happened? I just got a ping on irc that braswell in 4.6 is
> still entirely toasted :(

Sorry for the delay, revert is now queued up.

greg k-h

Re: drm/i915 4.5/4.6 stable backport request for CHV

[Greg KH]

On Wed, Jun 22, 2016 at 03:55:03PM +0200, Daniel Vetter wrote:
> On Mon, Jun 6, 2016 at 11:32 AM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Sat, Jun 04, 2016 at 02:06:58PM -0700, Greg KH wrote:
> >> On Fri, May 27, 2016 at 11:30:30AM +0300, ville.syrjala@linux.intel.com wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > Several nasty i915 regressions affecting CHV slipped through
> >> > to 4.5 and 4.6.
> >> >
> >> > The first fix we want in 4.5 and 4.6 is
> >> > commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
> >> > It won't cherry-pick cleanly to either one, so I've included conflict
> >> > free versions for both. This one fixes display FIFO underruns that can
> >> > lead to the screen totally blanking out.
> >>
> >> Now applied, thanks.
> >>
> >> > The other one I'd like to have in 4.6 is
> >> > commit 9f6151c90390 ("drm/i915: Pass the correct crtc state to .update_plane()")
> >> > which avoids a totally corrupted display in some cases.
> >>
> >> Now applied.
> >>
> >> > And the third on is a bit more annoying. The regression is caused by
> >> > commit 9dbaab56ac09 ("drm/i915: Exit cherryview_irq_handler() after one pass")
> >> > which I though we had prevented from getting out on its own, but turns
> >> > out I was wrong. It basically makes the GPU unusable, so we do need to
> >> > fix it somehow. The simple solution would be to revert it in 4.6 only.
> >> > The more complicated solution is to backport the proper fix, which more
> >> > or less requires the following set of commits [1], which is maybe a bit
> >> > too much for stable. I could try to trim it a bit perhaps, but then we
> >> > start to enter the territory of untested code which I don't particularly
> >> > like. Let me know what you think.
> >> >
> >> > [1]
> >> >  1e1cace942ef ("drm/i915: Eliminate loop from VLV irq handler")
> >> >  a5e485a95c9c ("drm/i915: Clear VLV_IER around irq processing")
> >> >  4a0a0202b023 ("drm/i915: Clear VLV_MASTER_IER around irq processing")
> >> >  7ce4d1f2730f ("drm/i915: Clear VLV_IIR after PIPESTAT")
> >> >  34c7b8a7b8b5 ("drm/i915: Set up VLV_MASTER_IER consistently")
> >> >  e5328c43d46e ("drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently")
> >> >  71b8b41d5b35 ("drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()")
> >> >  6b7eafc1b43d ("drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall")
> >> >  9ab981f22bef ("drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()")
> >> >  d6c698035892 ("drm/i915: Clear display interrupt before enabling when turning on the power well")
> >> >  8bb613068a63 ("drm/i915: Move vlv/chv display irq code to a more logical place")
> >> >  9918271efc7a ("drm/i915: Skip display irq setup if display irqs aren't flagged as enabled")
> >> >  ad22d10654ea ("drm/i915: Fix up vlv/chv display irq setup")
> >> >  93de68f94081 ("drm/i915: Remove "VLV magic" from irq setup")
> >>
> >> I think reverting that one patch for 4.6 makes more sense than adding
> >> all of these patches.  I'll do that if you want me to.
> >
> > That works for me. Thanks.
> 
> Has this happened? I just got a ping on irc that braswell in 4.6 is
> still entirely toasted :(

Sorry for the delay, revert is now queued up.

greg k-h
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