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From: Paul Burton <paul.burton@imgtec.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
Date: Thu, 9 Jun 2016 13:09:51 +0100	[thread overview]
Message-ID: <20160609120952.4799-1-paul.burton@imgtec.com> (raw)

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

---

 arch/mips/lib/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c0..db81953 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	if (start_addr == stop)
 		return;
 
-	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 }
-- 
2.8.3

             reply	other threads:[~2016-06-09 12:09 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-09 12:09 Paul Burton [this message]
2016-06-09 12:09 ` [U-Boot] [PATCH 2/2] MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex Paul Burton
2016-06-10 10:46   ` Daniel Schwierzeck
2016-06-10 10:42 ` [U-Boot] [PATCH 1/2] MIPS: Fix invalidate_dcache_range to operate on L1 Dcache Daniel Schwierzeck

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