From: Dong Aisheng <dongas86@gmail.com> To: Shawn Guo <shawnguo@kernel.org> Cc: Dong Aisheng <aisheng.dong@nxp.com>, linux-clk@vger.kernel.org, anson.huang@nxp.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Date: Sun, 12 Jun 2016 20:19:47 +0800 [thread overview] Message-ID: <20160612121947.GF32690@shlinux2> (raw) In-Reply-To: <20160612115204.GB32690@shlinux2> On Sun, Jun 12, 2016 at 07:52:04PM +0800, Dong Aisheng wrote: > On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote: > > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote: > > > pllx_bypass_src mux shouldn't be the parent of pllx clock > > > since it's only valid when when pllx BYPASS bit is set. > > > Thus it is actually one parent of pllx_bypass only. > > > > > > Instead, pllx parent should be fixed to osc according to > > > reference manual. > > > Other plls have the same issue. > > > > > > e.g. before fix, the pll tree is: > > > osc 6 6 24000000 0 0 > > > pll1_bypass_src 0 0 24000000 0 0 > > > pll1 0 0 792000000 0 0 > > > pll1_bypass 0 0 792000000 0 0 > > > pll1_sys 0 0 792000000 0 0 > > > > > > After the fix, it's: > > > osc 6 6 24000000 0 0 > > > pll1 0 0 792000000 0 0 > > > pll1_bypass 0 0 792000000 0 0 > > > pll1_sys 0 0 792000000 0 0 > > > > > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > > > I squashed 7 ~ 11 into one patch and applied it, thanks. > > > > I'm fine. > Thanks > You probably may need to change the patch title after merge. clk: imx: fix pll clock parents Regards Dong Aisheng > Regards > Dong Aisheng > > > Shawn > > -- > > To unsubscribe from this list: send the line "unsubscribe linux-clk" in > > the body of a message to majordomo@vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: dongas86@gmail.com (Dong Aisheng) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/11] clk: imx6ul: fix pll clock parents Date: Sun, 12 Jun 2016 20:19:47 +0800 [thread overview] Message-ID: <20160612121947.GF32690@shlinux2> (raw) In-Reply-To: <20160612115204.GB32690@shlinux2> On Sun, Jun 12, 2016 at 07:52:04PM +0800, Dong Aisheng wrote: > On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote: > > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote: > > > pllx_bypass_src mux shouldn't be the parent of pllx clock > > > since it's only valid when when pllx BYPASS bit is set. > > > Thus it is actually one parent of pllx_bypass only. > > > > > > Instead, pllx parent should be fixed to osc according to > > > reference manual. > > > Other plls have the same issue. > > > > > > e.g. before fix, the pll tree is: > > > osc 6 6 24000000 0 0 > > > pll1_bypass_src 0 0 24000000 0 0 > > > pll1 0 0 792000000 0 0 > > > pll1_bypass 0 0 792000000 0 0 > > > pll1_sys 0 0 792000000 0 0 > > > > > > After the fix, it's: > > > osc 6 6 24000000 0 0 > > > pll1 0 0 792000000 0 0 > > > pll1_bypass 0 0 792000000 0 0 > > > pll1_sys 0 0 792000000 0 0 > > > > > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > > > I squashed 7 ~ 11 into one patch and applied it, thanks. > > > > I'm fine. > Thanks > You probably may need to change the patch title after merge. clk: imx: fix pll clock parents Regards Dong Aisheng > Regards > Dong Aisheng > > > Shawn > > -- > > To unsubscribe from this list: send the line "unsubscribe linux-clk" in > > the body of a message to majordomo at vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2016-06-12 12:25 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-08 14:33 [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 02/11] clk: imx: correct AV PLL rate formula Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:30 ` Shawn Guo 2016-06-12 11:30 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 03/11] clk: imx7d: correct dram root clk parent select Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:31 ` Shawn Guo 2016-06-12 11:31 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 04/11] clk: imx: correct dram pll type Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:33 ` Shawn Guo 2016-06-12 11:33 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-09 7:43 ` Lothar Waßmann 2016-06-09 7:43 ` Lothar Waßmann 2016-06-09 7:43 ` Lothar Waßmann 2016-06-12 11:56 ` Dong Aisheng 2016-06-12 11:56 ` Dong Aisheng 2016-06-12 11:36 ` Shawn Guo 2016-06-12 11:36 ` Shawn Guo 2016-06-12 11:51 ` Dong Aisheng 2016-06-12 11:51 ` Dong Aisheng 2016-06-12 12:13 ` Dong Aisheng 2016-06-12 12:13 ` Dong Aisheng 2016-06-12 13:29 ` Shawn Guo 2016-06-12 13:29 ` Shawn Guo 2016-06-12 14:51 ` Dong Aisheng 2016-06-12 14:51 ` Dong Aisheng 2016-06-12 14:51 ` Dong Aisheng 2016-06-13 7:37 ` [PATCH V2 1/1] clk: imx: refine the powerdown " Dong Aisheng 2016-06-13 7:37 ` Dong Aisheng 2016-06-13 11:42 ` kbuild test robot 2016-06-13 11:42 ` kbuild test robot 2016-06-13 12:24 ` [PATCH V3 " Dong Aisheng 2016-06-13 12:24 ` Dong Aisheng 2016-06-16 1:05 ` Shawn Guo 2016-06-16 1:05 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 06/11] clk: imx6ul: fix gpt2 clock names Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:41 ` Shawn Guo 2016-06-12 11:41 ` Shawn Guo 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 11:52 ` Dong Aisheng 2016-06-13 7:38 ` [PATCH V2 1/1] " Dong Aisheng 2016-06-13 7:38 ` Dong Aisheng 2016-06-16 1:06 ` Shawn Guo 2016-06-16 1:06 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:43 ` Shawn Guo 2016-06-12 11:43 ` Shawn Guo 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 12:19 ` Dong Aisheng [this message] 2016-06-12 12:19 ` Dong Aisheng 2016-06-12 13:22 ` Shawn Guo 2016-06-12 13:22 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 08/11] clk: imx6q: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 09/11] clk: imx6sx: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 10/11] clk: imx6sl: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 11/11] clk: imx7d: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 14:56 ` [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng 2016-06-12 14:56 ` Dong Aisheng 2016-06-12 14:56 ` Dong Aisheng 2016-06-13 2:54 ` Shawn Guo 2016-06-13 2:54 ` Shawn Guo 2016-06-13 2:54 ` Shawn Guo
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